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| author | Alex Deucher <alexander.deucher@amd.com> | 2013-09-06 15:58:56 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-09-06 15:58:56 -0400 |
| commit | 58d008883165ba35c83041fa9ed84937163d5f76 (patch) | |
| tree | 9c77d3d3484009b78a91d3e549db1a136113e130 /intel/tests/gen6-3d.batch-ref.txt | |
| parent | 8a2e0fa917996e72bfc0dbdf228fc0bfb433d279 (diff) | |
radeon: pad CS to 8 DW
Aligns the IB to 8 DWs. The aligns the IB to the
CP fetch size. r6xx also require at least 4 DW
alignment to avoid a hw bug.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'intel/tests/gen6-3d.batch-ref.txt')
0 files changed, 0 insertions, 0 deletions