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authorChris Wilson <chris@chris-wilson.co.uk>2012-02-09 10:29:22 +0000
committerChris Wilson <chris@chris-wilson.co.uk>2012-02-15 11:16:59 +0000
commit23eeb7e1e45417a5a84f826286dd982dba440cd3 (patch)
treefa744258a4354cc23f45b32beb652fe863d1b238 /include/drm
parent9b3ad51ae5fd9654df8ef75de845a519015150bb (diff)
intel: Detect cache domain inconsistency with valgrind
Every access to either the GTT or CPU pointer is supposed to be proceeded by a set_domain ioctl so that GEM is able to manage the cache domains correctly and for the following access to be coherent. Of course, some people explicitly want incoherent, non-blocking access which is going to trigger warnings by this patch but are probably better served by explicit suppression. v2: Also mark the pointers as inaccessible following the explicit unmap and implicit unmap upon return to the cache. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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