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| author | Marek Olšák <marek.olsak@amd.com> | 2013-11-22 23:31:13 +0100 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2013-11-23 00:35:39 +0100 |
| commit | 67d92404d62044972599dcef3011d17fca46eed5 (patch) | |
| tree | eab74c852d5271e5caaf26257505c68352428eb3 /include/drm/radeon_drm.h | |
| parent | ce8af454259279c14c44bcd32c429640ca5e1691 (diff) | |
radeon: implement 2D tiling for CIK
Bug fixes and simplification by Marek.
We have to use the tile index of 0 for non-MSAA depth-stencil after all.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'include/drm/radeon_drm.h')
| -rw-r--r-- | include/drm/radeon_drm.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h index d1bebf5a..96ea5559 100644 --- a/include/drm/radeon_drm.h +++ b/include/drm/radeon_drm.h @@ -979,6 +979,10 @@ struct drm_radeon_cs { #define RADEON_INFO_RING_WORKING 0x15 /* SI tile mode array */ #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 +/* query if CP DMA is supported on the compute ring */ +#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 +/* CIK macrotile mode array */ +#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 struct drm_radeon_info { uint32_t request; @@ -1004,6 +1008,13 @@ struct drm_radeon_info { #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 +#define CIK_TILE_MODE_COLOR_2D 14 +#define CIK_TILE_MODE_COLOR_2D_SCANOUT 10 +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_64 0 +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_128 1 +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_256 2 +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_512 3 +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_ROW_SIZE 4 #define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 #endif |