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| author | Matthieu Castet <castet.matthieu@free.fr> | 2007-08-08 22:55:32 +0200 |
|---|---|---|
| committer | Matthieu Castet <castet.matthieu@free.fr> | 2007-08-08 22:55:32 +0200 |
| commit | e326acf5493a7193954d3dd794855e2a11dc1782 (patch) | |
| tree | 34007c628dc829201f9b304ee1d342eaca65b0f2 | |
| parent | 05633ca3708f48cfbbb77518da4e791d7e1613c2 (diff) | |
nouveau : nv10, nv20, nv30 : don't save all channel in the same RAMFC entry
This should improve multi fifo
| -rw-r--r-- | shared-core/nv10_fifo.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c index 47af0ff0..a056460d 100644 --- a/shared-core/nv10_fifo.c +++ b/shared-core/nv10_fifo.c @@ -33,7 +33,7 @@ NV10_RAMFC_##offset/4, (val)) #define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \ NV10_RAMFC_##offset/4) -#define NV10_RAMFC(c) (dev_priv->ramfc_offset + NV10_RAMFC__SIZE) +#define NV10_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV10_RAMFC__SIZE)) #define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32) int |