diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2013-03-01 15:37:01 -0800 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2013-03-28 13:24:15 -0700 |
| commit | ca678bc073462623cfc89dea80271bc361f1655f (patch) | |
| tree | 697909ec62a16e88a376756cca32403d7adf00d5 | |
| parent | 1eb2860b4bd0306dddc5b2f2dc7403aa65c5e476 (diff) | |
intel: Fix Haswell CRW PCI IDs.
The second digit was off by one, which meant we accidentally treated
GT(n) as GT(n-1). This also meant no support for GT1 at all.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
| -rw-r--r-- | intel/intel_chipset.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 2760dc8c..5aea3f2b 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -115,15 +115,15 @@ #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A -#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */ -#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22 -#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32 -#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */ -#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 -#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 -#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */ -#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A -#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A +#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ +#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 +#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22 +#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */ +#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 +#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26 +#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ +#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A +#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */ #define PCI_CHIP_VALLEYVIEW_1 0x0f31 |