nouveau: Pass channel struct around instead of channel id.

16 files changed, 516 insertions, 521 deletions

diff --git a/linux-core/nouveau_sgdma.c b/linux-core/nouveau_sgdma.c
index 0ddac952..6393a469 100644
--- a/linux-core/nouveau_sgdma.c
+++ b/linux-core/nouveau_sgdma.c
@@ -211,7 +211,7 @@ nouveau_sgdma_init(struct drm_device *dev)
 		obj_size  = (aper_size >> NV_CTXDMA_PAGE_SHIFT) * 8;
 	}
 
-	if ((ret = nouveau_gpuobj_new(dev, -1, obj_size, 16,
+	if ((ret = nouveau_gpuobj_new(dev, NULL, obj_size, 16,
 				      NVOBJ_FLAG_ALLOW_NO_REFS |
 				      NVOBJ_FLAG_ZERO_ALLOC |
 				      NVOBJ_FLAG_ZERO_FREE, &gpuobj)))  {
diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h
index dd323a0b..8ec91898 100644
--- a/shared-core/nouveau_drv.h
+++ b/shared-core/nouveau_drv.h
@@ -92,8 +92,11 @@ struct nouveau_gpuobj_ref {
 	int handle;
 };
 
-struct nouveau_fifo
+struct nouveau_channel
 {
+	struct drm_device *dev;
+	int id;
+
 	/* owner of this fifo */
 	struct drm_file *file_priv;
 	/* mapping of the fifo itself */
@@ -136,57 +139,64 @@ struct nouveau_config {
 	} cmdbuf;
 };
 
-struct nouveau_engine_func {
-	struct {
-		void	*priv;
+struct nouveau_instmem_engine {
+	void	*priv;
 
-		int	(*init)(struct drm_device *dev);
-		void	(*takedown)(struct drm_device *dev);
+	int	(*init)(struct drm_device *dev);
+	void	(*takedown)(struct drm_device *dev);
 
-		int	(*populate)(struct drm_device *, struct nouveau_gpuobj *,
-				    uint32_t *size);
-		void	(*clear)(struct drm_device *, struct nouveau_gpuobj *);
-		int	(*bind)(struct drm_device *, struct nouveau_gpuobj *);
-		int	(*unbind)(struct drm_device *, struct nouveau_gpuobj *);
-	} instmem;
+	int	(*populate)(struct drm_device *, struct nouveau_gpuobj *,
+			    uint32_t *size);
+	void	(*clear)(struct drm_device *, struct nouveau_gpuobj *);
+	int	(*bind)(struct drm_device *, struct nouveau_gpuobj *);
+	int	(*unbind)(struct drm_device *, struct nouveau_gpuobj *);
+};
 
-	struct {
-		int	(*init)(struct drm_device *dev);
-		void	(*takedown)(struct drm_device *dev);
-	} mc;
+struct nouveau_mc_engine {
+	int  (*init)(struct drm_device *dev);
+	void (*takedown)(struct drm_device *dev);
+};
 
-	struct {
-		int	(*init)(struct drm_device *dev);
-		uint64_t (*read)(struct drm_device *dev);
-		void	(*takedown)(struct drm_device *dev);
-	} timer;
+struct nouveau_timer_engine {
+	int      (*init)(struct drm_device *dev);
+	void     (*takedown)(struct drm_device *dev);
+	uint64_t (*read)(struct drm_device *dev);
+};
 
-	struct {
-		int	(*init)(struct drm_device *dev);
-		void	(*takedown)(struct drm_device *dev);
-	} fb;
+struct nouveau_fb_engine {
+	int  (*init)(struct drm_device *dev);
+	void (*takedown)(struct drm_device *dev);
+};
 
-	struct {
-		int	(*init)(struct drm_device *);
-		void	(*takedown)(struct drm_device *);
+struct nouveau_fifo_engine {
+	void *priv;
 
-		int	(*create_context)(struct drm_device *, int channel);
-		void	(*destroy_context)(struct drm_device *, int channel);
-		int	(*load_context)(struct drm_device *, int channel);
-		int	(*save_context)(struct drm_device *, int channel);
-	} graph;
+	int  (*init)(struct drm_device *);
+	void (*takedown)(struct drm_device *);
 
-	struct {
-		void	*priv;
+	int  (*create_context)(struct nouveau_channel *);
+	void (*destroy_context)(struct nouveau_channel *);
+	int  (*load_context)(struct nouveau_channel *);
+	int  (*save_context)(struct nouveau_channel *);
+};
 
-		int	(*init)(struct drm_device *);
-		void	(*takedown)(struct drm_device *);
+struct nouveau_pgraph_engine {
+	int  (*init)(struct drm_device *);
+	void (*takedown)(struct drm_device *);
 
-		int	(*create_context)(struct drm_device *, int channel);
-		void	(*destroy_context)(struct drm_device *, int channel);
-		int	(*load_context)(struct drm_device *, int channel);
-		int	(*save_context)(struct drm_device *, int channel);
-	} fifo;
+	int  (*create_context)(struct nouveau_channel *);
+	void (*destroy_context)(struct nouveau_channel *);
+	int  (*load_context)(struct nouveau_channel *);
+	int  (*save_context)(struct nouveau_channel *);
+};
+
+struct nouveau_engine {
+	struct nouveau_instmem_engine instmem;
+	struct nouveau_mc_engine      mc;
+	struct nouveau_timer_engine   timer;
+	struct nouveau_fb_engine      fb;
+	struct nouveau_pgraph_engine  graph;
+	struct nouveau_fifo_engine    fifo;
 };
 
 struct drm_nouveau_private {
@@ -207,9 +217,9 @@ struct drm_nouveau_private {
 	drm_local_map_t *ramin; /* NV40 onwards */
 
 	int fifo_alloc_count;
-	struct nouveau_fifo *fifos[NV_MAX_FIFO_NUMBER];
+	struct nouveau_channel *fifos[NV_MAX_FIFO_NUMBER];
 
-	struct nouveau_engine_func Engine;
+	struct nouveau_engine Engine;
 
 	/* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
 	struct nouveau_gpuobj *ramht;
@@ -262,93 +272,108 @@ struct drm_nouveau_private {
 	struct nouveau_gpuobj *gpuobj_all;
 };
 
+#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id,cl,ch) do {  \
+	struct drm_nouveau_private *nv = dev->dev_private;   \
+	if (!nouveau_fifo_owner(dev, (cl), (id))) {          \
+		DRM_ERROR("pid %d doesn't own channel %d\n", \
+			  DRM_CURRENTPID, (id));             \
+		return -EPERM;                               \
+	}                                                    \
+	(ch) = nv->fifos[(id)];                              \
+} while(0)
+
 /* nouveau_state.c */
-extern void nouveau_preclose(struct drm_device * dev,
-			     struct drm_file *file_priv);
-extern int nouveau_load(struct drm_device *dev, unsigned long flags);
-extern int nouveau_firstopen(struct drm_device *dev);
-extern void nouveau_lastclose(struct drm_device *dev);
-extern int nouveau_unload(struct drm_device *dev);
-extern int nouveau_ioctl_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv);
-extern int nouveau_ioctl_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv);
-extern void nouveau_wait_for_idle(struct drm_device *dev);
-extern int nouveau_ioctl_card_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
+extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
+extern int  nouveau_load(struct drm_device *, unsigned long flags);
+extern int  nouveau_firstopen(struct drm_device *);
+extern void nouveau_lastclose(struct drm_device *);
+extern int  nouveau_unload(struct drm_device *);
+extern int  nouveau_ioctl_getparam(struct drm_device *, void *data,
+				   struct drm_file *);
+extern int  nouveau_ioctl_setparam(struct drm_device *, void *data,
+				   struct drm_file *);
+extern void nouveau_wait_for_idle(struct drm_device *);
+extern int  nouveau_ioctl_card_init(struct drm_device *, void *data,
+				    struct drm_file *);
 
 /* nouveau_mem.c */
-extern int               nouveau_mem_init_heap(struct mem_block **,
-					       uint64_t start, uint64_t size);
+extern int  nouveau_mem_init_heap(struct mem_block **, uint64_t start,
+				 uint64_t size);
 extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
 						 uint64_t size, int align2,
-						 struct drm_file *file_priv);
-extern void              nouveau_mem_takedown(struct mem_block **heap);
-extern void              nouveau_mem_free_block(struct mem_block *);
-extern uint64_t          nouveau_mem_fb_amount(struct drm_device *dev);
-extern void              nouveau_mem_release(struct drm_file *file_priv,
-					     struct mem_block *heap);
-extern int               nouveau_ioctl_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
-extern int               nouveau_ioctl_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
-extern struct mem_block* nouveau_mem_alloc(struct drm_device *dev,
+						 struct drm_file *);
+extern void nouveau_mem_takedown(struct mem_block **heap);
+extern void nouveau_mem_free_block(struct mem_block *);
+extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
+extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
+extern int  nouveau_ioctl_mem_alloc(struct drm_device *, void *data,
+				    struct drm_file *);
+extern int  nouveau_ioctl_mem_free(struct drm_device *, void *data,
+				   struct drm_file *);
+extern struct mem_block* nouveau_mem_alloc(struct drm_device *,
 					   int alignment, uint64_t size,
-					   int flags,
-					   struct drm_file *file_priv);
-extern void              nouveau_mem_free(struct drm_device* dev, struct mem_block*);
-extern int               nouveau_mem_init(struct drm_device *dev);
-extern void              nouveau_mem_close(struct drm_device *dev);
+					   int flags, struct drm_file *);
+extern void nouveau_mem_free(struct drm_device *dev, struct mem_block*);
+extern int  nouveau_mem_init(struct drm_device *);
+extern void nouveau_mem_close(struct drm_device *);
 
 /* nouveau_notifier.c */
-extern int  nouveau_notifier_init_channel(struct drm_device *, int channel,
-					  struct drm_file *file_priv);
-extern void nouveau_notifier_takedown_channel(struct drm_device *, int channel);
-extern int  nouveau_notifier_alloc(struct drm_device *, int channel,
-				   uint32_t handle, int cout, uint32_t *offset);
-extern int  nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
+extern int  nouveau_notifier_init_channel(struct nouveau_channel *);
+extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
+extern int  nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
+				   int cout, uint32_t *offset);
+extern int  nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
+					 struct drm_file *);
 
 /* nouveau_fifo.c */
-extern int  nouveau_fifo_init(struct drm_device *dev);
-extern int  nouveau_fifo_number(struct drm_device *dev);
-extern int  nouveau_fifo_ctx_size(struct drm_device *dev);
-extern void nouveau_fifo_cleanup(struct drm_device *dev,
-				 struct drm_file *file_priv);
-extern int  nouveau_fifo_owner(struct drm_device *dev,
-			       struct drm_file *file_priv, int channel);
-extern void nouveau_fifo_free(struct drm_device *dev, int channel);
+extern int  nouveau_fifo_init(struct drm_device *);
+extern int  nouveau_fifo_number(struct drm_device *);
+extern int  nouveau_fifo_ctx_size(struct drm_device *);
+extern void nouveau_fifo_cleanup(struct drm_device *, struct drm_file *);
+extern int  nouveau_fifo_owner(struct drm_device *, struct drm_file *,
+			       int channel);
+extern void nouveau_fifo_free(struct nouveau_channel *);
 
 /* nouveau_object.c */
-extern void nouveau_gpuobj_takedown(struct drm_device *dev);
-extern int nouveau_gpuobj_channel_init(struct drm_device *, int channel,
+extern void nouveau_gpuobj_takedown(struct drm_device *);
+extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
 				       uint32_t vram_h, uint32_t tt_h);
-extern void nouveau_gpuobj_channel_takedown(struct drm_device *, int channel);
-extern int nouveau_gpuobj_new(struct drm_device *, int channel, int size, int align,
-			      uint32_t flags, struct nouveau_gpuobj **);
+extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
+extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
+			      int size, int align, uint32_t flags,
+			      struct nouveau_gpuobj **);
 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
-extern int nouveau_gpuobj_ref_add(struct drm_device *, int channel, uint32_t handle,
-				  struct nouveau_gpuobj *,
+extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
+				  uint32_t handle, struct nouveau_gpuobj *,
+				  struct nouveau_gpuobj_ref **);
+extern int nouveau_gpuobj_ref_del(struct drm_device *,
 				  struct nouveau_gpuobj_ref **);
-extern int nouveau_gpuobj_ref_del(struct drm_device *, struct nouveau_gpuobj_ref **);
-extern int nouveau_gpuobj_new_ref(struct drm_device *, int chan_obj, int chan_ref,
+extern int nouveau_gpuobj_new_ref(struct drm_device *,
+				  struct nouveau_channel *alloc_chan,
+				  struct nouveau_channel *ref_chan,
 				  uint32_t handle, int size, int align,
 				  uint32_t flags, struct nouveau_gpuobj_ref **);
 extern int nouveau_gpuobj_new_fake(struct drm_device *, uint32_t offset,
 				   uint32_t size, uint32_t flags,
-				   struct nouveau_gpuobj**,
+				   struct nouveau_gpuobj **,
 				   struct nouveau_gpuobj_ref**);
-extern int nouveau_gpuobj_dma_new(struct drm_device *, int channel, int class,
-				  uint64_t offset, uint64_t size,
-				  int access, int target,
-				  struct nouveau_gpuobj **);
-extern int nouveau_gpuobj_gart_dma_new(struct drm_device *, int channel,
+extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
+				  uint64_t offset, uint64_t size, int access,
+				  int target, struct nouveau_gpuobj **);
+extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
 				       uint64_t offset, uint64_t size,
 				       int access, struct nouveau_gpuobj **,
 				       uint32_t *o_ret);
-extern int nouveau_gpuobj_gr_new(struct drm_device *, int channel, int class,
+extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
 				 struct nouveau_gpuobj **);
-extern int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
+extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
+				     struct drm_file *);
 
 /* nouveau_irq.c */
 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
-extern void        nouveau_irq_preinstall(struct drm_device*);
-extern void        nouveau_irq_postinstall(struct drm_device*);
-extern void        nouveau_irq_uninstall(struct drm_device*);
+extern void        nouveau_irq_preinstall(struct drm_device *);
+extern void        nouveau_irq_postinstall(struct drm_device *);
+extern void        nouveau_irq_uninstall(struct drm_device *);
 
 /* nouveau_sgdma.c */
 extern int nouveau_sgdma_init(struct drm_device *);
@@ -358,131 +383,131 @@ extern int nouveau_sgdma_nottm_hack_init(struct drm_device *);
 extern void nouveau_sgdma_nottm_hack_takedown(struct drm_device *);
 
 /* nv04_fb.c */
-extern int  nv04_fb_init(struct drm_device *dev);
-extern void nv04_fb_takedown(struct drm_device *dev);
+extern int  nv04_fb_init(struct drm_device *);
+extern void nv04_fb_takedown(struct drm_device *);
 
 /* nv10_fb.c */
-extern int  nv10_fb_init(struct drm_device *dev);
-extern void nv10_fb_takedown(struct drm_device *dev);
+extern int  nv10_fb_init(struct drm_device *);
+extern void nv10_fb_takedown(struct drm_device *);
 
 /* nv40_fb.c */
-extern int  nv40_fb_init(struct drm_device *dev);
-extern void nv40_fb_takedown(struct drm_device *dev);
+extern int  nv40_fb_init(struct drm_device *);
+extern void nv40_fb_takedown(struct drm_device *);
 
 /* nv04_fifo.c */
-extern int  nv04_fifo_create_context(struct drm_device *dev, int channel);
-extern void nv04_fifo_destroy_context(struct drm_device *dev, int channel);
-extern int  nv04_fifo_load_context(struct drm_device *dev, int channel);
-extern int  nv04_fifo_save_context(struct drm_device *dev, int channel);
+extern int  nv04_fifo_create_context(struct nouveau_channel *);
+extern void nv04_fifo_destroy_context(struct nouveau_channel *);
+extern int  nv04_fifo_load_context(struct nouveau_channel *);
+extern int  nv04_fifo_save_context(struct nouveau_channel *);
 
 /* nv10_fifo.c */
-extern int  nv10_fifo_create_context(struct drm_device *dev, int channel);
-extern void nv10_fifo_destroy_context(struct drm_device *dev, int channel);
-extern int  nv10_fifo_load_context(struct drm_device *dev, int channel);
-extern int  nv10_fifo_save_context(struct drm_device *dev, int channel);
+extern int  nv10_fifo_create_context(struct nouveau_channel *);
+extern void nv10_fifo_destroy_context(struct nouveau_channel *);
+extern int  nv10_fifo_load_context(struct nouveau_channel *);
+extern int  nv10_fifo_save_context(struct nouveau_channel *);
 
 /* nv40_fifo.c */
-extern int  nv40_fifo_create_context(struct drm_device *, int channel);
-extern void nv40_fifo_destroy_context(struct drm_device *, int channel);
-extern int  nv40_fifo_load_context(struct drm_device *, int channel);
-extern int  nv40_fifo_save_context(struct drm_device *, int channel);
+extern int  nv40_fifo_create_context(struct nouveau_channel *);
+extern void nv40_fifo_destroy_context(struct nouveau_channel *);
+extern int  nv40_fifo_load_context(struct nouveau_channel *);
+extern int  nv40_fifo_save_context(struct nouveau_channel *);
 
 /* nv50_fifo.c */
 extern int  nv50_fifo_init(struct drm_device *);
 extern void nv50_fifo_takedown(struct drm_device *);
-extern int  nv50_fifo_create_context(struct drm_device *, int channel);
-extern void nv50_fifo_destroy_context(struct drm_device *, int channel);
-extern int  nv50_fifo_load_context(struct drm_device *, int channel);
-extern int  nv50_fifo_save_context(struct drm_device *, int channel);
+extern int  nv50_fifo_create_context(struct nouveau_channel *);
+extern void nv50_fifo_destroy_context(struct nouveau_channel *);
+extern int  nv50_fifo_load_context(struct nouveau_channel *);
+extern int  nv50_fifo_save_context(struct nouveau_channel *);
 
 /* nv04_graph.c */
-extern void nouveau_nv04_context_switch(struct drm_device *dev);
-extern int  nv04_graph_init(struct drm_device *dev);
-extern void nv04_graph_takedown(struct drm_device *dev);
-extern int  nv04_graph_create_context(struct drm_device *dev, int channel);
-extern void nv04_graph_destroy_context(struct drm_device *dev, int channel);
-extern int  nv04_graph_load_context(struct drm_device *dev, int channel);
-extern int  nv04_graph_save_context(struct drm_device *dev, int channel);
+extern void nouveau_nv04_context_switch(struct drm_device *);
+extern int  nv04_graph_init(struct drm_device *);
+extern void nv04_graph_takedown(struct drm_device *);
+extern int  nv04_graph_create_context(struct nouveau_channel *);
+extern void nv04_graph_destroy_context(struct nouveau_channel *);
+extern int  nv04_graph_load_context(struct nouveau_channel *);
+extern int  nv04_graph_save_context(struct nouveau_channel *);
 
 /* nv10_graph.c */
-extern void nouveau_nv10_context_switch(struct drm_device *dev);
-extern int  nv10_graph_init(struct drm_device *dev);
-extern void nv10_graph_takedown(struct drm_device *dev);
-extern int  nv10_graph_create_context(struct drm_device *dev, int channel);
-extern void nv10_graph_destroy_context(struct drm_device *dev, int channel);
-extern int  nv10_graph_load_context(struct drm_device *dev, int channel);
-extern int  nv10_graph_save_context(struct drm_device *dev, int channel);
+extern void nouveau_nv10_context_switch(struct drm_device *);
+extern int  nv10_graph_init(struct drm_device *);
+extern void nv10_graph_takedown(struct drm_device *);
+extern int  nv10_graph_create_context(struct nouveau_channel *);
+extern void nv10_graph_destroy_context(struct nouveau_channel *);
+extern int  nv10_graph_load_context(struct nouveau_channel *);
+extern int  nv10_graph_save_context(struct nouveau_channel *);
 
 /* nv20_graph.c */
-extern void nouveau_nv20_context_switch(struct drm_device *dev);
-extern int  nv20_graph_init(struct drm_device *dev);
-extern void nv20_graph_takedown(struct drm_device *dev);
-extern int  nv20_graph_create_context(struct drm_device *dev, int channel);
-extern void nv20_graph_destroy_context(struct drm_device *dev, int channel);
-extern int  nv20_graph_load_context(struct drm_device *dev, int channel);
-extern int  nv20_graph_save_context(struct drm_device *dev, int channel);
+extern void nouveau_nv20_context_switch(struct drm_device *);
+extern int  nv20_graph_init(struct drm_device *);
+extern void nv20_graph_takedown(struct drm_device *);
+extern int  nv20_graph_create_context(struct nouveau_channel *);
+extern void nv20_graph_destroy_context(struct nouveau_channel *);
+extern int  nv20_graph_load_context(struct nouveau_channel *);
+extern int  nv20_graph_save_context(struct nouveau_channel *);
 
 /* nv30_graph.c */
-extern int  nv30_graph_init(struct drm_device *dev);
-extern void nv30_graph_takedown(struct drm_device *dev);
-extern int  nv30_graph_create_context(struct drm_device *, int channel);
-extern void nv30_graph_destroy_context(struct drm_device *, int channel);
-extern int  nv30_graph_load_context(struct drm_device *, int channel);
-extern int  nv30_graph_save_context(struct drm_device *, int channel);
+extern int  nv30_graph_init(struct drm_device *);
+extern void nv30_graph_takedown(struct drm_device *);
+extern int  nv30_graph_create_context(struct nouveau_channel *);
+extern void nv30_graph_destroy_context(struct nouveau_channel *);
+extern int  nv30_graph_load_context(struct nouveau_channel *);
+extern int  nv30_graph_save_context(struct nouveau_channel *);
 
 /* nv40_graph.c */
 extern int  nv40_graph_init(struct drm_device *);
 extern void nv40_graph_takedown(struct drm_device *);
-extern int  nv40_graph_create_context(struct drm_device *, int channel);
-extern void nv40_graph_destroy_context(struct drm_device *, int channel);
-extern int  nv40_graph_load_context(struct drm_device *, int channel);
-extern int  nv40_graph_save_context(struct drm_device *, int channel);
+extern int  nv40_graph_create_context(struct nouveau_channel *);
+extern void nv40_graph_destroy_context(struct nouveau_channel *);
+extern int  nv40_graph_load_context(struct nouveau_channel *);
+extern int  nv40_graph_save_context(struct nouveau_channel *);
 
 /* nv50_graph.c */
 extern int  nv50_graph_init(struct drm_device *);
 extern void nv50_graph_takedown(struct drm_device *);
-extern int  nv50_graph_create_context(struct drm_device *, int channel);
-extern void nv50_graph_destroy_context(struct drm_device *, int channel);
-extern int  nv50_graph_load_context(struct drm_device *, int channel);
-extern int  nv50_graph_save_context(struct drm_device *, int channel);
+extern int  nv50_graph_create_context(struct nouveau_channel *);
+extern void nv50_graph_destroy_context(struct nouveau_channel *);
+extern int  nv50_graph_load_context(struct nouveau_channel *);
+extern int  nv50_graph_save_context(struct nouveau_channel *);
 
 /* nv04_instmem.c */
-extern int  nv04_instmem_init(struct drm_device *dev);
-extern void nv04_instmem_takedown(struct drm_device *dev);
-extern int  nv04_instmem_populate(struct drm_device*, struct nouveau_gpuobj*,
+extern int  nv04_instmem_init(struct drm_device *);
+extern void nv04_instmem_takedown(struct drm_device *);
+extern int  nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
 				  uint32_t *size);
-extern void nv04_instmem_clear(struct drm_device*, struct nouveau_gpuobj*);
-extern int  nv04_instmem_bind(struct drm_device*, struct nouveau_gpuobj*);
-extern int  nv04_instmem_unbind(struct drm_device*, struct nouveau_gpuobj*);
+extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
+extern int  nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
+extern int  nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
 
 /* nv50_instmem.c */
-extern int  nv50_instmem_init(struct drm_device *dev);
-extern void nv50_instmem_takedown(struct drm_device *dev);
-extern int  nv50_instmem_populate(struct drm_device*, struct nouveau_gpuobj*,
+extern int  nv50_instmem_init(struct drm_device *);
+extern void nv50_instmem_takedown(struct drm_device *);
+extern int  nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
 				  uint32_t *size);
-extern void nv50_instmem_clear(struct drm_device*, struct nouveau_gpuobj*);
-extern int  nv50_instmem_bind(struct drm_device*, struct nouveau_gpuobj*);
-extern int  nv50_instmem_unbind(struct drm_device*, struct nouveau_gpuobj*);
+extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
+extern int  nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
+extern int  nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
 
 /* nv04_mc.c */
-extern int  nv04_mc_init(struct drm_device *dev);
-extern void nv04_mc_takedown(struct drm_device *dev);
+extern int  nv04_mc_init(struct drm_device *);
+extern void nv04_mc_takedown(struct drm_device *);
 
 /* nv40_mc.c */
-extern int  nv40_mc_init(struct drm_device *dev);
-extern void nv40_mc_takedown(struct drm_device *dev);
+extern int  nv40_mc_init(struct drm_device *);
+extern void nv40_mc_takedown(struct drm_device *);
 
 /* nv50_mc.c */
-extern int  nv50_mc_init(struct drm_device *dev);
-extern void nv50_mc_takedown(struct drm_device *dev);
+extern int  nv50_mc_init(struct drm_device *);
+extern void nv50_mc_takedown(struct drm_device *);
 
 /* nv04_timer.c */
-extern int  nv04_timer_init(struct drm_device *dev);
-extern uint64_t nv04_timer_read(struct drm_device *dev);
-extern void nv04_timer_takedown(struct drm_device *dev);
+extern int  nv04_timer_init(struct drm_device *);
+extern uint64_t nv04_timer_read(struct drm_device *);
+extern void nv04_timer_takedown(struct drm_device *);
 
 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
-				unsigned long arg);
+				 unsigned long arg);
 
 #if defined(__powerpc__)
 #define NV_READ(reg)        in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) )
diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c
index e5d3ab3c..c7ce1d8d 100644
--- a/shared-core/nouveau_fifo.c
+++ b/shared-core/nouveau_fifo.c
@@ -186,10 +186,10 @@ int nouveau_fifo_init(struct drm_device *dev)
 }
 
 static int
-nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel)
+nouveau_fifo_cmdbuf_alloc(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	struct nouveau_config *config = &dev_priv->config;
 	struct mem_block *cb;
 	int cb_min_size = max(NV03_FIFO_SIZE,PAGE_SIZE);
@@ -211,37 +211,34 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel)
 	}
 
 	if (cb->flags & NOUVEAU_MEM_AGP) {
-		ret = nouveau_gpuobj_gart_dma_new(dev, channel,
-						  cb->start, cb->size,
+		ret = nouveau_gpuobj_gart_dma_new(chan, cb->start, cb->size,
 						  NV_DMA_ACCESS_RO,
 						  &pushbuf,
 						  &chan->pushbuf_base);
 	} else
 	if (cb->flags & NOUVEAU_MEM_PCI) {
-		ret = nouveau_gpuobj_dma_new(dev, channel,
-					     NV_CLASS_DMA_IN_MEMORY,
+		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
 					     cb->start, cb->size,
 					     NV_DMA_ACCESS_RO,
 					     NV_DMA_TARGET_PCI_NONLINEAR,
 					     &pushbuf);
 		chan->pushbuf_base = 0;
 	} else if (dev_priv->card_type != NV_04) {
-		ret = nouveau_gpuobj_dma_new
-			(dev, channel, NV_CLASS_DMA_IN_MEMORY,
-			 cb->start,
-			 cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM,
-			 &pushbuf);
+		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
+					     cb->start, cb->size,
+					     NV_DMA_ACCESS_RO,
+					     NV_DMA_TARGET_VIDMEM, &pushbuf);
 		chan->pushbuf_base = 0;
 	} else {
 		/* NV04 cmdbuf hack, from original ddx.. not sure of it's
 		 * exact reason for existing :)  PCI access to cmdbuf in
 		 * VRAM.
 		 */
-		ret = nouveau_gpuobj_dma_new
-			(dev, channel, NV_CLASS_DMA_IN_MEMORY,
-			 cb->start + drm_get_resource_start(dev, 1),
-			 cb->size, NV_DMA_ACCESS_RO,
-			 NV_DMA_TARGET_PCI, &pushbuf);
+		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
+					     cb->start +
+					       drm_get_resource_start(dev, 1),
+					     cb->size, NV_DMA_ACCESS_RO,
+					     NV_DMA_TARGET_PCI, &pushbuf);
 		chan->pushbuf_base = 0;
 	}
 
@@ -251,7 +248,7 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel)
 		return ret;
 	}
 
-	if ((ret = nouveau_gpuobj_ref_add(dev, channel, 0, pushbuf,
+	if ((ret = nouveau_gpuobj_ref_add(dev, chan, 0, pushbuf,
 					  &chan->pushbuf))) {
 		DRM_ERROR("Error referencing push buffer ctxdma: %d\n", ret);
 		if (pushbuf != dev_priv->gart_info.sg_ctxdma)
@@ -270,8 +267,8 @@ int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret,
 {
 	int ret;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_engine_func *engine = &dev_priv->Engine;
-	struct nouveau_fifo *chan;
+	struct nouveau_engine *engine = &dev_priv->Engine;
+	struct nouveau_channel *chan;
 	int channel;
 
 	/*
@@ -293,34 +290,36 @@ int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret,
 		return -EINVAL;
 	(*chan_ret) = channel;
 
-	dev_priv->fifos[channel] = drm_calloc(1, sizeof(struct nouveau_fifo),
+	dev_priv->fifos[channel] = drm_calloc(1, sizeof(struct nouveau_channel),
 					      DRM_MEM_DRIVER);
 	if (!dev_priv->fifos[channel])
 		return -ENOMEM;
 	dev_priv->fifo_alloc_count++;
 	chan = dev_priv->fifos[channel];
+	chan->dev = dev;
+	chan->id = channel;
 	chan->file_priv = file_priv;
 
 	DRM_INFO("Allocating FIFO number %d\n", channel);
 
 	/* Setup channel's default objects */
-	ret = nouveau_gpuobj_channel_init(dev, channel, vram_handle, tt_handle);
+	ret = nouveau_gpuobj_channel_init(chan, vram_handle, tt_handle);
 	if (ret) {
-		nouveau_fifo_free(dev, channel);
+		nouveau_fifo_free(chan);
 		return ret;
 	}
 
 	/* allocate a command buffer, and create a dma object for the gpu */
-	ret = nouveau_fifo_cmdbuf_alloc(dev, channel);
+	ret = nouveau_fifo_cmdbuf_alloc(chan);
 	if (ret) {
-		nouveau_fifo_free(dev, channel);
+		nouveau_fifo_free(chan);
 		return ret;
 	}
 
 	/* Allocate space for per-channel fixed notifier memory */
-	ret = nouveau_notifier_init_channel(dev, channel, file_priv);
+	ret = nouveau_notifier_init_channel(chan);
 	if (ret) {
-		nouveau_fifo_free(dev, channel);
+		nouveau_fifo_free(chan);
 		return ret;
 	}
 
@@ -333,16 +332,16 @@ int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret,
 	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
 
 	/* Create a graphics context for new channel */
-	ret = engine->graph.create_context(dev, channel);
+	ret = engine->graph.create_context(chan);
 	if (ret) {
-		nouveau_fifo_free(dev, channel);
+		nouveau_fifo_free(chan);
 		return ret;
 	}
 
 	/* Construct inital RAMFC for new channel */
-	ret = engine->fifo.create_context(dev, channel);
+	ret = engine->fifo.create_context(chan);
 	if (ret) {
-		nouveau_fifo_free(dev, channel);
+		nouveau_fifo_free(chan);
 		return ret;
 	}
 
@@ -359,15 +358,15 @@ int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret,
 	 * other case, the GPU will handle this when it switches contexts.
 	 */
 	if (dev_priv->fifo_alloc_count == 1) {
-		ret = engine->fifo.load_context(dev, channel);
+		ret = engine->fifo.load_context(chan);
 		if (ret) {
-			nouveau_fifo_free(dev, channel);
+			nouveau_fifo_free(chan);
 			return ret;
 		}
 
-		ret = engine->graph.load_context(dev, channel);
+		ret = engine->graph.load_context(chan);
 		if (ret) {
-			nouveau_fifo_free(dev, channel);
+			nouveau_fifo_free(chan);
 			return ret;
 		}
 
@@ -399,28 +398,23 @@ int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret,
 }
 
 /* stops a fifo */
-void nouveau_fifo_free(struct drm_device *dev, int channel)
+void nouveau_fifo_free(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_engine_func *engine = &dev_priv->Engine;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
-
-	if (!chan) {
-		DRM_ERROR("Freeing non-existant channel %d\n", channel);
-		return;
-	}
+	struct nouveau_engine *engine = &dev_priv->Engine;
 
-	DRM_INFO("%s: freeing fifo %d\n", __func__, channel);
+	DRM_INFO("%s: freeing fifo %d\n", __func__, chan->id);
 
 	/* disable the fifo caches */
 	NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
 
 	// FIXME XXX needs more code
 
-	engine->fifo.destroy_context(dev, channel);
+	engine->fifo.destroy_context(chan);
 
 	/* Cleanup PGRAPH state */
-	engine->graph.destroy_context(dev, channel);
+	engine->graph.destroy_context(chan);
 
 	/* reenable the fifo caches */
 	NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
@@ -432,12 +426,12 @@ void nouveau_fifo_free(struct drm_device *dev, int channel)
 		chan->pushbuf_mem = NULL;
 	}
 
-	nouveau_notifier_takedown_channel(dev, channel);
+	nouveau_notifier_takedown_channel(chan);
 
 	/* Destroy objects belonging to the channel */
-	nouveau_gpuobj_channel_takedown(dev, channel);
+	nouveau_gpuobj_channel_takedown(chan);
 
-	dev_priv->fifos[channel] = NULL;
+	dev_priv->fifos[chan->id] = NULL;
 	dev_priv->fifo_alloc_count--;
 	drm_free(chan, sizeof(*chan), DRM_MEM_DRIVER);
 }
@@ -445,14 +439,16 @@ void nouveau_fifo_free(struct drm_device *dev, int channel)
 /* cleanups all the fifos from file_priv */
 void nouveau_fifo_cleanup(struct drm_device *dev, struct drm_file *file_priv)
 {
-	int i;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
+	int i;
 
 	DRM_DEBUG("clearing FIFO enables from file_priv\n");
-	for(i=0;i<nouveau_fifo_number(dev);i++)
-		if (dev_priv->fifos[i] &&
-		    dev_priv->fifos[i]->file_priv==file_priv)
-			nouveau_fifo_free(dev,i);
+	for(i = 0; i < nouveau_fifo_number(dev); i++) {
+		struct nouveau_channel *chan = dev_priv->fifos[i];
+
+		if (chan && chan->file_priv == file_priv)
+			nouveau_fifo_free(chan);
+	}
 }
 
 int
@@ -477,7 +473,7 @@ static int nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, struct d
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	struct drm_nouveau_fifo_alloc *init = data;
 	struct drm_map_list *entry;
-	struct nouveau_fifo *chan;
+	struct nouveau_channel *chan;
 	int res;
 
 	if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c
index 7a982ba4..b1090587 100644
--- a/shared-core/nouveau_notifier.c
+++ b/shared-core/nouveau_notifier.c
@@ -30,11 +30,10 @@
 #include "nouveau_drv.h"
 
 int
-nouveau_notifier_init_channel(struct drm_device *dev, int channel,
-			      struct drm_file *file_priv)
+nouveau_notifier_init_channel(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	int flags, ret;
 
 	/*TODO: PCI notifier blocks */
@@ -47,9 +46,9 @@ nouveau_notifier_init_channel(struct drm_device *dev, int channel,
 		flags = NOUVEAU_MEM_FB;
 	flags |= NOUVEAU_MEM_MAPPED;
 
-DRM_DEBUG("Allocating notifier block in %d\n", flags);
+	DRM_DEBUG("Allocating notifier block in %d\n", flags);
 	chan->notifier_block = nouveau_mem_alloc(dev, 0, PAGE_SIZE, flags,
-						 file_priv);
+						 (struct drm_file *)-2);
 	if (!chan->notifier_block)
 		return -ENOMEM;
 
@@ -62,25 +61,23 @@ DRM_DEBUG("Allocating notifier block in %d\n", flags);
 }
 
 void
-nouveau_notifier_takedown_channel(struct drm_device *dev, int channel)
+nouveau_notifier_takedown_channel(struct nouveau_channel *chan)
 {
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
+	struct drm_device *dev = chan->dev;
 
 	if (chan->notifier_block) {
 		nouveau_mem_free(dev, chan->notifier_block);
 		chan->notifier_block = NULL;
 	}
 
-	/*XXX: heap destroy */
+	nouveau_mem_takedown(&chan->notifier_heap);
 }
 
 int
-nouveau_notifier_alloc(struct drm_device *dev, int channel, uint32_t handle,
+nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle,
 		       int count, uint32_t *b_offset)
 {
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
+	struct drm_device *dev = chan->dev;
 	struct nouveau_gpuobj *nobj = NULL;
 	struct mem_block *mem;
 	uint32_t offset;
@@ -88,14 +85,14 @@ nouveau_notifier_alloc(struct drm_device *dev, int channel, uint32_t handle,
 
 	if (!chan->notifier_heap) {
 		DRM_ERROR("Channel %d doesn't have a notifier heap!\n",
-			  channel);
+			  chan->id);
 		return -EINVAL;
 	}
 
 	mem = nouveau_mem_alloc_block(chan->notifier_heap, 32, 0,
 				      chan->file_priv);
 	if (!mem) {
-		DRM_ERROR("Channel %d notifier block full\n", channel);
+		DRM_ERROR("Channel %d notifier block full\n", chan->id);
 		return -ENOMEM;
 	}
 	mem->flags = NOUVEAU_MEM_NOTIFIER;
@@ -113,7 +110,7 @@ nouveau_notifier_alloc(struct drm_device *dev, int channel, uint32_t handle,
 		return -EINVAL;
 	}
 
-	if ((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY,
+	if ((ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
 					  offset, mem->size,
 					  NV_DMA_ACCESS_RW, target, &nobj))) {
 		nouveau_mem_free_block(mem);
@@ -121,7 +118,7 @@ nouveau_notifier_alloc(struct drm_device *dev, int channel, uint32_t handle,
 		return ret;
 	}
 
-	if ((ret = nouveau_gpuobj_ref_add(dev, channel, handle, nobj, NULL))) {
+	if ((ret = nouveau_gpuobj_ref_add(dev, chan, handle, nobj, NULL))) {
 		nouveau_gpuobj_del(dev, &nobj);
 		nouveau_mem_free_block(mem);
 		DRM_ERROR("Error referencing notifier ctxdma: %d\n", ret);
@@ -133,19 +130,16 @@ nouveau_notifier_alloc(struct drm_device *dev, int channel, uint32_t handle,
 }
 
 int
-nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv)
+nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data,
+			     struct drm_file *file_priv)
 {
 	struct drm_nouveau_notifier_alloc *na = data;
+	struct nouveau_channel *chan;
 	int ret;
 
-	if (!nouveau_fifo_owner(dev, file_priv, na->channel)) {
-		DRM_ERROR("pid %d doesn't own channel %d\n",
-			  DRM_CURRENTPID, na->channel);
-		return -EPERM;
-	}
+	NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(na->channel, file_priv, chan);
 
-	ret = nouveau_notifier_alloc(dev, na->channel, na->handle,
-				     na->count, &na->offset);
+	ret = nouveau_notifier_alloc(chan, na->handle, na->count, &na->offset);
 	if (ret)
 		return ret;
 
diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c
index e8b12bb7..274bb2a7 100644
--- a/shared-core/nouveau_object.c
+++ b/shared-core/nouveau_object.c
@@ -100,7 +100,7 @@ static int
 nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
 {
 	struct drm_nouveau_private *dev_priv=dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[ref->channel];
+	struct nouveau_channel *chan = dev_priv->fifos[ref->channel];
 	struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
 	struct nouveau_gpuobj *gpuobj = ref->gpuobj;
 	uint32_t ctx, co, ho;
@@ -149,7 +149,7 @@ static void
 nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[ref->channel];
+	struct nouveau_channel *chan = dev_priv->fifos[ref->channel];
 	struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
 	uint32_t co, ho;
 
@@ -180,34 +180,28 @@ nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
 }
 
 int
-nouveau_gpuobj_new(struct drm_device *dev, int channel, int size, int align,
-		   uint32_t flags, struct nouveau_gpuobj **gpuobj_ret)
+nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
+		   int size, int align, uint32_t flags,
+		   struct nouveau_gpuobj **gpuobj_ret)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_engine_func *engine = &dev_priv->Engine;
-	struct nouveau_fifo *chan = NULL;
+	struct nouveau_engine *engine = &dev_priv->Engine;
 	struct nouveau_gpuobj *gpuobj;
 	struct mem_block *pramin = NULL;
 	int ret;
 
 	DRM_DEBUG("ch%d size=%d align=%d flags=0x%08x\n",
-		  channel, size, align, flags);
+		  chan ? chan->id : -1, size, align, flags);
 
 	if (!dev_priv || !gpuobj_ret || *gpuobj_ret != NULL)
 		return -EINVAL;
 
-	if (channel >= 0) {
-		if (channel > nouveau_fifo_number(dev))
-			return -EINVAL;
-		chan = dev_priv->fifos[channel];
-	}
-
 	gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER);
 	if (!gpuobj)
 		return -ENOMEM;
 	DRM_DEBUG("gpuobj %p\n", gpuobj);
 	gpuobj->flags = flags;
-	gpuobj->im_channel = channel;
+	gpuobj->im_channel = chan ? chan->id : -1;
 
 	/* Choose between global instmem heap, and per-channel private
 	 * instmem heap.  On <NV50 allow requests for private instmem
@@ -288,7 +282,7 @@ void nouveau_gpuobj_takedown(struct drm_device *dev)
 int nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_engine_func *engine = &dev_priv->Engine;
+	struct nouveau_engine *engine = &dev_priv->Engine;
 	struct nouveau_gpuobj *gpuobj;
 
 	DRM_DEBUG("gpuobj %p\n", pgpuobj ? *pgpuobj : NULL);
@@ -325,7 +319,8 @@ int nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj)
 }
 
 static int
-nouveau_gpuobj_instance_get(struct drm_device *dev, int channel,
+nouveau_gpuobj_instance_get(struct drm_device *dev,
+			    struct nouveau_channel *chan,
 			    struct nouveau_gpuobj *gpuobj, uint32_t *inst)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -337,15 +332,15 @@ nouveau_gpuobj_instance_get(struct drm_device *dev, int channel,
 		return 0;
 	}
 
-	if ((channel > 0) && gpuobj->im_channel != channel) {
+	if (chan && gpuobj->im_channel != chan->id) {
 		DRM_ERROR("Channel mismatch: obj %d, ref %d\n",
-			  gpuobj->im_channel, channel);
+			  gpuobj->im_channel, chan->id);
 		return -EINVAL;
 	}
 
 	/* NV50 channel-local instance */
-	if (channel > 0) {
-		cpramin = dev_priv->fifos[channel]->ramin->gpuobj;
+	if (chan > 0) {
+		cpramin = chan->ramin->gpuobj;
 		*inst = gpuobj->im_pramin->start - cpramin->im_pramin->start;
 		return 0;
 	}
@@ -371,29 +366,25 @@ nouveau_gpuobj_instance_get(struct drm_device *dev, int channel,
 }
 
 int
-nouveau_gpuobj_ref_add(struct drm_device *dev, int channel, uint32_t handle,
-		       struct nouveau_gpuobj *gpuobj, struct nouveau_gpuobj_ref **ref_ret)
+nouveau_gpuobj_ref_add(struct drm_device *dev, struct nouveau_channel *chan,
+		       uint32_t handle, struct nouveau_gpuobj *gpuobj,
+		       struct nouveau_gpuobj_ref **ref_ret)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = NULL;
 	struct nouveau_gpuobj_ref *ref;
 	uint32_t instance;
 	int ret;
 
-	DRM_DEBUG("ch%d h=0x%08x gpuobj=%p\n", channel, handle, gpuobj);
+	DRM_DEBUG("ch%d h=0x%08x gpuobj=%p\n",
+		  chan ? chan->id : -1, handle, gpuobj);
 
 	if (!dev_priv || !gpuobj || (ref_ret && *ref_ret != NULL))
 		return -EINVAL;
 
-	if (channel >= 0) {
-		if (channel > nouveau_fifo_number(dev))
-			return -EINVAL;
-		chan = dev_priv->fifos[channel];
-	} else
-	if (!ref_ret)
+	if (!chan && !ref_ret)
 		return -EINVAL;
 
-	ret = nouveau_gpuobj_instance_get(dev, channel, gpuobj, &instance);
+	ret = nouveau_gpuobj_instance_get(dev, chan, gpuobj, &instance);
 	if (ret)
 		return ret;
 
@@ -401,7 +392,7 @@ nouveau_gpuobj_ref_add(struct drm_device *dev, int channel, uint32_t handle,
 	if (!ref)
 		return -ENOMEM;
 	ref->gpuobj   = gpuobj;
-	ref->channel  = channel;
+	ref->channel  = chan ? chan->id : -1;
 	ref->instance = instance;
 
 	if (!ref_ret) {
@@ -452,8 +443,9 @@ int nouveau_gpuobj_ref_del(struct drm_device *dev, struct nouveau_gpuobj_ref **p
 }
 
 int
-nouveau_gpuobj_new_ref(struct drm_device *dev, int oc, int rc, uint32_t handle,
-		       int size, int align, uint32_t flags,
+nouveau_gpuobj_new_ref(struct drm_device *dev,
+		       struct nouveau_channel *oc, struct nouveau_channel *rc,
+		       uint32_t handle, int size, int align, uint32_t flags,
 		       struct nouveau_gpuobj_ref **ref)
 {
 	struct nouveau_gpuobj *gpuobj = NULL;
@@ -471,11 +463,9 @@ nouveau_gpuobj_new_ref(struct drm_device *dev, int oc, int rc, uint32_t handle,
 }
 
 static int
-nouveau_gpuobj_ref_find(struct drm_device *dev, int channel, uint32_t handle,
+nouveau_gpuobj_ref_find(struct nouveau_channel *chan, uint32_t handle,
 			struct nouveau_gpuobj_ref **ref_ret)
 {
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	struct nouveau_gpuobj_ref *ref = chan->ramht_refs;
 
 	while (ref) {
@@ -524,7 +514,7 @@ nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t offset, uint32_t size,
 	}
 
 	if (pref) {
-		if ((i = nouveau_gpuobj_ref_add(dev, -1, 0, gpuobj, pref))) {
+		if ((i = nouveau_gpuobj_ref_add(dev, NULL, 0, gpuobj, pref))) {
 			nouveau_gpuobj_del(dev, &gpuobj);
 			return i;
 		}
@@ -577,10 +567,11 @@ nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class)
    to it that can be used to set up context objects.
 */
 int
-nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class,
-		       uint64_t offset, uint64_t size, int access, int target,
-		       struct nouveau_gpuobj **gpuobj)
+nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class,
+		       uint64_t offset, uint64_t size, int access,
+		       int target, struct nouveau_gpuobj **gpuobj)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	int ret;
 	uint32_t is_scatter_gather = 0;
@@ -591,7 +582,7 @@ nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class,
 
 
 	DRM_DEBUG("ch%d class=0x%04x offset=0x%llx size=0x%llx\n",
-		  channel, class, offset, size);
+		  chan->id, class, offset, size);
 	DRM_DEBUG("access=%d target=%d\n", access, target);
 
 	switch (target) {
@@ -608,7 +599,7 @@ nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class,
                 break;
         }
 	
-	ret = nouveau_gpuobj_new(dev, channel,
+	ret = nouveau_gpuobj_new(dev, chan,
 				 is_scatter_gather ? ((page_count << 2) + 12) : nouveau_gpuobj_class_instmem_size(dev, class),
 				 16,
 				 NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
@@ -711,19 +702,19 @@ nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class,
 }
 
 int
-nouveau_gpuobj_gart_dma_new(struct drm_device *dev, int channel,
+nouveau_gpuobj_gart_dma_new(struct nouveau_channel *chan,
 			    uint64_t offset, uint64_t size, int access,
 			    struct nouveau_gpuobj **gpuobj,
 			    uint32_t *o_ret)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	int ret;
 
 	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP ||
 	    (dev_priv->card_type >= NV_50 &&
 	     dev_priv->gart_info.type == NOUVEAU_GART_SGDMA)) {
-		ret = nouveau_gpuobj_dma_new(dev, channel,
-					     NV_CLASS_DMA_IN_MEMORY,
+		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
 					     offset, size, access,
 					     NV_DMA_TARGET_AGP, gpuobj);
 		if (o_ret)
@@ -798,15 +789,16 @@ nouveau_gpuobj_gart_dma_new(struct drm_device *dev, int channel,
    set to 0?
 */
 int
-nouveau_gpuobj_gr_new(struct drm_device *dev, int channel, int class,
+nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class,
 		      struct nouveau_gpuobj **gpuobj)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	int ret;
 
-	DRM_DEBUG("ch%d class=0x%04x\n", channel, class);
+	DRM_DEBUG("ch%d class=0x%04x\n", chan->id, class);
 
-	ret = nouveau_gpuobj_new(dev, channel,
+	ret = nouveau_gpuobj_new(dev, chan,
 				 nouveau_gpuobj_class_instmem_size(dev, class),
 				 16,
 				 NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
@@ -847,14 +839,14 @@ nouveau_gpuobj_gr_new(struct drm_device *dev, int channel, int class,
 }
 
 static int
-nouveau_gpuobj_channel_init_pramin(struct drm_device *dev, int channel)
+nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	struct nouveau_gpuobj *pramin = NULL;
 	int size, base, ret;
 
-	DRM_DEBUG("ch%d\n", channel);
+	DRM_DEBUG("ch%d\n", chan->id);
 
 	/* Base amount for object storage (4KiB enough?) */
 	size = 0x1000;
@@ -876,8 +868,8 @@ nouveau_gpuobj_channel_init_pramin(struct drm_device *dev, int channel)
 	}
 
 	DRM_DEBUG("ch%d PRAMIN size: 0x%08x bytes, base alloc=0x%08x\n",
-		  channel, size, base);
-	ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, size, 0x1000, 0,
+		  chan->id, size, base);
+	ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, size, 0x1000, 0,
 				     &chan->ramin);
 	if (ret) {
 		DRM_ERROR("Error allocating channel PRAMIN: %d\n", ret);
@@ -897,21 +889,21 @@ nouveau_gpuobj_channel_init_pramin(struct drm_device *dev, int channel)
 }
 
 int
-nouveau_gpuobj_channel_init(struct drm_device *dev, int channel,
+nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
 			    uint32_t vram_h, uint32_t tt_h)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	struct nouveau_gpuobj *vram = NULL, *tt = NULL;
 	int ret, i;
 
-	DRM_DEBUG("ch%d vram=0x%08x tt=0x%08x\n", channel, vram_h, tt_h);
+	DRM_DEBUG("ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);
 
 	/* Reserve a block of PRAMIN for the channel
 	 *XXX: maybe on <NV50 too at some point
 	 */
 	if (0 || dev_priv->card_type == NV_50) {
-		ret = nouveau_gpuobj_channel_init_pramin(dev, channel);
+		ret = nouveau_gpuobj_channel_init_pramin(chan);
 		if (ret)
 			return ret;
 	}
@@ -930,7 +922,7 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel,
 			INSTANCE_WR(chan->vm_pd, (i+4)/4, 0xdeadcafe);
 		}
 
-		if ((ret = nouveau_gpuobj_ref_add(dev, -1, 0,
+		if ((ret = nouveau_gpuobj_ref_add(dev, NULL, 0,
 						  dev_priv->gart_info.sg_ctxdma,
 						  &chan->vm_gart_pt)))
 			return ret;
@@ -941,12 +933,12 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel,
 
 	/* RAMHT */
 	if (dev_priv->card_type < NV_50) {
-		ret = nouveau_gpuobj_ref_add(dev, -1, 0, dev_priv->ramht,
+		ret = nouveau_gpuobj_ref_add(dev, NULL, 0, dev_priv->ramht,
 					     &chan->ramht);
 		if (ret)
 			return ret;
 	} else {
-		ret = nouveau_gpuobj_new_ref(dev, channel, channel, 0,
+		ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0,
 					     0x8000, 16,
 					     NVOBJ_FLAG_ZERO_ALLOC,
 					     &chan->ramht);
@@ -955,7 +947,7 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel,
 	}
 
 	/* VRAM ctxdma */
-	if ((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY,
+	if ((ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
 					  0, dev_priv->fb_available_size,
 					  NV_DMA_ACCESS_RW,
 					  NV_DMA_TARGET_VIDMEM, &vram))) {
@@ -963,20 +955,19 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel,
 		return ret;
 	}
 
-	if ((ret = nouveau_gpuobj_ref_add(dev, channel, vram_h, vram, NULL))) {
+	if ((ret = nouveau_gpuobj_ref_add(dev, chan, vram_h, vram, NULL))) {
 		DRM_ERROR("Error referencing VRAM ctxdma: %d\n", ret);
 		return ret;
 	}
 
 	/* TT memory ctxdma */
 	if (dev_priv->gart_info.type != NOUVEAU_GART_NONE) {
-		ret = nouveau_gpuobj_gart_dma_new(dev, channel, 0,
+		ret = nouveau_gpuobj_gart_dma_new(chan, 0,
 						  dev_priv->gart_info.aper_size,
 						  NV_DMA_ACCESS_RW, &tt, NULL);
 	} else
 	if (dev_priv->pci_heap) {
-		ret = nouveau_gpuobj_dma_new(dev, channel,
-					     NV_CLASS_DMA_IN_MEMORY,
+		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
 					     0, dev->sg->pages * PAGE_SIZE,
 					     NV_DMA_ACCESS_RW,
 					     NV_DMA_TARGET_PCI_NONLINEAR, &tt);
@@ -990,7 +981,7 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel,
 		return ret;
 	}
 
-	ret = nouveau_gpuobj_ref_add(dev, channel, tt_h, tt, NULL);
+	ret = nouveau_gpuobj_ref_add(dev, chan, tt_h, tt, NULL);
 	if (ret) {
 		DRM_ERROR("Error referencing TT ctxdma: %d\n", ret);
 		return ret;
@@ -1000,13 +991,12 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel,
 }
 
 void
-nouveau_gpuobj_channel_takedown(struct drm_device *dev, int channel)
+nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan)
 {
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
+	struct drm_device *dev = chan->dev;
 	struct nouveau_gpuobj_ref *ref;
 
-	DRM_DEBUG("ch%d\n", channel);
+	DRM_DEBUG("ch%d\n", chan->id);
 
 	while ((ref = chan->ramht_refs)) {
 		chan->ramht_refs = ref->next;
@@ -1024,35 +1014,33 @@ nouveau_gpuobj_channel_takedown(struct drm_device *dev, int channel)
 
 }
 
-int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv)
+int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data,
+			      struct drm_file *file_priv)
 {
+	struct nouveau_channel *chan;
 	struct drm_nouveau_grobj_alloc *init = data;
 	struct nouveau_gpuobj *gr = NULL;
 	int ret;
 
-	if (!nouveau_fifo_owner(dev, file_priv, init->channel)) {
-		DRM_ERROR("pid %d doesn't own channel %d\n",
-				DRM_CURRENTPID, init->channel);
-		return -EINVAL;
-	}
+	NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(init->channel, file_priv, chan);
 
 	//FIXME: check args, only allow trusted objects to be created
 	
 	if (init->handle == ~0)
 		return -EINVAL;
-	if (nouveau_gpuobj_ref_find(dev, init->channel, init->handle, NULL) ==
+
+	if (nouveau_gpuobj_ref_find(chan, init->handle, NULL) ==
 	    0)
 		return -EEXIST;
 
-	ret = nouveau_gpuobj_gr_new(dev, init->channel, init->class, &gr);
+	ret = nouveau_gpuobj_gr_new(chan, init->class, &gr);
 	if (ret) {
 		DRM_ERROR("Error creating gr object: %d (%d/0x%08x)\n",
 			  ret, init->channel, init->handle);
 		return ret;
 	}
 
-	if ((ret = nouveau_gpuobj_ref_add(dev, init->channel, init->handle,
-					  gr, NULL))) {
+	if ((ret = nouveau_gpuobj_ref_add(dev, chan, init->handle, gr, NULL))) {
 		DRM_ERROR("Error referencing gr object: %d (%d/0x%08x\n)",
 			  ret, init->channel, init->handle);
 		nouveau_gpuobj_del(dev, &gr);
diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c
index f45f2783..26ba8fbf 100644
--- a/shared-core/nouveau_state.c
+++ b/shared-core/nouveau_state.c
@@ -93,7 +93,7 @@ static uint64_t nouveau_stub_timer_read(struct drm_device *dev) { return 0; }
 static int nouveau_init_engine_ptrs(struct drm_device *dev)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_engine_func *engine = &dev_priv->Engine;
+	struct nouveau_engine *engine = &dev_priv->Engine;
 
 	switch (dev_priv->chipset & 0xf0) {
 	case 0x00:
@@ -270,7 +270,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
 static int nouveau_card_init(struct drm_device *dev)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_engine_func *engine;
+	struct nouveau_engine *engine;
 	int ret;
 
 	/* Map any PCI resources we need on the card */
@@ -332,7 +332,7 @@ static int nouveau_card_init(struct drm_device *dev)
 static void nouveau_card_takedown(struct drm_device *dev)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_engine_func *engine = &dev_priv->Engine;
+	struct nouveau_engine *engine = &dev_priv->Engine;
 
 	if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
 		engine->fifo.takedown(dev);
@@ -526,6 +526,7 @@ void nouveau_wait_for_idle(struct drm_device *dev)
 		uint32_t status;
 		do {
 			uint32_t pmc_e = NV_READ(NV03_PMC_ENABLE);
+			(void)pmc_e;
 			status = NV_READ(NV04_PGRAPH_STATUS);
 			if (!status)
 				break;
diff --git a/shared-core/nv04_fifo.c b/shared-core/nv04_fifo.c
index 564efd0b..4d61f4fe 100644
--- a/shared-core/nv04_fifo.c
+++ b/shared-core/nv04_fifo.c
@@ -36,13 +36,13 @@
 #define NV04_RAMFC__SIZE 32
 
 int
-nv04_fifo_create_context(struct drm_device *dev, int channel)
+nv04_fifo_create_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	int ret;
 
-	if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(channel),
+	if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id),
 						NV04_RAMFC__SIZE,
 						NVOBJ_FLAG_ZERO_ALLOC |
 						NVOBJ_FLAG_ZERO_FREE,
@@ -62,30 +62,29 @@ nv04_fifo_create_context(struct drm_device *dev, int channel)
 			     0));
 
 	/* enable the fifo dma operation */
-	NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<channel));
+	NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE) | (1<<chan->id));
 	return 0;
 }
 
 void
-nv04_fifo_destroy_context(struct drm_device *dev, int channel)
+nv04_fifo_destroy_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
-
-	NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<channel));
+	
+	NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
 
-	if (chan->ramfc)
-		nouveau_gpuobj_ref_del(dev, &chan->ramfc);
+	nouveau_gpuobj_ref_del(dev, &chan->ramfc);
 }
 
 int
-nv04_fifo_load_context(struct drm_device *dev, int channel)
+nv04_fifo_load_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	uint32_t tmp;
 
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, (1<<8) | channel);
+	NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, (1<<8) | chan->id);
 
 	NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET));
 	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT));
@@ -107,10 +106,10 @@ nv04_fifo_load_context(struct drm_device *dev, int channel)
 }
 
 int
-nv04_fifo_save_context(struct drm_device *dev, int channel)
+nv04_fifo_save_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	uint32_t tmp;
 
 	RAMFC_WR(DMA_PUT, NV04_PFIFO_CACHE1_DMA_PUT);
diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c
index e35e3071..b2ea7804 100644
--- a/shared-core/nv04_graph.c
+++ b/shared-core/nv04_graph.c
@@ -336,14 +336,13 @@ void nouveau_nv04_context_switch(struct drm_device *dev)
 	NV_WRITE(NV04_PGRAPH_FIFO,0x1);
 }
 
-int nv04_graph_create_context(struct drm_device *dev, int channel) {
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	DRM_DEBUG("nv04_graph_context_create %d\n", channel);
+int nv04_graph_create_context(struct nouveau_channel *chan) {
+	DRM_DEBUG("nv04_graph_context_create %d\n", chan->id);
 
-	memset(dev_priv->fifos[channel]->pgraph_ctx, 0, sizeof(dev_priv->fifos[channel]->pgraph_ctx));
+	memset(chan->pgraph_ctx, 0, sizeof(chan->pgraph_ctx));
 
 	//dev_priv->fifos[channel].pgraph_ctx_user = channel << 24;
-	dev_priv->fifos[channel]->pgraph_ctx[0] = 0x0001ffff;
+	chan->pgraph_ctx[0] = 0x0001ffff;
 	/* is it really needed ??? */
 	//dev_priv->fifos[channel].pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4);
 	//dev_priv->fifos[channel].pgraph_ctx[2] = NV_READ(0x004006b0);
@@ -351,17 +350,17 @@ int nv04_graph_create_context(struct drm_device *dev, int channel) {
 	return 0;
 }
 
-void nv04_graph_destroy_context(struct drm_device *dev, int channel)
+void nv04_graph_destroy_context(struct nouveau_channel *chan)
 {
 }
 
-int nv04_graph_load_context(struct drm_device *dev, int channel)
+int nv04_graph_load_context(struct nouveau_channel *chan)
 {
 	DRM_ERROR("stub!\n");
 	return 0;
 }
 
-int nv04_graph_save_context(struct drm_device *dev, int channel)
+int nv04_graph_save_context(struct nouveau_channel *chan)
 {
 	DRM_ERROR("stub!\n");
 	return 0;
diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c
index 7b9c665b..47af0ff0 100644
--- a/shared-core/nv10_fifo.c
+++ b/shared-core/nv10_fifo.c
@@ -37,13 +37,13 @@
 #define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32)
 
 int
-nv10_fifo_create_context(struct drm_device *dev, int channel)
+nv10_fifo_create_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	int ret;
 
-	if ((ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(channel),
+	if ((ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id),
 						NV10_RAMFC__SIZE,
 						NVOBJ_FLAG_ZERO_ALLOC |
 						NVOBJ_FLAG_ZERO_FREE,
@@ -65,30 +65,29 @@ nv10_fifo_create_context(struct drm_device *dev, int channel)
 				 0);
 
 	/* enable the fifo dma operation */
-	NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<channel));
+	NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<chan->id));
 	return 0;
 }
 
 void
-nv10_fifo_destroy_context(struct drm_device *dev, int channel)
+nv10_fifo_destroy_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 
-	NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<channel));
+	NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
 
-	if (chan->ramfc)
-		nouveau_gpuobj_ref_del(dev, &chan->ramfc);
+	nouveau_gpuobj_ref_del(dev, &chan->ramfc);
 }
 
 int
-nv10_fifo_load_context(struct drm_device *dev, int channel)
+nv10_fifo_load_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	uint32_t tmp;
 
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH1            , 0x00000100 | channel);
+	NV_WRITE(NV03_PFIFO_CACHE1_PUSH1            , 0x00000100 | chan->id);
 
 	NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET          , RAMFC_RD(DMA_GET));
 	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT          , RAMFC_RD(DMA_PUT));
@@ -124,10 +123,10 @@ nv10_fifo_load_context(struct drm_device *dev, int channel)
 }
 
 int
-nv10_fifo_save_context(struct drm_device *dev, int channel)
+nv10_fifo_save_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	uint32_t tmp;
 
 	RAMFC_WR(DMA_PUT          , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c
index ce1cbfa7..a2df2d71 100644
--- a/shared-core/nv10_graph.c
+++ b/shared-core/nv10_graph.c
@@ -544,33 +544,33 @@ static int nv10_graph_ctx_regs_find_offset(struct drm_device *dev, int reg)
 	return -1;
 }
 
-int nv10_graph_load_context(struct drm_device *dev, int channel)
+int nv10_graph_load_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *fifo = dev_priv->fifos[channel];
 	int i, j;
 
 	for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++)
-		NV_WRITE(nv10_graph_ctx_regs[i], fifo->pgraph_ctx[i]);
+		NV_WRITE(nv10_graph_ctx_regs[i], chan->pgraph_ctx[i]);
 	if (dev_priv->chipset>=0x17) {
 		for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++)
-			NV_WRITE(nv17_graph_ctx_regs[j], fifo->pgraph_ctx[i]);
+			NV_WRITE(nv17_graph_ctx_regs[j], chan->pgraph_ctx[i]);
 	}
 
 	return 0;
 }
 
-int nv10_graph_save_context(struct drm_device *dev, int channel)
+int nv10_graph_save_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *fifo = dev_priv->fifos[channel];
 	int i, j;
 
 	for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++)
-		fifo->pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]);
+		chan->pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]);
 	if (dev_priv->chipset>=0x17) {
 		for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++)
-			fifo->pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]);
+			chan->pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]);
 	}
 
 	return 0;
@@ -579,12 +579,17 @@ int nv10_graph_save_context(struct drm_device *dev, int channel)
 void nouveau_nv10_context_switch(struct drm_device *dev)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	int channel, channel_old;
+	struct nouveau_channel *next, *last;
+	int chid;
 
-	channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
-	channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
+	chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
+	next = dev_priv->fifos[chid];
 
-	DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel);
+	chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
+	last = dev_priv->fifos[chid];
+
+	DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",
+		 last->id, next->id);
 
 	NV_WRITE(NV04_PGRAPH_FIFO,0x0);
 #if 0
@@ -592,7 +597,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev)
 	NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000);
 	NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
 #endif
-	nv10_graph_save_context(dev, channel_old);
+	nv10_graph_save_context(last);
 	
 	nouveau_wait_for_idle(dev);
 
@@ -601,10 +606,10 @@ void nouveau_nv10_context_switch(struct drm_device *dev)
 
 	nouveau_wait_for_idle(dev);
 
-	nv10_graph_load_context(dev, channel);
+	nv10_graph_load_context(next);
 	
 	NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
-	NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24);
+	NV_WRITE(NV10_PGRAPH_CTX_USER, next->id << 24);
 	NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
 #if 0
 	NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
@@ -617,17 +622,17 @@ void nouveau_nv10_context_switch(struct drm_device *dev)
 #define NV_WRITE_CTX(reg, val) do { \
 	int offset = nv10_graph_ctx_regs_find_offset(dev, reg); \
 	if (offset > 0) \
-		fifo->pgraph_ctx[offset] = val; \
+		chan->pgraph_ctx[offset] = val; \
 	} while (0)
 
-int nv10_graph_create_context(struct drm_device *dev, int channel) {
+int nv10_graph_create_context(struct nouveau_channel *chan) {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *fifo = dev_priv->fifos[channel];
 	uint32_t tmp, vramsz;
 
-	DRM_DEBUG("nv10_graph_context_create %d\n", channel);
+	DRM_DEBUG("nv10_graph_context_create %d\n", chan->id);
 
-	memset(fifo->pgraph_ctx, 0, sizeof(fifo->pgraph_ctx));
+	memset(chan->pgraph_ctx, 0, sizeof(chan->pgraph_ctx));
 
 	/* per channel init from ddx */
 	tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
@@ -663,7 +668,7 @@ int nv10_graph_create_context(struct drm_device *dev, int channel) {
 
 	/* for the first channel init the regs */
 	if (dev_priv->fifo_alloc_count == 0)
-		nv10_graph_load_context(dev, channel);
+		nv10_graph_load_context(chan);
 
 
 	//XXX should be saved/restored for each fifo
@@ -672,7 +677,7 @@ int nv10_graph_create_context(struct drm_device *dev, int channel) {
 	return 0;
 }
 
-void nv10_graph_destroy_context(struct drm_device *dev, int channel)
+void nv10_graph_destroy_context(struct nouveau_channel *chan)
 {
 }
 
diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c
index 1670c527..d397390f 100644
--- a/shared-core/nv20_graph.c
+++ b/shared-core/nv20_graph.c
@@ -29,39 +29,36 @@
 
 #define NV20_GRCTX_SIZE (3529*4)
 
-int nv20_graph_create_context(struct drm_device *dev, int channel) {
-	struct drm_nouveau_private *dev_priv =
-		(struct drm_nouveau_private *)dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
+int nv20_graph_create_context(struct nouveau_channel *chan) {
+	struct drm_device *dev = chan->dev;
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	unsigned int ctx_size = NV20_GRCTX_SIZE;
 	int ret;
 
-	if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, ctx_size, 16,
+	if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16,
 					  NVOBJ_FLAG_ZERO_ALLOC,
 					  &chan->ramin_grctx)))
 		return ret;
 
 	/* Initialise default context values */
-	INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, channel<<24); /* CTX_USER */
+	INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); /* CTX_USER */
 
-	INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel,
+	INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id,
 		    chan->ramin_grctx->instance >> 4);
 	return 0;
 }
 
-void nv20_graph_destroy_context(struct drm_device *dev, int channel) {
+void nv20_graph_destroy_context(struct nouveau_channel *chan) {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 
-	if (chan->ramin_grctx)
-		nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx);
+	nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx);
 
-	INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, 0);
+	INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0);
 }
 
 static void nv20_graph_rdi(struct drm_device *dev) {
-	struct drm_nouveau_private *dev_priv =
-		(struct drm_nouveau_private *)dev->dev_private;
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	int i;
 
 	NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000);
@@ -73,13 +70,12 @@ static void nv20_graph_rdi(struct drm_device *dev) {
 
 /* Save current context (from PGRAPH) into the channel's context
  */
-int nv20_graph_save_context(struct drm_device *dev, int channel) {
-	struct drm_nouveau_private *dev_priv =
-		(struct drm_nouveau_private *)dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
+int nv20_graph_save_context(struct nouveau_channel *chan) {
+	struct drm_device *dev = chan->dev;
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	uint32_t instance;
 
-	instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel);
+	instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, chan->id);
 	if (!instance) {
 		return -EINVAL;
 	}
@@ -94,20 +90,19 @@ int nv20_graph_save_context(struct drm_device *dev, int channel) {
 
 /* Restore the context for a specific channel into PGRAPH
  */
-int nv20_graph_load_context(struct drm_device *dev, int channel) {
-	struct drm_nouveau_private *dev_priv =
-		(struct drm_nouveau_private *)dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
+int nv20_graph_load_context(struct nouveau_channel *chan) {
+	struct drm_device *dev = chan->dev;
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	uint32_t instance;
 
-	instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel);
+	instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, chan->id);
 	if (!instance) {
 		return -EINVAL;
 	}
 	if (instance != (chan->ramin_grctx->instance >> 4))
 		DRM_ERROR("nv20_graph_load_context_current : bad instance\n");
 
-	NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24);
+	NV_WRITE(NV10_PGRAPH_CTX_USER, chan->id << 24);
 	NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance);
 	NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 1 /* restore ctx */);
 	return 0;
@@ -116,27 +111,32 @@ int nv20_graph_load_context(struct drm_device *dev, int channel) {
 void nouveau_nv20_context_switch(struct drm_device *dev)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	int channel, channel_old;
+	struct nouveau_channel *next, *last;
+	int chid;
+
+	chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
+	next = dev_priv->fifos[chid];
 
-	channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
-	channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
+	chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
+	last = dev_priv->fifos[chid];
 
-	DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel);
+	DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",
+		  last->id, next->id);
 
 	NV_WRITE(NV04_PGRAPH_FIFO,0x0);
 
-	nv20_graph_save_context(dev, channel_old);
+	nv20_graph_save_context(last);
 	
 	nouveau_wait_for_idle(dev);
 
 	NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000000);
 
-	nv20_graph_load_context(dev, channel);
+	nv20_graph_load_context(next);
 
 	nouveau_wait_for_idle(dev);
 	
-	if ((NV_READ(NV10_PGRAPH_CTX_USER) >> 24) != channel)
-		DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", channel, NV_READ(NV10_PGRAPH_CTX_USER) >> 24);
+	if ((NV_READ(NV10_PGRAPH_CTX_USER) >> 24) != next->id)
+		DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", next->id, NV_READ(NV10_PGRAPH_CTX_USER) >> 24);
 
 	NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
 	NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
@@ -157,7 +157,7 @@ int nv20_graph_init(struct drm_device *dev) {
 
 	/* Create Context Pointer Table */
 	dev_priv->ctx_table_size = 32 * 4;
-	if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0,
+	if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0,
 					  dev_priv->ctx_table_size, 16,
 					  NVOBJ_FLAG_ZERO_ALLOC,
 					  &dev_priv->ctx_table)))
diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c
index 4ed2e2ba..c605c84e 100644
--- a/shared-core/nv30_graph.c
+++ b/shared-core/nv30_graph.c
@@ -100,11 +100,10 @@ static void nv30_graph_context_init(struct drm_device *dev, struct nouveau_gpuob
 }
 
 
-int nv30_graph_create_context(struct drm_device *dev, int channel)
+int nv30_graph_create_context(struct nouveau_channel *chan)
 {
-	struct drm_nouveau_private *dev_priv =
-		(struct drm_nouveau_private *)dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
+	struct drm_device *dev = chan->dev;
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *);
 	unsigned int ctx_size;
 	int ret;
@@ -116,7 +115,7 @@ int nv30_graph_create_context(struct drm_device *dev, int channel)
 		break;
 	}
 
-	if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, ctx_size, 16,
+	if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16,
 					  NVOBJ_FLAG_ZERO_ALLOC,
 					  &chan->ramin_grctx)))
 		return ret;
@@ -124,23 +123,22 @@ int nv30_graph_create_context(struct drm_device *dev, int channel)
 	/* Initialise default context values */
 	ctx_init(dev, chan->ramin_grctx->gpuobj);
         
-        INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, channel<<24); /* CTX_USER */
-        INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel,
+        INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); /* CTX_USER */
+        INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id,
 		    chan->ramin_grctx->instance >> 4);
 
 	return 0;
 }
 
-void nv30_graph_destroy_context(struct drm_device *dev, int channel)
+void nv30_graph_destroy_context(struct nouveau_channel *chan)
 {
-	struct drm_nouveau_private *dev_priv =
-		(struct drm_nouveau_private *)dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
+	struct drm_device *dev = chan->dev;
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
 	if (chan->ramin_grctx)
 		nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx);
 
-	INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, 0);
+	INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0);
 }
 
 static int
@@ -161,10 +159,10 @@ nouveau_graph_wait_idle(struct drm_device *dev)
 	return 0;
 }
 
-int nv30_graph_load_context(struct drm_device *dev, int channel)
+int nv30_graph_load_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	uint32_t inst;
 
 	if (!chan->ramin_grctx)
@@ -178,10 +176,10 @@ int nv30_graph_load_context(struct drm_device *dev, int channel)
 	return nouveau_graph_wait_idle(dev);
 }
 
-int nv30_graph_save_context(struct drm_device *dev, int channel)
+int nv30_graph_save_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	uint32_t inst;
 
 	if (!chan->ramin_grctx)
@@ -197,8 +195,7 @@ int nv30_graph_save_context(struct drm_device *dev, int channel)
 
 int nv30_graph_init(struct drm_device *dev)
 {
-	struct drm_nouveau_private *dev_priv =
-		(struct drm_nouveau_private *)dev->dev_private;
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	uint32_t vramsz, tmp;
 	int ret, i;
 
@@ -209,7 +206,7 @@ int nv30_graph_init(struct drm_device *dev)
 
         /* Create Context Pointer Table */
         dev_priv->ctx_table_size = 32 * 4;
-	if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0,
+	if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0,
 					  dev_priv->ctx_table_size, 16,
 					  NVOBJ_FLAG_ZERO_ALLOC,
 					  &dev_priv->ctx_table)))
diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c
index ecb1d21e..f04c2882 100644
--- a/shared-core/nv40_fifo.c
+++ b/shared-core/nv40_fifo.c
@@ -37,13 +37,13 @@
 #define NV40_RAMFC__SIZE 128
 
 int
-nv40_fifo_create_context(struct drm_device *dev, int channel)
+nv40_fifo_create_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	int ret;
 
-	if ((ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(channel),
+	if ((ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id),
 						NV40_RAMFC__SIZE,
 						NVOBJ_FLAG_ZERO_ALLOC |
 						NVOBJ_FLAG_ZERO_FREE,
@@ -68,27 +68,27 @@ nv40_fifo_create_context(struct drm_device *dev, int channel)
 	RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF);
 
 	/* enable the fifo dma operation */
-	NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<channel));
+	NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<chan->id));
 	return 0;
 }
 
 void
-nv40_fifo_destroy_context(struct drm_device *dev, int channel)
+nv40_fifo_destroy_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 
-	NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<channel));
+	NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
 
 	if (chan->ramfc)
 		nouveau_gpuobj_ref_del(dev, &chan->ramfc);
 }
 
 int
-nv40_fifo_load_context(struct drm_device *dev, int channel)
+nv40_fifo_load_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	uint32_t tmp, tmp2;
 
 	NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET          , RAMFC_RD(DMA_GET));
@@ -135,7 +135,7 @@ nv40_fifo_load_context(struct drm_device *dev, int channel)
 	NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, tmp);
 
 	/* Set channel active, and in DMA mode */
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH1  , 0x00010000 | channel);
+	NV_WRITE(NV03_PFIFO_CACHE1_PUSH1  , 0x00010000 | chan->id);
 	/* Reset DMA_CTL_AT_INFO to INVALID */
 	tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
 	NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
@@ -144,10 +144,10 @@ nv40_fifo_load_context(struct drm_device *dev, int channel)
 }
 
 int
-nv40_fifo_save_context(struct drm_device *dev, int channel)
+nv40_fifo_save_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	uint32_t tmp;
 
 	RAMFC_WR(DMA_PUT          , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c
index 441dbae7..c79b63cc 100644
--- a/shared-core/nv40_graph.c
+++ b/shared-core/nv40_graph.c
@@ -1224,11 +1224,10 @@ nv4e_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
 }
 
 int
-nv40_graph_create_context(struct drm_device *dev, int channel)
+nv40_graph_create_context(struct nouveau_channel *chan)
 {
-	struct drm_nouveau_private *dev_priv =
-		(struct drm_nouveau_private *)dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
+	struct drm_device *dev = chan->dev;
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *);
 	unsigned int ctx_size;
 	int ret;
@@ -1272,7 +1271,7 @@ nv40_graph_create_context(struct drm_device *dev, int channel)
 		break;
 	}
 
-	if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, ctx_size, 16,
+	if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16,
 					  NVOBJ_FLAG_ZERO_ALLOC,
 					  &chan->ramin_grctx)))
 		return ret;
@@ -1284,13 +1283,9 @@ nv40_graph_create_context(struct drm_device *dev, int channel)
 }
 
 void
-nv40_graph_destroy_context(struct drm_device *dev, int channel)
+nv40_graph_destroy_context(struct nouveau_channel *chan)
 {
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
-
-	if (chan->ramin_grctx)
-		nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx);
+	nouveau_gpuobj_ref_del(chan->dev, &chan->ramin_grctx);
 }
 
 static int
@@ -1327,10 +1322,9 @@ nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
  *XXX: fails sometimes, not sure why..
  */
 int
-nv40_graph_save_context(struct drm_device *dev, int channel)
+nv40_graph_save_context(struct nouveau_channel *chan)
 {
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
+	struct drm_device *dev = chan->dev;
 	uint32_t inst;
 
 	if (!chan->ramin_grctx)
@@ -1344,10 +1338,10 @@ nv40_graph_save_context(struct drm_device *dev, int channel)
  * XXX: fails sometimes.. not sure why
  */
 int
-nv40_graph_load_context(struct drm_device *dev, int channel)
+nv40_graph_load_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	uint32_t inst;
 	int ret;
 
diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c
index f7b98220..a5e79260 100644
--- a/shared-core/nv50_fifo.c
+++ b/shared-core/nv50_fifo.c
@@ -63,7 +63,7 @@ static int
 nv50_fifo_channel_enable(struct drm_device *dev, int channel)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
+	struct nouveau_channel *chan = dev_priv->fifos[channel];
 
 	DRM_DEBUG("ch%d\n", channel);
 
@@ -150,7 +150,7 @@ nv50_fifo_init_regs(struct drm_device *dev)
 
 	DRM_DEBUG("\n");
 
-	if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, 0x1000,
+	if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 0x1000,
 					  0x1000,
 					  NVOBJ_FLAG_ZERO_ALLOC |
 					  NVOBJ_FLAG_ZERO_FREE,
@@ -191,7 +191,7 @@ nv50_fifo_init(struct drm_device *dev)
 
 	nv50_fifo_init_reset(dev);
 
-	if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, (128+2)*4, 0x1000,
+	if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, (128+2)*4, 0x1000,
 				   NVOBJ_FLAG_ZERO_ALLOC,
 				   &priv->thingo))) {
 		DRM_ERROR("error creating thingo: %d\n", ret);
@@ -225,14 +225,14 @@ nv50_fifo_takedown(struct drm_device *dev)
 }
 
 int
-nv50_fifo_create_context(struct drm_device *dev, int channel)
+nv50_fifo_create_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	struct nouveau_gpuobj *ramfc = NULL;
 	int ret;
 
-	DRM_DEBUG("ch%d\n", channel);
+	DRM_DEBUG("ch%d\n", chan->id);
 
 	if (IS_G80) {
 		uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start;
@@ -242,7 +242,7 @@ nv50_fifo_create_context(struct drm_device *dev, int channel)
 						   &ramfc, &chan->ramfc)))
 				return ret;
 	} else {
-		if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, 0x100,
+		if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 0x100,
 						  256,
 						  NVOBJ_FLAG_ZERO_ALLOC |
 						  NVOBJ_FLAG_ZERO_FREE,
@@ -266,15 +266,15 @@ nv50_fifo_create_context(struct drm_device *dev, int channel)
 	INSTANCE_WR(ramfc, 0x4c/4, chan->pushbuf_mem->size - 1);
 
 	if (!IS_G80) {
-		INSTANCE_WR(chan->ramin->gpuobj, 0, channel);
+		INSTANCE_WR(chan->ramin->gpuobj, 0, chan->id);
 		INSTANCE_WR(chan->ramin->gpuobj, 1, chan->ramfc->instance);
 
 		INSTANCE_WR(ramfc, 0x88/4, 0x3d520); /* some vram addy >> 10 */
 		INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12);
 	}
 
-	if ((ret = nv50_fifo_channel_enable(dev, channel))) {
-		DRM_ERROR("error enabling ch%d: %d\n", channel, ret);
+	if ((ret = nv50_fifo_channel_enable(dev, chan->id))) {
+		DRM_ERROR("error enabling ch%d: %d\n", chan->id, ret);
 		nouveau_gpuobj_ref_del(dev, &chan->ramfc);
 		return ret;
 	}
@@ -283,25 +283,24 @@ nv50_fifo_create_context(struct drm_device *dev, int channel)
 }
 
 void
-nv50_fifo_destroy_context(struct drm_device *dev, int channel)
+nv50_fifo_destroy_context(struct nouveau_channel *chan)
 {
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
+	struct drm_device *dev = chan->dev;
 
-	DRM_DEBUG("ch%d\n", channel);
+	DRM_DEBUG("ch%d\n", chan->id);
 
-	nv50_fifo_channel_disable(dev, channel, 0);
+	nv50_fifo_channel_disable(dev, chan->id, 0);
 	nouveau_gpuobj_ref_del(dev, &chan->ramfc);
 }
 
 int
-nv50_fifo_load_context(struct drm_device *dev, int channel)
+nv50_fifo_load_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	struct nouveau_gpuobj *ramfc = chan->ramfc->gpuobj;
 
-	DRM_DEBUG("ch%d\n", channel);
+	DRM_DEBUG("ch%d\n", chan->id);
 
 	/*XXX: incomplete, only touches the regs that NV does */
 
@@ -319,14 +318,14 @@ nv50_fifo_load_context(struct drm_device *dev, int channel)
 		NV_WRITE(0x3410, INSTANCE_RD(ramfc, 0x98/4));
 	}
 
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, channel | (1<<16));
+	NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16));
 	return 0;
 }
 
 int
-nv50_fifo_save_context(struct drm_device *dev, int channel)
+nv50_fifo_save_context(struct nouveau_channel *chan)
 {
-	DRM_DEBUG("ch%d\n", channel);
+	DRM_DEBUG("ch%d\n", chan->id);
 	DRM_ERROR("stub!\n");
 	return 0;
 }
diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c
index 8df5df25..59c8cfeb 100644
--- a/shared-core/nv50_graph.c
+++ b/shared-core/nv50_graph.c
@@ -188,17 +188,17 @@ nv50_graph_takedown(struct drm_device *dev)
 }
 
 int
-nv50_graph_create_context(struct drm_device *dev, int channel)
+nv50_graph_create_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
 	int grctx_size = 0x60000, hdr;
 	int ret;
 
-	DRM_DEBUG("ch%d\n", channel);
+	DRM_DEBUG("ch%d\n", chan->id);
 
-	if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0,
+	if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0,
 					  grctx_size, 0x1000,
 					  NVOBJ_FLAG_ZERO_ALLOC |
 					  NVOBJ_FLAG_ZERO_FREE,
@@ -218,13 +218,13 @@ nv50_graph_create_context(struct drm_device *dev, int channel)
 }
 
 void
-nv50_graph_destroy_context(struct drm_device *dev, int channel)
+nv50_graph_destroy_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	int i, hdr;
 
-	DRM_DEBUG("ch%d\n", channel);
+	DRM_DEBUG("ch%d\n", chan->id);
 
 	hdr = IS_G80 ? 0x200 : 0x20;
 	for (i=hdr; i<hdr+24; i+=4)
@@ -266,14 +266,14 @@ nv50_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
 }
 
 int
-nv50_graph_load_context(struct drm_device *dev, int channel)
+nv50_graph_load_context(struct nouveau_channel *chan)
 {
+	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
 	uint32_t inst = ((chan->ramin->instance >> 12) | (1<<31));
 	int ret; (void)ret;
 
-	DRM_DEBUG("ch%d\n", channel);
+	DRM_DEBUG("ch%d\n", chan->id);
 
 #if 0
 	if ((ret = nv50_graph_transfer_context(dev, inst, 0)))
@@ -288,13 +288,12 @@ nv50_graph_load_context(struct drm_device *dev, int channel)
 }
 
 int
-nv50_graph_save_context(struct drm_device *dev, int channel)
+nv50_graph_save_context(struct nouveau_channel *chan)
 {
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_fifo *chan = dev_priv->fifos[channel];
+	struct drm_device *dev = chan->dev;
 	uint32_t inst = ((chan->ramin->instance >> 12) | (1<<31));
 
-	DRM_DEBUG("ch%d\n", channel);
+	DRM_DEBUG("ch%d\n", chan->id);
 
 	return nv50_graph_transfer_context(dev, inst, 1);
 }