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authorMichel Daenzer <michel@daenzer.net>2003-02-04 19:20:18 +0000
committerMichel Daenzer <michel@daenzer.net>2003-02-04 19:20:18 +0000
commit73bf29a6c14d12f86fbce48f6f6bace0de6732a6 (patch)
treecb8b57d77440eef5b07ffe67aa671865d47aca37
parentf13af50838a2a207269ef46c3561ca1250dc6c12 (diff)
fix PCI and AGP posting problems (based on testing by Chris Ison and
suggestions by Benjamin Herrenschmidt and Arjan van de Ven) remove radeon_flush_write_combine() which has been unused for a while
-rw-r--r--shared-core/radeon_drv.h16
-rw-r--r--shared/radeon_drv.h16
2 files changed, 14 insertions, 18 deletions
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 22c5d04f..fb8fbafe 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -824,13 +824,6 @@ do { \
* Ring control
*/
-#if defined(__powerpc__)
-#define radeon_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring )
-#else
-#define radeon_flush_write_combine() DRM_WRITEMEMORYBARRIER()
-#endif
-
-
#define RADEON_VERBOSE 0
#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
@@ -864,8 +857,13 @@ do { \
dev_priv->ring.tail = write; \
} while (0)
-#define COMMIT_RING() do { \
- RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
+#define COMMIT_RING() do { \
+ /* Flush writes to ring */ \
+ DRM_READMEMORYBARRIER(); \
+ GET_RING_HEAD( &dev_priv->ring ); \
+ RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
+ /* read from PCI bus to ensure correct posting */ \
+ RADEON_READ( RADEON_CP_RB_RPTR ); \
} while (0)
#define OUT_RING( x ) do { \
diff --git a/shared/radeon_drv.h b/shared/radeon_drv.h
index 22c5d04f..fb8fbafe 100644
--- a/shared/radeon_drv.h
+++ b/shared/radeon_drv.h
@@ -824,13 +824,6 @@ do { \
* Ring control
*/
-#if defined(__powerpc__)
-#define radeon_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring )
-#else
-#define radeon_flush_write_combine() DRM_WRITEMEMORYBARRIER()
-#endif
-
-
#define RADEON_VERBOSE 0
#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
@@ -864,8 +857,13 @@ do { \
dev_priv->ring.tail = write; \
} while (0)
-#define COMMIT_RING() do { \
- RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
+#define COMMIT_RING() do { \
+ /* Flush writes to ring */ \
+ DRM_READMEMORYBARRIER(); \
+ GET_RING_HEAD( &dev_priv->ring ); \
+ RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
+ /* read from PCI bus to ensure correct posting */ \
+ RADEON_READ( RADEON_CP_RB_RPTR ); \
} while (0)
#define OUT_RING( x ) do { \