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authorBen Skeggs <skeggsb@gmail.com>2007-08-15 00:56:24 +1000
committerBen Skeggs <skeggsb@gmail.com>2007-08-15 01:04:41 +1000
commit02c4e0e757b69cd6ae38b8ab2c078b3f06fea661 (patch)
treefd1a71ecb661b7f491428777c6bbce74b1511e54
parent3ee211f4f7435792752c1dbcd3a60e2e7abfba09 (diff)
nouveau/nv40: Fix channel scheduling.
Ensure NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLE gets set, otherwise channels will appear to "freeze" in some circumstances.
-rw-r--r--shared-core/nouveau_drv.h1
-rw-r--r--shared-core/nouveau_state.c2
-rw-r--r--shared-core/nv40_fifo.c13
3 files changed, 15 insertions, 1 deletions
diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h
index e3d0ff4c..b7459b1b 100644
--- a/shared-core/nouveau_drv.h
+++ b/shared-core/nouveau_drv.h
@@ -455,6 +455,7 @@ extern int nv10_fifo_load_context(struct nouveau_channel *);
extern int nv10_fifo_save_context(struct nouveau_channel *);
/* nv40_fifo.c */
+extern int nv40_fifo_init(struct drm_device *);
extern int nv40_fifo_create_context(struct nouveau_channel *);
extern void nv40_fifo_destroy_context(struct nouveau_channel *);
extern int nv40_fifo_load_context(struct nouveau_channel *);
diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c
index eac38060..d885f7c6 100644
--- a/shared-core/nouveau_state.c
+++ b/shared-core/nouveau_state.c
@@ -224,7 +224,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->graph.destroy_context = nv40_graph_destroy_context;
engine->graph.load_context = nv40_graph_load_context;
engine->graph.save_context = nv40_graph_save_context;
- engine->fifo.init = nouveau_fifo_init;
+ engine->fifo.init = nv40_fifo_init;
engine->fifo.takedown = nouveau_stub_takedown;
engine->fifo.create_context = nv40_fifo_create_context;
engine->fifo.destroy_context = nv40_fifo_destroy_context;
diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c
index eb160ee2..ce3f8fdd 100644
--- a/shared-core/nv40_fifo.c
+++ b/shared-core/nv40_fifo.c
@@ -193,3 +193,16 @@ nv40_fifo_save_context(struct nouveau_channel *chan)
return 0;
}
+int
+nv40_fifo_init(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ int ret;
+
+ if ((ret = nouveau_fifo_init(dev)))
+ return ret;
+
+ NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff);
+ return 0;
+}
+