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authorMichel Dänzer <michel.daenzer@amd.com>2013-11-14 16:40:30 +0100
committerMarek Olšák <marek.olsak@amd.com>2013-11-23 00:35:34 +0100
commitce8af454259279c14c44bcd32c429640ca5e1691 (patch)
treee63d2c5bcbf4c25a38b4c3861d3032d4e4fbbb68 /radeon
parent0c3fd8708fc54b4b46f5db20d34eb29508537b08 (diff)
radeon: fix mipmap level 0 and 1 alignment for SI and CIK
Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'radeon')
-rw-r--r--radeon/radeon_surface.c22
1 files changed, 12 insertions, 10 deletions
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index c663999e..c6aefc15 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -1541,6 +1541,7 @@ static int si_surface_init_1d(struct radeon_surface_manager *surf_man,
uint64_t offset, unsigned start_level)
{
uint32_t xalign, yalign, zalign, slice_align;
+ unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes);
unsigned i;
/* compute alignment */
@@ -1552,11 +1553,11 @@ static int si_surface_init_1d(struct radeon_surface_manager *surf_man,
xalign = MAX2((bpe == 1) ? 64 : 32, xalign);
}
- if (!start_level) {
- surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
+ if (start_level <= 1) {
+ surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
if (offset) {
- offset = ALIGN(offset, surf->bo_alignment);
+ offset = ALIGN(offset, alignment);
}
}
@@ -1567,7 +1568,7 @@ static int si_surface_init_1d(struct radeon_surface_manager *surf_man,
/* level0 and first mipmap need to have alignment */
offset = surf->bo_size;
if ((i == 0)) {
- offset = ALIGN(offset, surf->bo_alignment);
+ offset = ALIGN(offset, alignment);
}
if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
if (surf->level == level) {
@@ -1609,6 +1610,7 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man,
uint64_t offset,
unsigned start_level)
{
+ uint64_t aligned_offset = offset;
unsigned tilew, tileh, tileb;
unsigned mtilew, mtileh, mtileb;
unsigned slice_pt;
@@ -1632,19 +1634,19 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man,
/* macro tile bytes */
mtileb = (mtilew / tilew) * (mtileh / tileh) * tileb;
- if (!start_level) {
+ if (start_level <= 1) {
unsigned alignment = MAX2(256, mtileb);
surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
- if (offset) {
- offset = ALIGN(offset, alignment);
+ if (aligned_offset) {
+ aligned_offset = ALIGN(aligned_offset, alignment);
}
}
/* build mipmap tree */
for (i = start_level; i <= surf->last_level; i++) {
level[i].mode = RADEON_SURF_MODE_2D;
- si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, offset);
+ si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, aligned_offset);
if (level[i].mode == RADEON_SURF_MODE_1D) {
switch (tile_mode) {
case SI_TILE_MODE_COLOR_2D_8BPP:
@@ -1669,9 +1671,9 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man,
return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
}
/* level0 and first mipmap need to have alignment */
- offset = surf->bo_size;
+ aligned_offset = surf->bo_size;
if ((i == 0)) {
- offset = ALIGN(offset, surf->bo_alignment);
+ aligned_offset = ALIGN(aligned_offset, surf->bo_alignment);
}
if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
if (surf->level == level) {