From f8d44600b775ffdce8be566c9c5764022ef2c3dc Mon Sep 17 00:00:00 2001 From: mstsirkin Date: Wed, 21 Oct 2015 14:20:27 +0000 Subject: pci: clarify configuration access capability rules The point of the configuration access capability is to enable access to other capabilities. The intent never was to allow writes to a random place within device BARs. Limiting drivers simplifies devices - and devices can always add another capability if drivers ever want to access some other range. This resolves VIRTIO-145. Cc: Gerd Hoffmann Signed-off-by: Michael S. Tsirkin Accepted by electronic ballot: https://www.oasis-open.org/apps/org/workgroup/virtio/ballot.php?id=2865 git-svn-id: https://tools.oasis-open.org/version-control/svn/virtio/branches/v1.0@547 0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652 --- content.tex | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/content.tex b/content.tex index e054919..941daa6 100644 --- a/content.tex +++ b/content.tex @@ -1132,6 +1132,7 @@ The virtio device configuration layout includes several structures: \item Notifications \item ISR Status \item Device-specific configuration (optional) +\item PCI configuration access \end{itemize} Each structure can be mapped by a Base Address register (BAR) belonging to @@ -1578,6 +1579,12 @@ at BAR selected by \field{cap.bar} and store the first \field{cap.length} bytes The driver MUST NOT write a \field{cap.offset} which is not a multiple of \field{cap.length} (ie. all accesses MUST be aligned). +The driver MUST NOT read or write \field{pci_cfg_data} +unless \field{cap.bar}, \field{cap.length} and \field{cap.offset} +address \field{cap.length} bytes within a BAR range +specified by some other Virtio Structure PCI Capability +of type other than \field{VIRTIO_PCI_CAP_PCI_CFG}. + \subsubsection{Legacy Interfaces: A Note on PCI Device Layout}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Legacy Interfaces: A Note on PCI Device Layout} Transitional devices MUST present part of configuration -- cgit v1.2.3