From 25665bb2f282d39d0ff34fee96a55e484b198fd7 Mon Sep 17 00:00:00 2001
From: rusty <rusty@0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652>
Date: Mon, 10 Feb 2014 10:33:25 +0000
Subject: patch feedback-8-7.patch

git-svn-id: https://tools.oasis-open.org/version-control/svn/virtio@223 0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652
---
 content.tex | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/content.tex b/content.tex
index 69f11a6..de24746 100644
--- a/content.tex
+++ b/content.tex
@@ -843,7 +843,13 @@ MUST access each field using the “natural” access method (i.e. 32-bit access
 
 \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / Virtio Structure PCI Capabilities}
 
-The virtio device configuration layout includes a common configuration structure, the notification area, ISR status register and a device-specific configuration registers.
+The virtio device configuration layout includes several structures:
+\begin{item}
+\item Common configuration
+\item Notifications
+\item ISR Status
+\item Device-specific configuration (optional)
+\end{item}
 
 Each structure can be mapped by a Base Address register (BAR) belonging to
 the function, or accessed via the special VIRTIO_PCI_CAP_PCI_CFG field in the PCI configuration space.
-- 
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