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@@ -838,10 +838,7 @@ any Revision ID value.
The device is configured via I/O and/or memory regions (though see
\ref{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / PCI configuration access capability}
-for access via the PCI configuration space).
-
-These regions contain the virtio header registers, the notification register, the
-ISR status register and device specific registers, as specified by Virtio
+for access via the PCI configuration space), as specified by Virtio
Structure PCI Capabilities.
Fields of different sizes are present in the device