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| author | rusty <rusty@0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652> | 2014-02-10 10:33:05 +0000 |
|---|---|---|
| committer | rusty <rusty@0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652> | 2014-02-10 10:33:05 +0000 |
| commit | b60e6fee3a1f457930e3978ded317608d71de052 (patch) | |
| tree | 2fdfcf56b4be85bfe2827a044a5a34d5d26f7fda | |
| parent | 173247e46945475ac9ddf2ed8d286d685a971d80 (diff) | |
patch feedback-8-6.patch
git-svn-id: https://tools.oasis-open.org/version-control/svn/virtio@222 0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652
| -rw-r--r-- | content.tex | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/content.tex b/content.tex index 1a86bf9..69f11a6 100644 --- a/content.tex +++ b/content.tex @@ -1094,7 +1094,13 @@ Queue Notify address. \subsubsection{ISR status capability}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / ISR status capability} The device MUST present at least one VIRTIO_PCI_CAP_ISR_CFG capability. This -refers to at least a single byte, which contains the 8-bit ISR status field. +refers to at least a single byte, which contains the 8-bit ISR status field: +\begin{lstlisting} +#define VIRTIO_PCI_ISR_VQ 0x1 +#define VIRTIO_PCI_ISR_CONFIG 0x2 +\end{lstlisting} + +See sections \ref{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Virtqueue Interrupts From The Device} and \ref{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Notification of Device Configuration Changes} for how this is used. \subsubsection{Device specific structure}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Device specific structure} |