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authorrusty <rusty@0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652>2014-02-10 10:32:09 +0000
committerrusty <rusty@0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652>2014-02-10 10:32:09 +0000
commit4f1ad91ad08eb408b04565b59b67f319870593f4 (patch)
treeb7636abc3471f103f98a77e31c20c785e39eef17
parent261e83f3478c58327444d88db755444659f30574 (diff)
We'll add more non-normative sections with hints for
implementing registers such as PCI class, status and command registers. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> git-svn-id: https://tools.oasis-open.org/version-control/svn/virtio@219 0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652
-rw-r--r--content.tex11
-rw-r--r--introduction.tex12
2 files changed, 23 insertions, 0 deletions
diff --git a/content.tex b/content.tex
index bc53749..05cbac8 100644
--- a/content.tex
+++ b/content.tex
@@ -799,6 +799,17 @@ into virtio general and bus-specific sections.
Virtio devices are commonly implemented as PCI devices.
+A Virtio device can be implemented as any kind of PCI device:
+a Conventional PCI device, a PCI-X device or a PCI Express
+device. A Virtio device using Virtio Over PCI Bus MUST expose to
+guest an interface that meets the specification requirements of
+the appropriate PCI specification: \hyperref[intro:PCI]{[PCI]},
+\hyperref[intro:PCI-X]{[PCI-X]} and \hyperref[intro:PCIe]{[PCIe]}
+respectively. To assure designs meet the latest level
+requirements, designers of Virtio Over PCI devices must refer to
+the PCI-SIG home page at \url{http://www.pcisig.com} for any
+approved changes.
+
\subsection{PCI Device Discovery}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Discovery}
Any PCI device with Vendor ID 0x1AF4, and Device ID 0x1000 through
diff --git a/introduction.tex b/introduction.tex
index 8e08d02..745fabf 100644
--- a/introduction.tex
+++ b/introduction.tex
@@ -43,6 +43,18 @@ The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "S
\phantomsection\label{intro:rfc2119}\textbf{[RFC2119]} & S. Bradner, Key words for use in RFCs to Indicate Requirement Levels, \newline\url{http://www.ietf.org/rfc/rfc2119.txt}, March 1997\\
\phantomsection\label{intro:S390 PoP}\textbf{[S390 PoP]} & z/Architecture Principles of Operation, \newline IBM Publication SA22-7832\\
\phantomsection\label{intro:S390 Common I/O}\textbf{[S390 Common I/O]} & ESA/390 Common I/O-Device and Self-Description, \newline IBM Publication SA22-7204\\
+ \phantomsection\label{intro:PCI}\textbf{[PCI]} &
+ Conventional PCI Specifications,
+ \newline\url{http://www.pcisig.com/specifications/conventional/},
+ PCI-SIG\\
+ \phantomsection\label{intro:PCI-X}\textbf{[PCI-X]} &
+ PCI-X Specifications,
+ \newline\url{http://www.pcisig.com/specifications/pcix_20/},
+ PCI-SIG\\
+ \phantomsection\label{intro:PCI-X}\textbf{[PCIe]} &
+ PCI Express Specifications
+ \newline\url{http://www.pcisig.com/specifications/pciexpress/},
+ PCI-SIG\\
\end{longtable}
\section{Structure Specifications}