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authormstsirkin <mstsirkin@0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652>2014-03-02 21:36:41 +0000
committermstsirkin <mstsirkin@0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652>2014-03-02 21:36:41 +0000
commit423d24a4f3d7a74cf29e04a562bbe256b041f007 (patch)
treed1d24ed6a4af8d86d8c1b46fc6a5a0b2c660e820
parentdf9e9d2cfeafc4ef98d1216df2160232c25e6124 (diff)
introduction: add link to 0.9.5 specification
Change accepted on VIRTIO TC Meeting, 3 December 2013 this version replaces it, so it's a non normative reference. VIRTIO-69 note: the link is added here but isn't used yet: will be used when we cleanup terminology definitions, by addressing VIRTIO-64 Cc: Patrick Durusau <patrick@durusau.net Signed-off-by: Michael S. Tsirkin <mst@redhat.com> git-svn-id: https://tools.oasis-open.org/version-control/svn/virtio@302 0c8fb4dd-22a2-4bb5-bc14-6c75a5f43652
-rw-r--r--introduction.tex11
1 files changed, 8 insertions, 3 deletions
diff --git a/introduction.tex b/introduction.tex
index 6e2b67f..1091911 100644
--- a/introduction.tex
+++ b/introduction.tex
@@ -79,9 +79,6 @@ To simplify transition and note differences, the following terms are used:
PCI Express Specifications
\newline\url{http://www.pcisig.com/specifications/pciexpress/},
PCI-SIG\\
- \phantomsection\label{intro:Virtio PCI Draft}\textbf{[Virtio PCI Draft]} &
- Virtio PCI Draft Specification
- \newline\url{http://ozlabs.org/~rusty/virtio-spec/virtio-0.9.5.pdf}\\
\phantomsection\label{intro:IEEE 802}\textbf{[IEEE 802]} &
IEEE Standard for Local and Metropolitan Area Networks: Overview and Architecture,
\newline\url{http://standards.ieee.org/about/get/802/802.html},
@@ -95,6 +92,14 @@ To simplify transition and note differences, the following terms are used:
\end{longtable}
+\section{Non-Normative References}
+
+\begin{longtable}{l p{5in}}
+ \phantomsection\label{intro:Virtio PCI Draft}\textbf{[Virtio PCI Draft]} &
+ Virtio PCI Draft Specification
+ \newline\url{http://ozlabs.org/~rusty/virtio-spec/virtio-0.9.5.pdf}\\
+\end{longtable}
+
\section{Structure Specifications}
Many device and driver in-memory structure layouts are documented using