h1. GMSL Configuration The system is composed by three distinct entities, each one configured separately. Their configurations and operating modes are below summarized, along with some points that have to be clarified on each component operations. h2. OV10635 h3. Relevant Pins and Configuration Parameters |_. PIN |_. Function| |FSIN | frame sync input| |VSYNC |vertical sync output| |HREF | horizontal data valid output| |D [9:0]| data pins| |SIOD-SIOC | SCCB interface| h3. VSYNC/HREF Polarities Register 0x4708 = 0x00 0x4708 [2] = HREF Polarity 0x4708 [1] = VSYNC Polarity 0x4708 [0] = PCLK Polarity _The sensor datasheet does not report what bit value corresponds to what; Application note or support from OV may be required_ As default value of 0x4708 register is 0x01, we may assume what is reported in timing diagrams in the sensor manual is respected with inverted pixel clock edge (rising instead of default falling). As the serializer is configured to latch data on the falling PCLK edge, this seems correct, as timing diagram of serializer operations show data are latched on the edge opposite to the one where pixel are emitted by the sensor) h3. Format configuration 0x4300 = 0x3a = UYVY components ordering 0x4605 = 0x08 = 8-bit YUV422 mode h3. Timing diagram !GMSL_Configuration/ov10635_timings.png! *Note* HREF != HSYNC HREF (or DE Data Enable) stays high while valid data are output, for the whole line length. VSYNC pulses at beginning of a new sensor scanout and stays low during the whole frame output duration. h2. MAX9271 Serializer h3. Relevant Pin and Configuration Parameters _LCCEN_: Enable/disable local control channel pins When LCCEN pin is high the serializer operating parameters are configured through register 0x07. Alternatively if LCCEN is low, pin 14/15/22 and 23 values are used to configure the serializer Pull-up to Vdd in RDACM20 configuration: register 0x07 is used to configure the following parameters _DBL_ : Double input mode In single input mode, pixel data are latched to PCLK falling/rising edge and their value stored one at the time in LATCH A to be then serialized on GMSL serial link. In double input mode, pixel data are read at PCLK/2 frequency and stored in LATCH B two at the time to be then serialized on GMSL serial link. Double input mode is required to have the serializer work with higher PCLK frequencies ( in the [33,3 - 100]MHz range in RDACM20). _HEVN_: Enable HS/VS encoding Timing signals generated by the image sensor (VSYNC/HSYNC) are encoded in serial data sent on GSML link. _BWS_: Serial link bus width. 1 = 32bit bus width; 0 = 24bit bus width; _EDC_: Error correction enable/disable _ES_: Specifies if data are latched on rising/falling PCLK edge. 1 = falling edge; 0 = rising edge h3. RDACM20 Configuration |_. Parameter |_. Value| |DBL | 1| |BWS | 0| |HVEN | 1| |EDC | 0| |ES | 1| RDACM20 uses double input mode, with a 24 bit serial link bus width, HSYNC/VSYNC encoding enabled and error correction disabled (one parity bit per word is used). Data are latched on falling PCLK edge and serialized at PCLK/2 frequency as we're using double input mode. The 24 bit encoded on the GMSL serial link are: 
0:21  = 2 * 11 bit pixel data (LATCH B content, or DIN-A + DIN-B in sensor manual)
22 = Forward control channel bit
23 = parity bit
*Note* see Table 2 (input map) because it reports HS and VS signals in DIN-A and DIN-B but they're not part of the data sent on serial link. h3. Serial link data output !GMSL_Configuration/IMG_20170822_214808.jpg! From the serializer manual, same image !GMSL_Configuration/max9271-serialization.png! *Questions* There are some ambiguities in the serializer manual. 1) with HVEN enabled, synchronization signals are said to be encoded in data sent on the serial link. Page 33, _HS/VS Encoding and/or Tracking_ paragraph: 
    HS/VS encoding by a GMSL serializer allows horizontal
    and vertical synchronization signals to be transmitted
    while conserving pixel data bandwidth. With HS/VS
    encoding enabled, 10-bit pixel data with a clock up to
    100MHz can be transmitted using one video pixel of
    data per HS/VS transition, versus 8-bit data with a clock
    up to 100MHz without HS/VS encoding.
From this statement it seems that each time VSYNC/HSYNC is detected (see below for what "detected" means) a special packet containing no pixel data but a "code" to indicate VS/HS is sent on the serial link ("code" as in something "GMSL proprietary" and part of the GSML protocol, not described in serializer/deserializer manual). From MAX9286 de-serializer manual instead, specifically in the HVSRC parameter description, it seems like the de-serializer expects HS/VS encoded in bits 14:15 (or 16:17) of the data sent on the serial link, along with pixel data. Possible answer: According to information provided by the manual of a different Maxim GMSL serializer (MAX96705) [manual[https://datasheets.maximintegrated.com/en/ds/MAX96705.pdf]], when HS/VS encoding is used, a packet with no pixel data but only informations about synchronism signals are sent during blank periods. Alternatively, if no HS/VS encoding is used, 2 bit of pixel data are reserved for HS/VS tracking. This seems to match the "10-bit vs 8-bit" reported in the above quote from serializer manual. 2) The following statement is not clear to me. Page 33, _HS/VS Encoding and/or Tracking_ paragraph 
    HS/VS encoding sends packets when HSYNC or VSYNC is low, use H/V
    inversion register bits if input HSYNC and VSYNC signals
    use an active-low convention to send data packets during the
    inactive pixel clock periods.
It seems from this statement that the serializer expects VSYNC to behave as Data Valid (stay high during the whole frame duration) and low during frame blanking (which is basically the inverted logic compared to what the image sensor does). If this is true, we should receive VSYNC packets during the whole frame duration, but that's not possible, as we actually receive data. Also, VSYNC polarity is inverted on de-serializer side, not on serializer one. Possible answer: The above quote from the serializer manual may be interpreted simply as the confirmation that packets containing encoded HS/VS information (now that another serializer manual confirmed that actual packets are sent for this purpose) are sent on the serial link when the synch signal is low, to guarantee no active pixel data are sent by the sensor during this "inactive" periods (this allows to connect HREF signal to HSYNC, as it happens in rdacm20 configuration). It is legit to assume the encoded HS/VS signals are sent recording transactions of falling and rising edges h3. Synchronism signal timings To be verified in image sensor configuration if the following constraints are respected With DBL=1: * HS/VS low pulse duration >= 5 PCLK cycles * HS/VS high pulse duration >= 2 PCLK cycles * Active duration of HS/VS + Blankings must be an even multiple of PCLK pulses h2. MAX9286 De-Serializer h3. De-serializer Configuration Parameters h3. general configuration Register 0x12 |DBL | 1| |EDC | 0| |BWS |0 (pull down to ground)| h3. FSYNC and VSYNC signal configuration The de-serializer run by default with inverted VSYNC Register 0x0c |HVEN |1| |INVS |1| |HVSRC | 01| FSYNC parameters |_. Parameter |_. Register |_. Bits |_.Default value |_.max9286 setting|_. Comment | |MSTLINKSEL | 0x00 | 7:5 | 111 | 111| Autodetect link used for CSI clock source | |EN_VS_GEN| 0x00 | 4 | 0 | 0 | Disable internal VSYNC (comes from Cameras) | |FSYNCMODE | 0x01 | 7:6 | 00 | 00 | Internally generate FSYNC| |FSYNCMETH | 0x01 | 1:0 | 10 | 10 | Auto mode: fsync follows slowest link | |FSYNC_PERDIV | 0x02 | 7:4 | 0000 | 0000 | FSYNC generated after 1 VSYNC pulse (on slowest link: auto mode) | |KVALSIGN | 0x03 | 4 | 0 | 0 | Positive KVAL value | |KVAL| 0x03 | 3:0 | 0001 | 0001 | 2us margin respect to rising edge of sloweset (auto mode) link | |PVALL|0x04 | 7:0 | 00000000 | 00000000 | Desired margin in PCLK cycles from rising edge of slowest (auto mode) link; Low byte | |PVALH| 0x05 | 4:0 | 0000 | 0000 | Desired margin in PCLK cycles from rising edge of slowest (auto mode) link; High byte | |PVALSIGN| 0x05 | 5 | 0 | 0 | Positive PVAL value | |FRMDIFFTHRL| 0x61 | 7:0 | 0 | 0 | Low byte of error threshold between the earliest and latest VSYNC (in pixel clock cycles) | |FRMDIFFTHRL| 0x62 | 4:0 | 01111 | 01111 | High byte of error threshold between the earliest and latest VSYNC (in pixel clock cycles). Disabled if all 13 bits are 0s| |ENFSINLAST | 0x64 | 5 | 0 | 0 | FSIN occurs anytime between VS rising edges (alternative is: FSIN occurs after all VS rising edges| KVAL and PVAL not configured in max9286 setup :/ The previously values determinate how frame synchronization is performed !GMSL_Configuration/fsync.png! h3. HS/VS location HVSRC parameter description in register 0x0c (page 66) reports that the de-serializer expects HS/VS in bit 14:15 
    Use D14/D15 for HSYNC/VSYNC (D[19:16] shifted to D[17:14]).
    For use with the MAX9271 when DBL = 0 or when HVEN = 1._
The following image describing the input map expected by deserializer for yuv8 format confirms that !GMSL_Configuration/de-serializer-input-map.png! This seems pretty different from what the serializer sends on the serial link, as bit 0:21 are reserved for two 11bit pixel data word, and there is no mention of HS/VS encoding in bits 14:15 (or 16:17). So, HS/VS are either encoded in special packets with no pixel data (something like CSI-2 short packets) or their bits part of the data sent on the serial link along with pixel data (but in that case, it seems all the 24 bits used by the serializer are actually used by two pixel data word) h3. VSYNC inversion The deserializer is configured to run with inverted VSYNC output on CSI bus. See below what it can possibly mean (inversion of short packet vertical synchronization codes?) h2. Open issues and testing A list of open issues and performed testing is reported in the following page a> 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 
/* mga_state.c -- State support for mga g200/g400
 * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
 *
 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 * 
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors: Jeff Hartmann <jhartmann@precisioninsight.com>
 * 	    Keith Whitwell <keithw@precisioninsight.com>
 *
 */

#define __NO_VERSION__
#include "drmP.h"
#include "mga_drv.h"
#include "drm.h"

typedef u_int16_t u16;
typedef u_int32_t u32;

static void mgaEmitClipRect(drm_mga_private_t * dev_priv,
			    drm_clip_rect_t * box)
{
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned int *regs = sarea_priv->ContextState;
	PRIMLOCALS;
	DRM_DEBUG("%s\n", __FUNCTION__);

	/* This takes 10 dwords */
	PRIMGETPTR(dev_priv);

	/* Force reset of dwgctl (eliminates clip disable) */
#if 0
	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_DWGSYNC, 0);
	PRIMOUTREG(MGAREG_DWGSYNC, 0);
	PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]);
#else
	PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]);
	PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0x80000000);
	PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]);
	PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0x80000000);
#endif

	PRIMOUTREG(MGAREG_DMAPAD, 0);
	PRIMOUTREG(MGAREG_CXBNDRY, ((box->x2) << 16) | (box->x1));
	PRIMOUTREG(MGAREG_YTOP, box->y1 * dev_priv->stride / 2);
	PRIMOUTREG(MGAREG_YBOT, box->y2 * dev_priv->stride / 2);

	PRIMADVANCE(dev_priv);
}

static void mgaEmitContext(drm_mga_private_t * dev_priv)
{
	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned int *regs = sarea_priv->ContextState;
	PRIMLOCALS;
	DRM_DEBUG("%s\n", __FUNCTION__);

	/* This takes a max of 15 dwords */
	PRIMGETPTR(dev_priv);

	PRIMOUTREG(MGAREG_DSTORG, regs[MGA_CTXREG_DSTORG]);
	PRIMOUTREG(MGAREG_MACCESS, regs[MGA_CTXREG_MACCESS]);
	PRIMOUTREG(MGAREG_PLNWT, regs[MGA_CTXREG_PLNWT]);
	PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]);

	PRIMOUTREG(MGAREG_ALPHACTRL, regs[MGA_CTXREG_ALPHACTRL]);
	PRIMOUTREG(MGAREG_FOGCOL, regs[MGA_CTXREG_FOGCOLOR]);
	PRIMOUTREG(MGAREG_WFLAG, regs[MGA_CTXREG_WFLAG]);
	PRIMOUTREG(MGAREG_ZORG, dev_priv->depthOffset);	/* invarient */

	if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
		PRIMOUTREG(MGAREG_WFLAG1, regs[MGA_CTXREG_WFLAG]);