Core-chat-meeting-2018-06-07
11:05 < geertu> Welcome to today's (delayed) Core Group Meeting!
11:05 < geertu> Agenda:
11:05 < geertu> 1. Status Updates
11:05 < geertu> 2. Discussion Topics
11:05 < geertu> Topic 1. Status updates
11:05 < geertu> A) What have we done since last time:
11:06 < geertu> Kaneko-san got M3-N thermal support merged.
11:06 < geertu> Kieran is investigating DMAC Virtualisation.
11:06 < geertu> Marek worked on U-Boot (Ebisu, mtdparts) and Linux (DA9063L, PCIe, Gen2
11:06 < geertu> PMIC quirk).
11:06 < geertu> Morimoto-san is happily designing and hacking periject.
11:06 < geertu> Shimoda-san upported USB2.0 PFC for R-Car E3, and discussed M3-W ES1.2
11:06 < geertu> handling.
11:06 < geertu> Ulrich is developing the R-Car Gen3 SoC memory size detection prototype.
11:06 < geertu> Geert revisited vfio PM Domain handling, coached Kieran for virt, played
11:06 < geertu> with Ebisu (upported SMP and WDT), did misc fixes and cleanups, reviews,
11:06 < geertu> and periupport analysis.
11:06 < geertu> B) What we plan to do till next time:
11:06 < geertu> Kaneko-san will upport M3-N WDT support.
11:06 < geertu> Kieran will continue his Virtualisation investigations.
11:06 < geertu> Marek will work on U-Boot (more Ebisu) and ATF (D3/Draak, V3M/Eagle,
11:06 < geertu> V3H/Condor?).
11:06 < geertu> Morimoto-san will enhance periject based on feedback.
11:06 < geertu> Niklas will investigate pinctrl problems on V3M.
11:06 < geertu> Shimoda-san will upport USB3.0 PFC for E3, and pave the way forward for
11:06 < geertu> IPMMU.
11:06 < geertu> Ulrich plans to finish memory size detection.
11:06 < geertu> Geert will handle CPG/MSSR and SYSC errata, and possibly additional tasks.
11:07 < geertu> C) Problems we have currently:
11:07 < geertu> Kieran's DMAC task was scheduled too late to complete before deadline.
11:07 < geertu> Morimoto-san wants more periject feedback.
11:07 < geertu> Ulrich has ATF support issues with Salvator-X H3 ES1.0, and needs ES3.0
11:07 < geertu> remote firmware update facilities.
11:07 < geertu> EOL(ist)
11:08 < geertu> Anything I missed?
11:08 < Marex> geertu: upstreaming the ATF ?
11:08 < pinchartl> geertu: I haven't thought about reporting that
11:08 < pinchartl> but I've also worked with Kieran on DMA virtualization
11:08 < pinchartl> I was going to include it in my multimedia report, but it makes more sense to include it in the core report
11:09 < geertu> Marex: As we're "the upstream team", isn't upstreaming assumed? ;-)
11:09 < dammsan> pinchartl: nice to see you at the core chat =)
11:09 < geertu> pinchartl: Added
11:09 < Marex> geertu: well I mean, there's probably team in Renesas that does the ATF work
11:09 < Marex> geertu: I dont want to step on their toes
11:10 < geertu> Marex: But a good point, for ATF we never explicitly mentioned that
11:10 < Marex> geertu: I can just start the process, which would reduce the amount of patches in meta-renesas
11:10 < Marex> shimoda: morimoto ^
11:10 < Marex> thoughts ?
11:10 < Marex> also, updating the D3 ATF and V3M/V3H ATF sucks
11:10 < Marex> I managed, but it needs testing
11:10 < Marex> if we got that upstream, this problem would go away
11:10 < geertu> Marex: Given there's no plat/master directory in upstream ATF, I doubt the Renesas ATF team is working on upstreaming
11:11 < dammsan> Marex: we might have some key person here at Renesas
11:11 < geertu> s/master/renesas/
11:12 < dammsan> Marex: maybe we can do a f2f meeting when you come to japan?
11:12 < Marex> dammsan: jupp
11:12 < Marex> dammsan: I am open to anything which trims down the amount of patches which we lug around
11:12 < dammsan> we will ask ATF people here to join
11:12 < geertu> dammsan: Good idea.
11:13 < Marex> dammsan: btw any chance on getting V3MSK while in japan ? :)
11:13 < dammsan> not sure, add it to your list of boards you need =)
11:13 < dammsan> and email me
11:14 < geertu> About the problems (C):
11:14 < geertu> The task scheduling has been discussed before this meeting.
11:14 < geertu> I believe Morimoto-san is still waiting for periject feedback from Laurent?
11:14 < Marex> dammsan: done
11:15 < dammsan> thanks
11:15 < morimoto> geertu: laurentu: yes
11:15 < geertu> pinchartl: ^
11:16 < morimoto> s/laurentu/pinchartl/
11:16 < pinchartl> morimoto: I'll read all the pending e-mails and reply
11:16 < morimoto> \me pinchartl always ignored my email...
11:16 < pinchartl> but I wonder whether this shouldn't be tied to the meeting we will have in Tokyo
11:17 < morimoto> pinchartl: OK
11:17 < pinchartl> as planning requires tooling
11:17 < pinchartl> I will still reply to the e-mails as soon as I can
11:18 < geertu> dammsan: For Uli, you just need to add remote MD control to Salvator-X H3 ES3.0, right?
11:18 < uli___> i might not even need that (right away) if your tip about the driver strength turns out to be the (only) issue
11:19 < uli___> then i could prototype the whole thing on my own board
11:19 < geertu> uli___: But eventually, you want to test on the real target, right?
11:19 < uli___> i would, yes
11:20 < geertu> OK
11:20 < geertu> Topic 2. Discussion Topics
11:20 < geertu> Anything we still need to discuss?
11:20 < geertu> Are there explicit core requests from Renesas, or from other groups?
11:21 < wsa_> only this I2C CPG reset issue
11:21 < geertu> wsa_: OK, I still have to reply to that email
11:21 < morimoto> so far, I don't received from BSP team
11:22 < neg> I have a question, is there any conclusion on how we should lable and group DT patches to ease upstream consumption with regard to the recent feedback?
11:22 < dammsan> geertu: yep, on my todo with MD pin control
11:23 < dammsan> geertu: i want paravirtualzied GPIO support at some point! =)
11:25 < geertu> dammsan: Added to peripelist/core/todo
11:25 < dammsan> thanks!!
11:26 < geertu> Anything else to discuss?
11:26 < geertu> Next chat meeting?
11:27 < pinchartl> two weeks from now is during OSSJ
11:27 < geertu> correct
11:28 < geertu> four weeks from now?
11:28 < wsa_> yup
11:28 < pinchartl> that sounds good to mee
11:28 < Marex> pinchartl: I hope this OSSJ is gonna be as awesome as the previous one ;-)
11:28 < morimoto> 5th, july ?
11:29 < geertu> Now, if you're interested in doing a core additional task, please say so before next chat meeting ;-)
11:29 < geertu> s/task/task in Q3/
11:29 < morimoto> awesome T Shirt
11:29 < kbingham> geertu, Well - I don't want to make any assumptions :D
11:30 < pinchartl> geertu: based on the discussion we just had, additional tasks for Q3.1 should be signed on June the 15th
11:30 < pinchartl> so I'd say, please say so before the end of this week
11:31 < geertu> Right.
11:31 < geertu> Time to pass the mic to the MM leader?
11:32 < geertu> Thanks for joining, and have a nice continued day!
/a>
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
/*
*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _INTEL_CHIPSET_H
#define _INTEL_CHIPSET_H
#define PCI_CHIP_I810 0x7121
#define PCI_CHIP_I810_DC100 0x7123
#define PCI_CHIP_I810_E 0x7125
#define PCI_CHIP_I815 0x1132
#define PCI_CHIP_I830_M 0x3577
#define PCI_CHIP_845_G 0x2562
#define PCI_CHIP_I855_GM 0x3582
#define PCI_CHIP_I865_G 0x2572
#define PCI_CHIP_I915_G 0x2582
#define PCI_CHIP_E7221_G 0x258A
#define PCI_CHIP_I915_GM 0x2592
#define PCI_CHIP_I945_G 0x2772
#define PCI_CHIP_I945_GM 0x27A2
#define PCI_CHIP_I945_GME 0x27AE
#define PCI_CHIP_Q35_G 0x29B2
#define PCI_CHIP_G33_G 0x29C2
#define PCI_CHIP_Q33_G 0x29D2
#define PCI_CHIP_IGD_GM 0xA011
#define PCI_CHIP_IGD_G 0xA001
#define IS_IGDGM(devid) (devid == PCI_CHIP_IGD_GM)
#define IS_IGDG(devid) (devid == PCI_CHIP_IGD_G)
#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
#define PCI_CHIP_I965_G 0x29A2
#define PCI_CHIP_I965_Q 0x2992
#define PCI_CHIP_I965_G_1 0x2982
#define PCI_CHIP_I946_GZ 0x2972
#define PCI_CHIP_I965_GM 0x2A02
#define PCI_CHIP_I965_GME 0x2A12
#define PCI_CHIP_GM45_GM 0x2A42
#define PCI_CHIP_IGD_E_G 0x2E02
#define PCI_CHIP_Q45_G 0x2E12
#define PCI_CHIP_G45_G 0x2E22
#define PCI_CHIP_G41_G 0x2E32
#define PCI_CHIP_ILD_G 0x0042
#define PCI_CHIP_ILM_G 0x0046
#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */
#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */
#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
#define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */
#define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */
#define PCI_CHIP_IVYBRIDGE_GT2 0x0162
#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */
#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */
#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
#define PCI_CHIP_HASWELL_GT2 0x0412
#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
#define PCI_CHIP_HASWELL_M_GT2 0x0416
#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
#define PCI_CHIP_HASWELL_S_GT2 0x041A
#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22
#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22
#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */
#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22
#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32
#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */
#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */
#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
#define PCI_CHIP_VALLEYVIEW_1 0x0f31
#define PCI_CHIP_VALLEYVIEW_2 0x0f32
#define PCI_CHIP_VALLEYVIEW_3 0x0f33
#define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \
devid == PCI_CHIP_I915_GM || \
devid == PCI_CHIP_I945_GM || \
devid == PCI_CHIP_I945_GME || \
devid == PCI_CHIP_I965_GM || \
devid == PCI_CHIP_I965_GME || \
devid == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \
devid == PCI_CHIP_IVYBRIDGE_M_GT2)
#define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
devid == PCI_CHIP_Q45_G || \
devid == PCI_CHIP_G45_G || \
devid == PCI_CHIP_G41_G)
#define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM)
#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
#define IS_ILD(devid) (devid == PCI_CHIP_ILD_G)
#define IS_ILM(devid) (devid == PCI_CHIP_ILM_G)
#define IS_915(devid) (devid == PCI_CHIP_I915_G || \
devid == PCI_CHIP_E7221_G || \
devid == PCI_CHIP_I915_GM)
#define IS_945GM(devid) (devid == PCI_CHIP_I945_GM || \
devid == PCI_CHIP_I945_GME)
#define IS_945(devid) (devid == PCI_CHIP_I945_G || \
devid == PCI_CHIP_I945_GM || \
devid == PCI_CHIP_I945_GME || \
IS_G33(devid))
#define IS_G33(devid) (devid == PCI_CHIP_G33_G || \
devid == PCI_CHIP_Q33_G || \
devid == PCI_CHIP_Q35_G || IS_IGD(devid))
#define IS_GEN2(devid) (devid == PCI_CHIP_I830_M || \
devid == PCI_CHIP_845_G || \
devid == PCI_CHIP_I855_GM || \
devid == PCI_CHIP_I865_G)
#define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
#define IS_GEN4(devid) (devid == PCI_CHIP_I965_G || \
devid == PCI_CHIP_I965_Q || \
devid == PCI_CHIP_I965_G_1 || \
devid == PCI_CHIP_I965_GM || \
devid == PCI_CHIP_I965_GME || \
devid == PCI_CHIP_I946_GZ || \
IS_G4X(devid))
#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
#define IS_GEN6(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
devid == PCI_CHIP_SANDYBRIDGE_S)
#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
IS_HASWELL(devid))
#define IS_IVYBRIDGE(dev) (dev == PCI_CHIP_IVYBRIDGE_GT1 || \
dev == PCI_CHIP_IVYBRIDGE_GT2 || \
dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \
dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \
dev == PCI_CHIP_IVYBRIDGE_S || \
dev == PCI_CHIP_IVYBRIDGE_S_GT2 || \
dev == PCI_CHIP_VALLEYVIEW_PO)
#define IS_VALLEYVIEW(dev) (((dev) == PCI_CHIP_VALLEYVIEW_PO) || \
((dev) == PCI_CHIP_VALLEYVIEW_1) || \
((dev) == PCI_CHIP_VALLEYVIEW_2) || \
((dev) == PCI_CHIP_VALLEYVIEW_3))
#define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
devid == PCI_CHIP_HASWELL_M_GT1 || \
devid == PCI_CHIP_HASWELL_S_GT1 || \
devid == PCI_CHIP_HASWELL_SDV_GT1 || \
devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
devid == PCI_CHIP_HASWELL_ULT_GT1 || \
devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
devid == PCI_CHIP_HASWELL_CRW_GT1 || \
devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
devid == PCI_CHIP_HASWELL_CRW_S_GT1)
#define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2 || \
devid == PCI_CHIP_HASWELL_M_GT2 || \
devid == PCI_CHIP_HASWELL_S_GT2 || \
devid == PCI_CHIP_HASWELL_SDV_GT2 || \
devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \
devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \
devid == PCI_CHIP_HASWELL_ULT_GT2 || \
devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \
devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
devid == PCI_CHIP_HASWELL_CRW_GT2 || \
devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
devid == PCI_CHIP_HASWELL_GT2_PLUS || \
devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \
devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \
devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
IS_HSW_GT2(devid))
#define IS_9XX(dev) (IS_GEN3(dev) || \
IS_GEN4(dev) || \
IS_GEN5(dev) || \
IS_GEN6(dev) || \
IS_GEN7(dev))
#endif /* _INTEL_CHIPSET_H */
|