Core-chat-meeting-2017-04-11 10:03 < geertu> Welcome to today's Core Group Chat! 10:03 < geertu> Agenda: 10:03 < geertu> 1. Status updates 10:04 < geertu> Topic 1. Status updates 10:04 < geertu> First is Niklas 10:05 < geertu> A) What have I done since last time 10:05 < geertu> B) What I plan to do till next time 10:05 < geertu> C) Problems I have currently 10:05 < geertu> D) Posted/Accepted bugfix patches 10:06 < neg> a) Nothing for core 10:06 < neg> b) Hope to pick something new from core TODO 10:06 < neg> c) None 10:06 < neg> d) None 10:06 < neg> --eot-- 10:07 < geertu> Thank you, Niklas 10:07 < geertu> Next is Jacopo 10:07 < jmondi> let me retreive the email I sent 10:07 < jmondi> A) 10:08 < jmondi> - v4 of RZ pin controller 10:08 < jmondi> - RZ clock tested and enabled on Genmai 10:08 < jmondi> - tested pin controller driver with DT overlays 10:08 < jmondi> - working on using JTAG debugger on Genmai 10:09 < geertu> So it's v4, not v5? 10:09 < jmondi> B) = C) = D) = NULL 10:09 < jmondi> geertu: I wrote v5 in the email, but I got confused 10:09 < jmondi> it's v4 10:09 < jmondi> -- eot -- 10:10 < geertu> Thank you, Jacopo. 10:10 < geertu> Next is Laurent. I assume he's just lurking around? 10:10 < pinchartl> correct 10:10 < pinchartl> I have no core task 10:10 < geertu> Next is Morimoto-san 10:11 < morimoto> A) What have I done since last time 10:11 < morimoto> I posted "SYS-DMAC + 40bit + descriptor mode" patch to ML, and it was accepted. 10:11 < morimoto> I created/fixed periupport script. I hope it is now useful :) 10:11 < morimoto> I updated "R-Car Gen3 datasheet" export paper work (Not related to PeriPeri Member/Task :) 10:11 < morimoto> B) What I plan to do till next time 10:11 < morimoto> C) Problems I have currently 10:11 < morimoto> D) Posted/Accepted bugfix patch 10:11 < morimoto> Nothing for Core group 10:11 < morimoto> --EOT-- 10:12 < geertu> Thank you, Morimoto-san 10:12 < geertu> Next is Magnus 10:12 < dammsan> no update from me, just lurking 10:13 < geertu> Next is myself 10:13 < geertu> A) 10:13 < geertu> - Finished R-Car H3 ES2.0 for clk/pfc/sysc 10:13 < geertu> - R-Car Gen2 CPG/MSSR 10:13 < geertu> - Started DTS sharing on H3 ES1.x/ES2.0, Salvator-X/ULCB 10:13 < geertu> - Some Easter holidays 10:13 < geertu> B) 10:13 < geertu> - More Easter holidays 10:13 < geertu> - Rework drivers/{clk,soc}/renesas/Kconfig 10:13 < geertu> - Publish R-Car Gen2 CPG/MSSR 10:13 < geertu> - DTS sharing 10:13 < geertu> C) None 10:14 < geertu> D) More clock fixes detected during R-Car Gen2 CPG/MSSR conversion: 10:14 < geertu> - [PATCH 1/3] ARM: dts: r8a7790: Correct parent of SSI[0-9] clocks 10:14 < geertu> - [PATCH 2/3] ARM: dts: r8a7791: Correct parent of SSI[0-9] clocks 10:14 < geertu> - [PATCH 3/3] ARM: dts: r8a7793: Correct parent of SSI[0-9] clocks 10:14 < geertu> - [PATCH] ARM: dts: r8a7792: Correct Z clock 10:14 < geertu> - [PATCH] ARM: dts: r8a7794: Add Z2 clock 10:14 < geertu> - [PATCH] ARM: dts: koelsch: Correct clock frequency of X2 DU clock 10:14 < geertu> - [PATCH] clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2 10:14 < geertu> - [PATCH] clk: renesas: r8a7745: Remove nonexisting scu-src[0789] 10:14 < geertu> - [PATCH] clk: renesas: r8a7745: Remove PLL configs for MD19=0 10:14 < geertu> EOT 10:14 < geertu> Next is Shimoda-san 10:14 < shimoda> A) 10:14 < shimoda> - I'm testing a new IPMMU workaround on R-Car H3 ES2.0. 10:14 < shimoda> B) 10:14 < shimoda> - Intend to make some plans about implementing IPMMU features with Magnus-san 10:14 < shimoda> C) and D) 10:15 < shimoda> - Nothing for core. 10:15 < shimoda> -- EOT -- 10:15 < geertu> Thank you, Shimoda-san 10:15 < geertu> Simon is excused, arriving in Kobe. His ABCD are: 10:15 < geertu> A) No Core task at this time 10:15 < geertu> B) No Core task at this time 10:15 < geertu> C) Selecting patches for upporting 10:15 < geertu> D) None 10:16 < geertu> Marek is also excused, he let me know the following: 10:16 < geertu> A) BD9571 MFD, GPIO, and regulator drivers 10:16 < geertu> B) Publish BD9571 drivers 10:16 < geertu> It's been a while I saw Khiem and Uli 10:17 < horms> I assume Khiem has been reassigned 10:18 < geertu> Probably 10:19 < geertu> And his email routed to (the Windows equivalent of) /dev/null 10:19 < geertu> Well, that went smooth! 10:19 < horms> likely 10:19 < geertu> Any other topics to discuss? 10:19 < dammsan> at least it is translated to CR LR before going into NULL 10:19 * horms has arrived in Kobe 10:19 -!- horms [~horms@g1-27-253-251-9.bmobile.ne.jp] has quit [Quit: Leaving] 10:19 < geertu> Perhaps periupport? 10:20 < geertu> I plan to go over the core related patches, as I believe several of them were upstreamed in some form 10:21 < geertu> I already did that for the patches that had identical patch IDs in upstream 10:22 < morimoto> geertu: I posted periupport patch again. I hope you can accept it 10:23 < geertu> morimoto: Thank you. But that will probably happen only next week. 10:24 < morimoto> OK, np 10:25 < geertu> Any other topics to discuss? 10:26 < geertu> For next meeting, I propose Tuesday, April 25, 08:00 GMT / 10:00 CEST / 11:00 EEST / 17:00 JST 10:26 < neg> I have a question about JTAG :-) 10:26 < geertu> neg: shoot! 10:26 < jmondi> I have -many- questions about JTAG 10:26 < jmondi> (joking, go on neg) 10:27 < geertu> neg: Machine gun questions? 10:27 < geertu> sorry, jmondi: Machine gun questions? 10:27 < neg> A while back I got my Flyswatter 2 and managed to find and modify some OpenOCD config files to get ut running on Gen2. If those could be tested on more boards then my Koelsch I think we could (re)try to get them picked up in upstream OpenOCD. Do you think there would be value in this? 10:28 < neg> I posted the configs at https://git.ragnatech.se/renesas-jtag/ and intend to write up elinux wiki page, I assume the SW settings to enable JTAG are OK to describe there as well? 10:30 < geertu> Cool! 10:30 < geertu> I only have 10:30 < geertu> source [find interface/ftdi/flyswatter2.cfg] 10:30 < geertu> reset_config trst_and_srst 10:30 < geertu> jtag_rclk 8 10:30 < neg> last question is aimed at Morimoto-san :-) 10:30 < geertu> (most from Magnus, IIRC) so I never got that far... 10:31 < jmondi> neg: I will send you patches to use OpenOCD+Flyswatter on RZ as well :) 10:32 < neg> jmondi: nice :-) 10:35 < kbingham> neg: I guess you haven't looked at G3 yet :) 10:36 < neg> kbingham: thats right :-) 10:36 * geertu assumes kbingham is not talking about SH7367 (SH-Mobile G3) 10:37 < kbingham> geertu: Well, maybe I was ... :D 10:37 < geertu> Every spelling mistake is a different SoC ;-) 10:37 * morimoto geertu solved my confusion 10:37 < geertu> morimoto: cs2000? 10:37 < morimoto> No, about G3 :) 10:37 * kbingham coughs : Gen 3 10:37 < geertu> kbingham: R-Car Gen3? 10:39 * morimoto I think neg's "last question" is not yet coming ? 10:39 < neg> morimoto: sry, my question was if it's OK to mention wich SW on the board you need to flip to enable JTAG, is this OK to mention on the elinux wiki? 10:40 < neg> for Gen2 that is 10:40 < morimoto> Ahh, OK. I think it is no problem 10:41 < neg> OK thanks 10:42 < neg> So I will let them stew in the reop and write a elinux page. If you try them out on Alt or Lager please let me know if all works I can resubmit them to OpenOCD and se what happens 10:43 < neg> that was all from me, thanks 10:46 < geertu> neg: Have you tried JTAG on the KZM9D? 10:46 -!- dammsan [~dammsan@s214090.ppp.asahi-net.or.jp] has quit [Remote host closed the connection] 10:46 < geertu> It may help to solve the SMP issue 10:46 < neg> geertu: no not yet, lurking in the back of my head tho 10:47 < neg> geertu: but I think Magnus once told me some special magic where needed to get it working 10:48 < geertu> OK 10:49 < geertu> Then I think we are finished? 10:49 < geertu> Thanks for joining, and have a nice continued day! 10:50 < shimoda> thank you! 10:50 < neg> I have nothing further, and the 25th works fine for me 10:50 < neg> thanks all 10:50 < jmondi> 25th is kind of bad for me 10:50 < jmondi> national holiday here and I don't plan to be home... 10:51 < jmondi> sorry I forgot to tell 10:52 < morimoto> 25th is OK for me too 10:52 < morimoto> thanks 11:01 < morimoto> geertu: are you still here ? 11:01 < morimoto> I want to ask you about cs2000 11:07 < geertu> morimoto: yes, still here 11:07 < morimoto> what does your "a mux clock driver with three parents" ? 11:08 < geertu> morimoto: it's a very simple driver where you can select between 3 parents 11:08 < morimoto> How to select it ? by DT ? 11:08 < geertu> By clk_ops.set_parent() 11:09 < geertu> or .determine_rate(), which selects the best parent for the requested rate 11:09 < geertu> drivers/clk/clk-mux.c 11:09 < morimoto> Ahh.. 11:10 < morimoto> OK, thanks. I will check clk-mux.c 11:17 < morimoto> 1 question again. Who/How to select parent clock of .set_parent() ? 11:17 < morimoto> This AUX_OUT usage is board specific 11:18 < morimoto> Ahh, OK, I understand 11:18 < morimoto> Thanks a id='n188' href='#n188'>188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 
#ifndef _I810_DRM_H_
#define _I810_DRM_H_

/* WARNING: These defines must be the same as what the Xserver uses.
 * if you change them, you must change the defines in the Xserver.
 */

#ifndef _I810_DEFINES_
#define _I810_DEFINES_

#define I810_DMA_BUF_ORDER		12
#define I810_DMA_BUF_SZ 		(1<<I810_DMA_BUF_ORDER)
#define I810_DMA_BUF_NR 		256
#define I810_NR_SAREA_CLIPRECTS 	8

/* Each region is a minimum of 64k, and there are at most 64 of them.
 */
#define I810_NR_TEX_REGIONS 64
#define I810_LOG_MIN_TEX_REGION_SIZE 16
#endif

#define I810_UPLOAD_TEX0IMAGE  0x1	/* handled clientside */
#define I810_UPLOAD_TEX1IMAGE  0x2	/* handled clientside */
#define I810_UPLOAD_CTX        0x4
#define I810_UPLOAD_BUFFERS    0x8
#define I810_UPLOAD_TEX0       0x10
#define I810_UPLOAD_TEX1       0x20
#define I810_UPLOAD_CLIPRECTS  0x40

/* Indices into buf.Setup where various bits of state are mirrored per
 * context and per buffer.  These can be fired at the card as a unit,
 * or in a piecewise fashion as required.
 */

/* Destbuffer state
 *    - backbuffer linear offset and pitch -- invarient in the current dri
 *    - zbuffer linear offset and pitch -- also invarient
 *    - drawing origin in back and depth buffers.
 *
 * Keep the depth/back buffer state here to accommodate private buffers
 * in the future.
 */
#define I810_DESTREG_DI0  0	/* CMD_OP_DESTBUFFER_INFO (2 dwords) */
#define I810_DESTREG_DI1  1
#define I810_DESTREG_DV0  2	/* GFX_OP_DESTBUFFER_VARS (2 dwords) */
#define I810_DESTREG_DV1  3
#define I810_DESTREG_DR0  4	/* GFX_OP_DRAWRECT_INFO (4 dwords) */
#define I810_DESTREG_DR1  5
#define I810_DESTREG_DR2  6
#define I810_DESTREG_DR3  7
#define I810_DESTREG_DR4  8
#define I810_DEST_SETUP_SIZE 10

/* Context state
 */
#define I810_CTXREG_CF0   0	/* GFX_OP_COLOR_FACTOR */
#define I810_CTXREG_CF1   1
#define I810_CTXREG_ST0   2	/* GFX_OP_STIPPLE */
#define I810_CTXREG_ST1   3
#define I810_CTXREG_VF    4	/* GFX_OP_VERTEX_FMT */
#define I810_CTXREG_MT    5	/* GFX_OP_MAP_TEXELS */
#define I810_CTXREG_MC0   6	/* GFX_OP_MAP_COLOR_STAGES - stage 0 */
#define I810_CTXREG_MC1   7	/* GFX_OP_MAP_COLOR_STAGES - stage 1 */
#define I810_CTXREG_MC2   8	/* GFX_OP_MAP_COLOR_STAGES - stage 2 */
#define I810_CTXREG_MA0   9	/* GFX_OP_MAP_ALPHA_STAGES - stage 0 */
#define I810_CTXREG_MA1   10	/* GFX_OP_MAP_ALPHA_STAGES - stage 1 */
#define I810_CTXREG_MA2   11	/* GFX_OP_MAP_ALPHA_STAGES - stage 2 */
#define I810_CTXREG_SDM   12	/* GFX_OP_SRC_DEST_MONO */
#define I810_CTXREG_FOG   13	/* GFX_OP_FOG_COLOR */
#define I810_CTXREG_B1    14	/* GFX_OP_BOOL_1 */
#define I810_CTXREG_B2    15	/* GFX_OP_BOOL_2 */
#define I810_CTXREG_LCS   16	/* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */
#define I810_CTXREG_PV    17	/* GFX_OP_PV_RULE -- Invarient! */
#define I810_CTXREG_ZA    18	/* GFX_OP_ZBIAS_ALPHAFUNC */
#define I810_CTXREG_AA    19	/* GFX_OP_ANTIALIAS */
#define I810_CTX_SETUP_SIZE 20

/* Texture state (per tex unit)
 */
#define I810_TEXREG_MI0  0	/* GFX_OP_MAP_INFO (4 dwords) */
#define I810_TEXREG_MI1  1
#define I810_TEXREG_MI2  2
#define I810_TEXREG_MI3  3
#define I810_TEXREG_MF   4	/* GFX_OP_MAP_FILTER */
#define I810_TEXREG_MLC  5	/* GFX_OP_MAP_LOD_CTL */
#define I810_TEXREG_MLL  6	/* GFX_OP_MAP_LOD_LIMITS */
#define I810_TEXREG_MCS  7	/* GFX_OP_MAP_COORD_SETS ??? */
#define I810_TEX_SETUP_SIZE 8

/* Flags for clear ioctl
 */
#define I810_FRONT   0x1
#define I810_BACK    0x2
#define I810_DEPTH   0x4

typedef enum _drm_i810_init_func {
	I810_INIT_DMA = 0x01,
	I810_CLEANUP_DMA = 0x02,
	I810_INIT_DMA_1_4 = 0x03
} drm_i810_init_func_t;

/* This is the init structure after v1.2 */
typedef struct _drm_i810_init {
	drm_i810_init_func_t func;
	unsigned int mmio_offset;
	unsigned int buffers_offset;
	int sarea_priv_offset;
	unsigned int ring_start;
	unsigned int ring_end;
	unsigned int ring_size;
	unsigned int front_offset;
	unsigned int back_offset;
	unsigned int depth_offset;
	unsigned int overlay_offset;
	unsigned int overlay_physical;
	unsigned int w;
	unsigned int h;
	unsigned int pitch;
	unsigned int pitch_bits;
} drm_i810_init_t;

/* Warning: If you change the SAREA structure you must change the Xserver
 * structure as well */

typedef struct _drm_i810_tex_region {
	unsigned char next, prev;	/* indices to form a circular LRU  */
	unsigned char in_use;	/* owned by a client, or free? */
	int age;		/* tracked by clients to update local LRU's */
} drm_i810_tex_region_t;

typedef struct _drm_i810_sarea {
	unsigned int ContextState[I810_CTX_SETUP_SIZE];
	unsigned int BufferState[I810_DEST_SETUP_SIZE];
	unsigned int TexState[2][I810_TEX_SETUP_SIZE];
	unsigned int dirty;

	unsigned int nbox;
	struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS];

	/* Maintain an LRU of contiguous regions of texture space.  If
	 * you think you own a region of texture memory, and it has an
	 * age different to the one you set, then you are mistaken and
	 * it has been stolen by another client.  If global texAge
	 * hasn't changed, there is no need to walk the list.
	 *
	 * These regions can be used as a proxy for the fine-grained
	 * texture information of other clients - by maintaining them
	 * in the same lru which is used to age their own textures,
	 * clients have an approximate lru for the whole of global
	 * texture space, and can make informed decisions as to which
	 * areas to kick out.  There is no need to choose whether to
	 * kick out your own texture or someone else's - simply eject
	 * them all in LRU order.
	 */

	drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
	/* Last elt is sentinal */
	int texAge;		/* last time texture was uploaded */
	int last_enqueue;	/* last time a buffer was enqueued */
	int last_dispatch;	/* age of the most recently dispatched buffer */
	int last_quiescent;	/*  */
	int ctxOwner;		/* last context to upload state */

	int vertex_prim;

	int pf_enabled;		/* is pageflipping allowed? */
	int pf_active;
	int pf_current_page;	/* which buffer is being displayed? */
} drm_i810_sarea_t;

/* WARNING: If you change any of these defines, make sure to change the
 * defines in the Xserver file (xf86drmMga.h)
 */

/* i810 specific ioctls
 * The device specific ioctl range is 0x40 to 0x79.
 */
#define DRM_I810_INIT		0x00
#define DRM_I810_VERTEX		0x01
#define DRM_I810_CLEAR		0x02
#define DRM_I810_FLUSH		0x03
#define DRM_I810_GETAGE		0x04
#define DRM_I810_GETBUF		0x05
#define DRM_I810_SWAP		0x06
#define DRM_I810_COPY		0x07
#define DRM_I810_DOCOPY		0x08
#define DRM_I810_OV0INFO	0x09
#define DRM_I810_FSTATUS	0x0a
#define DRM_I810_OV0FLIP	0x0b
#define DRM_I810_MC		0x0c
#define DRM_I810_RSTATUS	0x0d
#define DRM_I810_FLIP		0x0e

#define DRM_IOCTL_I810_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
#define DRM_IOCTL_I810_VERTEX		DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
#define DRM_IOCTL_I810_CLEAR		DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
#define DRM_IOCTL_I810_FLUSH		DRM_IO(  DRM_COMMAND_BASE + DRM_I810_FLUSH)
#define DRM_IOCTL_I810_GETAGE		DRM_IO(  DRM_COMMAND_BASE + DRM_I810_GETAGE)
#define DRM_IOCTL_I810_GETBUF		DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t)
#define DRM_IOCTL_I810_SWAP		DRM_IO(  DRM_COMMAND_BASE + DRM_I810_SWAP)
#define DRM_IOCTL_I810_COPY		DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
#define DRM_IOCTL_I810_DOCOPY		DRM_IO(  DRM_COMMAND_BASE + DRM_I810_DOCOPY)
#define DRM_IOCTL_I810_OV0INFO		DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
#define DRM_IOCTL_I810_FSTATUS		DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS)
#define DRM_IOCTL_I810_OV0FLIP		DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
#define DRM_IOCTL_I810_MC		DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
#define DRM_IOCTL_I810_RSTATUS		DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS)
#define DRM_IOCTL_I810_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP)

typedef struct _drm_i810_clear {
	int clear_color;
	int clear_depth;
	int flags;
} drm_i810_clear_t;

/* These may be placeholders if we have more cliprects than
 * I810_NR_SAREA_CLIPRECTS.  In that case, the client sets discard to
 * false, indicating that the buffer will be dispatched again with a
 * new set of cliprects.
 */
typedef struct _drm_i810_vertex {
	int idx;		/* buffer index */
	int used;		/* nr bytes in use */
	int discard;		/* client is finished with the buffer? */
} drm_i810_vertex_t;

typedef struct _drm_i810_copy_t {
	int idx;		/* buffer index */
	int used;		/* nr bytes in use */
	void *address;		/* Address to copy from */
} drm_i810_copy_t;

#define PR_TRIANGLES         (0x0<<18)
#define PR_TRISTRIP_0        (0x1<<18)
#define PR_TRISTRIP_1        (0x2<<18)
#define PR_TRIFAN            (0x3<<18)
#define PR_POLYGON           (0x4<<18)
#define PR_LINES             (0x5<<18)
#define PR_LINESTRIP         (0x6<<18)
#define PR_RECTS             (0x7<<18)
#define PR_MASK              (0x7<<18)

typedef struct drm_i810_dma {
	void *virtual;
	int request_idx;
	int request_size;
	int granted;
} drm_i810_dma_t;

typedef struct _drm_i810_overlay_t {
	unsigned int offset;	/* Address of the Overlay Regs */
	unsigned int physical;
} drm_i810_overlay_t;

typedef struct _drm_i810_mc {
	int idx;		/* buffer index */
	int used;		/* nr bytes in use */
	int num_blocks;		/* number of GFXBlocks */
	int *length;		/* List of lengths for GFXBlocks (FUTURE) */
	unsigned int last_render;	/* Last Render Request */
} drm_i810_mc_t;

#endif				/* _I810_DRM_H_ */