title: "BSP 4.1.x upport: simple-bridge: Validate pixel clock"
team: MM
key: ed367c5b-5cf5-4f6a-9382-186ef72c2bbe
status: New

bsp41x:
 - ae5ed0b2888c3c084849e3b1b77001c4b3519f5d # drm/bridge: dumb-vga-dac: Add dot clock valid check
 - fccc46cf75fd45b867c8c8501c526a92efc4d49b # arm64: dts: r8a77995-draak: Set max dot clock for vga
 - 64ee34a191cefc9fd10042f785996c811c336992 # arm64: dts: r8a77990-ebisu: Set max dot clock for vga
 - a117af5977b652da0abece0b1a17049db4a76d09 # arm64: dts: salvator-common: Set max dot clock for vga

comments:
 - The ADV7123 VGA DAC used on the Draak, Ebisu and Salvator-X boards has a
   pixel clock rate limit of 140MHz. The simple-bridge driver should implement
   a .mode_valid() operation to reject modes that require a too high clock
   frequency.

   However, the ADV7123 comes in multiple variants, with different frequency
   limits. Matching on the compatible string to get the frequency limit is an
   option, but would lead to a proliferation of compatible strings. A
   vendor-specific DT property may be a better solution.

 - The limits set in the BSP's DT sources doesn't match the AD7123's limit.
   Those limits must not be copied blindly, more information is needed from the
   BSP team to understand the actual hardware limits, and where they come from.