title: "R-Mobile APE6: Add SMP support"

team: Core
key: e06f8a62-abe3-11eb-bae6-5b3014b8c809
status: Active
assignee: Geert

upstream:
  - lore: 20210204135409.1652604-1-geert+renesas@glider.be # [PATCH/RFC 0/6] ARM: r8a73a4: Add SMP support

comments:
  - Known issues:
      - While initial secondary CPU bring-up during boot works, CPU cores
        fail to come online after offlining/onlining them using the sysfs
        interface ("echo [01] > /sys/*/*/cpu/cpu[0-9]*{off,on}line").

      - This breaks detection of the CFI FLASH.  I traced this back to
        setting the SBAR_BAREN bit in the SYSC.CA15BAR register.
        Presumably this affects the LBSC in some way?

  - To do:
      - Call into rmobile-sysc instead of hardcoding the SYSC mapping,
      - Describe CCI-400 in DT and call cci_enable_port_by_index()?
      - Let pm-rcar-gen2.c call into rcar-rst instead of hardcoding the RST
        mapping,
      - Abstract SYSC vs. RST access and merge with pm-rcar-gen2.c?

  - Questions:
      - Do we want to bring up the Cortex-A7 cores, too? We don't on R-Car
        H2 neither.