From e23b634ec4399e06695e28959cc34876efa48119 Mon Sep 17 00:00:00 2001
From: Wolfram Sang <wsa+renesas@sang-engineering.com>
Date: Fri, 17 Jun 2022 22:57:11 +0200
Subject: projects: linux: io: updates up to W24
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
projects/linux/io/S4-enable-IO-devices.yaml | 15 +++++++++++++++
1 file changed, 15 insertions(+)
(limited to 'projects/linux')
diff --git a/projects/linux/io/S4-enable-IO-devices.yaml b/projects/linux/io/S4-enable-IO-devices.yaml
index a594208..8ef16b5 100644
--- a/projects/linux/io/S4-enable-IO-devices.yaml
+++ b/projects/linux/io/S4-enable-IO-devices.yaml
@@ -19,25 +19,40 @@ upstream:
- lore: 20220608094831.8242-1-wsa+renesas@sang-engineering.com # [PATCH] dt-bindings: mmc: renesas,sdhi: R-Car V3U is R-Car Gen4
- lore: 20220608122344.3431-1-wsa+renesas@sang-engineering.com # [PATCH] dt-bindings: mmc: renesas,sdhi: Add R-Car Gen4 clock requirements
+ - lore: 20220614094937.8104-1-wsa+renesas@sang-engineering.com # [PATCH v2] clk: renesas: r8a779f0: Add HSCIF clocks
+ - lore: 20220613131007.10027-1-wsa+renesas@sang-engineering.com # [PATCH] dt-bindings: serial: renesas,hscif: Document r8a779f0 bindings
+ - lore: 20220614095109.8175-1-wsa+renesas@sang-engineering.com # [PATCH v2] arm64: dts: renesas: r8a779f0: Add HSCIF nodes
+ - lore: 20220613131033.10053-2-wsa+renesas@sang-engineering.com # [PATCH 2/2] arm64: dts: renesas: spider-cpu: Switch from SCIF3 to HSCIF0
+ - lore: 20220613134914.18655-1-wsa+renesas@sang-engineering.com # [PATCH 1/3] arm64: dts: renesas: r8a779f0: Add DMA properties to SCIF3
+ - lore: 20220614095242.8264-1-wsa+renesas@sang-engineering.com # [PATCH v2] arm64: dts: renesas: r8a779f0: Add SCIF nodes
+ - lore: 20220613134914.18655-3-wsa+renesas@sang-engineering.com # [PATCH 3/3] arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector
comments:
- CMT0/1
+ - prototype patches exist, clocksouce-switch test fails for CMT3, needs investigation
- HSCIF
- HSCIF 0+1 can be muxed to FTDI chips, HSCIF3 to MSIOF headers using an external FTDI, HSCIF2 maybe via unpopulated I2C header
+ - all HSCIFs could be tested, patches sent
- MSIOF
- RPC
- not for upstream because RPC shall only be accessed via OPTEE. See BSP commit 1f83a133b853138fad712d0a08a7689aac1e0183 ("Disable SPI flash via RPC")
+ - done
- SCIF
- SCIF 0+3 can be muxed to FTDI chips, SCIF1 to MSIOF headers using an external FTDI, SCIF4 maybe via unpopulated I2C header
+ - all SCIFs could be tested, patches sent
- SD/MMC
- eMMC enabled and works, microSD enabled but still needs testing
- first patches sent, only final DTS addition kept until testing is done
- SD0H support was missing, resend needed
+ - eMMC works but is too slow compared to BSP, investigation needed
+ - microSD fails the same way the BSP does
+ - Shimoda-san researched that this is because SW6 needs to select the proper voltage
+ - SW is under the heat sink, though. So, for upstream only eMMC is desired
- THS/CIVM
- first version sent
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