From 8ac8e1d2333f0bb8dd4bc9a4908c889826c072aa Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 22 Mar 2019 11:40:27 +0100 Subject: projects: linux: core: Merge clock errata Signed-off-by: Geert Uytterhoeven --- projects/linux/core/bsp392_clk_renesas_errata.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 projects/linux/core/bsp392_clk_renesas_errata.yaml (limited to 'projects/linux/core/bsp392_clk_renesas_errata.yaml') diff --git a/projects/linux/core/bsp392_clk_renesas_errata.yaml b/projects/linux/core/bsp392_clk_renesas_errata.yaml new file mode 100644 index 0000000..9d7e0ad --- /dev/null +++ b/projects/linux/core/bsp392_clk_renesas_errata.yaml @@ -0,0 +1,18 @@ +title: "From bsp392, upport clk: renesas: errata" +team: Core +key: 67a370b6-df7b-4d7f-ace2-b7470925f38c +status: New + +relationships: + +bsp-commits: + - 1ad2ac2ebaee63e6df1489d145e9a17bc8dc32a0 # clk: renesas: r8a7796: Correct parent clock of EHCI/OHCI + - 5944af98d299aeb81c1f867b2869ea912b3b8eb7 # clk: renesas: r8a77{95,96,965,990}: Correct parent clock of Audio-DMAC + - a368826e8647d23a758207e191b14b2207182632 # clk: renesas: r8a77{95,96,965}: Correct parent clock of SYS-DMAC + - accceea30bd4f4aca1be5771e48db70e83e0b10e # clk: renesas: r8a77{95,965,990}: Correct parent clock of EHCI/OHCI + - e6b2f32570db4c47730e2217f3aa602a370f5aa5 # clk: renesas: r8a7796: Correct parent clock of HS-USB + - f1699a5ab267220bebcaa99104c3f3e69f1fa453 # clk: renesas: r8a77{95,965,990}: Correct parent clock of HS-USB + +upstream: + +comments: -- cgit v1.2.3