Age | Commit message (Collapse) | Author |
|
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
|
|
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
|
|
This reduces visual clutter.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
|
|
Forgot to mark this done in the auto-update sweep.
Fixes: 2b91cf69328b0655 ("Auto-update sweep for v5.5-rc1")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
|
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
|
|
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Disabling cpuible was just one possible mitigation for a system
controller issue, to prevent conflicts between powering off CPU cores or
the 3D Graphics Engine, and changing the state of another power domain
through SYSC, which could lead to CPG state machine lock-ups. Other
mitigations are to make use of the new System Controller External
Request Mask Register, present in newer SoCs and SoC revisions, or to
keep some power areas always powered.
However, we believe this issue cannot happen in the upstream kernel, as
upstream has no support for graphics acceleration yet.
Hence this task became unblocked.
CPUidle for R-Car H3 and M3-W is in next.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
.determine_rate() has been implemented for Z and SD clocks,
on R-Car Gen2 and Gen3.
To do: div6 and RZ/N1.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Add SYSCEXTMASK explanation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
|
|
|
|
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[wsa: mark this one as 'Abandoned' instead of 'Done'. Minor rewording]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
|
|
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[wsa: mark this one as 'Done' instead of 'Abandoned'. Minor rewording]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
|
|
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
|
|
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
|
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
|
|
Signed-off-by: Jacopo Mondi <jacopo@jmondi.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
|
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
|
|
The following commits were already upstreamed when the list was
created:
bsp: 63ec9d6fc03d5692 ("arm64: dts: r8a77990: Fix SCIF5 DMA channels")
v5.1: e20119f7eaaaf6aa ("arm64: dts: renesas: r8a77990: Fix SCIF5 DMA channels")
bsp: 2fba5e0e94db930a ("media: i2c: adv748x: Use devm to allocate the device struct")
v5.1: fb517583b3fe0bb6 ("media: i2c: adv748x: Use devm to allocate the device struct")
bsp: 620f3e493e55cf95 ("media: rcar-vin: Allow independent VIN link enablement")
v5.1: c5ff0edb8e2270a7 ("media: rcar-vin: Allow independent VIN link enablement")
bsp: 3058f51605307b06 ("clk: renesas: r8a77{95,96,965,990}: Rename DRIF clock names")
v5.2: 3c14505c68ca6b3b ("clk: renesas: rcar-gen3: Rename DRIF clocks")
bsp: 46a818b22337d135 ("clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate return value")
v5.2: b953eaaeb58efc94 ("clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value")
bsp: f920a58743e6980b ("pinctrl: sh-pfc: r8a77990: Rename RTS{0,1,3,4}# pin function definitions")
v5.2: 624a7a12cc0cc776 ("pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions")
bsp: e4118df28958fdcc ("pinctrl: sh-pfc: r8a77965: Fix SEL_NDF name")
bsp: 988d160a4e6f4e0c ("pinctrl: sh-pfc: r8a7796: Rename SEL_NDFC to SEL_NDF")
v5.2: e551122cdb7fcb9a ("pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF")
bsp: 79bbcf1d8d76fd0a ("pinctrl: sh-pfc: r8a77{95,96,965}: Rename SEL_ADG_B to SEL_ADGB and rename SEL_ADG_C to SEL_ADGC")
v5.2: a040f3dec8eb7b11 ("pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}")
Hence remove them.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
All of these are already present in YAML files:
- addfe9203290e3c2 ("mmc: renesas_sdhi: Fix hang up in HS400 timing mode selection")
- b2e044a3602f7f9f ("mmc: renesas_sdhi: Change HS400 manual calibration value for r8a77990")
- 2e4d341d1cc11c05 ("ravb: Protect access to ts_skb_list with spinlock.")
- 444401e833c4ad62 ("ravb: Fix use-after-free ravb_tstamp_skb")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Included in v5.3-rc1.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
|