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-rw-r--r--projects/linux/io/bsp392_I2C.yaml19
-rw-r--r--projects/linux/io/bsp392_MSIOF.yaml19
-rw-r--r--projects/linux/io/bsp392_PCIe.yaml16
-rw-r--r--projects/linux/io/bsp392_PWM.yaml14
-rw-r--r--projects/linux/io/bsp392_RAVB.yaml15
-rw-r--r--projects/linux/io/bsp392_SCIF.yaml17
-rw-r--r--projects/linux/io/bsp392_SDHI.yaml17
-rw-r--r--projects/linux/io/bsp392_SDHI_HS400_add.yaml16
-rw-r--r--projects/linux/io/bsp392_Thermal.yaml15
-rw-r--r--projects/linux/io/bsp392_USB2_PHY.yaml15
10 files changed, 163 insertions, 0 deletions
diff --git a/projects/linux/io/bsp392_I2C.yaml b/projects/linux/io/bsp392_I2C.yaml
new file mode 100644
index 0000000..f4146b5
--- /dev/null
+++ b/projects/linux/io/bsp392_I2C.yaml
@@ -0,0 +1,19 @@
+title: "From bsp392, upport I2C patches"
+team: IO
+key: bdff6043-b6fc-4a0a-9ffe-effbb49ceafd
+status: Active
+assignee: Wolfram
+
+relationships:
+
+bsp-commits:
+ - 3bec6b7f9307cf3a2c122e3ac1030b1f8e9f5680 # i2c: rcar: Tidy up the register order for hardware specification ver1.00
+ - 55d2d2fb8b04b4b7bbdbd68d5e0523841b610de2 # i2c: rcar: Fix I2C DMA transmission by setting sequence
+ - 6865112eb6b070e9fde3b577eb0685980ede201b # i2c: rcar: Support the suspend/resume
+ - ece7b231072daaee86431233c80bfbde4740a2ca # i2c: rcar: Fix disable ICDMAER register
+
+upstream:
+
+comments:
+ - "3bec6b7f9307cf3a2c122e3ac1030b1f8e9f5680: https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=69347, when to enable IRQ is still an open question"
+ - "6865112eb6b070e9fde3b577eb0685980ede201b: linux-next:9ac6cb5fbb1781d120ca0ad29d014d35c9c3f0c4,18569fa89a4db9ed6b5181624788a1574a9b6ed7,81d696c7c4ff8c981333159d072da65268bfe6d5"
diff --git a/projects/linux/io/bsp392_MSIOF.yaml b/projects/linux/io/bsp392_MSIOF.yaml
new file mode 100644
index 0000000..4297e60
--- /dev/null
+++ b/projects/linux/io/bsp392_MSIOF.yaml
@@ -0,0 +1,19 @@
+title: "From bsp392, upport MSIOF patches"
+team: IO
+key: 1185bf87-d9d3-4cbf-a5fa-c46794018cba
+status: Active
+assignee: Geert
+
+relationships:
+
+bsp-commits:
+ - 0577dba6b377ff60fc5f284ea7bd3eeb28e781f5 # spi: sh-msiof: Add reset of registers before starting transfer
+ - 9312d43151d28307f527920dafbd7789eabdc63a # spi: sh-msiof: Add MSIOF module clock changing processing for R-Car Gen3
+ - a14d0903968f1524304f5b4de3da584778dbdfde # spi: sh-msiof: Set 2 clock delay for R-Car H3 Ver.3.0 only
+ - f925bf9ef632042ebb32e52108cc97305c15183d # spi: sh-msiof: Add support for r8a7795
+
+upstream:
+
+comments:
+ - "9312d43151d28307f527920dafbd7789eabdc63a: Proposing 'N': Should use ´assigned-clocks´ and ´assigned-clock-rates´ in board DTS file that actually uses MSIOF"
+ - "f925bf9ef632042ebb32e52108cc97305c15183d: Proposing 'N': not needed as the driver matches against ´renesas,rcar-gen3-msiof´"
diff --git a/projects/linux/io/bsp392_PCIe.yaml b/projects/linux/io/bsp392_PCIe.yaml
new file mode 100644
index 0000000..4ae0a12
--- /dev/null
+++ b/projects/linux/io/bsp392_PCIe.yaml
@@ -0,0 +1,16 @@
+title: "From bsp392, upport PCIe patches"
+team: IO
+key: 7ddd3743-fa13-4966-bcf0-10609b873ab5
+status: Active
+assignee: Marek
+
+relationships:
+
+bsp-commits:
+ - a860c564527572e4b8c4e458b826d5e59852de88 # PCI: pcie-rcar: Handle returned value of rcar_pcie_wait_for_dl
+ - bcc3bd0d2c677658201abcda3d09a18a51fa42c0 # PCI: Avoid PCI device removing/rescanning through sysfs triggers a deadlock
+
+upstream:
+
+comments:
+ - "bcc3bd0d2c677658201abcda3d09a18a51fa42c0: Already discussed by upstream in https://patchwork.ozlabs.org/patch/993438/"
diff --git a/projects/linux/io/bsp392_PWM.yaml b/projects/linux/io/bsp392_PWM.yaml
new file mode 100644
index 0000000..af84d07
--- /dev/null
+++ b/projects/linux/io/bsp392_PWM.yaml
@@ -0,0 +1,14 @@
+title: "From bsp392, upport PWM patches"
+team: IO
+key: e704e989-ccaa-48a5-8f58-28c5b93467ff
+status: Active
+assignee: Shimoda
+
+relationships:
+
+bsp-commits:
+ - 70b4a22f220fef943c45a1122fa02d6faa42d2fe # pwm: Avoid deadlock warning when removing PWM device
+
+upstream:
+
+comments:
diff --git a/projects/linux/io/bsp392_RAVB.yaml b/projects/linux/io/bsp392_RAVB.yaml
new file mode 100644
index 0000000..bbade9b
--- /dev/null
+++ b/projects/linux/io/bsp392_RAVB.yaml
@@ -0,0 +1,15 @@
+title: "From bsp392, upport RAVB patches"
+team: IO
+key: 24e341d7-74db-42c6-ba03-785030932abf
+status: Active
+assignee: Simon
+
+relationships:
+
+bsp-commits:
+ - 0b3fe9516f77238d2f71db71b5c0ab9b0e72cd60 # ravb: Decrease TxFIFO depth of Q3 and Q2 to one
+ - da44dfbbf4a29cc07ad9a6f73e7b07eb156899dd # ravb: Avoid unsupported internal delay mode for R-Car E3/D3
+
+upstream:
+
+comments:
diff --git a/projects/linux/io/bsp392_SCIF.yaml b/projects/linux/io/bsp392_SCIF.yaml
new file mode 100644
index 0000000..37405d7
--- /dev/null
+++ b/projects/linux/io/bsp392_SCIF.yaml
@@ -0,0 +1,17 @@
+title: "From bsp392, upport SCIF patches"
+team: IO
+key: 6b4d4b45-c823-4090-9074-cfa2231dcb57
+status: Done
+assignee: Geert
+# and Ulrich, too
+
+relationships:
+
+bsp-commits:
+ - 7e52a3e6a91194e99a2bca9b4e7bc915b8b2410e # serial: sh-sci: Fix transfer sequence of unsupport DMA transfer
+
+upstream:
+ - torvalds: c58a3ae58bce99d20fdbc5d97beecf31cc19f3dd # serial: sh-sci: do not warn if DMA transfers are not supported
+
+comments:
+ - "7e52a3e6a91194e99a2bca9b4e7bc915b8b2410e: Alternative solution"
diff --git a/projects/linux/io/bsp392_SDHI.yaml b/projects/linux/io/bsp392_SDHI.yaml
new file mode 100644
index 0000000..1ba550c
--- /dev/null
+++ b/projects/linux/io/bsp392_SDHI.yaml
@@ -0,0 +1,17 @@
+title: "From bsp392, upport SDHI patches"
+team: IO
+key: fa60988e-b712-4a2a-a26b-5f2f76773720
+status: Active
+assignee: Wolfram
+# and Marek, too
+
+relationships:
+
+bsp-commits:
+ - 5cf2049947bb17a52ae41162e7aa16dd315d8081 # mmc: renesas_sdhi_core: fix card initialization failure in high speed mode
+ - d286828a8ea35374297425c03f5ecd27fac35e10 # mmc: renesas_sdhi: Change HW adjustment register according to speed mode
+
+upstream:
+
+comments:
+ - "5cf2049947bb17a52ae41162e7aa16dd315d8081: linux-next:3ad323c78b89880bc4761a5bfb35b7d12e2709c9"
diff --git a/projects/linux/io/bsp392_SDHI_HS400_add.yaml b/projects/linux/io/bsp392_SDHI_HS400_add.yaml
new file mode 100644
index 0000000..b01294f
--- /dev/null
+++ b/projects/linux/io/bsp392_SDHI_HS400_add.yaml
@@ -0,0 +1,16 @@
+title: "From bsp392, refactor and upport HS400 manual calibration mode"
+team: IO
+key: eaaeb5e9-2e3b-4e4e-b18c-97c13d5f5605
+status: New
+assignee: Niklas
+
+relationships:
+
+bsp-commits:
+ - 1f84d574931b1319ebc1229678816338578f2d1e # mmc: renesas_sdhi_core: Add adjust HS400 offset by manual calibration mode
+ - a27609e63e9c4915706022b367d1d005833fe547 # mmc: tmio: Add adjust HS400 offset by manual calibration mode
+
+upstream:
+
+comments:
+ - "planned for Q2/19"
diff --git a/projects/linux/io/bsp392_Thermal.yaml b/projects/linux/io/bsp392_Thermal.yaml
new file mode 100644
index 0000000..7e06a2b
--- /dev/null
+++ b/projects/linux/io/bsp392_Thermal.yaml
@@ -0,0 +1,15 @@
+title: "From bsp392, upport Thermal patches"
+team: IO
+key: 645abdbb-77f4-4ffe-b75a-aa97fe40e1e1
+status: Active
+assignee: Kaneko
+
+relationships:
+
+bsp-commits:
+ - 958bd36e03b70026ac3a33aaa6afc202e7158d2d # thermal: rcar_gen3_thermal: [E3] Update calculation formula due to HW evaluation
+ - d4e41702e53b3ca0365666ec8b8182464c8ba2cc # thermal: rcar_gen3_thermal: [H3/M3N] Update calculation formula due to HW evaluation
+
+upstream:
+
+comments:
diff --git a/projects/linux/io/bsp392_USB2_PHY.yaml b/projects/linux/io/bsp392_USB2_PHY.yaml
new file mode 100644
index 0000000..d7aa42c
--- /dev/null
+++ b/projects/linux/io/bsp392_USB2_PHY.yaml
@@ -0,0 +1,15 @@
+title: "From bsp392, upport USB2 PHY patches"
+team: IO
+key: f792d195-7843-4cdd-958f-3497b8ac7469
+status: Active
+assignee: Shimoda
+
+relationships:
+
+bsp-commits:
+ - be61ce267539e16c9fca8fb793fbf3ef975554bd # phy: rcar-gen3-usb2: Add wait for IDDIG
+ - f2d95125e9b042d45eac818edfd6f2ce5d89780f # phy: rcar-gen3-usb2: Add dedicated pin to E3
+
+upstream:
+
+comments:
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/*
 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sub license,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#ifndef VIA_3D_REG_H
#define VIA_3D_REG_H
#define HC_REG_BASE             0x0400

#define HC_REG_TRANS_SPACE      0x0040

#define HC_ParaN_MASK           0xffffffff
#define HC_Para_MASK            0x00ffffff
#define HC_SubA_MASK            0xff000000
#define HC_SubA_SHIFT           24
/* Transmission Setting
 */
#define HC_REG_TRANS_SET        0x003c
#define HC_ParaSubType_MASK     0xff000000
#define HC_ParaType_MASK        0x00ff0000
#define HC_ParaOS_MASK          0x0000ff00
#define HC_ParaAdr_MASK         0x000000ff
#define HC_ParaSubType_SHIFT    24
#define HC_ParaType_SHIFT       16
#define HC_ParaOS_SHIFT         8
#define HC_ParaAdr_SHIFT        0

#define HC_ParaType_CmdVdata    0x0000
#define HC_ParaType_NotTex      0x0001
#define HC_ParaType_Tex         0x0002
#define HC_ParaType_Palette     0x0003
#define HC_ParaType_PreCR       0x0010
#define HC_ParaType_Auto        0x00fe

/* Transmission Space
 */
#define HC_REG_Hpara0           0x0040
#define HC_REG_HpataAF          0x02fc

/* Read
 */
#define HC_REG_HREngSt          0x0000
#define HC_REG_HRFIFOempty      0x0004
#define HC_REG_HRFIFOfull       0x0008
#define HC_REG_HRErr            0x000c
#define HC_REG_FIFOstatus       0x0010
/* HC_REG_HREngSt          0x0000
 */
#define HC_HDASZC_MASK          0x00010000
#define HC_HSGEMI_MASK          0x0000f000
#define HC_HLGEMISt_MASK        0x00000f00
#define HC_HCRSt_MASK           0x00000080
#define HC_HSE0St_MASK          0x00000040
#define HC_HSE1St_MASK          0x00000020
#define HC_HPESt_MASK           0x00000010
#define HC_HXESt_MASK           0x00000008
#define HC_HBESt_MASK           0x00000004
#define HC_HE2St_MASK           0x00000002
#define HC_HE3St_MASK           0x00000001
/* HC_REG_HRFIFOempty      0x0004
 */
#define HC_HRZDempty_MASK       0x00000010
#define HC_HRTXAempty_MASK      0x00000008
#define HC_HRTXDempty_MASK      0x00000004
#define HC_HWZDempty_MASK       0x00000002
#define HC_HWCDempty_MASK       0x00000001
/* HC_REG_HRFIFOfull       0x0008
 */
#define HC_HRZDfull_MASK        0x00000010
#define HC_HRTXAfull_MASK       0x00000008
#define HC_HRTXDfull_MASK       0x00000004
#define HC_HWZDfull_MASK        0x00000002
#define HC_HWCDfull_MASK        0x00000001
/* HC_REG_HRErr            0x000c
 */
#define HC_HAGPCMErr_MASK       0x80000000
#define HC_HAGPCMErrC_MASK      0x70000000
/* HC_REG_FIFOstatus       0x0010
 */
#define HC_HRFIFOATall_MASK     0x80000000
#define HC_HRFIFOATbusy_MASK    0x40000000
#define HC_HRATFGMDo_MASK       0x00000100
#define HC_HRATFGMDi_MASK       0x00000080
#define HC_HRATFRZD_MASK        0x00000040
#define HC_HRATFRTXA_MASK       0x00000020
#define HC_HRATFRTXD_MASK       0x00000010
#define HC_HRATFWZD_MASK        0x00000008
#define HC_HRATFWCD_MASK        0x00000004
#define HC_HRATTXTAG_MASK       0x00000002
#define HC_HRATTXCH_MASK        0x00000001

/* AGP Command Setting
 */
#define HC_SubA_HAGPBstL        0x0060
#define HC_SubA_HAGPBendL       0x0061
#define HC_SubA_HAGPCMNT        0x0062
#define HC_SubA_HAGPBpL         0x0063
#define HC_SubA_HAGPBpH         0x0064
/* HC_SubA_HAGPCMNT        0x0062
 */
#define HC_HAGPCMNT_MASK        0x00800000
#define HC_HCmdErrClr_MASK      0x00400000
#define HC_HAGPBendH_MASK       0x0000ff00
#define HC_HAGPBstH_MASK        0x000000ff
#define HC_HAGPBendH_SHIFT      8
#define HC_HAGPBstH_SHIFT       0
/* HC_SubA_HAGPBpL         0x0063
 */
#define HC_HAGPBpL_MASK         0x00fffffc
#define HC_HAGPBpID_MASK        0x00000003
#define HC_HAGPBpID_PAUSE       0x00000000
#define HC_HAGPBpID_JUMP        0x00000001
#define HC_HAGPBpID_STOP        0x00000002
/* HC_SubA_HAGPBpH         0x0064
 */
#define HC_HAGPBpH_MASK         0x00ffffff

/* Miscellaneous Settings
 */
#define HC_SubA_HClipTB         0x0070
#define HC_SubA_HClipLR         0x0071
#define HC_SubA_HFPClipTL       0x0072
#define HC_SubA_HFPClipBL       0x0073
#define HC_SubA_HFPClipLL       0x0074
#define HC_SubA_HFPClipRL       0x0075
#define HC_SubA_HFPClipTBH      0x0076
#define HC_SubA_HFPClipLRH      0x0077
#define HC_SubA_HLP             0x0078
#define HC_SubA_HLPRF           0x0079
#define HC_SubA_HSolidCL        0x007a
#define HC_SubA_HPixGC          0x007b
#define HC_SubA_HSPXYOS         0x007c
#define HC_SubA_HVertexCNT      0x007d

#define HC_HClipT_MASK          0x00fff000
#define HC_HClipT_SHIFT         12
#define HC_HClipB_MASK          0x00000fff
#define HC_HClipB_SHIFT         0
#define HC_HClipL_MASK          0x00fff000
#define HC_HClipL_SHIFT         12
#define HC_HClipR_MASK          0x00000fff
#define HC_HClipR_SHIFT         0
#define HC_HFPClipBH_MASK       0x0000ff00
#define HC_HFPClipBH_SHIFT      8
#define HC_HFPClipTH_MASK       0x000000ff
#define HC_HFPClipTH_SHIFT      0
#define HC_HFPClipRH_MASK       0x0000ff00
#define HC_HFPClipRH_SHIFT      8
#define HC_HFPClipLH_MASK       0x000000ff
#define HC_HFPClipLH_SHIFT      0
#define HC_HSolidCH_MASK        0x000000ff
#define HC_HPixGC_MASK          0x00800000
#define HC_HSPXOS_MASK          0x00fff000
#define HC_HSPXOS_SHIFT         12
#define HC_HSPYOS_MASK          0x00000fff

/* Command
 * Command A
 */
#define HC_HCmdHeader_MASK      0xfe000000	/*0xffe00000 */
#define HC_HE3Fire_MASK         0x00100000
#define HC_HPMType_MASK         0x000f0000
#define HC_HEFlag_MASK          0x0000e000
#define HC_HShading_MASK        0x00001c00
#define HC_HPMValidN_MASK       0x00000200
#define HC_HPLEND_MASK          0x00000100
#define HC_HVCycle_MASK         0x000000ff
#define HC_HVCycle_Style_MASK   0x000000c0
#define HC_HVCycle_ChgA_MASK    0x00000030
#define HC_HVCycle_ChgB_MASK    0x0000000c
#define HC_HVCycle_ChgC_MASK    0x00000003
#define HC_HPMType_Point        0x00000000
#define HC_HPMType_Line         0x00010000
#define HC_HPMType_Tri          0x00020000
#define HC_HPMType_TriWF        0x00040000
#define HC_HEFlag_NoAA          0x00000000
#define HC_HEFlag_ab            0x00008000
#define HC_HEFlag_bc            0x00004000
#define HC_HEFlag_ca            0x00002000
#define HC_HShading_Solid       0x00000000
#define HC_HShading_FlatA       0x00000400
#define HC_HShading_FlatB       0x00000800
#define HC_HShading_FlatC       0x00000c00
#define HC_HShading_Gouraud     0x00001000
#define HC_HVCycle_Full         0x00000000
#define HC_HVCycle_AFP          0x00000040
#define HC_HVCycle_One          0x000000c0
#define HC_HVCycle_NewA         0x00000000
#define HC_HVCycle_AA           0x00000010
#define HC_HVCycle_AB           0x00000020
#define HC_HVCycle_AC           0x00000030
#define HC_HVCycle_NewB         0x00000000
#define HC_HVCycle_BA           0x00000004
#define HC_HVCycle_BB           0x00000008
#define HC_HVCycle_BC           0x0000000c
#define HC_HVCycle_NewC         0x00000000
#define HC_HVCycle_CA           0x00000001
#define HC_HVCycle_CB           0x00000002
#define HC_HVCycle_CC           0x00000003

/* Command B
 */
#define HC_HLPrst_MASK          0x00010000
#define HC_HLLastP_MASK         0x00008000
#define HC_HVPMSK_MASK          0x00007f80
#define HC_HBFace_MASK          0x00000040
#define HC_H2nd1VT_MASK         0x0000003f
#define HC_HVPMSK_X             0x00004000
#define HC_HVPMSK_Y             0x00002000
#define HC_HVPMSK_Z             0x00001000
#define HC_HVPMSK_W             0x00000800
#define HC_HVPMSK_Cd            0x00000400
#define HC_HVPMSK_Cs            0x00000200
#define HC_HVPMSK_S             0x00000100
#define HC_HVPMSK_T             0x00000080

/* Enable Setting
 */
#define HC_SubA_HEnable         0x0000
#define HC_HenTXEnvMap_MASK     0x00200000
#define HC_HenVertexCNT_MASK    0x00100000
#define HC_HenCPUDAZ_MASK       0x00080000
#define HC_HenDASZWC_MASK       0x00040000
#define HC_HenFBCull_MASK       0x00020000
#define HC_HenCW_MASK           0x00010000
#define HC_HenAA_MASK           0x00008000
#define HC_HenST_MASK           0x00004000
#define HC_HenZT_MASK           0x00002000
#define HC_HenZW_MASK           0x00001000
#define HC_HenAT_MASK           0x00000800
#define HC_HenAW_MASK           0x00000400
#define HC_HenSP_MASK           0x00000200
#define HC_HenLP_MASK           0x00000100
#define HC_HenTXCH_MASK         0x00000080
#define HC_HenTXMP_MASK         0x00000040
#define HC_HenTXPP_MASK         0x00000020
#define HC_HenTXTR_MASK         0x00000010
#define HC_HenCS_MASK           0x00000008
#define HC_HenFOG_MASK          0x00000004
#define HC_HenABL_MASK          0x00000002
#define HC_HenDT_MASK           0x00000001

/* Z Setting
 */
#define HC_SubA_HZWBBasL        0x0010
#define HC_SubA_HZWBBasH        0x0011
#define HC_SubA_HZWBType        0x0012
#define HC_SubA_HZBiasL         0x0013
#define HC_SubA_HZWBend         0x0014
#define HC_SubA_HZWTMD          0x0015
#define HC_SubA_HZWCDL          0x0016
#define HC_SubA_HZWCTAGnum      0x0017
#define HC_SubA_HZCYNum         0x0018
#define HC_SubA_HZWCFire        0x0019
/* HC_SubA_HZWBType
 */
#define HC_HZWBType_MASK        0x00800000
#define HC_HZBiasedWB_MASK      0x00400000
#define HC_HZONEasFF_MASK       0x00200000
#define HC_HZOONEasFF_MASK      0x00100000
#define HC_HZWBFM_MASK          0x00030000
#define HC_HZWBLoc_MASK         0x0000c000
#define HC_HZWBPit_MASK         0x00003fff
#define HC_HZWBFM_16            0x00000000
#define HC_HZWBFM_32            0x00020000
#define HC_HZWBFM_24            0x00030000
#define HC_HZWBLoc_Local        0x00000000
#define HC_HZWBLoc_SyS          0x00004000
/* HC_SubA_HZWBend
 */
#define HC_HZWBend_MASK         0x00ffe000
#define HC_HZBiasH_MASK         0x000000ff
#define HC_HZWBend_SHIFT        10
/* HC_SubA_HZWTMD
 */
#define HC_HZWTMD_MASK          0x00070000
#define HC_HEBEBias_MASK        0x00007f00
#define HC_HZNF_MASK            0x000000ff
#define HC_HZWTMD_NeverPass     0x00000000
#define HC_HZWTMD_LT            0x00010000
#define HC_HZWTMD_EQ            0x00020000
#define HC_HZWTMD_LE            0x00030000
#define HC_HZWTMD_GT            0x00040000
#define HC_HZWTMD_NE            0x00050000
#define HC_HZWTMD_GE            0x00060000
#define HC_HZWTMD_AllPass       0x00070000
#define HC_HEBEBias_SHIFT       8
/* HC_SubA_HZWCDL          0x0016
 */
#define HC_HZWCDL_MASK          0x00ffffff
/* HC_SubA_HZWCTAGnum      0x0017
 */
#define HC_HZWCTAGnum_MASK      0x00ff0000
#define HC_HZWCTAGnum_SHIFT     16
#define HC_HZWCDH_MASK          0x000000ff
#define HC_HZWCDH_SHIFT         0
/* HC_SubA_HZCYNum         0x0018
 */
#define HC_HZCYNum_MASK         0x00030000
#define HC_HZCYNum_SHIFT        16
#define HC_HZWCQWnum_MASK       0x00003fff
#define HC_HZWCQWnum_SHIFT      0
/* HC_SubA_HZWCFire        0x0019
 */
#define HC_ZWCFire_MASK         0x00010000
#define HC_HZWCQWnumLast_MASK   0x00003fff
#define HC_HZWCQWnumLast_SHIFT  0

/* Stencil Setting
 */
#define HC_SubA_HSTREF          0x0023
#define HC_SubA_HSTMD           0x0024
/* HC_SubA_HSBFM
 */
#define HC_HSBFM_MASK           0x00030000
#define HC_HSBLoc_MASK          0x0000c000
#define HC_HSBPit_MASK          0x00003fff
/* HC_SubA_HSTREF
 */
#define HC_HSTREF_MASK          0x00ff0000
#define HC_HSTOPMSK_MASK        0x0000ff00
#define HC_HSTBMSK_MASK         0x000000ff
#define HC_HSTREF_SHIFT         16
#define HC_HSTOPMSK_SHIFT       8
/* HC_SubA_HSTMD
 */
#define HC_HSTMD_MASK           0x00070000
#define HC_HSTOPSF_MASK         0x000001c0
#define HC_HSTOPSPZF_MASK       0x00000038
#define HC_HSTOPSPZP_MASK       0x00000007
#define HC_HSTMD_NeverPass      0x00000000
#define HC_HSTMD_LT             0x00010000
#define HC_HSTMD_EQ             0x00020000
#define HC_HSTMD_LE             0x00030000
#define HC_HSTMD_GT             0x00040000
#define HC_HSTMD_NE             0x00050000
#define HC_HSTMD_GE             0x00060000
#define HC_HSTMD_AllPass        0x00070000
#define HC_HSTOPSF_KEEP         0x00000000
#define HC_HSTOPSF_ZERO         0x00000040
#define HC_HSTOPSF_REPLACE      0x00000080
#define HC_HSTOPSF_INCRSAT      0x000000c0
#define HC_HSTOPSF_DECRSAT      0x00000100
#define HC_HSTOPSF_INVERT       0x00000140
#define HC_HSTOPSF_INCR         0x00000180
#define HC_HSTOPSF_DECR         0x000001c0
#define HC_HSTOPSPZF_KEEP       0x00000000
#define HC_HSTOPSPZF_ZERO       0x00000008
#define HC_HSTOPSPZF_REPLACE    0x00000010
#define HC_HSTOPSPZF_INCRSAT    0x00000018
#define HC_HSTOPSPZF_DECRSAT    0x00000020
#define HC_HSTOPSPZF_INVERT     0x00000028
#define HC_HSTOPSPZF_INCR       0x00000030
#define HC_HSTOPSPZF_DECR       0x00000038
#define HC_HSTOPSPZP_KEEP       0x00000000
#define HC_HSTOPSPZP_ZERO       0x00000001
#define HC_HSTOPSPZP_REPLACE    0x00000002
#define HC_HSTOPSPZP_INCRSAT    0x00000003
#define HC_HSTOPSPZP_DECRSAT    0x00000004
#define HC_HSTOPSPZP_INVERT     0x00000005
#define HC_HSTOPSPZP_INCR       0x00000006
#define HC_HSTOPSPZP_DECR       0x00000007

/* Alpha Setting
 */
#define HC_SubA_HABBasL         0x0030
#define HC_SubA_HABBasH         0x0031
#define HC_SubA_HABFM           0x0032
#define HC_SubA_HATMD           0x0033
#define HC_SubA_HABLCsat        0x0034
#define HC_SubA_HABLCop         0x0035
#define HC_SubA_HABLAsat        0x0036
#define HC_SubA_HABLAop         0x0037
#define HC_SubA_HABLRCa         0x0038
#define HC_SubA_HABLRFCa        0x0039
#define HC_SubA_HABLRCbias      0x003a
#define HC_SubA_HABLRCb         0x003b
#define HC_SubA_HABLRFCb        0x003c
#define HC_SubA_HABLRAa         0x003d
#define HC_SubA_HABLRAb         0x003e
/* HC_SubA_HABFM
 */
#define HC_HABFM_MASK           0x00030000
#define HC_HABLoc_MASK          0x0000c000
#define HC_HABPit_MASK          0x000007ff
/* HC_SubA_HATMD
 */
#define HC_HATMD_MASK           0x00000700
#define HC_HATREF_MASK          0x000000ff
#define HC_HATMD_NeverPass      0x00000000
#define HC_HATMD_LT             0x00000100
#define HC_HATMD_EQ             0x00000200
#define HC_HATMD_LE             0x00000300
#define HC_HATMD_GT             0x00000400
#define HC_HATMD_NE             0x00000500
#define HC_HATMD_GE             0x00000600
#define HC_HATMD_AllPass        0x00000700
/* HC_SubA_HABLCsat
 */
#define HC_HABLCsat_MASK        0x00010000
#define HC_HABLCa_MASK          0x0000fc00
#define HC_HABLCa_C_MASK        0x0000c000
#define HC_HABLCa_OPC_MASK      0x00003c00
#define HC_HABLFCa_MASK         0x000003f0
#define HC_HABLFCa_C_MASK       0x00000300
#define HC_HABLFCa_OPC_MASK     0x000000f0
#define HC_HABLCbias_MASK       0x0000000f
#define HC_HABLCbias_C_MASK     0x00000008
#define HC_HABLCbias_OPC_MASK   0x00000007
/*-- Define the input color.
 */
#define HC_XC_Csrc              0x00000000
#define HC_XC_Cdst              0x00000001
#define HC_XC_Asrc              0x00000002
#define HC_XC_Adst              0x00000003
#define HC_XC_Fog               0x00000004
#define HC_XC_HABLRC            0x00000005
#define HC_XC_minSrcDst         0x00000006
#define HC_XC_maxSrcDst         0x00000007
#define HC_XC_mimAsrcInvAdst    0x00000008
#define HC_XC_OPC               0x00000000
#define HC_XC_InvOPC            0x00000010
#define HC_XC_OPCp5             0x00000020
/*-- Define the input Alpha
 */
#define HC_XA_OPA               0x00000000
#define HC_XA_InvOPA            0x00000010
#define HC_XA_OPAp5             0x00000020
#define HC_XA_0                 0x00000000
#define HC_XA_Asrc              0x00000001
#define HC_XA_Adst              0x00000002
#define HC_XA_Fog               0x00000003
#define HC_XA_minAsrcFog        0x00000004
#define HC_XA_minAsrcAdst       0x00000005
#define HC_XA_maxAsrcFog        0x00000006
#define HC_XA_maxAsrcAdst       0x00000007
#define HC_XA_HABLRA            0x00000008
#define HC_XA_minAsrcInvAdst    0x00000008
#define HC_XA_HABLFRA           0x00000009
/*--
 */
#define HC_HABLCa_OPC           (HC_XC_OPC << 10)
#define HC_HABLCa_InvOPC        (HC_XC_InvOPC << 10)
#define HC_HABLCa_OPCp5         (HC_XC_OPCp5 << 10)
#define HC_HABLCa_Csrc          (HC_XC_Csrc << 10)
#define HC_HABLCa_Cdst          (HC_XC_Cdst << 10)
#define HC_HABLCa_Asrc          (HC_XC_Asrc << 10)
#define HC_HABLCa_Adst          (HC_XC_Adst << 10)
#define HC_HABLCa_Fog           (HC_XC_Fog << 10)
#define HC_HABLCa_HABLRCa       (HC_XC_HABLRC << 10)
#define HC_HABLCa_minSrcDst     (HC_XC_minSrcDst << 10)
#define HC_HABLCa_maxSrcDst     (HC_XC_maxSrcDst << 10)
#define HC_HABLFCa_OPC              (HC_XC_OPC << 4)
#define HC_HABLFCa_InvOPC           (HC_XC_InvOPC << 4)
#define HC_HABLFCa_OPCp5            (HC_XC_OPCp5 << 4)
#define HC_HABLFCa_Csrc             (HC_XC_Csrc << 4)
#define HC_HABLFCa_Cdst             (HC_XC_Cdst << 4)
#define HC_HABLFCa_Asrc             (HC_XC_Asrc << 4)
#define HC_HABLFCa_Adst             (HC_XC_Adst << 4)
#define HC_HABLFCa_Fog              (HC_XC_Fog << 4)
#define HC_HABLFCa_HABLRCa          (HC_XC_HABLRC << 4)
#define HC_HABLFCa_minSrcDst        (HC_XC_minSrcDst << 4)
#define HC_HABLFCa_maxSrcDst        (HC_XC_maxSrcDst << 4)
#define HC_HABLFCa_mimAsrcInvAdst   (HC_XC_mimAsrcInvAdst << 4)
#define HC_HABLCbias_HABLRCbias 0x00000000
#define HC_HABLCbias_Asrc       0x00000001
#define HC_HABLCbias_Adst       0x00000002
#define HC_HABLCbias_Fog        0x00000003
#define HC_HABLCbias_Cin        0x00000004
/* HC_SubA_HABLCop         0x0035
 */
#define HC_HABLdot_MASK         0x00010000
#define HC_HABLCop_MASK         0x00004000
#define HC_HABLCb_MASK          0x00003f00
#define HC_HABLCb_C_MASK        0x00003000
#define HC_HABLCb_OPC_MASK      0x00000f00
#define HC_HABLFCb_MASK         0x000000fc
#define HC_HABLFCb_C_MASK       0x000000c0
#define HC_HABLFCb_OPC_MASK     0x0000003c
#define HC_HABLCshift_MASK      0x00000003
#define HC_HABLCb_OPC           (HC_XC_OPC << 8)
#define HC_HABLCb_InvOPC        (HC_XC_InvOPC << 8)
#define HC_HABLCb_OPCp5         (HC_XC_OPCp5 << 8)
#define HC_HABLCb_Csrc          (HC_XC_Csrc << 8)
#define HC_HABLCb_Cdst          (HC_XC_Cdst << 8)
#define HC_HABLCb_Asrc          (HC_XC_Asrc << 8)
#define HC_HABLCb_Adst          (HC_XC_Adst << 8)
#define HC_HABLCb_Fog           (HC_XC_Fog << 8)
#define HC_HABLCb_HABLRCa       (HC_XC_HABLRC << 8)
#define HC_HABLCb_minSrcDst     (HC_XC_minSrcDst << 8)
#define HC_HABLCb_maxSrcDst     (HC_XC_maxSrcDst << 8)
#define HC_HABLFCb_OPC              (HC_XC_OPC << 2)
#define HC_HABLFCb_InvOPC           (HC_XC_InvOPC << 2)
#define HC_HABLFCb_OPCp5            (HC_XC_OPCp5 << 2)
#define HC_HABLFCb_Csrc             (HC_XC_Csrc << 2)
#define HC_HABLFCb_Cdst             (HC_XC_Cdst << 2)
#define HC_HABLFCb_Asrc             (HC_XC_Asrc << 2)
#define HC_HABLFCb_Adst             (HC_XC_Adst << 2)
#define HC_HABLFCb_Fog              (HC_XC_Fog << 2)
#define HC_HABLFCb_HABLRCb          (HC_XC_HABLRC << 2)
#define HC_HABLFCb_minSrcDst        (HC_XC_minSrcDst << 2)
#define HC_HABLFCb_maxSrcDst        (HC_XC_maxSrcDst << 2)
#define HC_HABLFCb_mimAsrcInvAdst   (HC_XC_mimAsrcInvAdst << 2)
/* HC_SubA_HABLAsat        0x0036
 */
#define HC_HABLAsat_MASK        0x00010000
#define HC_HABLAa_MASK          0x0000fc00
#define HC_HABLAa_A_MASK        0x0000c000
#define HC_HABLAa_OPA_MASK      0x00003c00
#define HC_HABLFAa_MASK         0x000003f0
#define HC_HABLFAa_A_MASK       0x00000300
#define HC_HABLFAa_OPA_MASK     0x000000f0
#define HC_HABLAbias_MASK       0x0000000f
#define HC_HABLAbias_A_MASK     0x00000008
#define HC_HABLAbias_OPA_MASK   0x00000007
#define HC_HABLAa_OPA           (HC_XA_OPA << 10)
#define HC_HABLAa_InvOPA        (HC_XA_InvOPA << 10)
#define HC_HABLAa_OPAp5         (HC_XA_OPAp5 << 10)
#define HC_HABLAa_0             (HC_XA_0 << 10)
#define HC_HABLAa_Asrc          (HC_XA_Asrc << 10)
#define HC_HABLAa_Adst          (HC_XA_Adst << 10)
#define HC_HABLAa_Fog           (HC_XA_Fog << 10)
#define HC_HABLAa_minAsrcFog    (HC_XA_minAsrcFog << 10)
#define HC_HABLAa_minAsrcAdst   (HC_XA_minAsrcAdst << 10)
#define HC_HABLAa_maxAsrcFog    (HC_XA_maxAsrcFog << 10)
#define HC_HABLAa_maxAsrcAdst   (HC_XA_maxAsrcAdst << 10)
#define HC_HABLAa_HABLRA        (HC_XA_HABLRA << 10)
#define HC_HABLFAa_OPA          (HC_XA_OPA << 4)
#define HC_HABLFAa_InvOPA       (HC_XA_InvOPA << 4)
#define HC_HABLFAa_OPAp5        (HC_XA_OPAp5 << 4)
#define HC_HABLFAa_0            (HC_XA_0 << 4)
#define HC_HABLFAa_Asrc         (HC_XA_Asrc << 4)
#define HC_HABLFAa_Adst         (HC_XA_Adst << 4)
#define HC_HABLFAa_Fog          (HC_XA_Fog << 4)
#define HC_HABLFAa_minAsrcFog   (HC_XA_minAsrcFog << 4)
#define HC_HABLFAa_minAsrcAdst  (HC_XA_minAsrcAdst << 4)
#define HC_HABLFAa_maxAsrcFog   (HC_XA_maxAsrcFog << 4)
#define HC_HABLFAa_maxAsrcAdst  (HC_XA_maxAsrcAdst << 4)
#define HC_HABLFAa_minAsrcInvAdst   (HC_XA_minAsrcInvAdst << 4)
#define HC_HABLFAa_HABLFRA          (HC_XA_HABLFRA << 4)
#define HC_HABLAbias_HABLRAbias 0x00000000
#define HC_HABLAbias_Asrc       0x00000001
#define HC_HABLAbias_Adst       0x00000002
#define HC_HABLAbias_Fog        0x00000003
#define HC_HABLAbias_Aaa        0x00000004
/* HC_SubA_HABLAop         0x0037
 */
#define HC_HABLAop_MASK         0x00004000
#define HC_HABLAb_MASK          0x00003f00
#define HC_HABLAb_OPA_MASK      0x00000f00
#define HC_HABLFAb_MASK         0x000000fc
#define HC_HABLFAb_OPA_MASK     0x0000003c
#define HC_HABLAshift_MASK      0x00000003
#define HC_HABLAb_OPA           (HC_XA_OPA << 8)
#define HC_HABLAb_InvOPA        (HC_XA_InvOPA << 8)
#define HC_HABLAb_OPAp5         (HC_XA_OPAp5 << 8)
#define HC_HABLAb_0             (HC_XA_0 << 8)
#define HC_HABLAb_Asrc          (HC_XA_Asrc << 8)
#define HC_HABLAb_Adst          (HC_XA_Adst << 8)
#define HC_HABLAb_Fog           (HC_XA_Fog << 8)
#define HC_HABLAb_minAsrcFog    (HC_XA_minAsrcFog << 8)
#define HC_HABLAb_minAsrcAdst   (HC_XA_minAsrcAdst << 8)
#define HC_HABLAb_maxAsrcFog    (HC_XA_maxAsrcFog << 8)
#define HC_HABLAb_maxAsrcAdst   (HC_XA_maxAsrcAdst << 8)
#define HC_HABLAb_HABLRA        (HC_XA_HABLRA << 8)
#define HC_HABLFAb_OPA          (HC_XA_OPA << 2)
#define HC_HABLFAb_InvOPA       (HC_XA_InvOPA << 2)
#define HC_HABLFAb_OPAp5        (HC_XA_OPAp5 << 2)
#define HC_HABLFAb_0            (HC_XA_0 << 2)
#define HC_HABLFAb_Asrc         (HC_XA_Asrc << 2)
#define HC_HABLFAb_Adst         (HC_XA_Adst << 2)
#define HC_HABLFAb_Fog          (HC_XA_Fog << 2)
#define HC_HABLFAb_minAsrcFog   (HC_XA_minAsrcFog << 2)
#define HC_HABLFAb_minAsrcAdst  (HC_XA_minAsrcAdst << 2)
#define HC_HABLFAb_maxAsrcFog   (HC_XA_maxAsrcFog << 2)
#define HC_HABLFAb_maxAsrcAdst  (HC_XA_maxAsrcAdst << 2)
#define HC_HABLFAb_minAsrcInvAdst   (HC_XA_minAsrcInvAdst << 2)
#define HC_HABLFAb_HABLFRA          (HC_XA_HABLFRA << 2)
/* HC_SubA_HABLRAa         0x003d
 */
#define HC_HABLRAa_MASK         0x00ff0000
#define HC_HABLRFAa_MASK        0x0000ff00
#define HC_HABLRAbias_MASK      0x000000ff
#define HC_HABLRAa_SHIFT        16
#define HC_HABLRFAa_SHIFT       8
/* HC_SubA_HABLRAb         0x003e
 */
#define HC_HABLRAb_MASK         0x0000ff00
#define HC_HABLRFAb_MASK        0x000000ff
#define HC_HABLRAb_SHIFT        8

/* Destination Setting
 */
#define HC_SubA_HDBBasL         0x0040
#define HC_SubA_HDBBasH         0x0041
#define HC_SubA_HDBFM           0x0042
#define HC_SubA_HFBBMSKL        0x0043
#define HC_SubA_HROP            0x0044
/* HC_SubA_HDBFM           0x0042
 */
#define HC_HDBFM_MASK           0x001f0000
#define HC_HDBLoc_MASK          0x0000c000
#define HC_HDBPit_MASK          0x00003fff
#define HC_HDBFM_RGB555         0x00000000
#define HC_HDBFM_RGB565         0x00010000
#define HC_HDBFM_ARGB4444       0x00020000
#define HC_HDBFM_ARGB1555       0x00030000
#define HC_HDBFM_BGR555         0x00040000
#define HC_HDBFM_BGR565         0x00050000
#define HC_HDBFM_ABGR4444       0x00060000
#define HC_HDBFM_ABGR1555       0x00070000
#define HC_HDBFM_ARGB0888       0x00080000
#define HC_HDBFM_ARGB8888       0x00090000
#define HC_HDBFM_ABGR0888       0x000a0000
#define HC_HDBFM_ABGR8888       0x000b0000
#define HC_HDBLoc_Local         0x00000000
#define HC_HDBLoc_Sys           0x00004000
/* HC_SubA_HROP            0x0044
 */
#define HC_HROP_MASK            0x00000f00
#define HC_HFBBMSKH_MASK        0x000000ff
#define HC_HROP_BLACK           0x00000000
#define HC_HROP_DPon            0x00000100
#define HC_HROP_DPna            0x00000200
#define HC_HROP_Pn              0x00000300
#define HC_HROP_PDna            0x00000400
#define HC_HROP_Dn              0x00000500
#define HC_HROP_DPx             0x00000600
#define HC_HROP_DPan            0x00000700
#define HC_HROP_DPa             0x00000800
#define HC_HROP_DPxn            0x00000900
#define HC_HROP_D               0x00000a00
#define HC_HROP_DPno            0x00000b00
#define HC_HROP_P               0x00000c00
#define HC_HROP_PDno            0x00000d00
#define HC_HROP_DPo             0x00000e00
#define HC_HROP_WHITE           0x00000f00

/* Fog Setting
 */
#define HC_SubA_HFogLF          0x0050
#define HC_SubA_HFogCL          0x0051
#define HC_SubA_HFogCH          0x0052
#define HC_SubA_HFogStL         0x0053
#define HC_SubA_HFogStH         0x0054
#define HC_SubA_HFogOOdMF       0x0055
#define HC_SubA_HFogOOdEF       0x0056
#define HC_SubA_HFogEndL        0x0057
#define HC_SubA_HFogDenst       0x0058
/* HC_SubA_FogLF           0x0050
 */
#define HC_FogLF_MASK           0x00000010
#define HC_FogEq_MASK           0x00000008
#define HC_FogMD_MASK           0x00000007
#define HC_FogMD_LocalFog        0x00000000
#define HC_FogMD_LinearFog       0x00000002
#define HC_FogMD_ExponentialFog  0x00000004
#define HC_FogMD_Exponential2Fog 0x00000005
/* #define HC_FogMD_FogTable       0x00000003 */

/* HC_SubA_HFogDenst        0x0058
 */
#define HC_FogDenst_MASK        0x001fff00
#define HC_FogEndL_MASK         0x000000ff

/* Texture subtype definitions
 */
#define HC_SubType_Tex0         0x00000000
#define HC_SubType_Tex1         0x00000001
#define HC_SubType_TexGeneral   0x000000fe

/* Attribute of texture n
 */
#define HC_SubA_HTXnL0BasL      0x0000
#define HC_SubA_HTXnL1BasL      0x0001
#define HC_SubA_HTXnL2BasL      0x0002
#define HC_SubA_HTXnL3BasL      0x0003
#define HC_SubA_HTXnL4BasL      0x0004
#define HC_SubA_HTXnL5BasL      0x0005
#define HC_SubA_HTXnL6BasL      0x0006
#define HC_SubA_HTXnL7BasL      0x0007
#define HC_SubA_HTXnL8BasL      0x0008
#define HC_SubA_HTXnL9BasL      0x0009
#define HC_SubA_HTXnLaBasL      0x000a
#define HC_SubA_HTXnLbBasL      0x000b
#define HC_SubA_HTXnLcBasL      0x000c
#define HC_SubA_HTXnLdBasL      0x000d
#define HC_SubA_HTXnLeBasL      0x000e
#define HC_SubA_HTXnLfBasL      0x000f
#define HC_SubA_HTXnL10BasL     0x0010
#define HC_SubA_HTXnL11BasL     0x0011
#define HC_SubA_HTXnL012BasH    0x0020
#define HC_SubA_HTXnL345BasH    0x0021
#define HC_SubA_HTXnL678BasH    0x0022
#define HC_SubA_HTXnL9abBasH    0x0023
#define HC_SubA_HTXnLcdeBasH    0x0024
#define HC_SubA_HTXnLf1011BasH  0x0025
#define HC_SubA_HTXnL0Pit       0x002b
#define HC_SubA_HTXnL1Pit       0x002c
#define HC_SubA_HTXnL2Pit       0x002d
#define HC_SubA_HTXnL3Pit       0x002e
#define HC_SubA_HTXnL4Pit       0x002f
#define HC_SubA_HTXnL5Pit       0x0030
#define HC_SubA_HTXnL6Pit       0x0031
#define HC_SubA_HTXnL7Pit       0x0032
#define HC_SubA_HTXnL8Pit       0x0033
#define HC_SubA_HTXnL9Pit       0x0034
#define HC_SubA_HTXnLaPit       0x0035
#define HC_SubA_HTXnLbPit       0x0036
#define HC_SubA_HTXnLcPit       0x0037
#define HC_SubA_HTXnLdPit       0x0038
#define HC_SubA_HTXnLePit       0x0039
#define HC_SubA_HTXnLfPit       0x003a
#define HC_SubA_HTXnL10Pit      0x003b
#define HC_SubA_HTXnL11Pit      0x003c
#define HC_SubA_HTXnL0_5WE      0x004b
#define HC_SubA_HTXnL6_bWE      0x004c
#define HC_SubA_HTXnLc_11WE     0x004d
#define HC_SubA_HTXnL0_5HE      0x0051
#define HC_SubA_HTXnL6_bHE      0x0052
#define HC_SubA_HTXnLc_11HE     0x0053
#define HC_SubA_HTXnL0OS        0x0077
#define HC_SubA_HTXnTB          0x0078
#define HC_SubA_HTXnMPMD        0x0079
#define HC_SubA_HTXnCLODu       0x007a
#define HC_SubA_HTXnFM          0x007b
#define HC_SubA_HTXnTRCH        0x007c
#define HC_SubA_HTXnTRCL        0x007d
#define HC_SubA_HTXnTBC         0x007e
#define HC_SubA_HTXnTRAH        0x007f
#define HC_SubA_HTXnTBLCsat     0x0080
#define HC_SubA_HTXnTBLCop      0x0081
#define HC_SubA_HTXnTBLMPfog    0x0082
#define HC_SubA_HTXnTBLAsat     0x0083
#define HC_SubA_HTXnTBLRCa      0x0085
#define HC_SubA_HTXnTBLRCb      0x0086
#define HC_SubA_HTXnTBLRCc      0x0087
#define HC_SubA_HTXnTBLRCbias   0x0088
#define HC_SubA_HTXnTBLRAa      0x0089
#define HC_SubA_HTXnTBLRFog     0x008a
#define HC_SubA_HTXnBumpM00     0x0090
#define HC_SubA_HTXnBumpM01     0x0091
#define HC_SubA_HTXnBumpM10     0x0092
#define HC_SubA_HTXnBumpM11     0x0093
#define HC_SubA_HTXnLScale      0x0094
#define HC_SubA_HTXSMD          0x0000
/* HC_SubA_HTXnL012BasH    0x0020
 */
#define HC_HTXnL0BasH_MASK      0x000000ff
#define HC_HTXnL1BasH_MASK      0x0000ff00
#define HC_HTXnL2BasH_MASK      0x00ff0000
#define HC_HTXnL1BasH_SHIFT     8
#define HC_HTXnL2BasH_SHIFT     16
/* HC_SubA_HTXnL345BasH    0x0021
 */
#define HC_HTXnL3BasH_MASK      0x000000ff
#define HC_HTXnL4BasH_MASK      0x0000ff00
#define HC_HTXnL5BasH_MASK      0x00ff0000
#define HC_HTXnL4BasH_SHIFT     8
#define HC_HTXnL5BasH_SHIFT     16
/* HC_SubA_HTXnL678BasH    0x0022
 */
#define HC_HTXnL6BasH_MASK      0x000000ff
#define HC_HTXnL7BasH_MASK      0x0000ff00
#define HC_HTXnL8BasH_MASK      0x00ff0000
#define HC_HTXnL7BasH_SHIFT     8
#define HC_HTXnL8BasH_SHIFT     16
/* HC_SubA_HTXnL9abBasH    0x0023
 */
#define HC_HTXnL9BasH_MASK      0x000000ff
#define HC_HTXnLaBasH_MASK      0x0000ff00
#define HC_HTXnLbBasH_MASK      0x00ff0000
#define HC_HTXnLaBasH_SHIFT     8
#define HC_HTXnLbBasH_SHIFT     16
/* HC_SubA_HTXnLcdeBasH    0x0024
 */
#define HC_HTXnLcBasH_MASK      0x000000ff
#define HC_HTXnLdBasH_MASK      0x0000ff00
#define HC_HTXnLeBasH_MASK      0x00ff0000
#define HC_HTXnLdBasH_SHIFT     8
#define HC_HTXnLeBasH_SHIFT     16
/* HC_SubA_HTXnLcdeBasH    0x0025
 */
#define HC_HTXnLfBasH_MASK      0x000000ff
#define HC_HTXnL10BasH_MASK      0x0000ff00
#define HC_HTXnL11BasH_MASK      0x00ff0000
#define HC_HTXnL10BasH_SHIFT     8
#define HC_HTXnL11BasH_SHIFT     16
/* HC_SubA_HTXnL0Pit       0x002b
 */
#define HC_HTXnLnPit_MASK       0x00003fff
#define HC_HTXnEnPit_MASK       0x00080000
#define HC_HTXnLnPitE_MASK      0x00f00000
#define HC_HTXnLnPitE_SHIFT     20
/* HC_SubA_HTXnL0_5WE      0x004b
 */
#define HC_HTXnL0WE_MASK        0x0000000f
#define HC_HTXnL1WE_MASK        0x000000f0
#define HC_HTXnL2WE_MASK        0x00000f00
#define HC_HTXnL3WE_MASK        0x0000f000
#define HC_HTXnL4WE_MASK        0x000f0000
#define HC_HTXnL5WE_MASK        0x00f00000
#define HC_HTXnL1WE_SHIFT       4
#define HC_HTXnL2WE_SHIFT       8
#define HC_HTXnL3WE_SHIFT       12
#define HC_HTXnL4WE_SHIFT       16
#define HC_HTXnL5WE_SHIFT       20
/* HC_SubA_HTXnL6_bWE      0x004c
 */
#define HC_HTXnL6WE_MASK        0x0000000f
#define HC_HTXnL7WE_MASK        0x000000f0
#define HC_HTXnL8WE_MASK        0x00000f00
#define HC_HTXnL9WE_MASK        0x0000f000
#define HC_HTXnLaWE_MASK        0x000f0000
#define HC_HTXnLbWE_MASK        0x00f00000
#define HC_HTXnL7WE_SHIFT       4
#define HC_HTXnL8WE_SHIFT       8
#define HC_HTXnL9WE_SHIFT       12
#define HC_HTXnLaWE_SHIFT       16
#define HC_HTXnLbWE_SHIFT       20
/* HC_SubA_HTXnLc_11WE      0x004d
 */