diff options
Diffstat (limited to 'projects/linux/core')
| -rw-r--r-- | projects/linux/core/bsp41x_clk_renesas.yaml | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/projects/linux/core/bsp41x_clk_renesas.yaml b/projects/linux/core/bsp41x_clk_renesas.yaml index 26d2f2a..5589c3d 100644 --- a/projects/linux/core/bsp41x_clk_renesas.yaml +++ b/projects/linux/core/bsp41x_clk_renesas.yaml @@ -7,7 +7,6 @@ bsp41x: - 7a967a750a3409554d72d9bc3842722e86703125 # clk: Add support parent clock in set_phase - 5e0b119a284593bbe5966da6049e2b5272830954 # clk: rcar-gen3: Add set_phase to set SDnCKCR in HS400 - 98599f0aa8efcf43299c95c392c868f74f69eda0 # clk: renesas: rcar-gen3: Add PLL clock and update z-clock for propagating frequency to parent - - ff6532cedf1b73081004e7f2b6e38e47e8234040 # clk: renesas: rcar-gen3: Add rounding for Z-clock frequency - 8be3f69874d57fc2bd3563b47ebca7fe189673b2 # clk: renesas: rcar-gen3: Add support when frequency does not propagate to parent in z clock divider - 226e92814ca5b8ea1ce789869cee131c9bc2a819 # clk: renesas: rcar-gen3: Add support ZG clock divider for R8A77990 - 97a8cbaabb27ab9b53c345798e87ff5de155cf94 # clk: renesas: rcar-gen3: Fix revision of R8A7796 for applying SD_SKIP_FIRST @@ -55,3 +54,6 @@ bsp41x: - e7a6e866fad61e16703ab2433d848926a85f5a8b # clk: renesas: r8a779a0: Add RADSP clocks - 8a6d0d59a9d4d19a1853dd5d6b89b18bc635e348 # clk: renesas: r8a779a0: Add VCPL4 clock - 60151ad45b0ded0aacab6438fbf03631b0f1c14f # clk: renesas: r8a779a0: Add WWDT clocks + +comments: + - "98599f0aa8efcf43299c95c392c868f74f69eda0: We need to upport with refactoring." |