diff options
| -rw-r--r-- | projects/linux/mm/bsp41x_simple-bridge-Validate-pixel-clock.yaml | 25 | ||||
| -rw-r--r-- | projects/linux/mm/done/bsp41x_validate-max-vga-dot-clock.yaml | 32 |
2 files changed, 25 insertions, 32 deletions
diff --git a/projects/linux/mm/bsp41x_simple-bridge-Validate-pixel-clock.yaml b/projects/linux/mm/bsp41x_simple-bridge-Validate-pixel-clock.yaml new file mode 100644 index 0000000..845c390 --- /dev/null +++ b/projects/linux/mm/bsp41x_simple-bridge-Validate-pixel-clock.yaml @@ -0,0 +1,25 @@ +title: "BSP 4.1.x upport: simple-bridge: Validate pixel clock" +team: MM +key: ed367c5b-5cf5-4f6a-9382-186ef72c2bbe +status: New + +bsp41x: + - ae5ed0b2888c3c084849e3b1b77001c4b3519f5d # drm/bridge: dumb-vga-dac: Add dot clock valid check + - fccc46cf75fd45b867c8c8501c526a92efc4d49b # arm64: dts: r8a77995-draak: Set max dot clock for vga + - 64ee34a191cefc9fd10042f785996c811c336992 # arm64: dts: r8a77990-ebisu: Set max dot clock for vga + - a117af5977b652da0abece0b1a17049db4a76d09 # arm64: dts: salvator-common: Set max dot clock for vga + +comments: + - The ADV7123 VGA DAC used on the Draak, Ebisu and Salvator-X boards has a + pixel clock rate limit of 140MHz. The simple-bridge driver should implement + a .mode_valid() operation to reject modes that require a too high clock + frequency. + + However, the ADV7123 comes in multiple variants, with different frequency + limits. Matching on the compatible string to get the frequency limit is an + option, but would lead to a proliferation of compatible strings. A + vendor-specific DT property may be a better solution. + + - The limits set in the BSP's DT sources doesn't match the AD7123's limit. + Those limits must not be copied blindly, more information is needed from the + BSP team to understand the actual hardware limits, and where they come from. diff --git a/projects/linux/mm/done/bsp41x_validate-max-vga-dot-clock.yaml b/projects/linux/mm/done/bsp41x_validate-max-vga-dot-clock.yaml deleted file mode 100644 index 00bc5f8..0000000 --- a/projects/linux/mm/done/bsp41x_validate-max-vga-dot-clock.yaml +++ /dev/null @@ -1,32 +0,0 @@ -title: Validate max VGA dot clock -team: MM -key: 2f0026f2-80ea-11eb-8800-00e04c68641b -status: Abandoned - -relationships: - -bsp41x: - - fccc46cf75fd45b867c8c8501c526a92efc4d49b # arm64: dts: r8a77995-draak: Set max dot clock for vga - - 64ee34a191cefc9fd10042f785996c811c336992 # arm64: dts: r8a77990-ebisu: Set max dot clock for vga - - a117af5977b652da0abece0b1a17049db4a76d09 # arm64: dts: salvator-common: Set max dot clock for vga - - ae5ed0b2888c3c084849e3b1b77001c4b3519f5d # drm/bridge: dumb-vga-dac: Add dot clock valid check - -upstream: - -comments: - - These patches are not suitable for upstream in their current form - - The maximum dot clock frequency isn't a property of the VGA connector, - rather, it is a property of the DU and/or the LVDS encoders. It seems - most appropriate to make it a property of the DU in which case it - should not be specified in DT, but rather be included in the driver in - the crtc .mode_valid() operation. - - Furthermore, the values in the BSP seem quite low and it is suggested - that they are validated against the hardware limits derived from the DU. - And as discuss the results of the investigation with the BSP team - as necessary. - - - Above text is copied from bsp392_validate-max-vga-dot-clock.yaml task - - - Above patches moved to bsp-41x-non-target.yaml |