#include <string>

#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <linux/videodev2.h>
#include <sys/ioctl.h>
#include <unistd.h>
#include <system_error>

#include <kms++/kms++.h>
#include <kms++util/kms++util.h>
#include <kms++util/videodevice.h>

using namespace std;
using namespace kms;

/*
 * V4L2 and DRM differ in their interpretation of YUV420::NV12
 *
 * V4L2 NV12 is a Y and UV co-located planes in a single plane buffer.
 * DRM NV12 is a Y and UV planes presented as dual plane buffer,
 * which is known as NM12 in V4L2.
 *
 * Since here we have hybrid DRM/V4L2 user space helper functions
 * we need to translate DRM::NV12 to V4L2:NM12 pixel format back
 * and forth to keep the data view consistent.
 */

/* V4L2 helper funcs */
static vector<PixelFormat> v4l2_get_formats(int fd, uint32_t buf_type)
{
	vector<PixelFormat> v;

	v4l2_fmtdesc desc{};
	desc.type = buf_type;

	while (ioctl(fd, VIDIOC_ENUM_FMT, &desc) == 0) {
		if (desc.pixelformat == V4L2_PIX_FMT_NV12M)
			v.push_back(PixelFormat::NV12);
		else if (desc.pixelformat != V4L2_PIX_FMT_NV12)
			v.push_back((PixelFormat)desc.pixelformat);

		desc.index++;
	}

	return v;
}

static void v4l2_set_format(int fd, PixelFormat fmt, uint32_t width, uint32_t height, uint32_t buf_type)
{
	int r;

	v4l2_format v4lfmt{};

	v4lfmt.type = buf_type;
	r = ioctl(fd, VIDIOC_G_FMT, &v4lfmt);
	ASSERT(r == 0);

	const PixelFormatInfo& pfi = get_pixel_format_info(fmt);

	bool mplane = buf_type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE || buf_type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;

	if (mplane) {
		v4l2_pix_format_mplane& mp = v4lfmt.fmt.pix_mp;
		uint32_t used_fmt;

		if (fmt == PixelFormat::NV12)
			used_fmt = V4L2_PIX_FMT_NV12M;
		else
			used_fmt = (uint32_t)fmt;

		mp.pixelformat = used_fmt;
		mp.width = width;
		mp.height = height;

		mp.num_planes = pfi.num_planes;

		for (unsigned i = 0; i < pfi.num_planes; ++i) {
			const PixelFormatPlaneInfo& pfpi = pfi.planes[i];
			v4l2_plane_pix_format& p = mp.plane_fmt[i];

			p.bytesperline = width * pfpi.bitspp / 8;
			p.sizeimage = p.bytesperline * height / pfpi.ysub;
		}

		r = ioctl(fd, VIDIOC_S_FMT, &v4lfmt);
		ASSERT(r == 0);

		ASSERT(mp.pixelformat == used_fmt);
		ASSERT(mp.width == width);
		ASSERT(mp.height == height);

		ASSERT(mp.num_planes == pfi.num_planes);

		for (unsigned i = 0; i < pfi.num_planes; ++i) {
			const PixelFormatPlaneInfo& pfpi = pfi.planes[i];
			v4l2_plane_pix_format& p = mp.plane_fmt[i];

			ASSERT(p.bytesperline == width * pfpi.bitspp / 8);
			ASSERT(p.sizeimage == p.bytesperline * height / pfpi.ysub);
		}
	} else {
		ASSERT(pfi.num_planes == 1);

		v4lfmt.fmt.pix.pixelformat = (uint32_t)fmt;
		v4lfmt.fmt.pix.width = width;
		v4lfmt.fmt.pix.height = height;
		v4lfmt.fmt.pix.bytesperline = width * pfi.planes[0].bitspp / 8;

		r = ioctl(fd, VIDIOC_S_FMT, &v4lfmt);
		ASSERT(r == 0);

		ASSERT(v4lfmt.fmt.pix.pixelformat == (uint32_t)fmt);
		ASSERT(v4lfmt.fmt.pix.width == width);
		ASSERT(v4lfmt.fmt.pix.height == height);
		ASSERT(v4lfmt.fmt.pix.bytesperline == width * pfi.planes[0].bitspp / 8);
	}
}

static void v4l2_get_selection(int fd, uint32_t& left, uint32_t& top, uint32_t& width, uint32_t& height, uint32_t buf_type)
{
	int r;
	struct v4l2_selection selection;

	if (buf_type == V4L2_BUF_TYPE_VIDEO_OUTPUT ||
	    buf_type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
		selection.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
		selection.target = V4L2_SEL_TGT_CROP;
	} else if (buf_type == V4L2_BUF_TYPE_VIDEO_CAPTURE ||
		   buf_type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
		selection.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
		selection.target = V4L2_SEL_TGT_COMPOSE;
	} else {
		FAIL("buf_type (%d) is not valid\n", buf_type);
	}

	r = ioctl(fd, VIDIOC_G_SELECTION, &selection);
	ASSERT(r == 0);

	left = selection.r.left;
	top = selection.r.top;
	width = selection.r.width;
	height = selection.r.height;
}

static void v4l2_set_selection(int fd, uint32_t& left, uint32_t& top, uint32_t& width, uint32_t& height, uint32_t buf_type)
{
	int r;
	struct v4l2_selection selection;

	if (buf_type == V4L2_BUF_TYPE_VIDEO_OUTPUT ||
	    buf_type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
		selection.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
		selection.target = V4L2_SEL_TGT_CROP;
	} else if (buf_type == V4L2_BUF_TYPE_VIDEO_CAPTURE ||
		   buf_type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
		selection.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
		selection.target = V4L2_SEL_TGT_COMPOSE;
	} else {
		FAIL("buf_type (%d) is not valid\n", buf_type);
	}

	selection.r.left = left;
	selection.r.top = top;
	selection.r.width = width;
	selection.r.height = height;

	r = ioctl(fd, VIDIOC_S_SELECTION, &selection);
	ASSERT(r == 0);

	left = selection.r.left;
	top = selection.r.top;
	width = selection.r.width;
	height = selection.r.height;
}

static void v4l2_request_bufs(int fd, uint32_t queue_size, uint32_t buf_type)
{
	v4l2_requestbuffers v4lreqbuf{};
	v4lreqbuf.type = buf_type;
	v4lreqbuf.memory = V4L2_MEMORY_DMABUF;
	v4lreqbuf.count = queue_size;
	int r = ioctl(fd, VIDIOC_REQBUFS, &v4lreqbuf);
	ASSERT(r == 0);
	ASSERT(v4lreqbuf.count == queue_size);
}

static void v4l2_queue_dmabuf(int fd, uint32_t index, DumbFramebuffer* fb, uint32_t buf_type)
{
	v4l2_buffer buf{};
	buf.type = buf_type;
	buf.memory = V4L2_MEMORY_DMABUF;
	buf.index = index;

	const PixelFormatInfo& pfi = get_pixel_format_info(fb->format());

	bool mplane = buf_type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE || buf_type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;

	if (mplane) {
		buf.length = pfi.num_planes;

		v4l2_plane planes[4]{};
		buf.m.planes = planes;

		for (unsigned i = 0; i < pfi.num_planes; ++i) {
			planes[i].m.fd = fb->prime_fd(i);
			planes[i].bytesused = fb->size(i);
			planes[i].length = fb->size(i);
		}

		int r = ioctl(fd, VIDIOC_QBUF, &buf);
		ASSERT(r == 0);
	} else {
		buf.m.fd = fb->prime_fd(0);

		int r = ioctl(fd, VIDIOC_QBUF, &buf);
		ASSERT(r == 0);
	}
}

static uint32_t v4l2_dequeue(int fd, uint32_t buf_type)
{
	v4l2_buffer buf{};
	buf.type = buf_type;
	buf.memory = V4L2_MEMORY_DMABUF;

	// V4L2 crashes if planes are not set
	v4l2_plane planes[4]{};
	buf.m.planes = planes;
	buf.length = 4;

	int r = ioctl(fd, VIDIOC_DQBUF, &buf);
	if (r)
		throw system_error(errno, generic_category());

	return buf.index;
}

VideoDevice::VideoDevice(const string& dev)
	: VideoDevice(::open(dev.c_str(), O_RDWR | O_NONBLOCK))
{
}

VideoDevice::VideoDevice(int fd)
	: m_fd(fd), m_has_capture(false), m_has_output(false), m_has_m2m(false)
{
	if (fd < 0)
		throw runtime_error("bad fd");

	struct v4l2_capability cap = {};
	int r = ioctl(fd, VIDIOC_QUERYCAP, &cap);
	ASSERT(r == 0);

	if (cap.capabilities & V4L2_CAP_VIDEO_CAPTURE_MPLANE) {
		m_has_capture = true;
		m_has_mplane_capture = true;
	} else if (cap.capabilities & V4L2_CAP_VIDEO_CAPTURE) {
		m_has_capture = true;
		m_has_mplane_capture = false;
	}

	if (cap.capabilities & V4L2_CAP_VIDEO_OUTPUT_MPLANE) {
		m_has_output = true;
		m_has_mplane_output = true;
	} else if (cap.capabilities & V4L2_CAP_VIDEO_OUTPUT) {
		m_has_output = true;
		m_has_mplane_output = false;
	}

	if (cap.capabilities & V4L2_CAP_VIDEO_M2M_MPLANE) {
		m_has_m2m = true;
		m_has_capture = true;
		m_has_output = true;
		m_has_mplane_m2m = true;
		m_has_mplane_capture = true;
		m_has_mplane_output = true;
	} else if (cap.capabilities & V4L2_CAP_VIDEO_M2M) {
		m_has_m2m = true;
		m_has_capture = true;
		m_has_output = true;
		m_has_mplane_m2m = false;
		m_has_mplane_capture = false;
		m_has_mplane_output = false;
	}
}

VideoDevice::~VideoDevice()
{
	::close(m_fd);
}

VideoStreamer* VideoDevice::get_capture_streamer()
{
	ASSERT(m_has_capture);

	if (!m_capture_streamer) {
		auto type = m_has_mplane_capture ? VideoStreamer::StreamerType::CaptureMulti : VideoStreamer::StreamerType::CaptureSingle;
		m_capture_streamer = std::unique_ptr<VideoStreamer>(new VideoStreamer(m_fd, type));
	}

	return m_capture_streamer.get();
}

VideoStreamer* VideoDevice::get_output_streamer()
{
	ASSERT(m_has_output);

	if (!m_output_streamer) {
		auto type = m_has_mplane_output ? VideoStreamer::StreamerType::OutputMulti : VideoStreamer::StreamerType::OutputSingle;
		m_output_streamer = std::unique_ptr<VideoStreamer>(new VideoStreamer(m_fd, type));
	}

	return m_output_streamer.get();
}

vector<tuple<uint32_t, uint32_t>> VideoDevice::get_discrete_frame_sizes(PixelFormat fmt)
{
	vector<tuple<uint32_t, uint32_t>> v;

	v4l2_frmsizeenum v4lfrms{};
	v4lfrms.pixel_format = (uint32_t)fmt;

	int r = ioctl(m_fd, VIDIOC_ENUM_FRAMESIZES, &v4lfrms);
	ASSERT(r);

	FAIL_IF(v4lfrms.type != V4L2_FRMSIZE_TYPE_DISCRETE, "No discrete frame sizes");

	while (ioctl(m_fd, VIDIOC_ENUM_FRAMESIZES, &v4lfrms) == 0) {
		v.emplace_back(v4lfrms.discrete.width, v4lfrms.discrete.height);
		v4lfrms.index++;
	};

	return v;
}

VideoDevice::VideoFrameSize VideoDevice::get_frame_sizes(PixelFormat fmt)
{
	v4l2_frmsizeenum v4lfrms{};
	v4lfrms.pixel_format = (uint32_t)fmt;

	int r = ioctl(m_fd, VIDIOC_ENUM_FRAMESIZES, &v4lfrms);
	ASSERT(r);

	FAIL_IF(v4lfrms.type == V4L2_FRMSIZE_TYPE_DISCRETE, "No continuous frame sizes");

	VideoFrameSize s;

	s.min_w = v4lfrms.stepwise.min_width;
	s.max_w = v4lfrms.stepwise.max_width;
	s.step_w = v4lfrms.stepwise.step_width;

	s.min_h = v4lfrms.stepwise.min_height;
	s.max_h = v4lfrms.stepwise.max_height;
	s.step_h = v4lfrms.stepwise.step_height;

	return s;
}

vector<string> VideoDevice::get_capture_devices()
{
	vector<string> v;

	for (int i = 0; i < 20; ++i) {
		string name = "/dev/video" + to_string(i);

		struct stat buffer;
		if (stat(name.c_str(), &buffer) != 0)
			continue;

		try {
			VideoDevice vid(name);

			if (vid.has_capture() && !vid.has_m2m())
				v.push_back(name);
		} catch (...) {
		}
	}

	return v;
}

vector<string> VideoDevice::get_m2m_devices()
{
	vector<string> v;

	for (int i = 0; i < 20; ++i) {
		string name = "/dev/video" + to_string(i);

		struct stat buffer;
		if (stat(name.c_str(), &buffer) != 0)
			continue;

		try {
			VideoDevice vid(name);

			if (vid.has_m2m())
				v.push_back(name);
		} catch (...) {
		}
	}

	return v;
}

VideoStreamer::VideoStreamer(int fd, StreamerType type)
	: m_fd(fd), m_type(type)
{
}

std::vector<string> VideoStreamer::get_ports()
{
	vector<string> v;

	switch (m_type) {
	case StreamerType::CaptureSingle:
	case StreamerType::CaptureMulti: {
		struct v4l2_input input {
		};

		while (ioctl(m_fd, VIDIOC_ENUMINPUT, &input) == 0) {
			v.push_back(string((char*)&input.name));
			input.index++;
		}

		break;
	}

	case StreamerType::OutputSingle:
	case StreamerType::OutputMulti: {
		struct v4l2_output output {
		};

		while (ioctl(m_fd, VIDIOC_ENUMOUTPUT, &output) == 0) {
			v.push_back(string((char*)&output.name));
			output.index++;
		}

		break;
	}

	default:
		FAIL("Bad StreamerType");
	}

	return v;
}

void VideoStreamer::set_port(uint32_t index)
{
	unsigned long req;

	switch (m_type) {
	case StreamerType::CaptureSingle:
	case StreamerType::CaptureMulti:
		req = VIDIOC_S_INPUT;
		break;

	case StreamerType::OutputSingle:
	case StreamerType::OutputMulti:
		req = VIDIOC_S_OUTPUT;
		break;

	default:
		FAIL("Bad StreamerType");
	}

	int r = ioctl(m_fd, req, &index);
	ASSERT(r == 0);
}

static v4l2_buf_type get_buf_type(VideoStreamer::StreamerType type)
{
	switch (type) {
	case VideoStreamer::StreamerType::CaptureSingle:
		return V4L2_BUF_TYPE_VIDEO_CAPTURE;
	case VideoStreamer::StreamerType::CaptureMulti:
		return V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
	case VideoStreamer::StreamerType::OutputSingle:
		return V4L2_BUF_TYPE_VIDEO_OUTPUT;
	case VideoStreamer::StreamerType::OutputMulti:
		return V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
	default:
		FAIL("Bad StreamerType");
	}
}

std::vector<PixelFormat> VideoStreamer::get_formats()
{
	return v4l2_get_formats(m_fd, get_buf_type(m_type));
}

void VideoStreamer::set_format(PixelFormat fmt, uint32_t width, uint32_t height)
{
	v4l2_set_format(m_fd, fmt, width, height, get_buf_type(m_type));
}

void VideoStreamer::get_selection(uint32_t& left, uint32_t& top, uint32_t& width, uint32_t& height)
{
	v4l2_get_selection(m_fd, left, top, width, height, get_buf_type(m_type));
}

void VideoStreamer::set_selection(uint32_t& left, uint32_t& top, uint32_t& width, uint32_t& height)
{
	v4l2_set_selection(m_fd, left, top, width, height, get_buf_type(m_type));
}

void VideoStreamer::set_queue_size(uint32_t queue_size)
{
	v4l2_request_bufs(m_fd, queue_size, get_buf_type(m_type));
	m_fbs.resize(queue_size);
}

void VideoStreamer::queue(DumbFramebuffer* fb)
{
	uint32_t idx;

	for (idx = 0; idx < m_fbs.size(); ++idx) {
		if (m_fbs[idx] == nullptr)
			break;
	}

	FAIL_IF(idx == m_fbs.size(), "queue full");

	m_fbs[idx] = fb;

	v4l2_queue_dmabuf(m_fd, idx, fb, get_buf_type(m_type));
}

DumbFramebuffer* VideoStreamer::dequeue()
{
	uint32_t idx = v4l2_dequeue(m_fd, get_buf_type(m_type));

	auto fb = m_fbs[idx];
	m_fbs[idx] = nullptr;

	return fb;
}

void VideoStreamer::stream_on()
{
	uint32_t buf_type = get_buf_type(m_type);
	int r = ioctl(m_fd, VIDIOC_STREAMON, &buf_type);
	FAIL_IF(r, "Failed to enable stream: %d", r);
}

void VideoStreamer::stream_off()
{
	uint32_t buf_type = get_buf_type(m_type);
	int r = ioctl(m_fd, VIDIOC_STREAMOFF, &buf_type);
	FAIL_IF(r, "Failed to disable stream: %d", r);
}
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<td class='lines'><pre><code><span class="hl com">/* r128_drv.h -- Private header for r128 driver -*- linux-c -*-</span>
<span class="hl com"> * Created: Mon Dec 13 09:51:11 1999 by faith&#64;precisioninsight.com</span>
<span class="hl com"> *</span>
<span class="hl com"> * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.</span>
<span class="hl com"> * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.</span>
<span class="hl com"> * All rights reserved.</span>
<span class="hl com"> *</span>
<span class="hl com"> * Permission is hereby granted, free of charge, to any person obtaining a</span>
<span class="hl com"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span>
<span class="hl com"> * to deal in the Software without restriction, including without limitation</span>
<span class="hl com"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span>
<span class="hl com"> * and/or sell copies of the Software, and to permit persons to whom the</span>
<span class="hl com"> * Software is furnished to do so, subject to the following conditions:</span>
<span class="hl com"> *</span>
<span class="hl com"> * The above copyright notice and this permission notice (including the next</span>
<span class="hl com"> * paragraph) shall be included in all copies or substantial portions of the</span>
<span class="hl com"> * Software.</span>
<span class="hl com"> *</span>
<span class="hl com"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</span>
<span class="hl com"> * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</span>
<span class="hl com"> * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</span>
<span class="hl com"> * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR</span>
<span class="hl com"> * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span>
<span class="hl com"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER</span>
<span class="hl com"> * DEALINGS IN THE SOFTWARE.</span>
<span class="hl com"> *</span>
<span class="hl com"> * Authors:</span>
<span class="hl com"> *    Rickard E. (Rik) Faith &lt;faith&#64;valinux.com&gt;</span>
<span class="hl com"> *    Kevin E. Martin &lt;martin&#64;valinux.com&gt;</span>
<span class="hl com"> *    Gareth Hughes &lt;gareth&#64;valinux.com&gt;</span>
<span class="hl com"> *    Michel Dänzer &lt;daenzerm&#64;student.ethz.ch&gt;</span>
<span class="hl com"> */</span>

<span class="hl ppc">#ifndef __R128_DRV_H__</span>
<span class="hl ppc">#define __R128_DRV_H__</span>

<span class="hl ppc">#define GET_RING_HEAD(ring)		DRM_READ32(  (ring)-&gt;ring_rptr, 0 )</span> <span class="hl com">/* (ring)-&gt;head */</span><span class="hl ppc"></span>
<span class="hl ppc">#define SET_RING_HEAD(ring,val)		DRM_WRITE32( (ring)-&gt;ring_rptr, 0, (val) )</span> <span class="hl com">/* (ring)-&gt;head */</span><span class="hl ppc"></span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> drm_r128_freelist <span class="hl opt">{</span>
   	<span class="hl kwb">unsigned int</span> age<span class="hl opt">;</span>
   	drm_buf_t <span class="hl opt">*</span>buf<span class="hl opt">;</span>
   	<span class="hl kwb">struct</span> drm_r128_freelist <span class="hl opt">*</span>next<span class="hl opt">;</span>
   	<span class="hl kwb">struct</span> drm_r128_freelist <span class="hl opt">*</span>prev<span class="hl opt">;</span>
<span class="hl opt">}</span> drm_r128_freelist_t<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> drm_r128_ring_buffer <span class="hl opt">{</span>
	u32 <span class="hl opt">*</span>start<span class="hl opt">;</span>
	u32 <span class="hl opt">*</span>end<span class="hl opt">;</span>
	<span class="hl kwb">int</span> size<span class="hl opt">;</span>
	<span class="hl kwb">int</span> size_l2qw<span class="hl opt">;</span>

	<span class="hl kwc">volatile</span> u32 <span class="hl opt">*</span>head<span class="hl opt">;</span>
	u32 tail<span class="hl opt">;</span>
	u32 tail_mask<span class="hl opt">;</span>
	<span class="hl kwb">int</span> space<span class="hl opt">;</span>

	<span class="hl kwb">int</span> high_mark<span class="hl opt">;</span>
	drm_local_map_t <span class="hl opt">*</span>ring_rptr<span class="hl opt">;</span>
<span class="hl opt">}</span> drm_r128_ring_buffer_t<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> drm_r128_private <span class="hl opt">{</span>
	drm_r128_ring_buffer_t ring<span class="hl opt">;</span>
	drm_r128_sarea_t <span class="hl opt">*</span>sarea_priv<span class="hl opt">;</span>

	<span class="hl kwb">int</span> cce_mode<span class="hl opt">;</span>
	<span class="hl kwb">int</span> cce_fifo_size<span class="hl opt">;</span>
	<span class="hl kwb">int</span> cce_running<span class="hl opt">;</span>

   	drm_r128_freelist_t <span class="hl opt">*</span>head<span class="hl opt">;</span>
   	drm_r128_freelist_t <span class="hl opt">*</span>tail<span class="hl opt">;</span>

	<span class="hl kwb">int</span> usec_timeout<span class="hl opt">;</span>
	<span class="hl kwb">int</span> is_pci<span class="hl opt">;</span>
	<span class="hl kwb">unsigned long</span> phys_pci_gart<span class="hl opt">;</span>
	dma_addr_t bus_pci_gart<span class="hl opt">;</span>
	<span class="hl kwb">unsigned long</span> cce_buffers_offset<span class="hl opt">;</span>

	atomic_t idle_count<span class="hl opt">;</span>

	<span class="hl kwb">int</span> page_flipping<span class="hl opt">;</span>
	<span class="hl kwb">int</span> current_page<span class="hl opt">;</span>
	u32 crtc_offset<span class="hl opt">;</span>
	u32 crtc_offset_cntl<span class="hl opt">;</span>

	u32 color_fmt<span class="hl opt">;</span>
	<span class="hl kwb">unsigned int</span> front_offset<span class="hl opt">;</span>
	<span class="hl kwb">unsigned int</span> front_pitch<span class="hl opt">;</span>
	<span class="hl kwb">unsigned int</span> back_offset<span class="hl opt">;</span>
	<span class="hl kwb">unsigned int</span> back_pitch<span class="hl opt">;</span>

	u32 depth_fmt<span class="hl opt">;</span>
	<span class="hl kwb">unsigned int</span> depth_offset<span class="hl opt">;</span>
	<span class="hl kwb">unsigned int</span> depth_pitch<span class="hl opt">;</span>
	<span class="hl kwb">unsigned int</span> span_offset<span class="hl opt">;</span>

	u32 front_pitch_offset_c<span class="hl opt">;</span>
	u32 back_pitch_offset_c<span class="hl opt">;</span>
	u32 depth_pitch_offset_c<span class="hl opt">;</span>
	u32 span_pitch_offset_c<span class="hl opt">;</span>

	drm_local_map_t <span class="hl opt">*</span>sarea<span class="hl opt">;</span>
	drm_local_map_t <span class="hl opt">*</span>fb<span class="hl opt">;</span>
	drm_local_map_t <span class="hl opt">*</span>mmio<span class="hl opt">;</span>
	drm_local_map_t <span class="hl opt">*</span>cce_ring<span class="hl opt">;</span>
	drm_local_map_t <span class="hl opt">*</span>ring_rptr<span class="hl opt">;</span>
	drm_local_map_t <span class="hl opt">*</span>buffers<span class="hl opt">;</span>
	drm_local_map_t <span class="hl opt">*</span>agp_textures<span class="hl opt">;</span>
<span class="hl opt">}</span> drm_r128_private_t<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> drm_r128_buf_priv <span class="hl opt">{</span>
	u32 age<span class="hl opt">;</span>
	<span class="hl kwb">int</span> prim<span class="hl opt">;</span>
	<span class="hl kwb">int</span> discard<span class="hl opt">;</span>
	<span class="hl kwb">int</span> dispatched<span class="hl opt">;</span>
   	drm_r128_freelist_t <span class="hl opt">*</span>list_entry<span class="hl opt">;</span>
<span class="hl opt">}</span> drm_r128_buf_priv_t<span class="hl opt">;</span>

				<span class="hl com">/* r128_cce.c */</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_cce_init</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_cce_start</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_cce_stop</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_cce_reset</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_cce_idle</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_engine_reset</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_fullscreen</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_cce_buffers</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_getparam</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>

<span class="hl kwc">extern</span> <span class="hl kwb">void</span> <span class="hl kwd">r128_freelist_reset</span><span class="hl opt">(</span> drm_device_t <span class="hl opt">*</span>dev <span class="hl opt">);</span>
<span class="hl kwc">extern</span> drm_buf_t <span class="hl opt">*</span><span class="hl kwd">r128_freelist_get</span><span class="hl opt">(</span> drm_device_t <span class="hl opt">*</span>dev <span class="hl opt">);</span>

<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_wait_ring</span><span class="hl opt">(</span> drm_r128_private_t <span class="hl opt">*</span>dev_priv<span class="hl opt">,</span> <span class="hl kwb">int</span> n <span class="hl opt">);</span>

<span class="hl kwb">static</span> __inline__ <span class="hl kwb">void</span>
<span class="hl kwd">r128_update_ring_snapshot</span><span class="hl opt">(</span> drm_r128_ring_buffer_t <span class="hl opt">*</span>ring <span class="hl opt">)</span>
<span class="hl opt">{</span>
	ring<span class="hl opt">-&gt;</span>space <span class="hl opt">= (</span><span class="hl kwd">GET_RING_HEAD</span><span class="hl opt">(</span> ring <span class="hl opt">) -</span> ring<span class="hl opt">-&gt;</span>tail<span class="hl opt">) *</span> <span class="hl kwa">sizeof</span><span class="hl opt">(</span>u32<span class="hl opt">);</span>
	<span class="hl kwa">if</span> <span class="hl opt">(</span> ring<span class="hl opt">-&gt;</span>space <span class="hl opt">&lt;=</span> <span class="hl num">0</span> <span class="hl opt">)</span>
		ring<span class="hl opt">-&gt;</span>space <span class="hl opt">+=</span> ring<span class="hl opt">-&gt;</span>size<span class="hl opt">;</span>
<span class="hl opt">}</span>

<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_do_cce_idle</span><span class="hl opt">(</span> drm_r128_private_t <span class="hl opt">*</span>dev_priv <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_do_cleanup_cce</span><span class="hl opt">(</span> drm_device_t <span class="hl opt">*</span>dev <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_do_cleanup_pageflip</span><span class="hl opt">(</span> drm_device_t <span class="hl opt">*</span>dev <span class="hl opt">);</span>

				<span class="hl com">/* r128_state.c */</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_cce_clear</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_cce_swap</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_cce_flip</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_cce_vertex</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_cce_indices</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_cce_blit</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_cce_depth</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_cce_stipple</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>
<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">r128_cce_indirect</span><span class="hl opt">(</span> DRM_IOCTL_ARGS <span class="hl opt">);</span>


<span class="hl com">/* Register definitions, register access macros and drmAddMap constants</span>
<span class="hl com"> * for Rage 128 kernel driver.</span>
<span class="hl com"> */</span>

<span class="hl ppc">#define R128_AUX_SC_CNTL		0x1660</span>
<span class="hl ppc">#	define R128_AUX1_SC_EN			(1 &lt;&lt; 0)</span>
<span class="hl ppc">#	define R128_AUX1_SC_MODE_OR		(0 &lt;&lt; 1)</span>
<span class="hl ppc">#	define R128_AUX1_SC_MODE_NAND		(1 &lt;&lt; 1)</span>
<span class="hl ppc">#	define R128_AUX2_SC_EN			(1 &lt;&lt; 2)</span>
<span class="hl ppc">#	define R128_AUX2_SC_MODE_OR		(0 &lt;&lt; 3)</span>
<span class="hl ppc">#	define R128_AUX2_SC_MODE_NAND		(1 &lt;&lt; 3)</span>
<span class="hl ppc">#	define R128_AUX3_SC_EN			(1 &lt;&lt; 4)</span>
<span class="hl ppc">#	define R128_AUX3_SC_MODE_OR		(0 &lt;&lt; 5)</span>
<span class="hl ppc">#	define R128_AUX3_SC_MODE_NAND		(1 &lt;&lt; 5)</span>
<span class="hl ppc">#define R128_AUX1_SC_LEFT		0x1664</span>
<span class="hl ppc">#define R128_AUX1_SC_RIGHT		0x1668</span>
<span class="hl ppc">#define R128_AUX1_SC_TOP		0x166c</span>
<span class="hl ppc">#define R128_AUX1_SC_BOTTOM		0x1670</span>
<span class="hl ppc">#define R128_AUX2_SC_LEFT		0x1674</span>
<span class="hl ppc">#define R128_AUX2_SC_RIGHT		0x1678</span>
<span class="hl ppc">#define R128_AUX2_SC_TOP		0x167c</span>
<span class="hl ppc">#define R128_AUX2_SC_BOTTOM		0x1680</span>
<span class="hl ppc">#define R128_AUX3_SC_LEFT		0x1684</span>
<span class="hl ppc">#define R128_AUX3_SC_RIGHT		0x1688</span>
<span class="hl ppc">#define R128_AUX3_SC_TOP		0x168c</span>
<span class="hl ppc">#define R128_AUX3_SC_BOTTOM		0x1690</span>

<span class="hl ppc">#define R128_BRUSH_DATA0		0x1480</span>
<span class="hl ppc">#define R128_BUS_CNTL			0x0030</span>
<span class="hl ppc">#	define R128_BUS_MASTER_DIS		(1 &lt;&lt; 6)</span>

<span class="hl ppc">#define R128_CLOCK_CNTL_INDEX		0x0008</span>
<span class="hl ppc">#define R128_CLOCK_CNTL_DATA		0x000c</span>
<span class="hl ppc">#	define R128_PLL_WR_EN			(1 &lt;&lt; 7)</span>
<span class="hl ppc">#define R128_CONSTANT_COLOR_C		0x1d34</span>
<span class="hl ppc">#define R128_CRTC_OFFSET		0x0224</span>
<span class="hl ppc">#define R128_CRTC_OFFSET_CNTL		0x0228</span>
<span class="hl ppc">#	define R128_CRTC_OFFSET_FLIP_CNTL	(1 &lt;&lt; 16)</span>

<span class="hl ppc">#define R128_DP_GUI_MASTER_CNTL		0x146c</span>
<span class="hl ppc">#       define R128_GMC_SRC_PITCH_OFFSET_CNTL	(1    &lt;&lt;  0)</span>
<span class="hl ppc">#       define R128_GMC_DST_PITCH_OFFSET_CNTL	(1    &lt;&lt;  1)</span>
<span class="hl ppc">#	define R128_GMC_BRUSH_SOLID_COLOR	(13   &lt;&lt;  4)</span>
<span class="hl ppc">#	define R128_GMC_BRUSH_NONE		(15   &lt;&lt;  4)</span>
<span class="hl ppc">#	define R128_GMC_DST_16BPP		(4    &lt;&lt;  8)</span>
<span class="hl ppc">#	define R128_GMC_DST_24BPP		(5    &lt;&lt;  8)</span>
<span class="hl ppc">#	define R128_GMC_DST_32BPP		(6    &lt;&lt;  8)</span>
<span class="hl ppc">#       define R128_GMC_DST_DATATYPE_SHIFT	8</span>
<span class="hl ppc">#	define R128_GMC_SRC_DATATYPE_COLOR	(3    &lt;&lt; 12)</span>
<span class="hl ppc">#	define R128_DP_SRC_SOURCE_MEMORY	(2    &lt;&lt; 24)</span>
<span class="hl ppc">#	define R128_DP_SRC_SOURCE_HOST_DATA	(3    &lt;&lt; 24)</span>
<span class="hl ppc">#	define R128_GMC_CLR_CMP_CNTL_DIS	(1    &lt;&lt; 28)</span>
<span class="hl ppc">#	define R128_GMC_AUX_CLIP_DIS		(1    &lt;&lt; 29)</span>
<span class="hl ppc">#	define R128_GMC_WR_MSK_DIS		(1    &lt;&lt; 30)</span>
<span class="hl ppc">#	define R128_ROP3_S			0x00cc0000</span>
<span class="hl ppc">#	define R128_ROP3_P			0x00f00000</span>
<span class="hl ppc">#define R128_DP_WRITE_MASK		0x16cc</span>
<span class="hl ppc">#define R128_DST_PITCH_OFFSET_C		0x1c80</span>
<span class="hl ppc">#	define R128_DST_TILE			(1 &lt;&lt; 31)</span>

<span class="hl ppc">#define R128_GEN_INT_CNTL		0x0040</span>
<span class="hl ppc">#	define R128_CRTC_VBLANK_INT_EN		(1 &lt;&lt;  0)</span>
<span class="hl ppc">#define R128_GEN_INT_STATUS		0x0044</span>
<span class="hl ppc">#	define R128_CRTC_VBLANK_INT		(1 &lt;&lt;  0)</span>
<span class="hl ppc">#	define R128_CRTC_VBLANK_INT_AK		(1 &lt;&lt;  0)</span>
<span class="hl ppc">#define R128_GEN_RESET_CNTL		0x00f0</span>
<span class="hl ppc">#	define R128_SOFT_RESET_GUI		(1 &lt;&lt;  0)</span>

<span class="hl ppc">#define R128_GUI_SCRATCH_REG0		0x15e0</span>
<span class="hl ppc">#define R128_GUI_SCRATCH_REG1		0x15e4</span>
<span class="hl ppc">#define R128_GUI_SCRATCH_REG2		0x15e8</span>
<span class="hl ppc">#define R128_GUI_SCRATCH_REG3		0x15ec</span>
<span class="hl ppc">#define R128_GUI_SCRATCH_REG4		0x15f0</span>
<span class="hl ppc">#define R128_GUI_SCRATCH_REG5		0x15f4</span>

<span class="hl ppc">#define R128_GUI_STAT			0x1740</span>
<span class="hl ppc">#	define R128_GUI_FIFOCNT_MASK		0x0fff</span>
<span class="hl ppc">#	define R128_GUI_ACTIVE			(1 &lt;&lt; 31)</span>

<span class="hl ppc">#define R128_MCLK_CNTL			0x000f</span>
<span class="hl ppc">#	define R128_FORCE_GCP			(1 &lt;&lt; 16)</span>
<span class="hl ppc">#	define R128_FORCE_PIPE3D_CP		(1 &lt;&lt; 17)</span>
<span class="hl ppc">#	define R128_FORCE_RCP			(1 &lt;&lt; 18)</span>

<span class="hl ppc">#define R128_PC_GUI_CTLSTAT		0x1748</span>
<span class="hl ppc">#define R128_PC_NGUI_CTLSTAT		0x0184</span>
<span class="hl ppc">#	define R128_PC_FLUSH_GUI		(3 &lt;&lt; 0)</span>
<span class="hl ppc">#	define R128_PC_RI_GUI			(1 &lt;&lt; 2)</span>
<span class="hl ppc">#	define R128_PC_FLUSH_ALL		0x00ff</span>
<span class="hl ppc">#	define R128_PC_BUSY			(1 &lt;&lt; 31)</span>

<span class="hl ppc">#define R128_PCI_GART_PAGE		0x017c</span>
<span class="hl ppc">#define R128_PRIM_TEX_CNTL_C		0x1cb0</span>

<span class="hl ppc">#define R128_SCALE_3D_CNTL		0x1a00</span>
<span class="hl ppc">#define R128_SEC_TEX_CNTL_C		0x1d00</span>
<span class="hl ppc">#define R128_SEC_TEXTURE_BORDER_COLOR_C	0x1d3c</span>
<span class="hl ppc">#define R128_SETUP_CNTL			0x1bc4</span>
<span class="hl ppc">#define R128_STEN_REF_MASK_C		0x1d40</span>

<span class="hl ppc">#define R128_TEX_CNTL_C			0x1c9c</span>
<span class="hl ppc">#	define R128_TEX_CACHE_FLUSH		(1 &lt;&lt; 23)</span>

<span class="hl ppc">#define R128_WAIT_UNTIL			0x1720</span>
<span class="hl ppc">#	define R128_EVENT_CRTC_OFFSET		(1 &lt;&lt; 0)</span>
<span class="hl ppc">#define R128_WINDOW_XY_OFFSET		0x1bcc</span>


<span class="hl com">/* CCE registers</span>
<span class="hl com"> */</span>
<span class="hl ppc">#define R128_PM4_BUFFER_OFFSET		0x0700</span>
<span class="hl ppc">#define R128_PM4_BUFFER_CNTL		0x0704</span>
<span class="hl ppc">#	define R128_PM4_MASK			(15 &lt;&lt; 28)</span>
<span class="hl ppc">#	define R128_PM4_NONPM4			(0  &lt;&lt; 28)</span>
<span class="hl ppc">#	define R128_PM4_192PIO			(1  &lt;&lt; 28)</span>
<span class="hl ppc">#	define R128_PM4_192BM			(2  &lt;&lt; 28)</span>
<span class="hl ppc">#	define R128_PM4_128PIO_64INDBM		(3  &lt;&lt; 28)</span>
<span class="hl ppc">#	define R128_PM4_128BM_64INDBM		(4  &lt;&lt; 28)</span>
<span class="hl ppc">#	define R128_PM4_64PIO_128INDBM		(5  &lt;&lt; 28)</span>
<span class="hl ppc">#	define R128_PM4_64BM_128INDBM		(6  &lt;&lt; 28)</span>
<span class="hl ppc">#	define R128_PM4_64PIO_64VCBM_64INDBM	(7  &lt;&lt; 28)</span>
<span class="hl ppc">#	define R128_PM4_64BM_64VCBM_64INDBM	(8  &lt;&lt; 28)</span>
<span class="hl ppc">#	define R128_PM4_64PIO_64VCPIO_64INDPIO	(15 &lt;&lt; 28)</span>

<span class="hl ppc">#define R128_PM4_BUFFER_WM_CNTL		0x0708</span>
<span class="hl ppc">#	define R128_WMA_SHIFT			0</span>
<span class="hl ppc">#	define R128_WMB_SHIFT			8</span>
<span class="hl ppc">#	define R128_WMC_SHIFT			16</span>
<span class="hl ppc">#	define R128_WB_WM_SHIFT			24</span>

<span class="hl ppc">#define R128_PM4_BUFFER_DL_RPTR_ADDR	0x070c</span>
<span class="hl ppc">#define R128_PM4_BUFFER_DL_RPTR		0x0710</span>
<span class="hl ppc">#define R128_PM4_BUFFER_DL_WPTR		0x0714</span>
<span class="hl ppc">#	define R128_PM4_BUFFER_DL_DONE		(1 &lt;&lt; 31)</span>

<span class="hl ppc">#define R128_PM4_VC_FPU_SETUP		0x071c</span>

<span class="hl ppc">#define R128_PM4_IW_INDOFF		0x0738</span>
<span class="hl ppc">#define R128_PM4_IW_INDSIZE		0x073c</span>

<span class="hl ppc">#define R128_PM4_STAT			0x07b8</span>
<span class="hl ppc">#	define R128_PM4_FIFOCNT_MASK		0x0fff</span>
<span class="hl ppc">#	define R128_PM4_BUSY			(1 &lt;&lt; 16)</span>
<span class="hl ppc">#	define R128_PM4_GUI_ACTIVE		(1 &lt;&lt; 31)</span>

<span class="hl ppc">#define R128_PM4_MICROCODE_ADDR		0x07d4</span>
<span class="hl ppc">#define R128_PM4_MICROCODE_RADDR	0x07d8</span>
<span class="hl ppc">#define R128_PM4_MICROCODE_DATAH	0x07dc</span>
<span class="hl ppc">#define R128_PM4_MICROCODE_DATAL	0x07e0</span>

<span class="hl ppc">#define R128_PM4_BUFFER_ADDR		0x07f0</span>
<span class="hl ppc">#define R128_PM4_MICRO_CNTL		0x07fc</span>
<span class="hl ppc">#	define R128_PM4_MICRO_FREERUN		(1 &lt;&lt; 30)</span>

<span class="hl ppc">#define R128_PM4_FIFO_DATA_EVEN		0x1000</span>
<span class="hl ppc">#define R128_PM4_FIFO_DATA_ODD		0x1004</span>


<span class="hl com">/* CCE command packets</span>
<span class="hl com"> */</span>
<span class="hl ppc">#define R128_CCE_PACKET0		0x00000000</span>
<span class="hl ppc">#define R128_CCE_PACKET1		0x40000000</span>
<span class="hl ppc">#define R128_CCE_PACKET2		0x80000000</span>
<span class="hl ppc">#define R128_CCE_PACKET3		0xC0000000</span>
<span class="hl ppc">#	define R128_CNTL_HOSTDATA_BLT		0x00009400</span>
<span class="hl ppc">#	define R128_CNTL_PAINT_MULTI		0x00009A00</span>
<span class="hl ppc">#	define R128_CNTL_BITBLT_MULTI		0x00009B00</span>
<span class="hl ppc">#	define R128_3D_RNDR_GEN_INDX_PRIM	0x00002300</span>

<span class="hl ppc">#define R128_CCE_PACKET_MASK		0xC0000000</span>
<span class="hl ppc">#define R128_CCE_PACKET_COUNT_MASK	0x3fff0000</span>
<span class="hl ppc">#define R128_CCE_PACKET0_REG_MASK	0x000007ff</span>
<span class="hl ppc">#define R128_CCE_PACKET1_REG0_MASK	0x000007ff</span>
<span class="hl ppc">#define R128_CCE_PACKET1_REG1_MASK	0x003ff800</span>

<span class="hl ppc">#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE		0x00000000</span>
<span class="hl ppc">#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT	0x00000001</span>
<span class="hl ppc">#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE		0x00000002</span>
<span class="hl ppc">#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE	0x00000003</span>
<span class="hl ppc">#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST	0x00000004</span>
<span class="hl ppc">#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN	0x00000005</span>
<span class="hl ppc">#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP	0x00000006</span>
<span class="hl ppc">#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2	0x00000007</span>
<span class="hl ppc">#define R128_CCE_VC_CNTL_PRIM_WALK_IND		0x00000010</span>
<span class="hl ppc">#define R128_CCE_VC_CNTL_PRIM_WALK_LIST		0x00000020</span>
<span class="hl ppc">#define R128_CCE_VC_CNTL_PRIM_WALK_RING		0x00000030</span>
<span class="hl ppc">#define R128_CCE_VC_CNTL_NUM_SHIFT		16</span>

<span class="hl ppc">#define R128_DATATYPE_VQ		0</span>
<span class="hl ppc">#define R128_DATATYPE_CI4		1</span>
<span class="hl ppc">#define R128_DATATYPE_CI8		2</span>
<span class="hl ppc">#define R128_DATATYPE_ARGB1555		3</span>
<span class="hl ppc">#define R128_DATATYPE_RGB565		4</span>
<span class="hl ppc">#define R128_DATATYPE_RGB888		5</span>
<span class="hl ppc">#define R128_DATATYPE_ARGB8888		6</span>
<span class="hl ppc">#define R128_DATATYPE_RGB332		7</span>
<span class="hl ppc">#define R128_DATATYPE_Y8		8</span>
<span class="hl ppc">#define R128_DATATYPE_RGB8		9</span>
<span class="hl ppc">#define R128_DATATYPE_CI16		10</span>
<span class="hl ppc">#define R128_DATATYPE_YVYU422		11</span>
<span class="hl ppc">#define R128_DATATYPE_VYUY422		12</span>
<span class="hl ppc">#define R128_DATATYPE_AYUV444		14</span>
<span class="hl ppc">#define R128_DATATYPE_ARGB4444		15</span>

<span class="hl com">/* Constants */</span>
<span class="hl ppc">#define R128_AGP_OFFSET			0x02000000</span>

<span class="hl ppc">#define R128_WATERMARK_L		16</span>
<span class="hl ppc">#define R128_WATERMARK_M		8</span>
<span class="hl ppc">#define R128_WATERMARK_N		8</span>
<span class="hl ppc">#define R128_WATERMARK_K		128</span>

<span class="hl ppc">#define R128_MAX_USEC_TIMEOUT		100000</span>	<span class="hl com">/* 100 ms */</span><span class="hl ppc"></span>

<span class="hl ppc">#define R128_LAST_FRAME_REG		R128_GUI_SCRATCH_REG0</span>
<span class="hl ppc">#define R128_LAST_DISPATCH_REG		R128_GUI_SCRATCH_REG1</span>
<span class="hl ppc">#define R128_MAX_VB_AGE			0x7fffffff</span>
<span class="hl ppc">#define R128_MAX_VB_VERTS		(0xffff)</span>

<span class="hl ppc">#define R128_RING_HIGH_MARK		128</span>

<span class="hl ppc">#define R128_PERFORMANCE_BOXES		0</span>

<span class="hl ppc">#define R128_READ(reg)		DRM_READ32(  dev_priv-&gt;mmio, (reg) )</span>
<span class="hl ppc">#define R128_WRITE(reg,val)	DRM_WRITE32( dev_priv-&gt;mmio, (reg), (val) )</span>
<span class="hl ppc">#define R128_READ8(reg)		DRM_READ8(   dev_priv-&gt;mmio, (reg) )</span>
<span class="hl ppc">#define R128_WRITE8(reg,val)	DRM_WRITE8(  dev_priv-&gt;mmio, (reg), (val) )</span>

<span class="hl ppc">#define R128_WRITE_PLL(addr,val)					\</span>
<span class="hl ppc">do {									\</span>
<span class="hl ppc">	R128_WRITE8(R128_CLOCK_CNTL_INDEX,				\</span>
<span class="hl ppc">		    ((addr) &amp; 0x1f) | R128_PLL_WR_EN);			\</span>
<span class="hl ppc">	R128_WRITE(R128_CLOCK_CNTL_DATA, (val));			\</span>
<span class="hl ppc">} while (0)</span>

<span class="hl kwc">extern</span> <span class="hl kwb">int</span> <span class="hl kwd">R128_READ_PLL</span><span class="hl opt">(</span>drm_device_t <span class="hl opt">*</span>dev<span class="hl opt">,</span> <span class="hl kwb">int</span> addr<span class="hl opt">);</span>


<span class="hl ppc">#define CCE_PACKET0( reg, n )		(R128_CCE_PACKET0 |		\</span>
<span class="hl ppc">					 ((n) &lt;&lt; 16) | ((reg) &gt;&gt; 2))</span>
<span class="hl ppc">#define CCE_PACKET1( reg0, reg1 )	(R128_CCE_PACKET1 |		\</span>
<span class="hl ppc">					 (((reg1) &gt;&gt; 2) &lt;&lt; 11) | ((reg0) &gt;&gt; 2))</span>
<span class="hl ppc">#define CCE_PACKET2()			(R128_CCE_PACKET2)</span>
<span class="hl ppc">#define CCE_PACKET3( pkt, n )		(R128_CCE_PACKET3 |		\</span>
<span class="hl ppc">					 (pkt) | ((n) &lt;&lt; 16))</span>


<span class="hl com">/* ================================================================