summaryrefslogtreecommitdiff
path: root/linux/README.drm
blob: 6441e01e587c09d8505e0b632feb8f96276c40ad (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
************************************************************
* For the very latest on DRI development, please see:      *
*     http://dri.sourceforge.net/                          *
************************************************************

The Direct Rendering Manager (drm) is a device-independent kernel-level
device driver that provides support for the XFree86 Direct Rendering
Infrastructure (DRI).

The DRM supports the Direct Rendering Infrastructure (DRI) in four major
ways:

    1. The DRM provides synchronized access to the graphics hardware via
       the use of an optimized two-tiered lock.

    2. The DRM enforces the DRI security policy for access to the graphics
       hardware by only allowing authenticated X11 clients access to
       restricted regions of memory.

    3. The DRM provides a generic DMA engine, complete with multiple
       queues and the ability to detect the need for an OpenGL context
       switch.

    4. The DRM is extensible via the use of small device-specific modules
       that rely extensively on the API exported by the DRM module.


Documentation on the DRI is available from:
    http://precisioninsight.com/piinsights.html

For specific information about kernel-level support, see:

    The Direct Rendering Manager, Kernel Support for the Direct Rendering
    Infrastructure
    http://precisioninsight.com/dr/drm.html

    Hardware Locking for the Direct Rendering Infrastructure
    http://precisioninsight.com/dr/locking.html

    A Security Analysis of the Direct Rendering Infrastructure
    http://precisioninsight.com/dr/security.html

************************************************************
* For the very latest on DRI development, please see:      *
*     http://dri.sourceforge.net/                          *
************************************************************
f='#n115'>115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254
/* i810_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*-
 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
 *
 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
 * 	    Jeff Hartmann <jhartmann@valinux.com>
 *
 */

#ifndef _I810_DRV_H_
#define _I810_DRV_H_

typedef struct drm_i810_buf_priv {
   	u32 *in_use;
   	int my_use_idx;
	int currently_mapped;
	void *virtual;
	void *kernel_virtual;
} drm_i810_buf_priv_t;

typedef struct _drm_i810_ring_buffer{
	int tail_mask;
	unsigned long Start;
	unsigned long End;
	unsigned long Size;
	u8 *virtual_start;
	int head;
	int tail;
	int space;
} drm_i810_ring_buffer_t;

typedef struct drm_i810_private {
	drm_map_t *sarea_map;
	drm_map_t *buffer_map;
	drm_map_t *mmio_map;

	drm_i810_sarea_t *sarea_priv;
   	drm_i810_ring_buffer_t ring;

      	void *hw_status_page;
   	unsigned long counter;

	dma_addr_t dma_status_page;

	drm_buf_t *mmap_buffer;


	u32 front_di1, back_di1, zi1;

	int back_offset;
	int depth_offset;
	int overlay_offset;
	int overlay_physical;
	int w, h;
	int pitch;
  	int back_pitch;
	int depth_pitch;

	int do_boxes;
	int dma_used;

	int current_page;
	int page_flipping;

	wait_queue_head_t irq_queue;
   	atomic_t irq_received;
   	atomic_t irq_emitted;
  
        int front_offset;
} drm_i810_private_t;

				/* i810_dma.c */
extern int  i810_dma_schedule(drm_device_t *dev, int locked);
extern int  i810_getbuf(struct inode *inode, struct file *filp,
			unsigned int cmd, unsigned long arg);
extern int  i810_dma_init(struct inode *inode, struct file *filp,
			  unsigned int cmd, unsigned long arg);
extern int  i810_dma_cleanup(drm_device_t *dev);
extern int  i810_flush_ioctl(struct inode *inode, struct file *filp,
			     unsigned int cmd, unsigned long arg);
extern void i810_reclaim_buffers(struct file *filp);
extern int  i810_getage(struct inode *inode, struct file *filp,
			unsigned int cmd, unsigned long arg);
extern int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma);

/* Obsolete:
 */
extern int i810_copybuf(struct inode *inode, struct file *filp,
			unsigned int cmd, unsigned long arg);
/* Obsolete:
 */
extern int i810_docopy(struct inode *inode, struct file *filp,
		       unsigned int cmd, unsigned long arg);

extern int i810_rstatus(struct inode *inode, struct file *filp,
			unsigned int cmd, unsigned long arg);
extern int i810_ov0_info(struct inode *inode, struct file *filp,
			unsigned int cmd, unsigned long arg);
extern int i810_fstatus(struct inode *inode, struct file *filp,
			unsigned int cmd, unsigned long arg);
extern int i810_ov0_flip(struct inode *inode, struct file *filp,
			unsigned int cmd, unsigned long arg);
extern int i810_dma_mc(struct inode *inode, struct file *filp,
			unsigned int cmd, unsigned long arg);


extern void i810_dma_quiescent(drm_device_t *dev);

int i810_dma_vertex(struct inode *inode, struct file *filp,
		    unsigned int cmd, unsigned long arg);

int i810_swap_bufs(struct inode *inode, struct file *filp,
		   unsigned int cmd, unsigned long arg);

int i810_clear_bufs(struct inode *inode, struct file *filp,
		    unsigned int cmd, unsigned long arg);

int i810_flip_bufs(struct inode *inode, struct file *filp,
		   unsigned int cmd, unsigned long arg);

#define I810_BASE(reg)		((unsigned long) \
				dev_priv->mmio_map->handle)
#define I810_ADDR(reg)		(I810_BASE(reg) + reg)
#define I810_DEREF(reg)		*(__volatile__ int *)I810_ADDR(reg)
#define I810_READ(reg)		I810_DEREF(reg)
#define I810_WRITE(reg,val) 	do { I810_DEREF(reg) = val; } while (0)
#define I810_DEREF16(reg)	*(__volatile__ u16 *)I810_ADDR(reg)
#define I810_READ16(reg)	I810_DEREF16(reg)
#define I810_WRITE16(reg,val)	do { I810_DEREF16(reg) = val; } while (0)

#define I810_VERBOSE 0
#define RING_LOCALS	unsigned int outring, ringmask; \
                        volatile char *virt;

#define BEGIN_LP_RING(n) do {						\
	if (I810_VERBOSE)                                               \
           DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", n, __FUNCTION__);	\
	if (dev_priv->ring.space < n*4)					\
		i810_wait_ring(dev, n*4);				\
	dev_priv->ring.space -= n*4;					\
	outring = dev_priv->ring.tail;					\
	ringmask = dev_priv->ring.tail_mask;				\
	virt = dev_priv->ring.virtual_start;				\
} while (0)

#define ADVANCE_LP_RING() do {				        \
	if (I810_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING\n");    	\
	dev_priv->ring.tail = outring;		        	\
	I810_WRITE(LP_RING + RING_TAIL, outring);	        \
} while(0)

#define OUT_RING(n) do {  				                \
	if (I810_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));	\
	*(volatile unsigned int *)(virt + outring) = n;	                \
	outring += 4;					                \
	outring &= ringmask;			                        \
} while (0)

#define GFX_OP_USER_INTERRUPT 		((0<<29)|(2<<23))
#define GFX_OP_BREAKPOINT_INTERRUPT	((0<<29)|(1<<23))
#define CMD_REPORT_HEAD			(7<<23)
#define CMD_STORE_DWORD_IDX		((0x21<<23) | 0x1)
#define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)

#define INST_PARSER_CLIENT   0x00000000
#define INST_OP_FLUSH        0x02000000
#define INST_FLUSH_MAP_CACHE 0x00000001


#define BB1_START_ADDR_MASK   (~0x7)
#define BB1_PROTECTED         (1<<0)
#define BB1_UNPROTECTED       (0<<0)
#define BB2_END_ADDR_MASK     (~0x7)

#define I810REG_HWSTAM		0x02098
#define I810REG_INT_IDENTITY_R	0x020a4
#define I810REG_INT_MASK_R 	0x020a8
#define I810REG_INT_ENABLE_R	0x020a0

#define LP_RING     		0x2030
#define HP_RING     		0x2040
#define RING_TAIL      		0x00
#define TAIL_ADDR		0x000FFFF8
#define RING_HEAD      		0x04
#define HEAD_WRAP_COUNT     	0xFFE00000
#define HEAD_WRAP_ONE       	0x00200000
#define HEAD_ADDR           	0x001FFFFC
#define RING_START     		0x08
#define START_ADDR          	0x00FFFFF8
#define RING_LEN       		0x0C
#define RING_NR_PAGES       	0x000FF000
#define RING_REPORT_MASK    	0x00000006
#define RING_REPORT_64K     	0x00000002
#define RING_REPORT_128K    	0x00000004
#define RING_NO_REPORT      	0x00000000
#define RING_VALID_MASK     	0x00000001
#define RING_VALID          	0x00000001
#define RING_INVALID        	0x00000000

#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
#define SC_UPDATE_SCISSOR       (0x1<<1)
#define SC_ENABLE_MASK          (0x1<<0)
#define SC_ENABLE               (0x1<<0)

#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
#define SCI_YMIN_MASK      (0xffff<<16)
#define SCI_XMIN_MASK      (0xffff<<0)
#define SCI_YMAX_MASK      (0xffff<<16)
#define SCI_XMAX_MASK      (0xffff<<0)