linux/Kconfig


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#
# Drm device configuration
#
# This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
#
config DRM
	bool "Direct Rendering Manager (XFree86 4.1.0 and higher DRI support)"
	help
	  Kernel-level support for the Direct Rendering Infrastructure (DRI)
	  introduced in XFree86 4.0. If you say Y here, you need to select
	  the module that's right for your graphics card from the list below.
	  These modules provide support for synchronization, security, and
	  DMA transfers. Please see <http://dri.sourceforge.net/> for more
	  details.  You should also select and configure AGP
	  (/dev/agpgart) support.

config DRM_TDFX
	tristate "3dfx Banshee/Voodoo3+"
	depends on DRM
	help
	  Choose this option if you have a 3dfx Banshee or Voodoo3 (or later),
	  graphics card.  If M is selected, the module will be called tdfx.

config DRM_R128
	tristate "ATI Rage 128"
	depends on DRM && PCI
	help
	  Choose this option if you have an ATI Rage 128 graphics card.  If M
	  is selected, the module will be called r128.  AGP support for
	  this card is strongly suggested (unless you have a PCI version).

config DRM_RADEON
	tristate "ATI Radeon"
	depends on DRM && PCI
	help
	  Choose this option if you have an ATI Radeon graphics card.  There
	  are both PCI and AGP versions.  You don't need to choose this to
	  run the Radeon in plain VGA mode.  There is a product page at
	  <http://www.ati.com/na/pages/products/pc/radeon32/index.html>.
	  If M is selected, the module will be called radeon.

config DRM_I810
	tristate "Intel I810"
	depends on DRM && AGP && AGP_INTEL
	help
	  Choose this option if you have an Intel I810 graphics card.  If M is
	  selected, the module will be called i810.  AGP support is required
	  for this driver to work.

config DRM_I830
	tristate "Intel 830M, 845G, 852GM, 855GM, 865G"
	depends on DRM && AGP && AGP_INTEL
	help
	  Choose this option if you have a system that has Intel 830M, 845G,
	  852GM, 855GM or 865G integrated graphics.  If M is selected, the
	  module will be called i830.  AGP support is required for this driver
	  to work. This driver will eventually be replaced by the i915 one.

config DRM_I915
	tristate "Intel 830M, 845G, 852GM, 855GM, 865G, 915G"
	depends on DRM && AGP && AGP_INTEL
	help
	  Choose this option if you have a system that has Intel 830M, 845G,
	  852GM, 855GM 865G or 915G integrated graphics.  If M is selected, the
	  module will be called i915.  AGP support is required for this driver
	  to work. This driver will eventually replace the I830 driver, when
	  later release of X start to use the new DDX and DRI.


config DRM_MGA
	tristate "Matrox g200/g400"
	depends on DRM && AGP && (!X86_64 || BROKEN)
	help
	  Choose this option if you have a Matrox G200, G400 or G450 graphics
	  card.  If M is selected, the module will be called mga.  AGP
	  support is required for this driver to work.

config DRM_SIS
	tristate "SiS video cards"
	depends on DRM && AGP
	help
	  Choose this option if you have a SiS 630 or compatible video 
          chipset. If M is selected the module will be called sis. AGP
          support is required for this driver to work.

config DRM_VIA
	tristate "Via unichrome video cards"
	depends on DRM 
	help
	  Choose this option if you have a Via unichrome or compatible video 
          chipset. If M is selected the module will be called via.

config DRM_MACH64
	tristate "ATI Rage Pro (Mach64)"
	depends on DRM && PCI
	help
	  Choose this option if you have an ATI Rage Pro (mach64 chipset)
	  graphics card.  Example cards include:  3D Rage Pro, Xpert 98,
	  3D Rage LT Pro, 3D Rage XL/XC, and 3D Rage Mobility (P/M, M1).
	  Cards earlier than ATI Rage Pro (e.g. Rage II) are not supported.
	  If M is selected, the module will be called mach64.  AGP support for
	  this card is strongly suggested (unless you have a PCI version).
/* $Id$
 * ffb_context.c: Creator/Creator3D DRI/DRM context switching.
 *
 * Copyright (C) 2000 David S. Miller (davem@redhat.com)
 *
 * Almost entirely stolen from tdfx_context.c, see there
 * for authors.
 */

#include <linux/sched.h>
#include <asm/upa.h>

#include "ffb.h"
#include "drmP.h"

#include "ffb_drv.h"

static int DRM(alloc_queue)(drm_device_t *dev, int is_2d_only)
{
	ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
	int i;

	for (i = 0; i < FFB_MAX_CTXS; i++) {
		if (fpriv->hw_state[i] == NULL)
			break;
	}
	if (i == FFB_MAX_CTXS)
		return -1;

	fpriv->hw_state[i] = kmalloc(sizeof(struct ffb_hw_context), GFP_KERNEL);
	if (fpriv->hw_state[i] == NULL)
		return -1;

	fpriv->hw_state[i]->is_2d_only = is_2d_only;

	/* Plus one because 0 is the special DRM_KERNEL_CONTEXT. */
	return i + 1;
}

static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx)
{
	ffb_fbcPtr ffb = fpriv->regs;
	struct ffb_hw_context *ctx;
	int i;

	ctx = fpriv->hw_state[idx - 1];
	if (idx == 0 || ctx == NULL)
		return;

	if (ctx->is_2d_only) {
		/* 2D applications only care about certain pieces
		 * of state.
		 */
		ctx->drawop = upa_readl(&ffb->drawop);
		ctx->ppc = upa_readl(&ffb->ppc);
		ctx->wid = upa_readl(&ffb->wid);
		ctx->fg = upa_readl(&ffb->fg);
		ctx->bg = upa_readl(&ffb->bg);
		ctx->xclip = upa_readl(&ffb->xclip);
		ctx->fbc = upa_readl(&ffb->fbc);
		ctx->rop = upa_readl(&ffb->rop);
		ctx->cmp = upa_readl(&ffb->cmp);
		ctx->matchab = upa_readl(&ffb->matchab);
		ctx->magnab = upa_readl(&ffb->magnab);
		ctx->pmask = upa_readl(&ffb->pmask);
		ctx->xpmask = upa_readl(&ffb->xpmask);
		ctx->lpat = upa_readl(&ffb->lpat);
		ctx->fontxy = upa_readl(&ffb->fontxy);
		ctx->fontw = upa_readl(&ffb->fontw);
		ctx->fontinc = upa_readl(&ffb->fontinc);

		/* stencil/stencilctl only exists on FFB2+ and later
		 * due to the introduction of 3DRAM-III.
		 */
		if (fpriv->ffb_type == ffb2_vertical_plus ||
		    fpriv->ffb_type == ffb2_horizontal_plus) {
			ctx->stencil = upa_readl(&ffb->stencil);
			ctx->stencilctl = upa_readl(&ffb->stencilctl);
		}

		for (i = 0; i < 32; i++)
			ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]);
		ctx->ucsr = upa_readl(&ffb->ucsr);
		return;
	}

	/* Fetch drawop. */
	ctx->drawop = upa_readl(&ffb->drawop);

	/* If we were saving the vertex registers, this is where
	 * we would do it.  We would save 32 32-bit words starting
	 * at ffb->suvtx.
	 */

	/* Capture rendering attributes. */

	ctx->ppc = upa_readl(&ffb->ppc);		/* Pixel Processor Control */
	ctx->wid = upa_readl(&ffb->wid);		/* Current WID */
	ctx->fg = upa_readl(&ffb->fg);			/* Constant FG color */
	ctx->bg = upa_readl(&ffb->bg);			/* Constant BG color */
	ctx->consty = upa_readl(&ffb->consty);		/* Constant Y */
	ctx->constz = upa_readl(&ffb->constz);		/* Constant Z */
	ctx->xclip = upa_readl(&ffb->xclip);		/* X plane clip */
	ctx->dcss = upa_readl(&ffb->dcss);		/* Depth Cue Scale Slope */
	ctx->vclipmin = upa_readl(&ffb->vclipmin);	/* Primary XY clip, minimum */
	ctx->vclipmax = upa_readl(&ffb->vclipmax);	/* Primary XY clip, maximum */
	ctx->vclipzmin = upa_readl(&ffb->vclipzmin);	/* Primary Z clip, minimum */
	ctx->vclipzmax = upa_readl(&ffb->vclipzmax);	/* Primary Z clip, maximum */
	ctx->dcsf = upa_readl(&ffb->dcsf);		/* Depth Cue Scale Front Bound */
	ctx->dcsb = upa_readl(&ffb->dcsb);		/* Depth Cue Scale Back Bound */
	ctx->dczf = upa_readl(&ffb->dczf);		/* Depth Cue Scale Z Front */
	ctx->dczb = upa_readl(&ffb->dczb);		/* Depth Cue Scale Z Back */
	ctx->blendc = upa_readl(&ffb->blendc);		/* Alpha Blend Control */
	ctx->blendc1 = upa_readl(&ffb->blendc1);	/* Alpha Blend Color 1 */
	ctx->blendc2 = upa_readl(&ffb->blendc2);	/* Alpha Blend Color 2 */
	ctx->fbc = upa_readl(&ffb->fbc);		/* Frame Buffer Control */
	ctx->rop = upa_readl(&ffb->rop);		/* Raster Operation */
	ctx->cmp = upa_readl(&ffb->cmp);		/* Compare Controls */
	ctx->matchab = upa_readl(&ffb->matchab);	/* Buffer A/B Match Ops */
	ctx->matchc = upa_readl(&ffb->matchc);		/* Buffer C Match Ops */
	ctx->magnab = upa_readl(&ffb->magnab);		/* Buffer A/B Magnitude Ops */
	ctx->magnc = upa_readl(&ffb->magnc);		/* Buffer C Magnitude Ops */
	ctx->pmask = upa_readl(&ffb->pmask);		/* RGB Plane Mask */
	ctx->xpmask = upa_readl(&ffb->xpmask);		/* X Plane Mask */
	ctx->ypmask = upa_readl(&ffb->ypmask);		/* Y Plane Mask */
	ctx->zpmask = upa_readl(&ffb->zpmask);		/* Z Plane Mask */

	/* Auxiliary Clips. */
	ctx->auxclip0min = upa_readl(&ffb->auxclip[0].min);
	ctx->auxclip0max = upa_readl(&ffb->auxclip[0].max);
	ctx->auxclip1min = upa_readl(&ffb->auxclip[1].min);
	ctx->auxclip1max = upa_readl(&ffb->auxclip[1].max);
	ctx->auxclip2min = upa_readl(&ffb->auxclip[2].min);
	ctx->auxclip2max = upa_readl(&ffb->auxclip[2].max);
	ctx->auxclip3min = upa_readl(&ffb->auxclip[3].min);
	ctx->auxclip3max = upa_readl(&ffb->auxclip[3].max);

	ctx->lpat = upa_readl(&ffb->lpat);		/* Line Pattern */
	ctx->fontxy = upa_readl(&ffb->fontxy);		/* XY Font Coordinate */
	ctx->fontw = upa_readl(&ffb->fontw);		/* Font Width */
	ctx->fontinc = upa_readl(&ffb->fontinc);	/* Font X/Y Increment */

	/* These registers/features only exist on FFB2 and later chips. */
	if (fpriv->ffb_type >= ffb2_prototype) {
		ctx->dcss1 = upa_readl(&ffb->dcss1);	/* Depth Cue Scale Slope 1 */
		ctx->dcss2 = upa_readl(&ffb->dcss2);	/* Depth Cue Scale Slope 2 */
		ctx->dcss2 = upa_readl(&ffb->dcss3);	/* Depth Cue Scale Slope 3 */
		ctx->dcs2  = upa_readl(&ffb->dcs2);	/* Depth Cue Scale 2 */
		ctx->dcs3  = upa_readl(&ffb->dcs3);	/* Depth Cue Scale 3 */
		ctx->dcs4  = upa_readl(&ffb->dcs4);	/* Depth Cue Scale 4 */
		ctx->dcd2  = upa_readl(&ffb->dcd2);	/* Depth Cue Depth 2 */
		ctx->dcd3  = upa_readl(&ffb->dcd3);	/* Depth Cue Depth 3 */
		ctx->dcd4  = upa_readl(&ffb->dcd4);	/* Depth Cue Depth 4 */

		/* And stencil/stencilctl only exists on FFB2+ and later
		 * due to the introduction of 3DRAM-III.
		 */
		if (fpriv->ffb_type == ffb2_vertical_plus ||
		    fpriv->ffb_type == ffb2_horizontal_plus) {
			ctx->stencil = upa_readl(&ffb->stencil);
			ctx->stencilctl = upa_readl(&ffb->stencilctl);
		}
	}

	/* Save the 32x32 area pattern. */
	for (i = 0; i < 32; i++)
		ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]);

	/* Finally, stash away the User Constol/Status Register. */
	ctx->ucsr = upa_readl(&ffb->ucsr);
}

static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx)
{
	ffb_fbcPtr ffb = fpriv->regs;
	struct ffb_hw_context *ctx;
	int i;

	ctx = fpriv->hw_state[idx - 1];
	if (idx == 0 || ctx == NULL)
		return;

	if (ctx->is_2d_only) {
		/* 2D applications only care about certain pieces
		 * of state.
		 */
		upa_writel(ctx->drawop, &ffb->drawop);

		/* If we were restoring the vertex registers, this is where
		 * we would do it.  We would restore 32 32-bit words starting
		 * at ffb->suvtx.
		 */

		upa_writel(ctx->ppc, &ffb->ppc);
		upa_writel(ctx->wid, &ffb->wid);
		upa_writel(ctx->fg,  &ffb->fg);
		upa_writel(ctx->bg, &ffb->bg);
		upa_writel(ctx->xclip, &ffb->xclip);
		upa_writel(ctx->fbc, &ffb->fbc);
		upa_writel(ctx->rop, &ffb->rop);
		upa_writel(ctx->cmp, &ffb->cmp);
		upa_writel(ctx->matchab, &ffb->matchab);
		upa_writel(ctx->magnab, &ffb->magnab);
		upa_writel(ctx->pmask, &ffb->pmask);
		upa_writel(ctx->xpmask, &ffb->xpmask);
		upa_writel(ctx->lpat, &ffb->lpat);
		upa_writel(ctx->fontxy, &ffb->fontxy);
		upa_writel(ctx->fontw, &ffb->fontw);
		upa_writel(ctx->fontinc, &ffb->fontinc);

		/* stencil/stencilctl only exists on FFB2+ and later
		 * due to the introduction of 3DRAM-III.
		 */
		if (fpriv->ffb_type == ffb2_vertical_plus ||
		    fpriv->ffb_type == ffb2_horizontal_plus) {
			upa_writel(ctx->stencil, &ffb->stencil);
			upa_writel(ctx->stencilctl, &ffb->stencilctl);
			upa_writel(0x80000000, &ffb->fbc);
			upa_writel((ctx->stencilctl | 0x80000),
				   &ffb->rawstencilctl);
			upa_writel(ctx->fbc, &ffb->fbc);
		}

		for (i = 0; i < 32; i++)
			upa_writel(ctx->area_pattern[i], &ffb->pattern[i]);
		upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr);
		return;
	}

	/* Restore drawop. */
	upa_writel(ctx->drawop, &ffb->drawop);

	/* If we were restoring the vertex registers, this is where
	 * we would do it.  We would restore 32 32-bit words starting
	 * at ffb->suvtx.
	 */

	/* Restore rendering attributes. */

	upa_writel(ctx->ppc, &ffb->ppc);		/* Pixel Processor Control */
	upa_writel(ctx->wid, &ffb->wid);		/* Current WID */
	upa_writel(ctx->fg, &ffb->fg);			/* Constant FG color */
	upa_writel(ctx->bg, &ffb->bg);			/* Constant BG color */
	upa_writel(ctx->consty, &ffb->consty);		/* Constant Y */
	upa_writel(ctx->constz, &ffb->constz);		/* Constant Z */
	upa_writel(ctx->xclip, &ffb->xclip);		/* X plane clip */
	upa_writel(ctx->dcss, &ffb->dcss);		/* Depth Cue Scale Slope */