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/*
 * Copyright 2005 Adam Jackson.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * on the rights to use, copy, modify, merge, publish, distribute, sub
 * license, and/or sell copies of the Software, and to permit persons to whom
 * the Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
 * ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

/* derived from tdfx_drv.c */

#include "drmP.h"
#include "imagine_drv.h"

#include "drm_pciids.h"

static struct drm_driver driver;

static struct pci_device_id pciidlist[] = {
    imagine_PCI_IDS
};

static int probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
    return drm_get_dev(pdev, ent, &driver);
}

static struct drm_driver driver = {
    .driver_features = DRIVER_USE_MTRR,
    .reclaim_buffers = drm_core_reclaim_buffers,
    .get_map_ofs = drm_core_get_map_ofs,
    .get_reg_ofs = drm_core_get_reg_ofs,
    .fops = {
        .owner = THIS_MODULE,
        .open = drm_open,
        .release = drm_release,
        .ioctl = drm_ioctl,
        .mmap = drm_mmap,
        .poll = drm_poll,
        .fasync = drm_fasync,
    },
    .pci_driver = {
        .name = DRIVER_NAME,
        .id_table = pciidlist,
        .probe = probe,
        .remove = __devexit_p(drm_cleanup_pci),
    },

    .name = DRIVER_NAME,
    .desc = DRIVER_DESC,
    .date = DRIVER_DATE,
    .major = DRIVER_MAJOR,
    .minor = DRIVER_MINOR,
    .patchlevel = DRIVER_PATCHLEVEL,
};

static int __init imagine_init(void)
{
    return drm_init(&driver, pciidlist);
}

static void __exit imagine_exit(void)
{
    drm_exit(&driver);
}

module_init(imagine_init);
module_exit(imagine_exit);

MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL and additional rights");
<<4) #define REG_LCDDPARST (1U<<3) #define LCD2DPAOFF (1U<<2) /*#define RESERVED_1 (1U<<1) */ #define EN_GEPWM (1U<<0) /* Enable GE power management */ #define BASE_3D_ENG 0x2800 #define M2REG_FLUSH_ENGINE_ADDRESS 0x000 #define M2REG_FLUSH_ENGINE_COMMAND 0x00 #define M2REG_FLUSH_FLIP_ENGINE_MASK (ONE_BIT_MASK<<21) #define M2REG_FLUSH_2D_ENGINE_MASK (ONE_BIT_MASK<<20) #define M2REG_FLUSH_3D_ENGINE_MASK TWENTY_BIT_MASK #define M2REG_RESET_ADDRESS 0x004 #define M2REG_RESET_COMMAND 0x01 #define M2REG_RESET_STATUS2_MASK (ONE_BIT_MASK<<10) #define M2REG_RESET_STATUS1_MASK (ONE_BIT_MASK<<9) #define M2REG_RESET_STATUS0_MASK (ONE_BIT_MASK<<8) #define M2REG_RESET_3DENG_MASK (ONE_BIT_MASK<<4) #define M2REG_RESET_2DENG_MASK (ONE_BIT_MASK<<2) /* Write register */ #define M2REG_AUTO_LINK_SETTING_ADDRESS 0x010 #define M2REG_AUTO_LINK_SETTING_COMMAND 0x04 #define M2REG_CLEAR_TIMER_INTERRUPT_MASK (ONE_BIT_MASK<<11) #define M2REG_CLEAR_INTERRUPT_3_MASK (ONE_BIT_MASK<<10) #define M2REG_CLEAR_INTERRUPT_2_MASK (ONE_BIT_MASK<<9) #define M2REG_CLEAR_INTERRUPT_0_MASK (ONE_BIT_MASK<<8) #define M2REG_CLEAR_COUNTERS_MASK (ONE_BIT_MASK<<4) #define M2REG_PCI_TRIGGER_MODE_MASK (ONE_BIT_MASK<<1) #define M2REG_INVALID_LIST_AUTO_INTERRUPT_MASK (ONE_BIT_MASK<<0) /* Read register */ #define M2REG_AUTO_LINK_STATUS_ADDRESS 0x010 #define M2REG_AUTO_LINK_STATUS_COMMAND 0x04 #define M2REG_ACTIVE_TIMER_INTERRUPT_MASK (ONE_BIT_MASK<<11) #define M2REG_ACTIVE_INTERRUPT_3_MASK (ONE_BIT_MASK<<10) #define M2REG_ACTIVE_INTERRUPT_2_MASK (ONE_BIT_MASK<<9) #define M2REG_ACTIVE_INTERRUPT_0_MASK (ONE_BIT_MASK<<8) #define M2REG_INVALID_LIST_AUTO_INTERRUPTED_MODE_MASK (ONE_BIT_MASK<<0) #define M2REG_PCI_TRIGGER_REGISTER_ADDRESS 0x014 #define M2REG_PCI_TRIGGER_REGISTER_COMMAND 0x05 /** * Begin instruction, double-word 0 */ #define BEGIN_STOP_STORE_CURRENT_POINTER_MASK (ONE_BIT_MASK<<22) #define BEGIN_VALID_MASK (ONE_BIT_MASK<<20) #define BEGIN_BEGIN_IDENTIFICATION_MASK TWENTY_BIT_MASK /** * Begin instruction, double-word 1 */ #define BEGIN_LINK_ENABLE_MASK (ONE_BIT_MASK<<31) #define BEGIN_COMMAND_LIST_LENGTH_MASK TWENTYTWO_BIT_MASK /* Hardware access functions */ static inline void OUT3C5B(struct drm_map * map, u8 index, u8 data) { DRM_WRITE8(map, 0x3C4, index); DRM_WRITE8(map, 0x3C5, data); } static inline void OUT3X5B(struct drm_map * map, u8 index, u8 data) { DRM_WRITE8(map, 0x3D4, index); DRM_WRITE8(map, 0x3D5, data); } static inline void OUT3CFB(struct drm_map * map, u8 index, u8 data) { DRM_WRITE8(map, 0x3CE, index); DRM_WRITE8(map, 0x3CF, data); } static inline u8 IN3C5B(struct drm_map * map, u8 index) { DRM_WRITE8(map, 0x3C4, index); return DRM_READ8(map, 0x3C5); } static inline u8 IN3X5B(struct drm_map * map, u8 index) { DRM_WRITE8(map, 0x3D4, index); return DRM_READ8(map, 0x3D5); } static inline u8 IN3CFB(struct drm_map * map, u8 index) { DRM_WRITE8(map, 0x3CE, index); return DRM_READ8(map, 0x3CF); } #endif