/*
* Copyright 2005 Stephane Marchesin.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __NOUVEAU_DRV_H__
#define __NOUVEAU_DRV_H__
#define DRIVER_AUTHOR "Stephane Marchesin"
#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
#define DRIVER_NAME "nouveau"
#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
#define DRIVER_DATE "20060213"
#define DRIVER_MAJOR 0
#define DRIVER_MINOR 0
#define DRIVER_PATCHLEVEL 11
#define NOUVEAU_FAMILY 0x0000FFFF
#define NOUVEAU_FLAGS 0xFFFF0000
#include "nouveau_drm.h"
#include "nouveau_reg.h"
#include "nouveau_bios.h"
#define MAX_NUM_DCB_ENTRIES 16
struct mem_block {
struct mem_block *next;
struct mem_block *prev;
uint64_t start;
uint64_t size;
struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
int flags;
drm_local_map_t *map;
drm_handle_t map_handle;
};
enum nouveau_flags {
NV_NFORCE =0x10000000,
NV_NFORCE2 =0x20000000
};
#define NVOBJ_ENGINE_SW 0
#define NVOBJ_ENGINE_GR 1
#define NVOBJ_ENGINE_INT 0xdeadbeef
#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
#define NVOBJ_FLAG_FAKE (1 << 3)
struct nouveau_gpuobj {
struct list_head list;
int im_channel;
struct mem_block *im_pramin;
struct mem_block *im_backing;
int im_bound;
uint32_t flags;
int refcount;
uint32_t engine;
uint32_t class;
void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
void *priv;
};
struct nouveau_gpuobj_ref {
struct list_head list;
struct nouveau_gpuobj *gpuobj;
uint32_t instance;
int channel;
int handle;
};
struct nouveau_channel
{
struct drm_device *dev;
int id;
/* owner of this fifo */
struct drm_file *file_priv;
/* mapping of the fifo itself */
drm_local_map_t *map;
/* mapping of the regs controling the fifo */
drm_local_map_t *regs;
/* Fencing */
uint32_t next_sequence;
/* DMA push buffer */
struct nouveau_gpuobj_ref *pushbuf;
struct mem_block *pushbuf_mem;
uint32_t pushbuf_base;
/* FIFO user control regs */
uint32_t user, user_size;
uint32_t put;
uint32_t get;
uint32_t ref_cnt;
/* Notifier memory */
struct mem_block *notifier_block;
struct mem_block *notifier_heap;
drm_local_map_t *notifier_map;
/* PFIFO context */
struct nouveau_gpuobj_ref *ramfc;
/* PGRAPH context */
/* XXX may be merge 2 pointers as private data ??? */
struct nouveau_gpuobj_ref *ramin_grctx;
void *pgraph_ctx;
/* NV50 VM */
struct nouveau_gpuobj *vm_pd;
struct nouveau_gpuobj_ref *vm_gart_pt;
struct nouveau_gpuobj_ref *vm_vram_pt;
/* Objects */
struct nouveau_gpuobj_ref *ramin; /* Private instmem */
struct mem_block *ramin_heap; /* Private PRAMIN heap */
struct nouveau_gpuobj_ref *ramht; /* Hash table */
struct list_head ramht_refs; /* Objects referenced by RAMHT */
};
struct nouveau_drm_channel {
struct nouveau_channel *chan;
/* DMA state */
int max, put, cur, free;
int push_free;
volatile uint32_t *pushbuf;
/* Notifiers */
uint32_t notify0_offset;
/* Buffer moves */
uint32_t m2mf_dma_source;
uint32_t m2mf_dma_destin;
};
struct nouveau_config {
struct {
int location;
int size;
} cmdbuf;
};
struct nouveau_instmem_engine {
void *priv;
int (*init)(struct drm_device *dev);
void (*takedown)(struct drm_device *dev);
int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
uint32_t *size);
void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
};
struct nouveau_mc_engine {
int (*init)(struct drm_device *dev);
void (*takedown)(struct drm_device *dev);
};
struct nouveau_timer_engine {
int (*init)(struct drm_device *dev);
void (*takedown)(struct drm_device *dev);
uint64_t (*read)(struct drm_device *dev);
};
struct nouveau_fb_engine {
int (*init)(struct drm_device *dev);
void (*takedown)(struct drm_device *dev);
};
struct nouveau_fifo_engine {
void *priv;
int channels;
int (*init)(struct drm_device *);
void (*takedown)(struct drm_device *);
int (*channel_id)(struct drm_device *);
int (*create_context)(struct nouveau_channel *);
void (*destroy_context)(struct nouveau_channel *);
int (*load_context)(struct nouveau_channel *);
int (*save_context)(struct nouveau_channel *);
};
struct nouveau_pgraph_engine {
int (*init)(struct drm_device *);
void (*takedown)(struct drm_device *);
int (*create_context)(struct nouveau_channel *);
void (*destroy_context)(struct nouveau_channel *);
int (*load_context)(struct nouveau_channel *);
int (*save_context)(struct nouveau_channel *);
};
struct nouveau_engine {
struct nouveau_instmem_engine instmem;
struct nouveau_mc_engine mc;
struct nouveau_timer_engine timer;
struct nouveau_fb_engine fb;
struct nouveau_pgraph_engine graph;
struct nouveau_fifo_engine fifo;
};
#define NOUVEAU_MAX_CHANNEL_NR 128
struct drm_nouveau_private {
enum {
NOUVEAU_CARD_INIT_DOWN,
NOUVEAU_CARD_INIT_DONE,
NOUVEAU_CARD_INIT_FAILED
} init_state;
int ttm;
/* the card type, takes NV_* as values */
int card_type;
/* exact chipset, derived from NV_PMC_BOOT_0 */
int chipset;
int flags;
drm_local_map_t *mmio;
drm_local_map_t *fb;
drm_local_map_t *ramin; /* NV40 onwards */
int fifo_alloc_count;
struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
struct nouveau_engine Engine;
struct nouveau_drm_channel channel;
/* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
struct nouveau_gpuobj *ramht;
uint32_t ramin_rsvd_vram;
uint32_t ramht_offset;
uint32_t ramht_size;
uint32_t ramht_bits;
uint32_t ramfc_offset;
uint32_t ramfc_size;
uint32_t ramro_offset;
uint32_t ramro_size;
/* base physical adresses */
uint64_t fb_phys;
uint64_t fb_available_size;
struct {
enum {
NOUVEAU_GART_NONE = 0,
NOUVEAU_GART_AGP,
NOUVEAU_GART_SGDMA
} type;
uint64_t aper_base;
uint64_t aper_size;
struct nouveau_gpuobj *sg_ctxdma;
struct page *sg_dummy_page;
dma_addr_t sg_dummy_bus;
/* nottm hack */
struct drm_ttm_backend *sg_be;
unsigned long sg_handle;
} gart_info;
/* G8x global VRAM page table */
struct nouveau_gpuobj *vm_vram_pt;
/* the mtrr covering the FB */
int fb_mtrr;
struct mem_block *agp_heap;
struct mem_block *fb_heap;
struct mem_block *fb_nomap_heap;
struct mem_block *ramin_heap;
struct mem_block *pci_heap;
/* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
uint32_t ctx_table_size;
struct nouveau_gpuobj_ref *ctx_table;
struct nouveau_config config;
struct list_head gpuobj_list;
void *display_priv; /* internal modesetting */
void *kms_priv; /* related to public interface */
/* Hook these up to the "public interface" to accomodate a certain allocation style. */
/* This is to avoid polluting the internal interface. */
void *(*alloc_crtc) (struct drm_device *dev);
void *(*alloc_output) (struct drm_device *dev);
void *(*alloc_connector) (struct drm_device *dev);
void (*free_crtc) (void *crtc);
void (*free_output) (void *output);
void (*free_connector) (void *connector);
struct bios bios;
struct {
int entries;
struct dcb_entry entry[MAX_NUM_DCB_ENTRIES];
unsigned char i2c_read[MAX_NUM_DCB_ENTRIES];
unsigned char i2c_write[MAX_NUM_DCB_ENTRIES];
} dcb_table;
};
#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
struct drm_nouveau_private *nv = dev->dev_private; \
if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
DRM_ERROR("called without init\n"); \
return -EINVAL; \
} \
} while(0)
#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id,cl,ch) do { \
struct drm_nouveau_private *nv = dev->dev_private; \
if (!nouveau_fifo_owner(dev, (cl), (id))) { \
DRM_ERROR("pid %d doesn't own channel %d\n", \
DRM_CURRENTPID, (id)); \
return -EPERM; \
} \
(ch) = nv->fifos[(id)]; \
} while(0)
/* nouveau_state.c */
extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
extern int nouveau_load(struct drm_device *, unsigned long flags);
extern in
"OR_REG", "OR_PS", "OR_WS", "OR_FB", "OR_PLL", "OR_MC", "SHIFT_LEFT_REG",
"SHIFT_LEFT_PS", "SHIFT_LEFT_WS", "SHIFT_LEFT_FB", "SHIFT_LEFT_PLL",
"SHIFT_LEFT_MC", "SHIFT_RIGHT_REG", "SHIFT_RIGHT_PS", "SHIFT_RIGHT_WS",
"SHIFT_RIGHT_FB", "SHIFT_RIGHT_PLL", "SHIFT_RIGHT_MC", "MUL_REG",
"MUL_PS", "MUL_WS", "MUL_FB", "MUL_PLL", "MUL_MC", "DIV_REG", "DIV_PS",
"DIV_WS", "DIV_FB", "DIV_PLL", "DIV_MC", "ADD_REG", "ADD_PS", "ADD_WS",
"ADD_FB", "ADD_PLL", "ADD_MC", "SUB_REG", "SUB_PS", "SUB_WS", "SUB_FB",
"SUB_PLL", "SUB_MC", "SET_ATI_PORT", "SET_PCI_PORT", "SET_SYS_IO_PORT",
"SET_REG_BLOCK", "SET_FB_BASE", "COMPARE_REG", "COMPARE_PS",
"COMPARE_WS", "COMPARE_FB", "COMPARE_PLL", "COMPARE_MC", "SWITCH",
"JUMP", "JUMP_EQUAL", "JUMP_BELOW", "JUMP_ABOVE", "JUMP_BELOW_OR_EQUAL",
"JUMP_ABOVE_OR_EQUAL", "JUMP_NOT_EQUAL", "TEST_REG", "TEST_PS", "TEST_WS",
"TEST_FB", "TEST_PLL", "TEST_MC", "DELAY_MILLISEC", "DELAY_MICROSEC",
"CALL_TABLE", "REPEAT", "CLEAR_REG", "CLEAR_PS", "CLEAR_WS", "CLEAR_FB",
"CLEAR_PLL", "CLEAR_MC", "NOP", "EOT", "MASK_REG", "MASK_PS", "MASK_WS",
"MASK_FB", "MASK_PLL", "MASK_MC", "POST_CARD", "BEEP", "SAVE_REG",
"RESTORE_REG", "SET_DATA_BLOCK", "XOR_REG", "XOR_PS", "XOR_WS", "XOR_FB",
"XOR_PLL", "XOR_MC", "SHL_REG", "SHL_PS", "SHL_WS", "SHL_FB", "SHL_PLL",
"SHL_MC", "SHR_REG", "SHR_PS", "SHR_WS", "SHR_FB", "SHR_PLL", "SHR_MC",
"DEBUG", "CTB_DS",
};
#define ATOM_TABLE_NAMES_CNT 74
static char *atom_table_names[ATOM_TABLE_NAMES_CNT]={
"ASIC_Init", "GetDisplaySurfaceSize", "ASIC_RegistersInit",
"VRAM_BlockVenderDetection", "SetClocksRatio", "MemoryControllerInit",
"GPIO_PinInit", "MemoryParamAdjust", "DVOEncoderControl",
"GPIOPinControl", "SetEngineClock", "SetMemoryClock", "SetPixelClock",
"DynamicClockGating", "ResetMemoryDLL", "ResetMemoryDevice",
"MemoryPLLInit", "EnableMemorySelfRefresh", "AdjustMemoryController",
"EnableASIC_StaticPwrMgt", "ASIC_StaticPwrMgtStatusChange",
"DAC_LoadDetection", "TMDS2EncoderControl", "LCD1OutputControl",
"DAC1EncoderControl", "DAC2EncoderControl", "DVOOutputControl",
"CV1OutputControl", "SetCRTC_DPM_State", "TVEncoderControl",
"TMDS1EncoderControl", "LVDSEncoderControl", "TV1OutputControl",
"EnableScaler", "BlankCRTC", "EnableCRTC", "GetPixelClock",
"EnableVGA_Render", "EnableVGA_Access", "SetCRTC_Timing",
"SetCRTC_OverScan", "SetCRTC_Replication", "SelectCRTC_Source",
"EnableGraphSurfaces", "UpdateCRTC_DoubleBufferRegisters",
"LUT_AutoFill", "EnableHW_IconCursor", "GetMemoryClock",
"GetEngineClock", "SetCRTC_UsingDTDTiming", "TVBootUpStdPinDetection",
"DFP2OutputControl", "VRAM_BlockDetectionByStrap", "MemoryCleanUp",
"ReadEDIDFromHWAssistedI2C", "WriteOneByteToHWAssistedI2C",
"ReadHWAssistedI2CStatus", "SpeedFanControl", "PowerConnectorDetection",
"MC_Synchronization", "ComputeMemoryEnginePLL", "MemoryRefreshConversion",
"VRAM_GetCurrentInfoBlock", "DynamicMemorySettings", "MemoryTraining",
"EnableLVDS_SS", "DFP1OutputControl", "SetVoltage", "CRT1OutputControl",
"CRT2OutputControl", "SetupHWAssistedI2CStatus", "ClockSource",
"MemoryDeviceInit", "EnableYUV",
};
#define ATOM_IO_NAMES_CNT 5
static char *atom_io_names[ATOM_IO_NAMES_CNT]={
"MM", "PLL", "MC", "PCIE", "PCIE PORT",
};
#else
#define ATOM_OP_NAMES_CNT 0
#define ATOM_TABLE_NAMES_CNT 0
#define ATOM_IO_NAMES_CNT 0
#endif
#endif