/* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*- * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Jeff Hartmann * Keith Whitwell * * Rewritten by: * Gareth Hughes */ #include "drmP.h" #include "drm.h" #include "mga_drm.h" #include "mga_drv.h" /* ================================================================ * DMA hardware state programming functions */ static void mga_emit_clip_rect( drm_mga_private_t *dev_priv, drm_clip_rect_t *box ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; unsigned int pitch = dev_priv->front_pitch; DMA_LOCALS; BEGIN_DMA( 2 ); /* Force reset of DWGCTL on G400 (eliminates clip disable bit). */ if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { DMA_BLOCK( MGA_DWGCTL, ctx->dwgctl, MGA_LEN + MGA_EXEC, 0x80000000, MGA_DWGCTL, ctx->dwgctl, MGA_LEN + MGA_EXEC, 0x80000000 ); } DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_CXBNDRY, (box->x2 << 16) | box->x1, MGA_YTOP, box->y1 * pitch, MGA_YBOT, box->y2 * pitch ); ADVANCE_DMA(); } static __inline__ void mga_g200_emit_context( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; DMA_LOCALS; BEGIN_DMA( 3 ); DMA_BLOCK( MGA_DSTORG, ctx->dstorg, MGA_MACCESS, ctx->maccess, MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl ); DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl, MGA_FOGCOL, ctx->fogcolor, MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset ); DMA_BLOCK( MGA_FCOL, ctx->fcol, MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000 ); ADVANCE_DMA(); } static __inline__ void mga_g400_emit_context( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; DMA_LOCALS; BEGIN_DMA( 4 ); DMA_BLOCK( MGA_DSTORG, ctx->dstorg, MGA_MACCESS, ctx->maccess, MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl ); DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl, MGA_FOGCOL, ctx->fogcolor, MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset ); DMA_BLOCK( MGA_WFLAG1, ctx->wflag, MGA_TDUALSTAGE0, ctx->tdualstage0, MGA_TDUALSTAGE1, ctx->tdualstage1, MGA_FCOL, ctx->fcol ); DMA_BLOCK( MGA_STENCIL, ctx->stencil, MGA_STENCILCTL, ctx->stencilctl, MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000 ); ADVANCE_DMA(); } static __inline__ void mga_g200_emit_tex0( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; DMA_LOCALS; BEGIN_DMA( 4 ); DMA_BLOCK( MGA_TEXCTL2, tex->texctl2, MGA_TEXCTL, tex->texctl, MGA_TEXFILTER, tex->texfilter, MGA_TEXBORDERCOL, tex->texbordercol ); DMA_BLOCK( MGA_TEXORG, tex->texorg, MGA_TEXORG1, tex->texorg1, MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3 ); DMA_BLOCK( MGA_TEXORG4, tex->texorg4, MGA_TEXWIDTH, tex->texwidth, MGA_TEXHEIGHT, tex->texheight, MGA_WR24, tex->texwidth ); DMA_BLOCK( MGA_WR34, tex->texheight, MGA_TEXTRANS, 0x0000ffff, MGA_TEXTRANSHIGH, 0x0000ffff, MGA_DMAPAD, 0x00000000 ); ADVANCE_DMA(); } static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; DMA_LOCALS; /* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */ /* tex->texctl, tex->texctl2); */ BEGIN_DMA( 6 ); DMA_BLOCK( MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC, MGA_TEXCTL, tex->texctl, MGA_TEXFILTER, tex->texfilter, MGA_TEXBORDERCOL, tex->texbordercol ); DMA_BLOCK( MGA_TEXORG, tex->texorg, MGA_TEXORG1, tex->texorg1, MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3 ); DMA_BLOCK( MGA_TEXORG4, tex->texorg4, MGA_TEXWIDTH, tex->texwidth, MGA_TEXHEIGHT, tex->texheight, MGA_WR49, 0x00000000 ); DMA_BLOCK( MGA_WR57, 0x00000000, MGA_WR53, 0x00000000, MGA_WR61, 0x00000000, MGA_WR52, MGA_G400_WR_MAGIC ); DMA_BLOCK( MGA_WR60, MGA_G400_WR_MAGIC, MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC, MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC, MGA_DMAPAD, 0x00000000 ); DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000, MGA_TEXTRANS, 0x0000ffff, MGA_TEXTRANSHIGH, 0x0000ffff ); ADVANCE_DMA(); } static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1]; DMA_LOCALS; /* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */ /* tex->texctl, tex->texctl2); */ BEGIN_DMA( 5 ); DMA_BLOCK( MGA_TEXCTL2, (tex->texctl2 | MGA_MAP1_ENABLE | MGA_G400_TC2_MAGIC), MGA_TEXCTL, tex->texctl, MGA_TEXFILTER, tex->texfilter, MGA_TEXBORDERCOL, tex->texbordercol ); DMA_BLOCK( MGA_TEXORG, tex->texorg, MGA_TEXORG1, tex->texorg1, MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3 ); DMA_BLOCK( MGA_TEXORG4, tex->texorg4, MGA_TEXWIDTH, tex->texwidth, MGA_TEXHEIGHT, tex->texheight, MGA_WR49, 0x00000000 ); DMA_BLOCK( MGA_WR57, 0x00000000, MGA_WR53, 0x00000000, MGA_WR61, 0x00000000, MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC ); DMA_BLOCK( MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC, MGA_TEXTRANS, 0x0000ffff, MGA_TEXTRANSHIGH, 0x0000ffff, MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC ); ADVANCE_DMA(); } static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int pipe = sarea_priv->warp_pipe; DMA_LOCALS; BEGIN_DMA( 3 ); DMA_BLOCK( MGA_WIADDR, MGA_WMODE_SUSPEND, MGA_WVRTXSZ, 0x00000007, MGA_WFLAG, 0x00000000, MGA_WR24, 0x00000000 ); DMA_BLOCK( MGA_WR25, 0x00000100, MGA_WR34, 0x00000000, MGA_WR42, 0x0000ffff, MGA_WR60, 0x0000ffff ); /* Padding required to to hardware bug. */ DMA_BLOCK( MGA_DMAPAD, 0xffffffff, MGA_DMAPAD, 0xffffffff, MGA_DMAPAD, 0xffffffff, MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] | MGA_WMODE_START | MGA_WAGP_ENABLE) ); ADVANCE_DMA(); } static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int pipe = sarea_priv->warp_pipe; DMA_LOCALS; /* printk("mga_g400_emit_pipe %x\n", pipe); */ BEGIN_DMA( 10 ); DMA_BLOCK( MGA_WIADDR2, MGA_WMODE_SUSPEND, MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000 ); if ( pipe & MGA_T2 ) { DMA_BLOCK( MGA_WVRTXSZ, 0x00001e09, MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000 ); DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000, MGA_WACCEPTSEQ, 0x00000000, MGA_WACCEPTSEQ, 0x00000000, MGA_WACCEPTSEQ, 0x1e000000 ); } else { if ( dev_priv->warp_pipe & MGA_T2 ) { /* Flush the WARP pipe */ DMA_BLOCK( MGA_YDST, 0x00000000, MGA_FXLEFT, 0x00000000, MGA_FXRIGHT, 0x00000001, MGA_DWGCTL, MGA_DWGCTL_FLUSH ); DMA_BLOCK( MGA_LEN + MGA_EXEC, 0x00000001, MGA_DWGSYNC, 0x00007000, MGA_TEXCTL2, MGA_G400_TC2_MAGIC, MGA_LEN + MGA_EXEC, 0x00000000 ); DMA_BLOCK( MGA_TEXCTL2, (MGA_DUALTEX | MGA_G400_TC2_MAGIC), MGA_LEN + MGA_EXEC, 0x00000000, MGA_TEXCTL2, MGA_G400_TC2_MAGIC, MGA_DMAPAD, 0x00000000 ); } DMA_BLOCK( MGA_WVRTXSZ, 0x00001807, MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000 ); DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000, MGA_WACCEPTSEQ, 0x00000000, MGA_WACCEPTSEQ, 0x00000000, MGA_WACCEPTSEQ, 0x18000000 ); } DMA_BLOCK( MGA_WFLAG, 0x00000000, MGA_WFLAG1, 0x00000000, MGA_WR56, MGA_G400_WR56_MAGIC, MGA_DMAPAD, 0x00000000 ); DMA_BLOCK( MGA_WR49, 0x00000000, /* tex0 */ MGA_WR57, 0x00000000, /* tex0 */ MGA_WR53, 0x00000000, /* tex1 */ MGA_WR61, 0x00000000 ); /* tex1 */ DMA_BLOCK( MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */ MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */ MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */ MGA_WR60, MGA_G400_WR_MAGIC ); /* tex1 height */ /* Padding required to to hardware bug */ DMA_BLOCK( MGA_DMAPAD, 0xffffffff, MGA_DMAPAD, 0xffffffff, MGA_DMAPAD, 0xffffffff, MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] | MGA_WMODE_START | MGA_WAGP_ENABLE) ); ADVANCE_DMA(); } static void mga_g200_emit_state( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) { mga_g200_emit_pipe( dev_priv ); dev_priv->warp_pipe = sarea_priv->warp_pipe; } if ( dirty & MGA_UPLOAD_CONTEXT ) { mga_g200_emit_context( dev_priv ); sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; } if ( dirty & MGA_UPLOAD_TEX0 ) { mga_g200_emit_tex0( dev_priv ); sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; } } static void mga_g400_emit_state( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; int multitex = sarea_priv->warp_pipe & MGA_T2; if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) { mga_g400_emit_pipe( dev_priv ); dev_priv->warp_pipe = sarea_priv->warp_pipe; } if ( dirty & MGA_UPLOAD_CONTEXT ) { mga_g400_emit_context( dev_priv ); sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; } if ( dirty & MGA_UPLOAD_TEX0 ) { mga_g400_emit_tex0( dev_priv ); sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; } if ( (dirty & MGA_UPLOAD_TEX1) && multitex ) { mga_g400_emit_tex1( dev_priv ); sarea_priv->dirty &= ~MGA_UPLOAD_TEX1; } } /* ================================================================ * SAREA state verification */ /* Disallow all write destinations except the front and backbuffer. */ static int mga_verify_context( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; if ( ctx->dstorg != dev_priv->front_offset && ctx->dstorg != dev_priv->back_offset ) { DRM_ERROR( "*** bad DSTORG: %x (front %x, back %x)\n\n", ctx->dstorg, dev_priv->front_offset, dev_priv->back_offset ); ctx->dstorg = 0; return DRM_ERR(EINVAL); } return 0; } /* Disallow texture reads from PCI space. */ static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit]; unsigned int org; org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK); if ( org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI) ) { DRM_ERROR( "*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit ); tex->texorg = 0; return DRM_ERR(EINVAL); } return 0; } static int mga_verify_state( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; int ret = 0; if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; if ( dirty & MGA_UPLOAD_CONTEXT ) ret |= mga_verify_context( dev_priv ); if ( dirty & MGA_UPLOAD_TEX0 ) ret |= mga_verify_tex( dev_priv, 0 ); if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { if ( dirty & MGA_UPLOAD_TEX1 ) ret |= mga_verify_tex( dev_priv, 1 ); if ( dirty & MGA_UPLOAD_PIPE ) ret |= ( sarea_priv->warp_pipe > MGA_MAX_G400_PIPES ); } else { if ( dirty & MGA_UPLOAD_PIPE ) ret |= ( sarea_priv->warp_pipe > MGA_MAX_G200_PIPES ); } return ( ret == 0 ); } static int mga_verify_iload( drm_mga_private_t *dev_priv, unsigned int dstorg, unsigned int length ) { if ( dstorg < dev_priv->texture_offset || dstorg + length > (dev_priv->texture_offset + dev_priv->texture_size) ) { DRM_ERROR( "*** bad iload DSTORG: 0x%x\n", dstorg ); return DRM_ERR(EINVAL); } if ( length & MGA_ILOAD_MASK ) { DRM_ERROR( "*** bad iload length: 0x%x\n", length & MGA_ILOAD_MASK ); return DRM_ERR(EINVAL); } return 0; } static int mga_verify_blit( drm_mga_private_t *dev_priv, unsigned int srcorg, unsigned int dstorg ) { if ( (srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) || (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ) { DRM_ERROR( "*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg ); return DRM_ERR(EINVAL); } return 0; } /* ================================================================ * */ static void mga_dma_dispatch_clear( drm_device_t *dev, drm_mga_clear_t *clear ) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; drm_clip_rect_t *pbox = sarea_priv->boxes; int nbox = sarea_priv->nbox; int i; DMA_LOCALS; DRM_DEBUG( "\n" ); BEGIN_DMA( 1 ); DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000, MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000 ); ADVANCE_DMA(); for ( i = 0 ; i < nbox ; i++ ) { drm_clip_rect_t *box = &pbox[i]; u32 height = box->y2 - box->y1; DRM_DEBUG( " from=%d,%d to=%d,%d\n", box->x1, box->y1, box->x2, box->y2 ); if ( clear->flags & MGA_FRONT ) { BEGIN_DMA( 2 ); DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_PLNWT, clear->color_mask, MGA_YDSTLEN, (box->y1 << 16) | height, MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_FCOL, clear->clear_color, MGA_DSTORG, dev_priv->front_offset, MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd ); ADVANCE_DMA(); } if ( clear->flags & MGA_BACK ) { BEGIN_DMA( 2 ); DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_PLNWT, clear->color_mask, MGA_YDSTLEN, (box->y1 << 16) | height, MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_FCOL, clear->clear_color, MGA_DSTORG, dev_priv->back_offset, MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd ); ADVANCE_DMA(); } if ( clear->flags & MGA_DEPTH ) { BEGIN_DMA( 2 ); DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_PLNWT, clear->depth_mask, MGA_YDSTLEN, (box->y1 << 16) | height, MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_FCOL, clear->clear_depth, MGA_DSTORG, dev_priv->depth_offset, MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd ); ADVANCE_DMA(); } } BEGIN_DMA( 1 ); /* Force reset of DWGCTL */ DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000, MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl ); ADVANCE_DMA(); FLUSH_DMA(); } static void mga_dma_dispatch_swap( drm_device_t *dev ) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; drm_clip_rect_t *pbox = sarea_priv->boxes; int nbox = sarea_priv->nbox; int i; DMA_LOCALS; DRM_DEBUG( "\n" ); sarea_priv->last_frame.head = dev_priv->prim.tail; sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap; BEGIN_DMA( 4 + nbox ); DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000, MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000 ); DMA_BLOCK( MGA_DSTORG, dev_priv->front_offset, MGA_MACCESS, dev_priv->maccess, MGA_SRCORG, dev_priv->back_offset, MGA_AR5, dev_priv->front_pitch ); DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000, MGA_PLNWT, 0xffffffff, MGA_DWGCTL, MGA_DWGCTL_COPY ); for ( i = 0 ; i < nbox ; i++ ) { drm_clip_rect_t *box = &pbox[i]; u32 height = box->y2 - box->y1; u32 start = box->y1 * dev_priv->front_pitch; DRM_DEBUG( " from=%d,%d to=%d,%d\n", box->x1, box->y1, box->x2, box->y2 ); DMA_BLOCK( MGA_AR0, start + box->x2 - 1, MGA_AR3, start + box->x1, MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1, MGA_YDSTLEN + MGA_EXEC, (box->y1 << 16) | height ); } DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_PLNWT, ctx->plnwt, MGA_SRCORG, dev_priv->front_offset, MGA_DWGCTL, ctx->dwgctl ); ADVANCE_DMA(); FLUSH_DMA(); DRM_DEBUG( "%s... done.\n", __FUNCTION__ ); } static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf ) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; u32 address = (u32) buf->bus_address; u32 length = (u32) buf->used; int i = 0; DMA_LOCALS; DRM_DEBUG( "vertex: buf=%d used=%d\n", buf->idx, buf->used ); if ( buf->used ) { buf_priv->dispatched = 1; MGA_EMIT_STATE( dev_priv, sarea_priv->dirty ); do { if ( i < sarea_priv->nbox ) { mga_emit_clip_rect( dev_priv, &sarea_priv->boxes[i] ); } BEGIN_DMA( 1 ); DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000, MGA_SECADDRESS, (address | MGA_DMA_VERTEX), MGA_SECEND, ((address + length) | MGA_PAGPXFER) ); ADVANCE_DMA(); } while ( ++i < sarea_priv->nbox ); } if ( buf_priv->discard ) { AGE_BUFFER( buf_priv ); buf->pending = 0; buf->used = 0; buf_priv->dispatched = 0; mga_freelist_put( dev, buf ); } FLUSH_DMA(); } static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf, unsigned int start, unsigned int end ) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; u32 address = (u32) buf->bus_address; int i = 0; DMA_LOCALS; DRM_DEBUG( "indices: buf=%d start=%d end=%d\n", buf->idx, start, end ); if ( start != end ) { buf_priv->dispatched = 1; MGA_EMIT_STATE( dev_priv, sarea_priv->dirty ); do { if ( i < sarea_priv->nbox ) { mga_emit_clip_rect( dev_priv, &sarea_priv->boxes[i] ); } BEGIN_DMA( 1 ); DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000, MGA_SETUPADDRESS, address + start, MGA_SETUPEND, ((address + end) | MGA_PAGPXFER) ); ADVANCE_DMA(); } while ( ++i < sarea_priv->nbox ); } if ( buf_priv->discard ) { AGE_BUFFER( buf_priv ); buf->pending = 0; buf->used = 0; buf_priv->dispatched = 0; mga_freelist_put( dev, buf ); } FLUSH_DMA(); } /* This copies a 64 byte aligned agp region to the frambuffer with a * standard blit, the ioctl needs to do checking. */ static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf, unsigned int dstorg, unsigned int length ) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state; u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM; u32 y2; DMA_LOCALS; DRM_DEBUG( "buf=%d used=%d\n", buf->idx, buf->used ); y2 = length / 64; BEGIN_DMA( 5 ); DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000, MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000 ); DMA_BLOCK( MGA_DSTORG, dstorg, MGA_MACCESS, 0x00000000, MGA_SRCORG, srcorg, MGA_AR5, 64 ); DMA_BLOCK( MGA_PITCH, 64, MGA_PLNWT, 0xffffffff, MGA_DMAPAD, 0x00000000, MGA_DWGCTL, MGA_DWGCTL_COPY ); DMA_BLOCK( MGA_AR0, 63, MGA_AR3, 0, MGA_FXBNDRY, (63 << 16) | 0, MGA_YDSTLEN + MGA_EXEC, y2 ); DMA_BLOCK( MGA_PLNWT, ctx->plnwt, MGA_SRCORG, dev_priv->front_offset, MGA_PITCH, dev_priv->front_pitch, MGA_DWGSYNC, 0x00007000 ); ADVANCE_DMA(); AGE_BUFFER( buf_priv ); buf->pending = 0; buf->used = 0; buf_priv->dispatched = 0; mga_freelist_put( dev, buf ); FLUSH_DMA(); } static void mga_dma_dispatch_blit( drm_device_t *dev, drm_mga_blit_t *blit ) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; drm_clip_rect_t *pbox = sarea_priv->boxes; int nbox = sarea_priv->nbox; u32 scandir = 0, i; DMA_LOCALS; DRM_DEBUG( "\n" ); BEGIN_DMA( 4 + nbox ); DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000, MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000 ); DMA_BLOCK( MGA_DWGCTL, MGA_DWGCTL_COPY, MGA_PLNWT, blit->planemask, MGA_SRCORG, blit->srcorg, MGA_DSTORG, blit->dstorg ); DMA_BLOCK( MGA_SGN, scandir, MGA_MACCESS, dev_priv->maccess, MGA_AR5, blit->ydir * blit->src_pitch, MGA_PITCH, blit->dst_pitch ); for ( i = 0 ; i < nbox ; i++ ) { int srcx = pbox[i].x1 + blit->delta_sx; int srcy = pbox[i].y1 + blit->delta_sy; int dstx = pbox[i].x1 + blit->delta_dx; int dsty = pbox[i].y1 + blit->delta_dy; int h = pbox[i].y2 - pbox[i].y1; int w = pbox[i].x2 - pbox[i].x1 - 1; int start; if ( blit->ydir == -1 ) { srcy = blit->height - srcy - 1; } start = srcy * blit->src_pitch + srcx; DMA_BLOCK( MGA_AR0, start + w, MGA_AR3, start, MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff), MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h ); } /* Do something to flush AGP? */ /* Force reset of DWGCTL */ DMA_BLOCK( MGA_DMAPAD, 0x00000000, MGA_PLNWT, ctx->plnwt, MGA_PITCH, dev_priv->front_pitch, MGA_DWGCTL, ctx->dwgctl ); ADVANCE_DMA(); } /* ================================================================ * */ int mga_dma_clear( DRM_IOCTL_ARGS ) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_clear_t clear; LOCK_TEST_WITH_RETURN( dev, filp ); DRM_COPY_FROM_USER_IOCTL( clear, (drm_mga_clear_t __user *)data, sizeof(clear) ); if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; WRAP_TEST_WITH_RETURN( dev_priv ); mga_dma_dispatch_clear( dev, &clear ); /* Make sure we restore the 3D state next time. */ dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; return 0; } int mga_dma_swap( DRM_IOCTL_ARGS ) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; LOCK_TEST_WITH_RETURN( dev, filp ); if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; WRAP_TEST_WITH_RETURN( dev_priv ); mga_dma_dispatch_swap( dev ); /* Make sure we restore the 3D state next time. */ dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; return 0; } int mga_dma_vertex( DRM_IOCTL_ARGS ) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; drm_buf_t *buf; drm_mga_buf_priv_t *buf_priv; drm_mga_vertex_t vertex; LOCK_TEST_WITH_RETURN( dev, filp ); DRM_COPY_FROM_USER_IOCTL( vertex, (drm_mga_vertex_t __user *)data, sizeof(vertex) ); if(vertex.idx < 0 || vertex.idx > dma->buf_count) return DRM_ERR(EINVAL); buf = dma->buflist[vertex.idx]; buf_priv = buf->dev_private; buf->used = vertex.used; buf_priv->discard = vertex.discard; if ( !mga_verify_state( dev_priv ) ) { if ( vertex.discard ) { if ( buf_priv->dispatched == 1 ) AGE_BUFFER( buf_priv ); buf_priv->dispatched = 0; mga_freelist_put( dev, buf ); } return DRM_ERR(EINVAL); } WRAP_TEST_WITH_RETURN( dev_priv ); mga_dma_dispatch_vertex( dev, buf ); return 0; } int mga_dma_indices( DRM_IOCTL_ARGS ) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; drm_buf_t *buf; drm_mga_buf_priv_t *buf_priv; drm_mga_indices_t indices; LOCK_TEST_WITH_RETURN( dev, filp ); DRM_COPY_FROM_USER_IOCTL( indices, (drm_mga_indices_t __user *)data, sizeof(indices) ); if(indices.idx < 0 || indices.idx > dma->buf_count) return DRM_ERR(EINVAL); buf = dma->buflist[indices.idx]; buf_priv = buf->dev_private; buf_priv->discard = indices.discard; if ( !mga_verify_state( dev_priv ) ) { if ( indices.discard ) { if ( buf_priv->dispatched == 1 ) AGE_BUFFER( buf_priv ); buf_priv->dispatched = 0; mga_freelist_put( dev, buf ); } return DRM_ERR(EINVAL); } WRAP_TEST_WITH_RETURN( dev_priv ); mga_dma_dispatch_indices( dev, buf, indices.start, indices.end ); return 0; } int mga_dma_iload( DRM_IOCTL_ARGS ) { DRM_DEVICE; drm_device_dma_t *dma = dev->dma; drm_mga_private_t *dev_priv = dev->dev_private; drm_buf_t *buf; drm_mga_buf_priv_t *buf_priv; drm_mga_iload_t iload; DRM_DEBUG( "\n" ); LOCK_TEST_WITH_RETURN( dev, filp ); DRM_COPY_FROM_USER_IOCTL( iload, (drm_mga_iload_t __user *)data, sizeof(iload) ); #if 0 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { if ( MGA_DMA_DEBUG ) DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ ); return DRM_ERR(EBUSY); } #endif if(iload.idx < 0 || iload.idx > dma->buf_count) return DRM_ERR(EINVAL); buf = dma->buflist[iload.idx]; buf_priv = buf->dev_private; if ( mga_verify_iload( dev_priv, iload.dstorg, iload.length ) ) { mga_freelist_put( dev, buf ); return DRM_ERR(EINVAL); } WRAP_TEST_WITH_RETURN( dev_priv ); mga_dma_dispatch_iload( dev, buf, iload.dstorg, iload.length ); /* Make sure we restore the 3D state next time. */ dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; return 0; } int mga_dma_blit( DRM_IOCTL_ARGS ) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_blit_t blit; DRM_DEBUG( "\n" ); LOCK_TEST_WITH_RETURN( dev, filp ); DRM_COPY_FROM_USER_IOCTL( blit, (drm_mga_blit_t __user *)data, sizeof(blit) ); if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; if ( mga_verify_blit( dev_priv, blit.srcorg, blit.dstorg ) ) return DRM_ERR(EINVAL); WRAP_TEST_WITH_RETURN( dev_priv ); mga_dma_dispatch_blit( dev, &blit ); /* Make sure we restore the 3D state next time. */ dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; return 0; } int mga_getparam( DRM_IOCTL_ARGS ) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_getparam_t param; int value; if ( !dev_priv ) { DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); return DRM_ERR(EINVAL); } DRM_COPY_FROM_USER_IOCTL( param, (drm_mga_getparam_t __user *)data, sizeof(param) ); DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); switch( param.param ) { case MGA_PARAM_IRQ_NR: value = dev->irq; break; default: return DRM_ERR(EINVAL); } if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { DRM_ERROR( "copy_to_user\n" ); return DRM_ERR(EFAULT); } return 0; } span class="hl ppc">#define DRM_DIR_NAME "/dev/dri" #define DRM_DEV_NAME "%s/card%d" #define DRM_CONTROL_DEV_NAME "%s/controlD%d" #define DRM_PROC_NAME "/proc/dri/" /* For backward Linux compatibility */ #define DRM_ERR_NO_DEVICE (-1001) #define DRM_ERR_NO_ACCESS (-1002) #define DRM_ERR_NOT_ROOT (-1003) #define DRM_ERR_INVALID (-1004) #define DRM_ERR_NO_FD (-1005) #define DRM_AGP_NO_HANDLE 0 typedef unsigned int drmSize, *drmSizePtr; /**< For mapped regions */ typedef void *drmAddress, **drmAddressPtr; /**< For mapped regions */ typedef struct _drmServerInfo { int (*debug_print)(const char *format, va_list ap); int (*load_module)(const char *name); void (*get_perms)(gid_t *, mode_t *); } drmServerInfo, *drmServerInfoPtr; typedef struct drmHashEntry { int fd; void (*f)(int, void *, void *); void *tagTable; } drmHashEntry; extern void *drmGetHashTable(void); extern drmHashEntry *drmGetEntry(int fd); /** * Driver version information. * * \sa drmGetVersion() and drmSetVersion(). */ typedef struct _drmVersion { int version_major; /**< Major version */ int version_minor; /**< Minor version */ int version_patchlevel; /**< Patch level */ int name_len; /**< Length of name buffer */ char *name; /**< Name of driver */ int date_len; /**< Length of date buffer */ char *date; /**< User-space buffer to hold date */ int desc_len; /**< Length of desc buffer */ char *desc; /**< User-space buffer to hold desc */ } drmVersion, *drmVersionPtr; typedef struct _drmStats { unsigned long count; /**< Number of data */ struct { unsigned long value; /**< Value from kernel */ const char *long_format; /**< Suggested format for long_name */ const char *long_name; /**< Long name for value */ const char *rate_format; /**< Suggested format for rate_name */ const char *rate_name; /**< Short name for value per second */ int isvalue; /**< True if value (vs. counter) */ const char *mult_names; /**< Multiplier names (e.g., "KGM") */ int mult; /**< Multiplier value (e.g., 1024) */ int verbose; /**< Suggest only in verbose output */ } data[15]; } drmStatsT; /* All of these enums *MUST* match with the kernel implementation -- so do *NOT* change them! (The drmlib implementation will just copy the flags instead of translating them.) */ typedef enum { DRM_FRAME_BUFFER = 0, /**< WC, no caching, no core dump */ DRM_REGISTERS = 1, /**< no caching, no core dump */ DRM_SHM = 2, /**< shared, cached */ DRM_AGP = 3, /**< AGP/GART */ DRM_SCATTER_GATHER = 4, /**< PCI scatter/gather */ DRM_CONSISTENT = 5 /**< PCI consistent */ } drmMapType; typedef enum { DRM_RESTRICTED = 0x0001, /**< Cannot be mapped to client-virtual */ DRM_READ_ONLY = 0x0002, /**< Read-only in client-virtual */ DRM_LOCKED = 0x0004, /**< Physical pages locked */ DRM_KERNEL = 0x0008, /**< Kernel requires access */ DRM_WRITE_COMBINING = 0x0010, /**< Use write-combining, if available */ DRM_CONTAINS_LOCK = 0x0020, /**< SHM page that contains lock */ DRM_REMOVABLE = 0x0040 /**< Removable mapping */ } drmMapFlags; /** * \warning These values *MUST* match drm.h */ typedef enum { /** \name Flags for DMA buffer dispatch */ /*@{*/ DRM_DMA_BLOCK = 0x01, /**< * Block until buffer dispatched. * * \note the buffer may not yet have been * processed by the hardware -- getting a * hardware lock with the hardware quiescent * will ensure that the buffer has been * processed. */ DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ /*@}*/ /** \name Flags for DMA buffer request */ /*@{*/ DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ /*@}*/ } drmDMAFlags; typedef enum { DRM_PAGE_ALIGN = 0x01, DRM_AGP_BUFFER = 0x02, DRM_SG_BUFFER = 0x04, DRM_FB_BUFFER = 0x08, DRM_PCI_BUFFER_RO = 0x10 } drmBufDescFlags; typedef enum { DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ /* These *HALT* flags aren't supported yet -- they will be used to support the full-screen DGA-like mode. */ DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ } drmLockFlags; typedef enum { DRM_CONTEXT_PRESERVED = 0x01, /**< This context is preserved and never swapped. */ DRM_CONTEXT_2DONLY = 0x02 /**< This context is for 2D rendering only. */ } drm_context_tFlags, *drm_context_tFlagsPtr; typedef struct _drmBufDesc { int count; /**< Number of buffers of this size */ int size; /**< Size in bytes */ int low_mark; /**< Low water mark */ int high_mark; /**< High water mark */ } drmBufDesc, *drmBufDescPtr; typedef struct _drmBufInfo { int count; /**< Number of buffers described in list */ drmBufDescPtr list; /**< List of buffer descriptions */ } drmBufInfo, *drmBufInfoPtr; typedef struct _drmBuf { int idx; /**< Index into the master buffer list */ int total; /**< Buffer size */ int used; /**< Amount of buffer in use (for DMA) */ drmAddress address; /**< Address */ } drmBuf, *drmBufPtr; /** * Buffer mapping information. * * Used by drmMapBufs() and drmUnmapBufs() to store information about the * mapped buffers. */ typedef struct _drmBufMap { int count; /**< Number of buffers mapped */ drmBufPtr list; /**< Buffers */ } drmBufMap, *drmBufMapPtr; typedef struct _drmLock { volatile unsigned int lock; char padding[60]; /* This is big enough for most current (and future?) architectures: DEC Alpha: 32 bytes Intel Merced: ? Intel P5/PPro/PII/PIII: 32 bytes Intel StrongARM: 32 bytes Intel i386/i486: 16 bytes MIPS: 32 bytes (?) Motorola 68k: 16 bytes Motorola PowerPC: 32 bytes Sun SPARC: 32 bytes */ } drmLock, *drmLockPtr; /** * Indices here refer to the offset into * list in drmBufInfo */ typedef struct _drmDMAReq { drm_context_t context; /**< Context handle */ int send_count; /**< Number of buffers to send */ int *send_list; /**< List of handles to buffers */ int *send_sizes; /**< Lengths of data to send, in bytes */ drmDMAFlags flags; /**< Flags */ int request_count; /**< Number of buffers requested */ int request_size; /**< Desired size of buffers requested */ int *request_list; /**< Buffer information */ int *request_sizes; /**< Minimum acceptable sizes */ int granted_count; /**< Number of buffers granted at this size */ } drmDMAReq, *drmDMAReqPtr; typedef struct _drmRegion { drm_handle_t handle; unsigned int offset; drmSize size; drmAddress map; } drmRegion, *drmRegionPtr; typedef struct _drmTextureRegion { unsigned char next; unsigned char prev; unsigned char in_use; unsigned char padding; /**< Explicitly pad this out */ unsigned int age; } drmTextureRegion, *drmTextureRegionPtr; typedef enum { DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ DRM_VBLANK_SIGNAL = 0x40000000 /* Send signal instead of blocking */ } drmVBlankSeqType; typedef struct _drmVBlankReq { drmVBlankSeqType type; unsigned int sequence; unsigned long signal; } drmVBlankReq, *drmVBlankReqPtr; typedef struct _drmVBlankReply { drmVBlankSeqType type; unsigned int sequence; long tval_sec; long tval_usec; } drmVBlankReply, *drmVBlankReplyPtr; typedef union _drmVBlank { drmVBlankReq request; drmVBlankReply reply; } drmVBlank, *drmVBlankPtr; typedef struct _drmSetVersion { int drm_di_major; int drm_di_minor; int drm_dd_major; int drm_dd_minor; } drmSetVersion, *drmSetVersionPtr; #define __drm_dummy_lock(lock) (*(__volatile__ unsigned int *)lock) #define DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ #define DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ #if defined(__GNUC__) && (__GNUC__ >= 2) # if defined(__i386) || defined(__AMD64__) || defined(__x86_64__) || defined(__amd64__) /* Reflect changes here to drmP.h */ #define DRM_CAS(lock,old,new,__ret) \ do { \ int __dummy; /* Can't mark eax as clobbered */ \ __asm__ __volatile__( \ "lock ; cmpxchg %4,%1\n\t" \ "setnz %0" \ : "=d" (__ret), \ "=m" (__drm_dummy_lock(lock)), \ "=a" (__dummy) \ : "2" (old), \ "r" (new)); \ } while (0) #elif defined(__alpha__) #define DRM_CAS(lock, old, new, ret) \ do { \ int old32; \ int cur32; \ __asm__ __volatile__( \ " mb\n" \ " zap %4, 0xF0, %0\n" \ " ldl_l %1, %2\n" \ " zap %1, 0xF0, %1\n" \ " cmpeq %0, %1, %1\n" \ " beq %1, 1f\n" \ " bis %5, %5, %1\n" \ " stl_c %1, %2\n" \ "1: xor %1, 1, %1\n" \ " stl %1, %3" \ : "=r" (old32), \ "=&r" (cur32), \ "=m" (__drm_dummy_lock(lock)),\ "=m" (ret) \ : "r" (old), \ "r" (new)); \ } while(0) #elif defined(__sparc__) #define DRM_CAS(lock,old,new,__ret) \ do { register unsigned int __old __asm("o0"); \ register unsigned int __new __asm("o1"); \ register volatile unsigned int *__lock __asm("o2"); \ __old = old; \ __new = new; \ __lock = (volatile unsigned int *)lock; \ __asm__ __volatile__( \ /*"cas [%2], %3, %0"*/ \ ".word 0xd3e29008\n\t" \ /*"membar #StoreStore | #StoreLoad"*/ \ ".word 0x8143e00a" \ : "=&r" (__new) \ : "0" (__new), \ "r" (__lock), \ "r" (__old) \ : "memory"); \ __ret = (__new != __old); \ } while(0) #elif defined(__ia64__) #ifdef __INTEL_COMPILER /* this currently generates bad code (missing stop bits)... */ #include <ia64intrin.h> #define DRM_CAS(lock,old,new,__ret) \ do { \ unsigned long __result, __old = (old) & 0xffffffff; \ __mf(); \ __result = _InterlockedCompareExchange_acq(&__drm_dummy_lock(lock), (new), __old);\ __ret = (__result) != (__old); \ /* __ret = (__sync_val_compare_and_swap(&__drm_dummy_lock(lock), \ (old), (new)) \ != (old)); */\ } while (0) #else #define DRM_CAS(lock,old,new,__ret) \ do { \ unsigned int __result, __old = (old); \ __asm__ __volatile__( \ "mf\n" \ "mov ar.ccv=%2\n" \ ";;\n" \ "cmpxchg4.acq %0=%1,%3,ar.ccv" \ : "=r" (__result), "=m" (__drm_dummy_lock(lock)) \ : "r" ((unsigned long)__old), "r" (new) \ : "memory"); \ __ret = (__result) != (__old); \ } while (0) #endif #elif defined(__powerpc__) #define DRM_CAS(lock,old,new,__ret) \ do { \ __asm__ __volatile__( \ "sync;" \ "0: lwarx %0,0,%1;" \ " xor. %0,%3,%0;" \ " bne 1f;" \ " stwcx. %2,0,%1;" \ " bne- 0b;" \ "1: " \ "sync;" \ : "=&r"(__ret) \ : "r"(lock), "r"(new), "r"(old) \ : "cr0", "memory"); \ } while (0) #endif /* architecture */ #endif /* __GNUC__ >= 2 */ #ifndef DRM_CAS #define DRM_CAS(lock,old,new,ret) do { ret=1; } while (0) /* FAST LOCK FAILS */ #endif #if defined(__alpha__) || defined(__powerpc__) #define DRM_CAS_RESULT(_result) int _result #else #define DRM_CAS_RESULT(_result) char _result #endif #define DRM_LIGHT_LOCK(fd,lock,context) \ do { \ DRM_CAS_RESULT(__ret); \ DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); \ if (__ret) drmGetLock(fd,context,0); \ } while(0) /* This one counts fast locks -- for benchmarking only. */ #define DRM_LIGHT_LOCK_COUNT(fd,lock,context,count) \ do { \ DRM_CAS_RESULT(__ret); \ DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); \ if (__ret) drmGetLock(fd,context,0); \ else ++count; \ } while(0) #define DRM_LOCK(fd,lock,context,flags) \ do { \ if (flags) drmGetLock(fd,context,flags); \ else DRM_LIGHT_LOCK(fd,lock,context); \ } while(0) #define DRM_UNLOCK(fd,lock,context) \ do { \ DRM_CAS_RESULT(__ret); \ DRM_CAS(lock,DRM_LOCK_HELD|context,context,__ret); \ if (__ret) drmUnlock(fd,context); \ } while(0) /* Simple spin locks */ #define DRM_SPINLOCK(spin,val) \ do { \ DRM_CAS_RESULT(__ret); \ do { \ DRM_CAS(spin,0,val,__ret); \ if (__ret) while ((spin)->lock); \ } while (__ret); \ } while(0) #define DRM_SPINLOCK_TAKE(spin,val) \ do { \ DRM_CAS_RESULT(__ret); \ int cur; \ do { \ cur = (*spin).lock; \ DRM_CAS(spin,cur,val,__ret); \ } while (__ret); \ } while(0) #define DRM_SPINLOCK_COUNT(spin,val,count,__ret) \ do { \ int __i; \ __ret = 1; \ for (__i = 0; __ret && __i < count; __i++) { \ DRM_CAS(spin,0,val,__ret); \ if (__ret) for (;__i < count && (spin)->lock; __i++); \ } \ } while(0) #define DRM_SPINUNLOCK(spin,val) \ do { \ DRM_CAS_RESULT(__ret); \ if ((*spin).lock == val) { /* else server stole lock */ \ do { \ DRM_CAS(spin,val,0,__ret); \ } while (__ret); \ } \ } while(0) /* General user-level programmer's API: unprivileged */ extern int drmAvailable(void); extern int drmOpen(const char *name, const char *busid); extern int drmOpenControl(int minor); extern int drmClose(int fd); extern drmVersionPtr drmGetVersion(int fd); extern drmVersionPtr drmGetLibVersion(int fd); extern void drmFreeVersion(drmVersionPtr); extern int drmGetMagic(int fd, drm_magic_t * magic); extern char *drmGetBusid(int fd); extern int drmGetInterruptFromBusID(int fd, int busnum, int devnum, int funcnum); extern int drmGetMap(int fd, int idx, drm_handle_t *offset, drmSize *size, drmMapType *type, drmMapFlags *flags, drm_handle_t *handle, int *mtrr); extern int drmGetClient(int fd, int idx, int *auth, int *pid, int *uid, unsigned long *magic, unsigned long *iocs); extern int drmGetStats(int fd, drmStatsT *stats); extern int drmSetInterfaceVersion(int fd, drmSetVersion *version); extern int drmCommandNone(int fd, unsigned long drmCommandIndex); extern int drmCommandRead(int fd, unsigned long drmCommandIndex, void *data, unsigned long size); extern int drmCommandWrite(int fd, unsigned long drmCommandIndex, void *data, unsigned long size); extern int drmCommandWriteRead(int fd, unsigned long drmCommandIndex, void *data, unsigned long size); /* General user-level programmer's API: X server (root) only */ extern void drmFreeBusid(const char *busid); extern int drmSetBusid(int fd, const char *busid); extern int drmAuthMagic(int fd, drm_magic_t magic); extern int drmAddMap(int fd, drm_handle_t offset, drmSize size, drmMapType type, drmMapFlags flags, drm_handle_t * handle); extern int drmRmMap(int fd, drm_handle_t handle); extern int drmAddContextPrivateMapping(int fd, drm_context_t ctx_id, drm_handle_t handle); extern int drmAddBufs(int fd, int count, int size, drmBufDescFlags flags, int agp_offset); extern int drmMarkBufs(int fd, double low, double high); extern int drmCreateContext(int fd, drm_context_t * handle); extern int drmSetContextFlags(int fd, drm_context_t context, drm_context_tFlags flags); extern int drmGetContextFlags(int fd, drm_context_t context, drm_context_tFlagsPtr flags); extern int drmAddContextTag(int fd, drm_context_t context, void *tag); extern int drmDelContextTag(int fd, drm_context_t context); extern void *drmGetContextTag(int fd, drm_context_t context); extern drm_context_t * drmGetReservedContextList(int fd, int *count); extern void drmFreeReservedContextList(drm_context_t *); extern int drmSwitchToContext(int fd, drm_context_t context); extern int drmDestroyContext(int fd, drm_context_t handle); extern int drmCreateDrawable(int fd, drm_drawable_t * handle); extern int drmDestroyDrawable(int fd, drm_drawable_t handle); extern int drmUpdateDrawableInfo(int fd, drm_drawable_t handle, drm_drawable_info_type_t type, unsigned int num, void *data); extern int drmCtlInstHandler(int fd, int irq); extern int drmCtlUninstHandler(int fd); /* General user-level programmer's API: authenticated client and/or X */ extern int drmMap(int fd, drm_handle_t handle, drmSize size, drmAddressPtr address); extern int drmUnmap(drmAddress address, drmSize size); extern drmBufInfoPtr drmGetBufInfo(int fd); extern drmBufMapPtr drmMapBufs(int fd); extern int drmUnmapBufs(drmBufMapPtr bufs); extern int drmDMA(int fd, drmDMAReqPtr request); extern int drmFreeBufs(int fd, int count, int *list); extern int drmGetLock(int fd, drm_context_t context, drmLockFlags flags); extern int drmUnlock(int fd, drm_context_t context); extern int drmFinish(int fd, int context, drmLockFlags flags); extern int drmGetContextPrivateMapping(int fd, drm_context_t ctx_id, drm_handle_t * handle); /* AGP/GART support: X server (root) only */ extern int drmAgpAcquire(int fd); extern int drmAgpRelease(int fd); extern int drmAgpEnable(int fd, unsigned long mode);