/* radeon_state.c -- State support for Radeon -*- linux-c -*- */
/*
 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Gareth Hughes <gareth@valinux.com>
 *    Kevin E. Martin <martin@valinux.com>
 */

#include "drmP.h"
#include "drm.h"
#include "drm_sarea.h"
#include "radeon_drm.h"
#include "radeon_drv.h"

/* ================================================================
 * Helper functions for client state checking and fixup
 */

static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
						    dev_priv,
						    struct drm_file *file_priv,
						    u32 * offset)
{
	u64 off = *offset;
	u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1;
	struct drm_radeon_driver_file_fields *radeon_priv;

	/* Hrm ... the story of the offset ... So this function converts
	 * the various ideas of what userland clients might have for an
	 * offset in the card address space into an offset into the card
	 * address space :) So with a sane client, it should just keep
	 * the value intact and just do some boundary checking. However,
	 * not all clients are sane. Some older clients pass us 0 based
	 * offsets relative to the start of the framebuffer and some may
	 * assume the AGP aperture it appended to the framebuffer, so we
	 * try to detect those cases and fix them up.
	 *
	 * Note: It might be a good idea here to make sure the offset lands
	 * in some "allowed" area to protect things like the PCIE GART...
	 */

	/* First, the best case, the offset already lands in either the
	 * framebuffer or the GART mapped space
	 */
	if (radeon_check_offset(dev_priv, off))
		return 0;

	/* Ok, that didn't happen... now check if we have a zero based
	 * offset that fits in the framebuffer + gart space, apply the
	 * magic offset we get from SETPARAM or calculated from fb_location
	 */
	if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
		radeon_priv = file_priv->driver_priv;
		off += radeon_priv->radeon_fb_delta;
	}

	/* Finally, assume we aimed at a GART offset if beyond the fb */
	if (off > fb_end)
		off = off - fb_end - 1 + dev_priv->gart_vm_start;

	/* Now recheck and fail if out of bounds */
	if (radeon_check_offset(dev_priv, off)) {
		DRM_DEBUG("offset fixed up to 0x%x\n", (unsigned int)off);
		*offset = off;
		return 0;
	}
	return -EINVAL;
}

static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
						     dev_priv,
						     struct drm_file *file_priv,
						     int id, u32 *data)
{
	switch (id) {

	case RADEON_EMIT_PP_MISC:
		if (radeon_check_and_fixup_offset(dev_priv, file_priv,
		    &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) {
			DRM_ERROR("Invalid depth buffer offset\n");
			return -EINVAL;
		}
		break;

	case RADEON_EMIT_PP_CNTL:
		if (radeon_check_and_fixup_offset(dev_priv, file_priv,
		    &data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) {
			DRM_ERROR("Invalid colour buffer offset\n");
			return -EINVAL;
		}
		break;

	case R200_EMIT_PP_TXOFFSET_0:
	case R200_EMIT_PP_TXOFFSET_1:
	case R200_EMIT_PP_TXOFFSET_2:
	case R200_EMIT_PP_TXOFFSET_3:
	case R200_EMIT_PP_TXOFFSET_4:
	case R200_EMIT_PP_TXOFFSET_5:
		if (radeon_check_and_fixup_offset(dev_priv, file_priv,
						  &data[0])) {
			DRM_ERROR("Invalid R200 texture offset\n");
			return -EINVAL;
		}
		break;

	case RADEON_EMIT_PP_TXFILTER_0:
	case RADEON_EMIT_PP_TXFILTER_1:
	case RADEON_EMIT_PP_TXFILTER_2:
		if (radeon_check_and_fixup_offset(dev_priv, file_priv,
		    &data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) {
			DRM_ERROR("Invalid R100 texture offset\n");
			return -EINVAL;
		}
		break;

	case R200_EMIT_PP_CUBIC_OFFSETS_0:
	case R200_EMIT_PP_CUBIC_OFFSETS_1:
	case R200_EMIT_PP_CUBIC_OFFSETS_2:
	case R200_EMIT_PP_CUBIC_OFFSETS_3:
	case R200_EMIT_PP_CUBIC_OFFSETS_4:
	case R200_EMIT_PP_CUBIC_OFFSETS_5:{
			int i;
			for (i = 0; i < 5; i++) {
				if (radeon_check_and_fixup_offset(dev_priv,
								  file_priv,
								  &data[i])) {
					DRM_ERROR
					    ("Invalid R200 cubic texture offset\n");
					return -EINVAL;
				}
			}
			break;
		}

	case RADEON_EMIT_PP_CUBIC_OFFSETS_T0:
	case RADEON_EMIT_PP_CUBIC_OFFSETS_T1:
	case RADEON_EMIT_PP_CUBIC_OFFSETS_T2:{
			int i;
			for (i = 0; i < 5; i++) {
				if (radeon_check_and_fixup_offset(dev_priv,
								  file_priv,
								  &data[i])) {
					DRM_ERROR
					    ("Invalid R100 cubic texture offset\n");
					return -EINVAL;
				}
			}
		}
		break;

	case R200_EMIT_VAP_CTL: {
			RING_LOCALS;
			BEGIN_RING(2);
			OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
			ADVANCE_RING();
		}
		break;

	case RADEON_EMIT_RB3D_COLORPITCH:
	case RADEON_EMIT_RE_LINE_PATTERN:
	case RADEON_EMIT_SE_LINE_WIDTH:
	case RADEON_EMIT_PP_LUM_MATRIX:
	case RADEON_EMIT_PP_ROT_MATRIX_0:
	case RADEON_EMIT_RB3D_STENCILREFMASK:
	case RADEON_EMIT_SE_VPORT_XSCALE:
	case RADEON_EMIT_SE_CNTL:
	case RADEON_EMIT_SE_CNTL_STATUS:
	case RADEON_EMIT_RE_MISC:
	case RADEON_EMIT_PP_BORDER_COLOR_0:
	case RADEON_EMIT_PP_BORDER_COLOR_1:
	case RADEON_EMIT_PP_BORDER_COLOR_2:
	case RADEON_EMIT_SE_ZBIAS_FACTOR:
	case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
	case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
	case R200_EMIT_PP_TXCBLEND_0:
	case R200_EMIT_PP_TXCBLEND_1:
	case R200_EMIT_PP_TXCBLEND_2:
	case R200_EMIT_PP_TXCBLEND_3:
	case R200_EMIT_PP_TXCBLEND_4:
	case R200_EMIT_PP_TXCBLEND_5:
	case R200_EMIT_PP_TXCBLEND_6:
	case R200_EMIT_PP_TXCBLEND_7:
	case R200_EMIT_TCL_LIGHT_MODEL_CTL_0:
	case R200_EMIT_TFACTOR_0:
	case R200_EMIT_VTX_FMT_0:
	case R200_EMIT_MATRIX_SELECT_0:
	case R200_EMIT_TEX_PROC_CTL_2:
	case R200_EMIT_TCL_UCP_VERT_BLEND_CTL:
	case R200_EMIT_PP_TXFILTER_0:
	case R200_EMIT_PP_TXFILTER_1:
	case R200_EMIT_PP_TXFILTER_2:
	case R200_EMIT_PP_TXFILTER_3:
	case R200_EMIT_PP_TXFILTER_4:
	case R200_EMIT_PP_TXFILTER_5:
	case R200_EMIT_VTE_CNTL:
	case R200_EMIT_OUTPUT_VTX_COMP_SEL:
	case R200_EMIT_PP_TAM_DEBUG3:
	case R200_EMIT_PP_CNTL_X:
	case R200_EMIT_RB3D_DEPTHXY_OFFSET:
	case R200_EMIT_RE_AUX_SCISSOR_CNTL:
	case R200_EMIT_RE_SCISSOR_TL_0:
	case R200_EMIT_RE_SCISSOR_TL_1:
	case R200_EMIT_RE_SCISSOR_TL_2:
	case R200_EMIT_SE_VAP_CNTL_STATUS:
	case R200_EMIT_SE_VTX_STATE_CNTL:
	case R200_EMIT_RE_POINTSIZE:
	case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0:
	case R200_EMIT_PP_CUBIC_FACES_0:
	case R200_EMIT_PP_CUBIC_FACES_1:
	case R200_EMIT_PP_CUBIC_FACES_2:
	case R200_EMIT_PP_CUBIC_FACES_3:
	case R200_EMIT_PP_CUBIC_FACES_4:
	case R200_EMIT_PP_CUBIC_FACES_5:
	case RADEON_EMIT_PP_TEX_SIZE_0:
	case RADEON_EMIT_PP_TEX_SIZE_1:
	case RADEON_EMIT_PP_TEX_SIZE_2:
	case R200_EMIT_RB3D_BLENDCOLOR:
	case R200_EMIT_TCL_POINT_SPRITE_CNTL:
	case RADEON_EMIT_PP_CUBIC_FACES_0:
	case RADEON_EMIT_PP_CUBIC_FACES_1:
	case RADEON_EMIT_PP_CUBIC_FACES_2:
	case R200_EMIT_PP_TRI_PERF_CNTL:
	case R200_EMIT_PP_AFS_0:
	case R200_EMIT_PP_AFS_1:
	case R200_EMIT_ATF_TFACTOR:
	case R200_EMIT_PP_TXCTLALL_0:
	case R200_EMIT_PP_TXCTLALL_1:
	case R200_EMIT_PP_TXCTLALL_2:
	case R200_EMIT_PP_TXCTLALL_3:
	case R200_EMIT_PP_TXCTLALL_4:
	case R200_EMIT_PP_TXCTLALL_5:
	case R200_EMIT_VAP_PVS_CNTL:
		/* These packets don't contain memory offsets */
		break;

	default:
		DRM_ERROR("Unknown state packet ID %d\n", id);
		return -EINVAL;
	}

	return 0;
}

static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
						     dev_priv,
						     struct drm_file *file_priv,
						     drm_radeon_kcmd_buffer_t *
						     cmdbuf,
						     unsigned int *cmdsz)
{
	u32 *cmd = (u32 *) cmdbuf->buf;
	u32 offset, narrays;
	int count, i, k;

	*cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16);

	if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) {
		DRM_ERROR("Not a type 3 packet\n");
		return -EINVAL;
	}

	if (4 * *cmdsz > cmdbuf->bufsz) {
		DRM_ERROR("Packet size larger than size of data provided\n");
		return -EINVAL;
	}

	switch(cmd[0] & 0xff00) {
	/* XXX Are there old drivers needing other packets? */

	case RADEON_3D_DRAW_IMMD:
	case RADEON_3D_DRAW_VBUF:
	case RADEON_3D_DRAW_INDX:
	case RADEON_WAIT_FOR_IDLE:
	case RADEON_CP_NOP:
	case RADEON_3D_CLEAR_ZMASK:
/*	case RADEON_CP_NEXT_CHAR:
	case RADEON_CP_PLY_NEXTSCAN:
	case RADEON_CP_SET_SCISSORS: */ /* probably safe but will never need them? */
		/* these packets are safe */
		break;

	case RADEON_CP_3D_DRAW_IMMD_2:
	case RADEON_CP_3D_DRAW_VBUF_2:
	case RADEON_CP_3D_DRAW_INDX_2:
	case RADEON_3D_CLEAR_HIZ:
		/* safe but r200 only */
		if ((dev_priv->chip_family < CHIP_R200) ||
		    (dev_priv->chip_family > CHIP_RV280)) {
			DRM_ERROR("Invalid 3d packet for non r200-class chip\n");
			return -EINVAL;
		}
		break;

	case RADEON_3D_LOAD_VBPNTR:
		count = (cmd[0] >> 16) & 0x3fff;

		if (count > 18) { /* 12 arrays max */
			DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
				  count);
			return -EINVAL;
		}

		/* carefully check packet contents */
		narrays = cmd[1] & ~0xc000;
		k = 0;
		i = 2;
		while ((k < narrays) && (i < (count + 2))) {
			i++;		/* skip attribute field */
			if (radeon_check_and_fixup_offset(dev_priv, file_priv,
							  &cmd[i])) {
				DRM_ERROR
				    ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
				     k, i);
				return -EINVAL;
			}
			k++;
			i++;
			if (k == narrays)
				break;
			/* have one more to process, they come in pairs */
			if (radeon_check_and_fixup_offset(dev_priv,
							  file_priv, &cmd[i]))
			{
				DRM_ERROR
				    ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
				     k, i);
				return -EINVAL;
			}
			k++;
			i++;
		}
		/* do the counts match what we expect ? */
		if ((k != narrays) || (i != (count + 2))) {
			DRM_ERROR
			    ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
			      k, i, narrays, count + 1);
			return -EINVAL;
		}
		break;

	case RADEON_3D_RNDR_GEN_INDX_PRIM:
		if (dev_priv->chip_family > CHIP_RS200) {
			DRM_ERROR("Invalid 3d packet for non-r100-class chip\n");
			return -EINVAL;
		}
		if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[1])) {
				DRM_ERROR("Invalid rndr_gen_indx offset\n");
				return -EINVAL;
		}
		break;

	case RADEON_CP_INDX_BUFFER:
		/* safe but r200 only */
		if ((dev_priv->chip_family < CHIP_R200) ||
		    (dev_priv->chip_family > CHIP_RV280)) {
			DRM_ERROR("Invalid 3d packet for non-r200-class chip\n");
			return -EINVAL;
		}
		if ((cmd[1] & 0x8000ffff) != 0x80000810) {
			DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]);
			return -EINVAL;
		}
		if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[2])) {
			DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]);
			return -EINVAL;
		}
		break;

	case RADEON_CNTL_HOSTDATA_BLT:
	case RADEON_CNTL_PAINT_MULTI:
	case RADEON_CNTL_BITBLT_MULTI:
		/* MSB of opcode: next DWORD GUI_CNTL */
		if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
			      | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
			offset = cmd[2] << 10;
			if (radeon_check_and_fixup_offset
			    (dev_priv, file_priv, &offset)) {
				DRM_ERROR("Invalid first packet offset\n");
				return -EINVAL;
			}
			cmd[2] = (cmd[2] & 0xffc00000) | offset >> 10;
		}

		if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
		    (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
			offset = cmd[3] << 10;
			if (radeon_check_and_fixup_offset
			    (dev_priv, file_priv, &offset)) {
				DRM_ERROR("Invalid second packet offset\n");
				return -EINVAL;
			}
			cmd[3] = (cmd[3] & 0xffc00000) | offset >> 10;
		}
		break;

	default:
		DRM_ERROR("Invalid packet type %x\n", cmd[0] & 0xff00);
		return -EINVAL;
	}

	return 0;
}

/* ================================================================
 * CP hardware state programming functions
 */

static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
					     struct drm_clip_rect * box)
{
	RING_LOCALS;

	DRM_DEBUG("   box:  x1=%d y1=%d  x2=%d y2=%d\n",
		  box->x1, box->y1, box->x2, box->y2);

	BEGIN_RING(4);
	OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
	OUT_RING((box->y1 << 16) | box->x1);
	OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
	OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1));
	ADVANCE_RING();
}

/* Emit 1.1 state
 */
static int radeon_emit_state(drm_radeon_private_t * dev_priv,
			     struct drm_file *file_priv,
			     drm_radeon_context_regs_t * ctx,
			     drm_radeon_texture_regs_t * tex,
			     unsigned int dirty)
{
	RING_LOCALS;
	DRM_DEBUG("dirty=0x%08x\n", dirty);

	if (dirty & RADEON_UPLOAD_CONTEXT) {
		if (radeon_check_and_fixup_offset(dev_priv, file_priv,
						  &ctx->rb3d_depthoffset)) {
			DRM_ERROR("Invalid depth buffer offset\n");
			return -EINVAL;
		}

		if (radeon_check_and_fixup_offset(dev_priv, file_priv,
						  &ctx->rb3d_coloroffset)) {
			DRM_ERROR("Invalid depth buffer offset\n");
			return -EINVAL;
		}

		BEGIN_RING(14);
		OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
		OUT_RING(ctx->pp_misc);
		OUT_RING(ctx->pp_fog_color);
		OUT_RING(ctx->re_solid_color);
		OUT_RING(ctx->rb3d_blendcntl);
		OUT_RING(ctx->rb3d_depthoffset);
		OUT_RING(ctx->rb3d_depthpitch);
		OUT_RING(ctx->rb3d_zstencilcntl);
		OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2));
		OUT_RING(ctx->pp_cntl);
		OUT_RING(ctx->rb3d_cntl);
		OUT_RING(ctx->rb3d_coloroffset);
		OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
		OUT_RING(ctx->rb3d_colorpitch);
		ADVANCE_RING();
	}

	if (dirty & RADEON_UPLOAD_VERTFMT) {
		BEGIN_RING(2);
		OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0));
		OUT_RING(ctx->se_coord_fmt);
		ADVANCE_RING();
	}

	if (dirty & RADEON_UPLOAD_LINE) {
		BEGIN_RING(5);
		OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1));
		OUT_RING(ctx->re_line_pattern);
		OUT_RING(ctx->re_line_state);
		OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0));
		OUT_RING(ctx->se_line_width);
		ADVANCE_RING();
	}

	if (dirty & RADEON_UPLOAD_BUMPMAP) {
		BEGIN_RING(5);
		OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0));
		OUT_RING(ctx->pp_lum_matrix);
		OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1));
		OUT_RING(ctx->pp_rot_matrix_0);
		OUT_RING(ctx->pp_rot_matrix_1);
		ADVANCE_RING();
	}

	if (dirty & RADEON_UPLOAD_MASKS) {
		BEGIN_RING(4);
		OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2));
		OUT_RING(ctx->rb3d_stencilrefmask);
		OUT_RING(ctx->rb3d_ropcntl);
		OUT_RING(ctx->rb3d_planemask);
		ADVANCE_RING();
	}

	if (dirty & RADEON_UPLOAD_VIEWPORT) {
		BEGIN_RING(7);
		OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5));
		OUT_RING(ctx->se_vport_xscale);
		OUT_RING(ctx->se_vport_xoffset);
		OUT_RING(ctx->se_vport_yscale);
		OUT_RING(ctx->se_vport_yoffset);
		OUT_RING(ctx->se_vport_zscale);
		OUT_RING(ctx->se_vport_zoffset);
		ADVANCE_RING();
	}

	if (dirty & RADEON_UPLOAD_SETUP) {
		BEGIN_RING(4);
		OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0));
		OUT_RING(ctx->se_cntl);
		OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0));
		OUT_RING(ctx->se_cntl_status);
		ADVANCE_RING();
	}

	if (dirty & RADEON_UPLOAD_MISC) {
		BEGIN_RING(2);
		OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0));
		OUT_RING(ctx->re_misc);
		ADVANCE_RING();
	}

	if (dirty & RADEON_UPLOAD_TEX0) {
		if (radeon_check_and_fixup_offset(dev_priv, file_priv,
						  &tex[0].pp_txoffset)) {
			DRM_ERROR("Invalid texture offset for unit 0\n");
			return -EINVAL;
		}

		BEGIN_RING(9);
		OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5));
		OUT_RING(tex[0].pp_txfilter);
		OUT_RING(tex[0].pp_txformat);
		OUT_RING(tex[0].pp_txoffset);
		OUT_RING(tex[0].pp_txcblend);
		OUT_RING(tex[0].pp_txablend);
		OUT_RING(tex[0].pp_tfactor);
		OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0));
		OUT_RING(tex[0].pp_border_color);
		ADVANCE_RING();
	}

	if (dirty & RADEON_UPLOAD_TEX1) {
		if (radeon_check_and_fixup_offset(dev_priv, file_priv,
						  &tex[1].pp_txoffset)) {
			DRM_ERROR("Invalid texture offset for unit 1\n");
			return -EINVAL;
		}

		BEGIN_RING(9);
		OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5));
		OUT_RING(tex[1].pp_txfilter);
		OUT_RING(tex[1].pp_txformat);
		OUT_RING(tex[1].pp_txoffset);
		OUT_RING(tex[1].pp_txcblend);
		OUT_RING(tex[1].pp_txablend);
		OUT_RING(tex[1].pp_tfactor);
		OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0));
		OUT_RING(tex[1].pp_border_color);
		ADVANCE_RING();
	}

	if (dirty & RADEON_UPLOAD_TEX2) {
		if (radeon_check_and_fixup_offset(dev_priv, file_priv,
						  &tex[2].pp_txoffset)) {
			DRM_ERROR("Invalid texture offset for unit 2\n");
			return -EINVAL;
		}

		BEGIN_RING(9);
		OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5));
		OUT_RING(tex[2].pp_txfilter);
		OUT_RING(tex[2].pp_txformat);
		OUT_RING(tex[2].pp_txoffset);
		OUT_RING(tex[2].pp_txcblend);
		OUT_RING(tex[2].pp_txablend);
		OUT_RING(tex[2].pp_tfactor);
		OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0));
		OUT_RING(tex[2].pp_border_color);
		ADVANCE_RING();
	}

	return 0;
}

/* Emit 1.2 state
 */
static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
			      struct drm_file *file_priv,
			      drm_radeon_state_t * state)
{
	RING_LOCALS;

	if (state->dirty & RADEON_UPLOAD_ZBIAS) {
		BEGIN_RING(3);
		OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1));
		OUT_RING(state->context2.se_zbias_factor);
		OUT_RING(state->context2.se_zbias_constant);
		ADVANCE_RING();
	}

	return radeon_emit_state(dev_priv, file_priv, &state->context,
				 state->tex, state->dirty);
}

/* New (1.3) state mechanism.  3 commands (packet, scalar, vector) in
 * 1.3 cmdbuffers allow all previous state to be updated as well as
 * the tcl scalar and vector areas.
 */
static struct {
	int start;
	int len;
	const char *name;
} packet[RADEON_MAX_STATE_PACKETS] = {
	{RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
	{RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
	{RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
	{RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
	{RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
	{RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
	{RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
	{RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
	{RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
	{RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
	{RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
	{RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
	{RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
	{RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
	{RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
	{RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
	{RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
	{RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
	{RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
	{RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
	{RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
		    "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
	{R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
	{R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
	{R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
	{R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
	{R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
	{R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
	{R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
	{R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
	{R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
	{R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
	{R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
	{R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
	{R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
	{R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
	{R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
	{R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
	{R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
	{R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
	{R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
	{R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
	{R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
	{R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
	{R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
	{R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
	{R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
	{R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
	{R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
	{R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
	{R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
	 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
	{R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
	{R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
	{R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
	{R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
	{R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
	{R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
	{R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
	{R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
	{R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
	{R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
	{R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
		    "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
	{R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"},	/* 61 */
	{R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
	{R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
	{R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
	{R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
	{R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
	{R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
	{R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
	{R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
	{R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
	{R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
	{R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
	{RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
	{RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
	{RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
	{R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
	{R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
	{RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
	{RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
	{RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
	{RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
	{RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
	{RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
	{R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
	{R200_PP_AFS_0, 32, "R200_PP_AFS_0"},     /* 85 */
	{R200_PP_AFS_1, 32, "R200_PP_AFS_1"},
	{R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
	{R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
	{R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
	{R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
	{R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
	{R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
	{R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
	{R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
};

/* ================================================================
 * Performance monitoring functions
 */

static void radeon_clear_box(drm_radeon_private_t * dev_priv,
			     int x, int y, int w, int h, int r, int g, int b)
{
	u32 color;
	RING_LOCALS;

	x += dev_priv->sarea_priv->boxes[0].x1;
	y += dev_priv->sarea_priv->boxes[0].y1;

	switch (dev_priv->color_fmt) {
	case RADEON_COLOR_FORMAT_RGB565:
		color = (((r & 0xf8) << 8) |
			 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
		break;
	case RADEON_COLOR_FORMAT_ARGB8888:
	default:
		color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
		break;
	}

	BEGIN_RING(4);
	RADEON_WAIT_UNTIL_3D_IDLE();
	OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
	OUT_RING(0xffffffff);
	ADVANCE_RING();

	BEGIN_RING(6);

	OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4));
	OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
		 RADEON_GMC_BRUSH_SOLID_COLOR |
		 (dev_priv->color_fmt << 8) |
		 RADEON_GMC_SRC_DATATYPE_COLOR |
		 RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);

	if (dev_priv->sarea_priv->pfCurrentPage == 1) {
		OUT_RING(dev_priv->front_pitch_offset);
	} else {
		OUT_RING(dev_priv->back_pitch_offset);
	}

	OUT_RING(color);

	OUT_RING((x << 16) | y);
	OUT_RING((w << 16) | h);

	ADVANCE_RING();
}

static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
{
	/* Collapse various things into a wait flag -- trying to
	 * guess if userspase slept -- better just to have them tell us.
	 */
	if (dev_priv->stats.last_frame_reads > 1 ||
	    dev_priv->stats.last_clear_reads > dev_priv->stats.clears) {
		dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
	}

	if (dev_priv->stats.freelist_loops) {
		dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
	}

	/* Purple box for page flipping
	 */
	if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
		radeon_clear_box(dev_priv, 4, 4, 8, 8, 255, 0, 255);

	/* Red box if we have to wait for idle at any point
	 */
	if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
		radeon_clear_box(dev_priv, 16, 4, 8, 8, 255, 0, 0);

	/* Blue box: lost context?
	 */

	/* Yellow box for texture swaps
	 */
	if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
		radeon_clear_box(dev_priv, 40, 4, 8, 8, 255, 255, 0);

	/* Green box if hardware never idles (as far as we can tell)
	 */
	if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
		radeon_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);

	/* Draw bars indicating number of buffers allocated
	 * (not a great measure, easily confused)
	 */
	if (dev_priv->stats.requested_bufs) {
		if (dev_priv->stats.requested_bufs > 100)
			dev_priv->stats.requested_bufs = 100;

		radeon_clear_box(dev_priv, 4, 16,
				 dev_priv->stats.requested_bufs, 4,
				 196, 128, 128);
	}

	memset(&dev_priv->stats, 0, sizeof(dev_priv->stats));

}

/* ================================================================
 * CP command dispatch functions
 */

static void radeon_cp_dispatch_clear(struct drm_device * dev,
				     drm_radeon_clear_t * clear,
				     drm_radeon_clear_rect_t * depth_boxes)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
	drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
	int nbox = sarea_priv->nbox;
	struct drm_clip_rect *pbox = sarea_priv->boxes;
	unsigned int flags = clear->flags;
	u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0;
	int i;
	RING_LOCALS;
	DRM_DEBUG("flags = 0x%x\n", flags);

	dev_priv->stats.clears++;

	if (dev_priv->sarea_priv->pfCurrentPage == 1) {
		unsigned int tmp = flags;

		flags &= ~(RADEON_FRONT | RADEON_BACK);
		if (tmp & RADEON_FRONT)
			flags |= RADEON_BACK;
		if (tmp & RADEON_BACK)
			flags |= RADEON_FRONT;
	}

	if (flags & (RADEON_FRONT | RADEON_BACK)) {

		BEGIN_RING(4);

		/* Ensure the 3D stream is idle before doing a
		 * 2D fill to clear the front or back buffer.
		 */
		RADEON_WAIT_UNTIL_3D_IDLE();

		OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
		OUT_RING(clear->color_mask);

		ADVANCE_RING();

		/* Make sure we restore the 3D state next time.
		 */
		dev_priv->sarea_priv->ctx_owner = 0;

		for (i = 0; i < nbox; i++) {
			int x = pbox[i].x1;
			int y = pbox[i].y1;
			int w = pbox[i].x2 - x;
			int h = pbox[i].y2 - y;

			DRM_DEBUG("%d,%d-%d,%d flags 0x%x\n",
				  x, y, w, h, flags);

			if (flags & RADEON_FRONT) {
				BEGIN_RING(6);

				OUT_RING(CP_PACKET3
					 (RADEON_CNTL_PAINT_MULTI, 4));
				OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
					 RADEON_GMC_BRUSH_SOLID_COLOR |
					 (dev_priv->
					  color_fmt << 8) |
					 RADEON_GMC_SRC_DATATYPE_COLOR |
					 RADEON_ROP3_P |
					 RADEON_GMC_CLR_CMP_CNTL_DIS);

				OUT_RING(dev_priv->front_pitch_offset);
				OUT_RING(clear->clear_color);

				OUT_RING((x << 16) | y);
				OUT_RING((w << 16) | h);

				ADVANCE_RING();
			}

			if (flags & RADEON_BACK) {
				BEGIN_RING(6);

				OUT_RING(CP_PACKET3
					 (RADEON_CNTL_PAINT_MULTI, 4));
				OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
					 RADEON_GMC_BRUSH_SOLID_COLOR |
					 (dev_priv->
					  color_fmt << 8) |
					 RADEON_GMC_SRC_DATATYPE_COLOR |
					 RADEON_ROP3_P |
					 RADEON_GMC_CLR_CMP_CNTL_DIS);

				OUT_RING(dev_priv->back_pitch_offset);
				OUT_RING(clear->clear_color);

				OUT_RING((x << 16) | y);
				OUT_RING((w << 16) | h);

				ADVANCE_RING();
			}
		}
	}

	/* hyper z clear */
	/* no docs available, based on reverse engeneering by Stephane Marchesin */
	if ((flags & (RADEON_DEPTH | RADEON_STENCIL))
	    && (flags & RADEON_CLEAR_FASTZ)) {

		int i;
		int depthpixperline =
		    dev_priv->depth_fmt ==
		    RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch /
						       2) : (dev_priv->
							     depth_pitch / 4);

		u32 clearmask;

		u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
		    ((clear->depth_mask & 0xff) << 24);

		/* Make sure we restore the 3D state next time.
		 * we haven't touched any "normal" state - still need this?
		 */
		dev_priv->sarea_priv->ctx_owner = 0;

		if ((dev_priv->flags & RADEON_HAS_HIERZ)
		    && (flags & RADEON_USE_HIERZ)) {
			/* FIXME : reverse engineer that for Rx00 cards */
			/* FIXME : the mask supposedly contains low-res z values. So can't set
			   just to the max (0xff? or actually 0x3fff?), need to take z clear
			   value into account? */
			/* pattern seems to work for r100, though get slight
			   rendering errors with glxgears. If hierz is not enabled for r100,
			   only 4 bits which indicate clear (15,16,31,32, all zero) matter, the
			   other ones are ignored, and the same clear mask can be used. That's
			   very different behaviour than R200 which needs different clear mask
			   and different number of tiles to clear if hierz is enabled or not !?!
			 */
			clearmask = (0xff << 22) | (0xff << 6) | 0x003f003f;
		} else {
			/* clear mask : chooses the clearing pattern.
			   rv250: could be used to clear only parts of macrotiles
			   (but that would get really complicated...)?
			   bit 0 and 1 (either or both of them ?!?!) are used to
			   not clear tile (or maybe one of the bits indicates if the tile is
			   compressed or not), bit 2 and 3 to not clear tile 1,...,.
			   Pattern is as follows:
			   | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29|
			   bits -------------------------------------------------
			   | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31|
			   rv100: clearmask covers 2x8 4x1 tiles, but one clear still
			   covers 256 pixels ?!?
			 */
			clearmask = 0x0;
		}

		BEGIN_RING(8);
		RADEON_WAIT_UNTIL_2D_IDLE();
		OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE,
			     tempRB3D_DEPTHCLEARVALUE);
		/* what offset is this exactly ? */
		OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0);
		/* need ctlstat, otherwise get some strange black flickering */
		OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT,
			     RADEON_RB3D_ZC_FLUSH_ALL);
		ADVANCE_RING();

		for (i = 0; i < nbox; i++) {
			int tileoffset, nrtilesx, nrtilesy, j;
			/* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */
			if ((dev_priv->flags & RADEON_HAS_HIERZ)
			    && (dev_priv->chip_family < CHIP_R200)) {
				/* FIXME : figure this out for r200 (when hierz is enabled). Or
				   maybe r200 actually doesn't need to put the low-res z value into
				   the tile cache like r100, but just needs to clear the hi-level z-buffer?
				   Works for R100, both with hierz and without.
				   R100 seems to operate on 2x1 8x8 tiles, but...
				   odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially
				   problematic with resolutions which are not 64 pix aligned? */
				tileoffset =
				    ((pbox[i].y1 >> 3) * depthpixperline +
				     pbox[i].x1) >> 6;
				nrtilesx =
				    ((pbox[i].x2 & ~63) -
				     (pbox[i].x1 & ~63)) >> 4;
				nrtilesy =
				    (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
				for (j = 0; j <= nrtilesy; j++) {
					BEGIN_RING(4);
					OUT_RING(CP_PACKET3
						 (RADEON_3D_CLEAR_ZMASK, 2));
					/* first tile */
					OUT_RING(tileoffset * 8);
					/* the number of tiles to clear */
					OUT_RING(nrtilesx + 4);
					/* clear mask : chooses the clearing pattern. */
					OUT_RING(clearmask);
					ADVANCE_RING();
					tileoffset += depthpixperline >> 6;
				}
			} else if ((dev_priv->chip_family >= CHIP_R200) &&
				   (dev_priv->chip_family <= CHIP_RV280)) {
				/* works for rv250. */
				/* find first macro tile (8x2 4x4 z-pixels on rv250) */
				tileoffset =
				    ((pbox[i].y1 >> 3) * depthpixperline +
				     pbox[i].x1) >> 5;
				nrtilesx =
				    (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5);
				nrtilesy =
				    (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
				for (j = 0; j <= nrtilesy; j++) {
					BEGIN_RING(4);
					OUT_RING(CP_PACKET3
						 (RADEON_3D_CLEAR_ZMASK, 2));
					/* first tile */
					/* judging by the first tile offset needed, could possibly
					   directly address/clear 4x4 tiles instead of 8x2 * 4x4
					   macro tiles, though would still need clear mask for
					   right/bottom if truely 4x4 granularity is desired ? */
					OUT_RING(tileoffset * 16);
					/* the number of tiles to clear */
					OUT_RING(nrtilesx + 1);
					/* clear mask : chooses the clearing pattern. */
					OUT_RING(clearmask);
					ADVANCE_RING();
					tileoffset += depthpixperline >> 5;
				}
			} else {	/* rv 100 */
				/* rv100 might not need 64 pix alignment, who knows */
				/* offsets are, hmm, weird */
				tileoffset =
				    ((pbox[i].y1 >> 4) * depthpixperline +
				     pbox[i].x1) >> 6;
				nrtilesx =
				    ((pbox[i].x2 & ~63) -
				     (pbox[i].x1 & ~63)) >> 4;
				nrtilesy =
				    (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4);
				for (j = 0; j <= nrtilesy; j++) {
					BEGIN_RING(4);
					OUT_RING(CP_PACKET3
						 (RADEON_3D_CLEAR_ZMASK, 2));
					OUT_RING(tileoffset * 128);
					/* the number of tiles to clear */
					OUT_RING(nrtilesx + 4);
					/* clear mask : chooses the clearing pattern. */
					OUT_RING(clearmask);
					ADVANCE_RING();
					tileoffset += depthpixperline >> 6;
				}
			}
		}

		/* TODO don't always clear all hi-level z tiles */
		if ((dev_priv->flags & RADEON_HAS_HIERZ)
		    && ((dev_priv->chip_family >= CHIP_R200) &&
			(dev_priv->chip_family <= CHIP_RV280))
		    && (flags & RADEON_USE_HIERZ))
			/* r100 and cards without hierarchical z-buffer have no high-level z-buffer */
			/* FIXME : the mask supposedly contains low-res z values. So can't set
			   just to the max (0xff? or actually 0x3fff?), need to take z clear
			   value into account? */
		{
			BEGIN_RING(4);
			OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2));
			OUT_RING(0x0);	/* First tile */
			OUT_RING(0x3cc0);
			OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f);
			ADVANCE_RING();
		}
	}

	/* We have to clear the depth and/or stencil buffers by
	 * rendering a quad into just those buffers.  Thus, we have to
	 * make sure the 3D engine is configured correctly.
	 */
	else if ((dev_priv->chip_family >= CHIP_R200) &&
		 (dev_priv->chip_family <= CHIP_RV280) &&
		 (flags & (RADEON_DEPTH | RADEON_STENCIL))) {

		int tempPP_CNTL;
		int tempRE_CNTL;
		int tempRB3D_CNTL;
		int tempRB3D_ZSTENCILCNTL;
		int tempRB3D_STENCILREFMASK;
		int tempRB3D_PLANEMASK;
		int tempSE_CNTL;
		int tempSE_VTE_CNTL;
		int tempSE_VTX_FMT_0;
		int tempSE_VTX_FMT_1;
		int tempSE_VAP_CNTL;
		int tempRE_AUX_SCISSOR_CNTL;

		tempPP_CNTL = 0;
		tempRE_CNTL = 0;

		tempRB3D_CNTL = depth_clear->rb3d_cntl;

		tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
		tempRB3D_STENCILREFMASK = 0x0;

		tempSE_CNTL = depth_clear->se_cntl;

		/* Disable TCL */

		tempSE_VAP_CNTL = (	/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK |  */
					  (0x9 <<
					   SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));

		tempRB3D_PLANEMASK = 0x0;

		tempRE_AUX_SCISSOR_CNTL = 0x0;

		tempSE_VTE_CNTL =
		    SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK;

		/* Vertex format (X, Y, Z, W) */
		tempSE_VTX_FMT_0 =
		    SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
		    SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
		tempSE_VTX_FMT_1 = 0x0;

		/*
		 * Depth buffer specific enables
		 */
		if (flags & RADEON_DEPTH) {
			/* Enable depth buffer */
			tempRB3D_CNTL |= RADEON_Z_ENABLE;
		} else {
			/* Disable depth buffer */
			tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
		}

		/*
		 * Stencil buffer specific enables
		 */
		if (flags & RADEON_STENCIL) {
			tempRB3D_CNTL |= RADEON_STENCIL_ENABLE;
			tempRB3D_STENCILREFMASK = clear->depth_mask;
		} else {
			tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
			tempRB3D_STENCILREFMASK = 0x00000000;
		}

		if (flags & RADEON_USE_COMP_ZBUF) {
			tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
			    RADEON_Z_DECOMPRESSION_ENABLE;
		}
		if (flags & RADEON_USE_HIERZ) {
			tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
		}

		BEGIN_RING(26);
		RADEON_WAIT_UNTIL_2D_IDLE();

		OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL);
		OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL);
		OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL);
		OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
		OUT_RING_REG(RADEON_RB3D_STENCILREFMASK,
			     tempRB3D_STENCILREFMASK);
		OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK);
		OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL);
		OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL);
		OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0);
		OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1);
		OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL);
		OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL);
		ADVANCE_RING();

		/* Make sure we restore the 3D state next time.
		 */
		dev_priv->sarea_priv->ctx_owner = 0;

		for (i = 0; i < nbox; i++) {

			/* Funny that this should be required --
			 *  sets top-left?
			 */
			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);

			BEGIN_RING(14);
			OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12));
			OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
				  RADEON_PRIM_WALK_RING |
				  (3 << RADEON_NUM_VERTICES_SHIFT)));
			OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
			OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
			OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
			OUT_RING(0x3f800000);
			OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
			OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
			OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
			OUT_RING(0x3f800000);
			OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
			OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
			OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
			OUT_RING(0x3f800000);
			ADVANCE_RING();
		}
	} else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) {

		int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;

		rb3d_cntl = depth_clear->rb3d_cntl;

		if (flags & RADEON_DEPTH) {
			rb3d_cntl |= RADEON_Z_ENABLE;
		} else {
			rb3d_cntl &= ~RADEON_Z_ENABLE;
		}

		if (flags & RADEON_STENCIL) {
			rb3d_cntl |= RADEON_STENCIL_ENABLE;
			rb3d_stencilrefmask = clear->depth_mask;	/* misnamed field */
		} else {
			rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
			rb3d_stencilrefmask = 0x00000000;
		}

		if (flags & RADEON_USE_COMP_ZBUF) {
			tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
			    RADEON_Z_DECOMPRESSION_ENABLE;
		}
		if (flags & RADEON_USE_HIERZ) {
			tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
		}

		BEGIN_RING(13);
		RADEON_WAIT_UNTIL_2D_IDLE();

		OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1));
		OUT_RING(0x00000000);
		OUT_RING(rb3d_cntl);

		OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
		OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask);
		OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000);
		OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl);
		ADVANCE_RING();

		/* Make sure we restore the 3D state next time.
		 */
		dev_priv->sarea_priv->ctx_owner = 0;

		for (i = 0; i < nbox; i++) {

			/* Funny that this should be required --
			 *  sets top-left?
			 */
			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);

			BEGIN_RING(15);

			OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13));
			OUT_RING(RADEON_VTX_Z_PRESENT |
				 RADEON_VTX_PKCOLOR_PRESENT);
			OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
				  RADEON_PRIM_WALK_RING |
				  RADEON_MAOS_ENABLE |
				  RADEON_VTX_FMT_RADEON_MODE |
				  (3 << RADEON_NUM_VERTICES_SHIFT)));

			OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
			OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
			OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
			OUT_RING(0x0);

			OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
			OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
			OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
			OUT_RING(0x0);

			OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
			OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
			OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
			OUT_RING(0x0);

			ADVANCE_RING();
		}
	}

	/* Increment the clear counter.  The client-side 3D driver must
	 * wait on this value before performing the clear ioctl.  We
	 * need this because the card's so damned fast...
	 */
	dev_priv->sarea_priv->last_clear++;

	BEGIN_RING(4);

	RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear);
	RADEON_WAIT_UNTIL_IDLE();

	ADVANCE_RING();
}

static void radeon_cp_dispatch_swap(struct drm_device * dev)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
	int nbox = sarea_priv->nbox;
	struct drm_clip_rect *pbox = sarea_priv->boxes;
	int i;
	RING_LOCALS;
	DRM_DEBUG("\n");

	/* Do some trivial performance monitoring...
	 */
	if (dev_priv->do_boxes)
		radeon_cp_performance_boxes(dev_priv);

	/* Wait for the 3D stream to idle before dispatching the bitblt.
	 * This will prevent data corruption between the two streams.
	 */
	BEGIN_RING(2);

	RADEON_WAIT_UNTIL_3D_IDLE();

	ADVANCE_RING();

	for (i = 0; i < nbox; i++) {
		int x = pbox[i].x1;
		int y = pbox[i].y1;
		int w = pbox[i].x2 - x;
		int h = pbox[i].y2 - y;

		DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);

		BEGIN_RING(9);

		OUT_RING(CP_PACKET0(RADEON_DP_GUI_MASTER_CNTL, 0));
		OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
			 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
			 RADEON_GMC_BRUSH_NONE |
			 (dev_priv->color_fmt << 8) |
			 RADEON_GMC_SRC_DATATYPE_COLOR |
			 RADEON_ROP3_S |
			 RADEON_DP_SRC_SOURCE_MEMORY |
			 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);

		/* Make this work even if front & back are flipped:
		 */
		OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1));
		if (dev_priv->sarea_priv->pfCurrentPage == 0) {
			OUT_RING(dev_priv->back_pitch_offset);
			OUT_RING(dev_priv->front_pitch_offset);
		} else {
			OUT_RING(dev_priv->front_pitch_offset);
			OUT_RING(dev_priv->back_pitch_offset);
		}

		OUT_RING(CP_PACKET0(RADEON_SRC_X_Y, 2));
		OUT_RING((x << 16) | y);
		OUT_RING((x << 16) | y);
		OUT_RING((w << 16) | h);

		ADVANCE_RING();
	}

	/* Increment the frame counter.  The client-side 3D driver must
	 * throttle the framerate by waiting for this value before
	 * performing the swapbuffer ioctl.
	 */
	dev_priv->sarea_priv->last_frame++;

	BEGIN_RING(4);

	RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
	RADEON_WAIT_UNTIL_2D_IDLE();

	ADVANCE_RING();
}

static void radeon_cp_dispatch_flip(struct drm_device * dev)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	struct drm_sarea *sarea = (struct drm_sarea *) dev_priv->sarea->handle;
	int offset = (dev_priv->sarea_priv->pfCurrentPage == 1)
	    ? dev_priv->front_offset : dev_priv->back_offset;
	RING_LOCALS;
	DRM_DEBUG("pfCurrentPage=%d\n",
		  dev_priv->sarea_priv->pfCurrentPage);

	/* Do some trivial performance monitoring...
	 */
	if (dev_priv->do_boxes) {
		dev_priv->stats.boxes |= RADEON_BOX_FLIP;
		radeon_cp_performance_boxes(dev_priv);
	}

	/* Update the frame offsets for both CRTCs
	 */
	BEGIN_RING(6);

	RADEON_WAIT_UNTIL_3D_IDLE();
	OUT_RING_REG(RADEON_CRTC_OFFSET,
		     ((sarea->frame.y * dev_priv->front_pitch +
		       sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
		     + offset);
	OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
		     + offset);

	ADVANCE_RING();

	/* Increment the frame counter.  The client-side 3D driver must
	 * throttle the framerate by waiting for this value before
	 * performing the swapbuffer ioctl.
	 */
	dev_priv->sarea_priv->last_frame++;
	dev_priv->sarea_priv->pfCurrentPage =
		1 - dev_priv->sarea_priv->pfCurrentPage;

	BEGIN_RING(2);

	RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);

	ADVANCE_RING();
}

static int bad_prim_vertex_nr(int primitive, int nr)
{
	switch (primitive & RADEON_PRIM_TYPE_MASK) {
	case RADEON_PRIM_TYPE_NONE:
	case RADEON_PRIM_TYPE_POINT:
		return nr < 1;
	case RADEON_PRIM_TYPE_LINE:
		return (nr & 1) || nr == 0;
	case RADEON_PRIM_TYPE_LINE_STRIP:
		return nr < 2;
	case RADEON_PRIM_TYPE_TRI_LIST:
	case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
	case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
	case RADEON_PRIM_TYPE_RECT_LIST:
		return nr % 3 || nr == 0;
	case RADEON_PRIM_TYPE_TRI_FAN:
	case RADEON_PRIM_TYPE_TRI_STRIP:
		return nr < 3;
	default:
		return 1;
	}
}

typedef struct {
	unsigned int start;
	unsigned int finish;
	unsigned int prim;
	unsigned int numverts;
	unsigned int offset;
	unsigned int vc_format;
} drm_radeon_tcl_prim_t;

static void radeon_cp_dispatch_vertex(struct drm_device * dev,
				      struct drm_buf * buf,
				      drm_radeon_tcl_prim_t * prim)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
	int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
	int numverts = (int)prim->numverts;
	int nbox = sarea_priv->nbox;
	int i = 0;
	RING_LOCALS;

	DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
		  prim->prim,
		  prim->vc_format, prim->start, prim->finish, prim->numverts);

	if (bad_prim_vertex_nr(prim->prim, prim->numverts)) {
		DRM_ERROR("bad prim %x numverts %d\n",
			  prim->prim, prim->numverts);
		return;
	}

	do {
		/* Emit the next cliprect */
		if (i < nbox) {
			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
		}

		/* Emit the vertex buffer rendering commands */
		BEGIN_RING(5);

		OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3));
		OUT_RING(offset);
		OUT_RING(numverts);
		OUT_RING(prim->vc_format);
		OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST |
			 RADEON_COLOR_ORDER_RGBA |
			 RADEON_VTX_FMT_RADEON_MODE |
			 (numverts << RADEON_NUM_VERTICES_SHIFT));

		ADVANCE_RING();

		i++;
	} while (i < nbox);
}

static void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
	RING_LOCALS;

	buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;

	/* Emit the vertex buffer age */
	BEGIN_RING(2);
	RADEON_DISPATCH_AGE(buf_priv->age);
	ADVANCE_RING();

	buf->pending = 1;
	buf->used = 0;
}

static void radeon_cp_dispatch_indirect(struct drm_device * dev,
					struct drm_buf * buf, int start, int end)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	RING_LOCALS;
	DRM_DEBUG("buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);

	if (start != end) {
		int offset = (dev_priv->gart_buffers_offset
			      + buf->offset + start);
		int dwords = (end - start + 3) / sizeof(u32);

		/* Indirect buffer data must be an even number of
		 * dwords, so if we've been given an odd number we must
		 * pad the data with a Type-2 CP packet.
		 */
		if (dwords & 1) {
			u32 *data = (u32 *)
			    ((char *)dev->agp_buffer_map->handle
			     + buf->offset + start);
			data[dwords++] = RADEON_CP_PACKET2;
		}

		/* Fire off the indirect buffer */
		BEGIN_RING(3);

		OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
		OUT_RING(offset);
		OUT_RING(dwords);

		ADVANCE_RING();
	}
}

static void radeon_cp_dispatch_indices(struct drm_device * dev,
				       struct drm_buf * elt_buf,
				       drm_radeon_tcl_prim_t * prim)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
	int offset = dev_priv->gart_buffers_offset + prim->offset;
	u32 *data;
	int dwords;
	int i = 0;
	int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
	int count = (prim->finish - start) / sizeof(u16);
	int nbox = sarea_priv->nbox;

	DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
		  prim->prim,
		  prim->vc_format,
		  prim->start, prim->finish, prim->offset, prim->numverts);

	if (bad_prim_vertex_nr(prim->prim, count)) {
		DRM_ERROR("bad prim %x count %d\n", prim->prim, count);
		return;
	}

	if (start >= prim->finish || (prim->start & 0x7)) {
		DRM_ERROR("buffer prim %d\n", prim->prim);
		return;
	}

	dwords = (prim->finish - prim->start + 3) / sizeof(u32);

	data = (u32 *) ((char *)dev->agp_buffer_map->handle +
			elt_buf->offset + prim->start);

	data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2);
	data[1] = offset;
	data[2] = prim->numverts;
	data[3] = prim->vc_format;
	data[4] = (prim->prim |
		   RADEON_PRIM_WALK_IND |
		   RADEON_COLOR_ORDER_RGBA |
		   RADEON_VTX_FMT_RADEON_MODE |
		   (count << RADEON_NUM_VERTICES_SHIFT));

	do {
		if (i < nbox)
			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);

		radeon_cp_dispatch_indirect(dev, elt_buf,
					    prim->start, prim->finish);

		i++;
	} while (i < nbox);

}

#define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE

static int radeon_cp_dispatch_texture(struct drm_device * dev,
				      struct drm_file *file_priv,
				      drm_radeon_texture_t * tex,
				      drm_radeon_tex_image_t * image)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	struct drm_buf *buf;
	u32 format;
	u32 *buffer;
	const u8 __user *data;
	int size, dwords, tex_width, blit_width, spitch;
	u32 height;
	int i;
	u32 texpitch, microtile;
	u32 offset, byte_offset;
	RING_LOCALS;

	if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
		DRM_ERROR("Invalid destination offset\n");
		return -EINVAL;
	}

	dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;

	/* Flush the pixel cache.  This ensures no pixel data gets mixed
	 * up with the texture data from the host data blit, otherwise
	 * part of the texture image may be corrupted.
	 */
	BEGIN_RING(4);
	RADEON_FLUSH_CACHE();
	RADEON_WAIT_UNTIL_IDLE();
	ADVANCE_RING();

	/* The compiler won't optimize away a division by a variable,
	 * even if the only legal values are powers of two.  Thus, we'll
	 * use a shift instead.
	 */
	switch (tex->format) {
	case RADEON_TXFORMAT_ARGB8888:
	case RADEON_TXFORMAT_RGBA8888:
		format = RADEON_COLOR_FORMAT_ARGB8888;
		tex_width = tex->width * 4;
		blit_width = image->width * 4;
		break;
	case RADEON_TXFORMAT_AI88:
	case RADEON_TXFORMAT_ARGB1555:
	case RADEON_TXFORMAT_RGB565:
	case RADEON_TXFORMAT_ARGB4444:
	case RADEON_TXFORMAT_VYUY422:
	case RADEON_TXFORMAT_YVYU422:
		format = RADEON_COLOR_FORMAT_RGB565;
		tex_width = tex->width * 2;
		blit_width = image->width * 2;
		break;
	case RADEON_TXFORMAT_I8:
	case RADEON_TXFORMAT_RGB332:
		format = RADEON_COLOR_FORMAT_CI8;
		tex_width = tex->width * 1;
		blit_width = image->width * 1;
		break;
	default:
		DRM_ERROR("invalid texture format %d\n", tex->format);
		return -EINVAL;
	}
	spitch = blit_width >> 6;
	if (spitch == 0 && image->height > 1)
		return -EINVAL;

	texpitch = tex->pitch;
	if ((texpitch << 22) & RADEON_DST_TILE_MICRO) {
		microtile = 1;
		if (tex_width < 64) {
			texpitch &= ~(RADEON_DST_TILE_MICRO >> 22);
			/* we got tiled coordinates, untile them */
			image->x *= 2;
		}
	} else
		microtile = 0;

	/* this might fail for zero-sized uploads - are those illegal? */
	if (!radeon_check_offset(dev_priv, tex->offset + image->height *
				blit_width - 1)) {
		DRM_ERROR("Invalid final destination offset\n");
		return -EINVAL;
	}

	DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);

	do {
		DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
			  tex->offset >> 10, tex->pitch, tex->format,
			  image->x, image->y, image->width, image->height);

		/* Make a copy of some parameters in case we have to
		 * update them for a multi-pass texture blit.
		 */
		height = image->height;
		data = (const u8 __user *)image->data;

		size = height * blit_width;

		if (size > RADEON_MAX_TEXTURE_SIZE) {
			height = RADEON_MAX_TEXTURE_SIZE / blit_width;
			size = height * blit_width;
		} else if (size < 4 && size > 0) {
			size = 4;
		} else if (size == 0) {
			return 0;
		}

		buf = radeon_freelist_get(dev);
		if (0 && !buf) {
			radeon_do_cp_idle(dev_priv);
			buf = radeon_freelist_get(dev);
		}
		if (!buf) {
			DRM_DEBUG("EAGAIN\n");
			if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
				return -EFAULT;
			return -EAGAIN;
		}

		/* Dispatch the indirect buffer.
		 */
		buffer =
		    (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
		dwords = size / 4;

#define RADEON_COPY_MT(_buf, _data, _width) \
	do { \
		if (DRM_COPY_FROM_USER(_buf, _data, (_width))) {\
			DRM_ERROR("EFAULT on pad, %d bytes\n", (_width)); \
			return -EFAULT; \
		} \
	} while(0)

		if (microtile) {
			/* texture micro tiling in use, minimum texture width is thus 16 bytes.
			   however, we cannot use blitter directly for texture width < 64 bytes,
			   since minimum tex pitch is 64 bytes and we need this to match
			   the texture width, otherwise the blitter will tile it wrong.
			   Thus, tiling manually in this case. Additionally, need to special
			   case tex height = 1, since our actual image will have height 2
			   and we need to ensure we don't read beyond the texture size
			   from user space. */
			if (tex->height == 1) {
				if (tex_width >= 64 || tex_width <= 16) {
					RADEON_COPY_MT(buffer, data,
						(int)(tex_width * sizeof(u32)));
				} else if (tex_width == 32) {
					RADEON_COPY_MT(buffer, data, 16);
					RADEON_COPY_MT(buffer + 8,
						       data + 16, 16);
				}
			} else if (tex_width >= 64 || tex_width == 16) {
				RADEON_COPY_MT(buffer, data,
					       (int)(dwords * sizeof(u32)));
			} else if (tex_width < 16) {
				for (i = 0; i < tex->height; i++) {
					RADEON_COPY_MT(buffer, data, tex_width);
					buffer += 4;
					data += tex_width;
				}
			} else if (tex_width == 32) {
				/* TODO: make sure this works when not fitting in one buffer
				   (i.e. 32bytes x 2048...) */
				for (i = 0; i < tex->height; i += 2) {
					RADEON_COPY_MT(buffer, data, 16);
					data += 16;
					RADEON_COPY_MT(buffer + 8, data, 16);
					data += 16;
					RADEON_COPY_MT(buffer + 4, data, 16);
					data += 16;
					RADEON_COPY_MT(buffer + 12, data, 16);
					data += 16;
					buffer += 16;
				}
			}
		} else {
			if (tex_width >= 32) {
				/* Texture image width is larger than the minimum, so we
				 * can upload it directly.
				 */
				RADEON_COPY_MT(buffer, data,
					       (int)(dwords * sizeof(u32)));
			} else {
				/* Texture image width is less than the minimum, so we
				 * need to pad out each image scanline to the minimum
				 * width.
				 */
				for (i = 0; i < tex->height; i++) {
					RADEON_COPY_MT(buffer, data, tex_width);
					buffer += 8;
					data += tex_width;
				}
			}
		}

#undef RADEON_COPY_MT
		byte_offset = (image->y & ~2047) * blit_width;
		buf->file_priv = file_priv;
		buf->used = size;
		offset = dev_priv->gart_buffers_offset + buf->offset;
		BEGIN_RING(9);
		OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
		OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
			 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
			 RADEON_GMC_BRUSH_NONE |
			 (format << 8) |
			 RADEON_GMC_SRC_DATATYPE_COLOR |
			 RADEON_ROP3_S |
			 RADEON_DP_SRC_SOURCE_MEMORY |
			 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
		OUT_RING((spitch << 22) | (offset >> 10));
		OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));
		OUT_RING(0);
		OUT_RING((image->x << 16) | (image->y % 2048));
		OUT_RING((image->width << 16) | height);
		RADEON_WAIT_UNTIL_2D_IDLE();
		ADVANCE_RING();
		COMMIT_RING();

		radeon_cp_discard_buffer(dev, buf);

		/* Update the input parameters for next time */
		image->y += height;
		image->height -= height;
		image->data = (const u8 __user *)image->data + size;
	} while (image->height > 0);

	/* Flush the pixel cache after the blit completes.  This ensures
	 * the texture data is written out to memory before rendering
	 * continues.
	 */
	BEGIN_RING(4);
	RADEON_FLUSH_CACHE();
	RADEON_WAIT_UNTIL_2D_IDLE();
	ADVANCE_RING();
	COMMIT_RING();

	return 0;
}

static void radeon_cp_dispatch_stipple(struct drm_device * dev, u32 * stipple)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	int i;
	RING_LOCALS;
	DRM_DEBUG("\n");

	BEGIN_RING(35);

	OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0));
	OUT_RING(0x00000000);

	OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31));
	for (i = 0; i < 32; i++) {
		OUT_RING(stipple[i]);
	}

	ADVANCE_RING();
}

static void radeon_apply_surface_regs(int surf_index,
				      drm_radeon_private_t *dev_priv)
{
	if (!dev_priv->mmio)
		return;

	radeon_do_cp_idle(dev_priv);

	RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index,
		     dev_priv->surfaces[surf_index].flags);
	RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index,
		     dev_priv->surfaces[surf_index].lower);
	RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index,
		     dev_priv->surfaces[surf_index].upper);
}

/* Allocates a virtual surface
 * doesn't always allocate a real surface, will stretch an existing
 * surface when possible.
 *
 * Note that refcount can be at most 2, since during a free refcount=3
 * might mean we have to allocate a new surface which might not always
 * be available.
 * For example : we allocate three contigous surfaces ABC. If B is
 * freed, we suddenly need two surfaces to store A and C, which might
 * not always be available.
 */
static int alloc_surface(drm_radeon_surface_alloc_t *new,
			 drm_radeon_private_t *dev_priv,
			 struct drm_file *file_priv)
{
	struct radeon_virt_surface *s;
	int i;
	int virt_surface_index;
	uint32_t new_upper, new_lower;

	new_lower = new->address;
	new_upper = new_lower + new->size - 1;

	/* sanity check */
	if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) ||
	    ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) !=
	     RADEON_SURF_ADDRESS_FIXED_MASK)
	    || ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0))
		return -1;

	/* make sure there is no overlap with existing surfaces */
	for (i = 0; i < RADEON_MAX_SURFACES; i++) {
		if ((dev_priv->surfaces[i].refcount != 0) &&
		    (((new_lower >= dev_priv->surfaces[i].lower) &&
		      (new_lower < dev_priv->surfaces[i].upper)) ||
		     ((new_lower < dev_priv->surfaces[i].lower) &&
		      (new_upper > dev_priv->surfaces[i].lower)))) {
			return -1;
		}
	}

	/* find a virtual surface */
	for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++)
		if (dev_priv->virt_surfaces[i].file_priv == 0)
			break;
	if (i == 2 * RADEON_MAX_SURFACES) {
		return -1;
	}
	virt_surface_index = i;

	/* try to reuse an existing surface */
	for (i = 0; i < RADEON_MAX_SURFACES; i++) {
		/* extend before */
		if ((dev_priv->surfaces[i].refcount == 1) &&
		    (new->flags == dev_priv->surfaces[i].flags) &&
		    (new_upper + 1 == dev_priv->surfaces[i].lower)) {
			s = &(dev_priv->virt_surfaces[virt_surface_index]);
			s->surface_index = i;
			s->lower = new_lower;
			s->upper = new_upper;
			s->flags = new->flags;
			s->file_priv = file_priv;
			dev_priv->surfaces[i].refcount++;
			dev_priv->surfaces[i].lower = s->lower;
			radeon_apply_surface_regs(s->surface_index, dev_priv);
			return virt_surface_index;
		}

		/* extend after */
		if ((dev_priv->surfaces[i].refcount == 1) &&
		    (new->flags == dev_priv->surfaces[i].flags) &&
		    (new_lower == dev_priv->surfaces[i].upper + 1)) {
			s = &(dev_priv->virt_surfaces[virt_surface_index]);
			s->surface_index = i;
			s->lower = new_lower;
			s->upper = new_upper;
			s->flags = new->flags;
			s->file_priv = file_priv;
			dev_priv->surfaces[i].refcount++;
			dev_priv->surfaces[i].upper = s->upper;
			radeon_apply_surface_regs(s->surface_index, dev_priv);
			return virt_surface_index;
		}
	}

	/* okay, we need a new one */
	for (i = 0; i < RADEON_MAX_SURFACES; i++) {
		if (dev_priv->surfaces[i].refcount == 0) {
			s = &(dev_priv->virt_surfaces[virt_surface_index]);
			s->surface_index = i;
			s->lower = new_lower;
			s->upper = new_upper;
			s->flags = new->flags;
			s->file_priv = file_priv;
			dev_priv->surfaces[i].refcount = 1;
			dev_priv->surfaces[i].lower = s->lower;
			dev_priv->surfaces[i].upper = s->upper;
			dev_priv->surfaces[i].flags = s->flags;
			radeon_apply_surface_regs(s->surface_index, dev_priv);
			return virt_surface_index;
		}
	}

	/* we didn't find anything */
	return -1;
}

static int free_surface(struct drm_file *file_priv,
			drm_radeon_private_t * dev_priv,
			int lower)
{
	struct radeon_virt_surface *s;
	int i;
	/* find the virtual surface */
	for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
		s = &(dev_priv->virt_surfaces[i]);
		if (s->file_priv) {
			if ((lower == s->lower) && (file_priv == s->file_priv))
			{
				if (dev_priv->surfaces[s->surface_index].
				    lower == s->lower)
					dev_priv->surfaces[s->surface_index].
					    lower = s->upper;

				if (dev_priv->surfaces[s->surface_index].
				    upper == s->upper)
					dev_priv->surfaces[s->surface_index].
					    upper = s->lower;

				dev_priv->surfaces[s->surface_index].refcount--;
				if (dev_priv->surfaces[s->surface_index].
				    refcount == 0)
					dev_priv->surfaces[s->surface_index].
					    flags = 0;
				s->file_priv = NULL;
				radeon_apply_surface_regs(s->surface_index,
							  dev_priv);
				return 0;
			}
		}
	}
	return 1;
}

static void radeon_surfaces_release(struct drm_file *file_priv,
				    drm_radeon_private_t * dev_priv)
{
	int i;
	for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
		if (dev_priv->virt_surfaces[i].file_priv == file_priv)
			free_surface(file_priv, dev_priv,
				     dev_priv->virt_surfaces[i].lower);
	}
}

/* ================================================================
 * IOCTL functions
 */
static int radeon_surface_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_surface_alloc_t *alloc = data;

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}

	if (alloc_surface(alloc, dev_priv, file_priv) == -1)
		return -EINVAL;
	else
		return 0;
}

static int radeon_surface_free(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_surface_free_t *memfree = data;

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}

	if (free_surface(file_priv, dev_priv, memfree->address))
		return -EINVAL;
	else
		return 0;
}

static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
	drm_radeon_clear_t *clear = data;
	drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
	DRM_DEBUG("\n");

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	RING_SPACE_TEST_WITH_RETURN(dev_priv);

	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;

	if (DRM_COPY_FROM_USER(&depth_boxes, clear->depth_boxes,
			       sarea_priv->nbox * sizeof(depth_boxes[0])))
		return -EFAULT;

	radeon_cp_dispatch_clear(dev, clear, depth_boxes);

	COMMIT_RING();
	return 0;
}

/* Not sure why this isn't set all the time:
 */
static int radeon_do_init_pageflip(struct drm_device * dev)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	RING_LOCALS;

	DRM_DEBUG("\n");

	BEGIN_RING(6);
	RADEON_WAIT_UNTIL_3D_IDLE();
	OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0));
	OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) |
		 RADEON_CRTC_OFFSET_FLIP_CNTL);
	OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0));
	OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) |
		 RADEON_CRTC_OFFSET_FLIP_CNTL);
	ADVANCE_RING();

	dev_priv->page_flipping = 1;

	if (dev_priv->sarea_priv->pfCurrentPage != 1)
		dev_priv->sarea_priv->pfCurrentPage = 0;

	return 0;
}

/* Swapping and flipping are different operations, need different ioctls.
 * They can & should be intermixed to support multiple 3d windows.
 */
static int radeon_cp_flip(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	DRM_DEBUG("\n");

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	RING_SPACE_TEST_WITH_RETURN(dev_priv);

	if (!dev_priv->page_flipping)
		radeon_do_init_pageflip(dev);

	radeon_cp_dispatch_flip(dev);

	COMMIT_RING();
	return 0;
}

static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
	DRM_DEBUG("\n");

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	RING_SPACE_TEST_WITH_RETURN(dev_priv);

	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;

	radeon_cp_dispatch_swap(dev);
	dev_priv->sarea_priv->ctx_owner = 0;

	COMMIT_RING();
	return 0;
}

static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_sarea_t *sarea_priv;
	struct drm_device_dma *dma = dev->dma;
	struct drm_buf *buf;
	drm_radeon_vertex_t *vertex = data;
	drm_radeon_tcl_prim_t prim;

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}

	sarea_priv = dev_priv->sarea_priv;

	DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
		  DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard);

	if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
		DRM_ERROR("buffer index %d (of %d max)\n",
			  vertex->idx, dma->buf_count - 1);
		return -EINVAL;
	}
	if (vertex->prim < 0 || vertex->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
		DRM_ERROR("buffer prim %d\n", vertex->prim);
		return -EINVAL;
	}

	RING_SPACE_TEST_WITH_RETURN(dev_priv);
	VB_AGE_TEST_WITH_RETURN(dev_priv);

	buf = dma->buflist[vertex->idx];

	if (buf->file_priv != file_priv) {
		DRM_ERROR("process %d using buffer owned by %p\n",
			  DRM_CURRENTPID, buf->file_priv);
		return -EINVAL;
	}
	if (buf->pending) {
		DRM_ERROR("sending pending buffer %d\n", vertex->idx);
		return -EINVAL;
	}

	/* Build up a prim_t record:
	 */
	if (vertex->count) {
		buf->used = vertex->count;	/* not used? */

		if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
			if (radeon_emit_state(dev_priv, file_priv,
					      &sarea_priv->context_state,
					      sarea_priv->tex_state,
					      sarea_priv->dirty)) {
				DRM_ERROR("radeon_emit_state failed\n");
				return -EINVAL;
			}

			sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
					       RADEON_UPLOAD_TEX1IMAGES |
					       RADEON_UPLOAD_TEX2IMAGES |
					       RADEON_REQUIRE_QUIESCENCE);
		}

		prim.start = 0;
		prim.finish = vertex->count;	/* unused */
		prim.prim = vertex->prim;
		prim.numverts = vertex->count;
		prim.vc_format = dev_priv->sarea_priv->vc_format;

		radeon_cp_dispatch_vertex(dev, buf, &prim);
	}

	if (vertex->discard) {
		radeon_cp_discard_buffer(dev, buf);
	}

	COMMIT_RING();
	return 0;
}

static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_sarea_t *sarea_priv;
	struct drm_device_dma *dma = dev->dma;
	struct drm_buf *buf;
	drm_radeon_indices_t *elts = data;
	drm_radeon_tcl_prim_t prim;
	int count;

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}
	sarea_priv = dev_priv->sarea_priv;

	DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
		  DRM_CURRENTPID, elts->idx, elts->start, elts->end,
		  elts->discard);

	if (elts->idx < 0 || elts->idx >= dma->buf_count) {
		DRM_ERROR("buffer index %d (of %d max)\n",
			  elts->idx, dma->buf_count - 1);
		return -EINVAL;
	}
	if (elts->prim < 0 || elts->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
		DRM_ERROR("buffer prim %d\n", elts->prim);
		return -EINVAL;
	}

	RING_SPACE_TEST_WITH_RETURN(dev_priv);
	VB_AGE_TEST_WITH_RETURN(dev_priv);

	buf = dma->buflist[elts->idx];

	if (buf->file_priv != file_priv) {
		DRM_ERROR("process %d using buffer owned by %p\n",
			  DRM_CURRENTPID, buf->file_priv);
		return -EINVAL;
	}
	if (buf->pending) {
		DRM_ERROR("sending pending buffer %d\n", elts->idx);
		return -EINVAL;
	}

	count = (elts->end - elts->start) / sizeof(u16);
	elts->start -= RADEON_INDEX_PRIM_OFFSET;

	if (elts->start & 0x7) {
		DRM_ERROR("misaligned buffer 0x%x\n", elts->start);
		return -EINVAL;
	}
	if (elts->start < buf->used) {
		DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used);
		return -EINVAL;
	}

	buf->used = elts->end;

	if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
		if (radeon_emit_state(dev_priv, file_priv,
				      &sarea_priv->context_state,
				      sarea_priv->tex_state,
				      sarea_priv->dirty)) {
			DRM_ERROR("radeon_emit_state failed\n");
			return -EINVAL;
		}

		sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
				       RADEON_UPLOAD_TEX1IMAGES |
				       RADEON_UPLOAD_TEX2IMAGES |
				       RADEON_REQUIRE_QUIESCENCE);
	}

	/* Build up a prim_t record:
	 */
	prim.start = elts->start;
	prim.finish = elts->end;
	prim.prim = elts->prim;
	prim.offset = 0;	/* offset from start of dma buffers */
	prim.numverts = RADEON_MAX_VB_VERTS;	/* duh */
	prim.vc_format = dev_priv->sarea_priv->vc_format;

	radeon_cp_dispatch_indices(dev, buf, &prim);
	if (elts->discard) {
		radeon_cp_discard_buffer(dev, buf);
	}

	COMMIT_RING();
	return 0;
}

static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_texture_t *tex = data;
	drm_radeon_tex_image_t image;
	int ret;

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	if (tex->image == NULL) {
		DRM_ERROR("null texture image!\n");
		return -EINVAL;
	}

	if (DRM_COPY_FROM_USER(&image,
			       (drm_radeon_tex_image_t __user *) tex->image,
			       sizeof(image)))
		return -EFAULT;

	RING_SPACE_TEST_WITH_RETURN(dev_priv);
	VB_AGE_TEST_WITH_RETURN(dev_priv);

	ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image);

	return ret;
}

static int radeon_cp_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_stipple_t *stipple = data;
	u32 mask[32];

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32)))
		return -EFAULT;

	RING_SPACE_TEST_WITH_RETURN(dev_priv);

	radeon_cp_dispatch_stipple(dev, mask);

	COMMIT_RING();
	return 0;
}

static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	struct drm_device_dma *dma = dev->dma;
	struct drm_buf *buf;
	drm_radeon_indirect_t *indirect = data;
	RING_LOCALS;

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}

	DRM_DEBUG("idx=%d s=%d e=%d d=%d\n",
		  indirect->idx, indirect->start, indirect->end,
		  indirect->discard);

	if (indirect->idx < 0 || indirect->idx >= dma->buf_count) {
		DRM_ERROR("buffer index %d (of %d max)\n",
			  indirect->idx, dma->buf_count - 1);
		return -EINVAL;
	}

	buf = dma->buflist[indirect->idx];

	if (buf->file_priv != file_priv) {
		DRM_ERROR("process %d using buffer owned by %p\n",
			  DRM_CURRENTPID, buf->file_priv);
		return -EINVAL;
	}
	if (buf->pending) {
		DRM_ERROR("sending pending buffer %d\n", indirect->idx);
		return -EINVAL;
	}

	if (indirect->start < buf->used) {
		DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
			  indirect->start, buf->used);
		return -EINVAL;
	}

	RING_SPACE_TEST_WITH_RETURN(dev_priv);
	VB_AGE_TEST_WITH_RETURN(dev_priv);

	buf->used = indirect->end;

	/* Wait for the 3D stream to idle before the indirect buffer
	 * containing 2D acceleration commands is processed.
	 */
	BEGIN_RING(2);

	RADEON_WAIT_UNTIL_3D_IDLE();

	ADVANCE_RING();

	/* Dispatch the indirect buffer full of commands from the
	 * X server.  This is insecure and is thus only available to
	 * privileged clients.
	 */
	radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
	if (indirect->discard) {
		radeon_cp_discard_buffer(dev, buf);
	}

	COMMIT_RING();
	return 0;
}

static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_sarea_t *sarea_priv;
	struct drm_device_dma *dma = dev->dma;
	struct drm_buf *buf;
	drm_radeon_vertex2_t *vertex = data;
	int i;
	unsigned char laststate;

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}

	sarea_priv = dev_priv->sarea_priv;

	DRM_DEBUG("pid=%d index=%d discard=%d\n",
		  DRM_CURRENTPID, vertex->idx, vertex->discard);

	if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
		DRM_ERROR("buffer index %d (of %d max)\n",
			  vertex->idx, dma->buf_count - 1);
		return -EINVAL;
	}

	RING_SPACE_TEST_WITH_RETURN(dev_priv);
	VB_AGE_TEST_WITH_RETURN(dev_priv);

	buf = dma->buflist[vertex->idx];

	if (buf->file_priv != file_priv) {
		DRM_ERROR("process %d using buffer owned by %p\n",
			  DRM_CURRENTPID, buf->file_priv);
		return -EINVAL;
	}

	if (buf->pending) {
		DRM_ERROR("sending pending buffer %d\n", vertex->idx);
		return -EINVAL;
	}

	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
		return -EINVAL;

	for (laststate = 0xff, i = 0; i < vertex->nr_prims; i++) {
		drm_radeon_prim_t prim;
		drm_radeon_tcl_prim_t tclprim;

		if (DRM_COPY_FROM_USER(&prim, &vertex->prim[i], sizeof(prim)))
			return -EFAULT;

		if (prim.stateidx != laststate) {
			drm_radeon_state_t state;

			if (DRM_COPY_FROM_USER(&state,
					       &vertex->state[prim.stateidx],
					       sizeof(state)))
				return -EFAULT;

			if (radeon_emit_state2(dev_priv, file_priv, &state)) {
				DRM_ERROR("radeon_emit_state2 failed\n");
				return -EINVAL;
			}

			laststate = prim.stateidx;
		}

		tclprim.start = prim.start;
		tclprim.finish = prim.finish;
		tclprim.prim = prim.prim;
		tclprim.vc_format = prim.vc_format;

		if (prim.prim & RADEON_PRIM_WALK_IND) {
			tclprim.offset = prim.numverts * 64;
			tclprim.numverts = RADEON_MAX_VB_VERTS;	/* duh */

			radeon_cp_dispatch_indices(dev, buf, &tclprim);
		} else {
			tclprim.numverts = prim.numverts;
			tclprim.offset = 0;	/* not used */

			radeon_cp_dispatch_vertex(dev, buf, &tclprim);
		}

		if (sarea_priv->nbox == 1)
			sarea_priv->nbox = 0;
	}

	if (vertex->discard) {
		radeon_cp_discard_buffer(dev, buf);
	}

	COMMIT_RING();
	return 0;
}

static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
			       struct drm_file *file_priv,
			       drm_radeon_cmd_header_t header,
			       drm_radeon_kcmd_buffer_t *cmdbuf)
{
	int id = (int)header.packet.packet_id;
	int sz, reg;
	int *data = (int *)cmdbuf->buf;
	RING_LOCALS;

	if (id >= RADEON_MAX_STATE_PACKETS)
		return -EINVAL;

	sz = packet[id].len;
	reg = packet[id].start;

	if (sz * sizeof(int) > cmdbuf->bufsz) {
		DRM_ERROR("Packet size provided larger than data provided\n");
		return -EINVAL;
	}

	if (radeon_check_and_fixup_packets(dev_priv, file_priv, id, data)) {
		DRM_ERROR("Packet verification failed\n");
		return -EINVAL;
	}

	BEGIN_RING(sz + 1);
	OUT_RING(CP_PACKET0(reg, (sz - 1)));
	OUT_RING_TABLE(data, sz);
	ADVANCE_RING();

	cmdbuf->buf += sz * sizeof(int);
	cmdbuf->bufsz -= sz * sizeof(int);
	return 0;
}

static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv,
					  drm_radeon_cmd_header_t header,
					  drm_radeon_kcmd_buffer_t *cmdbuf)
{
	int sz = header.scalars.count;
	int start = header.scalars.offset;
	int stride = header.scalars.stride;
	RING_LOCALS;

	BEGIN_RING(3 + sz);
	OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
	OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
	OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
	OUT_RING_TABLE(cmdbuf->buf, sz);
	ADVANCE_RING();
	cmdbuf->buf += sz * sizeof(int);
	cmdbuf->bufsz -= sz * sizeof(int);
	return 0;
}

/* God this is ugly
 */
static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv,
					   drm_radeon_cmd_header_t header,
					   drm_radeon_kcmd_buffer_t *cmdbuf)
{
	int sz = header.scalars.count;
	int start = ((unsigned int)header.scalars.offset) + 0x100;
	int stride = header.scalars.stride;
	RING_LOCALS;

	BEGIN_RING(3 + sz);
	OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
	OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
	OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
	OUT_RING_TABLE(cmdbuf->buf, sz);
	ADVANCE_RING();
	cmdbuf->buf += sz * sizeof(int);
	cmdbuf->bufsz -= sz * sizeof(int);
	return 0;
}

static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv,
					  drm_radeon_cmd_header_t header,
					  drm_radeon_kcmd_buffer_t *cmdbuf)
{
	int sz = header.vectors.count;
	int start = header.vectors.offset;
	int stride = header.vectors.stride;
	RING_LOCALS;

	BEGIN_RING(5 + sz);
	OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
	OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
	OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
	OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
	OUT_RING_TABLE(cmdbuf->buf, sz);
	ADVANCE_RING();

	cmdbuf->buf += sz * sizeof(int);
	cmdbuf->bufsz -= sz * sizeof(int);
	return 0;
}

static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
					  drm_radeon_cmd_header_t header,
					  drm_radeon_kcmd_buffer_t *cmdbuf)
{
	int sz = header.veclinear.count * 4;
	int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
	RING_LOCALS;

	if (!sz)
		return 0;
	if (sz * 4 > cmdbuf->bufsz)
		return -EINVAL;

	BEGIN_RING(5 + sz);
	OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
	OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
	OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
	OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
	OUT_RING_TABLE(cmdbuf->buf, sz);
	ADVANCE_RING();

	cmdbuf->buf += sz * sizeof(int);
	cmdbuf->bufsz -= sz * sizeof(int);
	return 0;
}

static int radeon_emit_packet3(struct drm_device * dev,
			       struct drm_file *file_priv,
			       drm_radeon_kcmd_buffer_t *cmdbuf)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	unsigned int cmdsz;
	int ret;
	RING_LOCALS;

	DRM_DEBUG("\n");

	if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
						  cmdbuf, &cmdsz))) {
		DRM_ERROR("Packet verification failed\n");
		return ret;
	}

	BEGIN_RING(cmdsz);
	OUT_RING_TABLE(cmdbuf->buf, cmdsz);
	ADVANCE_RING();

	cmdbuf->buf += cmdsz * 4;
	cmdbuf->bufsz -= cmdsz * 4;
	return 0;
}

static int radeon_emit_packet3_cliprect(struct drm_device *dev,
					struct drm_file *file_priv,
					drm_radeon_kcmd_buffer_t *cmdbuf,
					int orig_nbox)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	struct drm_clip_rect box;
	unsigned int cmdsz;
	int ret;
	struct drm_clip_rect __user *boxes = cmdbuf->boxes;
	int i = 0;
	RING_LOCALS;

	DRM_DEBUG("\n");

	if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
						  cmdbuf, &cmdsz))) {
		DRM_ERROR("Packet verification failed\n");
		return ret;
	}

	if (!orig_nbox)
		goto out;

	do {
		if (i < cmdbuf->nbox) {
			if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box)))
				return -EFAULT;
			/* FIXME The second and subsequent times round
			 * this loop, send a WAIT_UNTIL_3D_IDLE before
			 * calling emit_clip_rect(). This fixes a
			 * lockup on fast machines when sending
			 * several cliprects with a cmdbuf, as when
			 * waving a 2D window over a 3D
			 * window. Something in the commands from user
			 * space seems to hang the card when they're
			 * sent several times in a row. That would be
			 * the correct place to fix it but this works
			 * around it until I can figure that out - Tim
			 * Smith */
			if (i) {
				BEGIN_RING(2);
				RADEON_WAIT_UNTIL_3D_IDLE();
				ADVANCE_RING();
			}
			radeon_emit_clip_rect(dev_priv, &box);
		}

		BEGIN_RING(cmdsz);
		OUT_RING_TABLE(cmdbuf->buf, cmdsz);
		ADVANCE_RING();

	} while (++i < cmdbuf->nbox);
	if (cmdbuf->nbox == 1)
		cmdbuf->nbox = 0;

      out:
	cmdbuf->buf += cmdsz * 4;
	cmdbuf->bufsz -= cmdsz * 4;
	return 0;
}

static int radeon_emit_wait(struct drm_device * dev, int flags)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	RING_LOCALS;

	DRM_DEBUG("%x\n", flags);
	switch (flags) {
	case RADEON_WAIT_2D:
		BEGIN_RING(2);
		RADEON_WAIT_UNTIL_2D_IDLE();
		ADVANCE_RING();
		break;
	case RADEON_WAIT_3D:
		BEGIN_RING(2);
		RADEON_WAIT_UNTIL_3D_IDLE();
		ADVANCE_RING();
		break;
	case RADEON_WAIT_2D | RADEON_WAIT_3D:
		BEGIN_RING(2);
		RADEON_WAIT_UNTIL_IDLE();
		ADVANCE_RING();
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	struct drm_device_dma *dma = dev->dma;
	struct drm_buf *buf = NULL;
	int idx;
	drm_radeon_kcmd_buffer_t *cmdbuf = data;
	drm_radeon_cmd_header_t header;
	int orig_nbox, orig_bufsz;
	char *kbuf = NULL;

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}

	RING_SPACE_TEST_WITH_RETURN(dev_priv);
	VB_AGE_TEST_WITH_RETURN(dev_priv);

	if (cmdbuf->bufsz > 64 * 1024 || cmdbuf->bufsz < 0) {
		return -EINVAL;
	}

	/* Allocate an in-kernel area and copy in the cmdbuf.  Do this to avoid
	 * races between checking values and using those values in other code,
	 * and simply to avoid a lot of function calls to copy in data.
	 */
	orig_bufsz = cmdbuf->bufsz;
	if (orig_bufsz != 0) {
		kbuf = drm_alloc(cmdbuf->bufsz, DRM_MEM_DRIVER);
		if (kbuf == NULL)
			return -ENOMEM;
		if (DRM_COPY_FROM_USER(kbuf, (void __user *)cmdbuf->buf,
				       cmdbuf->bufsz)) {
			drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
			return -EFAULT;
		}
		cmdbuf->buf = kbuf;
	}

	orig_nbox = cmdbuf->nbox;

	if (dev_priv->chip_family >= CHIP_R300) {
		int temp;
		temp = r300_do_cp_cmdbuf(dev, file_priv, cmdbuf);

		if (orig_bufsz != 0)
			drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);

		return temp;
	}

	/* microcode_version != r300 */
	while (cmdbuf->bufsz >= sizeof(header)) {

		header.i = *(int *)cmdbuf->buf;
		cmdbuf->buf += sizeof(header);
		cmdbuf->bufsz -= sizeof(header);

		switch (header.header.cmd_type) {
		case RADEON_CMD_PACKET:
			DRM_DEBUG("RADEON_CMD_PACKET\n");
			if (radeon_emit_packets
			    (dev_priv, file_priv, header, cmdbuf)) {
				DRM_ERROR("radeon_emit_packets failed\n");
				goto err;
			}
			break;

		case RADEON_CMD_SCALARS:
			DRM_DEBUG("RADEON_CMD_SCALARS\n");
			if (radeon_emit_scalars(dev_priv, header, cmdbuf)) {
				DRM_ERROR("radeon_emit_scalars failed\n");
				goto err;
			}
			break;

		case RADEON_CMD_VECTORS:
			DRM_DEBUG("RADEON_CMD_VECTORS\n");
			if (radeon_emit_vectors(dev_priv, header, cmdbuf)) {
				DRM_ERROR("radeon_emit_vectors failed\n");
				goto err;
			}
			break;

		case RADEON_CMD_DMA_DISCARD:
			DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
			idx = header.dma.buf_idx;
			if (idx < 0 || idx >= dma->buf_count) {
				DRM_ERROR("buffer index %d (of %d max)\n",
					  idx, dma->buf_count - 1);
				goto err;
			}

			buf = dma->buflist[idx];
			if (buf->file_priv != file_priv || buf->pending) {
				DRM_ERROR("bad buffer %p %p %d\n",
					  buf->file_priv, file_priv,
					  buf->pending);
				goto err;
			}

			radeon_cp_discard_buffer(dev, buf);
			break;

		case RADEON_CMD_PACKET3:
			DRM_DEBUG("RADEON_CMD_PACKET3\n");
			if (radeon_emit_packet3(dev, file_priv, cmdbuf)) {
				DRM_ERROR("radeon_emit_packet3 failed\n");
				goto err;
			}
			break;

		case RADEON_CMD_PACKET3_CLIP:
			DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
			if (radeon_emit_packet3_cliprect
			    (dev, file_priv, cmdbuf, orig_nbox)) {
				DRM_ERROR("radeon_emit_packet3_clip failed\n");
				goto err;
			}
			break;

		case RADEON_CMD_SCALARS2:
			DRM_DEBUG("RADEON_CMD_SCALARS2\n");
			if (radeon_emit_scalars2(dev_priv, header, cmdbuf)) {
				DRM_ERROR("radeon_emit_scalars2 failed\n");
				goto err;
			}
			break;

		case RADEON_CMD_WAIT:
			DRM_DEBUG("RADEON_CMD_WAIT\n");
			if (radeon_emit_wait(dev, header.wait.flags)) {
				DRM_ERROR("radeon_emit_wait failed\n");
				goto err;
			}
			break;
		case RADEON_CMD_VECLINEAR:
			DRM_DEBUG("RADEON_CMD_VECLINEAR\n");
			if (radeon_emit_veclinear(dev_priv, header, cmdbuf)) {
				DRM_ERROR("radeon_emit_veclinear failed\n");
				goto err;
			}
			break;

		default:
			DRM_ERROR("bad cmd_type %d at %p\n",
				  header.header.cmd_type,
				  cmdbuf->buf - sizeof(header));
			goto err;
		}
	}

	if (orig_bufsz != 0)
		drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);

	DRM_DEBUG("DONE\n");
	COMMIT_RING();
	return 0;

      err:
	if (orig_bufsz != 0)
		drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
	return -EINVAL;
}

static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_getparam_t *param = data;
	int value;

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}

	DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);

	switch (param->param) {
	case RADEON_PARAM_GART_BUFFER_OFFSET:
		value = dev_priv->gart_buffers_offset;
		break;
	case RADEON_PARAM_LAST_FRAME:
		dev_priv->stats.last_frame_reads++;
		value = GET_SCRATCH(0);
		break;
	case RADEON_PARAM_LAST_DISPATCH:
		value = GET_SCRATCH(1);
		break;
	case RADEON_PARAM_LAST_CLEAR:
		dev_priv->stats.last_clear_reads++;
		value = GET_SCRATCH(2);
		break;
	case RADEON_PARAM_IRQ_NR:
		value = dev->irq;
		break;
	case RADEON_PARAM_GART_BASE:
		value = dev_priv->gart_vm_start;
		break;
	case RADEON_PARAM_REGISTER_HANDLE:
		value = dev_priv->mmio->offset;
		break;
	case RADEON_PARAM_STATUS_HANDLE:
		value = dev_priv->ring_rptr_offset;
		break;
#ifndef __LP64__
		/*
		 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
		 * pointer which can't fit into an int-sized variable.  According to
		 * Michel Dänzer, the ioctl() is only used on embedded platforms, so
		 * not supporting it shouldn't be a problem.  If the same functionality
		 * is needed on 64-bit platforms, a new ioctl() would have to be added,
		 * so backwards-compatibility for the embedded platforms can be
		 * maintained.  --davidm 4-Feb-2004.
		 */
	case RADEON_PARAM_SAREA_HANDLE:
		/* The lock is the first dword in the sarea. */
		value = (long)dev->lock.hw_lock;
		break;
#endif
	case RADEON_PARAM_GART_TEX_HANDLE:
		value = dev_priv->gart_textures_offset;
		break;
	case RADEON_PARAM_SCRATCH_OFFSET:
		if (!dev_priv->writeback_works)
			return -EINVAL;
		value = RADEON_SCRATCH_REG_OFFSET;
		break;

	case RADEON_PARAM_CARD_TYPE:
		if (dev_priv->flags & RADEON_IS_PCIE)
			value = RADEON_CARD_PCIE;
		else if (dev_priv->flags & RADEON_IS_AGP)
			value = RADEON_CARD_AGP;
		else
			value = RADEON_CARD_PCI;
		break;
	case RADEON_PARAM_VBLANK_CRTC:
		value = radeon_vblank_crtc_get(dev);
		break;
	case RADEON_PARAM_FB_LOCATION:
		value = radeon_read_fb_location(dev_priv);
		break;
	case RADEON_PARAM_NUM_GB_PIPES:
		value = dev_priv->num_gb_pipes;
		break;
	default:
		DRM_DEBUG( "Invalid parameter %d\n", param->param );
		return -EINVAL;
	}

	if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
		DRM_ERROR("copy_to_user\n");
		return -EFAULT;
	}

	return 0;
}

static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_setparam_t *sp = data;
	struct drm_radeon_driver_file_fields *radeon_priv;

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}

	switch (sp->param) {
	case RADEON_SETPARAM_FB_LOCATION:
		radeon_priv = file_priv->driver_priv;
		radeon_priv->radeon_fb_delta = dev_priv->fb_location -
		    sp->value;
		break;
	case RADEON_SETPARAM_SWITCH_TILING:
		if (sp->value == 0) {
			DRM_DEBUG("color tiling disabled\n");
			dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
			dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
			if (dev_priv->sarea_priv)
				dev_priv->sarea_priv->tiling_enabled = 0;
		} else if (sp->value == 1) {
			DRM_DEBUG("color tiling enabled\n");
			dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
			dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
			if (dev_priv->sarea_priv)
				dev_priv->sarea_priv->tiling_enabled = 1;
		}
		break;
	case RADEON_SETPARAM_PCIGART_LOCATION:
		dev_priv->pcigart_offset = sp->value;
		dev_priv->pcigart_offset_set = 1;
		break;
	case RADEON_SETPARAM_NEW_MEMMAP:
		dev_priv->new_memmap = sp->value;
		break;
	case RADEON_SETPARAM_PCIGART_TABLE_SIZE:
		dev_priv->gart_info.table_size = sp->value;
		if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE)
			dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
		break;
	case RADEON_SETPARAM_VBLANK_CRTC:
		return radeon_vblank_crtc_set(dev, sp->value);
		break;
	default:
		DRM_DEBUG("Invalid parameter %d\n", sp->param);
		return -EINVAL;
	}

	return 0;
}

/* When a client dies:
 *    - Check for and clean up flipped page state
 *    - Free any alloced GART memory.
 *    - Free any alloced radeon surfaces.
 *
 * DRM infrastructure takes care of reclaiming dma buffers.
 */
void radeon_driver_preclose(struct drm_device *dev,
			    struct drm_file *file_priv)
{
	if (dev->dev_private) {
		drm_radeon_private_t *dev_priv = dev->dev_private;
		dev_priv->page_flipping = 0;
		radeon_mem_release(file_priv, dev_priv->gart_heap);
		radeon_mem_release(file_priv, dev_priv->fb_heap);
		radeon_surfaces_release(file_priv, dev_priv);
	}
}

void radeon_driver_lastclose(struct drm_device *dev)
{
	if (dev->dev_private) {
		drm_radeon_private_t *dev_priv = dev->dev_private;

		if (dev_priv->sarea_priv &&
		    dev_priv->sarea_priv->pfCurrentPage != 0)
			radeon_cp_dispatch_flip(dev);
	}

	radeon_do_release(dev);
}

int radeon_driver_open(struct drm_device *dev, struct drm_file *file_priv)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	struct drm_radeon_driver_file_fields *radeon_priv;

	DRM_DEBUG("\n");
	radeon_priv =
	    (struct drm_radeon_driver_file_fields *)
	    drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES);

	if (!radeon_priv)
		return -ENOMEM;

	file_priv->driver_priv = radeon_priv;

	if (dev_priv)
		radeon_priv->radeon_fb_delta = dev_priv->fb_location;
	else
		radeon_priv->radeon_fb_delta = 0;
	return 0;
}

void radeon_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
{
	struct drm_radeon_driver_file_fields *radeon_priv =
	    file_priv->driver_priv;

	drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES);
}

struct drm_ioctl_desc radeon_ioctls[] = {
	DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH)
};

int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);
2528' href='#n2528'>2528</a>
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<a id='n2775' href='#n2775'>2775</a>
<a id='n2776' href='#n2776'>2776</a>
<a id='n2777' href='#n2777'>2777</a>
<a id='n2778' href='#n2778'>2778</a>
<a id='n2779' href='#n2779'>2779</a>
<a id='n2780' href='#n2780'>2780</a>
<a id='n2781' href='#n2781'>2781</a>
<a id='n2782' href='#n2782'>2782</a>
<a id='n2783' href='#n2783'>2783</a>
<a id='n2784' href='#n2784'>2784</a>
<a id='n2785' href='#n2785'>2785</a>
<a id='n2786' href='#n2786'>2786</a>
<a id='n2787' href='#n2787'>2787</a>
<a id='n2788' href='#n2788'>2788</a>
<a id='n2789' href='#n2789'>2789</a>
<a id='n2790' href='#n2790'>2790</a>
<a id='n2791' href='#n2791'>2791</a>
<a id='n2792' href='#n2792'>2792</a>
<a id='n2793' href='#n2793'>2793</a>
<a id='n2794' href='#n2794'>2794</a>
<a id='n2795' href='#n2795'>2795</a>
<a id='n2796' href='#n2796'>2796</a>
<a id='n2797' href='#n2797'>2797</a>
<a id='n2798' href='#n2798'>2798</a>
<a id='n2799' href='#n2799'>2799</a>
<a id='n2800' href='#n2800'>2800</a>
<a id='n2801' href='#n2801'>2801</a>
<a id='n2802' href='#n2802'>2802</a>
<a id='n2803' href='#n2803'>2803</a>
<a id='n2804' href='#n2804'>2804</a>
<a id='n2805' href='#n2805'>2805</a>
<a id='n2806' href='#n2806'>2806</a>
<a id='n2807' href='#n2807'>2807</a>
<a id='n2808' href='#n2808'>2808</a>
<a id='n2809' href='#n2809'>2809</a>
<a id='n2810' href='#n2810'>2810</a>
<a id='n2811' href='#n2811'>2811</a>
<a id='n2812' href='#n2812'>2812</a>
<a id='n2813' href='#n2813'>2813</a>
<a id='n2814' href='#n2814'>2814</a>
<a id='n2815' href='#n2815'>2815</a>
<a id='n2816' href='#n2816'>2816</a>
<a id='n2817' href='#n2817'>2817</a>
<a id='n2818' href='#n2818'>2818</a>
<a id='n2819' href='#n2819'>2819</a>
<a id='n2820' href='#n2820'>2820</a>
<a id='n2821' href='#n2821'>2821</a>
<a id='n2822' href='#n2822'>2822</a>
<a id='n2823' href='#n2823'>2823</a>
<a id='n2824' href='#n2824'>2824</a>
<a id='n2825' href='#n2825'>2825</a>
<a id='n2826' href='#n2826'>2826</a>
<a id='n2827' href='#n2827'>2827</a>
<a id='n2828' href='#n2828'>2828</a>
<a id='n2829' href='#n2829'>2829</a>
<a id='n2830' href='#n2830'>2830</a>
<a id='n2831' href='#n2831'>2831</a>
<a id='n2832' href='#n2832'>2832</a>
<a id='n2833' href='#n2833'>2833</a>
<a id='n2834' href='#n2834'>2834</a>
<a id='n2835' href='#n2835'>2835</a>
<a id='n2836' href='#n2836'>2836</a>
<a id='n2837' href='#n2837'>2837</a>
<a id='n2838' href='#n2838'>2838</a>
<a id='n2839' href='#n2839'>2839</a>
<a id='n2840' href='#n2840'>2840</a>
<a id='n2841' href='#n2841'>2841</a>
<a id='n2842' href='#n2842'>2842</a>
<a id='n2843' href='#n2843'>2843</a>
<a id='n2844' href='#n2844'>2844</a>
<a id='n2845' href='#n2845'>2845</a>
<a id='n2846' href='#n2846'>2846</a>
<a id='n2847' href='#n2847'>2847</a>
<a id='n2848' href='#n2848'>2848</a>
<a id='n2849' href='#n2849'>2849</a>
<a id='n2850' href='#n2850'>2850</a>
<a id='n2851' href='#n2851'>2851</a>
<a id='n2852' href='#n2852'>2852</a>
<a id='n2853' href='#n2853'>2853</a>
<a id='n2854' href='#n2854'>2854</a>
<a id='n2855' href='#n2855'>2855</a>
<a id='n2856' href='#n2856'>2856</a>
<a id='n2857' href='#n2857'>2857</a>
<a id='n2858' href='#n2858'>2858</a>
<a id='n2859' href='#n2859'>2859</a>
<a id='n2860' href='#n2860'>2860</a>
<a id='n2861' href='#n2861'>2861</a>
<a id='n2862' href='#n2862'>2862</a>
<a id='n2863' href='#n2863'>2863</a>
<a id='n2864' href='#n2864'>2864</a>
<a id='n2865' href='#n2865'>2865</a>
<a id='n2866' href='#n2866'>2866</a>
<a id='n2867' href='#n2867'>2867</a>
<a id='n2868' href='#n2868'>2868</a>
<a id='n2869' href='#n2869'>2869</a>
<a id='n2870' href='#n2870'>2870</a>
<a id='n2871' href='#n2871'>2871</a>
<a id='n2872' href='#n2872'>2872</a>
<a id='n2873' href='#n2873'>2873</a>
<a id='n2874' href='#n2874'>2874</a>
<a id='n2875' href='#n2875'>2875</a>
<a id='n2876' href='#n2876'>2876</a>
<a id='n2877' href='#n2877'>2877</a>
<a id='n2878' href='#n2878'>2878</a>
<a id='n2879' href='#n2879'>2879</a>
<a id='n2880' href='#n2880'>2880</a>
<a id='n2881' href='#n2881'>2881</a>
<a id='n2882' href='#n2882'>2882</a>
<a id='n2883' href='#n2883'>2883</a>
<a id='n2884' href='#n2884'>2884</a>
<a id='n2885' href='#n2885'>2885</a>
<a id='n2886' href='#n2886'>2886</a>
<a id='n2887' href='#n2887'>2887</a>
<a id='n2888' href='#n2888'>2888</a>
<a id='n2889' href='#n2889'>2889</a>
<a id='n2890' href='#n2890'>2890</a>
<a id='n2891' href='#n2891'>2891</a>
<a id='n2892' href='#n2892'>2892</a>
<a id='n2893' href='#n2893'>2893</a>
<a id='n2894' href='#n2894'>2894</a>
<a id='n2895' href='#n2895'>2895</a>
<a id='n2896' href='#n2896'>2896</a>
<a id='n2897' href='#n2897'>2897</a>
<a id='n2898' href='#n2898'>2898</a>
<a id='n2899' href='#n2899'>2899</a>
<a id='n2900' href='#n2900'>2900</a>
<a id='n2901' href='#n2901'>2901</a>
<a id='n2902' href='#n2902'>2902</a>
<a id='n2903' href='#n2903'>2903</a>
<a id='n2904' href='#n2904'>2904</a>
<a id='n2905' href='#n2905'>2905</a>
<a id='n2906' href='#n2906'>2906</a>
<a id='n2907' href='#n2907'>2907</a>
<a id='n2908' href='#n2908'>2908</a>
<a id='n2909' href='#n2909'>2909</a>
<a id='n2910' href='#n2910'>2910</a>
<a id='n2911' href='#n2911'>2911</a>
<a id='n2912' href='#n2912'>2912</a>
<a id='n2913' href='#n2913'>2913</a>
<a id='n2914' href='#n2914'>2914</a>
<a id='n2915' href='#n2915'>2915</a>
<a id='n2916' href='#n2916'>2916</a>
<a id='n2917' href='#n2917'>2917</a>
<a id='n2918' href='#n2918'>2918</a>
<a id='n2919' href='#n2919'>2919</a>
<a id='n2920' href='#n2920'>2920</a>
<a id='n2921' href='#n2921'>2921</a>
<a id='n2922' href='#n2922'>2922</a>
<a id='n2923' href='#n2923'>2923</a>
<a id='n2924' href='#n2924'>2924</a>
<a id='n2925' href='#n2925'>2925</a>
<a id='n2926' href='#n2926'>2926</a>
<a id='n2927' href='#n2927'>2927</a>
<a id='n2928' href='#n2928'>2928</a>
<a id='n2929' href='#n2929'>2929</a>
<a id='n2930' href='#n2930'>2930</a>
<a id='n2931' href='#n2931'>2931</a>
<a id='n2932' href='#n2932'>2932</a>
<a id='n2933' href='#n2933'>2933</a>
<a id='n2934' href='#n2934'>2934</a>
<a id='n2935' href='#n2935'>2935</a>
<a id='n2936' href='#n2936'>2936</a>
<a id='n2937' href='#n2937'>2937</a>
<a id='n2938' href='#n2938'>2938</a>
<a id='n2939' href='#n2939'>2939</a>
<a id='n2940' href='#n2940'>2940</a>
<a id='n2941' href='#n2941'>2941</a>
<a id='n2942' href='#n2942'>2942</a>
<a id='n2943' href='#n2943'>2943</a>
<a id='n2944' href='#n2944'>2944</a>
<a id='n2945' href='#n2945'>2945</a>
<a id='n2946' href='#n2946'>2946</a>
<a id='n2947' href='#n2947'>2947</a>
<a id='n2948' href='#n2948'>2948</a>
<a id='n2949' href='#n2949'>2949</a>
<a id='n2950' href='#n2950'>2950</a>
<a id='n2951' href='#n2951'>2951</a>
<a id='n2952' href='#n2952'>2952</a>
<a id='n2953' href='#n2953'>2953</a>
<a id='n2954' href='#n2954'>2954</a>
<a id='n2955' href='#n2955'>2955</a>
<a id='n2956' href='#n2956'>2956</a>
<a id='n2957' href='#n2957'>2957</a>
<a id='n2958' href='#n2958'>2958</a>
<a id='n2959' href='#n2959'>2959</a>
<a id='n2960' href='#n2960'>2960</a>
<a id='n2961' href='#n2961'>2961</a>
<a id='n2962' href='#n2962'>2962</a>
<a id='n2963' href='#n2963'>2963</a>
<a id='n2964' href='#n2964'>2964</a>
<a id='n2965' href='#n2965'>2965</a>
<a id='n2966' href='#n2966'>2966</a>
<a id='n2967' href='#n2967'>2967</a>
<a id='n2968' href='#n2968'>2968</a>
<a id='n2969' href='#n2969'>2969</a>
<a id='n2970' href='#n2970'>2970</a>
<a id='n2971' href='#n2971'>2971</a>
<a id='n2972' href='#n2972'>2972</a>
<a id='n2973' href='#n2973'>2973</a>
<a id='n2974' href='#n2974'>2974</a>
<a id='n2975' href='#n2975'>2975</a>
<a id='n2976' href='#n2976'>2976</a>
<a id='n2977' href='#n2977'>2977</a>
<a id='n2978' href='#n2978'>2978</a>
<a id='n2979' href='#n2979'>2979</a>
<a id='n2980' href='#n2980'>2980</a>
<a id='n2981' href='#n2981'>2981</a>
<a id='n2982' href='#n2982'>2982</a>
<a id='n2983' href='#n2983'>2983</a>
<a id='n2984' href='#n2984'>2984</a>
<a id='n2985' href='#n2985'>2985</a>
<a id='n2986' href='#n2986'>2986</a>
<a id='n2987' href='#n2987'>2987</a>
<a id='n2988' href='#n2988'>2988</a>
<a id='n2989' href='#n2989'>2989</a>
<a id='n2990' href='#n2990'>2990</a>
<a id='n2991' href='#n2991'>2991</a>
<a id='n2992' href='#n2992'>2992</a>
<a id='n2993' href='#n2993'>2993</a>
<a id='n2994' href='#n2994'>2994</a>
<a id='n2995' href='#n2995'>2995</a>
<a id='n2996' href='#n2996'>2996</a>
<a id='n2997' href='#n2997'>2997</a>
<a id='n2998' href='#n2998'>2998</a>
<a id='n2999' href='#n2999'>2999</a>
<a id='n3000' href='#n3000'>3000</a>
<a id='n3001' href='#n3001'>3001</a>
<a id='n3002' href='#n3002'>3002</a>
<a id='n3003' href='#n3003'>3003</a>
<a id='n3004' href='#n3004'>3004</a>
<a id='n3005' href='#n3005'>3005</a>
<a id='n3006' href='#n3006'>3006</a>
<a id='n3007' href='#n3007'>3007</a>
<a id='n3008' href='#n3008'>3008</a>
<a id='n3009' href='#n3009'>3009</a>
<a id='n3010' href='#n3010'>3010</a>
<a id='n3011' href='#n3011'>3011</a>
<a id='n3012' href='#n3012'>3012</a>
<a id='n3013' href='#n3013'>3013</a>
<a id='n3014' href='#n3014'>3014</a>
<a id='n3015' href='#n3015'>3015</a>
<a id='n3016' href='#n3016'>3016</a>
<a id='n3017' href='#n3017'>3017</a>
<a id='n3018' href='#n3018'>3018</a>
<a id='n3019' href='#n3019'>3019</a>
<a id='n3020' href='#n3020'>3020</a>
<a id='n3021' href='#n3021'>3021</a>
<a id='n3022' href='#n3022'>3022</a>
<a id='n3023' href='#n3023'>3023</a>
<a id='n3024' href='#n3024'>3024</a>
<a id='n3025' href='#n3025'>3025</a>
<a id='n3026' href='#n3026'>3026</a>
<a id='n3027' href='#n3027'>3027</a>
<a id='n3028' href='#n3028'>3028</a>
<a id='n3029' href='#n3029'>3029</a>
<a id='n3030' href='#n3030'>3030</a>
<a id='n3031' href='#n3031'>3031</a>
<a id='n3032' href='#n3032'>3032</a>
<a id='n3033' href='#n3033'>3033</a>
<a id='n3034' href='#n3034'>3034</a>
<a id='n3035' href='#n3035'>3035</a>
<a id='n3036' href='#n3036'>3036</a>
<a id='n3037' href='#n3037'>3037</a>
<a id='n3038' href='#n3038'>3038</a>
<a id='n3039' href='#n3039'>3039</a>
<a id='n3040' href='#n3040'>3040</a>
<a id='n3041' href='#n3041'>3041</a>
<a id='n3042' href='#n3042'>3042</a>
<a id='n3043' href='#n3043'>3043</a>
<a id='n3044' href='#n3044'>3044</a>
<a id='n3045' href='#n3045'>3045</a>
<a id='n3046' href='#n3046'>3046</a>
<a id='n3047' href='#n3047'>3047</a>
<a id='n3048' href='#n3048'>3048</a>
<a id='n3049' href='#n3049'>3049</a>
<a id='n3050' href='#n3050'>3050</a>
<a id='n3051' href='#n3051'>3051</a>
<a id='n3052' href='#n3052'>3052</a>
<a id='n3053' href='#n3053'>3053</a>
<a id='n3054' href='#n3054'>3054</a>
<a id='n3055' href='#n3055'>3055</a>
<a id='n3056' href='#n3056'>3056</a>
<a id='n3057' href='#n3057'>3057</a>
<a id='n3058' href='#n3058'>3058</a>
<a id='n3059' href='#n3059'>3059</a>
<a id='n3060' href='#n3060'>3060</a>
<a id='n3061' href='#n3061'>3061</a>
<a id='n3062' href='#n3062'>3062</a>
<a id='n3063' href='#n3063'>3063</a>
<a id='n3064' href='#n3064'>3064</a>
<a id='n3065' href='#n3065'>3065</a>
<a id='n3066' href='#n3066'>3066</a>
<a id='n3067' href='#n3067'>3067</a>
<a id='n3068' href='#n3068'>3068</a>
<a id='n3069' href='#n3069'>3069</a>
<a id='n3070' href='#n3070'>3070</a>
<a id='n3071' href='#n3071'>3071</a>
<a id='n3072' href='#n3072'>3072</a>
<a id='n3073' href='#n3073'>3073</a>
<a id='n3074' href='#n3074'>3074</a>
<a id='n3075' href='#n3075'>3075</a>
<a id='n3076' href='#n3076'>3076</a>
<a id='n3077' href='#n3077'>3077</a>
<a id='n3078' href='#n3078'>3078</a>
<a id='n3079' href='#n3079'>3079</a>
<a id='n3080' href='#n3080'>3080</a>
<a id='n3081' href='#n3081'>3081</a>
<a id='n3082' href='#n3082'>3082</a>
<a id='n3083' href='#n3083'>3083</a>
<a id='n3084' href='#n3084'>3084</a>
<a id='n3085' href='#n3085'>3085</a>
<a id='n3086' href='#n3086'>3086</a>
<a id='n3087' href='#n3087'>3087</a>
<a id='n3088' href='#n3088'>3088</a>
<a id='n3089' href='#n3089'>3089</a>
<a id='n3090' href='#n3090'>3090</a>
<a id='n3091' href='#n3091'>3091</a>
<a id='n3092' href='#n3092'>3092</a>
<a id='n3093' href='#n3093'>3093</a>
<a id='n3094' href='#n3094'>3094</a>
<a id='n3095' href='#n3095'>3095</a>
<a id='n3096' href='#n3096'>3096</a>
<a id='n3097' href='#n3097'>3097</a>
<a id='n3098' href='#n3098'>3098</a>
<a id='n3099' href='#n3099'>3099</a>
<a id='n3100' href='#n3100'>3100</a>
<a id='n3101' href='#n3101'>3101</a>
<a id='n3102' href='#n3102'>3102</a>
<a id='n3103' href='#n3103'>3103</a>
<a id='n3104' href='#n3104'>3104</a>
<a id='n3105' href='#n3105'>3105</a>
<a id='n3106' href='#n3106'>3106</a>
<a id='n3107' href='#n3107'>3107</a>
<a id='n3108' href='#n3108'>3108</a>
<a id='n3109' href='#n3109'>3109</a>
<a id='n3110' href='#n3110'>3110</a>
<a id='n3111' href='#n3111'>3111</a>
<a id='n3112' href='#n3112'>3112</a>
<a id='n3113' href='#n3113'>3113</a>
<a id='n3114' href='#n3114'>3114</a>
<a id='n3115' href='#n3115'>3115</a>
<a id='n3116' href='#n3116'>3116</a>
<a id='n3117' href='#n3117'>3117</a>
<a id='n3118' href='#n3118'>3118</a>
<a id='n3119' href='#n3119'>3119</a>
<a id='n3120' href='#n3120'>3120</a>
<a id='n3121' href='#n3121'>3121</a>
<a id='n3122' href='#n3122'>3122</a>
<a id='n3123' href='#n3123'>3123</a>
<a id='n3124' href='#n3124'>3124</a>
<a id='n3125' href='#n3125'>3125</a>
<a id='n3126' href='#n3126'>3126</a>
<a id='n3127' href='#n3127'>3127</a>
<a id='n3128' href='#n3128'>3128</a>
<a id='n3129' href='#n3129'>3129</a>
<a id='n3130' href='#n3130'>3130</a>
<a id='n3131' href='#n3131'>3131</a>
<a id='n3132' href='#n3132'>3132</a>
<a id='n3133' href='#n3133'>3133</a>
<a id='n3134' href='#n3134'>3134</a>
<a id='n3135' href='#n3135'>3135</a>
<a id='n3136' href='#n3136'>3136</a>
<a id='n3137' href='#n3137'>3137</a>
<a id='n3138' href='#n3138'>3138</a>
<a id='n3139' href='#n3139'>3139</a>
<a id='n3140' href='#n3140'>3140</a>
<a id='n3141' href='#n3141'>3141</a>
<a id='n3142' href='#n3142'>3142</a>
<a id='n3143' href='#n3143'>3143</a>
<a id='n3144' href='#n3144'>3144</a>
<a id='n3145' href='#n3145'>3145</a>
<a id='n3146' href='#n3146'>3146</a>
<a id='n3147' href='#n3147'>3147</a>
<a id='n3148' href='#n3148'>3148</a>
<a id='n3149' href='#n3149'>3149</a>
<a id='n3150' href='#n3150'>3150</a>
<a id='n3151' href='#n3151'>3151</a>
<a id='n3152' href='#n3152'>3152</a>
<a id='n3153' href='#n3153'>3153</a>
<a id='n3154' href='#n3154'>3154</a>
<a id='n3155' href='#n3155'>3155</a>
<a id='n3156' href='#n3156'>3156</a>
<a id='n3157' href='#n3157'>3157</a>
<a id='n3158' href='#n3158'>3158</a>
<a id='n3159' href='#n3159'>3159</a>
<a id='n3160' href='#n3160'>3160</a>
<a id='n3161' href='#n3161'>3161</a>
<a id='n3162' href='#n3162'>3162</a>
<a id='n3163' href='#n3163'>3163</a>
<a id='n3164' href='#n3164'>3164</a>
<a id='n3165' href='#n3165'>3165</a>
<a id='n3166' href='#n3166'>3166</a>
<a id='n3167' href='#n3167'>3167</a>
<a id='n3168' href='#n3168'>3168</a>
<a id='n3169' href='#n3169'>3169</a>
<a id='n3170' href='#n3170'>3170</a>
<a id='n3171' href='#n3171'>3171</a>
<a id='n3172' href='#n3172'>3172</a>
<a id='n3173' href='#n3173'>3173</a>
<a id='n3174' href='#n3174'>3174</a>
<a id='n3175' href='#n3175'>3175</a>
<a id='n3176' href='#n3176'>3176</a>
<a id='n3177' href='#n3177'>3177</a>
<a id='n3178' href='#n3178'>3178</a>
<a id='n3179' href='#n3179'>3179</a>
<a id='n3180' href='#n3180'>3180</a>
<a id='n3181' href='#n3181'>3181</a>
<a id='n3182' href='#n3182'>3182</a>
<a id='n3183' href='#n3183'>3183</a>
<a id='n3184' href='#n3184'>3184</a>
<a id='n3185' href='#n3185'>3185</a>
<a id='n3186' href='#n3186'>3186</a>
<a id='n3187' href='#n3187'>3187</a>
<a id='n3188' href='#n3188'>3188</a>
<a id='n3189' href='#n3189'>3189</a>
<a id='n3190' href='#n3190'>3190</a>
<a id='n3191' href='#n3191'>3191</a>
<a id='n3192' href='#n3192'>3192</a>
<a id='n3193' href='#n3193'>3193</a>
<a id='n3194' href='#n3194'>3194</a>
<a id='n3195' href='#n3195'>3195</a>
<a id='n3196' href='#n3196'>3196</a>
<a id='n3197' href='#n3197'>3197</a>
<a id='n3198' href='#n3198'>3198</a>
<a id='n3199' href='#n3199'>3199</a>
<a id='n3200' href='#n3200'>3200</a>
<a id='n3201' href='#n3201'>3201</a>
<a id='n3202' href='#n3202'>3202</a>
<a id='n3203' href='#n3203'>3203</a>
<a id='n3204' href='#n3204'>3204</a>
<a id='n3205' href='#n3205'>3205</a>
<a id='n3206' href='#n3206'>3206</a>
<a id='n3207' href='#n3207'>3207</a>
<a id='n3208' href='#n3208'>3208</a>
<a id='n3209' href='#n3209'>3209</a>
<a id='n3210' href='#n3210'>3210</a>
<a id='n3211' href='#n3211'>3211</a>
<a id='n3212' href='#n3212'>3212</a>
<a id='n3213' href='#n3213'>3213</a>
<a id='n3214' href='#n3214'>3214</a>
<a id='n3215' href='#n3215'>3215</a>
<a id='n3216' href='#n3216'>3216</a>
<a id='n3217' href='#n3217'>3217</a>
<a id='n3218' href='#n3218'>3218</a>
<a id='n3219' href='#n3219'>3219</a>
<a id='n3220' href='#n3220'>3220</a>
<a id='n3221' href='#n3221'>3221</a>
<a id='n3222' href='#n3222'>3222</a>
<a id='n3223' href='#n3223'>3223</a>
<a id='n3224' href='#n3224'>3224</a>
<a id='n3225' href='#n3225'>3225</a>
<a id='n3226' href='#n3226'>3226</a>
<a id='n3227' href='#n3227'>3227</a>
<a id='n3228' href='#n3228'>3228</a>
<a id='n3229' href='#n3229'>3229</a>
<a id='n3230' href='#n3230'>3230</a>
<a id='n3231' href='#n3231'>3231</a>
<a id='n3232' href='#n3232'>3232</a>
<a id='n3233' href='#n3233'>3233</a>
<a id='n3234' href='#n3234'>3234</a>
<a id='n3235' href='#n3235'>3235</a>
<a id='n3236' href='#n3236'>3236</a>
<a id='n3237' href='#n3237'>3237</a>
<a id='n3238' href='#n3238'>3238</a>
<a id='n3239' href='#n3239'>3239</a>
<a id='n3240' href='#n3240'>3240</a>
<a id='n3241' href='#n3241'>3241</a>
<a id='n3242' href='#n3242'>3242</a>
<a id='n3243' href='#n3243'>3243</a>
<a id='n3244' href='#n3244'>3244</a>
<a id='n3245' href='#n3245'>3245</a>
<a id='n3246' href='#n3246'>3246</a>
<a id='n3247' href='#n3247'>3247</a>
<a id='n3248' href='#n3248'>3248</a>
<a id='n3249' href='#n3249'>3249</a>
<a id='n3250' href='#n3250'>3250</a>
<a id='n3251' href='#n3251'>3251</a>
<a id='n3252' href='#n3252'>3252</a>
<a id='n3253' href='#n3253'>3253</a>
<a id='n3254' href='#n3254'>3254</a>
<a id='n3255' href='#n3255'>3255</a>
<a id='n3256' href='#n3256'>3256</a>
<a id='n3257' href='#n3257'>3257</a>
<a id='n3258' href='#n3258'>3258</a>
<a id='n3259' href='#n3259'>3259</a>
<a id='n3260' href='#n3260'>3260</a>
<a id='n3261' href='#n3261'>3261</a>
<a id='n3262' href='#n3262'>3262</a>
<a id='n3263' href='#n3263'>3263</a>
<a id='n3264' href='#n3264'>3264</a>
<a id='n3265' href='#n3265'>3265</a>
<a id='n3266' href='#n3266'>3266</a>
<a id='n3267' href='#n3267'>3267</a>
<a id='n3268' href='#n3268'>3268</a>
<a id='n3269' href='#n3269'>3269</a>
<a id='n3270' href='#n3270'>3270</a>
<a id='n3271' href='#n3271'>3271</a>
<a id='n3272' href='#n3272'>3272</a>
<a id='n3273' href='#n3273'>3273</a>
<a id='n3274' href='#n3274'>3274</a>
<a id='n3275' href='#n3275'>3275</a>
<a id='n3276' href='#n3276'>3276</a>
<a id='n3277' href='#n3277'>3277</a>
<a id='n3278' href='#n3278'>3278</a>
<a id='n3279' href='#n3279'>3279</a>
<a id='n3280' href='#n3280'>3280</a>
<a id='n3281' href='#n3281'>3281</a>
<a id='n3282' href='#n3282'>3282</a>
<a id='n3283' href='#n3283'>3283</a>
<a id='n3284' href='#n3284'>3284</a>
<a id='n3285' href='#n3285'>3285</a>
<a id='n3286' href='#n3286'>3286</a>
<a id='n3287' href='#n3287'>3287</a>
<a id='n3288' href='#n3288'>3288</a>
<a id='n3289' href='#n3289'>3289</a>
<a id='n3290' href='#n3290'>3290</a>
<a id='n3291' href='#n3291'>3291</a>
<a id='n3292' href='#n3292'>3292</a>
<a id='n3293' href='#n3293'>3293</a>
<a id='n3294' href='#n3294'>3294</a>
<a id='n3295' href='#n3295'>3295</a>
<a id='n3296' href='#n3296'>3296</a>
<a id='n3297' href='#n3297'>3297</a>
<a id='n3298' href='#n3298'>3298</a>
<a id='n3299' href='#n3299'>3299</a>
<a id='n3300' href='#n3300'>3300</a>
<a id='n3301' href='#n3301'>3301</a>
<a id='n3302' href='#n3302'>3302</a>
<a id='n3303' href='#n3303'>3303</a>
<a id='n3304' href='#n3304'>3304</a>
<a id='n3305' href='#n3305'>3305</a>
<a id='n3306' href='#n3306'>3306</a>
<a id='n3307' href='#n3307'>3307</a>
<a id='n3308' href='#n3308'>3308</a>
<a id='n3309' href='#n3309'>3309</a>
<a id='n3310' href='#n3310'>3310</a>
<a id='n3311' href='#n3311'>3311</a>
<a id='n3312' href='#n3312'>3312</a>
<a id='n3313' href='#n3313'>3313</a>
<a id='n3314' href='#n3314'>3314</a>
<a id='n3315' href='#n3315'>3315</a>
<a id='n3316' href='#n3316'>3316</a>
<a id='n3317' href='#n3317'>3317</a>
<a id='n3318' href='#n3318'>3318</a>
<a id='n3319' href='#n3319'>3319</a>
<a id='n3320' href='#n3320'>3320</a>
<a id='n3321' href='#n3321'>3321</a>
<a id='n3322' href='#n3322'>3322</a>
<a id='n3323' href='#n3323'>3323</a>
<a id='n3324' href='#n3324'>3324</a>
<a id='n3325' href='#n3325'>3325</a>
<a id='n3326' href='#n3326'>3326</a>
<a id='n3327' href='#n3327'>3327</a>
<a id='n3328' href='#n3328'>3328</a>
<a id='n3329' href='#n3329'>3329</a>
<a id='n3330' href='#n3330'>3330</a>
<a id='n3331' href='#n3331'>3331</a>
<a id='n3332' href='#n3332'>3332</a>
<a id='n3333' href='#n3333'>3333</a>
<a id='n3334' href='#n3334'>3334</a>
<a id='n3335' href='#n3335'>3335</a>
<a id='n3336' href='#n3336'>3336</a>
<a id='n3337' href='#n3337'>3337</a>
<a id='n3338' href='#n3338'>3338</a>
<a id='n3339' href='#n3339'>3339</a>
<a id='n3340' href='#n3340'>3340</a>
<a id='n3341' href='#n3341'>3341</a>
<a id='n3342' href='#n3342'>3342</a>
<a id='n3343' href='#n3343'>3343</a>
<a id='n3344' href='#n3344'>3344</a>
<a id='n3345' href='#n3345'>3345</a>
<a id='n3346' href='#n3346'>3346</a>
<a id='n3347' href='#n3347'>3347</a>
<a id='n3348' href='#n3348'>3348</a>
<a id='n3349' href='#n3349'>3349</a>
<a id='n3350' href='#n3350'>3350</a>
<a id='n3351' href='#n3351'>3351</a>
<a id='n3352' href='#n3352'>3352</a>
<a id='n3353' href='#n3353'>3353</a>
<a id='n3354' href='#n3354'>3354</a>
<a id='n3355' href='#n3355'>3355</a>
<a id='n3356' href='#n3356'>3356</a>
<a id='n3357' href='#n3357'>3357</a>
<a id='n3358' href='#n3358'>3358</a>
<a id='n3359' href='#n3359'>3359</a>
<a id='n3360' href='#n3360'>3360</a>
<a id='n3361' href='#n3361'>3361</a>
<a id='n3362' href='#n3362'>3362</a>
<a id='n3363' href='#n3363'>3363</a>
<a id='n3364' href='#n3364'>3364</a>
<a id='n3365' href='#n3365'>3365</a>
<a id='n3366' href='#n3366'>3366</a>
<a id='n3367' href='#n3367'>3367</a>
<a id='n3368' href='#n3368'>3368</a>
<a id='n3369' href='#n3369'>3369</a>
<a id='n3370' href='#n3370'>3370</a>
<a id='n3371' href='#n3371'>3371</a>
<a id='n3372' href='#n3372'>3372</a>
<a id='n3373' href='#n3373'>3373</a>
<a id='n3374' href='#n3374'>3374</a>
<a id='n3375' href='#n3375'>3375</a>
<a id='n3376' href='#n3376'>3376</a>
<a id='n3377' href='#n3377'>3377</a>
<a id='n3378' href='#n3378'>3378</a>
<a id='n3379' href='#n3379'>3379</a>
<a id='n3380' href='#n3380'>3380</a>
<a id='n3381' href='#n3381'>3381</a>
<a id='n3382' href='#n3382'>3382</a>
<a id='n3383' href='#n3383'>3383</a>
<a id='n3384' href='#n3384'>3384</a>
<a id='n3385' href='#n3385'>3385</a>
<a id='n3386' href='#n3386'>3386</a>
<a id='n3387' href='#n3387'>3387</a>
<a id='n3388' href='#n3388'>3388</a>
<a id='n3389' href='#n3389'>3389</a>
<a id='n3390' href='#n3390'>3390</a>
<a id='n3391' href='#n3391'>3391</a>
<a id='n3392' href='#n3392'>3392</a>
<a id='n3393' href='#n3393'>3393</a>
<a id='n3394' href='#n3394'>3394</a>
<a id='n3395' href='#n3395'>3395</a>
<a id='n3396' href='#n3396'>3396</a>
<a id='n3397' href='#n3397'>3397</a>
<a id='n3398' href='#n3398'>3398</a>
<a id='n3399' href='#n3399'>3399</a>
<a id='n3400' href='#n3400'>3400</a>
<a id='n3401' href='#n3401'>3401</a>
<a id='n3402' href='#n3402'>3402</a>
<a id='n3403' href='#n3403'>3403</a>
<a id='n3404' href='#n3404'>3404</a>
<a id='n3405' href='#n3405'>3405</a>
<a id='n3406' href='#n3406'>3406</a>
<a id='n3407' href='#n3407'>3407</a>
<a id='n3408' href='#n3408'>3408</a>
<a id='n3409' href='#n3409'>3409</a>
<a id='n3410' href='#n3410'>3410</a>
<a id='n3411' href='#n3411'>3411</a>
<a id='n3412' href='#n3412'>3412</a>
<a id='n3413' href='#n3413'>3413</a>
<a id='n3414' href='#n3414'>3414</a>
<a id='n3415' href='#n3415'>3415</a>
<a id='n3416' href='#n3416'>3416</a>
<a id='n3417' href='#n3417'>3417</a>
<a id='n3418' href='#n3418'>3418</a>
<a id='n3419' href='#n3419'>3419</a>
<a id='n3420' href='#n3420'>3420</a>
<a id='n3421' href='#n3421'>3421</a>
<a id='n3422' href='#n3422'>3422</a>
<a id='n3423' href='#n3423'>3423</a>
<a id='n3424' href='#n3424'>3424</a>
<a id='n3425' href='#n3425'>3425</a>
<a id='n3426' href='#n3426'>3426</a>
<a id='n3427' href='#n3427'>3427</a>
<a id='n3428' href='#n3428'>3428</a>
<a id='n3429' href='#n3429'>3429</a>
<a id='n3430' href='#n3430'>3430</a>
<a id='n3431' href='#n3431'>3431</a>
<a id='n3432' href='#n3432'>3432</a>
<a id='n3433' href='#n3433'>3433</a>
<a id='n3434' href='#n3434'>3434</a>
<a id='n3435' href='#n3435'>3435</a>
<a id='n3436' href='#n3436'>3436</a>
<a id='n3437' href='#n3437'>3437</a>
<a id='n3438' href='#n3438'>3438</a>
<a id='n3439' href='#n3439'>3439</a>
<a id='n3440' href='#n3440'>3440</a>
<a id='n3441' href='#n3441'>3441</a>
<a id='n3442' href='#n3442'>3442</a>
<a id='n3443' href='#n3443'>3443</a>
<a id='n3444' href='#n3444'>3444</a>
<a id='n3445' href='#n3445'>3445</a>
<a id='n3446' href='#n3446'>3446</a>
<a id='n3447' href='#n3447'>3447</a>
<a id='n3448' href='#n3448'>3448</a>
<a id='n3449' href='#n3449'>3449</a>
<a id='n3450' href='#n3450'>3450</a>
<a id='n3451' href='#n3451'>3451</a>
<a id='n3452' href='#n3452'>3452</a>
<a id='n3453' href='#n3453'>3453</a>
<a id='n3454' href='#n3454'>3454</a>
<a id='n3455' href='#n3455'>3455</a>
<a id='n3456' href='#n3456'>3456</a>
<a id='n3457' href='#n3457'>3457</a>
<a id='n3458' href='#n3458'>3458</a>
<a id='n3459' href='#n3459'>3459</a>
<a id='n3460' href='#n3460'>3460</a>
<a id='n3461' href='#n3461'>3461</a>
<a id='n3462' href='#n3462'>3462</a>
<a id='n3463' href='#n3463'>3463</a>
<a id='n3464' href='#n3464'>3464</a>
<a id='n3465' href='#n3465'>3465</a>
<a id='n3466' href='#n3466'>3466</a>
<a id='n3467' href='#n3467'>3467</a>
<a id='n3468' href='#n3468'>3468</a>
<a id='n3469' href='#n3469'>3469</a>
<a id='n3470' href='#n3470'>3470</a>
<a id='n3471' href='#n3471'>3471</a>
<a id='n3472' href='#n3472'>3472</a>
<a id='n3473' href='#n3473'>3473</a>
<a id='n3474' href='#n3474'>3474</a>
<a id='n3475' href='#n3475'>3475</a>
<a id='n3476' href='#n3476'>3476</a>
<a id='n3477' href='#n3477'>3477</a>
<a id='n3478' href='#n3478'>3478</a>
<a id='n3479' href='#n3479'>3479</a>
<a id='n3480' href='#n3480'>3480</a>
<a id='n3481' href='#n3481'>3481</a>
<a id='n3482' href='#n3482'>3482</a>
<a id='n3483' href='#n3483'>3483</a>
<a id='n3484' href='#n3484'>3484</a>
<a id='n3485' href='#n3485'>3485</a>
<a id='n3486' href='#n3486'>3486</a>
<a id='n3487' href='#n3487'>3487</a>
<a id='n3488' href='#n3488'>3488</a>
<a id='n3489' href='#n3489'>3489</a>
<a id='n3490' href='#n3490'>3490</a>
<a id='n3491' href='#n3491'>3491</a>
<a id='n3492' href='#n3492'>3492</a>
<a id='n3493' href='#n3493'>3493</a>
<a id='n3494' href='#n3494'>3494</a>
<a id='n3495' href='#n3495'>3495</a>
<a id='n3496' href='#n3496'>3496</a>
<a id='n3497' href='#n3497'>3497</a>
<a id='n3498' href='#n3498'>3498</a>
<a id='n3499' href='#n3499'>3499</a>
<a id='n3500' href='#n3500'>3500</a>
<a id='n3501' href='#n3501'>3501</a>
<a id='n3502' href='#n3502'>3502</a>
<a id='n3503' href='#n3503'>3503</a>
<a id='n3504' href='#n3504'>3504</a>
<a id='n3505' href='#n3505'>3505</a>
<a id='n3506' href='#n3506'>3506</a>
<a id='n3507' href='#n3507'>3507</a>
<a id='n3508' href='#n3508'>3508</a>
<a id='n3509' href='#n3509'>3509</a>
<a id='n3510' href='#n3510'>3510</a>
<a id='n3511' href='#n3511'>3511</a>
<a id='n3512' href='#n3512'>3512</a>
<a id='n3513' href='#n3513'>3513</a>
<a id='n3514' href='#n3514'>3514</a>
<a id='n3515' href='#n3515'>3515</a>
<a id='n3516' href='#n3516'>3516</a>
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<a id='n3518' href='#n3518'>3518</a>
<a id='n3519' href='#n3519'>3519</a>
<a id='n3520' href='#n3520'>3520</a>
<a id='n3521' href='#n3521'>3521</a>
<a id='n3522' href='#n3522'>3522</a>
<a id='n3523' href='#n3523'>3523</a>
<a id='n3524' href='#n3524'>3524</a>
<a id='n3525' href='#n3525'>3525</a>
<a id='n3526' href='#n3526'>3526</a>
<a id='n3527' href='#n3527'>3527</a>
<a id='n3528' href='#n3528'>3528</a>
<a id='n3529' href='#n3529'>3529</a>
<a id='n3530' href='#n3530'>3530</a>
<a id='n3531' href='#n3531'>3531</a>
<a id='n3532' href='#n3532'>3532</a>
<a id='n3533' href='#n3533'>3533</a>
<a id='n3534' href='#n3534'>3534</a>
<a id='n3535' href='#n3535'>3535</a>
<a id='n3536' href='#n3536'>3536</a>
<a id='n3537' href='#n3537'>3537</a>
<a id='n3538' href='#n3538'>3538</a>
<a id='n3539' href='#n3539'>3539</a>
<a id='n3540' href='#n3540'>3540</a>
<a id='n3541' href='#n3541'>3541</a>
<a id='n3542' href='#n3542'>3542</a>
<a id='n3543' href='#n3543'>3543</a>
<a id='n3544' href='#n3544'>3544</a>
<a id='n3545' href='#n3545'>3545</a>
<a id='n3546' href='#n3546'>3546</a>
<a id='n3547' href='#n3547'>3547</a>
<a id='n3548' href='#n3548'>3548</a>
<a id='n3549' href='#n3549'>3549</a>
<a id='n3550' href='#n3550'>3550</a>
<a id='n3551' href='#n3551'>3551</a>
<a id='n3552' href='#n3552'>3552</a>
<a id='n3553' href='#n3553'>3553</a>
<a id='n3554' href='#n3554'>3554</a>
<a id='n3555' href='#n3555'>3555</a>
<a id='n3556' href='#n3556'>3556</a>
<a id='n3557' href='#n3557'>3557</a>
<a id='n3558' href='#n3558'>3558</a>
<a id='n3559' href='#n3559'>3559</a>
<a id='n3560' href='#n3560'>3560</a>
<a id='n3561' href='#n3561'>3561</a>
<a id='n3562' href='#n3562'>3562</a>
<a id='n3563' href='#n3563'>3563</a>
<a id='n3564' href='#n3564'>3564</a>
<a id='n3565' href='#n3565'>3565</a>
<a id='n3566' href='#n3566'>3566</a>
<a id='n3567' href='#n3567'>3567</a>
<a id='n3568' href='#n3568'>3568</a>
<a id='n3569' href='#n3569'>3569</a>
<a id='n3570' href='#n3570'>3570</a>
<a id='n3571' href='#n3571'>3571</a>
<a id='n3572' href='#n3572'>3572</a>
<a id='n3573' href='#n3573'>3573</a>
<a id='n3574' href='#n3574'>3574</a>
<a id='n3575' href='#n3575'>3575</a>
<a id='n3576' href='#n3576'>3576</a>
<a id='n3577' href='#n3577'>3577</a>
<a id='n3578' href='#n3578'>3578</a>
<a id='n3579' href='#n3579'>3579</a>
<a id='n3580' href='#n3580'>3580</a>
<a id='n3581' href='#n3581'>3581</a>
<a id='n3582' href='#n3582'>3582</a>
<a id='n3583' href='#n3583'>3583</a>
<a id='n3584' href='#n3584'>3584</a>
<a id='n3585' href='#n3585'>3585</a>
<a id='n3586' href='#n3586'>3586</a>
<a id='n3587' href='#n3587'>3587</a>
<a id='n3588' href='#n3588'>3588</a>
<a id='n3589' href='#n3589'>3589</a>
<a id='n3590' href='#n3590'>3590</a>
<a id='n3591' href='#n3591'>3591</a>
<a id='n3592' href='#n3592'>3592</a>
<a id='n3593' href='#n3593'>3593</a>
<a id='n3594' href='#n3594'>3594</a>
<a id='n3595' href='#n3595'>3595</a>
<a id='n3596' href='#n3596'>3596</a>
<a id='n3597' href='#n3597'>3597</a>
<a id='n3598' href='#n3598'>3598</a>
<a id='n3599' href='#n3599'>3599</a>
<a id='n3600' href='#n3600'>3600</a>
<a id='n3601' href='#n3601'>3601</a>
<a id='n3602' href='#n3602'>3602</a>
<a id='n3603' href='#n3603'>3603</a>
<a id='n3604' href='#n3604'>3604</a>
<a id='n3605' href='#n3605'>3605</a>
<a id='n3606' href='#n3606'>3606</a>
<a id='n3607' href='#n3607'>3607</a>
<a id='n3608' href='#n3608'>3608</a>
<a id='n3609' href='#n3609'>3609</a>
<a id='n3610' href='#n3610'>3610</a>
<a id='n3611' href='#n3611'>3611</a>
<a id='n3612' href='#n3612'>3612</a>
<a id='n3613' href='#n3613'>3613</a>
<a id='n3614' href='#n3614'>3614</a>
<a id='n3615' href='#n3615'>3615</a>
<a id='n3616' href='#n3616'>3616</a>
<a id='n3617' href='#n3617'>3617</a>
<a id='n3618' href='#n3618'>3618</a>
<a id='n3619' href='#n3619'>3619</a>
<a id='n3620' href='#n3620'>3620</a>
<a id='n3621' href='#n3621'>3621</a>
<a id='n3622' href='#n3622'>3622</a>
<a id='n3623' href='#n3623'>3623</a>
<a id='n3624' href='#n3624'>3624</a>
<a id='n3625' href='#n3625'>3625</a>
<a id='n3626' href='#n3626'>3626</a>
<a id='n3627' href='#n3627'>3627</a>
<a id='n3628' href='#n3628'>3628</a>
<a id='n3629' href='#n3629'>3629</a>
<a id='n3630' href='#n3630'>3630</a>
<a id='n3631' href='#n3631'>3631</a>
<a id='n3632' href='#n3632'>3632</a>
<a id='n3633' href='#n3633'>3633</a>
<a id='n3634' href='#n3634'>3634</a>
<a id='n3635' href='#n3635'>3635</a>
<a id='n3636' href='#n3636'>3636</a>
<a id='n3637' href='#n3637'>3637</a>
<a id='n3638' href='#n3638'>3638</a>
<a id='n3639' href='#n3639'>3639</a>
<a id='n3640' href='#n3640'>3640</a>
<a id='n3641' href='#n3641'>3641</a>
<a id='n3642' href='#n3642'>3642</a>
<a id='n3643' href='#n3643'>3643</a>
<a id='n3644' href='#n3644'>3644</a>
<a id='n3645' href='#n3645'>3645</a>
<a id='n3646' href='#n3646'>3646</a>
<a id='n3647' href='#n3647'>3647</a>
<a id='n3648' href='#n3648'>3648</a>
<a id='n3649' href='#n3649'>3649</a>
<a id='n3650' href='#n3650'>3650</a>
<a id='n3651' href='#n3651'>3651</a>
<a id='n3652' href='#n3652'>3652</a>
<a id='n3653' href='#n3653'>3653</a>
<a id='n3654' href='#n3654'>3654</a>
<a id='n3655' href='#n3655'>3655</a>
<a id='n3656' href='#n3656'>3656</a>
<a id='n3657' href='#n3657'>3657</a>
<a id='n3658' href='#n3658'>3658</a>
<a id='n3659' href='#n3659'>3659</a>
<a id='n3660' href='#n3660'>3660</a>
<a id='n3661' href='#n3661'>3661</a>
<a id='n3662' href='#n3662'>3662</a>
<a id='n3663' href='#n3663'>3663</a>
<a id='n3664' href='#n3664'>3664</a>
<a id='n3665' href='#n3665'>3665</a>
<a id='n3666' href='#n3666'>3666</a>
<a id='n3667' href='#n3667'>3667</a>
<a id='n3668' href='#n3668'>3668</a>
<a id='n3669' href='#n3669'>3669</a>
<a id='n3670' href='#n3670'>3670</a>
<a id='n3671' href='#n3671'>3671</a>
<a id='n3672' href='#n3672'>3672</a>
<a id='n3673' href='#n3673'>3673</a>
<a id='n3674' href='#n3674'>3674</a>
<a id='n3675' href='#n3675'>3675</a>
<a id='n3676' href='#n3676'>3676</a>
<a id='n3677' href='#n3677'>3677</a>
<a id='n3678' href='#n3678'>3678</a>
<a id='n3679' href='#n3679'>3679</a>
<a id='n3680' href='#n3680'>3680</a>
<a id='n3681' href='#n3681'>3681</a>
<a id='n3682' href='#n3682'>3682</a>
<a id='n3683' href='#n3683'>3683</a>
<a id='n3684' href='#n3684'>3684</a>
<a id='n3685' href='#n3685'>3685</a>
<a id='n3686' href='#n3686'>3686</a>
<a id='n3687' href='#n3687'>3687</a>
<a id='n3688' href='#n3688'>3688</a>
<a id='n3689' href='#n3689'>3689</a>
<a id='n3690' href='#n3690'>3690</a>
<a id='n3691' href='#n3691'>3691</a>
<a id='n3692' href='#n3692'>3692</a>
<a id='n3693' href='#n3693'>3693</a>
<a id='n3694' href='#n3694'>3694</a>
<a id='n3695' href='#n3695'>3695</a>
<a id='n3696' href='#n3696'>3696</a>
<a id='n3697' href='#n3697'>3697</a>
<a id='n3698' href='#n3698'>3698</a>
<a id='n3699' href='#n3699'>3699</a>
<a id='n3700' href='#n3700'>3700</a>
<a id='n3701' href='#n3701'>3701</a>
<a id='n3702' href='#n3702'>3702</a>
<a id='n3703' href='#n3703'>3703</a>
<a id='n3704' href='#n3704'>3704</a>
<a id='n3705' href='#n3705'>3705</a>
<a id='n3706' href='#n3706'>3706</a>
<a id='n3707' href='#n3707'>3707</a>
<a id='n3708' href='#n3708'>3708</a>
<a id='n3709' href='#n3709'>3709</a>
<a id='n3710' href='#n3710'>3710</a>
<a id='n3711' href='#n3711'>3711</a>
<a id='n3712' href='#n3712'>3712</a>
<a id='n3713' href='#n3713'>3713</a>
<a id='n3714' href='#n3714'>3714</a>
<a id='n3715' href='#n3715'>3715</a>
<a id='n3716' href='#n3716'>3716</a>
<a id='n3717' href='#n3717'>3717</a>
<a id='n3718' href='#n3718'>3718</a>
<a id='n3719' href='#n3719'>3719</a>
<a id='n3720' href='#n3720'>3720</a>
<a id='n3721' href='#n3721'>3721</a>
<a id='n3722' href='#n3722'>3722</a>
<a id='n3723' href='#n3723'>3723</a>
<a id='n3724' href='#n3724'>3724</a>
<a id='n3725' href='#n3725'>3725</a>
<a id='n3726' href='#n3726'>3726</a>
<a id='n3727' href='#n3727'>3727</a>
<a id='n3728' href='#n3728'>3728</a>
<a id='n3729' href='#n3729'>3729</a>
<a id='n3730' href='#n3730'>3730</a>
<a id='n3731' href='#n3731'>3731</a>
<a id='n3732' href='#n3732'>3732</a>
<a id='n3733' href='#n3733'>3733</a>
<a id='n3734' href='#n3734'>3734</a>
<a id='n3735' href='#n3735'>3735</a>
<a id='n3736' href='#n3736'>3736</a>
<a id='n3737' href='#n3737'>3737</a>
<a id='n3738' href='#n3738'>3738</a>
<a id='n3739' href='#n3739'>3739</a>
<a id='n3740' href='#n3740'>3740</a>
<a id='n3741' href='#n3741'>3741</a>
<a id='n3742' href='#n3742'>3742</a>
<a id='n3743' href='#n3743'>3743</a>
<a id='n3744' href='#n3744'>3744</a>
<a id='n3745' href='#n3745'>3745</a>
<a id='n3746' href='#n3746'>3746</a>
<a id='n3747' href='#n3747'>3747</a>
<a id='n3748' href='#n3748'>3748</a>
<a id='n3749' href='#n3749'>3749</a>
<a id='n3750' href='#n3750'>3750</a>
<a id='n3751' href='#n3751'>3751</a>
<a id='n3752' href='#n3752'>3752</a>
<a id='n3753' href='#n3753'>3753</a>
<a id='n3754' href='#n3754'>3754</a>
<a id='n3755' href='#n3755'>3755</a>
<a id='n3756' href='#n3756'>3756</a>
<a id='n3757' href='#n3757'>3757</a>
<a id='n3758' href='#n3758'>3758</a>
<a id='n3759' href='#n3759'>3759</a>
<a id='n3760' href='#n3760'>3760</a>
<a id='n3761' href='#n3761'>3761</a>
<a id='n3762' href='#n3762'>3762</a>
<a id='n3763' href='#n3763'>3763</a>
<a id='n3764' href='#n3764'>3764</a>
<a id='n3765' href='#n3765'>3765</a>
<a id='n3766' href='#n3766'>3766</a>
<a id='n3767' href='#n3767'>3767</a>
<a id='n3768' href='#n3768'>3768</a>
<a id='n3769' href='#n3769'>3769</a>
<a id='n3770' href='#n3770'>3770</a>
<a id='n3771' href='#n3771'>3771</a>
<a id='n3772' href='#n3772'>3772</a>
<a id='n3773' href='#n3773'>3773</a>
<a id='n3774' href='#n3774'>3774</a>
<a id='n3775' href='#n3775'>3775</a>
<a id='n3776' href='#n3776'>3776</a>
<a id='n3777' href='#n3777'>3777</a>
<a id='n3778' href='#n3778'>3778</a>
<a id='n3779' href='#n3779'>3779</a>
<a id='n3780' href='#n3780'>3780</a>
<a id='n3781' href='#n3781'>3781</a>
<a id='n3782' href='#n3782'>3782</a>
<a id='n3783' href='#n3783'>3783</a>
<a id='n3784' href='#n3784'>3784</a>
<a id='n3785' href='#n3785'>3785</a>
<a id='n3786' href='#n3786'>3786</a>
<a id='n3787' href='#n3787'>3787</a>
<a id='n3788' href='#n3788'>3788</a>
<a id='n3789' href='#n3789'>3789</a>
<a id='n3790' href='#n3790'>3790</a>
<a id='n3791' href='#n3791'>3791</a>
<a id='n3792' href='#n3792'>3792</a>
<a id='n3793' href='#n3793'>3793</a>
<a id='n3794' href='#n3794'>3794</a>
<a id='n3795' href='#n3795'>3795</a>
<a id='n3796' href='#n3796'>3796</a>
<a id='n3797' href='#n3797'>3797</a>
<a id='n3798' href='#n3798'>3798</a>
<a id='n3799' href='#n3799'>3799</a>
<a id='n3800' href='#n3800'>3800</a>
<a id='n3801' href='#n3801'>3801</a>
<a id='n3802' href='#n3802'>3802</a>
<a id='n3803' href='#n3803'>3803</a>
<a id='n3804' href='#n3804'>3804</a>
<a id='n3805' href='#n3805'>3805</a>
<a id='n3806' href='#n3806'>3806</a>
<a id='n3807' href='#n3807'>3807</a>
<a id='n3808' href='#n3808'>3808</a>
<a id='n3809' href='#n3809'>3809</a>
<a id='n3810' href='#n3810'>3810</a>
<a id='n3811' href='#n3811'>3811</a>
<a id='n3812' href='#n3812'>3812</a>
<a id='n3813' href='#n3813'>3813</a>
<a id='n3814' href='#n3814'>3814</a>
<a id='n3815' href='#n3815'>3815</a>
<a id='n3816' href='#n3816'>3816</a>
<a id='n3817' href='#n3817'>3817</a>
<a id='n3818' href='#n3818'>3818</a>
<a id='n3819' href='#n3819'>3819</a>
<a id='n3820' href='#n3820'>3820</a>
<a id='n3821' href='#n3821'>3821</a>
<a id='n3822' href='#n3822'>3822</a>
<a id='n3823' href='#n3823'>3823</a>
<a id='n3824' href='#n3824'>3824</a>
<a id='n3825' href='#n3825'>3825</a>
<a id='n3826' href='#n3826'>3826</a>
<a id='n3827' href='#n3827'>3827</a>
<a id='n3828' href='#n3828'>3828</a>
<a id='n3829' href='#n3829'>3829</a>
<a id='n3830' href='#n3830'>3830</a>
<a id='n3831' href='#n3831'>3831</a>
<a id='n3832' href='#n3832'>3832</a>
<a id='n3833' href='#n3833'>3833</a>
<a id='n3834' href='#n3834'>3834</a>
<a id='n3835' href='#n3835'>3835</a>
<a id='n3836' href='#n3836'>3836</a>
<a id='n3837' href='#n3837'>3837</a>
<a id='n3838' href='#n3838'>3838</a>
<a id='n3839' href='#n3839'>3839</a>
<a id='n3840' href='#n3840'>3840</a>
<a id='n3841' href='#n3841'>3841</a>
<a id='n3842' href='#n3842'>3842</a>
<a id='n3843' href='#n3843'>3843</a>
<a id='n3844' href='#n3844'>3844</a>
<a id='n3845' href='#n3845'>3845</a>
<a id='n3846' href='#n3846'>3846</a>
<a id='n3847' href='#n3847'>3847</a>
<a id='n3848' href='#n3848'>3848</a>
<a id='n3849' href='#n3849'>3849</a>
<a id='n3850' href='#n3850'>3850</a>
<a id='n3851' href='#n3851'>3851</a>
<a id='n3852' href='#n3852'>3852</a>
<a id='n3853' href='#n3853'>3853</a>
<a id='n3854' href='#n3854'>3854</a>
<a id='n3855' href='#n3855'>3855</a>
<a id='n3856' href='#n3856'>3856</a>
<a id='n3857' href='#n3857'>3857</a>
<a id='n3858' href='#n3858'>3858</a>
<a id='n3859' href='#n3859'>3859</a>
<a id='n3860' href='#n3860'>3860</a>
<a id='n3861' href='#n3861'>3861</a>
<a id='n3862' href='#n3862'>3862</a>
<a id='n3863' href='#n3863'>3863</a>
<a id='n3864' href='#n3864'>3864</a>
<a id='n3865' href='#n3865'>3865</a>
<a id='n3866' href='#n3866'>3866</a>
<a id='n3867' href='#n3867'>3867</a>
<a id='n3868' href='#n3868'>3868</a>
<a id='n3869' href='#n3869'>3869</a>
<a id='n3870' href='#n3870'>3870</a>
<a id='n3871' href='#n3871'>3871</a>
<a id='n3872' href='#n3872'>3872</a>
<a id='n3873' href='#n3873'>3873</a>
<a id='n3874' href='#n3874'>3874</a>
<a id='n3875' href='#n3875'>3875</a>
<a id='n3876' href='#n3876'>3876</a>
<a id='n3877' href='#n3877'>3877</a>
<a id='n3878' href='#n3878'>3878</a>
<a id='n3879' href='#n3879'>3879</a>
<a id='n3880' href='#n3880'>3880</a>
<a id='n3881' href='#n3881'>3881</a>
<a id='n3882' href='#n3882'>3882</a>
<a id='n3883' href='#n3883'>3883</a>
<a id='n3884' href='#n3884'>3884</a>
<a id='n3885' href='#n3885'>3885</a>
<a id='n3886' href='#n3886'>3886</a>
<a id='n3887' href='#n3887'>3887</a>
<a id='n3888' href='#n3888'>3888</a>
<a id='n3889' href='#n3889'>3889</a>
<a id='n3890' href='#n3890'>3890</a>
<a id='n3891' href='#n3891'>3891</a>
<a id='n3892' href='#n3892'>3892</a>
<a id='n3893' href='#n3893'>3893</a>
<a id='n3894' href='#n3894'>3894</a>
<a id='n3895' href='#n3895'>3895</a>
<a id='n3896' href='#n3896'>3896</a>
<a id='n3897' href='#n3897'>3897</a>
<a id='n3898' href='#n3898'>3898</a>
<a id='n3899' href='#n3899'>3899</a>
<a id='n3900' href='#n3900'>3900</a>
<a id='n3901' href='#n3901'>3901</a>
<a id='n3902' href='#n3902'>3902</a>
<a id='n3903' href='#n3903'>3903</a>
<a id='n3904' href='#n3904'>3904</a>
<a id='n3905' href='#n3905'>3905</a>
<a id='n3906' href='#n3906'>3906</a>
<a id='n3907' href='#n3907'>3907</a>
<a id='n3908' href='#n3908'>3908</a>
<a id='n3909' href='#n3909'>3909</a>
<a id='n3910' href='#n3910'>3910</a>
<a id='n3911' href='#n3911'>3911</a>
<a id='n3912' href='#n3912'>3912</a>
<a id='n3913' href='#n3913'>3913</a>
<a id='n3914' href='#n3914'>3914</a>
<a id='n3915' href='#n3915'>3915</a>
<a id='n3916' href='#n3916'>3916</a>
<a id='n3917' href='#n3917'>3917</a>
<a id='n3918' href='#n3918'>3918</a>
<a id='n3919' href='#n3919'>3919</a>
<a id='n3920' href='#n3920'>3920</a>
<a id='n3921' href='#n3921'>3921</a>
<a id='n3922' href='#n3922'>3922</a>
<a id='n3923' href='#n3923'>3923</a>
<a id='n3924' href='#n3924'>3924</a>
<a id='n3925' href='#n3925'>3925</a>
<a id='n3926' href='#n3926'>3926</a>
<a id='n3927' href='#n3927'>3927</a>
<a id='n3928' href='#n3928'>3928</a>
<a id='n3929' href='#n3929'>3929</a>
<a id='n3930' href='#n3930'>3930</a>
<a id='n3931' href='#n3931'>3931</a>
<a id='n3932' href='#n3932'>3932</a>
<a id='n3933' href='#n3933'>3933</a>
<a id='n3934' href='#n3934'>3934</a>
<a id='n3935' href='#n3935'>3935</a>
<a id='n3936' href='#n3936'>3936</a>
<a id='n3937' href='#n3937'>3937</a>
<a id='n3938' href='#n3938'>3938</a>
<a id='n3939' href='#n3939'>3939</a>
<a id='n3940' href='#n3940'>3940</a>
<a id='n3941' href='#n3941'>3941</a>
<a id='n3942' href='#n3942'>3942</a>
<a id='n3943' href='#n3943'>3943</a>
<a id='n3944' href='#n3944'>3944</a>
<a id='n3945' href='#n3945'>3945</a>
<a id='n3946' href='#n3946'>3946</a>
<a id='n3947' href='#n3947'>3947</a>
<a id='n3948' href='#n3948'>3948</a>
<a id='n3949' href='#n3949'>3949</a>
<a id='n3950' href='#n3950'>3950</a>
<a id='n3951' href='#n3951'>3951</a>
<a id='n3952' href='#n3952'>3952</a>
<a id='n3953' href='#n3953'>3953</a>
<a id='n3954' href='#n3954'>3954</a>
<a id='n3955' href='#n3955'>3955</a>
<a id='n3956' href='#n3956'>3956</a>
<a id='n3957' href='#n3957'>3957</a>
<a id='n3958' href='#n3958'>3958</a>
<a id='n3959' href='#n3959'>3959</a>
<a id='n3960' href='#n3960'>3960</a>
<a id='n3961' href='#n3961'>3961</a>
<a id='n3962' href='#n3962'>3962</a>
<a id='n3963' href='#n3963'>3963</a>
<a id='n3964' href='#n3964'>3964</a>
<a id='n3965' href='#n3965'>3965</a>
<a id='n3966' href='#n3966'>3966</a>
<a id='n3967' href='#n3967'>3967</a>
<a id='n3968' href='#n3968'>3968</a>
<a id='n3969' href='#n3969'>3969</a>
<a id='n3970' href='#n3970'>3970</a>
<a id='n3971' href='#n3971'>3971</a>
<a id='n3972' href='#n3972'>3972</a>
<a id='n3973' href='#n3973'>3973</a>
<a id='n3974' href='#n3974'>3974</a>
<a id='n3975' href='#n3975'>3975</a>
<a id='n3976' href='#n3976'>3976</a>
<a id='n3977' href='#n3977'>3977</a>
<a id='n3978' href='#n3978'>3978</a>
<a id='n3979' href='#n3979'>3979</a>
<a id='n3980' href='#n3980'>3980</a>
<a id='n3981' href='#n3981'>3981</a>
<a id='n3982' href='#n3982'>3982</a>
<a id='n3983' href='#n3983'>3983</a>
<a id='n3984' href='#n3984'>3984</a>
<a id='n3985' href='#n3985'>3985</a>
<a id='n3986' href='#n3986'>3986</a>
<a id='n3987' href='#n3987'>3987</a>
<a id='n3988' href='#n3988'>3988</a>
<a id='n3989' href='#n3989'>3989</a>
<a id='n3990' href='#n3990'>3990</a>
<a id='n3991' href='#n3991'>3991</a>
<a id='n3992' href='#n3992'>3992</a>
<a id='n3993' href='#n3993'>3993</a>
<a id='n3994' href='#n3994'>3994</a>
<a id='n3995' href='#n3995'>3995</a>
<a id='n3996' href='#n3996'>3996</a>
<a id='n3997' href='#n3997'>3997</a>
<a id='n3998' href='#n3998'>3998</a>
<a id='n3999' href='#n3999'>3999</a>
<a id='n4000' href='#n4000'>4000</a>
<a id='n4001' href='#n4001'>4001</a>
<a id='n4002' href='#n4002'>4002</a>
<a id='n4003' href='#n4003'>4003</a>
<a id='n4004' href='#n4004'>4004</a>
<a id='n4005' href='#n4005'>4005</a>
<a id='n4006' href='#n4006'>4006</a>
<a id='n4007' href='#n4007'>4007</a>
<a id='n4008' href='#n4008'>4008</a>
<a id='n4009' href='#n4009'>4009</a>
<a id='n4010' href='#n4010'>4010</a>
<a id='n4011' href='#n4011'>4011</a>
<a id='n4012' href='#n4012'>4012</a>
<a id='n4013' href='#n4013'>4013</a>
<a id='n4014' href='#n4014'>4014</a>
<a id='n4015' href='#n4015'>4015</a>
<a id='n4016' href='#n4016'>4016</a>
<a id='n4017' href='#n4017'>4017</a>
<a id='n4018' href='#n4018'>4018</a>
<a id='n4019' href='#n4019'>4019</a>
<a id='n4020' href='#n4020'>4020</a>
<a id='n4021' href='#n4021'>4021</a>
<a id='n4022' href='#n4022'>4022</a>
<a id='n4023' href='#n4023'>4023</a>
<a id='n4024' href='#n4024'>4024</a>
<a id='n4025' href='#n4025'>4025</a>
<a id='n4026' href='#n4026'>4026</a>
<a id='n4027' href='#n4027'>4027</a>
<a id='n4028' href='#n4028'>4028</a>
<a id='n4029' href='#n4029'>4029</a>
<a id='n4030' href='#n4030'>4030</a>
<a id='n4031' href='#n4031'>4031</a>
<a id='n4032' href='#n4032'>4032</a>
<a id='n4033' href='#n4033'>4033</a>
<a id='n4034' href='#n4034'>4034</a>
<a id='n4035' href='#n4035'>4035</a>
<a id='n4036' href='#n4036'>4036</a>
<a id='n4037' href='#n4037'>4037</a>
<a id='n4038' href='#n4038'>4038</a>
<a id='n4039' href='#n4039'>4039</a>
<a id='n4040' href='#n4040'>4040</a>
<a id='n4041' href='#n4041'>4041</a>
<a id='n4042' href='#n4042'>4042</a>
<a id='n4043' href='#n4043'>4043</a>
<a id='n4044' href='#n4044'>4044</a>
<a id='n4045' href='#n4045'>4045</a>
<a id='n4046' href='#n4046'>4046</a>
<a id='n4047' href='#n4047'>4047</a>
<a id='n4048' href='#n4048'>4048</a>
<a id='n4049' href='#n4049'>4049</a>
<a id='n4050' href='#n4050'>4050</a>
<a id='n4051' href='#n4051'>4051</a>
<a id='n4052' href='#n4052'>4052</a>
<a id='n4053' href='#n4053'>4053</a>
<a id='n4054' href='#n4054'>4054</a>
<a id='n4055' href='#n4055'>4055</a>
<a id='n4056' href='#n4056'>4056</a>
<a id='n4057' href='#n4057'>4057</a>
<a id='n4058' href='#n4058'>4058</a>
<a id='n4059' href='#n4059'>4059</a>
<a id='n4060' href='#n4060'>4060</a>
<a id='n4061' href='#n4061'>4061</a>
<a id='n4062' href='#n4062'>4062</a>
<a id='n4063' href='#n4063'>4063</a>
<a id='n4064' href='#n4064'>4064</a>
<a id='n4065' href='#n4065'>4065</a>
<a id='n4066' href='#n4066'>4066</a>
<a id='n4067' href='#n4067'>4067</a>
<a id='n4068' href='#n4068'>4068</a>
<a id='n4069' href='#n4069'>4069</a>
<a id='n4070' href='#n4070'>4070</a>
<a id='n4071' href='#n4071'>4071</a>
<a id='n4072' href='#n4072'>4072</a>
<a id='n4073' href='#n4073'>4073</a>
<a id='n4074' href='#n4074'>4074</a>
<a id='n4075' href='#n4075'>4075</a>
<a id='n4076' href='#n4076'>4076</a>
<a id='n4077' href='#n4077'>4077</a>
<a id='n4078' href='#n4078'>4078</a>
<a id='n4079' href='#n4079'>4079</a>
<a id='n4080' href='#n4080'>4080</a>
<a id='n4081' href='#n4081'>4081</a>
<a id='n4082' href='#n4082'>4082</a>
<a id='n4083' href='#n4083'>4083</a>
<a id='n4084' href='#n4084'>4084</a>
<a id='n4085' href='#n4085'>4085</a>
<a id='n4086' href='#n4086'>4086</a>
<a id='n4087' href='#n4087'>4087</a>
<a id='n4088' href='#n4088'>4088</a>
<a id='n4089' href='#n4089'>4089</a>
<a id='n4090' href='#n4090'>4090</a>
<a id='n4091' href='#n4091'>4091</a>
<a id='n4092' href='#n4092'>4092</a>
<a id='n4093' href='#n4093'>4093</a>
<a id='n4094' href='#n4094'>4094</a>
<a id='n4095' href='#n4095'>4095</a>
<a id='n4096' href='#n4096'>4096</a>
<a id='n4097' href='#n4097'>4097</a>
<a id='n4098' href='#n4098'>4098</a>
<a id='n4099' href='#n4099'>4099</a>
<a id='n4100' href='#n4100'>4100</a>
<a id='n4101' href='#n4101'>4101</a>
<a id='n4102' href='#n4102'>4102</a>
<a id='n4103' href='#n4103'>4103</a>
<a id='n4104' href='#n4104'>4104</a>
<a id='n4105' href='#n4105'>4105</a>
<a id='n4106' href='#n4106'>4106</a>
<a id='n4107' href='#n4107'>4107</a>
<a id='n4108' href='#n4108'>4108</a>
<a id='n4109' href='#n4109'>4109</a>
<a id='n4110' href='#n4110'>4110</a>
<a id='n4111' href='#n4111'>4111</a>
<a id='n4112' href='#n4112'>4112</a>
<a id='n4113' href='#n4113'>4113</a>
<a id='n4114' href='#n4114'>4114</a>
<a id='n4115' href='#n4115'>4115</a>
<a id='n4116' href='#n4116'>4116</a>
<a id='n4117' href='#n4117'>4117</a>
<a id='n4118' href='#n4118'>4118</a>
<a id='n4119' href='#n4119'>4119</a>
<a id='n4120' href='#n4120'>4120</a>
<a id='n4121' href='#n4121'>4121</a>
<a id='n4122' href='#n4122'>4122</a>
<a id='n4123' href='#n4123'>4123</a>
<a id='n4124' href='#n4124'>4124</a>
<a id='n4125' href='#n4125'>4125</a>
<a id='n4126' href='#n4126'>4126</a>
<a id='n4127' href='#n4127'>4127</a>
<a id='n4128' href='#n4128'>4128</a>
<a id='n4129' href='#n4129'>4129</a>
<a id='n4130' href='#n4130'>4130</a>
<a id='n4131' href='#n4131'>4131</a>
<a id='n4132' href='#n4132'>4132</a>
<a id='n4133' href='#n4133'>4133</a>
<a id='n4134' href='#n4134'>4134</a>
<a id='n4135' href='#n4135'>4135</a>
<a id='n4136' href='#n4136'>4136</a>
<a id='n4137' href='#n4137'>4137</a>
<a id='n4138' href='#n4138'>4138</a>
<a id='n4139' href='#n4139'>4139</a>
<a id='n4140' href='#n4140'>4140</a>
<a id='n4141' href='#n4141'>4141</a>
<a id='n4142' href='#n4142'>4142</a>
<a id='n4143' href='#n4143'>4143</a>
<a id='n4144' href='#n4144'>4144</a>
<a id='n4145' href='#n4145'>4145</a>
<a id='n4146' href='#n4146'>4146</a>
<a id='n4147' href='#n4147'>4147</a>
<a id='n4148' href='#n4148'>4148</a>
<a id='n4149' href='#n4149'>4149</a>
<a id='n4150' href='#n4150'>4150</a>
<a id='n4151' href='#n4151'>4151</a>
<a id='n4152' href='#n4152'>4152</a>
<a id='n4153' href='#n4153'>4153</a>
<a id='n4154' href='#n4154'>4154</a>
<a id='n4155' href='#n4155'>4155</a>
<a id='n4156' href='#n4156'>4156</a>
<a id='n4157' href='#n4157'>4157</a>
<a id='n4158' href='#n4158'>4158</a>
<a id='n4159' href='#n4159'>4159</a>
<a id='n4160' href='#n4160'>4160</a>
<a id='n4161' href='#n4161'>4161</a>
<a id='n4162' href='#n4162'>4162</a>
<a id='n4163' href='#n4163'>4163</a>
<a id='n4164' href='#n4164'>4164</a>
<a id='n4165' href='#n4165'>4165</a>
<a id='n4166' href='#n4166'>4166</a>
<a id='n4167' href='#n4167'>4167</a>
<a id='n4168' href='#n4168'>4168</a>
<a id='n4169' href='#n4169'>4169</a>
<a id='n4170' href='#n4170'>4170</a>
<a id='n4171' href='#n4171'>4171</a>
<a id='n4172' href='#n4172'>4172</a>
<a id='n4173' href='#n4173'>4173</a>
<a id='n4174' href='#n4174'>4174</a>
<a id='n4175' href='#n4175'>4175</a>
<a id='n4176' href='#n4176'>4176</a>
<a id='n4177' href='#n4177'>4177</a>
<a id='n4178' href='#n4178'>4178</a>
<a id='n4179' href='#n4179'>4179</a>
<a id='n4180' href='#n4180'>4180</a>
<a id='n4181' href='#n4181'>4181</a>
<a id='n4182' href='#n4182'>4182</a>
<a id='n4183' href='#n4183'>4183</a>
<a id='n4184' href='#n4184'>4184</a>
<a id='n4185' href='#n4185'>4185</a>
<a id='n4186' href='#n4186'>4186</a>
<a id='n4187' href='#n4187'>4187</a>
<a id='n4188' href='#n4188'>4188</a>
<a id='n4189' href='#n4189'>4189</a>
<a id='n4190' href='#n4190'>4190</a>
<a id='n4191' href='#n4191'>4191</a>
<a id='n4192' href='#n4192'>4192</a>
<a id='n4193' href='#n4193'>4193</a>
<a id='n4194' href='#n4194'>4194</a>
<a id='n4195' href='#n4195'>4195</a>
<a id='n4196' href='#n4196'>4196</a>
<a id='n4197' href='#n4197'>4197</a>
<a id='n4198' href='#n4198'>4198</a>
<a id='n4199' href='#n4199'>4199</a>
<a id='n4200' href='#n4200'>4200</a>
<a id='n4201' href='#n4201'>4201</a>
<a id='n4202' href='#n4202'>4202</a>
<a id='n4203' href='#n4203'>4203</a>
<a id='n4204' href='#n4204'>4204</a>
<a id='n4205' href='#n4205'>4205</a>
<a id='n4206' href='#n4206'>4206</a>
<a id='n4207' href='#n4207'>4207</a>
<a id='n4208' href='#n4208'>4208</a>
<a id='n4209' href='#n4209'>4209</a>
<a id='n4210' href='#n4210'>4210</a>
<a id='n4211' href='#n4211'>4211</a>
<a id='n4212' href='#n4212'>4212</a>
<a id='n4213' href='#n4213'>4213</a>
<a id='n4214' href='#n4214'>4214</a>
<a id='n4215' href='#n4215'>4215</a>
<a id='n4216' href='#n4216'>4216</a>
<a id='n4217' href='#n4217'>4217</a>
<a id='n4218' href='#n4218'>4218</a>
<a id='n4219' href='#n4219'>4219</a>
<a id='n4220' href='#n4220'>4220</a>
<a id='n4221' href='#n4221'>4221</a>
<a id='n4222' href='#n4222'>4222</a>
<a id='n4223' href='#n4223'>4223</a>
<a id='n4224' href='#n4224'>4224</a>
<a id='n4225' href='#n4225'>4225</a>
<a id='n4226' href='#n4226'>4226</a>
<a id='n4227' href='#n4227'>4227</a>
<a id='n4228' href='#n4228'>4228</a>
<a id='n4229' href='#n4229'>4229</a>
<a id='n4230' href='#n4230'>4230</a>
<a id='n4231' href='#n4231'>4231</a>
<a id='n4232' href='#n4232'>4232</a>
<a id='n4233' href='#n4233'>4233</a>
<a id='n4234' href='#n4234'>4234</a>
<a id='n4235' href='#n4235'>4235</a>
<a id='n4236' href='#n4236'>4236</a>
<a id='n4237' href='#n4237'>4237</a>
<a id='n4238' href='#n4238'>4238</a>
<a id='n4239' href='#n4239'>4239</a>
<a id='n4240' href='#n4240'>4240</a>
<a id='n4241' href='#n4241'>4241</a>
<a id='n4242' href='#n4242'>4242</a>
<a id='n4243' href='#n4243'>4243</a>
<a id='n4244' href='#n4244'>4244</a>
<a id='n4245' href='#n4245'>4245</a>
<a id='n4246' href='#n4246'>4246</a>
<a id='n4247' href='#n4247'>4247</a>
<a id='n4248' href='#n4248'>4248</a>
<a id='n4249' href='#n4249'>4249</a>
<a id='n4250' href='#n4250'>4250</a>
<a id='n4251' href='#n4251'>4251</a>
<a id='n4252' href='#n4252'>4252</a>
<a id='n4253' href='#n4253'>4253</a>
<a id='n4254' href='#n4254'>4254</a>
<a id='n4255' href='#n4255'>4255</a>
<a id='n4256' href='#n4256'>4256</a>
<a id='n4257' href='#n4257'>4257</a>
<a id='n4258' href='#n4258'>4258</a>
<a id='n4259' href='#n4259'>4259</a>
<a id='n4260' href='#n4260'>4260</a>
<a id='n4261' href='#n4261'>4261</a>
<a id='n4262' href='#n4262'>4262</a>
<a id='n4263' href='#n4263'>4263</a>
<a id='n4264' href='#n4264'>4264</a>
<a id='n4265' href='#n4265'>4265</a>
<a id='n4266' href='#n4266'>4266</a>
<a id='n4267' href='#n4267'>4267</a>
<a id='n4268' href='#n4268'>4268</a>
<a id='n4269' href='#n4269'>4269</a>
<a id='n4270' href='#n4270'>4270</a>
<a id='n4271' href='#n4271'>4271</a>
<a id='n4272' href='#n4272'>4272</a>
<a id='n4273' href='#n4273'>4273</a>
<a id='n4274' href='#n4274'>4274</a>
<a id='n4275' href='#n4275'>4275</a>
<a id='n4276' href='#n4276'>4276</a>
<a id='n4277' href='#n4277'>4277</a>
<a id='n4278' href='#n4278'>4278</a>
<a id='n4279' href='#n4279'>4279</a>
<a id='n4280' href='#n4280'>4280</a>
<a id='n4281' href='#n4281'>4281</a>
<a id='n4282' href='#n4282'>4282</a>
<a id='n4283' href='#n4283'>4283</a>
<a id='n4284' href='#n4284'>4284</a>
<a id='n4285' href='#n4285'>4285</a>
<a id='n4286' href='#n4286'>4286</a>
<a id='n4287' href='#n4287'>4287</a>
<a id='n4288' href='#n4288'>4288</a>
<a id='n4289' href='#n4289'>4289</a>
<a id='n4290' href='#n4290'>4290</a>
<a id='n4291' href='#n4291'>4291</a>
<a id='n4292' href='#n4292'>4292</a>
<a id='n4293' href='#n4293'>4293</a>
<a id='n4294' href='#n4294'>4294</a>
<a id='n4295' href='#n4295'>4295</a>
<a id='n4296' href='#n4296'>4296</a>
<a id='n4297' href='#n4297'>4297</a>
<a id='n4298' href='#n4298'>4298</a>
<a id='n4299' href='#n4299'>4299</a>
<a id='n4300' href='#n4300'>4300</a>
<a id='n4301' href='#n4301'>4301</a>
<a id='n4302' href='#n4302'>4302</a>
<a id='n4303' href='#n4303'>4303</a>
<a id='n4304' href='#n4304'>4304</a>
<a id='n4305' href='#n4305'>4305</a>
<a id='n4306' href='#n4306'>4306</a>
<a id='n4307' href='#n4307'>4307</a>
<a id='n4308' href='#n4308'>4308</a>
<a id='n4309' href='#n4309'>4309</a>
<a id='n4310' href='#n4310'>4310</a>
<a id='n4311' href='#n4311'>4311</a>
<a id='n4312' href='#n4312'>4312</a>
<a id='n4313' href='#n4313'>4313</a>
<a id='n4314' href='#n4314'>4314</a>
<a id='n4315' href='#n4315'>4315</a>
<a id='n4316' href='#n4316'>4316</a>
<a id='n4317' href='#n4317'>4317</a>
<a id='n4318' href='#n4318'>4318</a>
<a id='n4319' href='#n4319'>4319</a>
<a id='n4320' href='#n4320'>4320</a>
<a id='n4321' href='#n4321'>4321</a>
<a id='n4322' href='#n4322'>4322</a>
<a id='n4323' href='#n4323'>4323</a>
<a id='n4324' href='#n4324'>4324</a>
<a id='n4325' href='#n4325'>4325</a>
<a id='n4326' href='#n4326'>4326</a>
<a id='n4327' href='#n4327'>4327</a>
<a id='n4328' href='#n4328'>4328</a>
<a id='n4329' href='#n4329'>4329</a>
<a id='n4330' href='#n4330'>4330</a>
<a id='n4331' href='#n4331'>4331</a>
<a id='n4332' href='#n4332'>4332</a>
<a id='n4333' href='#n4333'>4333</a>
<a id='n4334' href='#n4334'>4334</a>
<a id='n4335' href='#n4335'>4335</a>
<a id='n4336' href='#n4336'>4336</a>
<a id='n4337' href='#n4337'>4337</a>
<a id='n4338' href='#n4338'>4338</a>
<a id='n4339' href='#n4339'>4339</a>
<a id='n4340' href='#n4340'>4340</a>
<a id='n4341' href='#n4341'>4341</a>
<a id='n4342' href='#n4342'>4342</a>
<a id='n4343' href='#n4343'>4343</a>
<a id='n4344' href='#n4344'>4344</a>
<a id='n4345' href='#n4345'>4345</a>
<a id='n4346' href='#n4346'>4346</a>
<a id='n4347' href='#n4347'>4347</a>
<a id='n4348' href='#n4348'>4348</a>
<a id='n4349' href='#n4349'>4349</a>
<a id='n4350' href='#n4350'>4350</a>
<a id='n4351' href='#n4351'>4351</a>
<a id='n4352' href='#n4352'>4352</a>
<a id='n4353' href='#n4353'>4353</a>
<a id='n4354' href='#n4354'>4354</a>
<a id='n4355' href='#n4355'>4355</a>
<a id='n4356' href='#n4356'>4356</a>
<a id='n4357' href='#n4357'>4357</a>
<a id='n4358' href='#n4358'>4358</a>
<a id='n4359' href='#n4359'>4359</a>
<a id='n4360' href='#n4360'>4360</a>
<a id='n4361' href='#n4361'>4361</a>
<a id='n4362' href='#n4362'>4362</a>
<a id='n4363' href='#n4363'>4363</a>
<a id='n4364' href='#n4364'>4364</a>
<a id='n4365' href='#n4365'>4365</a>
<a id='n4366' href='#n4366'>4366</a>
<a id='n4367' href='#n4367'>4367</a>
<a id='n4368' href='#n4368'>4368</a>
<a id='n4369' href='#n4369'>4369</a>
<a id='n4370' href='#n4370'>4370</a>
<a id='n4371' href='#n4371'>4371</a>
<a id='n4372' href='#n4372'>4372</a>
<a id='n4373' href='#n4373'>4373</a>
<a id='n4374' href='#n4374'>4374</a>
<a id='n4375' href='#n4375'>4375</a>
<a id='n4376' href='#n4376'>4376</a>
<a id='n4377' href='#n4377'>4377</a>
<a id='n4378' href='#n4378'>4378</a>
<a id='n4379' href='#n4379'>4379</a>
<a id='n4380' href='#n4380'>4380</a>
<a id='n4381' href='#n4381'>4381</a>
<a id='n4382' href='#n4382'>4382</a>
<a id='n4383' href='#n4383'>4383</a>
<a id='n4384' href='#n4384'>4384</a>
<a id='n4385' href='#n4385'>4385</a>
<a id='n4386' href='#n4386'>4386</a>
<a id='n4387' href='#n4387'>4387</a>
<a id='n4388' href='#n4388'>4388</a>
<a id='n4389' href='#n4389'>4389</a>
<a id='n4390' href='#n4390'>4390</a>
<a id='n4391' href='#n4391'>4391</a>
<a id='n4392' href='#n4392'>4392</a>
<a id='n4393' href='#n4393'>4393</a>
<a id='n4394' href='#n4394'>4394</a>
<a id='n4395' href='#n4395'>4395</a>
<a id='n4396' href='#n4396'>4396</a>
<a id='n4397' href='#n4397'>4397</a>
<a id='n4398' href='#n4398'>4398</a>
<a id='n4399' href='#n4399'>4399</a>
<a id='n4400' href='#n4400'>4400</a>
<a id='n4401' href='#n4401'>4401</a>
<a id='n4402' href='#n4402'>4402</a>
<a id='n4403' href='#n4403'>4403</a>
<a id='n4404' href='#n4404'>4404</a>
<a id='n4405' href='#n4405'>4405</a>
<a id='n4406' href='#n4406'>4406</a>
<a id='n4407' href='#n4407'>4407</a>
<a id='n4408' href='#n4408'>4408</a>
<a id='n4409' href='#n4409'>4409</a>
<a id='n4410' href='#n4410'>4410</a>
<a id='n4411' href='#n4411'>4411</a>
<a id='n4412' href='#n4412'>4412</a>
<a id='n4413' href='#n4413'>4413</a>
<a id='n4414' href='#n4414'>4414</a>
<a id='n4415' href='#n4415'>4415</a>
<a id='n4416' href='#n4416'>4416</a>
<a id='n4417' href='#n4417'>4417</a>
<a id='n4418' href='#n4418'>4418</a>
<a id='n4419' href='#n4419'>4419</a>
<a id='n4420' href='#n4420'>4420</a>
<a id='n4421' href='#n4421'>4421</a>
<a id='n4422' href='#n4422'>4422</a>
<a id='n4423' href='#n4423'>4423</a>
<a id='n4424' href='#n4424'>4424</a>
<a id='n4425' href='#n4425'>4425</a>
<a id='n4426' href='#n4426'>4426</a>
<a id='n4427' href='#n4427'>4427</a>
<a id='n4428' href='#n4428'>4428</a>
<a id='n4429' href='#n4429'>4429</a>
<a id='n4430' href='#n4430'>4430</a>
<a id='n4431' href='#n4431'>4431</a>
<a id='n4432' href='#n4432'>4432</a>
<a id='n4433' href='#n4433'>4433</a>
<a id='n4434' href='#n4434'>4434</a>
<a id='n4435' href='#n4435'>4435</a>
<a id='n4436' href='#n4436'>4436</a>
<a id='n4437' href='#n4437'>4437</a>
<a id='n4438' href='#n4438'>4438</a>
<a id='n4439' href='#n4439'>4439</a>
<a id='n4440' href='#n4440'>4440</a>
<a id='n4441' href='#n4441'>4441</a>
<a id='n4442' href='#n4442'>4442</a>
<a id='n4443' href='#n4443'>4443</a>
<a id='n4444' href='#n4444'>4444</a>
<a id='n4445' href='#n4445'>4445</a>
<a id='n4446' href='#n4446'>4446</a>
<a id='n4447' href='#n4447'>4447</a>
<a id='n4448' href='#n4448'>4448</a>
<a id='n4449' href='#n4449'>4449</a>
<a id='n4450' href='#n4450'>4450</a>
<a id='n4451' href='#n4451'>4451</a>
<a id='n4452' href='#n4452'>4452</a>
<a id='n4453' href='#n4453'>4453</a>
<a id='n4454' href='#n4454'>4454</a>
<a id='n4455' href='#n4455'>4455</a>
<a id='n4456' href='#n4456'>4456</a>
<a id='n4457' href='#n4457'>4457</a>
<a id='n4458' href='#n4458'>4458</a>
<a id='n4459' href='#n4459'>4459</a>
<a id='n4460' href='#n4460'>4460</a>
<a id='n4461' href='#n4461'>4461</a>
<a id='n4462' href='#n4462'>4462</a>
<a id='n4463' href='#n4463'>4463</a>
<a id='n4464' href='#n4464'>4464</a>
<a id='n4465' href='#n4465'>4465</a>
<a id='n4466' href='#n4466'>4466</a>
<a id='n4467' href='#n4467'>4467</a>
<a id='n4468' href='#n4468'>4468</a>
<a id='n4469' href='#n4469'>4469</a>
<a id='n4470' href='#n4470'>4470</a>
<a id='n4471' href='#n4471'>4471</a>
<a id='n4472' href='#n4472'>4472</a>
<a id='n4473' href='#n4473'>4473</a>
<a id='n4474' href='#n4474'>4474</a>
<a id='n4475' href='#n4475'>4475</a>
<a id='n4476' href='#n4476'>4476</a>
<a id='n4477' href='#n4477'>4477</a>
<a id='n4478' href='#n4478'>4478</a>
<a id='n4479' href='#n4479'>4479</a>
<a id='n4480' href='#n4480'>4480</a>
<a id='n4481' href='#n4481'>4481</a>
<a id='n4482' href='#n4482'>4482</a>
<a id='n4483' href='#n4483'>4483</a>
<a id='n4484' href='#n4484'>4484</a>
<a id='n4485' href='#n4485'>4485</a>
<a id='n4486' href='#n4486'>4486</a>
<a id='n4487' href='#n4487'>4487</a>
<a id='n4488' href='#n4488'>4488</a>
<a id='n4489' href='#n4489'>4489</a>
<a id='n4490' href='#n4490'>4490</a>
<a id='n4491' href='#n4491'>4491</a>
<a id='n4492' href='#n4492'>4492</a>
<a id='n4493' href='#n4493'>4493</a>
<a id='n4494' href='#n4494'>4494</a>
<a id='n4495' href='#n4495'>4495</a>
<a id='n4496' href='#n4496'>4496</a>
<a id='n4497' href='#n4497'>4497</a>
<a id='n4498' href='#n4498'>4498</a>
<a id='n4499' href='#n4499'>4499</a>
<a id='n4500' href='#n4500'>4500</a>
<a id='n4501' href='#n4501'>4501</a>
<a id='n4502' href='#n4502'>4502</a>
<a id='n4503' href='#n4503'>4503</a>
<a id='n4504' href='#n4504'>4504</a>
<a id='n4505' href='#n4505'>4505</a>
<a id='n4506' href='#n4506'>4506</a>
<a id='n4507' href='#n4507'>4507</a>
<a id='n4508' href='#n4508'>4508</a>
<a id='n4509' href='#n4509'>4509</a>
<a id='n4510' href='#n4510'>4510</a>
<a id='n4511' href='#n4511'>4511</a>
<a id='n4512' href='#n4512'>4512</a>
<a id='n4513' href='#n4513'>4513</a>
<a id='n4514' href='#n4514'>4514</a>
<a id='n4515' href='#n4515'>4515</a>
<a id='n4516' href='#n4516'>4516</a>
<a id='n4517' href='#n4517'>4517</a>
<a id='n4518' href='#n4518'>4518</a>
<a id='n4519' href='#n4519'>4519</a>
<a id='n4520' href='#n4520'>4520</a>
<a id='n4521' href='#n4521'>4521</a>
<a id='n4522' href='#n4522'>4522</a>
<a id='n4523' href='#n4523'>4523</a>
<a id='n4524' href='#n4524'>4524</a>
<a id='n4525' href='#n4525'>4525</a>
<a id='n4526' href='#n4526'>4526</a>
<a id='n4527' href='#n4527'>4527</a>
<a id='n4528' href='#n4528'>4528</a>
<a id='n4529' href='#n4529'>4529</a>
<a id='n4530' href='#n4530'>4530</a>
<a id='n4531' href='#n4531'>4531</a>
<a id='n4532' href='#n4532'>4532</a>
<a id='n4533' href='#n4533'>4533</a>
<a id='n4534' href='#n4534'>4534</a>
<a id='n4535' href='#n4535'>4535</a>
<a id='n4536' href='#n4536'>4536</a>
<a id='n4537' href='#n4537'>4537</a>
<a id='n4538' href='#n4538'>4538</a>
<a id='n4539' href='#n4539'>4539</a>
<a id='n4540' href='#n4540'>4540</a>
<a id='n4541' href='#n4541'>4541</a>
<a id='n4542' href='#n4542'>4542</a>
<a id='n4543' href='#n4543'>4543</a>
<a id='n4544' href='#n4544'>4544</a>
<a id='n4545' href='#n4545'>4545</a>
<a id='n4546' href='#n4546'>4546</a>
<a id='n4547' href='#n4547'>4547</a>
<a id='n4548' href='#n4548'>4548</a>
<a id='n4549' href='#n4549'>4549</a>
<a id='n4550' href='#n4550'>4550</a>
<a id='n4551' href='#n4551'>4551</a>
<a id='n4552' href='#n4552'>4552</a>
<a id='n4553' href='#n4553'>4553</a>
<a id='n4554' href='#n4554'>4554</a>
<a id='n4555' href='#n4555'>4555</a>
<a id='n4556' href='#n4556'>4556</a>
<a id='n4557' href='#n4557'>4557</a>
<a id='n4558' href='#n4558'>4558</a>
<a id='n4559' href='#n4559'>4559</a>
<a id='n4560' href='#n4560'>4560</a>
<a id='n4561' href='#n4561'>4561</a>
<a id='n4562' href='#n4562'>4562</a>
<a id='n4563' href='#n4563'>4563</a>
<a id='n4564' href='#n4564'>4564</a>
<a id='n4565' href='#n4565'>4565</a>
<a id='n4566' href='#n4566'>4566</a>
<a id='n4567' href='#n4567'>4567</a>
<a id='n4568' href='#n4568'>4568</a>
<a id='n4569' href='#n4569'>4569</a>
<a id='n4570' href='#n4570'>4570</a>
<a id='n4571' href='#n4571'>4571</a>
<a id='n4572' href='#n4572'>4572</a>
<a id='n4573' href='#n4573'>4573</a>
<a id='n4574' href='#n4574'>4574</a>
<a id='n4575' href='#n4575'>4575</a>
<a id='n4576' href='#n4576'>4576</a>
<a id='n4577' href='#n4577'>4577</a>
<a id='n4578' href='#n4578'>4578</a>
<a id='n4579' href='#n4579'>4579</a>
<a id='n4580' href='#n4580'>4580</a>
<a id='n4581' href='#n4581'>4581</a>
<a id='n4582' href='#n4582'>4582</a>
<a id='n4583' href='#n4583'>4583</a>
<a id='n4584' href='#n4584'>4584</a>
<a id='n4585' href='#n4585'>4585</a>
<a id='n4586' href='#n4586'>4586</a>
<a id='n4587' href='#n4587'>4587</a>
<a id='n4588' href='#n4588'>4588</a>
<a id='n4589' href='#n4589'>4589</a>
<a id='n4590' href='#n4590'>4590</a>
<a id='n4591' href='#n4591'>4591</a>
<a id='n4592' href='#n4592'>4592</a>
<a id='n4593' href='#n4593'>4593</a>
<a id='n4594' href='#n4594'>4594</a>
<a id='n4595' href='#n4595'>4595</a>
<a id='n4596' href='#n4596'>4596</a>
<a id='n4597' href='#n4597'>4597</a>
<a id='n4598' href='#n4598'>4598</a>
<a id='n4599' href='#n4599'>4599</a>
<a id='n4600' href='#n4600'>4600</a>
<a id='n4601' href='#n4601'>4601</a>
<a id='n4602' href='#n4602'>4602</a>
<a id='n4603' href='#n4603'>4603</a>
<a id='n4604' href='#n4604'>4604</a>
<a id='n4605' href='#n4605'>4605</a>
<a id='n4606' href='#n4606'>4606</a>
<a id='n4607' href='#n4607'>4607</a>
<a id='n4608' href='#n4608'>4608</a>
<a id='n4609' href='#n4609'>4609</a>
<a id='n4610' href='#n4610'>4610</a>
<a id='n4611' href='#n4611'>4611</a>
<a id='n4612' href='#n4612'>4612</a>
<a id='n4613' href='#n4613'>4613</a>
<a id='n4614' href='#n4614'>4614</a>
<a id='n4615' href='#n4615'>4615</a>
<a id='n4616' href='#n4616'>4616</a>
<a id='n4617' href='#n4617'>4617</a>
<a id='n4618' href='#n4618'>4618</a>
<a id='n4619' href='#n4619'>4619</a>
<a id='n4620' href='#n4620'>4620</a>
<a id='n4621' href='#n4621'>4621</a>
<a id='n4622' href='#n4622'>4622</a>
<a id='n4623' href='#n4623'>4623</a>
<a id='n4624' href='#n4624'>4624</a>
<a id='n4625' href='#n4625'>4625</a>
<a id='n4626' href='#n4626'>4626</a>
<a id='n4627' href='#n4627'>4627</a>
<a id='n4628' href='#n4628'>4628</a>
<a id='n4629' href='#n4629'>4629</a>
<a id='n4630' href='#n4630'>4630</a>
<a id='n4631' href='#n4631'>4631</a>
<a id='n4632' href='#n4632'>4632</a>
<a id='n4633' href='#n4633'>4633</a>
<a id='n4634' href='#n4634'>4634</a>
<a id='n4635' href='#n4635'>4635</a>
<a id='n4636' href='#n4636'>4636</a>
<a id='n4637' href='#n4637'>4637</a>
<a id='n4638' href='#n4638'>4638</a>
<a id='n4639' href='#n4639'>4639</a>
<a id='n4640' href='#n4640'>4640</a>
<a id='n4641' href='#n4641'>4641</a>
<a id='n4642' href='#n4642'>4642</a>
<a id='n4643' href='#n4643'>4643</a>
<a id='n4644' href='#n4644'>4644</a>
<a id='n4645' href='#n4645'>4645</a>
<a id='n4646' href='#n4646'>4646</a>
<a id='n4647' href='#n4647'>4647</a>
<a id='n4648' href='#n4648'>4648</a>
<a id='n4649' href='#n4649'>4649</a>
<a id='n4650' href='#n4650'>4650</a>
<a id='n4651' href='#n4651'>4651</a>
<a id='n4652' href='#n4652'>4652</a>
<a id='n4653' href='#n4653'>4653</a>
<a id='n4654' href='#n4654'>4654</a>
<a id='n4655' href='#n4655'>4655</a>
<a id='n4656' href='#n4656'>4656</a>
<a id='n4657' href='#n4657'>4657</a>
<a id='n4658' href='#n4658'>4658</a>
<a id='n4659' href='#n4659'>4659</a>
<a id='n4660' href='#n4660'>4660</a>
<a id='n4661' href='#n4661'>4661</a>
<a id='n4662' href='#n4662'>4662</a>
<a id='n4663' href='#n4663'>4663</a>
<a id='n4664' href='#n4664'>4664</a>
<a id='n4665' href='#n4665'>4665</a>
<a id='n4666' href='#n4666'>4666</a>
<a id='n4667' href='#n4667'>4667</a>
<a id='n4668' href='#n4668'>4668</a>
<a id='n4669' href='#n4669'>4669</a>
<a id='n4670' href='#n4670'>4670</a>
<a id='n4671' href='#n4671'>4671</a>
<a id='n4672' href='#n4672'>4672</a>
<a id='n4673' href='#n4673'>4673</a>
<a id='n4674' href='#n4674'>4674</a>
<a id='n4675' href='#n4675'>4675</a>
<a id='n4676' href='#n4676'>4676</a>
<a id='n4677' href='#n4677'>4677</a>
<a id='n4678' href='#n4678'>4678</a>
<a id='n4679' href='#n4679'>4679</a>
<a id='n4680' href='#n4680'>4680</a>
<a id='n4681' href='#n4681'>4681</a>
<a id='n4682' href='#n4682'>4682</a>
<a id='n4683' href='#n4683'>4683</a>
<a id='n4684' href='#n4684'>4684</a>
<a id='n4685' href='#n4685'>4685</a>
<a id='n4686' href='#n4686'>4686</a>
<a id='n4687' href='#n4687'>4687</a>
<a id='n4688' href='#n4688'>4688</a>
<a id='n4689' href='#n4689'>4689</a>
<a id='n4690' href='#n4690'>4690</a>
<a id='n4691' href='#n4691'>4691</a>
<a id='n4692' href='#n4692'>4692</a>
<a id='n4693' href='#n4693'>4693</a>
<a id='n4694' href='#n4694'>4694</a>
<a id='n4695' href='#n4695'>4695</a>
<a id='n4696' href='#n4696'>4696</a>
<a id='n4697' href='#n4697'>4697</a>
<a id='n4698' href='#n4698'>4698</a>
<a id='n4699' href='#n4699'>4699</a>
<a id='n4700' href='#n4700'>4700</a>
<a id='n4701' href='#n4701'>4701</a>
<a id='n4702' href='#n4702'>4702</a>
<a id='n4703' href='#n4703'>4703</a>
<a id='n4704' href='#n4704'>4704</a>
<a id='n4705' href='#n4705'>4705</a>
<a id='n4706' href='#n4706'>4706</a>
<a id='n4707' href='#n4707'>4707</a>
<a id='n4708' href='#n4708'>4708</a>
<a id='n4709' href='#n4709'>4709</a>
<a id='n4710' href='#n4710'>4710</a>
<a id='n4711' href='#n4711'>4711</a>
<a id='n4712' href='#n4712'>4712</a>
<a id='n4713' href='#n4713'>4713</a>
<a id='n4714' href='#n4714'>4714</a>
<a id='n4715' href='#n4715'>4715</a>
<a id='n4716' href='#n4716'>4716</a>
<a id='n4717' href='#n4717'>4717</a>
<a id='n4718' href='#n4718'>4718</a>
<a id='n4719' href='#n4719'>4719</a>
<a id='n4720' href='#n4720'>4720</a>
<a id='n4721' href='#n4721'>4721</a>
<a id='n4722' href='#n4722'>4722</a>
<a id='n4723' href='#n4723'>4723</a>
<a id='n4724' href='#n4724'>4724</a>
<a id='n4725' href='#n4725'>4725</a>
<a id='n4726' href='#n4726'>4726</a>
<a id='n4727' href='#n4727'>4727</a>
<a id='n4728' href='#n4728'>4728</a>
<a id='n4729' href='#n4729'>4729</a>
<a id='n4730' href='#n4730'>4730</a>
<a id='n4731' href='#n4731'>4731</a>
<a id='n4732' href='#n4732'>4732</a>
<a id='n4733' href='#n4733'>4733</a>
<a id='n4734' href='#n4734'>4734</a>
<a id='n4735' href='#n4735'>4735</a>
<a id='n4736' href='#n4736'>4736</a>
<a id='n4737' href='#n4737'>4737</a>
<a id='n4738' href='#n4738'>4738</a>
<a id='n4739' href='#n4739'>4739</a>
<a id='n4740' href='#n4740'>4740</a>
<a id='n4741' href='#n4741'>4741</a>
<a id='n4742' href='#n4742'>4742</a>
<a id='n4743' href='#n4743'>4743</a>
<a id='n4744' href='#n4744'>4744</a>
<a id='n4745' href='#n4745'>4745</a>
<a id='n4746' href='#n4746'>4746</a>
<a id='n4747' href='#n4747'>4747</a>
<a id='n4748' href='#n4748'>4748</a>
<a id='n4749' href='#n4749'>4749</a>
<a id='n4750' href='#n4750'>4750</a>
<a id='n4751' href='#n4751'>4751</a>
<a id='n4752' href='#n4752'>4752</a>
<a id='n4753' href='#n4753'>4753</a>
<a id='n4754' href='#n4754'>4754</a>
<a id='n4755' href='#n4755'>4755</a>
<a id='n4756' href='#n4756'>4756</a>
<a id='n4757' href='#n4757'>4757</a>
<a id='n4758' href='#n4758'>4758</a>
<a id='n4759' href='#n4759'>4759</a>
<a id='n4760' href='#n4760'>4760</a>
<a id='n4761' href='#n4761'>4761</a>
<a id='n4762' href='#n4762'>4762</a>
<a id='n4763' href='#n4763'>4763</a>
<a id='n4764' href='#n4764'>4764</a>
<a id='n4765' href='#n4765'>4765</a>
<a id='n4766' href='#n4766'>4766</a>
<a id='n4767' href='#n4767'>4767</a>
<a id='n4768' href='#n4768'>4768</a>
<a id='n4769' href='#n4769'>4769</a>
<a id='n4770' href='#n4770'>4770</a>
<a id='n4771' href='#n4771'>4771</a>
<a id='n4772' href='#n4772'>4772</a>
<a id='n4773' href='#n4773'>4773</a>
<a id='n4774' href='#n4774'>4774</a>
<a id='n4775' href='#n4775'>4775</a>
<a id='n4776' href='#n4776'>4776</a>
<a id='n4777' href='#n4777'>4777</a>
<a id='n4778' href='#n4778'>4778</a>
<a id='n4779' href='#n4779'>4779</a>
<a id='n4780' href='#n4780'>4780</a>
<a id='n4781' href='#n4781'>4781</a>
<a id='n4782' href='#n4782'>4782</a>
<a id='n4783' href='#n4783'>4783</a>
<a id='n4784' href='#n4784'>4784</a>
<a id='n4785' href='#n4785'>4785</a>
<a id='n4786' href='#n4786'>4786</a>
<a id='n4787' href='#n4787'>4787</a>
<a id='n4788' href='#n4788'>4788</a>
<a id='n4789' href='#n4789'>4789</a>
<a id='n4790' href='#n4790'>4790</a>
<a id='n4791' href='#n4791'>4791</a>
<a id='n4792' href='#n4792'>4792</a>
<a id='n4793' href='#n4793'>4793</a>
<a id='n4794' href='#n4794'>4794</a>
<a id='n4795' href='#n4795'>4795</a>
<a id='n4796' href='#n4796'>4796</a>
<a id='n4797' href='#n4797'>4797</a>
<a id='n4798' href='#n4798'>4798</a>
<a id='n4799' href='#n4799'>4799</a>
<a id='n4800' href='#n4800'>4800</a>
<a id='n4801' href='#n4801'>4801</a>
<a id='n4802' href='#n4802'>4802</a>
<a id='n4803' href='#n4803'>4803</a>
<a id='n4804' href='#n4804'>4804</a>
<a id='n4805' href='#n4805'>4805</a>
<a id='n4806' href='#n4806'>4806</a>
<a id='n4807' href='#n4807'>4807</a>
<a id='n4808' href='#n4808'>4808</a>
<a id='n4809' href='#n4809'>4809</a>
<a id='n4810' href='#n4810'>4810</a>
<a id='n4811' href='#n4811'>4811</a>
<a id='n4812' href='#n4812'>4812</a>
<a id='n4813' href='#n4813'>4813</a>
<a id='n4814' href='#n4814'>4814</a>
<a id='n4815' href='#n4815'>4815</a>
<a id='n4816' href='#n4816'>4816</a>
<a id='n4817' href='#n4817'>4817</a>
<a id='n4818' href='#n4818'>4818</a>
<a id='n4819' href='#n4819'>4819</a>
<a id='n4820' href='#n4820'>4820</a>
<a id='n4821' href='#n4821'>4821</a>
<a id='n4822' href='#n4822'>4822</a>
<a id='n4823' href='#n4823'>4823</a>
<a id='n4824' href='#n4824'>4824</a>
<a id='n4825' href='#n4825'>4825</a>
<a id='n4826' href='#n4826'>4826</a>
<a id='n4827' href='#n4827'>4827</a>
<a id='n4828' href='#n4828'>4828</a>
<a id='n4829' href='#n4829'>4829</a>
<a id='n4830' href='#n4830'>4830</a>
<a id='n4831' href='#n4831'>4831</a>
<a id='n4832' href='#n4832'>4832</a>
<a id='n4833' href='#n4833'>4833</a>
<a id='n4834' href='#n4834'>4834</a>
<a id='n4835' href='#n4835'>4835</a>
<a id='n4836' href='#n4836'>4836</a>
<a id='n4837' href='#n4837'>4837</a>
<a id='n4838' href='#n4838'>4838</a>
<a id='n4839' href='#n4839'>4839</a>
<a id='n4840' href='#n4840'>4840</a>
<a id='n4841' href='#n4841'>4841</a>
<a id='n4842' href='#n4842'>4842</a>
<a id='n4843' href='#n4843'>4843</a>
<a id='n4844' href='#n4844'>4844</a>
<a id='n4845' href='#n4845'>4845</a>
<a id='n4846' href='#n4846'>4846</a>
<a id='n4847' href='#n4847'>4847</a>
<a id='n4848' href='#n4848'>4848</a>
<a id='n4849' href='#n4849'>4849</a>
<a id='n4850' href='#n4850'>4850</a>
<a id='n4851' href='#n4851'>4851</a>
<a id='n4852' href='#n4852'>4852</a>
<a id='n4853' href='#n4853'>4853</a>
<a id='n4854' href='#n4854'>4854</a>
<a id='n4855' href='#n4855'>4855</a>
<a id='n4856' href='#n4856'>4856</a>
<a id='n4857' href='#n4857'>4857</a>
<a id='n4858' href='#n4858'>4858</a>
<a id='n4859' href='#n4859'>4859</a>
<a id='n4860' href='#n4860'>4860</a>
<a id='n4861' href='#n4861'>4861</a>
<a id='n4862' href='#n4862'>4862</a>
<a id='n4863' href='#n4863'>4863</a>
<a id='n4864' href='#n4864'>4864</a>
<a id='n4865' href='#n4865'>4865</a>
<a id='n4866' href='#n4866'>4866</a>
<a id='n4867' href='#n4867'>4867</a>
<a id='n4868' href='#n4868'>4868</a>
<a id='n4869' href='#n4869'>4869</a>
<a id='n4870' href='#n4870'>4870</a>
<a id='n4871' href='#n4871'>4871</a>
<a id='n4872' href='#n4872'>4872</a>
<a id='n4873' href='#n4873'>4873</a>
<a id='n4874' href='#n4874'>4874</a>
<a id='n4875' href='#n4875'>4875</a>
<a id='n4876' href='#n4876'>4876</a>
<a id='n4877' href='#n4877'>4877</a>
<a id='n4878' href='#n4878'>4878</a>
<a id='n4879' href='#n4879'>4879</a>
<a id='n4880' href='#n4880'>4880</a>
<a id='n4881' href='#n4881'>4881</a>
<a id='n4882' href='#n4882'>4882</a>
<a id='n4883' href='#n4883'>4883</a>
<a id='n4884' href='#n4884'>4884</a>
<a id='n4885' href='#n4885'>4885</a>
<a id='n4886' href='#n4886'>4886</a>
<a id='n4887' href='#n4887'>4887</a>
<a id='n4888' href='#n4888'>4888</a>
<a id='n4889' href='#n4889'>4889</a>
<a id='n4890' href='#n4890'>4890</a>
<a id='n4891' href='#n4891'>4891</a>
<a id='n4892' href='#n4892'>4892</a>
<a id='n4893' href='#n4893'>4893</a>
<a id='n4894' href='#n4894'>4894</a>
<a id='n4895' href='#n4895'>4895</a>
<a id='n4896' href='#n4896'>4896</a>
<a id='n4897' href='#n4897'>4897</a>
<a id='n4898' href='#n4898'>4898</a>
<a id='n4899' href='#n4899'>4899</a>
<a id='n4900' href='#n4900'>4900</a>
<a id='n4901' href='#n4901'>4901</a>
<a id='n4902' href='#n4902'>4902</a>
<a id='n4903' href='#n4903'>4903</a>
<a id='n4904' href='#n4904'>4904</a>
<a id='n4905' href='#n4905'>4905</a>
<a id='n4906' href='#n4906'>4906</a>
<a id='n4907' href='#n4907'>4907</a>
<a id='n4908' href='#n4908'>4908</a>
<a id='n4909' href='#n4909'>4909</a>
<a id='n4910' href='#n4910'>4910</a>
<a id='n4911' href='#n4911'>4911</a>
<a id='n4912' href='#n4912'>4912</a>
<a id='n4913' href='#n4913'>4913</a>
<a id='n4914' href='#n4914'>4914</a>
<a id='n4915' href='#n4915'>4915</a>
<a id='n4916' href='#n4916'>4916</a>
<a id='n4917' href='#n4917'>4917</a>
<a id='n4918' href='#n4918'>4918</a>
<a id='n4919' href='#n4919'>4919</a>
<a id='n4920' href='#n4920'>4920</a>
<a id='n4921' href='#n4921'>4921</a>
<a id='n4922' href='#n4922'>4922</a>
<a id='n4923' href='#n4923'>4923</a>
<a id='n4924' href='#n4924'>4924</a>
<a id='n4925' href='#n4925'>4925</a>
<a id='n4926' href='#n4926'>4926</a>
<a id='n4927' href='#n4927'>4927</a>
<a id='n4928' href='#n4928'>4928</a>
<a id='n4929' href='#n4929'>4929</a>
<a id='n4930' href='#n4930'>4930</a>
<a id='n4931' href='#n4931'>4931</a>
<a id='n4932' href='#n4932'>4932</a>
<a id='n4933' href='#n4933'>4933</a>
<a id='n4934' href='#n4934'>4934</a>
<a id='n4935' href='#n4935'>4935</a>
<a id='n4936' href='#n4936'>4936</a>
<a id='n4937' href='#n4937'>4937</a>
<a id='n4938' href='#n4938'>4938</a>
<a id='n4939' href='#n4939'>4939</a>
<a id='n4940' href='#n4940'>4940</a>
<a id='n4941' href='#n4941'>4941</a>
<a id='n4942' href='#n4942'>4942</a>
<a id='n4943' href='#n4943'>4943</a>
<a id='n4944' href='#n4944'>4944</a>
<a id='n4945' href='#n4945'>4945</a>
<a id='n4946' href='#n4946'>4946</a>
<a id='n4947' href='#n4947'>4947</a>
<a id='n4948' href='#n4948'>4948</a>
<a id='n4949' href='#n4949'>4949</a>
<a id='n4950' href='#n4950'>4950</a>
<a id='n4951' href='#n4951'>4951</a>
<a id='n4952' href='#n4952'>4952</a>
<a id='n4953' href='#n4953'>4953</a>
<a id='n4954' href='#n4954'>4954</a>
<a id='n4955' href='#n4955'>4955</a>
<a id='n4956' href='#n4956'>4956</a>
<a id='n4957' href='#n4957'>4957</a>
<a id='n4958' href='#n4958'>4958</a>
<a id='n4959' href='#n4959'>4959</a>
<a id='n4960' href='#n4960'>4960</a>
<a id='n4961' href='#n4961'>4961</a>
<a id='n4962' href='#n4962'>4962</a>
<a id='n4963' href='#n4963'>4963</a>
<a id='n4964' href='#n4964'>4964</a>
<a id='n4965' href='#n4965'>4965</a>
<a id='n4966' href='#n4966'>4966</a>
<a id='n4967' href='#n4967'>4967</a>
<a id='n4968' href='#n4968'>4968</a>
<a id='n4969' href='#n4969'>4969</a>
<a id='n4970' href='#n4970'>4970</a>
<a id='n4971' href='#n4971'>4971</a>
<a id='n4972' href='#n4972'>4972</a>
<a id='n4973' href='#n4973'>4973</a>
<a id='n4974' href='#n4974'>4974</a>
<a id='n4975' href='#n4975'>4975</a>
<a id='n4976' href='#n4976'>4976</a>
<a id='n4977' href='#n4977'>4977</a>
<a id='n4978' href='#n4978'>4978</a>
<a id='n4979' href='#n4979'>4979</a>
<a id='n4980' href='#n4980'>4980</a>
<a id='n4981' href='#n4981'>4981</a>
<a id='n4982' href='#n4982'>4982</a>
<a id='n4983' href='#n4983'>4983</a>
<a id='n4984' href='#n4984'>4984</a>
<a id='n4985' href='#n4985'>4985</a>
<a id='n4986' href='#n4986'>4986</a>
<a id='n4987' href='#n4987'>4987</a>
<a id='n4988' href='#n4988'>4988</a>
<a id='n4989' href='#n4989'>4989</a>
<a id='n4990' href='#n4990'>4990</a>
<a id='n4991' href='#n4991'>4991</a>
<a id='n4992' href='#n4992'>4992</a>
<a id='n4993' href='#n4993'>4993</a>
<a id='n4994' href='#n4994'>4994</a>
<a id='n4995' href='#n4995'>4995</a>
<a id='n4996' href='#n4996'>4996</a>
<a id='n4997' href='#n4997'>4997</a>
<a id='n4998' href='#n4998'>4998</a>
<a id='n4999' href='#n4999'>4999</a>
<a id='n5000' href='#n5000'>5000</a>
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<a id='n5002' href='#n5002'>5002</a>
<a id='n5003' href='#n5003'>5003</a>
<a id='n5004' href='#n5004'>5004</a>
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<a id='n5025' href='#n5025'>5025</a>
</pre></td>
<td class='lines'><pre><code><span class="hl com">/*</span>
<span class="hl com"> * Copyright 2006-2007 Advanced Micro Devices, Inc.  </span>
<span class="hl com"> *</span>
<span class="hl com"> * Permission is hereby granted, free of charge, to any person obtaining a</span>
<span class="hl com"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span>
<span class="hl com"> * to deal in the Software without restriction, including without limitation</span>
<span class="hl com"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span>
<span class="hl com"> * and/or sell copies of the Software, and to permit persons to whom the</span>
<span class="hl com"> * Software is furnished to do so, subject to the following conditions:</span>
<span class="hl com"> *</span>
<span class="hl com"> * The above copyright notice and this permission notice shall be included in</span>
<span class="hl com"> * all copies or substantial portions of the Software.</span>
<span class="hl com"> *</span>
<span class="hl com"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</span>
<span class="hl com"> * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</span>
<span class="hl com"> * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</span>
<span class="hl com"> * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</span>
<span class="hl com"> * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span>
<span class="hl com"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span>
<span class="hl com"> * OTHER DEALINGS IN THE SOFTWARE.</span>
<span class="hl com"> */</span>


<span class="hl com">/****************************************************************************/</span>	
<span class="hl com">/*Portion I: Definitions  shared between VBIOS and Driver                   */</span>
<span class="hl com">/****************************************************************************/</span>


<span class="hl ppc">#ifndef _ATOMBIOS_H</span>
<span class="hl ppc">#define _ATOMBIOS_H</span>

<span class="hl ppc">#define ATOM_VERSION_MAJOR                   0x00020000</span>
<span class="hl ppc">#define ATOM_VERSION_MINOR                   0x00000002</span>

<span class="hl ppc">#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)</span>

<span class="hl com">/* Endianness should be specified before inclusion,</span>
<span class="hl com"> * default to little endian</span>
<span class="hl com"> */</span>
<span class="hl ppc">#ifndef ATOM_BIG_ENDIAN</span>
<span class="hl ppc">#error Endian not specified</span>
<span class="hl ppc">#endif</span>

<span class="hl ppc">#ifdef _H2INC</span>
  <span class="hl ppc">#ifndef ULONG </span>
    <span class="hl kwc">typedef</span> <span class="hl kwb">unsigned long</span> ULONG<span class="hl opt">;</span>
  <span class="hl ppc">#endif</span>

  <span class="hl ppc">#ifndef UCHAR</span>
    <span class="hl kwc">typedef</span> <span class="hl kwb">unsigned char</span> UCHAR<span class="hl opt">;</span>
  <span class="hl ppc">#endif</span>

  <span class="hl ppc">#ifndef USHORT </span>
    <span class="hl kwc">typedef</span> <span class="hl kwb">unsigned short</span> USHORT<span class="hl opt">;</span>
  <span class="hl ppc">#endif</span>
<span class="hl ppc">#endif</span>
      
<span class="hl ppc">#define ATOM_DAC_A            0 </span>
<span class="hl ppc">#define ATOM_DAC_B            1</span>
<span class="hl ppc">#define ATOM_EXT_DAC          2</span>

<span class="hl ppc">#define ATOM_CRTC1            0</span>
<span class="hl ppc">#define ATOM_CRTC2            1</span>

<span class="hl ppc">#define ATOM_DIGA             0</span>
<span class="hl ppc">#define ATOM_DIGB             1</span>

<span class="hl ppc">#define ATOM_PPLL1            0</span>
<span class="hl ppc">#define ATOM_PPLL2            1</span>

<span class="hl ppc">#define ATOM_SCALER1          0</span>
<span class="hl ppc">#define ATOM_SCALER2          1</span>

<span class="hl ppc">#define ATOM_SCALER_DISABLE   0   </span>
<span class="hl ppc">#define ATOM_SCALER_CENTER    1   </span>
<span class="hl ppc">#define ATOM_SCALER_EXPANSION 2   </span>
<span class="hl ppc">#define ATOM_SCALER_MULTI_EX  3   </span>

<span class="hl ppc">#define ATOM_DISABLE          0</span>
<span class="hl ppc">#define ATOM_ENABLE           1</span>
<span class="hl ppc">#define ATOM_LCD_BLOFF                          (ATOM_DISABLE+2)</span>
<span class="hl ppc">#define ATOM_LCD_BLON                           (ATOM_ENABLE+2)</span>
<span class="hl ppc">#define ATOM_LCD_BL_BRIGHTNESS_CONTROL          (ATOM_ENABLE+3)</span>
<span class="hl ppc">#define ATOM_LCD_SELFTEST_START									(ATOM_DISABLE+5)</span>
<span class="hl ppc">#define ATOM_LCD_SELFTEST_STOP									(ATOM_ENABLE+5)</span>
<span class="hl ppc">#define ATOM_ENCODER_INIT			                  (ATOM_DISABLE+7)</span>

<span class="hl ppc">#define ATOM_BLANKING         1</span>
<span class="hl ppc">#define ATOM_BLANKING_OFF     0</span>

<span class="hl ppc">#define ATOM_CURSOR1          0</span>
<span class="hl ppc">#define ATOM_CURSOR2          1</span>

<span class="hl ppc">#define ATOM_ICON1            0</span>
<span class="hl ppc">#define ATOM_ICON2            1</span>

<span class="hl ppc">#define ATOM_CRT1             0</span>
<span class="hl ppc">#define ATOM_CRT2             1</span>

<span class="hl ppc">#define ATOM_TV_NTSC          1</span>
<span class="hl ppc">#define ATOM_TV_NTSCJ         2</span>
<span class="hl ppc">#define ATOM_TV_PAL           3</span>
<span class="hl ppc">#define ATOM_TV_PALM          4</span>
<span class="hl ppc">#define ATOM_TV_PALCN         5</span>
<span class="hl ppc">#define ATOM_TV_PALN          6</span>
<span class="hl ppc">#define ATOM_TV_PAL60         7</span>
<span class="hl ppc">#define ATOM_TV_SECAM         8</span>
<span class="hl ppc">#define ATOM_TV_CV            16</span>

<span class="hl ppc">#define ATOM_DAC1_PS2         1</span>
<span class="hl ppc">#define ATOM_DAC1_CV          2</span>
<span class="hl ppc">#define ATOM_DAC1_NTSC        3</span>
<span class="hl ppc">#define ATOM_DAC1_PAL         4</span>

<span class="hl ppc">#define ATOM_DAC2_PS2         ATOM_DAC1_PS2</span>
<span class="hl ppc">#define ATOM_DAC2_CV          ATOM_DAC1_CV</span>
<span class="hl ppc">#define ATOM_DAC2_NTSC        ATOM_DAC1_NTSC</span>
<span class="hl ppc">#define ATOM_DAC2_PAL         ATOM_DAC1_PAL</span>
 
<span class="hl ppc">#define ATOM_PM_ON            0</span>
<span class="hl ppc">#define ATOM_PM_STANDBY       1</span>
<span class="hl ppc">#define ATOM_PM_SUSPEND       2</span>
<span class="hl ppc">#define ATOM_PM_OFF           3</span>

<span class="hl com">/* Bit0:{=0:single, =1:dual},</span>
<span class="hl com">   Bit1 {=0:666RGB, =1:888RGB},</span>
<span class="hl com">   Bit2:3:{Grey level}</span>
<span class="hl com">   Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/</span>

<span class="hl ppc">#define ATOM_PANEL_MISC_DUAL               0x00000001</span>
<span class="hl ppc">#define ATOM_PANEL_MISC_888RGB             0x00000002</span>
<span class="hl ppc">#define ATOM_PANEL_MISC_GREY_LEVEL         0x0000000C</span>
<span class="hl ppc">#define ATOM_PANEL_MISC_FPDI               0x00000010</span>
<span class="hl ppc">#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT   2</span>
<span class="hl ppc">#define ATOM_PANEL_MISC_SPATIAL            0x00000020</span>
<span class="hl ppc">#define ATOM_PANEL_MISC_TEMPORAL           0x00000040</span>
<span class="hl ppc">#define ATOM_PANEL_MISC_API_ENABLED        0x00000080</span>


<span class="hl ppc">#define MEMTYPE_DDR1</span>              <span class="hl pps">&quot;DDR1&quot;</span><span class="hl ppc"></span>
<span class="hl ppc">#define MEMTYPE_DDR2</span>              <span class="hl pps">&quot;DDR2&quot;</span><span class="hl ppc"></span>
<span class="hl ppc">#define MEMTYPE_DDR3</span>              <span class="hl pps">&quot;DDR3&quot;</span><span class="hl ppc"></span>
<span class="hl ppc">#define MEMTYPE_DDR4</span>              <span class="hl pps">&quot;DDR4&quot;</span><span class="hl ppc"></span>

<span class="hl ppc">#define ASIC_BUS_TYPE_PCI</span>         <span class="hl pps">&quot;PCI&quot;</span><span class="hl ppc"></span>
<span class="hl ppc">#define ASIC_BUS_TYPE_AGP</span>         <span class="hl pps">&quot;AGP&quot;</span><span class="hl ppc"></span>
<span class="hl ppc">#define ASIC_BUS_TYPE_PCIE</span>        <span class="hl pps">&quot;PCI_EXPRESS&quot;</span><span class="hl ppc"></span>

<span class="hl com">/* Maximum size of that FireGL flag string */</span>

<span class="hl ppc">#define ATOM_FIREGL_FLAG_STRING</span>     <span class="hl pps">&quot;FGL&quot;</span><span class="hl ppc"></span>             <span class="hl slc">//Flag used to enable FireGL Support</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING  3</span>        <span class="hl slc">//sizeof( ATOM_FIREGL_FLAG_STRING )</span>
<span class="hl ppc"></span>
<span class="hl ppc">#define ATOM_FAKE_DESKTOP_STRING</span>    <span class="hl pps">&quot;DSK&quot;</span><span class="hl ppc"></span>             <span class="hl slc">//Flag used to enable mobile ASIC on Desktop</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING  ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING </span>

<span class="hl ppc">#define ATOM_M54T_FLAG_STRING</span>       <span class="hl pps">&quot;M54T&quot;</span><span class="hl ppc"></span>            <span class="hl slc">//Flag used to enable M54T Support</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING    4</span>        <span class="hl slc">//sizeof( ATOM_M54T_FLAG_STRING )</span>
<span class="hl ppc"></span>
<span class="hl ppc">#define HW_ASSISTED_I2C_STATUS_FAILURE          2</span>
<span class="hl ppc">#define HW_ASSISTED_I2C_STATUS_SUCCESS          1</span>

<span class="hl ppc">#pragma pack(1)</span>                                       <span class="hl com">/* BIOS data must use byte aligment */</span><span class="hl ppc"></span>

<span class="hl com">/*  Define offset to location of ROM header. */</span>

<span class="hl ppc">#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER		0x00000048L</span>
<span class="hl ppc">#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE				    0x00000002L</span>

<span class="hl ppc">#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE    0x94</span>
<span class="hl ppc">#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE   20</span>    <span class="hl com">/* including the terminator 0x0! */</span><span class="hl ppc"></span>
<span class="hl ppc">#define	OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER		0x002f</span>
<span class="hl ppc">#define	OFFSET_TO_GET_ATOMBIOS_STRINGS_START		0x006e</span>

<span class="hl com">/* Common header for all ROM Data tables.</span>
<span class="hl com">  Every table pointed  _ATOM_MASTER_DATA_TABLE has this common header. </span>
<span class="hl com">  And the pointer actually points to this header. */</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_COMMON_TABLE_HEADER
<span class="hl opt">{</span>
  USHORT usStructureSize<span class="hl opt">;</span>
  UCHAR  ucTableFormatRevision<span class="hl opt">;</span>   <span class="hl com">/*Change it when the Parser is not backward compatible */</span>
  UCHAR  ucTableContentRevision<span class="hl opt">;</span>  <span class="hl com">/*Change it only when the table needs to change but the firmware */</span>
                                  <span class="hl com">/*Image can&apos;t be updated, while Driver needs to carry the new table! */</span>
<span class="hl opt">}</span>ATOM_COMMON_TABLE_HEADER<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_ROM_HEADER
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER		sHeader<span class="hl opt">;</span>
  UCHAR	 uaFirmWareSignature<span class="hl opt">[</span><span class="hl num">4</span><span class="hl opt">];</span>    <span class="hl com">/*Signature to distinguish between Atombios and non-atombios, </span>
<span class="hl com">                                      atombios should init it as &quot;ATOM&quot;, don&apos;t change the position */</span>
  USHORT usBiosRuntimeSegmentAddress<span class="hl opt">;</span>
  USHORT usProtectedModeInfoOffset<span class="hl opt">;</span>
  USHORT usConfigFilenameOffset<span class="hl opt">;</span>
  USHORT usCRC_BlockOffset<span class="hl opt">;</span>
  USHORT usBIOS_BootupMessageOffset<span class="hl opt">;</span>
  USHORT usInt10Offset<span class="hl opt">;</span>
  USHORT usPciBusDevInitCode<span class="hl opt">;</span>
  USHORT usIoBaseAddress<span class="hl opt">;</span>
  USHORT usSubsystemVendorID<span class="hl opt">;</span>
  USHORT usSubsystemID<span class="hl opt">;</span>
  USHORT usPCI_InfoOffset<span class="hl opt">;</span> 
  USHORT usMasterCommandTableOffset<span class="hl opt">;</span> <span class="hl com">/*Offset for SW to get all command table offsets, Don&apos;t change the position */</span>
  USHORT usMasterDataTableOffset<span class="hl opt">;</span>   <span class="hl com">/*Offset for SW to get all data table offsets, Don&apos;t change the position */</span>
  UCHAR  ucExtendedFunctionCode<span class="hl opt">;</span>
  UCHAR  ucReserved<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_ROM_HEADER<span class="hl opt">;</span>

<span class="hl com">/*==============================Command Table Portion==================================== */</span>

<span class="hl ppc">#ifdef	UEFI_BUILD</span>
	<span class="hl ppc">#define	UTEMP	USHORT</span>
	<span class="hl ppc">#define	USHORT	void*</span>
<span class="hl ppc">#endif</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_MASTER_LIST_OF_COMMAND_TABLES<span class="hl opt">{</span>
  USHORT ASIC_Init<span class="hl opt">;</span>                              <span class="hl slc">//Function Table, used by various SW components,latest version 1.1</span>
  USHORT GetDisplaySurfaceSize<span class="hl opt">;</span>                  <span class="hl slc">//Atomic Table,  Used by Bios when enabling HW ICON</span>
  USHORT ASIC_RegistersInit<span class="hl opt">;</span>                     <span class="hl slc">//Atomic Table,  indirectly used by various SW components,called from ASIC_Init</span>
  USHORT VRAM_BlockVenderDetection<span class="hl opt">;</span>              <span class="hl slc">//Atomic Table,  used only by Bios</span>
  USHORT DIGxEncoderControl<span class="hl opt">;</span>										 <span class="hl slc">//Only used by Bios</span>
  USHORT MemoryControllerInit<span class="hl opt">;</span>                   <span class="hl slc">//Atomic Table,  indirectly used by various SW components,called from ASIC_Init</span>
  USHORT EnableCRTCMemReq<span class="hl opt">;</span>                       <span class="hl slc">//Function Table,directly used by various SW components,latest version 2.1</span>
  USHORT MemoryParamAdjust<span class="hl opt">;</span> 										 <span class="hl slc">//Atomic Table,  indirectly used by various SW components,called from SetMemoryClock if needed</span>
  USHORT DVOEncoderControl<span class="hl opt">;</span>                      <span class="hl slc">//Function Table,directly used by various SW components,latest version 1.2</span>
  USHORT GPIOPinControl<span class="hl opt">;</span>												 <span class="hl slc">//Atomic Table,  only used by Bios</span>
  USHORT SetEngineClock<span class="hl opt">;</span>                         <span class="hl slc">//Function Table,directly used by various SW components,latest version 1.1</span>
  USHORT SetMemoryClock<span class="hl opt">;</span>                         <span class="hl slc">//Function Table,directly used by various SW components,latest version 1.1</span>
  USHORT SetPixelClock<span class="hl opt">;</span>                          <span class="hl slc">//Function Table,directly used by various SW components,latest version 1.2  </span>
  USHORT DynamicClockGating<span class="hl opt">;</span>                     <span class="hl slc">//Atomic Table,  indirectly used by various SW components,called from ASIC_Init</span>
  USHORT ResetMemoryDLL<span class="hl opt">;</span>                         <span class="hl slc">//Atomic Table,  indirectly used by various SW components,called from SetMemoryClock</span>
  USHORT ResetMemoryDevice<span class="hl opt">;</span>                      <span class="hl slc">//Atomic Table,  indirectly used by various SW components,called from SetMemoryClock</span>
  USHORT MemoryPLLInit<span class="hl opt">;</span>
  USHORT AdjustDisplayPll<span class="hl opt">;</span>												<span class="hl slc">//only used by Bios</span>
  USHORT AdjustMemoryController<span class="hl opt">;</span>                 <span class="hl slc">//Atomic Table,  indirectly used by various SW components,called from SetMemoryClock                </span>
  USHORT EnableASIC_StaticPwrMgt<span class="hl opt">;</span>                <span class="hl slc">//Atomic Table,  only used by Bios</span>
  USHORT ASIC_StaticPwrMgtStatusChange<span class="hl opt">;</span>          <span class="hl slc">//Obsolete ,     only used by Bios   </span>
  USHORT DAC_LoadDetection<span class="hl opt">;</span>                      <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.2  </span>
  USHORT LVTMAEncoderControl<span class="hl opt">;</span>                    <span class="hl slc">//Atomic Table,directly used by various SW components,latest version 1.3</span>
  USHORT LCD1OutputControl<span class="hl opt">;</span>                      <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1 </span>
  USHORT DAC1EncoderControl<span class="hl opt">;</span>                     <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1  </span>
  USHORT DAC2EncoderControl<span class="hl opt">;</span>                     <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1 </span>
  USHORT DVOOutputControl<span class="hl opt">;</span>                       <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1 </span>
  USHORT CV1OutputControl<span class="hl opt">;</span>                       <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1 </span>
  USHORT GetConditionalGoldenSetting<span class="hl opt">;</span>            <span class="hl slc">//only used by Bios</span>
  USHORT TVEncoderControl<span class="hl opt">;</span>                       <span class="hl slc">//Function Table,directly used by various SW components,latest version 1.1</span>
  USHORT TMDSAEncoderControl<span class="hl opt">;</span>                    <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.3</span>
  USHORT LVDSEncoderControl<span class="hl opt">;</span>                     <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.3</span>
  USHORT TV1OutputControl<span class="hl opt">;</span>                       <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1</span>
  USHORT EnableScaler<span class="hl opt">;</span>                           <span class="hl slc">//Atomic Table,  used only by Bios</span>
  USHORT BlankCRTC<span class="hl opt">;</span>                              <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1 </span>
  USHORT EnableCRTC<span class="hl opt">;</span>                             <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1 </span>
  USHORT GetPixelClock<span class="hl opt">;</span>                          <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1 </span>
  USHORT EnableVGA_Render<span class="hl opt">;</span>                       <span class="hl slc">//Function Table,directly used by various SW components,latest version 1.1</span>
  USHORT EnableVGA_Access<span class="hl opt">;</span>                       <span class="hl slc">//Obsolete ,     only used by Bios</span>
  USHORT SetCRTC_Timing<span class="hl opt">;</span>                         <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1</span>
  USHORT SetCRTC_OverScan<span class="hl opt">;</span>                       <span class="hl slc">//Atomic Table,  used by various SW components,latest version 1.1 </span>
  USHORT SetCRTC_Replication<span class="hl opt">;</span>                    <span class="hl slc">//Atomic Table,  used only by Bios</span>
  USHORT SelectCRTC_Source<span class="hl opt">;</span>                      <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1 </span>
  USHORT EnableGraphSurfaces<span class="hl opt">;</span>                    <span class="hl slc">//Atomic Table,  used only by Bios</span>
  USHORT UpdateCRTC_DoubleBufferRegisters<span class="hl opt">;</span>
  USHORT LUT_AutoFill<span class="hl opt">;</span>                           <span class="hl slc">//Atomic Table,  only used by Bios</span>
  USHORT EnableHW_IconCursor<span class="hl opt">;</span>                    <span class="hl slc">//Atomic Table,  only used by Bios</span>
  USHORT GetMemoryClock<span class="hl opt">;</span>                         <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1 </span>
  USHORT GetEngineClock<span class="hl opt">;</span>                         <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1 </span>
  USHORT SetCRTC_UsingDTDTiming<span class="hl opt">;</span>                 <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1</span>
  USHORT ExternalEncoderControl<span class="hl opt">;</span>                 <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 2.1</span>
  USHORT LVTMAOutputControl<span class="hl opt">;</span>                     <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1</span>
  USHORT VRAM_BlockDetectionByStrap<span class="hl opt">;</span>             <span class="hl slc">//Atomic Table,  used only by Bios</span>
  USHORT MemoryCleanUp<span class="hl opt">;</span>                          <span class="hl slc">//Atomic Table,  only used by Bios    </span>
  USHORT ProcessI2cChannelTransaction<span class="hl opt">;</span>           <span class="hl slc">//Function Table,only used by Bios</span>
  USHORT WriteOneByteToHWAssistedI2C<span class="hl opt">;</span>            <span class="hl slc">//Function Table,indirectly used by various SW components </span>
  USHORT ReadHWAssistedI2CStatus<span class="hl opt">;</span>                <span class="hl slc">//Atomic Table,  indirectly used by various SW components</span>
  USHORT SpeedFanControl<span class="hl opt">;</span>                        <span class="hl slc">//Function Table,indirectly used by various SW components,called from ASIC_Init</span>
  USHORT PowerConnectorDetection<span class="hl opt">;</span>                <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1</span>
  USHORT MC_Synchronization<span class="hl opt">;</span>                     <span class="hl slc">//Atomic Table,  indirectly used by various SW components,called from SetMemoryClock</span>
  USHORT ComputeMemoryEnginePLL<span class="hl opt">;</span>                 <span class="hl slc">//Atomic Table,  indirectly used by various SW components,called from SetMemory/EngineClock</span>
  USHORT MemoryRefreshConversion<span class="hl opt">;</span>                <span class="hl slc">//Atomic Table,  indirectly used by various SW components,called from SetMemory or SetEngineClock</span>
  USHORT VRAM_GetCurrentInfoBlock<span class="hl opt">;</span>               <span class="hl slc">//Atomic Table,  used only by Bios</span>
  USHORT DynamicMemorySettings<span class="hl opt">;</span>                  <span class="hl slc">//Atomic Table,  indirectly used by various SW components,called from SetMemoryClock</span>
  USHORT MemoryTraining<span class="hl opt">;</span>                         <span class="hl slc">//Atomic Table,  used only by Bios</span>
  USHORT EnableSpreadSpectrumOnPPLL<span class="hl opt">;</span>             <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.2</span>
  USHORT TMDSAOutputControl<span class="hl opt">;</span>                     <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1</span>
  USHORT SetVoltage<span class="hl opt">;</span>                             <span class="hl slc">//Function Table,directly and/or indirectly used by various SW components,latest version 1.1</span>
  USHORT DAC1OutputControl<span class="hl opt">;</span>                      <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1</span>
  USHORT DAC2OutputControl<span class="hl opt">;</span>                      <span class="hl slc">//Atomic Table,  directly used by various SW components,latest version 1.1</span>
  USHORT SetupHWAssistedI2CStatus<span class="hl opt">;</span>               <span class="hl slc">//Function Table,only used by Bios, obsolete soon.Switch to use &quot;ReadEDIDFromHWAssistedI2C&quot;</span>
  USHORT ClockSource<span class="hl opt">;</span>                            <span class="hl slc">//Atomic Table,  indirectly used by various SW components,called from ASIC_Init</span>
  USHORT MemoryDeviceInit<span class="hl opt">;</span>                       <span class="hl slc">//Atomic Table,  indirectly used by various SW components,called from SetMemoryClock</span>
  USHORT EnableYUV<span class="hl opt">;</span>                              <span class="hl slc">//Atomic Table,  indirectly used by various SW components,called from EnableVGARender</span>
  USHORT DIG1EncoderControl<span class="hl opt">;</span>                     <span class="hl slc">//Atomic Table,directly used by various SW components,latest version 1.1</span>
  USHORT DIG2EncoderControl<span class="hl opt">;</span>                     <span class="hl slc">//Atomic Table,directly used by various SW components,latest version 1.1</span>
  USHORT DIG1TransmitterControl<span class="hl opt">;</span>                 <span class="hl slc">//Atomic Table,directly used by various SW components,latest version 1.1</span>
  USHORT DIG2TransmitterControl<span class="hl opt">;</span>	               <span class="hl slc">//Atomic Table,directly used by various SW components,latest version 1.1 </span>
  USHORT ProcessAuxChannelTransaction<span class="hl opt">;</span>					 <span class="hl slc">//Function Table,only used by Bios</span>
  USHORT DPEncoderService<span class="hl opt">;</span>											 <span class="hl slc">//Function Table,only used by Bios</span>
<span class="hl opt">}</span>ATOM_MASTER_LIST_OF_COMMAND_TABLES<span class="hl opt">;</span>   

<span class="hl slc">// For backward compatible </span>
<span class="hl ppc">#define ReadEDIDFromHWAssistedI2C                ProcessI2cChannelTransaction</span>
<span class="hl ppc">#define UNIPHYTransmitterControl						     DIG1TransmitterControl</span>
<span class="hl ppc">#define LVTMATransmitterControl							     DIG2TransmitterControl</span>
<span class="hl ppc">#define SetCRTC_DPM_State                        GetConditionalGoldenSetting</span>
<span class="hl ppc">#define SetUniphyInstance                        ASIC_StaticPwrMgtStatusChange</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_MASTER_COMMAND_TABLE
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER           sHeader<span class="hl opt">;</span>
  ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_MASTER_COMMAND_TABLE<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used in every command table</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_TABLE_ATTRIBUTE
<span class="hl opt">{</span>
<span class="hl ppc">#if ATOM_BIG_ENDIAN</span>
  USHORT  UpdatedByUtility<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>         <span class="hl slc">//[15]=Table updated by utility flag</span>
  USHORT  PS_SizeInBytes<span class="hl opt">:</span><span class="hl num">7</span><span class="hl opt">;</span>           <span class="hl slc">//[14:8]=Size of parameter space in Bytes (multiple of a dword), </span>
  USHORT  WS_SizeInBytes<span class="hl opt">:</span><span class="hl num">8</span><span class="hl opt">;</span>           <span class="hl slc">//[7:0]=Size of workspace in Bytes (in multiple of a dword), </span>
<span class="hl ppc">#else</span>
  USHORT  WS_SizeInBytes<span class="hl opt">:</span><span class="hl num">8</span><span class="hl opt">;</span>           <span class="hl slc">//[7:0]=Size of workspace in Bytes (in multiple of a dword), </span>
  USHORT  PS_SizeInBytes<span class="hl opt">:</span><span class="hl num">7</span><span class="hl opt">;</span>           <span class="hl slc">//[14:8]=Size of parameter space in Bytes (multiple of a dword), </span>
  USHORT  UpdatedByUtility<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>         <span class="hl slc">//[15]=Table updated by utility flag</span>
<span class="hl ppc">#endif</span>
<span class="hl opt">}</span>ATOM_TABLE_ATTRIBUTE<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">union</span> _ATOM_TABLE_ATTRIBUTE_ACCESS
<span class="hl opt">{</span>
  ATOM_TABLE_ATTRIBUTE sbfAccess<span class="hl opt">;</span>
  USHORT               susAccess<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_TABLE_ATTRIBUTE_ACCESS<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Common header for all command tables.</span>
<span class="hl slc">// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. </span>
<span class="hl slc">// And the pointer actually points to this header.</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER CommonHeader<span class="hl opt">;</span>
  ATOM_TABLE_ATTRIBUTE     TableAttribute<span class="hl opt">;</span>	
<span class="hl opt">}</span>ATOM_COMMON_ROM_COMMAND_TABLE_HEADER<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by ComputeMemoryEnginePLLTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl ppc">#define COMPUTE_MEMORY_PLL_PARAM        1</span>
<span class="hl ppc">#define COMPUTE_ENGINE_PLL_PARAM        2</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
<span class="hl opt">{</span>
  ULONG   ulClock<span class="hl opt">;</span>        <span class="hl slc">//When returen, it&apos;s the re-calculated clock based on given Fb_div Post_Div and ref_div</span>
  UCHAR   ucAction<span class="hl opt">;</span>       <span class="hl slc">//0:reserved //1:Memory //2:Engine  </span>
  UCHAR   ucReserved<span class="hl opt">;</span>     <span class="hl slc">//may expand to return larger Fbdiv later</span>
  UCHAR   ucFbDiv<span class="hl opt">;</span>        <span class="hl slc">//return value</span>
  UCHAR   ucPostDiv<span class="hl opt">;</span>      <span class="hl slc">//return value</span>
<span class="hl opt">}</span>COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
<span class="hl opt">{</span>
  ULONG   ulClock<span class="hl opt">;</span>        <span class="hl slc">//When return, [23:0] return real clock </span>
  UCHAR   ucAction<span class="hl opt">;</span>       <span class="hl slc">//0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register</span>
  USHORT  usFbDiv<span class="hl opt">;</span>		    <span class="hl slc">//return Feedback value to be written to register</span>
  UCHAR   ucPostDiv<span class="hl opt">;</span>      <span class="hl slc">//return post div to be written to register</span>
<span class="hl opt">}</span>COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2<span class="hl opt">;</span>
<span class="hl ppc">#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS</span>


<span class="hl ppc">#define SET_CLOCK_FREQ_MASK                     0x00FFFFFF</span>  <span class="hl slc">//Clock change tables only take bit [23:0] as the requested clock value</span>
<span class="hl ppc"></span><span class="hl ppc">#define USE_NON_BUS_CLOCK_MASK                  0x01000000</span>  <span class="hl slc">//Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)</span>
<span class="hl ppc"></span><span class="hl ppc">#define USE_MEMORY_SELF_REFRESH_MASK            0x02000000</span>	<span class="hl slc">//Only applicable to memory clock change, when set, using memory self refresh during clock transition</span>
<span class="hl ppc"></span><span class="hl ppc">#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04000000</span>  <span class="hl slc">//Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change</span>
<span class="hl ppc"></span><span class="hl ppc">#define FIRST_TIME_CHANGE_CLOCK									0x08000000</span>	<span class="hl slc">//Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup</span>
<span class="hl ppc"></span><span class="hl ppc">#define SKIP_SW_PROGRAM_PLL											0x10000000</span>	<span class="hl slc">//Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL</span>
<span class="hl ppc"></span><span class="hl ppc">#define USE_SS_ENABLED_PIXEL_CLOCK  USE_NON_BUS_CLOCK_MASK</span>

<span class="hl ppc">#define b3USE_NON_BUS_CLOCK_MASK                  0x01</span>       <span class="hl slc">//Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)</span>
<span class="hl ppc"></span><span class="hl ppc">#define b3USE_MEMORY_SELF_REFRESH                 0x02</span>	     <span class="hl slc">//Only applicable to memory clock change, when set, using memory self refresh during clock transition</span>
<span class="hl ppc"></span><span class="hl ppc">#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04</span>       <span class="hl slc">//Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change</span>
<span class="hl ppc"></span><span class="hl ppc">#define b3FIRST_TIME_CHANGE_CLOCK									0x08</span>       <span class="hl slc">//Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup</span>
<span class="hl ppc"></span><span class="hl ppc">#define b3SKIP_SW_PROGRAM_PLL											0x10</span>			 <span class="hl slc">//Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL</span>
<span class="hl ppc"></span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_COMPUTE_CLOCK_FREQ
<span class="hl opt">{</span>
<span class="hl ppc">#if ATOM_BIG_ENDIAN</span>
  ULONG ulComputeClockFlag<span class="hl opt">:</span><span class="hl num">8</span><span class="hl opt">;</span>                 <span class="hl slc">// =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM</span>
  ULONG ulClockFreq<span class="hl opt">:</span><span class="hl num">24</span><span class="hl opt">;</span>                       <span class="hl slc">// in unit of 10kHz</span>
<span class="hl ppc">#else</span>
  ULONG ulClockFreq<span class="hl opt">:</span><span class="hl num">24</span><span class="hl opt">;</span>                       <span class="hl slc">// in unit of 10kHz</span>
  ULONG ulComputeClockFlag<span class="hl opt">:</span><span class="hl num">8</span><span class="hl opt">;</span>                 <span class="hl slc">// =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM</span>
<span class="hl ppc">#endif</span>
<span class="hl opt">}</span>ATOM_COMPUTE_CLOCK_FREQ<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_S_MPLL_FB_DIVIDER
<span class="hl opt">{</span>
  USHORT usFbDivFrac<span class="hl opt">;</span>  
  USHORT usFbDiv<span class="hl opt">;</span>  
<span class="hl opt">}</span>ATOM_S_MPLL_FB_DIVIDER<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
<span class="hl opt">{</span>
  <span class="hl kwb">union</span>
  <span class="hl opt">{</span>
    ATOM_COMPUTE_CLOCK_FREQ  ulClock<span class="hl opt">;</span>         <span class="hl slc">//Input Parameter</span>
    ATOM_S_MPLL_FB_DIVIDER   ulFbDiv<span class="hl opt">;</span>         <span class="hl slc">//Output Parameter</span>
  <span class="hl opt">};</span>
  UCHAR   ucRefDiv<span class="hl opt">;</span>                           <span class="hl slc">//Output Parameter      </span>
  UCHAR   ucPostDiv<span class="hl opt">;</span>                          <span class="hl slc">//Output Parameter      </span>
  UCHAR   ucCntlFlag<span class="hl opt">;</span>                         <span class="hl slc">//Output Parameter      </span>
  UCHAR   ucReserved<span class="hl opt">;</span>
<span class="hl opt">}</span>COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3<span class="hl opt">;</span>

<span class="hl slc">// ucCntlFlag</span>
<span class="hl ppc">#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN          1</span>
<span class="hl ppc">#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE            2</span>
<span class="hl ppc">#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE         4</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _DYNAMICE_MEMORY_SETTINGS_PARAMETER
<span class="hl opt">{</span>
  ATOM_COMPUTE_CLOCK_FREQ ulClock<span class="hl opt">;</span>
  ULONG ulReserved<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>
<span class="hl opt">}</span>DYNAMICE_MEMORY_SETTINGS_PARAMETER<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _DYNAMICE_ENGINE_SETTINGS_PARAMETER
<span class="hl opt">{</span>
  ATOM_COMPUTE_CLOCK_FREQ ulClock<span class="hl opt">;</span>
  ULONG ulMemoryClock<span class="hl opt">;</span>
  ULONG ulReserved<span class="hl opt">;</span>
<span class="hl opt">}</span>DYNAMICE_ENGINE_SETTINGS_PARAMETER<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by SetEngineClockTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _SET_ENGINE_CLOCK_PARAMETERS
<span class="hl opt">{</span>
  ULONG ulTargetEngineClock<span class="hl opt">;</span>          <span class="hl slc">//In 10Khz unit</span>
<span class="hl opt">}</span>SET_ENGINE_CLOCK_PARAMETERS<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _SET_ENGINE_CLOCK_PS_ALLOCATION
<span class="hl opt">{</span>
  ULONG ulTargetEngineClock<span class="hl opt">;</span>          <span class="hl slc">//In 10Khz unit</span>
  COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved<span class="hl opt">;</span>
<span class="hl opt">}</span>SET_ENGINE_CLOCK_PS_ALLOCATION<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by SetMemoryClockTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _SET_MEMORY_CLOCK_PARAMETERS
<span class="hl opt">{</span>
  ULONG ulTargetMemoryClock<span class="hl opt">;</span>          <span class="hl slc">//In 10Khz unit</span>
<span class="hl opt">}</span>SET_MEMORY_CLOCK_PARAMETERS<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _SET_MEMORY_CLOCK_PS_ALLOCATION
<span class="hl opt">{</span>
  ULONG ulTargetMemoryClock<span class="hl opt">;</span>          <span class="hl slc">//In 10Khz unit</span>
  COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved<span class="hl opt">;</span>
<span class="hl opt">}</span>SET_MEMORY_CLOCK_PS_ALLOCATION<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by ASIC_Init.ctb</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ASIC_INIT_PARAMETERS
<span class="hl opt">{</span>
  ULONG ulDefaultEngineClock<span class="hl opt">;</span>         <span class="hl slc">//In 10Khz unit</span>
  ULONG ulDefaultMemoryClock<span class="hl opt">;</span>         <span class="hl slc">//In 10Khz unit</span>
<span class="hl opt">}</span>ASIC_INIT_PARAMETERS<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ASIC_INIT_PS_ALLOCATION
<span class="hl opt">{</span>
  ASIC_INIT_PARAMETERS sASICInitClocks<span class="hl opt">;</span>
  SET_ENGINE_CLOCK_PS_ALLOCATION sReserved<span class="hl opt">;</span> <span class="hl slc">//Caller doesn&apos;t need to init this structure</span>
<span class="hl opt">}</span>ASIC_INIT_PS_ALLOCATION<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structure used by DynamicClockGatingTable.ctb</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _DYNAMIC_CLOCK_GATING_PARAMETERS 
<span class="hl opt">{</span>
  UCHAR ucEnable<span class="hl opt">;</span>                     <span class="hl slc">// ATOM_ENABLE or ATOM_DISABLE</span>
  UCHAR ucPadding<span class="hl opt">[</span><span class="hl num">3</span><span class="hl opt">];</span>
<span class="hl opt">}</span>DYNAMIC_CLOCK_GATING_PARAMETERS<span class="hl opt">;</span>
<span class="hl ppc">#define  DYNAMIC_CLOCK_GATING_PS_ALLOCATION  DYNAMIC_CLOCK_GATING_PARAMETERS</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structure used by EnableASIC_StaticPwrMgtTable.ctb</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
<span class="hl opt">{</span>
  UCHAR ucEnable<span class="hl opt">;</span>                     <span class="hl slc">// ATOM_ENABLE or ATOM_DISABLE</span>
  UCHAR ucPadding<span class="hl opt">[</span><span class="hl num">3</span><span class="hl opt">];</span>
<span class="hl opt">}</span>ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS<span class="hl opt">;</span>
<span class="hl ppc">#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION  ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by DAC_LoadDetectionTable.ctb</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _DAC_LOAD_DETECTION_PARAMETERS
<span class="hl opt">{</span>
  USHORT usDeviceID<span class="hl opt">;</span>                  <span class="hl slc">//{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}</span>
  UCHAR  ucDacType<span class="hl opt">;</span>                   <span class="hl slc">//{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}</span>
  UCHAR  ucMisc<span class="hl opt">;</span>											<span class="hl slc">//Valid only when table revision =1.3 and above</span>
<span class="hl opt">}</span>DAC_LOAD_DETECTION_PARAMETERS<span class="hl opt">;</span>

<span class="hl slc">// DAC_LOAD_DETECTION_PARAMETERS.ucMisc</span>
<span class="hl ppc">#define DAC_LOAD_MISC_YPrPb						0x01</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _DAC_LOAD_DETECTION_PS_ALLOCATION
<span class="hl opt">{</span>
  DAC_LOAD_DETECTION_PARAMETERS            sDacload<span class="hl opt">;</span>
  ULONG                                    Reserved<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span><span class="hl slc">// Don&apos;t set this one, allocation for EXT DAC</span>
<span class="hl opt">}</span>DAC_LOAD_DETECTION_PS_ALLOCATION<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _DAC_ENCODER_CONTROL_PARAMETERS 
<span class="hl opt">{</span>
  USHORT usPixelClock<span class="hl opt">;</span>                <span class="hl slc">// in 10KHz; for bios convenient</span>
  UCHAR  ucDacStandard<span class="hl opt">;</span>               <span class="hl slc">// See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)</span>
  UCHAR  ucAction<span class="hl opt">;</span>                    <span class="hl slc">// 0: turn off encoder</span>
                                      <span class="hl slc">// 1: setup and turn on encoder</span>
                                      <span class="hl slc">// 7: ATOM_ENCODER_INIT Initialize DAC</span>
<span class="hl opt">}</span>DAC_ENCODER_CONTROL_PARAMETERS<span class="hl opt">;</span>

<span class="hl ppc">#define DAC_ENCODER_CONTROL_PS_ALLOCATION  DAC_ENCODER_CONTROL_PARAMETERS</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by DIG1EncoderControlTable</span>
<span class="hl slc">//                    DIG2EncoderControlTable</span>
<span class="hl slc">//                    ExternalEncoderControlTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _DIG_ENCODER_CONTROL_PARAMETERS
<span class="hl opt">{</span>
  USHORT usPixelClock<span class="hl opt">;</span>		<span class="hl slc">// in 10KHz; for bios convenient</span>
  UCHAR  ucConfig<span class="hl opt">;</span>		  
                            <span class="hl slc">// [2] Link Select:</span>
                            <span class="hl slc">// =0: PHY linkA if bfLane&lt;3</span>
                            <span class="hl slc">// =1: PHY linkB if bfLanes&lt;3</span>
                            <span class="hl slc">// =0: PHY linkA+B if bfLanes=3</span>
                            <span class="hl slc">// [3] Transmitter Sel</span>
                            <span class="hl slc">// =0: UNIPHY or PCIEPHY</span>
                            <span class="hl slc">// =1: LVTMA 					</span>
  UCHAR ucAction<span class="hl opt">;</span>           <span class="hl slc">// =0: turn off encoder					</span>
                            <span class="hl slc">// =1: turn on encoder			</span>
  UCHAR ucEncoderMode<span class="hl opt">;</span>
                            <span class="hl slc">// =0: DP   encoder      </span>
                            <span class="hl slc">// =1: LVDS encoder          </span>
                            <span class="hl slc">// =2: DVI  encoder  </span>
                            <span class="hl slc">// =3: HDMI encoder</span>
                            <span class="hl slc">// =4: SDVO encoder</span>
  UCHAR ucLaneNum<span class="hl opt">;</span>          <span class="hl slc">// how many lanes to enable</span>
  UCHAR ucReserved<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>
<span class="hl opt">}</span>DIG_ENCODER_CONTROL_PARAMETERS<span class="hl opt">;</span>
<span class="hl ppc">#define DIG_ENCODER_CONTROL_PS_ALLOCATION			  DIG_ENCODER_CONTROL_PARAMETERS</span>
<span class="hl ppc">#define EXTERNAL_ENCODER_CONTROL_PARAMETER			DIG_ENCODER_CONTROL_PARAMETERS</span>

<span class="hl slc">//ucConfig</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK				0x01</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ		0x00</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ		0x01</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK				  0x04</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_LINKA								  0x00</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_LINKB								  0x04</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_LINKA_B							  ATOM_TRANSMITTER_CONFIG_LINKA</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_LINKB_A							  ATOM_ENCODER_CONFIG_LINKB</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK	0x08</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_UNIPHY							  0x00</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_LVTMA								  0x08</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_TRANSMITTER1				  0x00</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_TRANSMITTER2				  0x08</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_DIGB								  0x80</span>			<span class="hl slc">// VBIOS Internal use, outside SW should set this bit=0</span>
<span class="hl ppc"></span><span class="hl slc">// ucAction</span>
<span class="hl slc">// ATOM_ENABLE:  Enable Encoder</span>
<span class="hl slc">// ATOM_DISABLE: Disable Encoder</span>

<span class="hl slc">//ucEncoderMode</span>
<span class="hl ppc">#define ATOM_ENCODER_MODE_DP											0</span>
<span class="hl ppc">#define ATOM_ENCODER_MODE_LVDS										1</span>
<span class="hl ppc">#define ATOM_ENCODER_MODE_DVI											2</span>
<span class="hl ppc">#define ATOM_ENCODER_MODE_HDMI										3</span>
<span class="hl ppc">#define ATOM_ENCODER_MODE_SDVO										4</span>
<span class="hl ppc">#define ATOM_ENCODER_MODE_TV											13</span>
<span class="hl ppc">#define ATOM_ENCODER_MODE_CV											14</span>
<span class="hl ppc">#define ATOM_ENCODER_MODE_CRT											15</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_DIG_ENCODER_CONFIG_V2
<span class="hl opt">{</span>
<span class="hl ppc">#if ATOM_BIG_ENDIAN</span>
    UCHAR ucReserved1<span class="hl opt">:</span><span class="hl num">2</span><span class="hl opt">;</span>
    UCHAR ucTransmitterSel<span class="hl opt">:</span><span class="hl num">2</span><span class="hl opt">;</span>     <span class="hl slc">// =0: UniphyAB, =1: UniphyCD  =2: UniphyEF</span>
    UCHAR ucLinkSel<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>            <span class="hl slc">// =0: linkA/C/E =1: linkB/D/F</span>
    UCHAR ucReserved<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
    UCHAR ucDPLinkRate<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>         <span class="hl slc">// =0: 1.62Ghz, =1: 2.7Ghz</span>
<span class="hl ppc">#else</span>
    UCHAR ucDPLinkRate<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>         <span class="hl slc">// =0: 1.62Ghz, =1: 2.7Ghz</span>
    UCHAR ucReserved<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
    UCHAR ucLinkSel<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>            <span class="hl slc">// =0: linkA/C/E =1: linkB/D/F</span>
    UCHAR ucTransmitterSel<span class="hl opt">:</span><span class="hl num">2</span><span class="hl opt">;</span>     <span class="hl slc">// =0: UniphyAB, =1: UniphyCD  =2: UniphyEF</span>
    UCHAR ucReserved1<span class="hl opt">:</span><span class="hl num">2</span><span class="hl opt">;</span>
<span class="hl ppc">#endif</span>
<span class="hl opt">}</span>ATOM_DIG_ENCODER_CONFIG_V2<span class="hl opt">;</span>


<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _DIG_ENCODER_CONTROL_PARAMETERS_V2
<span class="hl opt">{</span>
  USHORT usPixelClock<span class="hl opt">;</span>      <span class="hl slc">// in 10KHz; for bios convenient</span>
  ATOM_DIG_ENCODER_CONFIG_V2 acConfig<span class="hl opt">;</span>
  UCHAR ucAction<span class="hl opt">;</span>                                       
  UCHAR ucEncoderMode<span class="hl opt">;</span>
                            <span class="hl slc">// =0: DP   encoder      </span>
                            <span class="hl slc">// =1: LVDS encoder          </span>
                            <span class="hl slc">// =2: DVI  encoder  </span>
                            <span class="hl slc">// =3: HDMI encoder</span>
                            <span class="hl slc">// =4: SDVO encoder</span>
  UCHAR ucLaneNum<span class="hl opt">;</span>          <span class="hl slc">// how many lanes to enable</span>
  UCHAR ucReserved<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>
<span class="hl opt">}</span>DIG_ENCODER_CONTROL_PARAMETERS_V2<span class="hl opt">;</span>

<span class="hl slc">//ucConfig</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK				0x01</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ		  0x00</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ		  0x01</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK				  0x04</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_V2_LINKA								  0x00</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_V2_LINKB								  0x04</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK	  0x18</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1				    0x00</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2				    0x08</span>
<span class="hl ppc">#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3				    0x10</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by UNIPHYTransmitterControlTable</span>
<span class="hl slc">//                    LVTMATransmitterControlTable</span>
<span class="hl slc">//                    DVOOutputControlTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_DP_VS_MODE
<span class="hl opt">{</span>
  UCHAR ucLaneSel<span class="hl opt">;</span>
  UCHAR ucLaneSet<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_DP_VS_MODE<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _DIG_TRANSMITTER_CONTROL_PARAMETERS
<span class="hl opt">{</span>
	<span class="hl kwb">union</span>
	<span class="hl opt">{</span>
  USHORT usPixelClock<span class="hl opt">;</span>		<span class="hl slc">// in 10KHz; for bios convenient</span>
	USHORT usInitInfo<span class="hl opt">;</span>			<span class="hl slc">// when init uniphy,lower 8bit is used for connector type defined in objectid.h</span>
  ATOM_DP_VS_MODE asMode<span class="hl opt">;</span> <span class="hl slc">// DP Voltage swing mode</span>
	<span class="hl opt">};</span>
  UCHAR ucConfig<span class="hl opt">;</span>
													<span class="hl slc">// [0]=0: 4 lane Link,      </span>
													<span class="hl slc">//    =1: 8 lane Link ( Dual Links TMDS ) </span>
                          <span class="hl slc">// [1]=0: InCoherent mode   </span>
													<span class="hl slc">//    =1: Coherent Mode										</span>
													<span class="hl slc">// [2] Link Select:</span>
  												<span class="hl slc">// =0: PHY linkA   if bfLane&lt;3</span>
													<span class="hl slc">// =1: PHY linkB   if bfLanes&lt;3</span>
		  										<span class="hl slc">// =0: PHY linkA+B if bfLanes=3		</span>
                          <span class="hl slc">// [5:4]PCIE lane Sel</span>
                          <span class="hl slc">// =0: lane 0~3 or 0~7</span>
                          <span class="hl slc">// =1: lane 4~7</span>
                          <span class="hl slc">// =2: lane 8~11 or 8~15</span>
                          <span class="hl slc">// =3: lane 12~15 </span>
	UCHAR ucAction<span class="hl opt">;</span>				  <span class="hl slc">// =0: turn off encoder					</span>
	                        <span class="hl slc">// =1: turn on encoder			</span>
  UCHAR ucReserved<span class="hl opt">[</span><span class="hl num">4</span><span class="hl opt">];</span>
<span class="hl opt">}</span>DIG_TRANSMITTER_CONTROL_PARAMETERS<span class="hl opt">;</span>

<span class="hl ppc">#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION		DIG_TRANSMITTER_CONTROL_PARAMETERS					</span>

<span class="hl slc">//ucInitInfo</span>
<span class="hl ppc">#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK	0x00ff			</span>

<span class="hl slc">//ucConfig </span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK			0x01</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_COHERENT				0x02</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK		0x04</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_LINKA						0x00</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_LINKB						0x04</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_LINKA_B					0x00			</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_LINKB_A					0x04</span>

<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK	0x08</span>			<span class="hl slc">// only used when ATOM_TRANSMITTER_ACTION_ENABLE</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER		0x00</span>				<span class="hl slc">// only used when ATOM_TRANSMITTER_ACTION_ENABLE</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER		0x08</span>				<span class="hl slc">// only used when ATOM_TRANSMITTER_ACTION_ENABLE</span>
<span class="hl ppc"></span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK			0x30</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL			0x00</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE			0x20</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN		0x30</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK		0xc0</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_LANE_0_3				0x00</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_LANE_0_7				0x00</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_LANE_4_7				0x40</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_LANE_8_11				0x80</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_LANE_8_15				0x80</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_LANE_12_15			0xc0</span>

<span class="hl slc">//ucAction</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_ACTION_DISABLE					       0</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_ACTION_ENABLE					       1</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF				       2</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_ACTION_LCD_BLON				       3</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL  4</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START		 5</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP			 6</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_ACTION_INIT						       7</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT	       8</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT		       9</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_ACTION_SETUP						       10</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH           11</span>


<span class="hl slc">// Following are used for DigTransmitterControlTable ver1.2</span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_DIG_TRANSMITTER_CONFIG_V2
<span class="hl opt">{</span>
<span class="hl ppc">#if ATOM_BIG_ENDIAN</span>
  UCHAR ucTransmitterSel<span class="hl opt">:</span><span class="hl num">2</span><span class="hl opt">;</span>         <span class="hl slc">//bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )</span>
                                    <span class="hl slc">//        =1 Dig Transmitter 2 ( Uniphy CD )</span>
                                    <span class="hl slc">//        =2 Dig Transmitter 3 ( Uniphy EF )</span>
  UCHAR ucReserved<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>               
  UCHAR fDPConnector<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>             <span class="hl slc">//bit4=0: DP connector  =1: None DP connector</span>
  UCHAR ucEncoderSel<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>             <span class="hl slc">//bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )</span>
  UCHAR ucLinkSel<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>                <span class="hl slc">//bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E</span>
                                    <span class="hl slc">//    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F</span>

  UCHAR fCoherentMode<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>            <span class="hl slc">//bit1=1: Coherent Mode ( for DVI/HDMI mode )</span>
  UCHAR fDualLinkConnector<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>       <span class="hl slc">//bit0=1: Dual Link DVI connector</span>
<span class="hl ppc">#else</span>
  UCHAR fDualLinkConnector<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>       <span class="hl slc">//bit0=1: Dual Link DVI connector</span>
  UCHAR fCoherentMode<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>            <span class="hl slc">//bit1=1: Coherent Mode ( for DVI/HDMI mode )</span>
  UCHAR ucLinkSel<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>                <span class="hl slc">//bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E</span>
                                    <span class="hl slc">//    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F</span>
  UCHAR ucEncoderSel<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>             <span class="hl slc">//bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )</span>
  UCHAR fDPConnector<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>             <span class="hl slc">//bit4=0: DP connector  =1: None DP connector</span>
  UCHAR ucReserved<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>               
  UCHAR ucTransmitterSel<span class="hl opt">:</span><span class="hl num">2</span><span class="hl opt">;</span>         <span class="hl slc">//bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )</span>
                                    <span class="hl slc">//        =1 Dig Transmitter 2 ( Uniphy CD )</span>
                                    <span class="hl slc">//        =2 Dig Transmitter 3 ( Uniphy EF )</span>
<span class="hl ppc">#endif</span>
<span class="hl opt">}</span>ATOM_DIG_TRANSMITTER_CONFIG_V2<span class="hl opt">;</span>

<span class="hl slc">//ucConfig </span>
<span class="hl slc">//Bit0</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR			0x01</span>

<span class="hl slc">//Bit1</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT				          0x02</span>

<span class="hl slc">//Bit2</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK		        0x04</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_V2_LINKA  			            0x00			</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_V2_LINKB				            0x04</span>

<span class="hl slc">// Bit3</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK	        0x08</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER		          0x00</span>				<span class="hl slc">// only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER		          0x08</span>				<span class="hl slc">// only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP</span>
<span class="hl ppc"></span>
<span class="hl slc">// Bit4</span>
<span class="hl ppc">#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR			        0x10</span>

<span class="hl slc">// Bit7:6</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK     0xC0</span>
<span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1           	0x00</span>	<span class="hl slc">//AB</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2           	0x40</span>	<span class="hl slc">//CD</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3           	0x80</span>	<span class="hl slc">//EF</span>
<span class="hl ppc"></span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
<span class="hl opt">{</span>
	<span class="hl kwb">union</span>
	<span class="hl opt">{</span>
  USHORT usPixelClock<span class="hl opt">;</span>		<span class="hl slc">// in 10KHz; for bios convenient</span>
	USHORT usInitInfo<span class="hl opt">;</span>			<span class="hl slc">// when init uniphy,lower 8bit is used for connector type defined in objectid.h</span>
  ATOM_DP_VS_MODE asMode<span class="hl opt">;</span> <span class="hl slc">// DP Voltage swing mode</span>
	<span class="hl opt">};</span>
  ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig<span class="hl opt">;</span>
	UCHAR ucAction<span class="hl opt">;</span>				  <span class="hl slc">// define as ATOM_TRANSMITER_ACTION_XXX	                       </span>
  UCHAR ucReserved<span class="hl opt">[</span><span class="hl num">4</span><span class="hl opt">];</span>
<span class="hl opt">}</span>DIG_TRANSMITTER_CONTROL_PARAMETERS_V2<span class="hl opt">;</span>


<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by DAC1OuputControlTable</span>
<span class="hl slc">//                    DAC2OuputControlTable</span>
<span class="hl slc">//                    LVTMAOutputControlTable  (Before DEC30)</span>
<span class="hl slc">//                    TMDSAOutputControlTable  (Before DEC30)</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
<span class="hl opt">{</span>
  UCHAR  ucAction<span class="hl opt">;</span>                    <span class="hl slc">// Possible input:ATOM_ENABLE||ATOMDISABLE</span>
                                      <span class="hl slc">// When the display is LCD, in addition to above:</span>
                                      <span class="hl slc">// ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||</span>
                                      <span class="hl slc">// ATOM_LCD_SELFTEST_STOP</span>
                                      
  UCHAR  aucPadding<span class="hl opt">[</span><span class="hl num">3</span><span class="hl opt">];</span>               <span class="hl slc">// padding to DWORD aligned</span>
<span class="hl opt">}</span>DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS<span class="hl opt">;</span>

<span class="hl ppc">#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS</span>


<span class="hl ppc">#define CRT1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS </span>
<span class="hl ppc">#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION</span>

<span class="hl ppc">#define CRT2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS </span>
<span class="hl ppc">#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION</span>

<span class="hl ppc">#define CV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS</span>
<span class="hl ppc">#define CV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION</span>

<span class="hl ppc">#define TV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS</span>
<span class="hl ppc">#define TV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION</span>

<span class="hl ppc">#define DFP1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS</span>
<span class="hl ppc">#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION</span>

<span class="hl ppc">#define DFP2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS</span>
<span class="hl ppc">#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION</span>

<span class="hl ppc">#define LCD1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS</span>
<span class="hl ppc">#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION</span>

<span class="hl ppc">#define DVO_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS</span>
<span class="hl ppc">#define DVO_OUTPUT_CONTROL_PS_ALLOCATION   DIG_TRANSMITTER_CONTROL_PS_ALLOCATION</span>
<span class="hl ppc">#define DVO_OUTPUT_CONTROL_PARAMETERS_V3	 DIG_TRANSMITTER_CONTROL_PARAMETERS</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by BlankCRTCTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _BLANK_CRTC_PARAMETERS
<span class="hl opt">{</span>
  UCHAR  ucCRTC<span class="hl opt">;</span>                    	<span class="hl slc">// ATOM_CRTC1 or ATOM_CRTC2</span>
  UCHAR  ucBlanking<span class="hl opt">;</span>                  <span class="hl slc">// ATOM_BLANKING or ATOM_BLANKINGOFF</span>
  USHORT usBlackColorRCr<span class="hl opt">;</span>
  USHORT usBlackColorGY<span class="hl opt">;</span>
  USHORT usBlackColorBCb<span class="hl opt">;</span>
<span class="hl opt">}</span>BLANK_CRTC_PARAMETERS<span class="hl opt">;</span>
<span class="hl ppc">#define BLANK_CRTC_PS_ALLOCATION    BLANK_CRTC_PARAMETERS</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by EnableCRTCTable</span>
<span class="hl slc">//                    EnableCRTCMemReqTable</span>
<span class="hl slc">//                    UpdateCRTC_DoubleBufferRegistersTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ENABLE_CRTC_PARAMETERS
<span class="hl opt">{</span>
  UCHAR ucCRTC<span class="hl opt">;</span>                    	  <span class="hl slc">// ATOM_CRTC1 or ATOM_CRTC2</span>
  UCHAR ucEnable<span class="hl opt">;</span>                     <span class="hl slc">// ATOM_ENABLE or ATOM_DISABLE </span>
  UCHAR ucPadding<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>
<span class="hl opt">}</span>ENABLE_CRTC_PARAMETERS<span class="hl opt">;</span>
<span class="hl ppc">#define ENABLE_CRTC_PS_ALLOCATION   ENABLE_CRTC_PARAMETERS</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by SetCRTC_OverScanTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _SET_CRTC_OVERSCAN_PARAMETERS
<span class="hl opt">{</span>
  USHORT usOverscanRight<span class="hl opt">;</span>             <span class="hl slc">// right</span>
  USHORT usOverscanLeft<span class="hl opt">;</span>              <span class="hl slc">// left</span>
  USHORT usOverscanBottom<span class="hl opt">;</span>            <span class="hl slc">// bottom</span>
  USHORT usOverscanTop<span class="hl opt">;</span>               <span class="hl slc">// top</span>
  UCHAR  ucCRTC<span class="hl opt">;</span>                      <span class="hl slc">// ATOM_CRTC1 or ATOM_CRTC2</span>
  UCHAR  ucPadding<span class="hl opt">[</span><span class="hl num">3</span><span class="hl opt">];</span>
<span class="hl opt">}</span>SET_CRTC_OVERSCAN_PARAMETERS<span class="hl opt">;</span>
<span class="hl ppc">#define SET_CRTC_OVERSCAN_PS_ALLOCATION  SET_CRTC_OVERSCAN_PARAMETERS</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by SetCRTC_ReplicationTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _SET_CRTC_REPLICATION_PARAMETERS
<span class="hl opt">{</span>
  UCHAR ucH_Replication<span class="hl opt">;</span>              <span class="hl slc">// horizontal replication</span>
  UCHAR ucV_Replication<span class="hl opt">;</span>              <span class="hl slc">// vertical replication</span>
  UCHAR usCRTC<span class="hl opt">;</span>                       <span class="hl slc">// ATOM_CRTC1 or ATOM_CRTC2</span>
  UCHAR ucPadding<span class="hl opt">;</span>
<span class="hl opt">}</span>SET_CRTC_REPLICATION_PARAMETERS<span class="hl opt">;</span>
<span class="hl ppc">#define SET_CRTC_REPLICATION_PS_ALLOCATION  SET_CRTC_REPLICATION_PARAMETERS</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by SelectCRTC_SourceTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _SELECT_CRTC_SOURCE_PARAMETERS
<span class="hl opt">{</span>
  UCHAR ucCRTC<span class="hl opt">;</span>                    	  <span class="hl slc">// ATOM_CRTC1 or ATOM_CRTC2</span>
  UCHAR ucDevice<span class="hl opt">;</span>                     <span class="hl slc">// ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....</span>
  UCHAR ucPadding<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>
<span class="hl opt">}</span>SELECT_CRTC_SOURCE_PARAMETERS<span class="hl opt">;</span>
<span class="hl ppc">#define SELECT_CRTC_SOURCE_PS_ALLOCATION  SELECT_CRTC_SOURCE_PARAMETERS</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _SELECT_CRTC_SOURCE_PARAMETERS_V2
<span class="hl opt">{</span>
  UCHAR ucCRTC<span class="hl opt">;</span>                    	  <span class="hl slc">// ATOM_CRTC1 or ATOM_CRTC2</span>
  UCHAR ucEncoderID<span class="hl opt">;</span>                  <span class="hl slc">// DAC1/DAC2/TVOUT/DIG1/DIG2/DVO</span>
  UCHAR ucEncodeMode<span class="hl opt">;</span>									<span class="hl slc">// Encoding mode, only valid when using DIG1/DIG2/DVO</span>
  UCHAR ucPadding<span class="hl opt">;</span>
<span class="hl opt">}</span>SELECT_CRTC_SOURCE_PARAMETERS_V2<span class="hl opt">;</span>

<span class="hl slc">//ucEncoderID</span>
<span class="hl slc">//#define ASIC_INT_DAC1_ENCODER_ID    						0x00 </span>
<span class="hl slc">//#define ASIC_INT_TV_ENCODER_ID									0x02</span>
<span class="hl slc">//#define ASIC_INT_DIG1_ENCODER_ID								0x03</span>
<span class="hl slc">//#define ASIC_INT_DAC2_ENCODER_ID								0x04</span>
<span class="hl slc">//#define ASIC_EXT_TV_ENCODER_ID									0x06</span>
<span class="hl slc">//#define ASIC_INT_DVO_ENCODER_ID									0x07</span>
<span class="hl slc">//#define ASIC_INT_DIG2_ENCODER_ID								0x09</span>
<span class="hl slc">//#define ASIC_EXT_DIG_ENCODER_ID									0x05</span>

<span class="hl slc">//ucEncodeMode</span>
<span class="hl slc">//#define ATOM_ENCODER_MODE_DP										0</span>
<span class="hl slc">//#define ATOM_ENCODER_MODE_LVDS									1</span>
<span class="hl slc">//#define ATOM_ENCODER_MODE_DVI										2</span>
<span class="hl slc">//#define ATOM_ENCODER_MODE_HDMI									3</span>
<span class="hl slc">//#define ATOM_ENCODER_MODE_SDVO									4</span>
<span class="hl slc">//#define ATOM_ENCODER_MODE_TV										13</span>
<span class="hl slc">//#define ATOM_ENCODER_MODE_CV										14</span>
<span class="hl slc">//#define ATOM_ENCODER_MODE_CRT										15</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by SetPixelClockTable</span>
<span class="hl slc">//                    GetPixelClockTable </span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">//Major revision=1., Minor revision=1</span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _PIXEL_CLOCK_PARAMETERS
<span class="hl opt">{</span>
  USHORT usPixelClock<span class="hl opt">;</span>                <span class="hl slc">// in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)</span>
                                      <span class="hl slc">// 0 means disable PPLL</span>
  USHORT usRefDiv<span class="hl opt">;</span>                    <span class="hl slc">// Reference divider</span>
  USHORT usFbDiv<span class="hl opt">;</span>                     <span class="hl slc">// feedback divider</span>
  UCHAR  ucPostDiv<span class="hl opt">;</span>                   <span class="hl slc">// post divider	</span>
  UCHAR  ucFracFbDiv<span class="hl opt">;</span>                 <span class="hl slc">// fractional feedback divider</span>
  UCHAR  ucPpll<span class="hl opt">;</span>                      <span class="hl slc">// ATOM_PPLL1 or ATOM_PPL2</span>
  UCHAR  ucRefDivSrc<span class="hl opt">;</span>                 <span class="hl slc">// ATOM_PJITTER or ATO_NONPJITTER</span>
  UCHAR  ucCRTC<span class="hl opt">;</span>                      <span class="hl slc">// Which CRTC uses this Ppll</span>
  UCHAR  ucPadding<span class="hl opt">;</span>
<span class="hl opt">}</span>PIXEL_CLOCK_PARAMETERS<span class="hl opt">;</span>

<span class="hl slc">//Major revision=1., Minor revision=2, add ucMiscIfno</span>
<span class="hl slc">//ucMiscInfo:</span>
<span class="hl ppc">#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1</span>
<span class="hl ppc">#define MISC_DEVICE_INDEX_MASK        0xF0</span>
<span class="hl ppc">#define MISC_DEVICE_INDEX_SHIFT       4</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _PIXEL_CLOCK_PARAMETERS_V2
<span class="hl opt">{</span>
  USHORT usPixelClock<span class="hl opt">;</span>                <span class="hl slc">// in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)</span>
                                      <span class="hl slc">// 0 means disable PPLL</span>
  USHORT usRefDiv<span class="hl opt">;</span>                    <span class="hl slc">// Reference divider</span>
  USHORT usFbDiv<span class="hl opt">;</span>                     <span class="hl slc">// feedback divider</span>
  UCHAR  ucPostDiv<span class="hl opt">;</span>                   <span class="hl slc">// post divider	</span>
  UCHAR  ucFracFbDiv<span class="hl opt">;</span>                 <span class="hl slc">// fractional feedback divider</span>
  UCHAR  ucPpll<span class="hl opt">;</span>                      <span class="hl slc">// ATOM_PPLL1 or ATOM_PPL2</span>
  UCHAR  ucRefDivSrc<span class="hl opt">;</span>                 <span class="hl slc">// ATOM_PJITTER or ATO_NONPJITTER</span>
  UCHAR  ucCRTC<span class="hl opt">;</span>                      <span class="hl slc">// Which CRTC uses this Ppll</span>
  UCHAR  ucMiscInfo<span class="hl opt">;</span>                  <span class="hl slc">// Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog</span>
<span class="hl opt">}</span>PIXEL_CLOCK_PARAMETERS_V2<span class="hl opt">;</span>

<span class="hl slc">//Major revision=1., Minor revision=3, structure/definition change</span>
<span class="hl slc">//ucEncoderMode:</span>
<span class="hl slc">//ATOM_ENCODER_MODE_DP</span>
<span class="hl slc">//ATOM_ENOCDER_MODE_LVDS</span>
<span class="hl slc">//ATOM_ENOCDER_MODE_DVI</span>
<span class="hl slc">//ATOM_ENOCDER_MODE_HDMI</span>
<span class="hl slc">//ATOM_ENOCDER_MODE_SDVO</span>
<span class="hl slc">//ATOM_ENCODER_MODE_TV										13</span>
<span class="hl slc">//ATOM_ENCODER_MODE_CV										14</span>
<span class="hl slc">//ATOM_ENCODER_MODE_CRT										15</span>

<span class="hl slc">//ucDVOConfig</span>
<span class="hl slc">//#define DVO_ENCODER_CONFIG_RATE_SEL							0x01</span>
<span class="hl slc">//#define DVO_ENCODER_CONFIG_DDR_SPEED						0x00</span>
<span class="hl slc">//#define DVO_ENCODER_CONFIG_SDR_SPEED						0x01</span>
<span class="hl slc">//#define DVO_ENCODER_CONFIG_OUTPUT_SEL						0x0c</span>
<span class="hl slc">//#define DVO_ENCODER_CONFIG_LOW12BIT							0x00</span>
<span class="hl slc">//#define DVO_ENCODER_CONFIG_UPPER12BIT						0x04</span>
<span class="hl slc">//#define DVO_ENCODER_CONFIG_24BIT								0x08</span>

<span class="hl slc">//ucMiscInfo: also changed, see below</span>
<span class="hl ppc">#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL						0x01</span>
<span class="hl ppc">#define PIXEL_CLOCK_MISC_VGA_MODE										0x02</span>
<span class="hl ppc">#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK							0x04</span>
<span class="hl ppc">#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1							0x00</span>
<span class="hl ppc">#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2							0x04</span>
<span class="hl ppc">#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK			0x08</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _PIXEL_CLOCK_PARAMETERS_V3
<span class="hl opt">{</span>
  USHORT usPixelClock<span class="hl opt">;</span>                <span class="hl slc">// in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)</span>
                                      <span class="hl slc">// 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.</span>
  USHORT usRefDiv<span class="hl opt">;</span>                    <span class="hl slc">// Reference divider</span>
  USHORT usFbDiv<span class="hl opt">;</span>                     <span class="hl slc">// feedback divider</span>
  UCHAR  ucPostDiv<span class="hl opt">;</span>                   <span class="hl slc">// post divider	</span>
  UCHAR  ucFracFbDiv<span class="hl opt">;</span>                 <span class="hl slc">// fractional feedback divider</span>
  UCHAR  ucPpll<span class="hl opt">;</span>                      <span class="hl slc">// ATOM_PPLL1 or ATOM_PPL2</span>
  UCHAR  ucTransmitterId<span class="hl opt">;</span>             <span class="hl slc">// graphic encoder id defined in objectId.h</span>
	<span class="hl kwb">union</span>
	<span class="hl opt">{</span>
  UCHAR  ucEncoderMode<span class="hl opt">;</span>               <span class="hl slc">// encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/</span>
	UCHAR  ucDVOConfig<span class="hl opt">;</span>									<span class="hl slc">// when use DVO, need to know SDR/DDR, 12bit or 24bit</span>
	<span class="hl opt">};</span>
  UCHAR  ucMiscInfo<span class="hl opt">;</span>                  <span class="hl slc">// bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel</span>
                                      <span class="hl slc">// bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source</span>
<span class="hl opt">}</span>PIXEL_CLOCK_PARAMETERS_V3<span class="hl opt">;</span>

<span class="hl ppc">#define PIXEL_CLOCK_PARAMETERS_LAST			PIXEL_CLOCK_PARAMETERS_V2</span>
<span class="hl ppc">#define GET_PIXEL_CLOCK_PS_ALLOCATION		PIXEL_CLOCK_PARAMETERS_LAST</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by AdjustDisplayPllTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ADJUST_DISPLAY_PLL_PARAMETERS
<span class="hl opt">{</span>
	USHORT usPixelClock<span class="hl opt">;</span>
	UCHAR ucTransmitterID<span class="hl opt">;</span>
	UCHAR ucEncodeMode<span class="hl opt">;</span>
	<span class="hl kwb">union</span>
	<span class="hl opt">{</span>
		UCHAR ucDVOConfig<span class="hl opt">;</span>									<span class="hl slc">//if DVO, need passing link rate and output 12bitlow or 24bit</span>
		UCHAR ucConfig<span class="hl opt">;</span>											<span class="hl slc">//if none DVO, not defined yet</span>
	<span class="hl opt">};</span>
	UCHAR ucReserved<span class="hl opt">[</span><span class="hl num">3</span><span class="hl opt">];</span>
<span class="hl opt">}</span>ADJUST_DISPLAY_PLL_PARAMETERS<span class="hl opt">;</span>

<span class="hl ppc">#define ADJUST_DISPLAY_CONFIG_SS_ENABLE       0x10</span>

<span class="hl ppc">#define ADJUST_DISPLAY_PLL_PS_ALLOCATION			ADJUST_DISPLAY_PLL_PARAMETERS</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by EnableYUVTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ENABLE_YUV_PARAMETERS
<span class="hl opt">{</span>
  UCHAR ucEnable<span class="hl opt">;</span>                     <span class="hl slc">// ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)</span>
  UCHAR ucCRTC<span class="hl opt">;</span>                       <span class="hl slc">// Which CRTC needs this YUV or RGB format</span>
  UCHAR ucPadding<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>
<span class="hl opt">}</span>ENABLE_YUV_PARAMETERS<span class="hl opt">;</span>
<span class="hl ppc">#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by GetMemoryClockTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _GET_MEMORY_CLOCK_PARAMETERS
<span class="hl opt">{</span>
  ULONG ulReturnMemoryClock<span class="hl opt">;</span>          <span class="hl slc">// current memory speed in 10KHz unit</span>
<span class="hl opt">}</span> GET_MEMORY_CLOCK_PARAMETERS<span class="hl opt">;</span>
<span class="hl ppc">#define GET_MEMORY_CLOCK_PS_ALLOCATION  GET_MEMORY_CLOCK_PARAMETERS</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by GetEngineClockTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _GET_ENGINE_CLOCK_PARAMETERS
<span class="hl opt">{</span>
  ULONG ulReturnEngineClock<span class="hl opt">;</span>          <span class="hl slc">// current engine speed in 10KHz unit</span>
<span class="hl opt">}</span> GET_ENGINE_CLOCK_PARAMETERS<span class="hl opt">;</span>
<span class="hl ppc">#define GET_ENGINE_CLOCK_PS_ALLOCATION  GET_ENGINE_CLOCK_PARAMETERS</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Following Structures and constant may be obsolete</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">//Maxium 8 bytes,the data read in will be placed in the parameter space.</span>
<span class="hl slc">//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed</span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
<span class="hl opt">{</span>
  USHORT    usPrescale<span class="hl opt">;</span>         <span class="hl slc">//Ratio between Engine clock and I2C clock</span>
  USHORT    usVRAMAddress<span class="hl opt">;</span>      <span class="hl slc">//Adress in Frame Buffer where to pace raw EDID</span>
  USHORT    usStatus<span class="hl opt">;</span>           <span class="hl slc">//When use output: lower byte EDID checksum, high byte hardware status</span>
                                <span class="hl slc">//WHen use input:  lower byte as &apos;byte to read&apos;:currently limited to 128byte or 1byte</span>
  UCHAR     ucSlaveAddr<span class="hl opt">;</span>        <span class="hl slc">//Read from which slave</span>
  UCHAR     ucLineNumber<span class="hl opt">;</span>       <span class="hl slc">//Read from which HW assisted line</span>
<span class="hl opt">}</span>READ_EDID_FROM_HW_I2C_DATA_PARAMETERS<span class="hl opt">;</span>
<span class="hl ppc">#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION  READ_EDID_FROM_HW_I2C_DATA_PARAMETERS</span>


<span class="hl ppc">#define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE                  0</span>
<span class="hl ppc">#define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES              1</span>
<span class="hl ppc">#define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK       2</span>
<span class="hl ppc">#define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK  3</span>
<span class="hl ppc">#define  ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK       4</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
<span class="hl opt">{</span>
  USHORT    usPrescale<span class="hl opt">;</span>         <span class="hl slc">//Ratio between Engine clock and I2C clock</span>
  USHORT    usByteOffset<span class="hl opt">;</span>       <span class="hl slc">//Write to which byte</span>
                                <span class="hl slc">//Upper portion of usByteOffset is Format of data </span>
                                <span class="hl slc">//1bytePS+offsetPS</span>
                                <span class="hl slc">//2bytesPS+offsetPS</span>
                                <span class="hl slc">//blockID+offsetPS</span>
                                <span class="hl slc">//blockID+offsetID</span>
                                <span class="hl slc">//blockID+counterID+offsetID</span>
  UCHAR     ucData<span class="hl opt">;</span>             <span class="hl slc">//PS data1</span>
  UCHAR     ucStatus<span class="hl opt">;</span>           <span class="hl slc">//Status byte 1=success, 2=failure, Also is used as PS data2</span>
  UCHAR     ucSlaveAddr<span class="hl opt">;</span>        <span class="hl slc">//Write to which slave</span>
  UCHAR     ucLineNumber<span class="hl opt">;</span>       <span class="hl slc">//Write from which HW assisted line</span>
<span class="hl opt">}</span>WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS<span class="hl opt">;</span>

<span class="hl ppc">#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION  WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _SET_UP_HW_I2C_DATA_PARAMETERS
<span class="hl opt">{</span>
  USHORT    usPrescale<span class="hl opt">;</span>         <span class="hl slc">//Ratio between Engine clock and I2C clock</span>
  UCHAR     ucSlaveAddr<span class="hl opt">;</span>        <span class="hl slc">//Write to which slave</span>
  UCHAR     ucLineNumber<span class="hl opt">;</span>       <span class="hl slc">//Write from which HW assisted line</span>
<span class="hl opt">}</span>SET_UP_HW_I2C_DATA_PARAMETERS<span class="hl opt">;</span>


<span class="hl com">/**************************************************************************/</span>
<span class="hl ppc">#define SPEED_FAN_CONTROL_PS_ALLOCATION   WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by PowerConnectorDetectionTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>	_POWER_CONNECTOR_DETECTION_PARAMETERS
<span class="hl opt">{</span>
  UCHAR   ucPowerConnectorStatus<span class="hl opt">;</span>      <span class="hl slc">//Used for return value 0: detected, 1:not detected</span>
	UCHAR   ucPwrBehaviorId<span class="hl opt">;</span>							
	USHORT	usPwrBudget<span class="hl opt">;</span>								 <span class="hl slc">//how much power currently boot to in unit of watt</span>
<span class="hl opt">}</span>POWER_CONNECTOR_DETECTION_PARAMETERS<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> POWER_CONNECTOR_DETECTION_PS_ALLOCATION
<span class="hl opt">{</span>                               
  UCHAR   ucPowerConnectorStatus<span class="hl opt">;</span>      <span class="hl slc">//Used for return value 0: detected, 1:not detected</span>
	UCHAR   ucReserved<span class="hl opt">;</span>
	USHORT	usPwrBudget<span class="hl opt">;</span>								 <span class="hl slc">//how much power currently boot to in unit of watt</span>
  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved<span class="hl opt">;</span>
<span class="hl opt">}</span>POWER_CONNECTOR_DETECTION_PS_ALLOCATION<span class="hl opt">;</span>

<span class="hl com">/****************************LVDS SS Command Table Definitions**********************/</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by EnableSpreadSpectrumOnPPLLTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>	_ENABLE_LVDS_SS_PARAMETERS
<span class="hl opt">{</span>
  USHORT  usSpreadSpectrumPercentage<span class="hl opt">;</span>       
  UCHAR   ucSpreadSpectrumType<span class="hl opt">;</span>           <span class="hl slc">//Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD</span>
  UCHAR   ucSpreadSpectrumStepSize_Delay<span class="hl opt">;</span> <span class="hl slc">//bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY</span>
  UCHAR   ucEnable<span class="hl opt">;</span>                       <span class="hl slc">//ATOM_ENABLE or ATOM_DISABLE</span>
  UCHAR   ucPadding<span class="hl opt">[</span><span class="hl num">3</span><span class="hl opt">];</span>
<span class="hl opt">}</span>ENABLE_LVDS_SS_PARAMETERS<span class="hl opt">;</span>

<span class="hl slc">//ucTableFormatRevision=1,ucTableContentRevision=2</span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>	_ENABLE_LVDS_SS_PARAMETERS_V2
<span class="hl opt">{</span>
  USHORT  usSpreadSpectrumPercentage<span class="hl opt">;</span>       
  UCHAR   ucSpreadSpectrumType<span class="hl opt">;</span>           <span class="hl slc">//Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD</span>
  UCHAR   ucSpreadSpectrumStep<span class="hl opt">;</span>           <span class="hl slc">//</span>
  UCHAR   ucEnable<span class="hl opt">;</span>                       <span class="hl slc">//ATOM_ENABLE or ATOM_DISABLE</span>
  UCHAR   ucSpreadSpectrumDelay<span class="hl opt">;</span>
  UCHAR   ucSpreadSpectrumRange<span class="hl opt">;</span>
  UCHAR   ucPadding<span class="hl opt">;</span>
<span class="hl opt">}</span>ENABLE_LVDS_SS_PARAMETERS_V2<span class="hl opt">;</span>

<span class="hl slc">//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.</span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>	_ENABLE_SPREAD_SPECTRUM_ON_PPLL
<span class="hl opt">{</span>
  USHORT  usSpreadSpectrumPercentage<span class="hl opt">;</span>
  UCHAR   ucSpreadSpectrumType<span class="hl opt">;</span>           <span class="hl slc">// Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD</span>
  UCHAR   ucSpreadSpectrumStep<span class="hl opt">;</span>           <span class="hl slc">//</span>
  UCHAR   ucEnable<span class="hl opt">;</span>                       <span class="hl slc">// ATOM_ENABLE or ATOM_DISABLE</span>
  UCHAR   ucSpreadSpectrumDelay<span class="hl opt">;</span>
  UCHAR   ucSpreadSpectrumRange<span class="hl opt">;</span>
  UCHAR   ucPpll<span class="hl opt">;</span>												  <span class="hl slc">// ATOM_PPLL1/ATOM_PPLL2</span>
<span class="hl opt">}</span>ENABLE_SPREAD_SPECTRUM_ON_PPLL<span class="hl opt">;</span>

<span class="hl ppc">#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION  ENABLE_SPREAD_SPECTRUM_ON_PPLL</span>

<span class="hl com">/**************************************************************************/</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _SET_PIXEL_CLOCK_PS_ALLOCATION
<span class="hl opt">{</span>
  PIXEL_CLOCK_PARAMETERS sPCLKInput<span class="hl opt">;</span>
  ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved<span class="hl opt">;</span><span class="hl slc">//Caller doesn&apos;t need to init this portion </span>
<span class="hl opt">}</span>SET_PIXEL_CLOCK_PS_ALLOCATION<span class="hl opt">;</span>

<span class="hl ppc">#define ENABLE_VGA_RENDER_PS_ALLOCATION   SET_PIXEL_CLOCK_PS_ALLOCATION</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by ###</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>	_MEMORY_TRAINING_PARAMETERS
<span class="hl opt">{</span>
  ULONG ulTargetMemoryClock<span class="hl opt">;</span>          <span class="hl slc">//In 10Khz unit</span>
<span class="hl opt">}</span>MEMORY_TRAINING_PARAMETERS<span class="hl opt">;</span>
<span class="hl ppc">#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS</span>


<span class="hl com">/****************************LVDS and other encoder command table definitions **********************/</span>


<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by LVDSEncoderControlTable   (Before DCE30)</span>
<span class="hl slc">//                    LVTMAEncoderControlTable  (Before DCE30)</span>
<span class="hl slc">//                    TMDSAEncoderControlTable  (Before DCE30)</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _LVDS_ENCODER_CONTROL_PARAMETERS
<span class="hl opt">{</span>
  USHORT usPixelClock<span class="hl opt">;</span>  <span class="hl slc">// in 10KHz; for bios convenient</span>
  UCHAR  ucMisc<span class="hl opt">;</span>        <span class="hl slc">// bit0=0: Enable single link</span>
                        <span class="hl slc">//     =1: Enable dual link</span>
                        <span class="hl slc">// Bit1=0: 666RGB</span>
                        <span class="hl slc">//     =1: 888RGB</span>
  UCHAR  ucAction<span class="hl opt">;</span>      <span class="hl slc">// 0: turn off encoder</span>
                        <span class="hl slc">// 1: setup and turn on encoder</span>
<span class="hl opt">}</span>LVDS_ENCODER_CONTROL_PARAMETERS<span class="hl opt">;</span>

<span class="hl ppc">#define LVDS_ENCODER_CONTROL_PS_ALLOCATION  LVDS_ENCODER_CONTROL_PARAMETERS</span>
   
<span class="hl ppc">#define TMDS1_ENCODER_CONTROL_PARAMETERS    LVDS_ENCODER_CONTROL_PARAMETERS</span>
<span class="hl ppc">#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS</span>

<span class="hl ppc">#define TMDS2_ENCODER_CONTROL_PARAMETERS    TMDS1_ENCODER_CONTROL_PARAMETERS</span>
<span class="hl ppc">#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS</span>


<span class="hl slc">//ucTableFormatRevision=1,ucTableContentRevision=2</span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _LVDS_ENCODER_CONTROL_PARAMETERS_V2
<span class="hl opt">{</span>
  USHORT usPixelClock<span class="hl opt">;</span>  <span class="hl slc">// in 10KHz; for bios convenient</span>
  UCHAR  ucMisc<span class="hl opt">;</span>        <span class="hl slc">// see PANEL_ENCODER_MISC_xx defintions below</span>
  UCHAR  ucAction<span class="hl opt">;</span>      <span class="hl slc">// 0: turn off encoder</span>
                        <span class="hl slc">// 1: setup and turn on encoder</span>
  UCHAR  ucTruncate<span class="hl opt">;</span>    <span class="hl slc">// bit0=0: Disable truncate</span>
                        <span class="hl slc">//     =1: Enable truncate</span>
                        <span class="hl slc">// bit4=0: 666RGB</span>
                        <span class="hl slc">//     =1: 888RGB</span>
  UCHAR  ucSpatial<span class="hl opt">;</span>     <span class="hl slc">// bit0=0: Disable spatial dithering</span>
                        <span class="hl slc">//     =1: Enable spatial dithering</span>
                        <span class="hl slc">// bit4=0: 666RGB</span>
                        <span class="hl slc">//     =1: 888RGB</span>
  UCHAR  ucTemporal<span class="hl opt">;</span>    <span class="hl slc">// bit0=0: Disable temporal dithering</span>
                        <span class="hl slc">//     =1: Enable temporal dithering</span>
                        <span class="hl slc">// bit4=0: 666RGB</span>
                        <span class="hl slc">//     =1: 888RGB</span>
                        <span class="hl slc">// bit5=0: Gray level 2</span>
                        <span class="hl slc">//     =1: Gray level 4</span>
  UCHAR  ucFRC<span class="hl opt">;</span>         <span class="hl slc">// bit4=0: 25FRC_SEL pattern E</span>
                        <span class="hl slc">//     =1: 25FRC_SEL pattern F</span>
                        <span class="hl slc">// bit6:5=0: 50FRC_SEL pattern A</span>
                        <span class="hl slc">//       =1: 50FRC_SEL pattern B</span>
                        <span class="hl slc">//       =2: 50FRC_SEL pattern C</span>
                        <span class="hl slc">//       =3: 50FRC_SEL pattern D</span>
                        <span class="hl slc">// bit7=0: 75FRC_SEL pattern E</span>
                        <span class="hl slc">//     =1: 75FRC_SEL pattern F</span>
<span class="hl opt">}</span>LVDS_ENCODER_CONTROL_PARAMETERS_V2<span class="hl opt">;</span>

<span class="hl ppc">#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2</span>
   
<span class="hl ppc">#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2    LVDS_ENCODER_CONTROL_PARAMETERS_V2</span>
<span class="hl ppc">#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2</span>
  
<span class="hl ppc">#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2    TMDS1_ENCODER_CONTROL_PARAMETERS_V2</span>
<span class="hl ppc">#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2</span>

<span class="hl ppc">#define LVDS_ENCODER_CONTROL_PARAMETERS_V3     LVDS_ENCODER_CONTROL_PARAMETERS_V2</span>
<span class="hl ppc">#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3  LVDS_ENCODER_CONTROL_PARAMETERS_V3</span>

<span class="hl ppc">#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3</span>
<span class="hl ppc">#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3</span>

<span class="hl ppc">#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3</span>
<span class="hl ppc">#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by ###</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
<span class="hl opt">{</span>                               
  UCHAR    ucEnable<span class="hl opt">;</span>            <span class="hl slc">// Enable or Disable External TMDS encoder</span>
  UCHAR    ucMisc<span class="hl opt">;</span>              <span class="hl slc">// Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}</span>
  UCHAR    ucPadding<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>
<span class="hl opt">}</span>ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
<span class="hl opt">{</span>                               
  ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS    sXTmdsEncoder<span class="hl opt">;</span>
  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION   sReserved<span class="hl opt">;</span>     <span class="hl slc">//Caller doesn&apos;t need to init this portion</span>
<span class="hl opt">}</span>ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION<span class="hl opt">;</span>

<span class="hl ppc">#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
<span class="hl opt">{</span>                               
  ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2    sXTmdsEncoder<span class="hl opt">;</span>
  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved<span class="hl opt">;</span>     <span class="hl slc">//Caller doesn&apos;t need to init this portion</span>
<span class="hl opt">}</span>ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
<span class="hl opt">{</span>
  DIG_ENCODER_CONTROL_PARAMETERS            sDigEncoder<span class="hl opt">;</span>
  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved<span class="hl opt">;</span>
<span class="hl opt">}</span>EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by DVOEncoderControlTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">//ucTableFormatRevision=1,ucTableContentRevision=3</span>

<span class="hl slc">//ucDVOConfig:</span>
<span class="hl ppc">#define DVO_ENCODER_CONFIG_RATE_SEL							0x01</span>
<span class="hl ppc">#define DVO_ENCODER_CONFIG_DDR_SPEED						0x00</span>
<span class="hl ppc">#define DVO_ENCODER_CONFIG_SDR_SPEED						0x01</span>
<span class="hl ppc">#define DVO_ENCODER_CONFIG_OUTPUT_SEL						0x0c</span>
<span class="hl ppc">#define DVO_ENCODER_CONFIG_LOW12BIT							0x00</span>
<span class="hl ppc">#define DVO_ENCODER_CONFIG_UPPER12BIT						0x04</span>
<span class="hl ppc">#define DVO_ENCODER_CONFIG_24BIT								0x08</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _DVO_ENCODER_CONTROL_PARAMETERS_V3
<span class="hl opt">{</span>
  USHORT usPixelClock<span class="hl opt">;</span> 
  UCHAR  ucDVOConfig<span class="hl opt">;</span>
  UCHAR  ucAction<span class="hl opt">;</span>														<span class="hl slc">//ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT</span>
  UCHAR  ucReseved<span class="hl opt">[</span><span class="hl num">4</span><span class="hl opt">];</span>
<span class="hl opt">}</span>DVO_ENCODER_CONTROL_PARAMETERS_V3<span class="hl opt">;</span>
<span class="hl ppc">#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3	DVO_ENCODER_CONTROL_PARAMETERS_V3</span>

<span class="hl slc">//ucTableFormatRevision=1</span>
<span class="hl slc">//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for </span>
<span class="hl slc">// bit1=0: non-coherent mode</span>
<span class="hl slc">//     =1: coherent mode</span>

<span class="hl slc">//==========================================================================================</span>
<span class="hl slc">//Only change is here next time when changing encoder parameter definitions again!</span>
<span class="hl ppc">#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST     LVDS_ENCODER_CONTROL_PARAMETERS_V3</span>
<span class="hl ppc">#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST  LVDS_ENCODER_CONTROL_PARAMETERS_LAST</span>

<span class="hl ppc">#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3</span>
<span class="hl ppc">#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST</span>

<span class="hl ppc">#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3</span>
<span class="hl ppc">#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST</span>

<span class="hl ppc">#define DVO_ENCODER_CONTROL_PARAMETERS_LAST      DVO_ENCODER_CONTROL_PARAMETERS</span>
<span class="hl ppc">#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST   DVO_ENCODER_CONTROL_PS_ALLOCATION</span>

<span class="hl slc">//==========================================================================================</span>
<span class="hl ppc">#define PANEL_ENCODER_MISC_DUAL                0x01</span>
<span class="hl ppc">#define PANEL_ENCODER_MISC_COHERENT            0x02</span>
<span class="hl ppc">#define	PANEL_ENCODER_MISC_TMDS_LINKB					 0x04</span>
<span class="hl ppc">#define	PANEL_ENCODER_MISC_HDMI_TYPE					 0x08</span>

<span class="hl ppc">#define PANEL_ENCODER_ACTION_DISABLE           ATOM_DISABLE</span>
<span class="hl ppc">#define PANEL_ENCODER_ACTION_ENABLE            ATOM_ENABLE</span>
<span class="hl ppc">#define PANEL_ENCODER_ACTION_COHERENTSEQ       (ATOM_ENABLE+1)</span>

<span class="hl ppc">#define PANEL_ENCODER_TRUNCATE_EN              0x01</span>
<span class="hl ppc">#define PANEL_ENCODER_TRUNCATE_DEPTH           0x10</span>
<span class="hl ppc">#define PANEL_ENCODER_SPATIAL_DITHER_EN        0x01</span>
<span class="hl ppc">#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH     0x10</span>
<span class="hl ppc">#define PANEL_ENCODER_TEMPORAL_DITHER_EN       0x01</span>
<span class="hl ppc">#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH    0x10</span>
<span class="hl ppc">#define PANEL_ENCODER_TEMPORAL_LEVEL_4         0x20</span>
<span class="hl ppc">#define PANEL_ENCODER_25FRC_MASK               0x10</span>
<span class="hl ppc">#define PANEL_ENCODER_25FRC_E                  0x00</span>
<span class="hl ppc">#define PANEL_ENCODER_25FRC_F                  0x10</span>
<span class="hl ppc">#define PANEL_ENCODER_50FRC_MASK               0x60</span>
<span class="hl ppc">#define PANEL_ENCODER_50FRC_A                  0x00</span>
<span class="hl ppc">#define PANEL_ENCODER_50FRC_B                  0x20</span>
<span class="hl ppc">#define PANEL_ENCODER_50FRC_C                  0x40</span>
<span class="hl ppc">#define PANEL_ENCODER_50FRC_D                  0x60</span>
<span class="hl ppc">#define PANEL_ENCODER_75FRC_MASK               0x80</span>
<span class="hl ppc">#define PANEL_ENCODER_75FRC_E                  0x00</span>
<span class="hl ppc">#define PANEL_ENCODER_75FRC_F                  0x80</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by SetVoltageTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl ppc">#define SET_VOLTAGE_TYPE_ASIC_VDDC             1</span>
<span class="hl ppc">#define SET_VOLTAGE_TYPE_ASIC_MVDDC            2</span>
<span class="hl ppc">#define SET_VOLTAGE_TYPE_ASIC_MVDDQ            3</span>
<span class="hl ppc">#define SET_VOLTAGE_TYPE_ASIC_VDDCI            4</span>
<span class="hl ppc">#define SET_VOLTAGE_INIT_MODE                  5</span>
<span class="hl ppc">#define SET_VOLTAGE_GET_MAX_VOLTAGE            6</span>					<span class="hl slc">//Gets the Max. voltage for the soldered Asic</span>
<span class="hl ppc"></span>
<span class="hl ppc">#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE       0x1</span>
<span class="hl ppc">#define SET_ASIC_VOLTAGE_MODE_SOURCE_A         0x2</span>
<span class="hl ppc">#define SET_ASIC_VOLTAGE_MODE_SOURCE_B         0x4</span>

<span class="hl ppc">#define	SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE      0x0</span>
<span class="hl ppc">#define	SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL      0x1	</span>
<span class="hl ppc">#define	SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK     0x2</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>	_SET_VOLTAGE_PARAMETERS
<span class="hl opt">{</span>
  UCHAR    ucVoltageType<span class="hl opt">;</span>               <span class="hl slc">// To tell which voltage to set up, VDDC/MVDDC/MVDDQ</span>
  UCHAR    ucVoltageMode<span class="hl opt">;</span>               <span class="hl slc">// To set all, to set source A or source B or ...</span>
  UCHAR    ucVoltageIndex<span class="hl opt">;</span>              <span class="hl slc">// An index to tell which voltage level</span>
  UCHAR    ucReserved<span class="hl opt">;</span>          
<span class="hl opt">}</span>SET_VOLTAGE_PARAMETERS<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>	_SET_VOLTAGE_PARAMETERS_V2
<span class="hl opt">{</span>
  UCHAR    ucVoltageType<span class="hl opt">;</span>               <span class="hl slc">// To tell which voltage to set up, VDDC/MVDDC/MVDDQ</span>
  UCHAR    ucVoltageMode<span class="hl opt">;</span>               <span class="hl slc">// Not used, maybe use for state machine for differen power mode</span>
  USHORT   usVoltageLevel<span class="hl opt">;</span>              <span class="hl slc">// real voltage level</span>
<span class="hl opt">}</span>SET_VOLTAGE_PARAMETERS_V2<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _SET_VOLTAGE_PS_ALLOCATION
<span class="hl opt">{</span>
  SET_VOLTAGE_PARAMETERS sASICSetVoltage<span class="hl opt">;</span>
  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved<span class="hl opt">;</span>
<span class="hl opt">}</span>SET_VOLTAGE_PS_ALLOCATION<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used by TVEncoderControlTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _TV_ENCODER_CONTROL_PARAMETERS
<span class="hl opt">{</span>
  USHORT usPixelClock<span class="hl opt">;</span>                <span class="hl slc">// in 10KHz; for bios convenient</span>
  UCHAR  ucTvStandard<span class="hl opt">;</span>                <span class="hl slc">// See definition &quot;ATOM_TV_NTSC ...&quot;</span>
  UCHAR  ucAction<span class="hl opt">;</span>                    <span class="hl slc">// 0: turn off encoder</span>
                                      <span class="hl slc">// 1: setup and turn on encoder</span>
<span class="hl opt">}</span>TV_ENCODER_CONTROL_PARAMETERS<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _TV_ENCODER_CONTROL_PS_ALLOCATION
<span class="hl opt">{</span>
  TV_ENCODER_CONTROL_PARAMETERS sTVEncoder<span class="hl opt">;</span>          
  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved<span class="hl opt">;</span> <span class="hl slc">// Don&apos;t set this one</span>
<span class="hl opt">}</span>TV_ENCODER_CONTROL_PS_ALLOCATION<span class="hl opt">;</span>

<span class="hl slc">//==============================Data Table Portion====================================</span>

<span class="hl ppc">#ifdef	UEFI_BUILD</span>
	<span class="hl ppc">#define	UTEMP	USHORT</span>
	<span class="hl ppc">#define	USHORT	void*</span>
<span class="hl ppc">#endif</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structure used in Data.mtb</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_MASTER_LIST_OF_DATA_TABLES
<span class="hl opt">{</span>
  USHORT        UtilityPipeLine<span class="hl opt">;</span>	        <span class="hl slc">// Offest for the utility to get parser info,Don&apos;t change this position!</span>
  USHORT        MultimediaCapabilityInfo<span class="hl opt">;</span> <span class="hl slc">// Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios </span>
  USHORT        MultimediaConfigInfo<span class="hl opt">;</span>     <span class="hl slc">// Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios</span>
  USHORT        StandardVESA_Timing<span class="hl opt">;</span>      <span class="hl slc">// Only used by Bios</span>
  USHORT        FirmwareInfo<span class="hl opt">;</span>             <span class="hl slc">// Shared by various SW components,latest version 1.4</span>
  USHORT        DAC_Info<span class="hl opt">;</span>                 <span class="hl slc">// Will be obsolete from R600</span>
  USHORT        LVDS_Info<span class="hl opt">;</span>                <span class="hl slc">// Shared by various SW components,latest version 1.1 </span>
  USHORT        TMDS_Info<span class="hl opt">;</span>                <span class="hl slc">// Will be obsolete from R600</span>
  USHORT        AnalogTV_Info<span class="hl opt">;</span>            <span class="hl slc">// Shared by various SW components,latest version 1.1 </span>
  USHORT        SupportedDevicesInfo<span class="hl opt">;</span>     <span class="hl slc">// Will be obsolete from R600</span>
  USHORT        GPIO_I2C_Info<span class="hl opt">;</span>            <span class="hl slc">// Shared by various SW components,latest version 1.2 will be used from R600           </span>
  USHORT        VRAM_UsageByFirmware<span class="hl opt">;</span>     <span class="hl slc">// Shared by various SW components,latest version 1.3 will be used from R600</span>
  USHORT        GPIO_Pin_LUT<span class="hl opt">;</span>             <span class="hl slc">// Shared by various SW components,latest version 1.1</span>
  USHORT        VESA_ToInternalModeLUT<span class="hl opt">;</span>   <span class="hl slc">// Only used by Bios</span>
  USHORT        ComponentVideoInfo<span class="hl opt">;</span>       <span class="hl slc">// Shared by various SW components,latest version 2.1 will be used from R600</span>
  USHORT        PowerPlayInfo<span class="hl opt">;</span>            <span class="hl slc">// Shared by various SW components,latest version 2.1,new design from R600</span>
  USHORT        CompassionateData<span class="hl opt">;</span>        <span class="hl slc">// Will be obsolete from R600</span>
  USHORT        SaveRestoreInfo<span class="hl opt">;</span>          <span class="hl slc">// Only used by Bios</span>
  USHORT        PPLL_SS_Info<span class="hl opt">;</span>             <span class="hl slc">// Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info</span>
  USHORT        OemInfo<span class="hl opt">;</span>                  <span class="hl slc">// Defined and used by external SW, should be obsolete soon</span>
  USHORT        XTMDS_Info<span class="hl opt">;</span>               <span class="hl slc">// Will be obsolete from R600</span>
  USHORT        MclkSS_Info<span class="hl opt">;</span>              <span class="hl slc">// Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used</span>
  USHORT        Object_Header<span class="hl opt">;</span>            <span class="hl slc">// Shared by various SW components,latest version 1.1</span>
  USHORT        IndirectIOAccess<span class="hl opt">;</span>         <span class="hl slc">// Only used by Bios,this table position can&apos;t change at all!!</span>
  USHORT        MC_InitParameter<span class="hl opt">;</span>         <span class="hl slc">// Only used by command table</span>
  USHORT        ASIC_VDDC_Info<span class="hl opt">;</span>						<span class="hl slc">// Will be obsolete from R600</span>
  USHORT        ASIC_InternalSS_Info<span class="hl opt">;</span>			<span class="hl slc">// New tabel name from R600, used to be called &quot;ASIC_MVDDC_Info&quot;</span>
  USHORT        TV_VideoMode<span class="hl opt">;</span>							<span class="hl slc">// Only used by command table</span>
  USHORT        VRAM_Info<span class="hl opt">;</span>								<span class="hl slc">// Only used by command table, latest version 1.3</span>
  USHORT        MemoryTrainingInfo<span class="hl opt">;</span>				<span class="hl slc">// Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1</span>
  USHORT        IntegratedSystemInfo<span class="hl opt">;</span>			<span class="hl slc">// Shared by various SW components</span>
  USHORT        ASIC_ProfilingInfo<span class="hl opt">;</span>				<span class="hl slc">// New table name from R600, used to be called &quot;ASIC_VDDCI_Info&quot; for pre-R600</span>
  USHORT        VoltageObjectInfo<span class="hl opt">;</span>				<span class="hl slc">// Shared by various SW components, latest version 1.1</span>
	USHORT				PowerSourceInfo<span class="hl opt">;</span>					<span class="hl slc">// Shared by various SW components, latest versoin 1.1</span>
<span class="hl opt">}</span>ATOM_MASTER_LIST_OF_DATA_TABLES<span class="hl opt">;</span>

<span class="hl ppc">#ifdef	UEFI_BUILD</span>
	<span class="hl ppc">#define	USHORT	UTEMP</span>
<span class="hl ppc">#endif</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_MASTER_DATA_TABLE
<span class="hl opt">{</span> 
  ATOM_COMMON_TABLE_HEADER sHeader<span class="hl opt">;</span>  
  ATOM_MASTER_LIST_OF_DATA_TABLES   ListOfDataTables<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_MASTER_DATA_TABLE<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structure used in MultimediaCapabilityInfoTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_MULTIMEDIA_CAPABILITY_INFO
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER sHeader<span class="hl opt">;</span>  
  ULONG                    ulSignature<span class="hl opt">;</span>      <span class="hl slc">// HW info table signature string &quot;$ATI&quot;</span>
  UCHAR                    ucI2C_Type<span class="hl opt">;</span>       <span class="hl slc">// I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)</span>
  UCHAR                    ucTV_OutInfo<span class="hl opt">;</span>     <span class="hl slc">// Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)</span>
  UCHAR                    ucVideoPortInfo<span class="hl opt">;</span>  <span class="hl slc">// Provides the video port capabilities</span>
  UCHAR                    ucHostPortInfo<span class="hl opt">;</span>   <span class="hl slc">// Provides host port configuration information</span>
<span class="hl opt">}</span>ATOM_MULTIMEDIA_CAPABILITY_INFO<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structure used in MultimediaConfigInfoTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_MULTIMEDIA_CONFIG_INFO
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER sHeader<span class="hl opt">;</span>
  ULONG                    ulSignature<span class="hl opt">;</span>      <span class="hl slc">// MM info table signature sting &quot;$MMT&quot;</span>
  UCHAR                    ucTunerInfo<span class="hl opt">;</span>      <span class="hl slc">// Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)</span>
  UCHAR                    ucAudioChipInfo<span class="hl opt">;</span>  <span class="hl slc">// List the audio chip type (3:0) product type (4) and OEM revision (7:5)</span>
  UCHAR                    ucProductID<span class="hl opt">;</span>      <span class="hl slc">// Defines as OEM ID or ATI board ID dependent on product type setting</span>
  UCHAR                    ucMiscInfo1<span class="hl opt">;</span>      <span class="hl slc">// Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)</span>
  UCHAR                    ucMiscInfo2<span class="hl opt">;</span>      <span class="hl slc">// I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)</span>
  UCHAR                    ucMiscInfo3<span class="hl opt">;</span>      <span class="hl slc">// Video Decoder Type (3:0) Video In Standard/Crystal (7:4)</span>
  UCHAR                    ucMiscInfo4<span class="hl opt">;</span>      <span class="hl slc">// Video Decoder Host Config (2:0) reserved (7:3)</span>
  UCHAR                    ucVideoInput0Info<span class="hl opt">;</span><span class="hl slc">// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)</span>
  UCHAR                    ucVideoInput1Info<span class="hl opt">;</span><span class="hl slc">// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)</span>
  UCHAR                    ucVideoInput2Info<span class="hl opt">;</span><span class="hl slc">// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)</span>
  UCHAR                    ucVideoInput3Info<span class="hl opt">;</span><span class="hl slc">// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)</span>
  UCHAR                    ucVideoInput4Info<span class="hl opt">;</span><span class="hl slc">// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)</span>
<span class="hl opt">}</span>ATOM_MULTIMEDIA_CONFIG_INFO<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used in FirmwareInfoTable</span>
<span class="hl com">/****************************************************************************/</span>	

<span class="hl slc">// usBIOSCapability Defintion:</span>
<span class="hl slc">// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; </span>
<span class="hl slc">// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; </span>
<span class="hl slc">// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; </span>
<span class="hl slc">// Others: Reserved</span>
<span class="hl ppc">#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED         0x0001</span>
<span class="hl ppc">#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT            0x0002</span>
<span class="hl ppc">#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT     0x0004</span>
<span class="hl ppc">#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT      0x0008</span>
<span class="hl ppc">#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT      0x0010</span>
<span class="hl ppc">#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU         0x0020</span>
<span class="hl ppc">#define ATOM_BIOS_INFO_WMI_SUPPORT                  0x0040</span>
<span class="hl ppc">#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM   0x0080</span>
<span class="hl ppc">#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT          0x0100</span>
<span class="hl ppc">#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK        0x1E00</span>
<span class="hl ppc">#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000</span>
<span class="hl ppc">#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE  0x4000</span>


<span class="hl ppc">#ifndef _H2INC</span>

<span class="hl slc">//Please don&apos;t add or expand this bitfield structure below, this one will retire soon.!</span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_FIRMWARE_CAPABILITY
<span class="hl opt">{</span>
<span class="hl ppc">#if ATOM_BIG_ENDIAN</span>
  USHORT Reserved<span class="hl opt">:</span><span class="hl num">3</span><span class="hl opt">;</span>
  USHORT HyperMemory_Size<span class="hl opt">:</span><span class="hl num">4</span><span class="hl opt">;</span>
  USHORT HyperMemory_Support<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT PPMode_Assigned<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT WMI_SUPPORT<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT GPUControlsBL<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT EngineClockSS_Support<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT MemoryClockSS_Support<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT ExtendedDesktopSupport<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT DualCRTC_Support<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT FirmwarePosted<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
<span class="hl ppc">#else</span>
  USHORT FirmwarePosted<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT DualCRTC_Support<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT ExtendedDesktopSupport<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT MemoryClockSS_Support<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT EngineClockSS_Support<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT GPUControlsBL<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT WMI_SUPPORT<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT PPMode_Assigned<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT HyperMemory_Support<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT HyperMemory_Size<span class="hl opt">:</span><span class="hl num">4</span><span class="hl opt">;</span>
  USHORT Reserved<span class="hl opt">:</span><span class="hl num">3</span><span class="hl opt">;</span>
<span class="hl ppc">#endif</span>
<span class="hl opt">}</span>ATOM_FIRMWARE_CAPABILITY<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">union</span> _ATOM_FIRMWARE_CAPABILITY_ACCESS
<span class="hl opt">{</span>
  ATOM_FIRMWARE_CAPABILITY sbfAccess<span class="hl opt">;</span>
  USHORT                   susAccess<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_FIRMWARE_CAPABILITY_ACCESS<span class="hl opt">;</span>

<span class="hl ppc">#else</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">union</span> _ATOM_FIRMWARE_CAPABILITY_ACCESS
<span class="hl opt">{</span>
  USHORT                   susAccess<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_FIRMWARE_CAPABILITY_ACCESS<span class="hl opt">;</span>

<span class="hl ppc">#endif</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_FIRMWARE_INFO
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER        sHeader<span class="hl opt">;</span> 
  ULONG                           ulFirmwareRevision<span class="hl opt">;</span>
  ULONG                           ulDefaultEngineClock<span class="hl opt">;</span>       <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulDefaultMemoryClock<span class="hl opt">;</span>       <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulDriverTargetEngineClock<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulDriverTargetMemoryClock<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulMaxEngineClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulMaxMemoryClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulMaxPixelClockPLL_Output<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulASICMaxEngineClock<span class="hl opt">;</span>       <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulASICMaxMemoryClock<span class="hl opt">;</span>       <span class="hl slc">//In 10Khz unit</span>
  UCHAR                           ucASICMaxTemperature<span class="hl opt">;</span>
  UCHAR                           ucPadding<span class="hl opt">[</span><span class="hl num">3</span><span class="hl opt">];</span>               <span class="hl slc">//Don&apos;t use them</span>
  ULONG                           aulReservedForBIOS<span class="hl opt">[</span><span class="hl num">3</span><span class="hl opt">];</span>      <span class="hl slc">//Don&apos;t use them</span>
  USHORT                          usMinEngineClockPLL_Input<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMaxEngineClockPLL_Input<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinEngineClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinMemoryClockPLL_Input<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMaxMemoryClockPLL_Input<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinMemoryClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMaxPixelClock<span class="hl opt">;</span>            <span class="hl slc">//In 10Khz unit, Max.  Pclk</span>
  USHORT                          usMinPixelClockPLL_Input<span class="hl opt">;</span>   <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMaxPixelClockPLL_Input<span class="hl opt">;</span>   <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinPixelClockPLL_Output<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit, the definitions above can&apos;t change!!!</span>
  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability<span class="hl opt">;</span>
  USHORT                          usReferenceClock<span class="hl opt">;</span>           <span class="hl slc">//In 10Khz unit	</span>
  USHORT                          usPM_RTS_Location<span class="hl opt">;</span>          <span class="hl slc">//RTS PM4 starting location in ROM in 1Kb unit </span>
  UCHAR                           ucPM_RTS_StreamSize<span class="hl opt">;</span>        <span class="hl slc">//RTS PM4 packets in Kb unit</span>
  UCHAR                           ucDesign_ID<span class="hl opt">;</span>                <span class="hl slc">//Indicate what is the board design</span>
  UCHAR                           ucMemoryModule_ID<span class="hl opt">;</span>          <span class="hl slc">//Indicate what is the board design</span>
<span class="hl opt">}</span>ATOM_FIRMWARE_INFO<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_FIRMWARE_INFO_V1_2
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER        sHeader<span class="hl opt">;</span> 
  ULONG                           ulFirmwareRevision<span class="hl opt">;</span>
  ULONG                           ulDefaultEngineClock<span class="hl opt">;</span>       <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulDefaultMemoryClock<span class="hl opt">;</span>       <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulDriverTargetEngineClock<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulDriverTargetMemoryClock<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulMaxEngineClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulMaxMemoryClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulMaxPixelClockPLL_Output<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulASICMaxEngineClock<span class="hl opt">;</span>       <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulASICMaxMemoryClock<span class="hl opt">;</span>       <span class="hl slc">//In 10Khz unit</span>
  UCHAR                           ucASICMaxTemperature<span class="hl opt">;</span>
  UCHAR                           ucMinAllowedBL_Level<span class="hl opt">;</span>
  UCHAR                           ucPadding<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>               <span class="hl slc">//Don&apos;t use them</span>
  ULONG                           aulReservedForBIOS<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>      <span class="hl slc">//Don&apos;t use them</span>
  ULONG                           ulMinPixelClockPLL_Output<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinEngineClockPLL_Input<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMaxEngineClockPLL_Input<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinEngineClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinMemoryClockPLL_Input<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMaxMemoryClockPLL_Input<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinMemoryClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMaxPixelClock<span class="hl opt">;</span>            <span class="hl slc">//In 10Khz unit, Max.  Pclk</span>
  USHORT                          usMinPixelClockPLL_Input<span class="hl opt">;</span>   <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMaxPixelClockPLL_Input<span class="hl opt">;</span>   <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinPixelClockPLL_Output<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output</span>
  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability<span class="hl opt">;</span>
  USHORT                          usReferenceClock<span class="hl opt">;</span>           <span class="hl slc">//In 10Khz unit	</span>
  USHORT                          usPM_RTS_Location<span class="hl opt">;</span>          <span class="hl slc">//RTS PM4 starting location in ROM in 1Kb unit </span>
  UCHAR                           ucPM_RTS_StreamSize<span class="hl opt">;</span>        <span class="hl slc">//RTS PM4 packets in Kb unit</span>
  UCHAR                           ucDesign_ID<span class="hl opt">;</span>                <span class="hl slc">//Indicate what is the board design</span>
  UCHAR                           ucMemoryModule_ID<span class="hl opt">;</span>          <span class="hl slc">//Indicate what is the board design</span>
<span class="hl opt">}</span>ATOM_FIRMWARE_INFO_V1_2<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_FIRMWARE_INFO_V1_3
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER        sHeader<span class="hl opt">;</span> 
  ULONG                           ulFirmwareRevision<span class="hl opt">;</span>
  ULONG                           ulDefaultEngineClock<span class="hl opt">;</span>       <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulDefaultMemoryClock<span class="hl opt">;</span>       <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulDriverTargetEngineClock<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulDriverTargetMemoryClock<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulMaxEngineClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulMaxMemoryClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulMaxPixelClockPLL_Output<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulASICMaxEngineClock<span class="hl opt">;</span>       <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulASICMaxMemoryClock<span class="hl opt">;</span>       <span class="hl slc">//In 10Khz unit</span>
  UCHAR                           ucASICMaxTemperature<span class="hl opt">;</span>
  UCHAR                           ucMinAllowedBL_Level<span class="hl opt">;</span>
  UCHAR                           ucPadding<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>               <span class="hl slc">//Don&apos;t use them</span>
  ULONG                           aulReservedForBIOS<span class="hl opt">;</span>         <span class="hl slc">//Don&apos;t use them</span>
  ULONG                           ul3DAccelerationEngineClock<span class="hl opt">;</span><span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulMinPixelClockPLL_Output<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinEngineClockPLL_Input<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMaxEngineClockPLL_Input<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinEngineClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinMemoryClockPLL_Input<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMaxMemoryClockPLL_Input<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinMemoryClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMaxPixelClock<span class="hl opt">;</span>            <span class="hl slc">//In 10Khz unit, Max.  Pclk</span>
  USHORT                          usMinPixelClockPLL_Input<span class="hl opt">;</span>   <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMaxPixelClockPLL_Input<span class="hl opt">;</span>   <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinPixelClockPLL_Output<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output</span>
  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability<span class="hl opt">;</span>
  USHORT                          usReferenceClock<span class="hl opt">;</span>           <span class="hl slc">//In 10Khz unit	</span>
  USHORT                          usPM_RTS_Location<span class="hl opt">;</span>          <span class="hl slc">//RTS PM4 starting location in ROM in 1Kb unit </span>
  UCHAR                           ucPM_RTS_StreamSize<span class="hl opt">;</span>        <span class="hl slc">//RTS PM4 packets in Kb unit</span>
  UCHAR                           ucDesign_ID<span class="hl opt">;</span>                <span class="hl slc">//Indicate what is the board design</span>
  UCHAR                           ucMemoryModule_ID<span class="hl opt">;</span>          <span class="hl slc">//Indicate what is the board design</span>
<span class="hl opt">}</span>ATOM_FIRMWARE_INFO_V1_3<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_FIRMWARE_INFO_V1_4
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER        sHeader<span class="hl opt">;</span> 
  ULONG                           ulFirmwareRevision<span class="hl opt">;</span>
  ULONG                           ulDefaultEngineClock<span class="hl opt">;</span>       <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulDefaultMemoryClock<span class="hl opt">;</span>       <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulDriverTargetEngineClock<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulDriverTargetMemoryClock<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulMaxEngineClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulMaxMemoryClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulMaxPixelClockPLL_Output<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulASICMaxEngineClock<span class="hl opt">;</span>       <span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulASICMaxMemoryClock<span class="hl opt">;</span>       <span class="hl slc">//In 10Khz unit</span>
  UCHAR                           ucASICMaxTemperature<span class="hl opt">;</span>
  UCHAR                           ucMinAllowedBL_Level<span class="hl opt">;</span>
  USHORT                          usBootUpVDDCVoltage<span class="hl opt">;</span>        <span class="hl slc">//In MV unit</span>
  USHORT                          usLcdMinPixelClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">// In MHz unit</span>
  USHORT                          usLcdMaxPixelClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">// In MHz unit</span>
  ULONG                           ul3DAccelerationEngineClock<span class="hl opt">;</span><span class="hl slc">//In 10Khz unit</span>
  ULONG                           ulMinPixelClockPLL_Output<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinEngineClockPLL_Input<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMaxEngineClockPLL_Input<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinEngineClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinMemoryClockPLL_Input<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMaxMemoryClockPLL_Input<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinMemoryClockPLL_Output<span class="hl opt">;</span> <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMaxPixelClock<span class="hl opt">;</span>            <span class="hl slc">//In 10Khz unit, Max.  Pclk</span>
  USHORT                          usMinPixelClockPLL_Input<span class="hl opt">;</span>   <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMaxPixelClockPLL_Input<span class="hl opt">;</span>   <span class="hl slc">//In 10Khz unit</span>
  USHORT                          usMinPixelClockPLL_Output<span class="hl opt">;</span>  <span class="hl slc">//In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output</span>
  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability<span class="hl opt">;</span>
  USHORT                          usReferenceClock<span class="hl opt">;</span>           <span class="hl slc">//In 10Khz unit	</span>
  USHORT                          usPM_RTS_Location<span class="hl opt">;</span>          <span class="hl slc">//RTS PM4 starting location in ROM in 1Kb unit </span>
  UCHAR                           ucPM_RTS_StreamSize<span class="hl opt">;</span>        <span class="hl slc">//RTS PM4 packets in Kb unit</span>
  UCHAR                           ucDesign_ID<span class="hl opt">;</span>                <span class="hl slc">//Indicate what is the board design</span>
  UCHAR                           ucMemoryModule_ID<span class="hl opt">;</span>          <span class="hl slc">//Indicate what is the board design</span>
<span class="hl opt">}</span>ATOM_FIRMWARE_INFO_V1_4<span class="hl opt">;</span>

<span class="hl ppc">#define ATOM_FIRMWARE_INFO_LAST  ATOM_FIRMWARE_INFO_V1_4</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structures used in IntegratedSystemInfoTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl ppc">#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN      0x2</span>
<span class="hl ppc">#define IGP_CAP_FLAG_AC_CARD               0x4</span>
<span class="hl ppc">#define IGP_CAP_FLAG_SDVO_CARD             0x8</span>
<span class="hl ppc">#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE     0x10</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_INTEGRATED_SYSTEM_INFO
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER        sHeader<span class="hl opt">;</span> 
  ULONG	                          ulBootUpEngineClock<span class="hl opt">;</span>		    <span class="hl slc">//in 10kHz unit</span>
  ULONG	                          ulBootUpMemoryClock<span class="hl opt">;</span>		    <span class="hl slc">//in 10kHz unit</span>
  ULONG	                          ulMaxSystemMemoryClock<span class="hl opt">;</span>	    <span class="hl slc">//in 10kHz unit</span>
  ULONG	                          ulMinSystemMemoryClock<span class="hl opt">;</span>	    <span class="hl slc">//in 10kHz unit</span>
  UCHAR                           ucNumberOfCyclesInPeriodHi<span class="hl opt">;</span>
  UCHAR                           ucLCDTimingSel<span class="hl opt">;</span>             <span class="hl slc">//=0:not valid.!=0 sel this timing descriptor from LCD EDID.</span>
  USHORT                          usReserved1<span class="hl opt">;</span>
  USHORT                          usInterNBVoltageLow<span class="hl opt">;</span>        <span class="hl slc">//An intermidiate PMW value to set the voltage </span>
  USHORT                          usInterNBVoltageHigh<span class="hl opt">;</span>       <span class="hl slc">//Another intermidiate PMW value to set the voltage </span>
  ULONG	                          ulReserved<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>

  USHORT	                        usFSBClock<span class="hl opt">;</span>			            <span class="hl slc">//In MHz unit</span>
  USHORT                          usCapabilityFlag<span class="hl opt">;</span>		        <span class="hl slc">//Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable</span>
																                              <span class="hl slc">//Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card</span>
                                                              <span class="hl slc">//Bit[4]==1: P/2 mode, ==0: P/1 mode</span>
  USHORT	                        usPCIENBCfgReg7<span class="hl opt">;</span>				    <span class="hl slc">//bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal</span>
  USHORT	                        usK8MemoryClock<span class="hl opt">;</span>            <span class="hl slc">//in MHz unit</span>
  USHORT	                        usK8SyncStartDelay<span class="hl opt">;</span>         <span class="hl slc">//in 0.01 us unit</span>
  USHORT	                        usK8DataReturnTime<span class="hl opt">;</span>         <span class="hl slc">//in 0.01 us unit</span>
  UCHAR                           ucMaxNBVoltage<span class="hl opt">;</span>
  UCHAR                           ucMinNBVoltage<span class="hl opt">;</span>
  UCHAR                           ucMemoryType<span class="hl opt">;</span>					      <span class="hl slc">//[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved</span>
  UCHAR                           ucNumberOfCyclesInPeriod<span class="hl opt">;</span>		<span class="hl slc">//CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod </span>
  UCHAR                           ucStartingPWM_HighTime<span class="hl opt">;</span>     <span class="hl slc">//CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime</span>
  UCHAR                           ucHTLinkWidth<span class="hl opt">;</span>              <span class="hl slc">//16 bit vs. 8 bit</span>
  UCHAR                           ucMaxNBVoltageHigh<span class="hl opt">;</span>    
  UCHAR                           ucMinNBVoltageHigh<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_INTEGRATED_SYSTEM_INFO<span class="hl opt">;</span>

<span class="hl com">/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO</span>
<span class="hl com">ulBootUpMemoryClock:    For Intel IGP,it&apos;s the UMA system memory clock </span>
<span class="hl com">                        For AMD IGP,it&apos;s 0 if no SidePort memory installed or it&apos;s the boot-up SidePort memory clock</span>
<span class="hl com">ulMaxSystemMemoryClock: For Intel IGP,it&apos;s the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it&apos;s 0</span>
<span class="hl com">                        For AMD IGP,for now this can be 0</span>
<span class="hl com">ulMinSystemMemoryClock: For Intel IGP,it&apos;s 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it&apos;s 0 </span>
<span class="hl com">                        For AMD IGP,for now this can be 0</span>
<span class="hl com"></span>
<span class="hl com">usFSBClock:             For Intel IGP,it&apos;s FSB Freq </span>
<span class="hl com">                        For AMD IGP,it&apos;s HT Link Speed</span>
<span class="hl com"></span>
<span class="hl com">usK8MemoryClock:        For AMD IGP only. For RevF CPU, set it to 200</span>
<span class="hl com">usK8SyncStartDelay:     For AMD IGP only. Memory access latency in K8, required for watermark calculation</span>
<span class="hl com">usK8DataReturnTime:     For AMD IGP only. Memory access latency in K8, required for watermark calculation</span>
<span class="hl com"></span>
<span class="hl com">VC:Voltage Control</span>
<span class="hl com">ucMaxNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.</span>
<span class="hl com">ucMinNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.</span>
<span class="hl com"></span>
<span class="hl com">ucNumberOfCyclesInPeriod:   Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. </span>
<span class="hl com">ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 </span>
<span class="hl com"></span>
<span class="hl com">ucMaxNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of  the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.</span>
<span class="hl com">ucMinNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.</span>
<span class="hl com"></span>
<span class="hl com"></span>
<span class="hl com">usInterNBVoltageLow:    Voltage regulator dependent PWM value. The value makes the the voltage &gt;=Min NB voltage but &lt;=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.</span>
<span class="hl com">usInterNBVoltageHigh:   Voltage regulator dependent PWM value. The value makes the the voltage &gt;=InterNBVoltageLow but &lt;=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.</span>
<span class="hl com">*/</span>


<span class="hl com">/*</span>
<span class="hl com">The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;</span>
<span class="hl com">Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. </span>
<span class="hl com">The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.</span>
<span class="hl com"></span>
<span class="hl com">SW components can access the IGP system infor structure in the same way as before</span>
<span class="hl com">*/</span>


<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_INTEGRATED_SYSTEM_INFO_V2
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER   sHeader<span class="hl opt">;</span>
  ULONG	                     ulBootUpEngineClock<span class="hl opt">;</span>       <span class="hl slc">//in 10kHz unit</span>
  ULONG			     ulReserved1<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>            <span class="hl slc">//must be 0x0 for the reserved</span>
  ULONG	                     ulBootUpUMAClock<span class="hl opt">;</span>          <span class="hl slc">//in 10kHz unit</span>
  ULONG	                     ulBootUpSidePortClock<span class="hl opt">;</span>     <span class="hl slc">//in 10kHz unit</span>
  ULONG	                     ulMinSidePortClock<span class="hl opt">;</span>        <span class="hl slc">//in 10kHz unit</span>
  ULONG			     ulReserved2<span class="hl opt">[</span><span class="hl num">6</span><span class="hl opt">];</span>            <span class="hl slc">//must be 0x0 for the reserved</span>
  ULONG                      ulSystemConfig<span class="hl opt">;</span>            <span class="hl slc">//see explanation below</span>
  ULONG                      ulBootUpReqDisplayVector<span class="hl opt">;</span>
  ULONG                      ulOtherDisplayMisc<span class="hl opt">;</span>
  ULONG                      ulDDISlot1Config<span class="hl opt">;</span>
  ULONG                      ulDDISlot2Config<span class="hl opt">;</span>
  UCHAR                      ucMemoryType<span class="hl opt">;</span>              <span class="hl slc">//[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved</span>
  UCHAR                      ucUMAChannelNumber<span class="hl opt">;</span>
  UCHAR                      ucDockingPinBit<span class="hl opt">;</span>
  UCHAR                      ucDockingPinPolarity<span class="hl opt">;</span>
  ULONG                      ulDockingPinCFGInfo<span class="hl opt">;</span>
  ULONG                      ulCPUCapInfo<span class="hl opt">;</span>
  USHORT                     usNumberOfCyclesInPeriod<span class="hl opt">;</span>
  USHORT                     usMaxNBVoltage<span class="hl opt">;</span>
  USHORT                     usMinNBVoltage<span class="hl opt">;</span>
  USHORT                     usBootUpNBVoltage<span class="hl opt">;</span>
  ULONG                      ulHTLinkFreq<span class="hl opt">;</span>              <span class="hl slc">//in 10Khz</span>
  USHORT                     usMinHTLinkWidth<span class="hl opt">;</span>
  USHORT                     usMaxHTLinkWidth<span class="hl opt">;</span>
  USHORT                     usUMASyncStartDelay<span class="hl opt">;</span>
  USHORT                     usUMADataReturnTime<span class="hl opt">;</span>
  USHORT                     usLinkStatusZeroTime<span class="hl opt">;</span>
  USHORT                     usReserved<span class="hl opt">;</span>
  ULONG                      ulHighVoltageHTLinkFreq<span class="hl opt">;</span>     <span class="hl slc">// in 10Khz</span>
  ULONG                      ulLowVoltageHTLinkFreq<span class="hl opt">;</span>      <span class="hl slc">// in 10Khz</span>
  USHORT                     usMaxUpStreamHTLinkWidth<span class="hl opt">;</span>
  USHORT                     usMaxDownStreamHTLinkWidth<span class="hl opt">;</span>
  USHORT                     usMinUpStreamHTLinkWidth<span class="hl opt">;</span>
  USHORT                     usMinDownStreamHTLinkWidth<span class="hl opt">;</span>
  ULONG                      ulReserved3<span class="hl opt">[</span><span class="hl num">97</span><span class="hl opt">];</span>          <span class="hl slc">//must be 0x0</span>
<span class="hl opt">}</span>ATOM_INTEGRATED_SYSTEM_INFO_V2<span class="hl opt">;</span>   

<span class="hl com">/*</span>
<span class="hl com">ulBootUpEngineClock:   Boot-up Engine Clock in 10Khz;</span>
<span class="hl com">ulBootUpUMAClock:      Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present</span>
<span class="hl com">ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock</span>
<span class="hl com"></span>
<span class="hl com">ulSystemConfig:  </span>
<span class="hl com">Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; </span>
<span class="hl com">Bit[1]=1: system boots up at AMD overdrived state or user customized  mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state</span>
<span class="hl com">      =0: system boots up at driver control state. Power state depends on PowerPlay table.</span>
<span class="hl com">Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.</span>
<span class="hl com">Bit[3]=1: Only one power state(Performance) will be supported.</span>
<span class="hl com">      =0: Multiple power states supported from PowerPlay table.</span>
<span class="hl com">Bit[4]=1: CLMC is supported and enabled on current system. </span>
<span class="hl com">      =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.  </span>
<span class="hl com">Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.  </span>
<span class="hl com">      =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.</span>
<span class="hl com">Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.</span>
<span class="hl com">      =0: Voltage settings is determined by powerplay table.</span>
<span class="hl com">Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we&apos;re using legacy C1E. This is workaround for CPU(Griffin) performance issue.</span>
<span class="hl com">      =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.</span>
<span class="hl com"></span>
<span class="hl com">ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.</span>
<span class="hl com"></span>
<span class="hl com">ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;</span>
<span class="hl com">			              [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition;</span>
<span class="hl com"></span>
<span class="hl com">ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).</span>
<span class="hl com">      [3:0]  - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)</span>
<span class="hl com">			[7:4]  - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)			</span>
<span class="hl com">			[15:8] - Lane configuration attribute; </span>
<span class="hl com">      [23:16]- Connector type, possible value:</span>
<span class="hl com">               CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D</span>
<span class="hl com">               CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D</span>
<span class="hl com">               CONNECTOR_OBJECT_ID_HDMI_TYPE_A</span>
<span class="hl com">               CONNECTOR_OBJECT_ID_DISPLAYPORT</span>
<span class="hl com">			[31:24]- Reserved</span>
<span class="hl com"></span>
<span class="hl com">ulDDISlot2Config: Same as Slot1.</span>
<span class="hl com">ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.</span>
<span class="hl com">For IGP, Hypermemory is the only memory type showed in CCC.</span>
<span class="hl com"></span>
<span class="hl com">ucUMAChannelNumber:  how many channels for the UMA;</span>
<span class="hl com"></span>
<span class="hl com">ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin </span>
<span class="hl com">ucDockingPinBit:     which bit in this register to read the pin status;</span>
<span class="hl com">ucDockingPinPolarity:Polarity of the pin when docked;</span>
<span class="hl com"></span>
<span class="hl com">ulCPUCapInfo:        [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0</span>
<span class="hl com"></span>
<span class="hl com">usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.</span>
<span class="hl com">usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. </span>
<span class="hl com">usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.</span>
<span class="hl com">                    GPIO mode: both usMaxNBVoltage &amp; usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0</span>
<span class="hl com">                    PWM mode: both usMaxNBVoltage &amp; usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1</span>
<span class="hl com">                    GPU SW don&apos;t control mode: usMaxNBVoltage &amp; usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE</span>
<span class="hl com">usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.</span>
<span class="hl com"></span>
<span class="hl com">ulHTLinkFreq:       Bootup HT link Frequency in 10Khz.</span>
<span class="hl com">usMinHTLinkWidth:   Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. </span>
<span class="hl com">                    If CDLW enabled, both upstream and downstream width should be the same during bootup.</span>
<span class="hl com">usMaxHTLinkWidth:   Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. </span>
<span class="hl com">                    If CDLW enabled, both upstream and downstream width should be the same during bootup.  </span>
<span class="hl com"></span>
<span class="hl com">usUMASyncStartDelay: Memory access latency, required for watermark calculation </span>
<span class="hl com">usUMADataReturnTime: Memory access latency, required for watermark calculation</span>
<span class="hl com">usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us </span>
<span class="hl com">for Griffin or Greyhound. SBIOS needs to convert to actual time by:</span>
<span class="hl com">                     if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)</span>
<span class="hl com">                     if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)</span>
<span class="hl com">                     if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)</span>
<span class="hl com">                     if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)</span>
<span class="hl com"></span>
<span class="hl com">ulHighVoltageHTLinkFreq:     HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.</span>
<span class="hl com">                             This must be less than or equal to ulHTLinkFreq(bootup frequency). </span>
<span class="hl com">ulLowVoltageHTLinkFreq:      HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.</span>
<span class="hl com">                             This must be less than or equal to ulHighVoltageHTLinkFreq.</span>
<span class="hl com"></span>
<span class="hl com">usMaxUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.</span>
<span class="hl com">usMaxDownStreamHTLinkWidth:  same as above.</span>
<span class="hl com">usMinUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.</span>
<span class="hl com">usMinDownStreamHTLinkWidth:  same as above.</span>
<span class="hl com">*/</span>


<span class="hl ppc">#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE                 0x00000001</span>
<span class="hl ppc">#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE             0x00000002</span>
<span class="hl ppc">#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE                  0x00000004 </span>
<span class="hl ppc">#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY         0x00000008</span>
<span class="hl ppc">#define SYSTEM_CONFIG_CLMC_ENABLED                        0x00000010</span>
<span class="hl ppc">#define SYSTEM_CONFIG_CDLW_ENABLED                        0x00000020</span>
<span class="hl ppc">#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED              0x00000040</span>
<span class="hl ppc">#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED            0x00000080</span>

<span class="hl ppc">#define IGP_DDI_SLOT_LANE_CONFIG_MASK                     0x000000FF</span>

<span class="hl ppc">#define b0IGP_DDI_SLOT_LANE_MAP_MASK                      0x0F</span>
<span class="hl ppc">#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK              0xF0</span>
<span class="hl ppc">#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3                    0x01</span>
<span class="hl ppc">#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7                    0x02</span>
<span class="hl ppc">#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11                   0x04</span>
<span class="hl ppc">#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15                  0x08</span>

<span class="hl ppc">#define IGP_DDI_SLOT_ATTRIBUTE_MASK                       0x0000FF00</span>
<span class="hl ppc">#define IGP_DDI_SLOT_CONFIG_REVERSED                      0x00000100</span>
<span class="hl ppc">#define b1IGP_DDI_SLOT_CONFIG_REVERSED                    0x01</span>

<span class="hl ppc">#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK                  0x00FF0000</span>

<span class="hl ppc">#define ATOM_CRT_INT_ENCODER1_INDEX                       0x00000000</span>
<span class="hl ppc">#define ATOM_LCD_INT_ENCODER1_INDEX                       0x00000001</span>
<span class="hl ppc">#define ATOM_TV_INT_ENCODER1_INDEX                        0x00000002</span>
<span class="hl ppc">#define ATOM_DFP_INT_ENCODER1_INDEX                       0x00000003</span>
<span class="hl ppc">#define ATOM_CRT_INT_ENCODER2_INDEX                       0x00000004</span>
<span class="hl ppc">#define ATOM_LCD_EXT_ENCODER1_INDEX                       0x00000005</span>
<span class="hl ppc">#define ATOM_TV_EXT_ENCODER1_INDEX                        0x00000006</span>
<span class="hl ppc">#define ATOM_DFP_EXT_ENCODER1_INDEX                       0x00000007</span>
<span class="hl ppc">#define ATOM_CV_INT_ENCODER1_INDEX                        0x00000008</span>
<span class="hl ppc">#define ATOM_DFP_INT_ENCODER2_INDEX                       0x00000009</span>
<span class="hl ppc">#define ATOM_CRT_EXT_ENCODER1_INDEX                       0x0000000A</span>
<span class="hl ppc">#define ATOM_CV_EXT_ENCODER1_INDEX                        0x0000000B</span>
<span class="hl ppc">#define ATOM_DFP_INT_ENCODER3_INDEX                       0x0000000C</span>
<span class="hl ppc">#define ATOM_DFP_INT_ENCODER4_INDEX                       0x0000000D</span>

<span class="hl slc">// define ASIC internal encoder id ( bit vector )</span>
<span class="hl ppc">#define ASIC_INT_DAC1_ENCODER_ID    											0x00 </span>
<span class="hl ppc">#define ASIC_INT_TV_ENCODER_ID														0x02</span>
<span class="hl ppc">#define ASIC_INT_DIG1_ENCODER_ID													0x03</span>
<span class="hl ppc">#define ASIC_INT_DAC2_ENCODER_ID													0x04</span>
<span class="hl ppc">#define ASIC_EXT_TV_ENCODER_ID														0x06</span>
<span class="hl ppc">#define ASIC_INT_DVO_ENCODER_ID														0x07</span>
<span class="hl ppc">#define ASIC_INT_DIG2_ENCODER_ID													0x09</span>
<span class="hl ppc">#define ASIC_EXT_DIG_ENCODER_ID														0x05</span>

<span class="hl slc">//define Encoder attribute</span>
<span class="hl ppc">#define ATOM_ANALOG_ENCODER																0</span>
<span class="hl ppc">#define ATOM_DIGITAL_ENCODER															1		</span>

<span class="hl ppc">#define ATOM_DEVICE_CRT1_INDEX                            0x00000000</span>
<span class="hl ppc">#define ATOM_DEVICE_LCD1_INDEX                            0x00000001</span>
<span class="hl ppc">#define ATOM_DEVICE_TV1_INDEX                             0x00000002</span>
<span class="hl ppc">#define ATOM_DEVICE_DFP1_INDEX                            0x00000003</span>
<span class="hl ppc">#define ATOM_DEVICE_CRT2_INDEX                            0x00000004</span>
<span class="hl ppc">#define ATOM_DEVICE_LCD2_INDEX                            0x00000005</span>
<span class="hl ppc">#define ATOM_DEVICE_TV2_INDEX                             0x00000006</span>
<span class="hl ppc">#define ATOM_DEVICE_DFP2_INDEX                            0x00000007</span>
<span class="hl ppc">#define ATOM_DEVICE_CV_INDEX                              0x00000008</span>
<span class="hl ppc">#define ATOM_DEVICE_DFP3_INDEX														0x00000009</span>
<span class="hl ppc">#define ATOM_DEVICE_DFP4_INDEX														0x0000000A</span>
<span class="hl ppc">#define ATOM_DEVICE_DFP5_INDEX														0x0000000B</span>
<span class="hl ppc">#define ATOM_DEVICE_RESERVEDC_INDEX                       0x0000000C</span>
<span class="hl ppc">#define ATOM_DEVICE_RESERVEDD_INDEX                       0x0000000D</span>
<span class="hl ppc">#define ATOM_DEVICE_RESERVEDE_INDEX                       0x0000000E</span>
<span class="hl ppc">#define ATOM_DEVICE_RESERVEDF_INDEX                       0x0000000F</span>
<span class="hl ppc">#define ATOM_MAX_SUPPORTED_DEVICE_INFO                    (ATOM_DEVICE_DFP3_INDEX+1)</span>
<span class="hl ppc">#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2                  ATOM_MAX_SUPPORTED_DEVICE_INFO</span>
<span class="hl ppc">#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3                  (ATOM_DEVICE_DFP5_INDEX + 1 )</span>

<span class="hl ppc">#define ATOM_MAX_SUPPORTED_DEVICE                         (ATOM_DEVICE_RESERVEDF_INDEX+1)</span>

<span class="hl ppc">#define ATOM_DEVICE_CRT1_SUPPORT                          (0x1L &lt;&lt; ATOM_DEVICE_CRT1_INDEX )</span>
<span class="hl ppc">#define ATOM_DEVICE_LCD1_SUPPORT                          (0x1L &lt;&lt; ATOM_DEVICE_LCD1_INDEX )</span>
<span class="hl ppc">#define ATOM_DEVICE_TV1_SUPPORT                           (0x1L &lt;&lt; ATOM_DEVICE_TV1_INDEX  )</span>
<span class="hl ppc">#define ATOM_DEVICE_DFP1_SUPPORT                          (0x1L &lt;&lt; ATOM_DEVICE_DFP1_INDEX)</span>
<span class="hl ppc">#define ATOM_DEVICE_CRT2_SUPPORT                          (0x1L &lt;&lt; ATOM_DEVICE_CRT2_INDEX )</span>
<span class="hl ppc">#define ATOM_DEVICE_LCD2_SUPPORT                          (0x1L &lt;&lt; ATOM_DEVICE_LCD2_INDEX )</span>
<span class="hl ppc">#define ATOM_DEVICE_TV2_SUPPORT                           (0x1L &lt;&lt; ATOM_DEVICE_TV2_INDEX  )</span>
<span class="hl ppc">#define ATOM_DEVICE_DFP2_SUPPORT                          (0x1L &lt;&lt; ATOM_DEVICE_DFP2_INDEX)</span>
<span class="hl ppc">#define ATOM_DEVICE_CV_SUPPORT                            (0x1L &lt;&lt; ATOM_DEVICE_CV_INDEX   )</span>
<span class="hl ppc">#define ATOM_DEVICE_DFP3_SUPPORT													(0x1L &lt;&lt; ATOM_DEVICE_DFP3_INDEX )</span>
<span class="hl ppc">#define ATOM_DEVICE_DFP4_SUPPORT													(0x1L &lt;&lt; ATOM_DEVICE_DFP4_INDEX )</span>
<span class="hl ppc">#define ATOM_DEVICE_DFP5_SUPPORT													(0x1L &lt;&lt; ATOM_DEVICE_DFP5_INDEX )</span>

<span class="hl ppc">#define ATOM_DEVICE_CRT_SUPPORT                           ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT</span>
<span class="hl ppc">#define ATOM_DEVICE_DFP_SUPPORT                           ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT |  ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT</span>
<span class="hl ppc">#define ATOM_DEVICE_TV_SUPPORT                            ATOM_DEVICE_TV1_SUPPORT  | ATOM_DEVICE_TV2_SUPPORT</span>
<span class="hl ppc">#define ATOM_DEVICE_LCD_SUPPORT                           ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT</span>

<span class="hl ppc">#define ATOM_DEVICE_CONNECTOR_TYPE_MASK                   0x000000F0</span>
<span class="hl ppc">#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT                  0x00000004</span>
<span class="hl ppc">#define ATOM_DEVICE_CONNECTOR_VGA                         0x00000001</span>
<span class="hl ppc">#define ATOM_DEVICE_CONNECTOR_DVI_I                       0x00000002</span>
<span class="hl ppc">#define ATOM_DEVICE_CONNECTOR_DVI_D                       0x00000003</span>
<span class="hl ppc">#define ATOM_DEVICE_CONNECTOR_DVI_A                       0x00000004</span>
<span class="hl ppc">#define ATOM_DEVICE_CONNECTOR_SVIDEO                      0x00000005</span>
<span class="hl ppc">#define ATOM_DEVICE_CONNECTOR_COMPOSITE                   0x00000006</span>
<span class="hl ppc">#define ATOM_DEVICE_CONNECTOR_LVDS                        0x00000007</span>
<span class="hl ppc">#define ATOM_DEVICE_CONNECTOR_DIGI_LINK                   0x00000008</span>
<span class="hl ppc">#define ATOM_DEVICE_CONNECTOR_SCART                       0x00000009</span>
<span class="hl ppc">#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A                 0x0000000A</span>
<span class="hl ppc">#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B                 0x0000000B</span>
<span class="hl ppc">#define ATOM_DEVICE_CONNECTOR_CASE_1                      0x0000000E</span>
<span class="hl ppc">#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT                 0x0000000F</span>


<span class="hl ppc">#define ATOM_DEVICE_DAC_INFO_MASK                         0x0000000F</span>
<span class="hl ppc">#define ATOM_DEVICE_DAC_INFO_SHIFT                        0x00000000</span>
<span class="hl ppc">#define ATOM_DEVICE_DAC_INFO_NODAC                        0x00000000</span>
<span class="hl ppc">#define ATOM_DEVICE_DAC_INFO_DACA                         0x00000001</span>
<span class="hl ppc">#define ATOM_DEVICE_DAC_INFO_DACB                         0x00000002</span>
<span class="hl ppc">#define ATOM_DEVICE_DAC_INFO_EXDAC                        0x00000003</span>

<span class="hl ppc">#define ATOM_DEVICE_I2C_ID_NOI2C                          0x00000000</span>

<span class="hl ppc">#define ATOM_DEVICE_I2C_LINEMUX_MASK                      0x0000000F</span>
<span class="hl ppc">#define ATOM_DEVICE_I2C_LINEMUX_SHIFT                     0x00000000</span>

<span class="hl ppc">#define ATOM_DEVICE_I2C_ID_MASK                           0x00000070</span>
<span class="hl ppc">#define ATOM_DEVICE_I2C_ID_SHIFT                          0x00000004</span>
<span class="hl ppc">#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE              0x00000001</span>
<span class="hl ppc">#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE                  0x00000002</span>
<span class="hl ppc">#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE                0x00000003</span>    <span class="hl slc">//For IGP RS600</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL                 0x00000004</span>    <span class="hl slc">//For IGP RS690</span>
<span class="hl ppc"></span>
<span class="hl ppc">#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK                 0x00000080</span>
<span class="hl ppc">#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT                0x00000007</span>
<span class="hl ppc">#define	ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C            0x00000000</span>
<span class="hl ppc">#define	ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C            0x00000001</span>

<span class="hl slc">//  usDeviceSupport:</span>
<span class="hl slc">//  Bits0	= 0 - no CRT1 support= 1- CRT1 is supported</span>
<span class="hl slc">//  Bit 1	= 0 - no LCD1 support= 1- LCD1 is supported</span>
<span class="hl slc">//  Bit 2	= 0 - no TV1  support= 1- TV1  is supported</span>
<span class="hl slc">//  Bit 3	= 0 - no DFP1 support= 1- DFP1 is supported</span>
<span class="hl slc">//  Bit 4	= 0 - no CRT2 support= 1- CRT2 is supported</span>
<span class="hl slc">//  Bit 5	= 0 - no LCD2 support= 1- LCD2 is supported</span>
<span class="hl slc">//  Bit 6	= 0 - no TV2  support= 1- TV2  is supported</span>
<span class="hl slc">//  Bit 7	= 0 - no DFP2 support= 1- DFP2 is supported</span>
<span class="hl slc">//  Bit 8	= 0 - no CV   support= 1- CV   is supported</span>
<span class="hl slc">//  Bit 9	= 0 - no DFP3 support= 1- DFP3 is supported</span>
<span class="hl slc">//  Byte1 (Supported Device Info)</span>
<span class="hl slc">//  Bit 0	= = 0 - no CV support= 1- CV is supported</span>
<span class="hl slc">//   </span>
<span class="hl slc">//  </span>

<span class="hl slc">//		ucI2C_ConfigID</span>
<span class="hl slc">//    [7:0] - I2C LINE Associate ID</span>
<span class="hl slc">//          = 0   - no I2C</span>
<span class="hl slc">//    [7]		-	HW_Cap        =	1,  [6:0]=HW assisted I2C ID(HW line selection)</span>
<span class="hl slc">//                          =	0,  [6:0]=SW assisted I2C ID</span>
<span class="hl slc">//    [6-4]	- HW_ENGINE_ID  =	1,  HW engine for NON multimedia use</span>
<span class="hl slc">//                          =	2,	HW engine for Multimedia use</span>
<span class="hl slc">//                          =	3-7	Reserved for future I2C engines</span>
<span class="hl slc">//		[3-0] - I2C_LINE_MUX  = A Mux number when it&apos;s HW assisted I2C or GPIO ID when it&apos;s SW I2C</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_I2C_ID_CONFIG
<span class="hl opt">{</span>
<span class="hl ppc">#if ATOM_BIG_ENDIAN</span>
  UCHAR   bfHW_Capable<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  UCHAR   bfHW_EngineID<span class="hl opt">:</span><span class="hl num">3</span><span class="hl opt">;</span>
  UCHAR   bfI2C_LineMux<span class="hl opt">:</span><span class="hl num">4</span><span class="hl opt">;</span>
<span class="hl ppc">#else</span>
  UCHAR   bfI2C_LineMux<span class="hl opt">:</span><span class="hl num">4</span><span class="hl opt">;</span>
  UCHAR   bfHW_EngineID<span class="hl opt">:</span><span class="hl num">3</span><span class="hl opt">;</span>
  UCHAR   bfHW_Capable<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
<span class="hl ppc">#endif</span>
<span class="hl opt">}</span>ATOM_I2C_ID_CONFIG<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">union</span> _ATOM_I2C_ID_CONFIG_ACCESS
<span class="hl opt">{</span>
  ATOM_I2C_ID_CONFIG sbfAccess<span class="hl opt">;</span>
  UCHAR              ucAccess<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_I2C_ID_CONFIG_ACCESS<span class="hl opt">;</span>
   

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structure used in GPIO_I2C_InfoTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_GPIO_I2C_ASSIGMENT
<span class="hl opt">{</span>
  USHORT                    usClkMaskRegisterIndex<span class="hl opt">;</span>
  USHORT                    usClkEnRegisterIndex<span class="hl opt">;</span>
  USHORT                    usClkY_RegisterIndex<span class="hl opt">;</span>
  USHORT                    usClkA_RegisterIndex<span class="hl opt">;</span>
  USHORT                    usDataMaskRegisterIndex<span class="hl opt">;</span>
  USHORT                    usDataEnRegisterIndex<span class="hl opt">;</span>
  USHORT                    usDataY_RegisterIndex<span class="hl opt">;</span>
  USHORT                    usDataA_RegisterIndex<span class="hl opt">;</span>
  ATOM_I2C_ID_CONFIG_ACCESS sucI2cId<span class="hl opt">;</span>
  UCHAR                     ucClkMaskShift<span class="hl opt">;</span>
  UCHAR                     ucClkEnShift<span class="hl opt">;</span>
  UCHAR                     ucClkY_Shift<span class="hl opt">;</span>
  UCHAR                     ucClkA_Shift<span class="hl opt">;</span>
  UCHAR                     ucDataMaskShift<span class="hl opt">;</span>
  UCHAR                     ucDataEnShift<span class="hl opt">;</span>
  UCHAR                     ucDataY_Shift<span class="hl opt">;</span>
  UCHAR                     ucDataA_Shift<span class="hl opt">;</span>
  UCHAR                     ucReserved1<span class="hl opt">;</span>
  UCHAR                     ucReserved2<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_GPIO_I2C_ASSIGMENT<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_GPIO_I2C_INFO
<span class="hl opt">{</span> 
  ATOM_COMMON_TABLE_HEADER	sHeader<span class="hl opt">;</span>
  ATOM_GPIO_I2C_ASSIGMENT   asGPIO_Info<span class="hl opt">[</span>ATOM_MAX_SUPPORTED_DEVICE<span class="hl opt">];</span>
<span class="hl opt">}</span>ATOM_GPIO_I2C_INFO<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Common Structure used in other structures</span>
<span class="hl com">/****************************************************************************/</span>	

<span class="hl ppc">#ifndef _H2INC</span>
  
<span class="hl slc">//Please don&apos;t add or expand this bitfield structure below, this one will retire soon.!</span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_MODE_MISC_INFO
<span class="hl opt">{</span> 
<span class="hl ppc">#if ATOM_BIG_ENDIAN</span>
  USHORT Reserved<span class="hl opt">:</span><span class="hl num">6</span><span class="hl opt">;</span>
  USHORT RGB888<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT DoubleClock<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT Interlace<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT CompositeSync<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT V_ReplicationBy2<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT H_ReplicationBy2<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT VerticalCutOff<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT VSyncPolarity<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>      <span class="hl slc">//0=Active High, 1=Active Low</span>
  USHORT HSyncPolarity<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>      <span class="hl slc">//0=Active High, 1=Active Low</span>
  USHORT HorizontalCutOff<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
<span class="hl ppc">#else</span>
  USHORT HorizontalCutOff<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT HSyncPolarity<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>      <span class="hl slc">//0=Active High, 1=Active Low</span>
  USHORT VSyncPolarity<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>      <span class="hl slc">//0=Active High, 1=Active Low</span>
  USHORT VerticalCutOff<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT H_ReplicationBy2<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT V_ReplicationBy2<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT CompositeSync<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT Interlace<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT DoubleClock<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT RGB888<span class="hl opt">:</span><span class="hl num">1</span><span class="hl opt">;</span>
  USHORT Reserved<span class="hl opt">:</span><span class="hl num">6</span><span class="hl opt">;</span>           
<span class="hl ppc">#endif</span>
<span class="hl opt">}</span>ATOM_MODE_MISC_INFO<span class="hl opt">;</span>
  
<span class="hl kwc">typedef</span> <span class="hl kwb">union</span> _ATOM_MODE_MISC_INFO_ACCESS
<span class="hl opt">{</span> 
  ATOM_MODE_MISC_INFO sbfAccess<span class="hl opt">;</span>
  USHORT              usAccess<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_MODE_MISC_INFO_ACCESS<span class="hl opt">;</span>
  
<span class="hl ppc">#else</span>
  
<span class="hl kwc">typedef</span> <span class="hl kwb">union</span> _ATOM_MODE_MISC_INFO_ACCESS
<span class="hl opt">{</span> 
  USHORT              usAccess<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_MODE_MISC_INFO_ACCESS<span class="hl opt">;</span>
   
<span class="hl ppc">#endif</span>

<span class="hl slc">// usModeMiscInfo-</span>
<span class="hl ppc">#define ATOM_H_CUTOFF           0x01</span>
<span class="hl ppc">#define ATOM_HSYNC_POLARITY     0x02</span>             <span class="hl slc">//0=Active High, 1=Active Low</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_VSYNC_POLARITY     0x04</span>             <span class="hl slc">//0=Active High, 1=Active Low</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_V_CUTOFF           0x08</span>
<span class="hl ppc">#define ATOM_H_REPLICATIONBY2   0x10</span>
<span class="hl ppc">#define ATOM_V_REPLICATIONBY2   0x20</span>
<span class="hl ppc">#define ATOM_COMPOSITESYNC      0x40</span>
<span class="hl ppc">#define ATOM_INTERLACE          0x80</span>
<span class="hl ppc">#define ATOM_DOUBLE_CLOCK_MODE  0x100</span>
<span class="hl ppc">#define ATOM_RGB888_MODE        0x200</span>

<span class="hl slc">//usRefreshRate-</span>
<span class="hl ppc">#define ATOM_REFRESH_43         43</span>
<span class="hl ppc">#define ATOM_REFRESH_47         47</span>
<span class="hl ppc">#define ATOM_REFRESH_56         56	</span>
<span class="hl ppc">#define ATOM_REFRESH_60         60</span>
<span class="hl ppc">#define ATOM_REFRESH_65         65</span>
<span class="hl ppc">#define ATOM_REFRESH_70         70</span>
<span class="hl ppc">#define ATOM_REFRESH_72         72</span>
<span class="hl ppc">#define ATOM_REFRESH_75         75</span>
<span class="hl ppc">#define ATOM_REFRESH_85         85</span>

<span class="hl slc">// ATOM_MODE_TIMING data are exactly the same as VESA timing data.</span>
<span class="hl slc">// Translation from EDID to ATOM_MODE_TIMING, use the following formula.</span>
<span class="hl slc">//</span>
<span class="hl slc">//	VESA_HTOTAL			=	VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK</span>
<span class="hl slc">//						=	EDID_HA + EDID_HBL</span>
<span class="hl slc">//	VESA_HDISP			=	VESA_ACTIVE	=	EDID_HA</span>
<span class="hl slc">//	VESA_HSYNC_START	=	VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH</span>
<span class="hl slc">//						=	EDID_HA + EDID_HSO</span>
<span class="hl slc">//	VESA_HSYNC_WIDTH	=	VESA_HSYNC_TIME	=	EDID_HSPW</span>
<span class="hl slc">//	VESA_BORDER			=	EDID_BORDER</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structure used in SetCRTC_UsingDTDTimingTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _SET_CRTC_USING_DTD_TIMING_PARAMETERS
<span class="hl opt">{</span>
  USHORT  usH_Size<span class="hl opt">;</span>
  USHORT  usH_Blanking_Time<span class="hl opt">;</span>
  USHORT  usV_Size<span class="hl opt">;</span>
  USHORT  usV_Blanking_Time<span class="hl opt">;</span>			
  USHORT  usH_SyncOffset<span class="hl opt">;</span>
  USHORT  usH_SyncWidth<span class="hl opt">;</span>
  USHORT  usV_SyncOffset<span class="hl opt">;</span>
  USHORT  usV_SyncWidth<span class="hl opt">;</span>
  ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo<span class="hl opt">;</span>  
  UCHAR   ucH_Border<span class="hl opt">;</span>         <span class="hl slc">// From DFP EDID</span>
  UCHAR   ucV_Border<span class="hl opt">;</span>
  UCHAR   ucCRTC<span class="hl opt">;</span>             <span class="hl slc">// ATOM_CRTC1 or ATOM_CRTC2  </span>
  UCHAR   ucPadding<span class="hl opt">[</span><span class="hl num">3</span><span class="hl opt">];</span>
<span class="hl opt">}</span>SET_CRTC_USING_DTD_TIMING_PARAMETERS<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structure used in SetCRTC_TimingTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _SET_CRTC_TIMING_PARAMETERS
<span class="hl opt">{</span>
  USHORT                      usH_Total<span class="hl opt">;</span>        <span class="hl slc">// horizontal total</span>
  USHORT                      usH_Disp<span class="hl opt">;</span>         <span class="hl slc">// horizontal display</span>
  USHORT                      usH_SyncStart<span class="hl opt">;</span>    <span class="hl slc">// horozontal Sync start</span>
  USHORT                      usH_SyncWidth<span class="hl opt">;</span>    <span class="hl slc">// horizontal Sync width</span>
  USHORT                      usV_Total<span class="hl opt">;</span>        <span class="hl slc">// vertical total</span>
  USHORT                      usV_Disp<span class="hl opt">;</span>         <span class="hl slc">// vertical display</span>
  USHORT                      usV_SyncStart<span class="hl opt">;</span>    <span class="hl slc">// vertical Sync start</span>
  USHORT                      usV_SyncWidth<span class="hl opt">;</span>    <span class="hl slc">// vertical Sync width</span>
  ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo<span class="hl opt">;</span>
  UCHAR                       ucCRTC<span class="hl opt">;</span>           <span class="hl slc">// ATOM_CRTC1 or ATOM_CRTC2</span>
  UCHAR                       ucOverscanRight<span class="hl opt">;</span>  <span class="hl slc">// right</span>
  UCHAR                       ucOverscanLeft<span class="hl opt">;</span>   <span class="hl slc">// left</span>
  UCHAR                       ucOverscanBottom<span class="hl opt">;</span> <span class="hl slc">// bottom</span>
  UCHAR                       ucOverscanTop<span class="hl opt">;</span>    <span class="hl slc">// top</span>
  UCHAR                       ucReserved<span class="hl opt">;</span>
<span class="hl opt">}</span>SET_CRTC_TIMING_PARAMETERS<span class="hl opt">;</span>
<span class="hl ppc">#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structure used in StandardVESA_TimingTable</span>
<span class="hl slc">//                   AnalogTV_InfoTable </span>
<span class="hl slc">//                   ComponentVideoInfoTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_MODE_TIMING
<span class="hl opt">{</span>
  USHORT  usCRTC_H_Total<span class="hl opt">;</span>
  USHORT  usCRTC_H_Disp<span class="hl opt">;</span>
  USHORT  usCRTC_H_SyncStart<span class="hl opt">;</span>
  USHORT  usCRTC_H_SyncWidth<span class="hl opt">;</span>
  USHORT  usCRTC_V_Total<span class="hl opt">;</span>
  USHORT  usCRTC_V_Disp<span class="hl opt">;</span>
  USHORT  usCRTC_V_SyncStart<span class="hl opt">;</span>
  USHORT  usCRTC_V_SyncWidth<span class="hl opt">;</span>
  USHORT  usPixelClock<span class="hl opt">;</span>					                 <span class="hl slc">//in 10Khz unit</span>
  ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo<span class="hl opt">;</span>
  USHORT  usCRTC_OverscanRight<span class="hl opt">;</span>
  USHORT  usCRTC_OverscanLeft<span class="hl opt">;</span>
  USHORT  usCRTC_OverscanBottom<span class="hl opt">;</span>
  USHORT  usCRTC_OverscanTop<span class="hl opt">;</span>
  USHORT  usReserve<span class="hl opt">;</span>
  UCHAR   ucInternalModeNumber<span class="hl opt">;</span>
  UCHAR   ucRefreshRate<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_MODE_TIMING<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_DTD_FORMAT
<span class="hl opt">{</span>
  USHORT  usPixClk<span class="hl opt">;</span>
  USHORT  usHActive<span class="hl opt">;</span>
  USHORT  usHBlanking_Time<span class="hl opt">;</span>
  USHORT  usVActive<span class="hl opt">;</span>
  USHORT  usVBlanking_Time<span class="hl opt">;</span>			
  USHORT  usHSyncOffset<span class="hl opt">;</span>
  USHORT  usHSyncWidth<span class="hl opt">;</span>
  USHORT  usVSyncOffset<span class="hl opt">;</span>
  USHORT  usVSyncWidth<span class="hl opt">;</span>
  USHORT  usImageHSize<span class="hl opt">;</span>
  USHORT  usImageVSize<span class="hl opt">;</span>
  UCHAR   ucHBorder<span class="hl opt">;</span>
  UCHAR   ucVBorder<span class="hl opt">;</span>
  ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo<span class="hl opt">;</span>
  UCHAR   ucInternalModeNumber<span class="hl opt">;</span>
  UCHAR   ucRefreshRate<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_DTD_FORMAT<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structure used in LVDS_InfoTable </span>
<span class="hl slc">//  * Need a document to describe this table</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl ppc">#define SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004</span>
<span class="hl ppc">#define SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008</span>
<span class="hl ppc">#define SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010</span>
<span class="hl ppc">#define SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020</span>

<span class="hl slc">//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. </span>
<span class="hl slc">//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL </span>
<span class="hl ppc">#define	LCDPANEL_CAP_READ_EDID									0x1</span>

<span class="hl slc">//ucTableFormatRevision=1</span>
<span class="hl slc">//ucTableContentRevision=1</span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_LVDS_INFO
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER sHeader<span class="hl opt">;</span>  
  ATOM_DTD_FORMAT     sLCDTiming<span class="hl opt">;</span>
  USHORT              usModePatchTableOffset<span class="hl opt">;</span>
  USHORT              usSupportedRefreshRate<span class="hl opt">;</span>     <span class="hl slc">//Refer to panel info table in ATOMBIOS extension Spec.</span>
  USHORT              usOffDelayInMs<span class="hl opt">;</span>
  UCHAR               ucPowerSequenceDigOntoDEin10Ms<span class="hl opt">;</span>
  UCHAR               ucPowerSequenceDEtoBLOnin10Ms<span class="hl opt">;</span>
  UCHAR               ucLVDS_Misc<span class="hl opt">;</span>               <span class="hl slc">// Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}</span>
                                                 <span class="hl slc">// Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}</span>
                                                 <span class="hl slc">// Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}</span>
                                                 <span class="hl slc">// Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}</span>
  UCHAR               ucPanelDefaultRefreshRate<span class="hl opt">;</span>
  UCHAR               ucPanelIdentification<span class="hl opt">;</span>
  UCHAR               ucSS_Id<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_LVDS_INFO<span class="hl opt">;</span>

<span class="hl slc">//ucTableFormatRevision=1</span>
<span class="hl slc">//ucTableContentRevision=2</span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_LVDS_INFO_V12
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER sHeader<span class="hl opt">;</span>  
  ATOM_DTD_FORMAT     sLCDTiming<span class="hl opt">;</span>
  USHORT              usExtInfoTableOffset<span class="hl opt">;</span>
  USHORT              usSupportedRefreshRate<span class="hl opt">;</span>     <span class="hl slc">//Refer to panel info table in ATOMBIOS extension Spec.</span>
  USHORT              usOffDelayInMs<span class="hl opt">;</span>
  UCHAR               ucPowerSequenceDigOntoDEin10Ms<span class="hl opt">;</span>
  UCHAR               ucPowerSequenceDEtoBLOnin10Ms<span class="hl opt">;</span>
  UCHAR               ucLVDS_Misc<span class="hl opt">;</span>               <span class="hl slc">// Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}</span>
                                                 <span class="hl slc">// Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}</span>
                                                 <span class="hl slc">// Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}</span>
                                                 <span class="hl slc">// Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}</span>
  UCHAR               ucPanelDefaultRefreshRate<span class="hl opt">;</span>
  UCHAR               ucPanelIdentification<span class="hl opt">;</span>
  UCHAR               ucSS_Id<span class="hl opt">;</span>
  USHORT              usLCDVenderID<span class="hl opt">;</span>
  USHORT              usLCDProductID<span class="hl opt">;</span>
  UCHAR               ucLCDPanel_SpecialHandlingCap<span class="hl opt">;</span> 
	UCHAR								ucPanelInfoSize<span class="hl opt">;</span>					<span class="hl slc">//  start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable</span>
  UCHAR               ucReserved<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>
<span class="hl opt">}</span>ATOM_LVDS_INFO_V12<span class="hl opt">;</span>

<span class="hl ppc">#define ATOM_LVDS_INFO_LAST  ATOM_LVDS_INFO_V12</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_PATCH_RECORD_MODE
<span class="hl opt">{</span>
  UCHAR     ucRecordType<span class="hl opt">;</span>
  USHORT    usHDisp<span class="hl opt">;</span>
  USHORT    usVDisp<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_PATCH_RECORD_MODE<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_LCD_RTS_RECORD
<span class="hl opt">{</span>
  UCHAR     ucRecordType<span class="hl opt">;</span>
  UCHAR     ucRTSValue<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_LCD_RTS_RECORD<span class="hl opt">;</span>

<span class="hl slc">//!! If the record below exits, it shoud always be the first record for easy use in command table!!! </span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_LCD_MODE_CONTROL_CAP
<span class="hl opt">{</span>
  UCHAR     ucRecordType<span class="hl opt">;</span>
  USHORT    usLCDCap<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_LCD_MODE_CONTROL_CAP<span class="hl opt">;</span>

<span class="hl ppc">#define LCD_MODE_CAP_BL_OFF                   1</span>
<span class="hl ppc">#define LCD_MODE_CAP_CRTC_OFF                 2</span>
<span class="hl ppc">#define LCD_MODE_CAP_PANEL_OFF                4</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_FAKE_EDID_PATCH_RECORD
<span class="hl opt">{</span>
  UCHAR ucRecordType<span class="hl opt">;</span>
  UCHAR ucFakeEDIDLength<span class="hl opt">;</span>
  UCHAR ucFakeEDIDString<span class="hl opt">[</span><span class="hl num">1</span><span class="hl opt">];</span>    <span class="hl slc">// This actually has ucFakeEdidLength elements.</span>
<span class="hl opt">}</span> ATOM_FAKE_EDID_PATCH_RECORD<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_PANEL_RESOLUTION_PATCH_RECORD
<span class="hl opt">{</span>
   UCHAR    ucRecordType<span class="hl opt">;</span>
   USHORT		usHSize<span class="hl opt">;</span>
   USHORT		usVSize<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_PANEL_RESOLUTION_PATCH_RECORD<span class="hl opt">;</span>

<span class="hl ppc">#define LCD_MODE_PATCH_RECORD_MODE_TYPE       1</span>
<span class="hl ppc">#define LCD_RTS_RECORD_TYPE                   2</span>
<span class="hl ppc">#define LCD_CAP_RECORD_TYPE                   3</span>
<span class="hl ppc">#define LCD_FAKE_EDID_PATCH_RECORD_TYPE       4</span>
<span class="hl ppc">#define LCD_PANEL_RESOLUTION_RECORD_TYPE      5</span>
<span class="hl ppc">#define ATOM_RECORD_END_TYPE                  0xFF</span>

<span class="hl com">/****************************Spread Spectrum Info Table Definitions **********************/</span>

<span class="hl slc">//ucTableFormatRevision=1</span>
<span class="hl slc">//ucTableContentRevision=2</span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
<span class="hl opt">{</span>
  USHORT              usSpreadSpectrumPercentage<span class="hl opt">;</span> 
  UCHAR               ucSpreadSpectrumType<span class="hl opt">;</span>	    <span class="hl slc">//Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD</span>
  UCHAR               ucSS_Step<span class="hl opt">;</span>
  UCHAR               ucSS_Delay<span class="hl opt">;</span>
  UCHAR               ucSS_Id<span class="hl opt">;</span>
  UCHAR               ucRecommandedRef_Div<span class="hl opt">;</span>
  UCHAR               ucSS_Range<span class="hl opt">;</span>               <span class="hl slc">//it was reserved for V11</span>
<span class="hl opt">}</span>ATOM_SPREAD_SPECTRUM_ASSIGNMENT<span class="hl opt">;</span>

<span class="hl ppc">#define ATOM_MAX_SS_ENTRY                      16</span>
<span class="hl ppc">#define ATOM_DP_SS_ID1												 0x0f1</span>			<span class="hl slc">// SS modulation freq=30k</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_DP_SS_ID2												 0x0f2</span>			<span class="hl slc">// SS modulation freq=33k</span>
<span class="hl ppc"></span>

<span class="hl ppc">#define ATOM_SS_DOWN_SPREAD_MODE_MASK          0x00000000</span>
<span class="hl ppc">#define ATOM_SS_DOWN_SPREAD_MODE               0x00000000</span>
<span class="hl ppc">#define ATOM_SS_CENTRE_SPREAD_MODE_MASK        0x00000001</span>
<span class="hl ppc">#define ATOM_SS_CENTRE_SPREAD_MODE             0x00000001</span>
<span class="hl ppc">#define ATOM_INTERNAL_SS_MASK                  0x00000000</span>
<span class="hl ppc">#define ATOM_EXTERNAL_SS_MASK                  0x00000002</span>
<span class="hl ppc">#define EXEC_SS_STEP_SIZE_SHIFT                2</span>
<span class="hl ppc">#define EXEC_SS_DELAY_SHIFT                    4    </span>
<span class="hl ppc">#define ACTIVEDATA_TO_BLON_DELAY_SHIFT         4</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_SPREAD_SPECTRUM_INFO
<span class="hl opt">{</span> 
  ATOM_COMMON_TABLE_HEADER	sHeader<span class="hl opt">;</span>
  ATOM_SPREAD_SPECTRUM_ASSIGNMENT   asSS_Info<span class="hl opt">[</span>ATOM_MAX_SS_ENTRY<span class="hl opt">];</span>
<span class="hl opt">}</span>ATOM_SPREAD_SPECTRUM_INFO<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structure used in AnalogTV_InfoTable (Top level)</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">//ucTVBootUpDefaultStd definiton:</span>

<span class="hl slc">//ATOM_TV_NTSC                1</span>
<span class="hl slc">//ATOM_TV_NTSCJ               2</span>
<span class="hl slc">//ATOM_TV_PAL                 3</span>
<span class="hl slc">//ATOM_TV_PALM                4</span>
<span class="hl slc">//ATOM_TV_PALCN               5</span>
<span class="hl slc">//ATOM_TV_PALN                6</span>
<span class="hl slc">//ATOM_TV_PAL60               7</span>
<span class="hl slc">//ATOM_TV_SECAM               8</span>

<span class="hl slc">//ucTVSuppportedStd definition:</span>
<span class="hl ppc">#define NTSC_SUPPORT          0x1</span>
<span class="hl ppc">#define NTSCJ_SUPPORT         0x2</span>

<span class="hl ppc">#define PAL_SUPPORT           0x4</span>
<span class="hl ppc">#define PALM_SUPPORT          0x8</span>
<span class="hl ppc">#define PALCN_SUPPORT         0x10</span>
<span class="hl ppc">#define PALN_SUPPORT          0x20</span>
<span class="hl ppc">#define PAL60_SUPPORT         0x40</span>
<span class="hl ppc">#define SECAM_SUPPORT         0x80</span>

<span class="hl ppc">#define MAX_SUPPORTED_TV_TIMING    2</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_ANALOG_TV_INFO
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER sHeader<span class="hl opt">;</span>  
  UCHAR                    ucTV_SupportedStandard<span class="hl opt">;</span>
  UCHAR                    ucTV_BootUpDefaultStandard<span class="hl opt">;</span> 
  UCHAR                    ucExt_TV_ASIC_ID<span class="hl opt">;</span>
  UCHAR                    ucExt_TV_ASIC_SlaveAddr<span class="hl opt">;</span>
  <span class="hl com">/*ATOM_DTD_FORMAT          aModeTimings[MAX_SUPPORTED_TV_TIMING];*/</span>
  ATOM_MODE_TIMING         aModeTimings<span class="hl opt">[</span>MAX_SUPPORTED_TV_TIMING<span class="hl opt">];</span>
<span class="hl opt">}</span>ATOM_ANALOG_TV_INFO<span class="hl opt">;</span>


<span class="hl com">/**************************************************************************/</span>
<span class="hl slc">// VRAM usage and their defintions</span>

<span class="hl slc">// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.</span>
<span class="hl slc">// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.</span>
<span class="hl slc">// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!</span>
<span class="hl slc">// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR</span>
<span class="hl slc">// To Bios:  ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR-&gt;MM_INDEX </span>

<span class="hl ppc">#ifndef VESA_MEMORY_IN_64K_BLOCK</span>
<span class="hl ppc">#define VESA_MEMORY_IN_64K_BLOCK        0x100</span>       <span class="hl slc">//256*64K=16Mb (Max. VESA memory is 16Mb!)</span>
<span class="hl ppc"></span><span class="hl ppc">#endif</span>

<span class="hl ppc">#define ATOM_EDID_RAW_DATASIZE          256</span>         <span class="hl slc">//In Bytes</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_HWICON_SURFACE_SIZE        4096</span>        <span class="hl slc">//In Bytes</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_HWICON_INFOTABLE_SIZE      32</span>
<span class="hl ppc">#define MAX_DTD_MODE_IN_VRAM            6</span>
<span class="hl ppc">#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE  (MAX_DTD_MODE_IN_VRAM*28)</span>    <span class="hl slc">//28= (SIZEOF ATOM_DTD_FORMAT) </span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_STD_MODE_SUPPORT_TBL_SIZE  32*8</span>                         <span class="hl slc">//32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)</span>
<span class="hl ppc"></span><span class="hl ppc">#define DFP_ENCODER_TYPE_OFFSET					0x80</span>
<span class="hl ppc">#define DP_ENCODER_LANE_NUM_OFFSET			0x84</span>
<span class="hl ppc">#define DP_ENCODER_LINK_RATE_OFFSET			0x88</span>

<span class="hl ppc">#define ATOM_HWICON1_SURFACE_ADDR       0</span>
<span class="hl ppc">#define ATOM_HWICON2_SURFACE_ADDR       (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)</span>
<span class="hl ppc">#define ATOM_HWICON_INFOTABLE_ADDR      (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)</span>
<span class="hl ppc">#define ATOM_CRT1_EDID_ADDR             (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)</span>
<span class="hl ppc">#define ATOM_CRT1_DTD_MODE_TBL_ADDR     (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)</span>
<span class="hl ppc">#define ATOM_CRT1_STD_MODE_TBL_ADDR	    (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)</span>

<span class="hl ppc">#define ATOM_LCD1_EDID_ADDR             (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)</span>
<span class="hl ppc">#define ATOM_LCD1_DTD_MODE_TBL_ADDR     (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)</span>
<span class="hl ppc">#define ATOM_LCD1_STD_MODE_TBL_ADDR   	(ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)</span>

<span class="hl ppc">#define ATOM_TV1_DTD_MODE_TBL_ADDR      (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)</span>

<span class="hl ppc">#define ATOM_DFP1_EDID_ADDR             (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)</span>
<span class="hl ppc">#define ATOM_DFP1_DTD_MODE_TBL_ADDR     (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)</span>
<span class="hl ppc">#define ATOM_DFP1_STD_MODE_TBL_ADDR	    (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)</span>

<span class="hl ppc">#define ATOM_CRT2_EDID_ADDR             (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)</span>
<span class="hl ppc">#define ATOM_CRT2_DTD_MODE_TBL_ADDR     (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)</span>
<span class="hl ppc">#define ATOM_CRT2_STD_MODE_TBL_ADDR	    (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)</span>

<span class="hl ppc">#define ATOM_LCD2_EDID_ADDR             (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)</span>
<span class="hl ppc">#define ATOM_LCD2_DTD_MODE_TBL_ADDR     (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)</span>
<span class="hl ppc">#define ATOM_LCD2_STD_MODE_TBL_ADDR   	(ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)</span>

<span class="hl ppc">#define ATOM_TV2_EDID_ADDR              (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)</span>
<span class="hl ppc">#define ATOM_TV2_DTD_MODE_TBL_ADDR      (ATOM_TV2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)</span>
<span class="hl ppc">#define ATOM_TV2_STD_MODE_TBL_ADDR  	  (ATOM_TV2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)</span>

<span class="hl ppc">#define ATOM_DFP2_EDID_ADDR             (ATOM_TV2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)</span>
<span class="hl ppc">#define ATOM_DFP2_DTD_MODE_TBL_ADDR     (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)</span>
<span class="hl ppc">#define ATOM_DFP2_STD_MODE_TBL_ADDR     (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)</span>

<span class="hl ppc">#define ATOM_CV_EDID_ADDR               (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)</span>
<span class="hl ppc">#define ATOM_CV_DTD_MODE_TBL_ADDR       (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)</span>
<span class="hl ppc">#define ATOM_CV_STD_MODE_TBL_ADDR       (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)</span>

<span class="hl ppc">#define ATOM_DFP3_EDID_ADDR             (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)</span>
<span class="hl ppc">#define ATOM_DFP3_DTD_MODE_TBL_ADDR     (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)</span>
<span class="hl ppc">#define ATOM_DFP3_STD_MODE_TBL_ADDR     (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)</span>

<span class="hl ppc">#define ATOM_DFP4_EDID_ADDR             (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)</span>
<span class="hl ppc">#define ATOM_DFP4_DTD_MODE_TBL_ADDR     (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)</span>
<span class="hl ppc">#define ATOM_DFP4_STD_MODE_TBL_ADDR     (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)</span>

<span class="hl ppc">#define ATOM_DFP5_EDID_ADDR             (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)</span>
<span class="hl ppc">#define ATOM_DFP5_DTD_MODE_TBL_ADDR     (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)</span>
<span class="hl ppc">#define ATOM_DFP5_STD_MODE_TBL_ADDR     (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)</span>

<span class="hl ppc">#define ATOM_DP_TRAINING_TBL_ADDR				(ATOM_DFP5_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE)       </span>

<span class="hl ppc">#define ATOM_STACK_STORAGE_START        (ATOM_DP_TRAINING_TBL_ADDR+256)       </span>
<span class="hl ppc">#define ATOM_STACK_STORAGE_END          ATOM_STACK_STORAGE_START+512        </span>

<span class="hl slc">//The size below is in Kb!</span>
<span class="hl ppc">#define ATOM_VRAM_RESERVE_SIZE         ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)&gt;&gt;10)+4)&amp;0xFFFC)</span>
   
<span class="hl ppc">#define	ATOM_VRAM_OPERATION_FLAGS_MASK         0xC0000000L</span>
<span class="hl ppc">#define ATOM_VRAM_OPERATION_FLAGS_SHIFT        30</span>
<span class="hl ppc">#define	ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION   0x1</span>
<span class="hl ppc">#define	ATOM_VRAM_BLOCK_NEEDS_RESERVATION      0x0</span>

<span class="hl com">/***********************************************************************************/</span>	
<span class="hl slc">// Structure used in VRAM_UsageByFirmwareTable</span>
<span class="hl slc">// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm</span>
<span class="hl slc">//        at running time.   </span>
<span class="hl slc">// note2: From RV770, the memory is more than 32bit addressable, so we will change </span>
<span class="hl slc">//        ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains </span>
<span class="hl slc">//        exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware </span>
<span class="hl slc">//        (in offset to start of memory address) is KB aligned instead of byte aligend.</span>
<span class="hl com">/***********************************************************************************/</span>	
<span class="hl ppc">#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO			1</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_FIRMWARE_VRAM_RESERVE_INFO
<span class="hl opt">{</span>
  ULONG   ulStartAddrUsedByFirmware<span class="hl opt">;</span>
  USHORT  usFirmwareUseInKb<span class="hl opt">;</span>
  USHORT  usReserved<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_FIRMWARE_VRAM_RESERVE_INFO<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_VRAM_USAGE_BY_FIRMWARE
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER sHeader<span class="hl opt">;</span>  
  ATOM_FIRMWARE_VRAM_RESERVE_INFO	asFirmwareVramReserveInfo<span class="hl opt">[</span>ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO<span class="hl opt">];</span>
<span class="hl opt">}</span>ATOM_VRAM_USAGE_BY_FIRMWARE<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structure used in GPIO_Pin_LUTTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_GPIO_PIN_ASSIGNMENT
<span class="hl opt">{</span>
  USHORT                   usGpioPin_AIndex<span class="hl opt">;</span>
  UCHAR                    ucGpioPinBitShift<span class="hl opt">;</span>
  UCHAR                    ucGPIO_ID<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_GPIO_PIN_ASSIGNMENT<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_GPIO_PIN_LUT
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER  sHeader<span class="hl opt">;</span>
  ATOM_GPIO_PIN_ASSIGNMENT	asGPIO_Pin<span class="hl opt">[</span><span class="hl num">1</span><span class="hl opt">];</span>
<span class="hl opt">}</span>ATOM_GPIO_PIN_LUT<span class="hl opt">;</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structure used in ComponentVideoInfoTable	</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl ppc">#define GPIO_PIN_ACTIVE_HIGH          0x1</span>

<span class="hl ppc">#define MAX_SUPPORTED_CV_STANDARDS    5</span>

<span class="hl slc">// definitions for ATOM_D_INFO.ucSettings</span>
<span class="hl ppc">#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK  0x1F</span>    <span class="hl slc">// [4:0]</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_GPIO_SETTINGS_RESERVED_MASK  0x60</span>    <span class="hl slc">// [6:5] = must be zeroed out</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_GPIO_SETTINGS_ACTIVE_MASK    0x80</span>    <span class="hl slc">// [7]</span>
<span class="hl ppc"></span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_GPIO_INFO
<span class="hl opt">{</span>
  USHORT  usAOffset<span class="hl opt">;</span>
  UCHAR   ucSettings<span class="hl opt">;</span>
  UCHAR   ucReserved<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_GPIO_INFO<span class="hl opt">;</span>

<span class="hl slc">// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)</span>
<span class="hl ppc">#define ATOM_CV_RESTRICT_FORMAT_SELECTION           0x2</span>

<span class="hl slc">// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i</span>
<span class="hl ppc">#define ATOM_GPIO_DEFAULT_MODE_EN                   0x80</span> <span class="hl slc">//[7];</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_GPIO_SETTING_PERMODE_MASK              0x7F</span> <span class="hl slc">//[6:0]</span>
<span class="hl ppc"></span>
<span class="hl slc">// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode</span>
<span class="hl slc">//Line 3 out put 5V.</span>
<span class="hl ppc">#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A       0x01</span>     <span class="hl slc">//represent gpio 3 state for 16:9</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B       0x02</span>     <span class="hl slc">//represent gpio 4 state for 16:9</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT   0x0   </span>

<span class="hl slc">//Line 3 out put 2.2V              </span>
<span class="hl ppc">#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04</span>     <span class="hl slc">//represent gpio 3 state for 4:3 Letter box</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08</span>     <span class="hl slc">//represent gpio 4 state for 4:3 Letter box</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2     </span>

<span class="hl slc">//Line 3 out put 0V</span>
<span class="hl ppc">#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A        0x10</span>     <span class="hl slc">//represent gpio 3 state for 4:3</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B        0x20</span>     <span class="hl slc">//represent gpio 4 state for 4:3</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT    0x4 </span>

<span class="hl ppc">#define ATOM_CV_LINE3_ASPECTRATIO_MASK              0x3F</span>     <span class="hl slc">// bit [5:0]</span>
<span class="hl ppc"></span>
<span class="hl ppc">#define ATOM_CV_LINE3_ASPECTRATIO_EXIST             0x80</span>     <span class="hl slc">//bit 7</span>
<span class="hl ppc"></span>
<span class="hl slc">//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.</span>
<span class="hl ppc">#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A   3</span>   <span class="hl slc">//bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B   4</span>   <span class="hl slc">//bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.</span>
<span class="hl ppc"></span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_COMPONENT_VIDEO_INFO
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER sHeader<span class="hl opt">;</span>
  USHORT             usMask_PinRegisterIndex<span class="hl opt">;</span>
  USHORT             usEN_PinRegisterIndex<span class="hl opt">;</span>
  USHORT             usY_PinRegisterIndex<span class="hl opt">;</span>
  USHORT             usA_PinRegisterIndex<span class="hl opt">;</span>
  UCHAR              ucBitShift<span class="hl opt">;</span>
  UCHAR              ucPinActiveState<span class="hl opt">;</span>  <span class="hl slc">//ucPinActiveState: Bit0=1 active high, =0 active low</span>
  ATOM_DTD_FORMAT    sReserved<span class="hl opt">;</span>         <span class="hl slc">// must be zeroed out</span>
  UCHAR              ucMiscInfo<span class="hl opt">;</span>
  UCHAR              uc480i<span class="hl opt">;</span>
  UCHAR              uc480p<span class="hl opt">;</span>
  UCHAR              uc720p<span class="hl opt">;</span>
  UCHAR              uc1080i<span class="hl opt">;</span>
  UCHAR              ucLetterBoxMode<span class="hl opt">;</span>
  UCHAR              ucReserved<span class="hl opt">[</span><span class="hl num">3</span><span class="hl opt">];</span>
  UCHAR              ucNumOfWbGpioBlocks<span class="hl opt">;</span> <span class="hl slc">//For Component video D-Connector support. If zere, NTSC type connector</span>
  ATOM_GPIO_INFO     aWbGpioStateBlock<span class="hl opt">[</span>MAX_SUPPORTED_CV_STANDARDS<span class="hl opt">];</span>
  ATOM_DTD_FORMAT    aModeTimings<span class="hl opt">[</span>MAX_SUPPORTED_CV_STANDARDS<span class="hl opt">];</span>
<span class="hl opt">}</span>ATOM_COMPONENT_VIDEO_INFO<span class="hl opt">;</span>

<span class="hl slc">//ucTableFormatRevision=2</span>
<span class="hl slc">//ucTableContentRevision=1</span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_COMPONENT_VIDEO_INFO_V21
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER sHeader<span class="hl opt">;</span>
  UCHAR              ucMiscInfo<span class="hl opt">;</span>
  UCHAR              uc480i<span class="hl opt">;</span>
  UCHAR              uc480p<span class="hl opt">;</span>
  UCHAR              uc720p<span class="hl opt">;</span>
  UCHAR              uc1080i<span class="hl opt">;</span>
  UCHAR              ucReserved<span class="hl opt">;</span>
  UCHAR              ucLetterBoxMode<span class="hl opt">;</span>
  UCHAR              ucNumOfWbGpioBlocks<span class="hl opt">;</span> <span class="hl slc">//For Component video D-Connector support. If zere, NTSC type connector</span>
  ATOM_GPIO_INFO     aWbGpioStateBlock<span class="hl opt">[</span>MAX_SUPPORTED_CV_STANDARDS<span class="hl opt">];</span>
  ATOM_DTD_FORMAT    aModeTimings<span class="hl opt">[</span>MAX_SUPPORTED_CV_STANDARDS<span class="hl opt">];</span>
<span class="hl opt">}</span>ATOM_COMPONENT_VIDEO_INFO_V21<span class="hl opt">;</span>

<span class="hl ppc">#define ATOM_COMPONENT_VIDEO_INFO_LAST  ATOM_COMPONENT_VIDEO_INFO_V21</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// Structure used in object_InfoTable</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_OBJECT_HEADER
<span class="hl opt">{</span> 
  ATOM_COMMON_TABLE_HEADER	sHeader<span class="hl opt">;</span>
  USHORT                    usDeviceSupport<span class="hl opt">;</span>
  USHORT                    usConnectorObjectTableOffset<span class="hl opt">;</span>
  USHORT                    usRouterObjectTableOffset<span class="hl opt">;</span>
  USHORT                    usEncoderObjectTableOffset<span class="hl opt">;</span>
  USHORT                    usProtectionObjectTableOffset<span class="hl opt">;</span> <span class="hl slc">//only available when Protection block is independent.</span>
  USHORT                    usDisplayPathTableOffset<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_OBJECT_HEADER<span class="hl opt">;</span>


<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_DISPLAY_OBJECT_PATH
<span class="hl opt">{</span>
  USHORT    usDeviceTag<span class="hl opt">;</span>                                   <span class="hl slc">//supported device </span>
  USHORT    usSize<span class="hl opt">;</span>                                        <span class="hl slc">//the size of ATOM_DISPLAY_OBJECT_PATH</span>
  USHORT    usConnObjectId<span class="hl opt">;</span>                                <span class="hl slc">//Connector Object ID </span>
  USHORT    usGPUObjectId<span class="hl opt">;</span>                                 <span class="hl slc">//GPU ID </span>
  USHORT    usGraphicObjIds<span class="hl opt">[</span><span class="hl num">1</span><span class="hl opt">];</span>                             <span class="hl slc">//1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.</span>
<span class="hl opt">}</span>ATOM_DISPLAY_OBJECT_PATH<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_DISPLAY_OBJECT_PATH_TABLE
<span class="hl opt">{</span>
  UCHAR                           ucNumOfDispPath<span class="hl opt">;</span>
  UCHAR                           ucVersion<span class="hl opt">;</span>
  UCHAR                           ucPadding<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>
  ATOM_DISPLAY_OBJECT_PATH        asDispPath<span class="hl opt">[</span><span class="hl num">1</span><span class="hl opt">];</span>
<span class="hl opt">}</span>ATOM_DISPLAY_OBJECT_PATH_TABLE<span class="hl opt">;</span>


<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_OBJECT                                <span class="hl slc">//each object has this structure    </span>
<span class="hl opt">{</span>
  USHORT              usObjectID<span class="hl opt">;</span>
  USHORT              usSrcDstTableOffset<span class="hl opt">;</span>
  USHORT              usRecordOffset<span class="hl opt">;</span>                     <span class="hl slc">//this pointing to a bunch of records defined below</span>
  USHORT              usReserved<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_OBJECT<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_OBJECT_TABLE                         <span class="hl slc">//Above 4 object table offset pointing to a bunch of objects all have this structure     </span>
<span class="hl opt">{</span>
  UCHAR               ucNumberOfObjects<span class="hl opt">;</span>
  UCHAR               ucPadding<span class="hl opt">[</span><span class="hl num">3</span><span class="hl opt">];</span>
  ATOM_OBJECT         asObjects<span class="hl opt">[</span><span class="hl num">1</span><span class="hl opt">];</span>
<span class="hl opt">}</span>ATOM_OBJECT_TABLE<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT         <span class="hl slc">//usSrcDstTableOffset pointing to this structure</span>
<span class="hl opt">{</span>
  UCHAR               ucNumberOfSrc<span class="hl opt">;</span>
  USHORT              usSrcObjectID<span class="hl opt">[</span><span class="hl num">1</span><span class="hl opt">];</span>
  UCHAR               ucNumberOfDst<span class="hl opt">;</span>
  USHORT              usDstObjectID<span class="hl opt">[</span><span class="hl num">1</span><span class="hl opt">];</span>
<span class="hl opt">}</span>ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT<span class="hl opt">;</span>


<span class="hl slc">//Related definitions, all records are differnt but they have a commond header</span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_COMMON_RECORD_HEADER
<span class="hl opt">{</span>
  UCHAR               ucRecordType<span class="hl opt">;</span>                      <span class="hl slc">//An emun to indicate the record type</span>
  UCHAR               ucRecordSize<span class="hl opt">;</span>                      <span class="hl slc">//The size of the whole record in byte</span>
<span class="hl opt">}</span>ATOM_COMMON_RECORD_HEADER<span class="hl opt">;</span>


<span class="hl ppc">#define ATOM_I2C_RECORD_TYPE                           1         </span>
<span class="hl ppc">#define ATOM_HPD_INT_RECORD_TYPE                       2</span>
<span class="hl ppc">#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE             3</span>
<span class="hl ppc">#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE          4</span>
<span class="hl ppc">#define	ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE	     5</span> <span class="hl slc">//Obsolete, switch to use GPIO_CNTL_RECORD_TYPE</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE          6</span> <span class="hl slc">//Obsolete, switch to use GPIO_CNTL_RECORD_TYPE</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE      7</span>
<span class="hl ppc">#define ATOM_JTAG_RECORD_TYPE                          8</span> <span class="hl slc">//Obsolete, switch to use GPIO_CNTL_RECORD_TYPE</span>
<span class="hl ppc"></span><span class="hl ppc">#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE              9</span>
<span class="hl ppc">#define ATOM_ENCODER_DVO_CF_RECORD_TYPE               10</span>
<span class="hl ppc">#define ATOM_CONNECTOR_CF_RECORD_TYPE                 11</span>
<span class="hl ppc">#define	ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE	      12</span>
<span class="hl ppc">#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE  13</span>
<span class="hl ppc">#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE				14</span>
<span class="hl ppc">#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE					15</span>

<span class="hl slc">//Must be updated when new record type is added,equal to that record definition!</span>
<span class="hl ppc">#define ATOM_MAX_OBJECT_RECORD_NUMBER             ATOM_CONNECTOR_CF_RECORD_TYPE     </span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_I2C_RECORD
<span class="hl opt">{</span>
  ATOM_COMMON_RECORD_HEADER   sheader<span class="hl opt">;</span>
  ATOM_I2C_ID_CONFIG          sucI2cId<span class="hl opt">;</span> 
  UCHAR                       ucI2CAddr<span class="hl opt">;</span>              <span class="hl slc">//The slave address, it&apos;s 0 when the record is attached to connector for DDC</span>
<span class="hl opt">}</span>ATOM_I2C_RECORD<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_HPD_INT_RECORD
<span class="hl opt">{</span>
  ATOM_COMMON_RECORD_HEADER   sheader<span class="hl opt">;</span>
  UCHAR                       ucHPDIntGPIOID<span class="hl opt">;</span>         <span class="hl slc">//Corresponding block in GPIO_PIN_INFO table gives the pin info           </span>
  UCHAR                       ucPluggged_PinState<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_HPD_INT_RECORD<span class="hl opt">;</span>


<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_OUTPUT_PROTECTION_RECORD 
<span class="hl opt">{</span>
  ATOM_COMMON_RECORD_HEADER   sheader<span class="hl opt">;</span>
  UCHAR                       ucProtectionFlag<span class="hl opt">;</span>
  UCHAR                       ucReserved<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_OUTPUT_PROTECTION_RECORD<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_CONNECTOR_DEVICE_TAG
<span class="hl opt">{</span>
  ULONG                       ulACPIDeviceEnum<span class="hl opt">;</span>       <span class="hl slc">//Reserved for now</span>
  USHORT                      usDeviceID<span class="hl opt">;</span>             <span class="hl slc">//This Id is same as &quot;ATOM_DEVICE_XXX_SUPPORT&quot;</span>
  USHORT                      usPadding<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_CONNECTOR_DEVICE_TAG<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_CONNECTOR_DEVICE_TAG_RECORD
<span class="hl opt">{</span>
  ATOM_COMMON_RECORD_HEADER   sheader<span class="hl opt">;</span>
  UCHAR                       ucNumberOfDevice<span class="hl opt">;</span>
  UCHAR                       ucReserved<span class="hl opt">;</span>
  ATOM_CONNECTOR_DEVICE_TAG   asDeviceTag<span class="hl opt">[</span><span class="hl num">1</span><span class="hl opt">];</span>         <span class="hl slc">//This Id is same as &quot;ATOM_DEVICE_XXX_SUPPORT&quot;, 1 is only for allocation</span>
<span class="hl opt">}</span>ATOM_CONNECTOR_DEVICE_TAG_RECORD<span class="hl opt">;</span>


<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
<span class="hl opt">{</span>
  ATOM_COMMON_RECORD_HEADER   sheader<span class="hl opt">;</span>
  UCHAR						            ucConfigGPIOID<span class="hl opt">;</span>
  UCHAR						            ucConfigGPIOState<span class="hl opt">;</span>	    <span class="hl slc">//Set to 1 when it&apos;s active high to enable external flow in</span>
  UCHAR                       ucFlowinGPIPID<span class="hl opt">;</span>
  UCHAR                       ucExtInGPIPID<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_ENCODER_FPGA_CONTROL_RECORD
<span class="hl opt">{</span>
  ATOM_COMMON_RECORD_HEADER   sheader<span class="hl opt">;</span>
  UCHAR                       ucCTL1GPIO_ID<span class="hl opt">;</span>
  UCHAR                       ucCTL1GPIOState<span class="hl opt">;</span>        <span class="hl slc">//Set to 1 when it&apos;s active high</span>
  UCHAR                       ucCTL2GPIO_ID<span class="hl opt">;</span>
  UCHAR                       ucCTL2GPIOState<span class="hl opt">;</span>        <span class="hl slc">//Set to 1 when it&apos;s active high</span>
  UCHAR                       ucCTL3GPIO_ID<span class="hl opt">;</span>
  UCHAR                       ucCTL3GPIOState<span class="hl opt">;</span>        <span class="hl slc">//Set to 1 when it&apos;s active high</span>
  UCHAR                       ucCTLFPGA_IN_ID<span class="hl opt">;</span>
  UCHAR                       ucPadding<span class="hl opt">[</span><span class="hl num">3</span><span class="hl opt">];</span>
<span class="hl opt">}</span>ATOM_ENCODER_FPGA_CONTROL_RECORD<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
<span class="hl opt">{</span>
  ATOM_COMMON_RECORD_HEADER   sheader<span class="hl opt">;</span>
  UCHAR                       ucGPIOID<span class="hl opt">;</span>               <span class="hl slc">//Corresponding block in GPIO_PIN_INFO table gives the pin info </span>
  UCHAR                       ucTVActiveState<span class="hl opt">;</span>        <span class="hl slc">//Indicating when the pin==0 or 1 when TV is connected</span>
<span class="hl opt">}</span>ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_JTAG_RECORD
<span class="hl opt">{</span>
  ATOM_COMMON_RECORD_HEADER   sheader<span class="hl opt">;</span>
  UCHAR                       ucTMSGPIO_ID<span class="hl opt">;</span>
  UCHAR                       ucTMSGPIOState<span class="hl opt">;</span>         <span class="hl slc">//Set to 1 when it&apos;s active high</span>
  UCHAR                       ucTCKGPIO_ID<span class="hl opt">;</span>
  UCHAR                       ucTCKGPIOState<span class="hl opt">;</span>         <span class="hl slc">//Set to 1 when it&apos;s active high</span>
  UCHAR                       ucTDOGPIO_ID<span class="hl opt">;</span>
  UCHAR                       ucTDOGPIOState<span class="hl opt">;</span>         <span class="hl slc">//Set to 1 when it&apos;s active high</span>
  UCHAR                       ucTDIGPIO_ID<span class="hl opt">;</span>
  UCHAR                       ucTDIGPIOState<span class="hl opt">;</span>         <span class="hl slc">//Set to 1 when it&apos;s active high</span>
  UCHAR                       ucPadding<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>
<span class="hl opt">}</span>ATOM_JTAG_RECORD<span class="hl opt">;</span>


<span class="hl slc">//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually</span>
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_GPIO_PIN_CONTROL_PAIR
<span class="hl opt">{</span>
  UCHAR                       ucGPIOID<span class="hl opt">;</span>               <span class="hl slc">// GPIO_ID, find the corresponding ID in GPIO_LUT table</span>
  UCHAR                       ucGPIO_PinState<span class="hl opt">;</span>        <span class="hl slc">// Pin state showing how to set-up the pin</span>
<span class="hl opt">}</span>ATOM_GPIO_PIN_CONTROL_PAIR<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_OBJECT_GPIO_CNTL_RECORD
<span class="hl opt">{</span>
  ATOM_COMMON_RECORD_HEADER   sheader<span class="hl opt">;</span>
  UCHAR                       ucFlags<span class="hl opt">;</span>                <span class="hl slc">// Future expnadibility</span>
  UCHAR                       ucNumberOfPins<span class="hl opt">;</span>         <span class="hl slc">// Number of GPIO pins used to control the object</span>
  ATOM_GPIO_PIN_CONTROL_PAIR  asGpio<span class="hl opt">[</span><span class="hl num">1</span><span class="hl opt">];</span>              <span class="hl slc">// the real gpio pin pair determined by number of pins ucNumberOfPins</span>
<span class="hl opt">}</span>ATOM_OBJECT_GPIO_CNTL_RECORD<span class="hl opt">;</span>

<span class="hl slc">//Definitions for GPIO pin state </span>
<span class="hl ppc">#define GPIO_PIN_TYPE_INPUT             0x00</span>
<span class="hl ppc">#define GPIO_PIN_TYPE_OUTPUT            0x10</span>
<span class="hl ppc">#define GPIO_PIN_TYPE_HW_CONTROL        0x20</span>

<span class="hl slc">//For GPIO_PIN_TYPE_OUTPUT the following is defined </span>
<span class="hl ppc">#define GPIO_PIN_OUTPUT_STATE_MASK      0x01</span>
<span class="hl ppc">#define GPIO_PIN_OUTPUT_STATE_SHIFT     0</span>
<span class="hl ppc">#define GPIO_PIN_STATE_ACTIVE_LOW       0x0</span>
<span class="hl ppc">#define GPIO_PIN_STATE_ACTIVE_HIGH      0x1</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_ENCODER_DVO_CF_RECORD
<span class="hl opt">{</span>
  ATOM_COMMON_RECORD_HEADER   sheader<span class="hl opt">;</span>
  ULONG                       ulStrengthControl<span class="hl opt">;</span>      <span class="hl slc">// DVOA strength control for CF</span>
  UCHAR                       ucPadding<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>
<span class="hl opt">}</span>ATOM_ENCODER_DVO_CF_RECORD<span class="hl opt">;</span>

<span class="hl slc">// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle</span>
<span class="hl ppc">#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA   1</span>
<span class="hl ppc">#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB   2</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_CONNECTOR_CF_RECORD
<span class="hl opt">{</span>
  ATOM_COMMON_RECORD_HEADER   sheader<span class="hl opt">;</span>
  USHORT                      usMaxPixClk<span class="hl opt">;</span>
  UCHAR                       ucFlowCntlGpioId<span class="hl opt">;</span>
  UCHAR                       ucSwapCntlGpioId<span class="hl opt">;</span>
  UCHAR                       ucConnectedDvoBundle<span class="hl opt">;</span>
  UCHAR                       ucPadding<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_CONNECTOR_CF_RECORD<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
<span class="hl opt">{</span>
  ATOM_COMMON_RECORD_HEADER   sheader<span class="hl opt">;</span>
	ATOM_DTD_FORMAT							asTiming<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_CONNECTOR_HARDCODE_DTD_RECORD<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
<span class="hl opt">{</span>
  ATOM_COMMON_RECORD_HEADER   sheader<span class="hl opt">;</span>                <span class="hl slc">//ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE</span>
  UCHAR                       ucSubConnectorType<span class="hl opt">;</span>     <span class="hl slc">//CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A</span>
  UCHAR                       ucReserved<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD<span class="hl opt">;</span>


<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
<span class="hl opt">{</span>
	ATOM_COMMON_RECORD_HEADER   sheader<span class="hl opt">;</span>                
	UCHAR												ucMuxType<span class="hl opt">;</span>							<span class="hl slc">//decide the number of ucMuxState, =0, no pin state, =1: single state with complement, &gt;1: multiple state</span>
	UCHAR												ucMuxControlPin<span class="hl opt">;</span>
	UCHAR												ucMuxState<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>					<span class="hl slc">//for alligment purpose</span>
<span class="hl opt">}</span>ATOM_ROUTER_DDC_PATH_SELECT_RECORD<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
<span class="hl opt">{</span>
	ATOM_COMMON_RECORD_HEADER   sheader<span class="hl opt">;</span>                
	UCHAR												ucMuxType<span class="hl opt">;</span>
	UCHAR												ucMuxControlPin<span class="hl opt">;</span>
	UCHAR												ucMuxState<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>					<span class="hl slc">//for alligment purpose</span>
<span class="hl opt">}</span>ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD<span class="hl opt">;</span>

<span class="hl slc">// define ucMuxType</span>
<span class="hl ppc">#define ATOM_ROUTER_MUX_PIN_STATE_MASK								0x0f</span>
<span class="hl ppc">#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT		0x01</span>

<span class="hl com">/****************************************************************************/</span>	
<span class="hl slc">// ASIC voltage data table</span>
<span class="hl com">/****************************************************************************/</span>	
<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_VOLTAGE_INFO_HEADER
<span class="hl opt">{</span>
   USHORT   usVDDCBaseLevel<span class="hl opt">;</span>                <span class="hl slc">//In number of 50mv unit</span>
   USHORT   usReserved<span class="hl opt">;</span>                     <span class="hl slc">//For possible extension table offset</span>
   UCHAR    ucNumOfVoltageEntries<span class="hl opt">;</span>
   UCHAR    ucBytesPerVoltageEntry<span class="hl opt">;</span>
   UCHAR    ucVoltageStep<span class="hl opt">;</span>                  <span class="hl slc">//Indicating in how many mv increament is one step, 0.5mv unit</span>
   UCHAR    ucDefaultVoltageEntry<span class="hl opt">;</span>
   UCHAR    ucVoltageControlI2cLine<span class="hl opt">;</span>
   UCHAR    ucVoltageControlAddress<span class="hl opt">;</span>
   UCHAR    ucVoltageControlOffset<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_VOLTAGE_INFO_HEADER<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_VOLTAGE_INFO
<span class="hl opt">{</span>
   ATOM_COMMON_TABLE_HEADER	sHeader<span class="hl opt">;</span> 
   ATOM_VOLTAGE_INFO_HEADER viHeader<span class="hl opt">;</span>
   UCHAR    ucVoltageEntries<span class="hl opt">[</span><span class="hl num">64</span><span class="hl opt">];</span>            <span class="hl slc">//64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry</span>
<span class="hl opt">}</span>ATOM_VOLTAGE_INFO<span class="hl opt">;</span>


<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_VOLTAGE_FORMULA
<span class="hl opt">{</span>
   USHORT   usVoltageBaseLevel<span class="hl opt">;</span>             <span class="hl slc">// In number of 1mv unit</span>
   USHORT   usVoltageStep<span class="hl opt">;</span>                  <span class="hl slc">// Indicating in how many mv increament is one step, 1mv unit</span>
	 UCHAR		ucNumOfVoltageEntries<span class="hl opt">;</span>					<span class="hl slc">// Number of Voltage Entry, which indicate max Voltage</span>
	 UCHAR		ucFlag<span class="hl opt">;</span>													<span class="hl slc">// bit0=0 :step is 1mv =1 0.5mv</span>
	 UCHAR		ucBaseVID<span class="hl opt">;</span>											<span class="hl slc">// if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep</span>
	 UCHAR		ucReserved<span class="hl opt">;</span>
	 UCHAR		ucVIDAdjustEntries<span class="hl opt">[</span><span class="hl num">32</span><span class="hl opt">];</span>					<span class="hl slc">// 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries</span>
<span class="hl opt">}</span>ATOM_VOLTAGE_FORMULA<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_VOLTAGE_CONTROL
<span class="hl opt">{</span>
	UCHAR		 ucVoltageControlId<span class="hl opt">;</span>							<span class="hl slc">//Indicate it is controlled by I2C or GPIO or HW state machine		</span>
  UCHAR    ucVoltageControlI2cLine<span class="hl opt">;</span>
  UCHAR    ucVoltageControlAddress<span class="hl opt">;</span>
  UCHAR    ucVoltageControlOffset<span class="hl opt">;</span>	 	
  USHORT   usGpioPin_AIndex<span class="hl opt">;</span>								<span class="hl slc">//GPIO_PAD register index</span>
  UCHAR    ucGpioPinBitShift<span class="hl opt">[</span><span class="hl num">9</span><span class="hl opt">];</span>						<span class="hl slc">//at most 8 pin support 255 VIDs, termintate with 0xff</span>
	UCHAR		 ucReserved<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_VOLTAGE_CONTROL<span class="hl opt">;</span>

<span class="hl slc">// Define ucVoltageControlId</span>
<span class="hl ppc">#define	VOLTAGE_CONTROLLED_BY_HW							0x00</span>
<span class="hl ppc">#define	VOLTAGE_CONTROLLED_BY_I2C_MASK				0x7F</span>
<span class="hl ppc">#define	VOLTAGE_CONTROLLED_BY_GPIO						0x80</span>
<span class="hl ppc">#define	VOLTAGE_CONTROL_ID_LM64								0x01</span>									<span class="hl slc">//I2C control, used for R5xx Core Voltage</span>
<span class="hl ppc"></span><span class="hl ppc">#define	VOLTAGE_CONTROL_ID_DAC								0x02</span>									<span class="hl slc">//I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI</span>
<span class="hl ppc"></span><span class="hl ppc">#define	VOLTAGE_CONTROL_ID_VT116xM						0x03</span>									<span class="hl slc">//I2C control, used for R6xx Core Voltage</span>
<span class="hl ppc"></span><span class="hl ppc">#define VOLTAGE_CONTROL_ID_DS4402							0x04									</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_VOLTAGE_OBJECT
<span class="hl opt">{</span>
 	 UCHAR		ucVoltageType<span class="hl opt">;</span>									<span class="hl slc">//Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI	 </span>
	 UCHAR		ucSize<span class="hl opt">;</span>													<span class="hl slc">//Size of Object	</span>
	 ATOM_VOLTAGE_CONTROL			asControl<span class="hl opt">;</span>			<span class="hl slc">//describ how to control 	 </span>
 	 ATOM_VOLTAGE_FORMULA			asFormula<span class="hl opt">;</span>			<span class="hl slc">//Indicate How to convert real Voltage to VID </span>
<span class="hl opt">}</span>ATOM_VOLTAGE_OBJECT<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_VOLTAGE_OBJECT_INFO
<span class="hl opt">{</span>
   ATOM_COMMON_TABLE_HEADER	sHeader<span class="hl opt">;</span> 
	 ATOM_VOLTAGE_OBJECT			asVoltageObj<span class="hl opt">[</span><span class="hl num">3</span><span class="hl opt">];</span>	<span class="hl slc">//Info for Voltage control	  	 </span>
<span class="hl opt">}</span>ATOM_VOLTAGE_OBJECT_INFO<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_LEAKID_VOLTAGE
<span class="hl opt">{</span>
	UCHAR		ucLeakageId<span class="hl opt">;</span>
	UCHAR		ucReserved<span class="hl opt">;</span>
	USHORT	usVoltage<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_LEAKID_VOLTAGE<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_ASIC_PROFILE_VOLTAGE
<span class="hl opt">{</span>
	UCHAR		ucProfileId<span class="hl opt">;</span>
	UCHAR		ucReserved<span class="hl opt">;</span>
	USHORT	usSize<span class="hl opt">;</span>
	USHORT	usEfuseSpareStartAddr<span class="hl opt">;</span>
	USHORT	usFuseIndex<span class="hl opt">[</span><span class="hl num">8</span><span class="hl opt">];</span>												<span class="hl slc">//from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, </span>
	ATOM_LEAKID_VOLTAGE					asLeakVol<span class="hl opt">[</span><span class="hl num">2</span><span class="hl opt">];</span>			<span class="hl slc">//Leakid and relatd voltage</span>
<span class="hl opt">}</span>ATOM_ASIC_PROFILE_VOLTAGE<span class="hl opt">;</span>

<span class="hl slc">//ucProfileId</span>
<span class="hl ppc">#define	ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE			1		</span>
<span class="hl ppc">#define	ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE			1</span>
<span class="hl ppc">#define	ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE					2</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span>  _ATOM_ASIC_PROFILING_INFO
<span class="hl opt">{</span>
  ATOM_COMMON_TABLE_HEADER			asHeader<span class="hl opt">;</span> 
	ATOM_ASIC_PROFILE_VOLTAGE			asVoltage<span class="hl opt">;</span>
<span class="hl opt">}</span>ATOM_ASIC_PROFILING_INFO<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_POWER_SOURCE_OBJECT
<span class="hl opt">{</span>
	UCHAR	ucPwrSrcId<span class="hl opt">;</span>													<span class="hl slc">// Power source</span>
	UCHAR	ucPwrSensorType<span class="hl opt">;</span>										<span class="hl slc">// GPIO, I2C or none</span>
	UCHAR	ucPwrSensId<span class="hl opt">;</span>											  <span class="hl slc">// if GPIO detect, it is GPIO id,  if I2C detect, it is I2C id</span>
	UCHAR	ucPwrSensSlaveAddr<span class="hl opt">;</span>									<span class="hl slc">// Slave address if I2C detect</span>
	UCHAR ucPwrSensRegIndex<span class="hl opt">;</span>									<span class="hl slc">// I2C register Index if I2C detect</span>
	UCHAR ucPwrSensRegBitMask<span class="hl opt">;</span>								<span class="hl slc">// detect which bit is used if I2C detect</span>
	UCHAR	ucPwrSensActiveState<span class="hl opt">;</span>								<span class="hl slc">// high active or low active</span>
	UCHAR	ucReserve<span class="hl opt">[</span><span class="hl num">3</span><span class="hl opt">];</span>												<span class="hl slc">// reserve		</span>
	USHORT usSensPwr<span class="hl opt">;</span>													<span class="hl slc">// in unit of watt</span>
<span class="hl opt">}</span>ATOM_POWER_SOURCE_OBJECT<span class="hl opt">;</span>

<span class="hl kwc">typedef</span> <span class="hl kwb">struct</span> _ATOM_POWER_SOURCE_INFO
<span class="hl opt">{</span>
		ATOM_COMMON_TABLE_HEADER		asHeader<span class="hl opt">;</span>
		UCHAR												asPwrbehave<span class="hl opt">[</span><span class="hl num">16</span><span class="hl opt">];</span>
		ATOM_POWER_SOURCE_OBJECT		asPwrObj<span class="hl opt">[</span><span class="hl num">1</span><span class="hl opt">];</span>
<span class="hl opt">}</span>ATOM_POWER_SOURCE_INFO<span class="hl opt">;</span>


<span class="hl slc">//Define ucPwrSrcId</span>
<span class="hl ppc">#define POWERSOURCE_PCIE_ID1						0x00</span>
<span class="hl ppc">#define POWERSOURCE_6PIN_CONNECTOR_ID1	0x01</span>
<span class="hl ppc">#define POWERSOURCE_8PIN_CONNECTOR_ID1	0x02</span>
<span class="hl ppc">#define POWERSOURCE_6PIN_CONNECTOR_ID2	0x04</span>
<span class="hl ppc">#define POWERSOURCE_8PIN_CONNECTOR_ID2	0x08</span>

<span class="hl slc">//define ucPwrSensorId</span>
<span class="hl ppc">#define POWER_SENSOR_ALWAYS							0x00</span>
<span class="hl ppc">#define POWER_SENSOR_GPIO								0x01</span>
<span class="hl ppc">#define POWER_SENSOR_I2C								0x02</span>

<span class="hl com">/**************************************************************************/</span>
<span class="hl slc">// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design</span>
<span class="hl slc">//Memory SS Info Table</span>
<span class="hl slc">//Define Memory Clock SS chip ID</span>
<span class="hl ppc">#define ICS91719  1</span>
<span class="hl ppc">#define ICS91720  2</span>

<span class="hl slc">//Define one structure to inform SW a &quot;block of data&quot; writing to external SS chip via I2C protocol