/linux-core/

return false; } /* Check RO channel */ DRM_WRITE8(map, 0x235c, 0x83); check = le16_to_cpu(DRM_READ16(map, 0x2360)); if ((check & 0x0f) != ((check & 0xf0) >> 4)) { return false; } /* Check RW channel */ DRM_WRITE8(map, 0x235c, 0x88); check = le16_to_cpu(DRM_READ16(map, 0x2360)); if ((check & 0x0f) != ((check & 0xf0) >> 4)) { return false; } /* Check RO channel outstanding */ DRM_WRITE8(map, 0x235c, 0x8f); check = le16_to_cpu(DRM_READ16(map, 0x2360)); if (0 != (check & 0x3ff)) { return false; } /* Check RW channel outstanding */ DRM_WRITE8(map, 0x235c, 0x90); check = le16_to_cpu(DRM_READ16(map, 0x2360)); if (0 != (check & 0x3ff)) { return false; } /* No pending PCIE request. GE stall. */ } return true; } static void xgi_ge_hang_reset(struct drm_map * map) { int time_out = 0xffff; DRM_WRITE8(map, 0xb057, 8); while (0 != le32_to_cpu(DRM_READ32(map, 0x2800) & 0xf0000000)) { while (0 != ((--time_out) & 0xfff)) /* empty */ ; if (0 == time_out) { u8 old_3ce; u8 old_3cf; u8 old_index; u8 old_36; DRM_INFO("Can not reset back 0x%x!\n", le32_to_cpu(DRM_READ32(map, 0x2800))); DRM_WRITE8(map, 0xb057, 0); /* Have to use 3x5.36 to reset. */ /* Save and close dynamic gating */ old_3ce = DRM_READ8(map, 0x3ce); DRM_WRITE8(map, 0x3ce, 0x2a); old_3cf = DRM_READ8(map, 0x3cf); DRM_WRITE8(map, 0x3cf, old_3cf & 0xfe); /* Reset GE */ old_index = DRM_READ8(map, 0x3d4); DRM_WRITE8(map, 0x3d4, 0x36); old_36 = DRM_READ8(map, 0x3d5); DRM_WRITE8(map, 0x3d5, old_36 | 0x10); while (0 != ((--time_out) & 0xfff)) /* empty */ ; DRM_WRITE8(map, 0x3d5, old_36); DRM_WRITE8(map, 0x3d4, old_index); /* Restore dynamic gating */ DRM_WRITE8(map, 0x3cf, old_3cf); DRM_WRITE8(map, 0x3ce, old_3ce); break; } } DRM_WRITE8(map, 0xb057, 0); } bool xgi_ge_irq_handler(struct xgi_info * info) { const u32 int_status = le32_to_cpu(DRM_READ32(info->mmio_map, 0x2810)); bool is_support_auto_reset = false; /* Check GE on/off */ if (0 == (0xffffc0f0 & int_status)) { if (0 != (0x1000 & int_status)) { /* We got GE stall interrupt. */ DRM_WRITE32(info->mmio_map, 0x2810, cpu_to_le32(int_status | 0x04000000)); if (is_support_auto_reset) { static cycles_t last_tick; static unsigned continue_int_count = 0; /* OE II is busy. */ if (!xgi_validate_signal(info->mmio_map)) { /* Nothing but skip. */ } else if (0 == continue_int_count++) { last_tick = get_cycles(); } else { const cycles_t new_tick = get_cycles(); if ((new_tick - last_tick) > STALL_INTERRUPT_RESET_THRESHOLD) { continue_int_count = 0; } else if (continue_int_count >= 3) { continue_int_count = 0; /* GE Hung up, need reset. */ DRM_INFO("Reset GE!\n"); xgi_ge_hang_reset(info->mmio_map); } } } } else if (0 != (0x1 & int_status)) { s_invalid_begin++; DRM_WRITE32(info->mmio_map, 0x2810, cpu_to_le32((int_status & ~0x01) | 0x04000000)); } return true; } return false; } bool xgi_crt_irq_handler(struct xgi_info * info) { bool ret = false; u8 save_3ce = DRM_READ8(info->mmio_map, 0x3ce); /* CRT1 interrupt just happened */ if (IN3CFB(info->mmio_map, 0x37) & 0x01) { u8 op3cf_3d; u8 op3cf_37; /* What happened? */ op3cf_37 = IN3CFB(info->mmio_map, 0x37); /* Clear CRT interrupt */ op3cf_3d = IN3CFB(info->mmio_map, 0x3d); OUT3CFB(info->mmio_map, 0x3d, (op3cf_3d | 0x04)); OUT3CFB(info->mmio_map, 0x3d, (op3cf_3d & ~0x04)); ret = true; } DRM_WRITE8(info->mmio_map, 0x3ce, save_3ce); return (ret); } bool xgi_dvi_irq_handler(struct xgi_info * info) { bool ret = false; const u8 save_3ce = DRM_READ8(info->mmio_map, 0x3ce); /* DVI interrupt just happened */ if (IN3CFB(info->mmio_map, 0x38) & 0x20) { const u8 save_3x4 = DRM_READ8(info->mmio_map, 0x3d4); u8 op3cf_39; u8 op3cf_37; u8 op3x5_5a; /* What happened? */ op3cf_37 = IN3CFB(info->mmio_map, 0x37); /* Notify BIOS that DVI plug/unplug happened */ op3x5_5a = IN3X5B(info->mmio_map, 0x5a); OUT3X5B(info->mmio_map, 0x5a, op3x5_5a & 0xf7); DRM_WRITE8(info->mmio_map, 0x3d4, save_3x4); /* Clear DVI interrupt */ op3cf_39 = IN3CFB(info->mmio_map, 0x39); OUT3C5B(info->mmio_map, 0x39, (op3cf_39 & ~0x01)); OUT3C5B(info->mmio_map, 0x39, (op3cf_39 | 0x01));