/* * Copyright 2007-8 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher */ #include "drmP.h" #include "radeon_drm.h" #include "radeon_drv.h" #define CURSOR_WIDTH 64 #define CURSOR_HEIGHT 64 static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock) { struct drm_radeon_private *dev_priv = crtc->dev->dev_private; struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); uint32_t cur_lock; if (radeon_is_avivo(dev_priv)) { cur_lock = RADEON_READ(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); if (lock) cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; else cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; RADEON_WRITE(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); } else { switch(radeon_crtc->crtc_id) { case 0: cur_lock = RADEON_READ(RADEON_CUR_OFFSET); if (lock) cur_lock |= RADEON_CUR_LOCK; else cur_lock &= ~RADEON_CUR_LOCK; RADEON_WRITE(RADEON_CUR_OFFSET, cur_lock); break; case 1: cur_lock = RADEON_READ(RADEON_CUR2_OFFSET); if (lock) cur_lock |= RADEON_CUR2_LOCK; else cur_lock &= ~RADEON_CUR2_LOCK; RADEON_WRITE(RADEON_CUR2_OFFSET, cur_lock); break; default: break; } } } static void radeon_hide_cursor(struct drm_crtc *crtc) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); struct drm_radeon_private *dev_priv = crtc->dev->dev_private; if (radeon_is_avivo(dev_priv)) { RADEON_WRITE(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); RADEON_WRITE_P(RADEON_MM_DATA, 0, ~AVIVO_D1CURSOR_EN); } else { switch(radeon_crtc->crtc_id) { case 0: RADEON_WRITE(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); break; case 1: RADEON_WRITE(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); break; default: return; } RADEON_WRITE_P(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN); } } static void radeon_show_cursor(struct drm_crtc *crtc) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); struct drm_radeon_private *dev_priv = crtc->dev->dev_private; if (radeon_is_avivo(dev_priv)) { RADEON_WRITE(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); RADEON_WRITE(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); } else { switch(radeon_crtc->crtc_id) { case 0: RADEON_WRITE(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); break; case 1: RADEON_WRITE(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); break; default: return; } RADEON_WRITE_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN | (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); } } static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, uint32_t width, uint32_t height) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); struct drm_radeon_private *dev_priv = crtc->dev->dev_private; struct drm_radeon_gem_object *obj_priv; obj_priv = obj->driver_private; if (radeon_is_avivo(dev_priv)) { RADEON_WRITE(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, dev_priv->fb_location + obj_priv->bo->offset); RADEON_WRITE(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, (width - 1) << 16 | (height - 1)); } else { switch(radeon_crtc->crtc_id) { case 0: /* offset is from DISP_BASE_ADDRESS */ RADEON_WRITE(RADEON_CUR_OFFSET, obj_priv->bo->offset); break; case 1: /* offset is from DISP2_BASE_ADDRESS */ RADEON_WRITE(RADEON_CUR2_OFFSET, obj_priv->bo->offset); break; default: break; } } } int radeon_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, uint32_t handle, uint32_t width, uint32_t height) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); struct drm_gem_object *obj; if (!handle) { /* turn off cursor */ radeon_hide_cursor(crtc); return 0; } obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); if (!obj) { DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id); return -EINVAL; } if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { DRM_ERROR("bad cursor width or height %d x %d\n", width, height); return -EINVAL; } radeon_lock_cursor(crtc, true); // XXX only 27 bit offset for legacy cursor radeon_set_cursor(crtc, obj, width, height); radeon_show_cursor(crtc); radeon_lock_cursor(crtc, false); mutex_lock(&crtc->dev->struct_mutex); drm_gem_object_unreference(obj); mutex_unlock(&crtc->dev->struct_mutex); return 0; } int radeon_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); struct drm_radeon_private *dev_priv = crtc->dev->dev_private; int xorigin = 0, yorigin = 0; if (x < 0) xorigin = -x + 1; if (y < 0) yorigin = -y + 1; if (xorigin >= CURSOR_WIDTH) xorigin = CURSOR_WIDTH - 1; if (yorigin >= CURSOR_HEIGHT) yorigin = CURSOR_HEIGHT - 1; radeon_lock_cursor(crtc, true); if (radeon_is_avivo(dev_priv)) { RADEON_WRITE(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0: x) << 16) | (yorigin ? 0 : y)); RADEON_WRITE(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); } else { if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) y /= 2; else if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) y *= 2; switch(radeon_crtc->crtc_id) { case 0: RADEON_WRITE(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK | (xorigin << 16) | yorigin)); RADEON_WRITE(RADEON_CUR_HORZ_VERT_POSN, (RADEON_CUR_LOCK | ((xorigin ? 0 : x) << 16) | (yorigin ? 0 : y))); break; case 1: RADEON_WRITE(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK | (xorigin << 16) | yorigin)); RADEON_WRITE(RADEON_CUR2_HORZ_VERT_POSN, (RADEON_CUR2_LOCK | ((xorigin ? 0 : x) << 16) | (yorigin ? 0 : y))); break; default: break; } } radeon_lock_cursor(crtc, false); return 0; } 0 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710
/* r128_state.c -- State support for r128 -*- linux-c -*-
* Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com
*
* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Authors:
* Gareth Hughes <gareth@valinux.com>
*/
#include "drmP.h"
#include "drm.h"
#include "r128_drm.h"
#include "r128_drv.h"
/* ================================================================
* CCE hardware state programming functions
*/
static void r128_emit_clip_rects( drm_r128_private_t *dev_priv,
drm_clip_rect_t *boxes, int count )
{
u32 aux_sc_cntl = 0x00000000;
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
BEGIN_RING( (count < 3? count: 3) * 5 + 2 );
if ( count >= 1 ) {
OUT_RING( CCE_PACKET0( R128_AUX1_SC_LEFT, 3 ) );
OUT_RING( boxes[0].x1 );
OUT_RING( boxes[0].x2 - 1 );
OUT_RING( boxes[0].y1 );
OUT_RING( boxes[0].y2 - 1 );
aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR);
}
if ( count >= 2 ) {
OUT_RING( CCE_PACKET0( R128_AUX2_SC_LEFT, 3 ) );
OUT_RING( boxes[1].x1 );
OUT_RING( boxes[1].x2 - 1 );
OUT_RING( boxes[1].y1 );
OUT_RING( boxes[1].y2 - 1 );
aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR);
}
if ( count >= 3 ) {
OUT_RING( CCE_PACKET0( R128_AUX3_SC_LEFT, 3 ) );
OUT_RING( boxes[2].x1 );
OUT_RING( boxes[2].x2 - 1 );
OUT_RING( boxes[2].y1 );
OUT_RING( boxes[2].y2 - 1 );
aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR);
}
OUT_RING( CCE_PACKET0( R128_AUX_SC_CNTL, 0 ) );
OUT_RING( aux_sc_cntl );
ADVANCE_RING();
}
static __inline__ void r128_emit_core( drm_r128_private_t *dev_priv )
{
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
BEGIN_RING( 2 );
OUT_RING( CCE_PACKET0( R128_SCALE_3D_CNTL, 0 ) );
OUT_RING( ctx->scale_3d_cntl );
ADVANCE_RING();
}
static __inline__ void r128_emit_context( drm_r128_private_t *dev_priv )
{
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
BEGIN_RING( 13 );
OUT_RING( CCE_PACKET0( R128_DST_PITCH_OFFSET_C, 11 ) );
OUT_RING( ctx->dst_pitch_offset_c );
OUT_RING( ctx->dp_gui_master_cntl_c );
OUT_RING( ctx->sc_top_left_c );
OUT_RING( ctx->sc_bottom_right_c );
OUT_RING( ctx->z_offset_c );
OUT_RING( ctx->z_pitch_c );
OUT_RING( ctx->z_sten_cntl_c );
OUT_RING( ctx->tex_cntl_c );
OUT_RING( ctx->misc_3d_state_cntl_reg );
OUT_RING( ctx->texture_clr_cmp_clr_c );
OUT_RING( ctx->texture_clr_cmp_msk_c );
OUT_RING( ctx->fog_color_c );
ADVANCE_RING();
}
static __inline__ void r128_emit_setup( drm_r128_private_t *dev_priv )
{
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
BEGIN_RING( 3 );
OUT_RING( CCE_PACKET1( R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP ) );
OUT_RING( ctx->setup_cntl );
OUT_RING( ctx->pm4_vc_fpu_setup );
ADVANCE_RING();
}
static __inline__ void r128_emit_masks( drm_r128_private_t *dev_priv )
{
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
BEGIN_RING( 5 );
OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) );
OUT_RING( ctx->dp_write_mask );
OUT_RING( CCE_PACKET0( R128_STEN_REF_MASK_C, 1 ) );
OUT_RING( ctx->sten_ref_mask_c );
OUT_RING( ctx->plane_3d_mask_c );
ADVANCE_RING();
}
static __inline__ void r128_emit_window( drm_r128_private_t *dev_priv )
{
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
BEGIN_RING( 2 );
OUT_RING( CCE_PACKET0( R128_WINDOW_XY_OFFSET, 0 ) );
OUT_RING( ctx->window_xy_offset );
ADVANCE_RING();
}
static __inline__ void r128_emit_tex0( drm_r128_private_t *dev_priv )
{
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0];
int i;
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
BEGIN_RING( 7 + R128_MAX_TEXTURE_LEVELS );
OUT_RING( CCE_PACKET0( R128_PRIM_TEX_CNTL_C,
2 + R128_MAX_TEXTURE_LEVELS ) );
OUT_RING( tex->tex_cntl );
OUT_RING( tex->tex_combine_cntl );
OUT_RING( ctx->tex_size_pitch_c );
for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) {
OUT_RING( tex->tex_offset[i] );
}
OUT_RING( CCE_PACKET0( R128_CONSTANT_COLOR_C, 1 ) );
OUT_RING( ctx->constant_color_c );
OUT_RING( tex->tex_border_color );
ADVANCE_RING();
}
static __inline__ void r128_emit_tex1( drm_r128_private_t *dev_priv )
{
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1];
int i;
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
BEGIN_RING( 5 + R128_MAX_TEXTURE_LEVELS );
OUT_RING( CCE_PACKET0( R128_SEC_TEX_CNTL_C,
1 + R128_MAX_TEXTURE_LEVELS ) );
OUT_RING( tex->tex_cntl );
OUT_RING( tex->tex_combine_cntl );
for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) {
OUT_RING( tex->tex_offset[i] );
}
OUT_RING( CCE_PACKET0( R128_SEC_TEXTURE_BORDER_COLOR_C, 0 ) );
OUT_RING( tex->tex_border_color );
ADVANCE_RING();
}
static __inline__ void r128_emit_state( drm_r128_private_t *dev_priv )
{
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
unsigned int dirty = sarea_priv->dirty;
DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty );
if ( dirty & R128_UPLOAD_CORE ) {
r128_emit_core( dev_priv );
sarea_priv->dirty &= ~R128_UPLOAD_CORE;
}
if ( dirty & R128_UPLOAD_CONTEXT ) {
r128_emit_context( dev_priv );
sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT;
}
if ( dirty & R128_UPLOAD_SETUP ) {
r128_emit_setup( dev_priv );
sarea_priv->dirty &= ~R128_UPLOAD_SETUP;
}
if ( dirty & R128_UPLOAD_MASKS ) {
r128_emit_masks( dev_priv );
sarea_priv->dirty &= ~R128_UPLOAD_MASKS;
}
if ( dirty & R128_UPLOAD_WINDOW ) {
r128_emit_window( dev_priv );
sarea_priv->dirty &= ~R128_UPLOAD_WINDOW;
}
if ( dirty & R128_UPLOAD_TEX0 ) {
r128_emit_tex0( dev_priv );
sarea_priv->dirty &= ~R128_UPLOAD_TEX0;
}
if ( dirty & R128_UPLOAD_TEX1 ) {
r128_emit_tex1( dev_priv );
sarea_priv->dirty &= ~R128_UPLOAD_TEX1;
}
/* Turn off the texture cache flushing */
sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH;
sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE;
}
#if R128_PERFORMANCE_BOXES
/* ================================================================
* Performance monitoring functions
*/
static void r128_clear_box( drm_r128_private_t *dev_priv,
int x, int y, int w, int h,
int r, int g, int b )
{
u32 pitch, offset;
u32 fb_bpp, color;
RING_LOCALS;
switch ( dev_priv->fb_bpp ) {
case 16:
fb_bpp = R128_GMC_DST_16BPP;
color = (((r & 0xf8) << 8) |
((g & 0xfc) << 3) |
((b & 0xf8) >> 3));
break;
case 24:
fb_bpp = R128_GMC_DST_24BPP;
color = ((r << 16) | (g << 8) | b);
break;
case 32:
fb_bpp = R128_GMC_DST_32BPP;
color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
break;
default:
return;
}
offset = dev_priv->back_offset;
pitch = dev_priv->back_pitch >> 3;
BEGIN_RING( 6 );
OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
R128_GMC_BRUSH_SOLID_COLOR |
fb_bpp |
R128_GMC_SRC_DATATYPE_COLOR |
R128_ROP3_P |
R128_GMC_CLR_CMP_CNTL_DIS |
R128_GMC_AUX_CLIP_DIS );
OUT_RING( (pitch << 21) | (offset >> 5) );
OUT_RING( color );
OUT_RING( (x << 16) | y );
OUT_RING( (w << 16) | h );
ADVANCE_RING();
}
static void r128_cce_performance_boxes( drm_r128_private_t *dev_priv )
{
if ( atomic_read( &dev_priv->idle_count ) == 0 ) {
r128_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
} else {
atomic_set( &dev_priv->idle_count, 0 );
}
}
#endif
/* ================================================================
* CCE command dispatch functions
*/
static void r128_print_dirty( const char *msg, unsigned int flags )
{
DRM_INFO( "%s: (0x%x) %s%s%s%s%s%s%s%s%s\n",
msg,
flags,
(flags & R128_UPLOAD_CORE) ? "core, " : "",
(flags & R128_UPLOAD_CONTEXT) ? "context, " : "",
(flags & R128_UPLOAD_SETUP) ? "setup, " : "",
(flags & R128_UPLOAD_TEX0) ? "tex0, " : "",
(flags & R128_UPLOAD_TEX1) ? "tex1, " : "",
(flags & R128_UPLOAD_MASKS) ? "masks, " : "",
(flags & R128_UPLOAD_WINDOW) ? "window, " : "",
(flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "",
(flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "" );
}
static void r128_cce_dispatch_clear( drm_device_t *dev,
drm_r128_clear_t *clear )
{
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
int nbox = sarea_priv->nbox;
drm_clip_rect_t *pbox = sarea_priv->boxes;
unsigned int flags = clear->flags;
int i;
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
unsigned int tmp = flags;
flags &= ~(R128_FRONT | R128_BACK);
if ( tmp & R128_FRONT ) flags |= R128_BACK;
if ( tmp & R128_BACK ) flags |= R128_FRONT;
}
for ( i = 0 ; i < nbox ; i++ ) {
int x = pbox[i].x1;
int y = pbox[i].y1;
int w = pbox[i].x2 - x;
int h = pbox[i].y2 - y;
DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
pbox[i].x1, pbox[i].y1, pbox[i].x2,
pbox[i].y2, flags );
if ( flags & (R128_FRONT | R128_BACK) ) {
BEGIN_RING( 2 );
OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) );
OUT_RING( clear->color_mask );
ADVANCE_RING();
}
if ( flags & R128_FRONT ) {
BEGIN_RING( 6 );
OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
R128_GMC_BRUSH_SOLID_COLOR |
(dev_priv->color_fmt << 8) |
R128_GMC_SRC_DATATYPE_COLOR |
R128_ROP3_P |
R128_GMC_CLR_CMP_CNTL_DIS |
R128_GMC_AUX_CLIP_DIS );
OUT_RING( dev_priv->front_pitch_offset_c );
OUT_RING( clear->clear_color );
OUT_RING( (x << 16) | y );
OUT_RING( (w << 16) | h );
ADVANCE_RING();
}
if ( flags & R128_BACK ) {
BEGIN_RING( 6 );
OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
R128_GMC_BRUSH_SOLID_COLOR |
(dev_priv->color_fmt << 8) |
R128_GMC_SRC_DATATYPE_COLOR |
R128_ROP3_P |
R128_GMC_CLR_CMP_CNTL_DIS |
R128_GMC_AUX_CLIP_DIS );
OUT_RING( dev_priv->back_pitch_offset_c );
OUT_RING( clear->clear_color );
OUT_RING( (x << 16) | y );
OUT_RING( (w << 16) | h );
ADVANCE_RING();
}
if ( flags & R128_DEPTH ) {
BEGIN_RING( 6 );
OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
R128_GMC_BRUSH_SOLID_COLOR |
(dev_priv->depth_fmt << 8) |
R128_GMC_SRC_DATATYPE_COLOR |
R128_ROP3_P |
R128_GMC_CLR_CMP_CNTL_DIS |
R128_GMC_AUX_CLIP_DIS |
R128_GMC_WR_MSK_DIS );
OUT_RING( dev_priv->depth_pitch_offset_c );
OUT_RING( clear->clear_depth );
OUT_RING( (x << 16) | y );
OUT_RING( (w << 16) | h );
ADVANCE_RING();
}
}
}
static void r128_cce_dispatch_swap( drm_device_t *dev )
{
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
int nbox = sarea_priv->nbox;
drm_clip_rect_t *pbox = sarea_priv->boxes;
int i;
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
#if R128_PERFORMANCE_BOXES
/* Do some trivial performance monitoring...
*/
r128_cce_performance_boxes( dev_priv );
#endif
for ( i = 0 ; i < nbox ; i++ ) {
int x = pbox[i].x1;
int y = pbox[i].y1;
int w = pbox[i].x2 - x;
int h = pbox[i].y2 - y;
BEGIN_RING( 7 );
OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) );
OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL |
R128_GMC_DST_PITCH_OFFSET_CNTL |
R128_GMC_BRUSH_NONE |
(dev_priv->color_fmt << 8) |
R128_GMC_SRC_DATATYPE_COLOR |
R128_ROP3_S |
R128_DP_SRC_SOURCE_MEMORY |
R128_GMC_CLR_CMP_CNTL_DIS |
R128_GMC_AUX_CLIP_DIS |
R128_GMC_WR_MSK_DIS );
/* Make this work even if front & back are flipped:
*/
if (dev_priv->current_page == 0) {
OUT_RING( dev_priv->back_pitch_offset_c );
OUT_RING( dev_priv->front_pitch_offset_c );
}
else {
OUT_RING( dev_priv->front_pitch_offset_c );
OUT_RING( dev_priv->back_pitch_offset_c );
}
OUT_RING( (x << 16) | y );
OUT_RING( (x << 16) | y );
OUT_RING( (w << 16) | h );
ADVANCE_RING();
}
/* Increment the frame counter. The client-side 3D driver must
* throttle the framerate by waiting for this value before
* performing the swapbuffer ioctl.
*/
dev_priv->sarea_priv->last_frame++;
BEGIN_RING( 2 );
OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) );
OUT_RING( dev_priv->sarea_priv->last_frame );
ADVANCE_RING();
}
static void r128_cce_dispatch_flip( drm_device_t *dev )
{
drm_r128_private_t *dev_priv = dev->dev_private;
RING_LOCALS;
DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
__FUNCTION__,
dev_priv->current_page,
dev_priv->sarea_priv->pfCurrentPage);
#if R128_PERFORMANCE_BOXES
/* Do some trivial performance monitoring...
*/
r128_cce_performance_boxes( dev_priv );
#endif
BEGIN_RING( 4 );
R128_WAIT_UNTIL_PAGE_FLIPPED();
OUT_RING( CCE_PACKET0( R128_CRTC_OFFSET, 0 ) );
if ( dev_priv->current_page == 0 ) {
OUT_RING( dev_priv->back_offset );
} else {
OUT_RING( dev_priv->front_offset );
}
ADVANCE_RING();
/* Increment the frame counter. The client-side 3D driver must
* throttle the framerate by waiting for this value before
* performing the swapbuffer ioctl.
*/
dev_priv->sarea_priv->last_frame++;
dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
1 - dev_priv->current_page;
BEGIN_RING( 2 );
OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) );
OUT_RING( dev_priv->sarea_priv->last_frame );
ADVANCE_RING();
}
static void r128_cce_dispatch_vertex( drm_device_t *dev,
drm_buf_t *buf )
{
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_buf_priv_t *buf_priv = buf->dev_private;
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
int format = sarea_priv->vc_format;
int offset = buf->bus_address;
int size = buf->used;
int prim = buf_priv->prim;
int i = 0;
RING_LOCALS;
DRM_DEBUG( "buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox );
if ( 0 )
r128_print_dirty( "dispatch_vertex", sarea_priv->dirty );
if ( buf->used ) {
buf_priv->dispatched = 1;
if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) {
r128_emit_state( dev_priv );
}
do {
/* Emit the next set of up to three cliprects */
if ( i < sarea_priv->nbox ) {
r128_emit_clip_rects( dev_priv,
&sarea_priv->boxes[i],
sarea_priv->nbox - i );
}
/* Emit the vertex buffer rendering commands */
BEGIN_RING( 5 );
OUT_RING( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, 3 ) );
OUT_RING( offset );
OUT_RING( size );
OUT_RING( format );
OUT_RING( prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST |
(size << R128_CCE_VC_CNTL_NUM_SHIFT) );
ADVANCE_RING();
i += 3;
} while ( i < sarea_priv->nbox );
}
if ( buf_priv->discard ) {
buf_priv->age = dev_priv->sarea_priv->last_dispatch;
/* Emit the vertex buffer age */
BEGIN_RING( 2 );
OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
OUT_RING( buf_priv->age );
ADVANCE_RING();
buf->pending = 1;
buf->used = 0;
/* FIXME: Check dispatched field */
buf_priv->dispatched = 0;
}
dev_priv->sarea_priv->last_dispatch++;
sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
sarea_priv->nbox = 0;
}
static void r128_cce_dispatch_indirect( drm_device_t *dev,
drm_buf_t *buf,
int start, int end )
{
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_buf_priv_t *buf_priv = buf->dev_private;
RING_LOCALS;
DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n",
buf->idx, start, end );
if ( start != end ) {
int offset = buf->bus_address + start;
int dwords = (end - start + 3) / sizeof(u32);
/* Indirect buffer data must be an even number of
* dwords, so if we've been given an odd number we must
* pad the data with a Type-2 CCE packet.
*/
if ( dwords & 1 ) {
u32 *data = (u32 *)
((char *)dev->agp_buffer_map->handle
+ buf->offset + start);
data[dwords++] = cpu_to_le32( R128_CCE_PACKET2 );
}
buf_priv->dispatched = 1;
/* Fire off the indirect buffer */
BEGIN_RING( 3 );
OUT_RING( CCE_PACKET0( R128_PM4_IW_INDOFF, 1 ) );
OUT_RING( offset );
OUT_RING( dwords );
ADVANCE_RING();
}
if ( buf_priv->discard ) {
buf_priv->age = dev_priv->sarea_priv->last_dispatch;
/* Emit the indirect buffer age */
BEGIN_RING( 2 );
OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
OUT_RING( buf_priv->age );
ADVANCE_RING();
buf->pending = 1;
buf->used = 0;
/* FIXME: Check dispatched field */
buf_priv->dispatched = 0;
}
dev_priv->sarea_priv->last_dispatch++;
}
static void r128_cce_dispatch_indices( drm_device_t *dev,
drm_buf_t *buf,
int start, int end,
int count )
{
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_buf_priv_t *buf_priv = buf->dev_private;
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
int format = sarea_priv->vc_format;
int offset = dev->agp_buffer_map->offset - dev_priv->cce_buffers_offset;
int prim = buf_priv->prim;
u32 *data;
int dwords;
int i = 0;
RING_LOCALS;
DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count );
if ( 0 )
r128_print_dirty( "dispatch_indices", sarea_priv->dirty );
if ( start != end ) {
buf_priv->dispatched = 1;
if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) {
r128_emit_state( dev_priv );
}
dwords = (end - start + 3) / sizeof(u32);
data = (u32 *)((char *)dev->agp_buffer_map->handle
+ buf->offset + start);
data[0] = cpu_to_le32( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM,
dwords-2 ) );
data[1] = cpu_to_le32( offset );
data[2] = cpu_to_le32( R128_MAX_VB_VERTS );
data[3] = cpu_to_le32( format );
data[4] = cpu_to_le32( (prim | R128_CCE_VC_CNTL_PRIM_WALK_IND |
(count << 16)) );
if ( count & 0x1 ) {
#ifdef __LITTLE_ENDIAN
data[dwords-1] &= 0x0000ffff;
#else
data[dwords-1] &= 0xffff0000;
#endif
}
do {
/* Emit the next set of up to three cliprects */
if ( i < sarea_priv->nbox ) {
r128_emit_clip_rects( dev_priv,
&sarea_priv->boxes[i],
sarea_priv->nbox - i );
}
r128_cce_dispatch_indirect( dev, buf, start, end );
i += 3;
} while ( i < sarea_priv->nbox );
}
if ( buf_priv->discard ) {
buf_priv->age = dev_priv->sarea_priv->last_dispatch;
/* Emit the vertex buffer age */
BEGIN_RING( 2 );
OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
OUT_RING( buf_priv->age );
ADVANCE_RING();
buf->pending = 1;
/* FIXME: Check dispatched field */
buf_priv->dispatched = 0;
}
dev_priv->sarea_priv->last_dispatch++;
sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
sarea_priv->nbox = 0;
}
static int r128_cce_dispatch_blit( DRMFILE filp,
drm_device_t *dev,
drm_r128_blit_t *blit )
{
drm_r128_private_t *dev_priv = dev->dev_private;
drm_device_dma_t *dma = dev->dma;
drm_buf_t *buf;
drm_r128_buf_priv_t *buf_priv;
u32 *data;
int dword_shift, dwords;
RING_LOCALS;
DRM_DEBUG( "\n" );
/* The compiler won't optimize away a division by a variable,
* even if the only legal values are powers of two. Thus, we'll
* use a shift instead.
*/
switch ( blit->format ) {
case R128_DATATYPE_ARGB8888:
dword_shift = 0;
break;
case R128_DATATYPE_ARGB1555:
case R128_DATATYPE_RGB565:
case R128_DATATYPE_ARGB4444:
case R128_DATATYPE_YVYU422:
case R128_DATATYPE_VYUY422:
dword_shift = 1;
break;
case R128_DATATYPE_CI8:
case R128_DATATYPE_RGB8:
dword_shift = 2;
break;
default:
DRM_ERROR( "invalid blit format %d\n", blit->format );
return DRM_ERR(EINVAL);
}
/* Flush the pixel cache, and mark the contents as Read Invalid.
* This ensures no pixel data gets mixed up with the texture
* data from the host data blit, otherwise part of the texture
* image may be corrupted.
*/
BEGIN_RING( 2 );
OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) );
OUT_RING( R128_PC_RI_GUI | R128_PC_FLUSH_GUI );
ADVANCE_RING();
/* Dispatch the indirect buffer.
*/
buf = dma->buflist[blit->idx];
buf_priv = buf->dev_private;
if ( buf->filp != filp ) {
DRM_ERROR( "process %d using buffer owned by %p\n",
DRM_CURRENTPID, buf->filp );
return DRM_ERR(EINVAL);
}
if ( buf->pending ) {
DRM_ERROR( "sending pending buffer %d\n", blit->idx );
return DRM_ERR(EINVAL);
}
buf_priv->discard = 1;
dwords = (blit->width * blit->height) >> dword_shift;
data = (u32 *)((char *)dev->agp_buffer_map->handle + buf->offset);
data[0] = cpu_to_le32( CCE_PACKET3( R128_CNTL_HOSTDATA_BLT, dwords + 6 ) );
data[1] = cpu_to_le32( (R128_GMC_DST_PITCH_OFFSET_CNTL |
R128_GMC_BRUSH_NONE |
(blit->format << 8) |
R128_GMC_SRC_DATATYPE_COLOR |
R128_ROP3_S |
R128_DP_SRC_SOURCE_HOST_DATA |
R128_GMC_CLR_CMP_CNTL_DIS |
R128_GMC_AUX_CLIP_DIS |
R128_GMC_WR_MSK_DIS) );
data[2] = cpu_to_le32( (blit->pitch << 21) | (blit->offset >> 5) );
data[3] = cpu_to_le32( 0xffffffff );
data[4] = cpu_to_le32( 0xffffffff );
data[5] = cpu_to_le32( (blit->y << 16) | blit->x );
data[6] = cpu_to_le32( (blit->height << 16) | blit->width );
data[7] = cpu_to_le32( dwords );
buf->used = (dwords + 8) * sizeof(u32);
r128_cce_dispatch_indirect( dev, buf, 0, buf->used );
/* Flush the pixel cache after the blit completes. This ensures
* the texture data is written out to memory before rendering
* continues.
*/
BEGIN_RING( 2 );
OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) );
OUT_RING( R128_PC_FLUSH_GUI );
ADVANCE_RING();
return 0;
}
/* ================================================================
* Tiled depth buffer management
*
* FIXME: These should all set the destination write mask for when we
* have hardware stencil support.
*/
static int r128_cce_dispatch_write_span( drm_device_t *dev,
drm_r128_depth_t *depth )
{
drm_r128_private_t *dev_priv = dev->dev_private;
int count, x, y;
u32 *buffer;
u8 *mask;
int i, buffer_size, mask_size;
RING_LOCALS;
DRM_DEBUG( "\n" );
count = depth->n;
if (count > 4096 || count <= 0)
return DRM_ERR(EMSGSIZE);
if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) {
return DRM_ERR(EFAULT);
}
if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) {
return DRM_ERR(EFAULT);
}
buffer_size = depth->n * sizeof(u32);
buffer = drm_alloc( buffer_size, DRM_MEM_BUFS );
if ( buffer == NULL )
return DRM_ERR(ENOMEM);
if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) {
drm_free( buffer, buffer_size, DRM_MEM_BUFS);
return DRM_ERR(EFAULT);
}
mask_size = depth->n * sizeof(u8);
if ( depth->mask ) {
mask = drm_alloc( mask_size, DRM_MEM_BUFS );
if ( mask == NULL ) {
drm_free( buffer, buffer_size, DRM_MEM_BUFS );
return DRM_ERR(ENOMEM);
}
if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) {
drm_free( buffer, buffer_size, DRM_MEM_BUFS );
drm_free( mask, mask_size, DRM_MEM_BUFS );
return DRM_ERR(EFAULT);
}
for ( i = 0 ; i < count ; i++, x++ ) {
if ( mask[i] ) {
BEGIN_RING( 6 );
OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
R128_GMC_BRUSH_SOLID_COLOR |
(dev_priv->depth_fmt << 8) |
R128_GMC_SRC_DATATYPE_COLOR |
R128_ROP3_P |
R128_GMC_CLR_CMP_CNTL_DIS |
R128_GMC_WR_MSK_DIS );
OUT_RING( dev_priv->depth_pitch_offset_c );
OUT_RING( buffer[i] );
OUT_RING( (x << 16) | y );
OUT_RING( (1 << 16) | 1 );
ADVANCE_RING();
}
}
drm_free( mask, mask_size, DRM_MEM_BUFS );
} else {
for ( i = 0 ; i < count ; i++, x++ ) {
BEGIN_RING( 6 );
OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
R128_GMC_BRUSH_SOLID_COLOR |
(dev_priv->depth_fmt << 8) |
R128_GMC_SRC_DATATYPE_COLOR |
R128_ROP3_P |
R128_GMC_CLR_CMP_CNTL_DIS |
R128_GMC_WR_MSK_DIS );
OUT_RING( dev_priv->depth_pitch_offset_c );
OUT_RING( buffer[i] );
OUT_RING( (x << 16) | y );
OUT_RING( (1 << 16) | 1 );
ADVANCE_RING();
}
}
drm_free( buffer, buffer_size, DRM_MEM_BUFS );
return 0;
}
static int r128_cce_dispatch_write_pixels( drm_device_t *dev,
drm_r128_depth_t *depth )
{
drm_r128_private_t *dev_priv = dev->dev_private;
int count, *x, *y;
u32 *buffer;
u8 *mask;
int i, xbuf_size, ybuf_size, buffer_size, mask_size;
RING_LOCALS;
DRM_DEBUG( "\n" );
count = depth->n;
if (count > 4096 || count <= 0)
return DRM_ERR(EMSGSIZE);
xbuf_size = count * sizeof(*x);
ybuf_size = count * sizeof(*y);
x = drm_alloc( xbuf_size, DRM_MEM_BUFS );
if ( x == NULL ) {
return DRM_ERR(ENOMEM);
}
y = drm_alloc( ybuf_size, DRM_MEM_BUFS );
if ( y == NULL ) {
drm_free( x, xbuf_size, DRM_MEM_BUFS );
return DRM_ERR(ENOMEM);
}
if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) {
drm_free( x, xbuf_size, DRM_MEM_BUFS );
drm_free( y, ybuf_size, DRM_MEM_BUFS );
return DRM_ERR(EFAULT);
}
if ( DRM_COPY_FROM_USER( y, depth->y, xbuf_size ) ) {
drm_free( x, xbuf_size, DRM_MEM_BUFS );
drm_free( y, ybuf_size, DRM_MEM_BUFS );
return DRM_ERR(EFAULT);
}
buffer_size = depth->n * sizeof(u32);
buffer = drm_alloc( buffer_size, DRM_MEM_BUFS );
if ( buffer == NULL ) {
drm_free( x, xbuf_size, DRM_MEM_BUFS );
drm_free( y, ybuf_size, DRM_MEM_BUFS );
return DRM_ERR(ENOMEM);
}
if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) {
drm_free( x, xbuf_size, DRM_MEM_BUFS );
drm_free( y, ybuf_size, DRM_MEM_BUFS );
drm_free( buffer, buffer_size, DRM_MEM_BUFS );
return DRM_ERR(EFAULT);
}
if ( depth->mask ) {
mask_size = depth->n * sizeof(u8);
mask = drm_alloc( mask_size, DRM_MEM_BUFS );
if ( mask == NULL ) {
drm_free( x, xbuf_size, DRM_MEM_BUFS );
drm_free( y, ybuf_size, DRM_MEM_BUFS );
drm_free( buffer, buffer_size, DRM_MEM_BUFS );
return DRM_ERR(ENOMEM);
}
if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) {
drm_free( x, xbuf_size, DRM_MEM_BUFS );
drm_free( y, ybuf_size, DRM_MEM_BUFS );
drm_free( buffer, buffer_size, DRM_MEM_BUFS );
drm_free( mask, mask_size, DRM_MEM_BUFS );
return DRM_ERR(EFAULT);
}
for ( i = 0 ; i < count ; i++ ) {
if ( mask[i] ) {
BEGIN_RING( 6 );
OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
R128_GMC_BRUSH_SOLID_COLOR |
(dev_priv->depth_fmt << 8) |
R128_GMC_SRC_DATATYPE_COLOR |
R128_ROP3_P |
R128_GMC_CLR_CMP_CNTL_DIS |
R128_GMC_WR_MSK_DIS );
OUT_RING( dev_priv->depth_pitch_offset_c );
OUT_RING( buffer[i] );
OUT_RING( (x[i] << 16) | y[i] );
OUT_RING( (1 << 16) | 1 );
ADVANCE_RING();
}
}
drm_free( mask, mask_size, DRM_MEM_BUFS );
} else {
for ( i = 0 ; i < count ; i++ ) {
BEGIN_RING( 6 );
OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
R128_GMC_BRUSH_SOLID_COLOR |
(dev_priv->depth_fmt << 8) |
R128_GMC_SRC_DATATYPE_COLOR |
R128_ROP3_P |
R128_GMC_CLR_CMP_CNTL_DIS |
R128_GMC_WR_MSK_DIS );
OUT_RING( dev_priv->depth_pitch_offset_c );
OUT_RING( buffer[i] );
OUT_RING( (x[i] << 16) | y[i] );
OUT_RING( (1 << 16) | 1 );
ADVANCE_RING();
}
}
drm_free( x, xbuf_size, DRM_MEM_BUFS );
drm_free( y, ybuf_size, DRM_MEM_BUFS );
drm_free( buffer, buffer_size, DRM_MEM_BUFS );
return 0;
}
static int r128_cce_dispatch_read_span( drm_device_t *dev,
drm_r128_depth_t *depth )
{
drm_r128_private_t *dev_priv = dev->dev_private;
int count, x, y;
RING_LOCALS;
DRM_DEBUG( "\n" );
count = depth->n;
if (count > 4096 || count <= 0)
return DRM_ERR(EMSGSIZE);
if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) {
return DRM_ERR(EFAULT);
}
if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) {
return DRM_ERR(EFAULT);
}
BEGIN_RING( 7 );
OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) );
OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL |
R128_GMC_DST_PITCH_OFFSET_CNTL |
R128_GMC_BRUSH_NONE |
(dev_priv->depth_fmt << 8) |
R128_GMC_SRC_DATATYPE_COLOR |
R128_ROP3_S |
R128_DP_SRC_SOURCE_MEMORY |
R128_GMC_CLR_CMP_CNTL_DIS |
R128_GMC_WR_MSK_DIS );
OUT_RING( dev_priv->depth_pitch_offset_c );
OUT_RING( dev_priv->span_pitch_offset_c );
OUT_RING( (x << 16) | y );
OUT_RING( (0 << 16) | 0 );
OUT_RING( (count << 16) | 1 );
ADVANCE_RING();
return 0;
}
static int r128_cce_dispatch_read_pixels( drm_device_t *dev,
drm_r128_depth_t *depth )
{
drm_r128_private_t *dev_priv = dev->dev_private;
int count, *x, *y;
int i, xbuf_size, ybuf_size;
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
count = depth->n;
if (count > 4096 || count <= 0)
return DRM_ERR(EMSGSIZE);
if ( count > dev_priv->depth_pitch ) {
count = dev_priv->depth_pitch;
}
xbuf_size = count * sizeof(*x);
ybuf_size = count * sizeof(*y);
x = drm_alloc( xbuf_size, DRM_MEM_BUFS );
if ( x == NULL ) {
return DRM_ERR(ENOMEM);
}
y = drm_alloc( ybuf_size, DRM_MEM_BUFS );
if ( y == NULL ) {
drm_free( x, xbuf_size, DRM_MEM_BUFS );
return DRM_ERR(ENOMEM);
}
if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) {
drm_free( x, xbuf_size, DRM_MEM_BUFS );
drm_free( y, ybuf_size, DRM_MEM_BUFS );
return DRM_ERR(EFAULT);
}
if ( DRM_COPY_FROM_USER( y, depth->y, ybuf_size ) ) {
drm_free( x, xbuf_size, DRM_MEM_BUFS );
drm_free( y, ybuf_size, DRM_MEM_BUFS );
return DRM_ERR(EFAULT);
}
for ( i = 0 ; i < count ; i++ ) {
BEGIN_RING( 7 );
OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) );
OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL |
R128_GMC_DST_PITCH_OFFSET_CNTL |
R128_GMC_BRUSH_NONE |
(dev_priv->depth_fmt << 8) |
R128_GMC_SRC_DATATYPE_COLOR |
R128_ROP3_S |
R128_DP_SRC_SOURCE_MEMORY |
R128_GMC_CLR_CMP_CNTL_DIS |
R128_GMC_WR_MSK_DIS );
OUT_RING( dev_priv->depth_pitch_offset_c );
OUT_RING( dev_priv->span_pitch_offset_c );
OUT_RING( (x[i] << 16) | y[i] );
OUT_RING( (i << 16) | 0 );
OUT_RING( (1 << 16) | 1 );
ADVANCE_RING();
}
drm_free( x, xbuf_size, DRM_MEM_BUFS );
drm_free( y, ybuf_size, DRM_MEM_BUFS );
return 0;
}
/* ================================================================
* Polygon stipple
*/
static void r128_cce_dispatch_stipple( drm_device_t *dev, u32 *stipple )
{
drm_r128_private_t *dev_priv = dev->dev_private;
int i;
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
BEGIN_RING( 33 );
OUT_RING( CCE_PACKET0( R128_BRUSH_DATA0, 31 ) );
for ( i = 0 ; i < 32 ; i++ ) {
OUT_RING( stipple[i] );
}
ADVANCE_RING();
}
/* ================================================================
* IOCTL functions
*/
int r128_cce_clear( DRM_IOCTL_ARGS )
{
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_r128_clear_t clear;
DRM_DEBUG( "\n" );
LOCK_TEST_WITH_RETURN( dev, filp );
DRM_COPY_FROM_USER_IOCTL( clear, (drm_r128_clear_t __user *) data,
sizeof(clear) );
RING_SPACE_TEST_WITH_RETURN( dev_priv );
if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS )
sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
r128_cce_dispatch_clear( dev, &clear );
COMMIT_RING();
/* Make sure we restore the 3D state next time.
*/
dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS;
return 0;
}
static int r128_do_init_pageflip( drm_device_t *dev )
{
drm_r128_private_t *dev_priv = dev->dev_private;
DRM_DEBUG( "\n" );
dev_priv->crtc_offset = R128_READ( R128_CRTC_OFFSET );
dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL );
R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset );
R128_WRITE( R128_CRTC_OFFSET_CNTL,
dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL );
dev_priv->page_flipping = 1;
dev_priv->current_page = 0;
dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
return 0;
}
int r128_do_cleanup_pageflip( drm_device_t *dev )
{
drm_r128_private_t *dev_priv = dev->dev_private;
DRM_DEBUG( "\n" );
R128_WRITE( R128_CRTC_OFFSET, dev_priv->crtc_offset );
R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl );
if (dev_priv->current_page != 0) {
r128_cce_dispatch_flip( dev );
COMMIT_RING();
}
dev_priv->page_flipping = 0;
return 0;
}
/* Swapping and flipping are different operations, need different ioctls.
* They can & should be intermixed to support multiple 3d windows.
*/
int r128_cce_flip( DRM_IOCTL_ARGS )
{
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
DRM_DEBUG( "%s\n", __FUNCTION__ );
LOCK_TEST_WITH_RETURN( dev, filp );
RING_SPACE_TEST_WITH_RETURN( dev_priv );
if (!dev_priv->page_flipping)
r128_do_init_pageflip( dev );
r128_cce_dispatch_flip( dev );
COMMIT_RING();
return 0;
}
int r128_cce_swap( DRM_IOCTL_ARGS )
{
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
DRM_DEBUG( "%s\n", __FUNCTION__ );
LOCK_TEST_WITH_RETURN( dev, filp );
RING_SPACE_TEST_WITH_RETURN( dev_priv );
if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS )
sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
r128_cce_dispatch_swap( dev );
dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT |
R128_UPLOAD_MASKS);
COMMIT_RING();
return 0;
}
int r128_cce_vertex( DRM_IOCTL_ARGS )
{
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_device_dma_t *dma = dev->dma;
drm_buf_t *buf;
drm_r128_buf_priv_t *buf_priv;
drm_r128_vertex_t vertex;
LOCK_TEST_WITH_RETURN( dev, filp );
if ( !dev_priv ) {
DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
return DRM_ERR(EINVAL);
}
DRM_COPY_FROM_USER_IOCTL( vertex, (drm_r128_vertex_t __user *) data,
sizeof(vertex) );
DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n",
DRM_CURRENTPID,
vertex.idx, vertex.count, vertex.discard );
if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
DRM_ERROR( "buffer index %d (of %d max)\n",
vertex.idx, dma->buf_count - 1 );
return DRM_ERR(EINVAL);
}
if ( vertex.prim < 0 ||
vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) {
DRM_ERROR( "buffer prim %d\n", vertex.prim );
return DRM_ERR(EINVAL);
}
RING_SPACE_TEST_WITH_RETURN( dev_priv );
VB_AGE_TEST_WITH_RETURN( dev_priv );
buf = dma->buflist[vertex.idx];
buf_priv = buf->dev_private;
if ( buf->filp != filp ) {
DRM_ERROR( "process %d using buffer owned by %p\n",
DRM_CURRENTPID, buf->filp );
return DRM_ERR(EINVAL);
}
if ( buf->pending ) {
DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
return DRM_ERR(EINVAL);
}
buf->used = vertex.count;
buf_priv->prim = vertex.prim;
buf_priv->discard = vertex.discard;
r128_cce_dispatch_vertex( dev, buf );
COMMIT_RING();
return 0;
}
int r128_cce_indices( DRM_IOCTL_ARGS )
{
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_device_dma_t *dma = dev->dma;
drm_buf_t *buf;
drm_r128_buf_priv_t *buf_priv;
drm_r128_indices_t elts;
int count;
LOCK_TEST_WITH_RETURN( dev, filp );
if ( !dev_priv ) {
DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
return DRM_ERR(EINVAL);
}
DRM_COPY_FROM_USER_IOCTL( elts, (drm_r128_indices_t __user *) data,
sizeof(elts) );
DRM_DEBUG( "pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID,
elts.idx, elts.start, elts.end, elts.discard );
if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
DRM_ERROR( "buffer index %d (of %d max)\n",
elts.idx, dma->buf_count - 1 );
return DRM_ERR(EINVAL);
}
if ( elts.prim < 0 ||
elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) {
DRM_ERROR( "buffer prim %d\n", elts.prim );
return DRM_ERR(EINVAL);
}
RING_SPACE_TEST_WITH_RETURN( dev_priv );
VB_AGE_TEST_WITH_RETURN( dev_priv );
buf = dma->buflist[elts.idx];
buf_priv = buf->dev_private;
if ( buf->filp != filp ) {
DRM_ERROR( "process %d using buffer owned by %p\n",
DRM_CURRENTPID, buf->filp );
return DRM_ERR(EINVAL);
}
if ( buf->pending ) {
DRM_ERROR( "sending pending buffer %d\n", elts.idx );
return DRM_ERR(EINVAL);
}
count = (elts.end - elts.start) / sizeof(u16);
elts.start -= R128_INDEX_PRIM_OFFSET;
if ( elts.start & 0x7 ) {
DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
return DRM_ERR(EINVAL);
}
if ( elts.start < buf->used ) {
DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
return DRM_ERR(EINVAL);
}
buf->used = elts.end;
buf_priv->prim = elts.prim;
buf_priv->discard = elts.discard;
r128_cce_dispatch_indices( dev, buf, elts.start, elts.end, count );
COMMIT_RING();
return 0;
}
int r128_cce_blit( DRM_IOCTL_ARGS )
{
DRM_DEVICE;
drm_device_dma_t *dma = dev->dma;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_blit_t blit;
int ret;
LOCK_TEST_WITH_RETURN( dev, filp );
DRM_COPY_FROM_USER_IOCTL( blit, (drm_r128_blit_t __user *) data,
sizeof(blit) );
DRM_DEBUG( "pid=%d index=%d\n", DRM_CURRENTPID, blit.idx );
if ( blit.idx < 0 || blit.idx >= dma->buf_count ) {
DRM_ERROR( "buffer index %d (of %d max)\n",
blit.idx, dma->buf_count - 1 );
return DRM_ERR(EINVAL);
}
RING_SPACE_TEST_WITH_RETURN( dev_priv );
VB_AGE_TEST_WITH_RETURN( dev_priv );
ret = r128_cce_dispatch_blit( filp, dev, &blit );
COMMIT_RING();
return ret;
}
int r128_cce_depth( DRM_IOCTL_ARGS )
{
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_depth_t depth;
int ret;
LOCK_TEST_WITH_RETURN( dev, filp );
DRM_COPY_FROM_USER_IOCTL( depth, (drm_r128_depth_t __user *) data,
sizeof(depth) );
RING_SPACE_TEST_WITH_RETURN( dev_priv );
ret = DRM_ERR(EINVAL);
switch ( depth.func ) {
case R128_WRITE_SPAN:
ret = r128_cce_dispatch_write_span( dev, &depth );
case R128_WRITE_PIXELS:
ret = r128_cce_dispatch_write_pixels( dev, &depth );
case R128_READ_SPAN:
ret = r128_cce_dispatch_read_span( dev, &depth );
case R128_READ_PIXELS:
ret = r128_cce_dispatch_read_pixels( dev, &depth );
}
COMMIT_RING();
return ret;
}
int r128_cce_stipple( DRM_IOCTL_ARGS )
{
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_stipple_t stipple;
u32 mask[32];