/** * \file drm_proc.c * /proc support for DRM * * \author Rickard E. (Rik) Faith * \author Gareth Hughes * * \par Acknowledgements: * Matthew J Sottek sent in a patch to fix * the problem with the proc files not outputting all their information. */ /* * Created: Mon Jan 11 09:48:47 1999 by faith@valinux.com * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include "drmP.h" static int drm_name_info(char *buf, char **start, off_t offset, int request, int *eof, void *data); static int drm_vm_info(char *buf, char **start, off_t offset, int request, int *eof, void *data); static int drm_clients_info(char *buf, char **start, off_t offset, int request, int *eof, void *data); static int drm_queues_info(char *buf, char **start, off_t offset, int request, int *eof, void *data); static int drm_bufs_info(char *buf, char **start, off_t offset, int request, int *eof, void *data); #if DRM_DEBUG_CODE static int drm_vma_info(char *buf, char **start, off_t offset, int request, int *eof, void *data); #endif /** * Proc file list. */ static struct drm_proc_list { const char *name; /**< file name */ int (*f) (char *, char **, off_t, int, int *, void *); /**< proc callback*/ } drm_proc_list[] = { {"name", drm_name_info}, {"mem", drm_mem_info}, {"vm", drm_vm_info}, {"clients", drm_clients_info}, {"queues", drm_queues_info}, {"bufs", drm_bufs_info}, #if DRM_DEBUG_CODE {"vma", drm_vma_info}, #endif }; #define DRM_PROC_ENTRIES (sizeof(drm_proc_list)/sizeof(drm_proc_list[0])) /** * Initialize the DRI proc filesystem for a device. * * \param dev DRM device. * \param minor device minor number. * \param root DRI proc dir entry. * \param dev_root resulting DRI device proc dir entry. * \return root entry pointer on success, or NULL on failure. * * Create the DRI proc root entry "/proc/dri", the device proc root entry * "/proc/dri/%minor%/", and each entry in proc_list as * "/proc/dri/%minor%/%name%". */ int drm_proc_init(drm_device_t * dev, int minor, struct proc_dir_entry *root, struct proc_dir_entry **dev_root) { struct proc_dir_entry *ent; int i, j; char name[64]; sprintf(name, "%d", minor); *dev_root = create_proc_entry(name, S_IFDIR, root); if (!*dev_root) { DRM_ERROR("Cannot create /proc/dri/%s\n", name); return -1; } for (i = 0; i < DRM_PROC_ENTRIES; i++) { ent = create_proc_entry(drm_proc_list[i].name, S_IFREG | S_IRUGO, *dev_root); if (!ent) { DRM_ERROR("Cannot create /proc/dri/%s/%s\n", name, drm_proc_list[i].name); for (j = 0; j < i; j++) remove_proc_entry(drm_proc_list[i].name, *dev_root); remove_proc_entry(name, root); return -1; } ent->read_proc = drm_proc_list[i].f; ent->data = dev; } return 0; } /** * Cleanup the proc filesystem resources. * * \param minor device minor number. * \param root DRI proc dir entry. * \param dev_root DRI device proc dir entry. * \return always zero. * * Remove all proc entries created by proc_init(). */ int drm_proc_cleanup(int minor, struct proc_dir_entry *root, struct proc_dir_entry *dev_root) { int i; char name[64]; if (!root || !dev_root) return 0; for (i = 0; i < DRM_PROC_ENTRIES; i++) remove_proc_entry(drm_proc_list[i].name, dev_root); sprintf(name, "%d", minor); remove_proc_entry(name, root); return 0; } /** * Called when "/proc/dri/.../name" is read. * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. * \param request requested number of bytes. * \param eof whether there is no more data to return. * \param data private data. * \return number of written bytes. * * Prints the device name together with the bus id if available. */ static int drm_name_info(char *buf, char **start, off_t offset, int request, int *eof, void *data) { drm_device_t *dev = (drm_device_t *) data; int len = 0; if (offset > DRM_PROC_LIMIT) { *eof = 1; return 0; } *start = &buf[offset]; *eof = 0; if (dev->unique) { DRM_PROC_PRINT("%s %s %s\n", dev->driver->pci_driver.name, pci_name(dev->pdev), dev->unique); } else { DRM_PROC_PRINT("%s %s\n", dev->driver->pci_driver.name, pci_name(dev->pdev)); } if (len > request + offset) return request; *eof = 1; return len - offset; } /** * Called when "/proc/dri/.../vm" is read. * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. * \param request requested number of bytes. * \param eof whether there is no more data to return. * \param data private data. * \return number of written bytes. * * Prints information about all mappings in drm_device::maplist. */ static int drm__vm_info(char *buf, char **start, off_t offset, int request, int *eof, void *data) { drm_device_t *dev = (drm_device_t *) data; int len = 0; drm_map_t *map; drm_map_list_t *r_list; struct list_head *list; /* Hardcoded from _DRM_FRAME_BUFFER, _DRM_REGISTERS, _DRM_SHM, _DRM_AGP, _DRM_SCATTER_GATHER, and _DRM_CONSISTENT. */ const char *types[] = { "FB", "REG", "SHM", "AGP", "SG", "PCI" }; const char *type; int i; if (offset > DRM_PROC_LIMIT) { *eof = 1; return 0; } *start = &buf[offset]; *eof = 0; DRM_PROC_PRINT("slot offset size type flags " "address mtrr\n\n"); i = 0; if (dev->maplist != NULL) list_for_each(list, &dev->maplist->head) { r_list = list_entry(list, drm_map_list_t, head); map = r_list->map; if (!map) continue; if (map->type < 0 || map->type > 5) type = "??"; else type = types[map->type]; DRM_PROC_PRINT("%4d 0x%08lx 0x%08lx %4.4s 0x%02x 0x%08lx ", i, map->offset, map->size, type, map->flags, (unsigned long)map->handle); if (map->mtrr < 0) { DRM_PROC_PRINT("none\n"); } else { DRM_PROC_PRINT("%4d\n", map->mtrr); } i++; } if (len > request + offset) return request; *eof = 1; return len - offset; } /** * Simply calls _vm_info() while holding the drm_device::struct_sem lock. */ static int drm_vm_info(char *buf, char **start, off_t offset, int request, int *eof, void *data) { drm_device_t *dev = (drm_device_t *) data; int ret; down(&dev->struct_sem); ret = drm__vm_info(buf, start, offset, request, eof, data); up(&dev->struct_sem); return ret; } /** * Called when "/proc/dri/.../queues" is read. * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. * \param request requested number of bytes. * \param eof whether there is no more data to return. * \param data private data. * \return number of written bytes. */ static int drm__queues_info(char *buf, char **start, off_t offset, int request, int *eof, void *data) { drm_device_t *dev = (drm_device_t *) data; int len = 0; int i; drm_queue_t *q; if (offset > DRM_PROC_LIMIT) { *eof = 1; return 0; } *start = &buf[offset]; *eof = 0; DRM_PROC_PRINT(" ctx/flags use fin" " blk/rw/rwf wait flushed queued" " locks\n\n"); for (i = 0; i < dev->queue_count; i++) { q = dev->queuelist[i]; atomic_inc(&q->use_count); DRM_PROC_PRINT_RET(atomic_dec(&q->use_count), "%5d/0x%03x %5d %5d" " %5d/%c%c/%c%c%c %5Zd\n", i, q->flags, atomic_read(&q->use_count), atomic_read(&q->finalization), atomic_read(&q->block_count), atomic_read(&q->block_read) ? 'r' : '-', atomic_read(&q->block_write) ? 'w' : '-', waitqueue_active(&q->read_queue) ? 'r' : '-', waitqueue_active(&q-> write_queue) ? 'w' : '-', waitqueue_active(&q-> flush_queue) ? 'f' : '-', DRM_BUFCOUNT(&q->waitlist)); atomic_dec(&q->use_count); } if (len > request + offset) return request; *eof = 1; return len - offset; } /** * Simply calls _queues_info() while holding the drm_device::struct_sem lock. */ static int drm_queues_info(char *buf, char **start, off_t offset, int request, int *eof, void *data) { drm_device_t *dev = (drm_device_t *) data; int ret; down(&dev->struct_sem); ret = drm__queues_info(buf, start, offset, request, eof, data); up(&dev->struct_sem); return ret; } /** * Called when "/proc/dri/.../bufs" is read. * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. * \param request requested number of bytes. * \param eof whether there is no more data to return. * \param data private data. * \return number of written bytes. */ static int drm__bufs_info(char *buf, char **start, off_t offset, int request, int *eof, void *data) { drm_device_t *dev = (drm_device_t *) data; int len = 0; drm_device_dma_t *dma = dev->dma; int i; if (!dma || offset > DRM_PROC_LIMIT) { *eof = 1; return 0; } *start = &buf[offset]; *eof = 0; DRM_PROC_PRINT(" o size count free segs pages kB\n\n"); for (i = 0; i <= DRM_MAX_ORDER; i++) { if (dma->bufs[i].buf_count) DRM_PROC_PRINT("%2d %8d %5d %5d %5d %5d %5ld\n", i, dma->bufs[i].buf_size, dma->bufs[i].buf_count, atomic_read(&dma->bufs[i] .freelist.count), dma->bufs[i].seg_count, dma->bufs[i].seg_count * (1 << dma->bufs[i].page_order), (dma->bufs[i].seg_count * (1 << dma->bufs[i].page_order)) * PAGE_SIZE / 1024); } DRM_PROC_PRINT("\n"); for (i = 0; i < dma->buf_count; i++) { if (i && !(i % 32)) DRM_PROC_PRINT("\n"); DRM_PROC_PRINT(" %d", dma->buflist[i]->list); } DRM_PROC_PRINT("\n"); if (len > request + offset) return request; *eof = 1; return len - offset; } /** * Simply calls _bufs_info() while holding the drm_device::struct_sem lock. */ static int drm_bufs_info(char *buf, char **start, off_t offset, int request, int *eof, void *data) { drm_device_t *dev = (drm_device_t *) data; int ret; down(&dev->struct_sem); ret = drm__bufs_info(buf, start, offset, request, eof, data); up(&dev->struct_sem); return ret; } /** * Called when "/proc/dri/.../clients" is read. * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. * \param request requested number of bytes. * \param eof whether there is no more data to return. * \param data private data. * \return number of written bytes. */ static int drm__clients_info(char *buf, char **start, off_t offset, int request, int *eof, void *data) { drm_device_t *dev = (drm_device_t *) data; int len = 0; drm_file_t *priv; if (offset > DRM_PROC_LIMIT) { *eof = 1; return 0; } *start = &buf[offset]; *eof = 0; DRM_PROC_PRINT("a dev pid uid magic ioctls\n\n"); for (priv = dev->file_first; priv; priv = priv->next) { DRM_PROC_PRINT("%c %3d %5d %5d %10u %10lu\n", priv->authenticated ? 'y' : 'n', priv->minor, priv->pid, priv->uid, priv->magic, priv->ioctl_count); } if (len > request + offset) return request; *eof = 1; return len - offset; } /** * Simply calls _clients_info() while holding the drm_device::struct_sem lock. */ static int drm_clients_info(char *buf, char **start, off_t offset, int request, int *eof, void *data) { drm_device_t *dev = (drm_device_t *) data; int ret; down(&dev->struct_sem); ret = drm__clients_info(buf, start, offset, request, eof, data); up(&dev->struct_sem); return ret; } #if DRM_DEBUG_CODE static int drm__vma_info(char *buf, char **start, off_t offset, int request, int *eof, void *data) { drm_device_t *dev = (drm_device_t *) data; int len = 0; drm_vma_entry_t *pt; struct vm_area_struct *vma; #if defined(__i386__) unsigned int pgprot; #endif if (offset > DRM_PROC_LIMIT) { *eof = 1; return 0; } *start = &buf[offset]; *eof = 0; DRM_PROC_PRINT("vma use count: %d, high_memory = %p, 0x%08lx\n", atomic_read(&dev->vma_count), high_memory, virt_to_phys(high_memory)); for (pt = dev->vmalist; pt; pt = pt->next) { if (!(vma = pt->vma)) continue; DRM_PROC_PRINT("\n%5d 0x%08lx-0x%08lx %c%c%c%c%c%c 0x%08lx", pt->pid, vma->vm_start, vma->vm_end, vma->vm_flags & VM_READ ? 'r' : '-', vma->vm_flags & VM_WRITE ? 'w' : '-', vma->vm_flags & VM_EXEC ? 'x' : '-', vma->vm_flags & VM_MAYSHARE ? 's' : 'p', vma->vm_flags & VM_LOCKED ? 'l' : '-', vma->vm_flags & VM_IO ? 'i' : '-', VM_OFFSET(vma)); #if defined(__i386__) pgprot = pgprot_val(vma->vm_page_prot); DRM_PROC_PRINT(" %c%c%c%c%c%c%c%c%c", pgprot & _PAGE_PRESENT ? 'p' : '-', pgprot & _PAGE_RW ? 'w' : 'r', pgprot & _PAGE_USER ? 'u' : 's', pgprot & _PAGE_PWT ? 't' : 'b', pgprot & _PAGE_PCD ? 'u' : 'c', pgprot & _PAGE_ACCESSED ? 'a' : '-', pgprot & _PAGE_DIRTY ? 'd' : '-', pgprot & _PAGE_PSE ? 'm' : 'k', pgprot & _PAGE_GLOBAL ? 'g' : 'l'); #endif DRM_PROC_PRINT("\n"); } if (len > request + offset) return request; *eof = 1; return len - offset; } static int drm_vma_info(char *buf, char **start, off_t offset, int request, int *eof, void *data) { drm_device_t *dev = (drm_device_t *) data; int ret; down(&dev->struct_sem); ret = drm__vma_info(buf, start, offset, request, eof, data); up(&dev->struct_sem); return ret; } #endif 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 
/*
 * Copyright 2007-8 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 */
#include "drmP.h"
#include "radeon_drm.h"
#include "radeon_drv.h"

#include "drm_crtc_helper.h"

void radeon_restore_common_regs(struct drm_device *dev)
{
	/* don't need this yet */
}

static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
{
	struct drm_radeon_private *dev_priv = dev->dev_private;
	int i = 0;

	/* FIXME: Certain revisions of R300 can't recover here.  Not sure of
	   the cause yet, but this workaround will mask the problem for now.
	   Other chips usually will pass at the very first test, so the
	   workaround shouldn't have any effect on them. */
	for (i = 0;
	     (i < 10000 &&
	      RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
	     i++);
}

static void radeon_pll_write_update(struct drm_device *dev)
{
	struct drm_radeon_private *dev_priv = dev->dev_private;

	while (RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);

	RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
			   RADEON_PPLL_ATOMIC_UPDATE_W,
			   ~(RADEON_PPLL_ATOMIC_UPDATE_W));
}

static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
{
	struct drm_radeon_private *dev_priv = dev->dev_private;
	int i = 0;


	/* FIXME: Certain revisions of R300 can't recover here.  Not sure of
	   the cause yet, but this workaround will mask the problem for now.
	   Other chips usually will pass at the very first test, so the
	   workaround shouldn't have any effect on them. */
	for (i = 0;
	     (i < 10000 &&
	      RADEON_READ_PLL(dev_priv, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
	     i++);
}

static void radeon_pll2_write_update(struct drm_device *dev)
{
	struct drm_radeon_private *dev_priv = dev->dev_private;

	while (RADEON_READ_PLL(dev_priv, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);

	RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_REF_DIV,
			   RADEON_P2PLL_ATOMIC_UPDATE_W,
			   ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
}

static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
				       uint16_t fb_div)
{
	unsigned int vcoFreq;

        if (!ref_div)
		return 1;

	vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;

	/*
	 * This is horribly crude: the VCO frequency range is divided into
	 * 3 parts, each part having a fixed PLL gain value.
	 */
	if (vcoFreq >= 30000)
		/*
		 * [300..max] MHz : 7
		 */
		return 7;
	else if (vcoFreq >= 18000)
		/*
		 * [180..300) MHz : 4
		 */
		return 4;
	else
		/*
		 * [0..180) MHz : 1
		 */
		return 1;
}

void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct drm_radeon_private *dev_priv = dev->dev_private;
	uint32_t mask;

	DRM_DEBUG("\n");

	mask = radeon_crtc->crtc_id ?
		(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) :
		(RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS);

	switch(mode) {
	case DRM_MODE_DPMS_ON:
		if (radeon_crtc->crtc_id)
			RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, 0, ~mask);
		else {
			RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
			RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
		}
		break;
	case DRM_MODE_DPMS_STANDBY:
		if (radeon_crtc->crtc_id)
			RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS), ~mask);
		else {
			RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
			RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS), ~mask);
		}
		break;
	case DRM_MODE_DPMS_SUSPEND:
		if (radeon_crtc->crtc_id)
			RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS), ~mask);
		else {
			RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
			RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS), ~mask);
		}
		break;
	case DRM_MODE_DPMS_OFF:
		if (radeon_crtc->crtc_id)
			RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
		else {
			RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~RADEON_CRTC_DISP_REQ_EN_B);
			RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
		}
		break;
	}

	if (mode != DRM_MODE_DPMS_OFF) {
		radeon_crtc_load_lut(crtc);
	}
}

/* properly set crtc bpp when using atombios */
void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_radeon_private *dev_priv = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	int format;
	uint32_t crtc_gen_cntl, crtc2_gen_cntl;

	switch (crtc->fb->bits_per_pixel) {
	case 15:      /*  555 */
		format = 3;
		break;
	case 16:      /*  565 */
		format = 4;
		break;
	case 24:      /*  RGB */
		format = 5;
		break;
	case 32:      /* xRGB */
		format = 6;
		break;
	default:
		return;
	}

	switch (radeon_crtc->crtc_id) {
	case 0:
		crtc_gen_cntl = RADEON_READ(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
		crtc_gen_cntl |= (format << 8);
		crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
		RADEON_WRITE(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
		break;
	case 1:
		crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
		crtc2_gen_cntl |= (format << 8);
		RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
		// not sure we need these...
		RADEON_WRITE(RADEON_FP_H2_SYNC_STRT_WID,   RADEON_READ(RADEON_CRTC2_H_SYNC_STRT_WID));
		RADEON_WRITE(RADEON_FP_V2_SYNC_STRT_WID,   RADEON_READ(RADEON_CRTC2_V_SYNC_STRT_WID));
		break;
	}
}

static bool radeon_set_crtc1_base(struct drm_crtc *crtc, int x, int y)
{
	struct drm_device *dev = crtc->dev;
	struct drm_radeon_private *dev_priv = dev->dev_private;
	struct radeon_framebuffer *radeon_fb;
	struct drm_gem_object *obj;
	struct drm_radeon_gem_object *obj_priv;
	uint32_t base;
	uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
	uint32_t crtc_pitch;
	uint32_t disp_merge_cntl;

	DRM_DEBUG("\n");

	radeon_fb = to_radeon_framebuffer(crtc->fb);

	obj = radeon_fb->base.mm_private;
	obj_priv = obj->driver_private;

	crtc_offset = obj_priv->bo->offset;

	crtc_offset_cntl = 0;

	/* TODO tiling */
	if (0) {
		if (radeon_is_r300(dev_priv))
			crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
					     R300_CRTC_MICRO_TILE_BUFFER_DIS |
					     R300_CRTC_MACRO_TILE_EN);
		else
			crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
	} else {
		if (radeon_is_r300(dev_priv))
			crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
					      R300_CRTC_MICRO_TILE_BUFFER_DIS |
					      R300_CRTC_MACRO_TILE_EN);
		else
			crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
	}

	base = obj_priv->bo->offset;

	/* TODO more tiling */
	if (0) {
		if (radeon_is_r300(dev_priv)) {
			crtc_tile_x0_y0 = x | (y << 16);
			base &= ~0x7ff;
		} else {
			int byteshift = crtc->fb->bits_per_pixel >> 4;
			int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11;
			base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
			crtc_offset_cntl |= (y % 16);
		}
	} else {
		int offset = y * crtc->fb->pitch + x;
		switch (crtc->fb->bits_per_pixel) {
		case 15:
		case 16:
			offset *= 2;
			break;
		case 24:
			offset *= 3;
			break;
		case 32:
			offset *= 4;
			break;
		default:
			return false;
		}
		base += offset;
	}

	base &= ~7;

	/* update sarea TODO */

	crtc_offset = base;

	crtc_pitch  = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
			((crtc->fb->bits_per_pixel * 8) - 1)) /
		       (crtc->fb->bits_per_pixel * 8));
	crtc_pitch |= crtc_pitch << 16;

	DRM_DEBUG("mc_fb_location: 0x%x\n", dev_priv->fb_location);

	RADEON_WRITE(RADEON_DISPLAY_BASE_ADDR, dev_priv->fb_location);

	if (radeon_is_r300(dev_priv))
		RADEON_WRITE(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
	RADEON_WRITE(RADEON_CRTC_OFFSET_CNTL, crtc_offset_cntl);
	RADEON_WRITE(RADEON_CRTC_OFFSET, crtc_offset);
	RADEON_WRITE(RADEON_CRTC_PITCH, crtc_pitch);

	disp_merge_cntl = RADEON_READ(RADEON_DISP_MERGE_CNTL);
	disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
	RADEON_WRITE(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);

	return true;
}

static bool radeon_set_crtc1_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
{
	struct drm_device *dev = crtc->dev;
	struct drm_radeon_private *dev_priv = dev->dev_private;
	int format;
	int hsync_start;
	int hsync_wid;
	int vsync_wid;
	uint32_t crtc_gen_cntl;
	uint32_t crtc_ext_cntl;
	uint32_t crtc_h_total_disp;
	uint32_t crtc_h_sync_strt_wid;
	uint32_t crtc_v_total_disp;
	uint32_t crtc_v_sync_strt_wid;

	DRM_DEBUG("\n");

	switch (crtc->fb->bits_per_pixel) {
	case 15:      /*  555 */
		format = 3;
		break;
	case 16:      /*  565 */
		format = 4;
		break;
	case 24:      /*  RGB */
		format = 5;
		break;
	case 32:      /* xRGB */
		format = 6;
		break;
	default:
		return false;
	}

	crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
			 | RADEON_CRTC_EN
			 | (format << 8)
			 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
			    ? RADEON_CRTC_DBL_SCAN_EN
			    : 0)
			 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
			    ? RADEON_CRTC_CSYNC_EN
			    : 0)
			 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
			    ? RADEON_CRTC_INTERLACE_EN
			    : 0));

	crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
	crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
			  RADEON_CRTC_VSYNC_DIS |
			  RADEON_CRTC_HSYNC_DIS |
			  RADEON_CRTC_DISPLAY_DIS);

	crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
			     | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));

	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
	if (!hsync_wid)
		hsync_wid = 1;
	hsync_start = mode->crtc_hsync_start - 8;

	crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
				| ((hsync_wid & 0x3f) << 16)
				| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
				   ? RADEON_CRTC_H_SYNC_POL
				   : 0));

	/* This works for double scan mode. */
	crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
			     | ((mode->crtc_vdisplay - 1) << 16));

	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
	if (!vsync_wid)
		vsync_wid = 1;

	crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
				| ((vsync_wid & 0x1f) << 16)
				| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
				   ? RADEON_CRTC_V_SYNC_POL
				   : 0));

	/* TODO -> Dell Server */
	if (0) {
		uint32_t disp_hw_debug = RADEON_READ(RADEON_DISP_HW_DEBUG);
		uint32_t tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
		uint32_t dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2);
		uint32_t crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);

		dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
		dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;

		/* For CRT on DAC2, don't turn it on if BIOS didn't
		   enable it, even it's detected.
		*/
		disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
		tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
		tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));

		RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		RADEON_WRITE(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
		RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
	}

	RADEON_WRITE(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl |
		     RADEON_CRTC_DISP_REQ_EN_B);

	RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl,
		       RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_DISPLAY_DIS);

	RADEON_WRITE(RADEON_CRTC_H_TOTAL_DISP, crtc_h_total_disp);
	RADEON_WRITE(RADEON_CRTC_H_SYNC_STRT_WID, crtc_h_sync_strt_wid);
	RADEON_WRITE(RADEON_CRTC_V_TOTAL_DISP, crtc_v_total_disp);
	RADEON_WRITE(RADEON_CRTC_V_SYNC_STRT_WID, crtc_v_sync_strt_wid);

	RADEON_WRITE(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);

	return true;
}

static void radeon_set_pll1(struct drm_crtc *crtc, struct drm_display_mode *mode)
{
	struct drm_device *dev = crtc->dev;
	struct drm_radeon_private *dev_priv = dev->dev_private;
	struct drm_encoder *encoder;
	uint32_t feedback_div = 0;
	uint32_t reference_div = 0;
	uint32_t post_divider = 0;
	uint32_t freq = 0;
	uint8_t pll_gain;
	int pll_flags = RADEON_PLL_LEGACY;
	bool use_bios_divs = false;
	/* PLL registers */
	uint32_t ppll_ref_div = 0;
        uint32_t ppll_div_3 = 0;
        uint32_t htotal_cntl = 0;
        uint32_t vclk_ecp_cntl;

	struct radeon_pll *pll = &dev_priv->mode_info.p1pll;

	struct {
		int divider;
		int bitvalue;
	} *post_div, post_divs[]   = {
		/* From RAGE 128 VR/RAGE 128 GL Register
		 * Reference Manual (Technical Reference
		 * Manual P/N RRG-G04100-C Rev. 0.04), page
		 * 3-17 (PLL_DIV_[3:0]).
		 */
		{  1, 0 },              /* VCLK_SRC                 */
		{  2, 1 },              /* VCLK_SRC/2               */
		{  4, 2 },              /* VCLK_SRC/4               */
		{  8, 3 },              /* VCLK_SRC/8               */
		{  3, 4 },              /* VCLK_SRC/3               */
		{ 16, 5 },              /* VCLK_SRC/16              */
		{  6, 6 },              /* VCLK_SRC/6               */
		{ 12, 7 },              /* VCLK_SRC/12              */
		{  0, 0 }
	};

	if (mode->clock > 200000) /* range limits??? */
		pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
	else
		pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc) {
			if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
				pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
			if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
				struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

				if (radeon_encoder->use_bios_dividers) {
					ppll_ref_div = radeon_encoder->panel_ref_divider;
					ppll_div_3   = (radeon_encoder->panel_fb_divider |
							(radeon_encoder->panel_post_divider << 16));
					htotal_cntl  = 0;
					use_bios_divs = true;
				} else
					pll_flags |= RADEON_PLL_USE_REF_DIV;
			}
		}
	}

	DRM_DEBUG("\n");

	if (!use_bios_divs) {
		radeon_compute_pll(pll, mode->clock, &freq, &feedback_div, &reference_div, &post_divider, pll_flags);

		for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
			if (post_div->divider == post_divider)
				break;
		}

		if (!post_div->divider) {
			post_div = &post_divs[0];
		}

		DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
			  (unsigned)freq,
			  feedback_div,
			  reference_div,
			  post_divider);

		ppll_ref_div   = reference_div;
#if defined(__powerpc__) && (0) /* TODO */
		/* apparently programming this otherwise causes a hang??? */
		if (info->MacModel == RADEON_MAC_IBOOK)
			state->ppll_div_3 = 0x000600ad;
		else
#endif
			ppll_div_3     = (feedback_div | (post_div->bitvalue << 16));
		htotal_cntl    = mode->htotal & 0x7;

	}

	vclk_ecp_cntl = (RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL) &
			 ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;

	pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.p1pll.reference_freq,
					   ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
					   ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK);

	if (dev_priv->flags & RADEON_IS_MOBILITY) {
		/* A temporal workaround for the occational blanking on certain laptop panels.
		   This appears to related to the PLL divider registers (fail to lock?).
		   It occurs even when all dividers are the same with their old settings.
		   In this case we really don't need to fiddle with PLL registers.
		   By doing this we can avoid the blanking problem with some panels.
		*/
		if ((ppll_ref_div == (RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
		    (ppll_div_3 == (RADEON_READ_PLL(dev_priv, RADEON_PPLL_DIV_3) &
					   (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
			RADEON_WRITE_P(RADEON_CLOCK_CNTL_INDEX,
				       RADEON_PLL_DIV_SEL,
				       ~(RADEON_PLL_DIV_SEL));
			radeon_pll_errata_after_index(dev_priv);
			return;
		}
	}

	RADEON_WRITE_PLL_P(dev_priv, RADEON_VCLK_ECP_CNTL,
			   RADEON_VCLK_SRC_SEL_CPUCLK,
			   ~(RADEON_VCLK_SRC_SEL_MASK));
	RADEON_WRITE_PLL_P(dev_priv,
			   RADEON_PPLL_CNTL,
			   RADEON_PPLL_RESET
			   | RADEON_PPLL_ATOMIC_UPDATE_EN
			   | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
			   | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
			   ~(RADEON_PPLL_RESET
			     | RADEON_PPLL_ATOMIC_UPDATE_EN
			     | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
			     | RADEON_PPLL_PVG_MASK));

	RADEON_WRITE_P(RADEON_CLOCK_CNTL_INDEX,
		       RADEON_PLL_DIV_SEL,
		       ~(RADEON_PLL_DIV_SEL));
	radeon_pll_errata_after_index(dev_priv);

	if (radeon_is_r300(dev_priv) ||
	    (dev_priv->chip_family == CHIP_RS300) ||
	    (dev_priv->chip_family == CHIP_RS400) ||
	    (dev_priv->chip_family == CHIP_RS480)) {
		if (ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
			/* When restoring console mode, use saved PPLL_REF_DIV
			 * setting.
			 */
			RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
					   ppll_ref_div,
					   0);
		} else {
			/* R300 uses ref_div_acc field as real ref divider */
			RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
					   (ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
					   ~R300_PPLL_REF_DIV_ACC_MASK);
		}
	} else {
		RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
				   ppll_ref_div,
				   ~RADEON_PPLL_REF_DIV_MASK);
	}

	RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_DIV_3,
			   ppll_div_3,
			   ~RADEON_PPLL_FB3_DIV_MASK);

	RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_DIV_3,
			   ppll_div_3,
			   ~RADEON_PPLL_POST3_DIV_MASK);

	radeon_pll_write_update(dev);
	radeon_pll_wait_for_read_update_complete(dev);

	RADEON_WRITE_PLL(dev_priv, RADEON_HTOTAL_CNTL, htotal_cntl);

	RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_CNTL,
			   0,
			   ~(RADEON_PPLL_RESET
			     | RADEON_PPLL_SLEEP
			     | RADEON_PPLL_ATOMIC_UPDATE_EN
			     | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));

	DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
		  ppll_ref_div,
		  ppll_div_3,
		  (unsigned)htotal_cntl,
		  RADEON_READ_PLL(dev_priv, RADEON_PPLL_CNTL));
	DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
		  ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
		  ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
		  (ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16);

	mdelay(50); /* Let the clock to lock */

	RADEON_WRITE_PLL_P(dev_priv, RADEON_VCLK_ECP_CNTL,
			   RADEON_VCLK_SRC_SEL_PPLLCLK,
			   ~(RADEON_VCLK_SRC_SEL_MASK));

	/*RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);*/

}

static bool radeon_set_crtc2_base(struct drm_crtc *crtc, int x, int y)
{
	struct drm_device *dev = crtc->dev;
	struct drm_radeon_private *dev_priv = dev->dev_private;
	struct radeon_framebuffer *radeon_fb;
	struct drm_gem_object *obj;
	struct drm_radeon_gem_object *obj_priv;
	uint32_t base;
	uint32_t crtc2_offset, crtc2_offset_cntl, crtc2_tile_x0_y0 = 0;
        uint32_t crtc2_pitch;
	uint32_t disp2_merge_cntl;

	DRM_DEBUG("\n");

	radeon_fb = to_radeon_framebuffer(crtc->fb);

	obj = radeon_fb->base.mm_private;
	obj_priv = obj->driver_private;

	crtc2_offset = obj_priv->bo->offset;

	crtc2_offset_cntl = 0;

	/* TODO tiling */
	if (0) {
		if (radeon_is_r300(dev_priv))
			crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
					      R300_CRTC_MICRO_TILE_BUFFER_DIS |
					      R300_CRTC_MACRO_TILE_EN);
		else
			crtc2_offset_cntl |= RADEON_CRTC_TILE_EN;
	} else {
		if (radeon_is_r300(dev_priv))
			crtc2_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
					       R300_CRTC_MICRO_TILE_BUFFER_DIS |
					       R300_CRTC_MACRO_TILE_EN);
		else
			crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN;
	}

	base = obj_priv->bo->offset;

	/* TODO more tiling */
	if (0) {
		if (radeon_is_r300(dev_priv)) {
			crtc2_tile_x0_y0 = x | (y << 16);
			base &= ~0x7ff;
		} else {
			int byteshift = crtc->fb->bits_per_pixel >> 4;
			int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11;
			base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
			crtc2_offset_cntl |= (y % 16);
		}
	} else {
		int offset = y * crtc->fb->pitch + x;
		switch (crtc->fb->bits_per_pixel) {
		case 15:
		case 16:
			offset *= 2;
			break;
		case 24:
			offset *= 3;
			break;
		case 32:
			offset *= 4;
			break;
		default:
			return false;
		}
		base += offset;
	}

	base &= ~7;

	/* update sarea TODO */

	crtc2_offset = base;

	crtc2_pitch  = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
			((crtc->fb->bits_per_pixel * 8) - 1)) /
		       (crtc->fb->bits_per_pixel * 8));
	crtc2_pitch |= crtc2_pitch << 16;

	RADEON_WRITE(RADEON_DISPLAY2_BASE_ADDR, dev_priv->fb_location);

	if (radeon_is_r300(dev_priv))
		RADEON_WRITE(R300_CRTC2_TILE_X0_Y0, crtc2_tile_x0_y0);
	RADEON_WRITE(RADEON_CRTC2_OFFSET_CNTL, crtc2_offset_cntl);
	RADEON_WRITE(RADEON_CRTC2_OFFSET, crtc2_offset);
	RADEON_WRITE(RADEON_CRTC2_PITCH, crtc2_pitch);

	disp2_merge_cntl = RADEON_READ(RADEON_DISP2_MERGE_CNTL);
	disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
	RADEON_WRITE(RADEON_DISP2_MERGE_CNTL,      disp2_merge_cntl);

	return true;
}

static bool radeon_set_crtc2_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
{
	struct drm_device *dev = crtc->dev;
	struct drm_radeon_private *dev_priv = dev->dev_private;
	int format;
	int hsync_start;
	int hsync_wid;
	int vsync_wid;
	uint32_t crtc2_gen_cntl;
	uint32_t crtc2_h_total_disp;
        uint32_t crtc2_h_sync_strt_wid;
        uint32_t crtc2_v_total_disp;
        uint32_t crtc2_v_sync_strt_wid;
	uint32_t fp_h2_sync_strt_wid;
	uint32_t fp_v2_sync_strt_wid;

	DRM_DEBUG("\n");

	switch (crtc->fb->bits_per_pixel) {
		
	case 15:      /*  555 */
		format = 3;
		break;
	case 16:      /*  565 */
		format = 4;
		break;
	case 24:      /*  RGB */
		format = 5;
		break;
	case 32:      /* xRGB */
		format = 6;
		break;
	default:
		return false;
	}

	crtc2_h_total_disp =
		((((mode->crtc_htotal / 8) - 1) & 0x3ff)
		 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));

	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
	if (!hsync_wid)
		hsync_wid = 1;
	hsync_start = mode->crtc_hsync_start - 8;

	crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff)
				 | ((hsync_wid & 0x3f) << 16)
				 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
				    ? RADEON_CRTC_H_SYNC_POL
				    : 0));

	/* This works for double scan mode. */
	crtc2_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
			      | ((mode->crtc_vdisplay - 1) << 16));

	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
	if (!vsync_wid)
		vsync_wid = 1;

	crtc2_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
				 | ((vsync_wid & 0x1f) << 16)
				 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
				    ? RADEON_CRTC2_V_SYNC_POL
				    : 0));

	/* check to see if TV DAC is enabled for another crtc and keep it enabled */
	if (RADEON_READ(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON)
		crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
	else
		crtc2_gen_cntl = 0;

	crtc2_gen_cntl |= (RADEON_CRTC2_EN
			   | (format << 8)
			   | RADEON_CRTC2_VSYNC_DIS
			   | RADEON_CRTC2_HSYNC_DIS
			   | RADEON_CRTC2_DISP_DIS
			   | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
			      ? RADEON_CRTC2_DBL_SCAN_EN
			      : 0)
			   | ((mode->flags & DRM_MODE_FLAG_CSYNC)
			      ? RADEON_CRTC2_CSYNC_EN
			      : 0)
			   | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
			      ? RADEON_CRTC2_INTERLACE_EN
			      : 0));

	fp_h2_sync_strt_wid = crtc2_h_sync_strt_wid;
	fp_v2_sync_strt_wid = crtc2_v_sync_strt_wid;

	RADEON_WRITE(RADEON_CRTC2_GEN_CNTL,
		     crtc2_gen_cntl | RADEON_CRTC2_VSYNC_DIS |
		     RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_DIS |
		     RADEON_CRTC2_DISP_REQ_EN_B);

	RADEON_WRITE(RADEON_CRTC2_H_TOTAL_DISP,    crtc2_h_total_disp);
	RADEON_WRITE(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
	RADEON_WRITE(RADEON_CRTC2_V_TOTAL_DISP,    crtc2_v_total_disp);
	RADEON_WRITE(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);

	RADEON_WRITE(RADEON_FP_H2_SYNC_STRT_WID,   fp_h2_sync_strt_wid);
	RADEON_WRITE(RADEON_FP_V2_SYNC_STRT_WID,   fp_v2_sync_strt_wid);

	RADEON_WRITE(RADEON_CRTC2_GEN_CNTL,        crtc2_gen_cntl);

	return true;

}

static void radeon_set_pll2(struct drm_crtc *crtc, struct drm_display_mode *mode)
{
	struct drm_device *dev = crtc->dev;
	struct drm_radeon_private *dev_priv = dev->dev_private;
	struct drm_encoder *encoder;
	uint32_t feedback_div = 0;
	uint32_t reference_div = 0;
	uint32_t post_divider = 0;
	uint32_t freq = 0;
	uint8_t pll_gain;
	int pll_flags = RADEON_PLL_LEGACY;
	bool use_bios_divs = false;
	/* PLL2 registers */
	uint32_t p2pll_ref_div = 0;
	uint32_t p2pll_div_0 = 0;
	uint32_t htotal_cntl2 = 0;
	uint32_t pixclks_cntl;

	struct radeon_pll *pll = &dev_priv->mode_info.p2pll;

	struct {
		int divider;
		int bitvalue;
	} *post_div, post_divs[]   = {
		/* From RAGE 128 VR/RAGE 128 GL Register
		 * Reference Manual (Technical Reference
		 * Manual P/N RRG-G04100-C Rev. 0.04), page
		 * 3-17 (PLL_DIV_[3:0]).
		 */
		{  1, 0 },              /* VCLK_SRC                 */
		{  2, 1 },              /* VCLK_SRC/2               */
		{  4, 2 },              /* VCLK_SRC/4               */
		{  8, 3 },              /* VCLK_SRC/8               */
		{  3, 4 },              /* VCLK_SRC/3               */
		{  6, 6 },              /* VCLK_SRC/6               */
		{ 12, 7 },              /* VCLK_SRC/12              */
		{  0, 0 }
	};

	if (mode->clock > 200000) /* range limits??? */
		pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
	else
		pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc) {
			if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
				pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
			if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
				struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

				if (radeon_encoder->use_bios_dividers) {
					p2pll_ref_div = radeon_encoder->panel_ref_divider;
					p2pll_div_0   = (radeon_encoder->panel_fb_divider |
							(radeon_encoder->panel_post_divider << 16));
					htotal_cntl2  = 0;
					use_bios_divs = true;
				} else
					pll_flags |= RADEON_PLL_USE_REF_DIV;
			}
		}
	}

	DRM_DEBUG("\n");

	if (!use_bios_divs) {
		radeon_compute_pll(pll, mode->clock, &freq, &feedback_div, &reference_div, &post_divider, pll_flags);

		for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
			if (post_div->divider == post_divider)
				break;
		}

		if (!post_div->divider) {
			post_div = &post_divs[0];
		}

		DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
			  (unsigned)freq,
			  feedback_div,
			  reference_div,
			  post_divider);

		p2pll_ref_div    = reference_div;
		p2pll_div_0      = (feedback_div | (post_div->bitvalue << 16));
		htotal_cntl2     = mode->htotal & 0x7;

	}

	pixclks_cntl     = ((RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL) &
			     ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
			    RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);

	pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.p2pll.reference_freq,
					   p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
					   p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK);


	RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL,
			   RADEON_PIX2CLK_SRC_SEL_CPUCLK,
			   ~(RADEON_PIX2CLK_SRC_SEL_MASK));

	RADEON_WRITE_PLL_P(dev_priv,
			   RADEON_P2PLL_CNTL,
			   RADEON_P2PLL_RESET
			   | RADEON_P2PLL_ATOMIC_UPDATE_EN
			   | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
			   ~(RADEON_P2PLL_RESET
			     | RADEON_P2PLL_ATOMIC_UPDATE_EN
			     | RADEON_P2PLL_PVG_MASK));


	RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_REF_DIV,
			   p2pll_ref_div,
			   ~RADEON_P2PLL_REF_DIV_MASK);

	RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_DIV_0,
			   p2pll_div_0,
			   ~RADEON_P2PLL_FB0_DIV_MASK);

	RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_DIV_0,
			   p2pll_div_0,
			   ~RADEON_P2PLL_POST0_DIV_MASK);

	radeon_pll2_write_update(dev);
	radeon_pll2_wait_for_read_update_complete(dev);

	RADEON_WRITE_PLL(dev_priv, RADEON_HTOTAL2_CNTL, htotal_cntl2);

	RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_CNTL,
			   0,
			   ~(RADEON_P2PLL_RESET
			     | RADEON_P2PLL_SLEEP
			     | RADEON_P2PLL_ATOMIC_UPDATE_EN));

	DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
		  (unsigned)p2pll_ref_div,
		  (unsigned)p2pll_div_0,
		  (unsigned)htotal_cntl2,
		  RADEON_READ_PLL(dev_priv, RADEON_P2PLL_CNTL));
	DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
		  (unsigned)p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
		  (unsigned)p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
		  (unsigned)((p2pll_div_0 &
			      RADEON_P2PLL_POST0_DIV_MASK) >>16));

	mdelay(50); /* Let the clock to lock */

	RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL,
			   RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,