/** * \file drm_os_linux.h * OS abstraction macros. */ #include /* For task queue support */ #include /** Current process ID */ #define DRM_CURRENTPID current->pid #define DRM_SUSER(p) capable(CAP_SYS_ADMIN) #define DRM_UDELAY(d) udelay(d) #if LINUX_VERSION_CODE <= 0x020608 /* KERNEL_VERSION(2,6,8) */ #ifndef __iomem #define __iomem #endif /** Read a byte from a MMIO region */ #define DRM_READ8(map, offset) readb(((void __iomem *)(map)->handle) + (offset)) /** Read a word from a MMIO region */ #define DRM_READ16(map, offset) readw(((void __iomem *)(map)->handle) + (offset)) /** Read a dword from a MMIO region */ #define DRM_READ32(map, offset) readl(((void __iomem *)(map)->handle) + (offset)) /** Write a byte into a MMIO region */ #define DRM_WRITE8(map, offset, val) writeb(val, ((void __iomem *)(map)->handle) + (offset)) /** Write a word into a MMIO region */ #define DRM_WRITE16(map, offset, val) writew(val, ((void __iomem *)(map)->handle) + (offset)) /** Write a dword into a MMIO region */ #define DRM_WRITE32(map, offset, val) writel(val, ((void __iomem *)(map)->handle) + (offset)) #else /** Read a byte from a MMIO region */ #define DRM_READ8(map, offset) readb((map)->handle + (offset)) /** Read a word from a MMIO region */ #define DRM_READ16(map, offset) readw((map)->handle + (offset)) /** Read a dword from a MMIO region */ #define DRM_READ32(map, offset) readl((map)->handle + (offset)) /** Write a byte into a MMIO region */ #define DRM_WRITE8(map, offset, val) writeb(val, (map)->handle + (offset)) /** Write a word into a MMIO region */ #define DRM_WRITE16(map, offset, val) writew(val, (map)->handle + (offset)) /** Write a dword into a MMIO region */ #define DRM_WRITE32(map, offset, val) writel(val, (map)->handle + (offset)) #endif /** Read memory barrier */ #define DRM_READMEMORYBARRIER() rmb() /** Write memory barrier */ #define DRM_WRITEMEMORYBARRIER() wmb() /** Read/write memory barrier */ #define DRM_MEMORYBARRIER() mb() /** IRQ handler arguments and return type and values */ #define DRM_IRQ_ARGS int irq, void *arg /** backwards compatibility with old irq return values */ #ifndef IRQ_HANDLED typedef void irqreturn_t; #define IRQ_HANDLED /* nothing */ #define IRQ_NONE /* nothing */ #endif /** AGP types */ #if __OS_HAS_AGP #define DRM_AGP_MEM struct agp_memory #define DRM_AGP_KERN struct agp_kern_info #else /* define some dummy types for non AGP supporting kernels */ struct no_agp_kern { unsigned long aper_base; unsigned long aper_size; }; #define DRM_AGP_MEM int #define DRM_AGP_KERN struct no_agp_kern #endif #if !(__OS_HAS_MTRR) static __inline__ int mtrr_add(unsigned long base, unsigned long size, unsigned int type, char increment) { return -ENODEV; } static __inline__ int mtrr_del(int reg, unsigned long base, unsigned long size) { return -ENODEV; } #define MTRR_TYPE_WRCOMB 1 #endif /** Other copying of data to kernel space */ #define DRM_COPY_FROM_USER(arg1, arg2, arg3) \ copy_from_user(arg1, arg2, arg3) /** Other copying of data from kernel space */ #define DRM_COPY_TO_USER(arg1, arg2, arg3) \ copy_to_user(arg1, arg2, arg3) /* Macros for copyfrom user, but checking readability only once */ #define DRM_VERIFYAREA_READ( uaddr, size ) \ (access_ok( VERIFY_READ, uaddr, size) ? 0 : -EFAULT) #define DRM_COPY_FROM_USER_UNCHECKED(arg1, arg2, arg3) \ __copy_from_user(arg1, arg2, arg3) #define DRM_COPY_TO_USER_UNCHECKED(arg1, arg2, arg3) \ __copy_to_user(arg1, arg2, arg3) #define DRM_GET_USER_UNCHECKED(val, uaddr) \ __get_user(val, uaddr) #define DRM_HZ HZ #define DRM_WAIT_ON( ret, queue, timeout, condition ) \ do { \ DECLARE_WAITQUEUE(entry, current); \ unsigned long end = jiffies + (timeout); \ add_wait_queue(&(queue), &entry); \ \ for (;;) { \ __set_current_state(TASK_INTERRUPTIBLE); \ if (condition) \ break; \ if (time_after_eq(jiffies, end)) { \ ret = -EBUSY; \ break; \ } \ schedule_timeout((HZ/100 > 1) ? HZ/100 : 1); \ if (signal_pending(current)) { \ ret = -EINTR; \ break; \ } \ } \ __set_current_state(TASK_RUNNING); \ remove_wait_queue(&(queue), &entry); \ } while (0) #define DRM_WAKEUP( queue ) wake_up_interruptible( queue ) #define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue ) /** Type for the OS's non-sleepable mutex lock */ #define DRM_SPINTYPE spinlock_t /** * Initialize the lock for use. name is an optional string describing the * lock */ #define DRM_SPININIT(l,name) spin_lock_init(l) #define DRM_SPINUNINIT(l) #define DRM_SPINLOCK(l) spin_lock(l) #define DRM_SPINUNLOCK(l) spin_unlock(l) #define DRM_SPINLOCK_IRQSAVE(l, _flags) spin_lock_irqsave(l, _flags); #define DRM_SPINUNLOCK_IRQRESTORE(l, _flags) spin_unlock_irqrestore(l, _flags); #define DRM_SPINLOCK_ASSERT(l) do {} while (0) >61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 
/*
 * Copyright 2005 Stephane Marchesin
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include "drmP.h"
#include "drm.h"
#include "drm_sarea.h"
#include "nouveau_drv.h"
#include "nouveau_drm.h"

static int nouveau_init_card_mappings(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int ret;

	/* resource 0 is mmio regs */
	/* resource 1 is linear FB */
	/* resource 2 is RAMIN (mmio regs + 0x1000000) */
	/* resource 6 is bios */

	/* map the mmio regs */
	ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
			      drm_get_resource_len(dev, 0),
			      _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
	if (ret) {
		DRM_ERROR("Unable to initialize the mmio mapping (%d). "
			  "Please report your setup to " DRIVER_EMAIL "\n",
			  ret);
		return -EINVAL;
	}
	DRM_DEBUG("regs mapped ok at 0x%lx\n", dev_priv->mmio->offset);

	/* map larger RAMIN aperture on NV40 cards */
	dev_priv->ramin = NULL;
	if (dev_priv->card_type >= NV_40) {
		int ramin_resource = 2;
		if (drm_get_resource_len(dev, ramin_resource) == 0)
			ramin_resource = 3;

		ret = drm_addmap(dev,
				 drm_get_resource_start(dev, ramin_resource),
				 drm_get_resource_len(dev, ramin_resource),
				 _DRM_REGISTERS, _DRM_READ_ONLY,
				 &dev_priv->ramin);
		if (ret) {
			DRM_ERROR("Failed to init RAMIN mapping, "
				  "limited instance memory available\n");
			dev_priv->ramin = NULL;
		}
	}

	/* On older cards (or if the above failed), create a map covering
	 * the BAR0 PRAMIN aperture */
	if (!dev_priv->ramin) {
		ret = drm_addmap(dev,
				 drm_get_resource_start(dev, 0) + NV_RAMIN,
				 (1*1024*1024),
				 _DRM_REGISTERS, _DRM_READ_ONLY,
				 &dev_priv->ramin);
		if (ret) {
			DRM_ERROR("Failed to map BAR0 PRAMIN: %d\n", ret);
			return ret;
		}
	}

	return 0;
}

static int nouveau_stub_init(struct drm_device *dev) { return 0; }
static void nouveau_stub_takedown(struct drm_device *dev) {}

static int nouveau_init_engine_ptrs(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->Engine;

	switch (dev_priv->chipset & 0xf0) {
	case 0x00:
		engine->instmem.init	= nv04_instmem_init;
		engine->instmem.takedown= nv04_instmem_takedown;
		engine->instmem.populate	= nv04_instmem_populate;
		engine->instmem.clear		= nv04_instmem_clear;
		engine->instmem.bind		= nv04_instmem_bind;
		engine->instmem.unbind		= nv04_instmem_unbind;
		engine->mc.init		= nv04_mc_init;
		engine->mc.takedown	= nv04_mc_takedown;
		engine->timer.init	= nv04_timer_init;
		engine->timer.read	= nv04_timer_read;
		engine->timer.takedown	= nv04_timer_takedown;
		engine->fb.init		= nv04_fb_init;
		engine->fb.takedown	= nv04_fb_takedown;
		engine->graph.init	= nv04_graph_init;
		engine->graph.takedown	= nv04_graph_takedown;
		engine->graph.create_context	= nv04_graph_create_context;
		engine->graph.destroy_context	= nv04_graph_destroy_context;
		engine->graph.load_context	= nv04_graph_load_context;
		engine->graph.save_context	= nv04_graph_save_context;
		engine->fifo.channels	= 16;
		engine->fifo.init	= nouveau_fifo_init;
		engine->fifo.takedown	= nouveau_stub_takedown;
		engine->fifo.channel_id		= nv04_fifo_channel_id;
		engine->fifo.create_context	= nv04_fifo_create_context;
		engine->fifo.destroy_context	= nv04_fifo_destroy_context;
		engine->fifo.load_context	= nv04_fifo_load_context;
		engine->fifo.save_context	= nv04_fifo_save_context;
		break;
	case 0x10:
		engine->instmem.init	= nv04_instmem_init;
		engine->instmem.takedown= nv04_instmem_takedown;
		engine->instmem.populate	= nv04_instmem_populate;
		engine->instmem.clear		= nv04_instmem_clear;
		engine->instmem.bind		= nv04_instmem_bind;
		engine->instmem.unbind		= nv04_instmem_unbind;
		engine->mc.init		= nv04_mc_init;
		engine->mc.takedown	= nv04_mc_takedown;
		engine->timer.init	= nv04_timer_init;
		engine->timer.read	= nv04_timer_read;
		engine->timer.takedown	= nv04_timer_takedown;
		engine->fb.init		= nv10_fb_init;
		engine->fb.takedown	= nv10_fb_takedown;
		engine->graph.init	= nv10_graph_init;
		engine->graph.takedown	= nv10_graph_takedown;
		engine->graph.create_context	= nv10_graph_create_context;
		engine->graph.destroy_context	= nv10_graph_destroy_context;
		engine->graph.load_context	= nv10_graph_load_context;
		engine->graph.save_context	= nv10_graph_save_context;
		engine->fifo.channels	= 32;
		engine->fifo.init	= nouveau_fifo_init;
		engine->fifo.takedown	= nouveau_stub_takedown;
		engine->fifo.channel_id		= nv10_fifo_channel_id;
		engine->fifo.create_context	= nv10_fifo_create_context;
		engine->fifo.destroy_context	= nv10_fifo_destroy_context;
		engine->fifo.load_context	= nv10_fifo_load_context;
		engine->fifo.save_context	= nv10_fifo_save_context;
		break;
	case 0x20:
		engine->instmem.init	= nv04_instmem_init;
		engine->instmem.takedown= nv04_instmem_takedown;
		engine->instmem.populate	= nv04_instmem_populate;
		engine->instmem.clear		= nv04_instmem_clear;
		engine->instmem.bind		= nv04_instmem_bind;
		engine->instmem.unbind		= nv04_instmem_unbind;
		engine->mc.init		= nv04_mc_init;
		engine->mc.takedown	= nv04_mc_takedown;
		engine->timer.init	= nv04_timer_init;
		engine->timer.read	= nv04_timer_read;
		engine->timer.takedown	= nv04_timer_takedown;
		engine->fb.init		= nv10_fb_init;
		engine->fb.takedown	= nv10_fb_takedown;
		engine->graph.init	= nv20_graph_init;
		engine->graph.takedown	= nv20_graph_takedown;
		engine->graph.create_context	= nv20_graph_create_context;
		engine->graph.destroy_context	= nv20_graph_destroy_context;
		engine->graph.load_context	= nv20_graph_load_context;
		engine->graph.save_context	= nv20_graph_save_context;
		engine->fifo.channels	= 32;
		engine->fifo.init	= nouveau_fifo_init;
		engine->fifo.takedown	= nouveau_stub_takedown;
		engine->fifo.channel_id		= nv10_fifo_channel_id;
		engine->fifo.create_context	= nv10_fifo_create_context;
		engine->fifo.destroy_context	= nv10_fifo_destroy_context;
		engine->fifo.load_context	= nv10_fifo_load_context;
		engine->fifo.save_context	= nv10_fifo_save_context;
		break;
	case 0x30:
		engine->instmem.init	= nv04_instmem_init;
		engine->instmem.takedown= nv04_instmem_takedown;
		engine->instmem.populate	= nv04_instmem_populate;
		engine->instmem.clear		= nv04_instmem_clear;
		engine->instmem.bind		= nv04_instmem_bind;
		engine->instmem.unbind		= nv04_instmem_unbind;
		engine->mc.init		= nv04_mc_init;
		engine->mc.takedown	= nv04_mc_takedown;
		engine->timer.init	= nv04_timer_init;
		engine->timer.read	= nv04_timer_read;
		engine->timer.takedown	= nv04_timer_takedown;
		engine->fb.init		= nv10_fb_init;
		engine->fb.takedown	= nv10_fb_takedown;
		engine->graph.init	= nv30_graph_init;
		engine->graph.takedown	= nv20_graph_takedown;
		engine->graph.create_context	= nv20_graph_create_context;
		engine->graph.destroy_context	= nv20_graph_destroy_context;
		engine->graph.load_context	= nv20_graph_load_context;
		engine->graph.save_context	= nv20_graph_save_context;
		engine->fifo.channels	= 32;
		engine->fifo.init	= nouveau_fifo_init;
		engine->fifo.takedown	= nouveau_stub_takedown;
		engine->fifo.channel_id		= nv10_fifo_channel_id;
		engine->fifo.create_context	= nv10_fifo_create_context;
		engine->fifo.destroy_context	= nv10_fifo_destroy_context;
		engine->fifo.load_context	= nv10_fifo_load_context;
		engine->fifo.save_context	= nv10_fifo_save_context;
		break;
	case 0x40:
	case 0x60:
		engine->instmem.init	= nv04_instmem_init;
		engine->instmem.takedown= nv04_instmem_takedown;
		engine->instmem.populate	= nv04_instmem_populate;
		engine->instmem.clear		= nv04_instmem_clear;
		engine->instmem.bind		= nv04_instmem_bind;
		engine->instmem.unbind		= nv04_instmem_unbind;
		engine->mc.init		= nv40_mc_init;
		engine->mc.takedown	= nv40_mc_takedown;
		engine->timer.init	= nv04_timer_init;
		engine->timer.read	= nv04_timer_read;
		engine->timer.takedown	= nv04_timer_takedown;
		engine->fb.init		= nv40_fb_init;
		engine->fb.takedown	= nv40_fb_takedown;
		engine->graph.init	= nv40_graph_init;
		engine->graph.takedown	= nv40_graph_takedown;
		engine->graph.create_context	= nv40_graph_create_context;
		engine->graph.destroy_context	= nv40_graph_destroy_context;
		engine->graph.load_context	= nv40_graph_load_context;
		engine->graph.save_context	= nv40_graph_save_context;
		engine->fifo.channels	= 32;
		engine->fifo.init	= nv40_fifo_init;
		engine->fifo.takedown	= nouveau_stub_takedown;
		engine->fifo.channel_id		= nv10_fifo_channel_id;
		engine->fifo.create_context	= nv40_fifo_create_context;
		engine->fifo.destroy_context	= nv40_fifo_destroy_context;
		engine->fifo.load_context	= nv40_fifo_load_context;
		engine->fifo.save_context	= nv40_fifo_save_context;
		break;
	case 0x50:
	case 0x80: /* gotta love NVIDIA's consistency.. */
	case 0x90:
		engine->instmem.init	= nv50_instmem_init;
		engine->instmem.takedown= nv50_instmem_takedown;
		engine->instmem.populate	= nv50_instmem_populate;
		engine->instmem.clear		= nv50_instmem_clear;
		engine->instmem.bind		= nv50_instmem_bind;
		engine->instmem.unbind		= nv50_instmem_unbind;
		engine->mc.init		= nv50_mc_init;
		engine->mc.takedown	= nv50_mc_takedown;
		engine->timer.init	= nv04_timer_init;
		engine->timer.read	= nv04_timer_read;
		engine->timer.takedown	= nv04_timer_takedown;
		engine->fb.init		= nouveau_stub_init;
		engine->fb.takedown	= nouveau_stub_takedown;
		engine->graph.init	= nv50_graph_init;
		engine->graph.takedown	= nv50_graph_takedown;
		engine->graph.create_context	= nv50_graph_create_context;
		engine->graph.destroy_context	= nv50_graph_destroy_context;
		engine->graph.load_context	= nv50_graph_load_context;
		engine->graph.save_context	= nv50_graph_save_context;
		engine->fifo.channels	= 128;
		engine->fifo.init	= nv50_fifo_init;
		engine->fifo.takedown	= nv50_fifo_takedown;
		engine->fifo.channel_id		= nv50_fifo_channel_id;
		engine->fifo.create_context	= nv50_fifo_create_context;
		engine->fifo.destroy_context	= nv50_fifo_destroy_context;
		engine->fifo.load_context	= nv50_fifo_load_context;
		engine->fifo.save_context	= nv50_fifo_save_context;
		break;
	default:
		DRM_ERROR("NV%02x unsupported\n", dev_priv->chipset);
		return 1;
	}

	return 0;
}

int
nouveau_card_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine;
	int ret;

	DRM_DEBUG("prev state = %d\n", dev_priv->init_state);

	if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
		return 0;
	dev_priv->ttm = 0;

	/* Determine exact chipset we're running on */
	if (dev_priv->card_type < NV_10)
		dev_priv->chipset = dev_priv->card_type;
	else
		dev_priv->chipset =
			(NV_READ(NV03_PMC_BOOT_0) & 0x0ff00000) >> 20;

	/* Initialise internal driver API hooks */
	ret = nouveau_init_engine_ptrs(dev);
	if (ret) return ret;
	engine = &dev_priv->Engine;
	dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;

	ret = nouveau_gpuobj_early_init(dev);
	if (ret) return ret;

	/* Initialise instance memory, must happen before mem_init so we
	 * know exactly how much VRAM we're able to use for "normal"
	 * purposes.
	 */
	ret = engine->instmem.init(dev);
	if (ret) return ret;

	/* Setup the memory manager */
	if (dev_priv->ttm) {
		ret = nouveau_mem_init_ttm(dev);
		if (ret) return ret;
	} else {
		ret = nouveau_mem_init(dev);
		if (ret) return ret;
	}

	ret = nouveau_gpuobj_init(dev);
	if (ret) return ret;

	/* Parse BIOS tables / Run init tables? */

	/* PMC */
	ret = engine->mc.init(dev);
	if (ret) return ret;

	/* PTIMER */
	ret = engine->timer.init(dev);
	if (ret) return ret;

	/* PFB */
	ret = engine->fb.init(dev);
	if (ret) return ret;

	/* PGRAPH */
	ret = engine->graph.init(dev);
	if (ret) return ret;

	/* PFIFO */
	ret = engine->fifo.init(dev);
	if (ret) return ret;

	/* this call irq_preinstall, register irq handler and
	 * call irq_postinstall
	 */
	ret = drm_irq_install(dev);
	if (ret) return ret;

	/* what about PVIDEO/PCRTC/PRAMDAC etc? */

	ret = nouveau_dma_channel_init(dev);
	if (ret) return ret;

	dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
	return 0;
}

static void nouveau_card_takedown(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->Engine;

	DRM_DEBUG("prev state = %d\n", dev_priv->init_state);

	if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
		nouveau_dma_channel_takedown(dev);

		engine->fifo.takedown(dev);
		engine->graph.takedown(dev);
		engine->fb.takedown(dev);
		engine->timer.takedown(dev);
		engine->mc.takedown(dev);

		nouveau_sgdma_nottm_hack_takedown(dev);
		nouveau_sgdma_takedown(dev);

		nouveau_gpuobj_takedown(dev);
		nouveau_gpuobj_del(dev, &dev_priv->vm_vram_pt);

		nouveau_mem_close(dev);
		engine->instmem.takedown(dev);

		drm_irq_uninstall(dev);

		nouveau_gpuobj_late_takedown(dev);

		dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
	}
}

/* here a client dies, release the stuff that was allocated for its
 * file_priv */
void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	nouveau_fifo_cleanup(dev, file_priv);
	nouveau_mem_release(file_priv,dev_priv->fb_heap);
	nouveau_mem_release(file_priv,dev_priv->agp_heap);
	nouveau_mem_release(file_priv,dev_priv->pci_heap);
}

/* first module load, setup the mmio/fb mapping */
int nouveau_firstopen(struct drm_device *dev)
{
#if defined(__powerpc__)
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct device_node *dn;
#endif
	int ret;
	/* Map any PCI resources we need on the card */
	ret = nouveau_init_card_mappings(dev);
	if (ret) return ret;

#if defined(__powerpc__)
	/* Put the card in BE mode if it's not */
	if (NV_READ(NV03_PMC_BOOT_1))
		NV_WRITE(NV03_PMC_BOOT_1,0x00000001);

	DRM_MEMORYBARRIER();
#endif

#if defined(__linux__) && defined(__powerpc__)
	/* if we have an OF card, copy vbios to RAMIN */
	dn = pci_device_to_OF_node(dev->pdev);
	if (dn)
	{
		int size;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22))
		const uint32_t *bios = of_get_property(dn, "NVDA,BMP", &size);
#else
		const uint32_t *bios = get_property(dn, "NVDA,BMP", &size);
#endif
		if (bios)
		{
			int i;
			for(i=0;i<size;i+=4)
				NV_WI32(i, bios[i/4]);
			DRM_INFO("OF bios successfully copied (%d bytes)\n",size);
		}
		else
			DRM_INFO("Unable to get the OF bios\n");
	}
	else
		DRM_INFO("Unable to get the OF node\n");
#endif
	return 0;
}

#define NV40_CHIPSET_MASK 0x00000baf
#define NV44_CHIPSET_MASK 0x00005450

int nouveau_load(struct drm_device *dev, unsigned long flags)
{
	struct drm_nouveau_private *dev_priv;
	void __iomem *regs;
	uint32_t reg0,reg1;
	uint8_t architecture = 0;

	dev_priv = drm_calloc(1, sizeof(*dev_priv), DRM_MEM_DRIVER);
	if (!dev_priv)
		return -ENOMEM;

	dev_priv->flags = flags & NOUVEAU_FLAGS;
	dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;

	DRM_DEBUG("vendor: 0x%X device: 0x%X class: 0x%X\n", dev->pci_vendor, dev->pci_device, dev->pdev->class);

	/* Time to determine the card architecture */
	regs = ioremap_nocache(pci_resource_start(dev->pdev, 0), 0x8);
	if (!regs) {
		DRM_ERROR("Could not ioremap to determine register\n");
		return -ENOMEM;
	}

	reg0 = readl(regs+NV03_PMC_BOOT_0);
	reg1 = readl(regs+NV03_PMC_BOOT_1);
#if defined(__powerpc__)
	if (reg1)
		reg0=___swab32(reg0);
#endif

	/* We're dealing with >=NV10 */
	if ((reg0 & 0x0f000000) > 0 ) {
		/* Bit 27-20 contain the architecture in hex */
		architecture = (reg0 & 0xff00000) >> 20;
	/* NV04 or NV05 */
	} else if ((reg0 & 0xff00fff0) == 0x20004000) {
		architecture = 0x04;
	}

	iounmap(regs);

	if (architecture >= 0x80) {
		dev_priv->card_type = NV_50;
	} else if (architecture >= 0x60) {
		/* FIXME we need to figure out who's who for NV6x */
		dev_priv->card_type = NV_44;
	} else if (architecture >= 0x50) {
		dev_priv->card_type = NV_50;
	} else if (architecture >= 0x40) {
		uint8_t subarch = architecture & 0xf;
		/* Selection criteria borrowed from NV40EXA */
		if (NV40_CHIPSET_MASK & (1 << subarch)) {
			dev_priv->card_type = NV_40;
		} else if (NV44_CHIPSET_MASK & (1 << subarch)) {
			dev_priv->card_type = NV_44;
		} else {
			dev_priv->card_type = NV_UNKNOWN;
		}
	} else if (architecture >= 0x30) {
		dev_priv->card_type = NV_30;
	} else if (architecture >= 0x20) {
		dev_priv->card_type = NV_20;
	} else if (architecture >= 0x17) {
		dev_priv->card_type = NV_17;
	} else if (architecture >= 0x11) {
		dev_priv->card_type = NV_11;
	} else if (architecture >= 0x10) {
		dev_priv->card_type = NV_10;
	} else if (architecture >= 0x04) {
		dev_priv->card_type = NV_04;
	} else {
		dev_priv->card_type = NV_UNKNOWN;
	}

	DRM_INFO("Detected an NV%d generation card (0x%08x)\n", dev_priv->card_type,reg0);

	if (dev_priv->card_type == NV_UNKNOWN) {
		return -EINVAL;
	}

	/* Special flags */
	if (dev->pci_device == 0x01a0) {
		dev_priv->flags |= NV_NFORCE;
	} else if (dev->pci_device == 0x01f0) {
		dev_priv->flags |= NV_NFORCE2;
	}

	dev->dev_private = (void *)dev_priv;

	return 0;
}

void nouveau_lastclose(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	/* In the case of an error dev_priv may not be be allocated yet */
	if (dev_priv && dev_priv->card_type) {
		nouveau_card_takedown(dev);

		if(dev_priv->fb_mtrr>0)
		{