From 1728bc637df023cce7b5abfeab2796ea481ca7e9 Mon Sep 17 00:00:00 2001 From: Keith Whitwell Date: Fri, 28 Mar 2003 14:27:37 +0000 Subject: merged drm-filp-0-1-branch --- shared/radeon_drv.h | 93 ++++++++++++++--------------------------------------- 1 file changed, 24 insertions(+), 69 deletions(-) (limited to 'shared/radeon_drv.h') diff --git a/shared/radeon_drv.h b/shared/radeon_drv.h index 635ad14b..7faffa7a 100644 --- a/shared/radeon_drv.h +++ b/shared/radeon_drv.h @@ -31,8 +31,8 @@ #ifndef __RADEON_DRV_H__ #define __RADEON_DRV_H__ -#define GET_RING_HEAD(ring) DRM_READ32( (volatile u32 *) (ring)->head ) -#define SET_RING_HEAD(ring,val) DRM_WRITE32( (volatile u32 *) (ring)->head , (val)) +#define GET_RING_HEAD(ring) DRM_READ32( (ring)->ring_rptr, 0 ) /* (ring)->head */ +#define SET_RING_HEAD(ring,val) DRM_WRITE32( (ring)->ring_rptr, 0, (val) ) /* (ring)->head */ typedef struct drm_radeon_freelist { unsigned int age; @@ -53,6 +53,7 @@ typedef struct drm_radeon_ring_buffer { int space; int high_mark; + drm_local_map_t *ring_rptr; } drm_radeon_ring_buffer_t; typedef struct drm_radeon_depth_clear_t { @@ -67,7 +68,7 @@ struct mem_block { struct mem_block *prev; int start; int size; - int pid; /* 0: free, -1: heap, other: real pids */ + DRMFILE filp; /* 0: free, -1: heap, other: real files */ }; typedef struct drm_radeon_private { @@ -126,13 +127,13 @@ typedef struct drm_radeon_private { drm_radeon_depth_clear_t depth_clear; - drm_map_t *sarea; - drm_map_t *fb; - drm_map_t *mmio; - drm_map_t *cp_ring; - drm_map_t *ring_rptr; - drm_map_t *buffers; - drm_map_t *agp_textures; + drm_local_map_t *sarea; + drm_local_map_t *fb; + drm_local_map_t *mmio; + drm_local_map_t *cp_ring; + drm_local_map_t *ring_rptr; + drm_local_map_t *buffers; + drm_local_map_t *agp_textures; struct mem_block *agp_heap; struct mem_block *fb_heap; @@ -183,7 +184,7 @@ extern int radeon_mem_alloc( DRM_IOCTL_ARGS ); extern int radeon_mem_free( DRM_IOCTL_ARGS ); extern int radeon_mem_init_heap( DRM_IOCTL_ARGS ); extern void radeon_mem_takedown( struct mem_block **heap ); -extern void radeon_mem_release( struct mem_block *heap ); +extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap ); /* radeon_irq.c */ extern int radeon_irq_emit( DRM_IOCTL_ARGS ); @@ -193,6 +194,7 @@ extern int radeon_emit_and_wait_irq(drm_device_t *dev); extern int radeon_wait_irq(drm_device_t *dev, int swi_nr); extern int radeon_emit_irq(drm_device_t *dev); +extern void radeon_do_release(drm_device_t *dev); /* Flags for stats.boxes */ @@ -266,8 +268,10 @@ extern int radeon_emit_irq(drm_device_t *dev); #define RADEON_SCRATCH_UMSK 0x0770 #define RADEON_SCRATCH_ADDR 0x0774 +#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) + #define GET_SCRATCH( x ) (dev_priv->writeback_works \ - ? DRM_READ32( &dev_priv->scratch[(x)] ) \ + ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) @@ -686,15 +690,10 @@ extern int radeon_emit_irq(drm_device_t *dev); #define RADEON_RING_HIGH_MARK 128 - -#define RADEON_BASE(reg) ((unsigned long)(dev_priv->mmio->handle)) -#define RADEON_ADDR(reg) (RADEON_BASE( reg ) + reg) - -#define RADEON_READ(reg) DRM_READ32( (volatile u32 *) RADEON_ADDR(reg) ) -#define RADEON_WRITE(reg,val) DRM_WRITE32( (volatile u32 *) RADEON_ADDR(reg), (val) ) - -#define RADEON_READ8(reg) DRM_READ8( (volatile u8 *) RADEON_ADDR(reg) ) -#define RADEON_WRITE8(reg,val) DRM_WRITE8( (volatile u8 *) RADEON_ADDR(reg), (val) ) +#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) +#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) +#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) +#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) #define RADEON_WRITE_PLL( addr, val ) \ do { \ @@ -771,16 +770,6 @@ extern int RADEON_READ_PLL( drm_device_t *dev, int addr ); * Misc helper macros */ -#define LOCK_TEST_WITH_RETURN( dev ) \ -do { \ - if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \ - dev->lock.pid != DRM_CURRENTPID ) { \ - DRM_ERROR( "%s called without lock held\n", __FUNCTION__ ); \ - return DRM_ERR(EINVAL); \ - } \ -} while (0) - - /* Perfbox functionality only. */ #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ @@ -827,43 +816,10 @@ do { \ #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; -#if defined(__alpha__) -# define RADEON_PAD_RING 16 /* pad ring requests to 16 lw boundaries */ -#else -# define RADEON_PAD_RING 0 -#endif - -#if RADEON_PAD_RING -# define radeon_pad_size(n) \ - (((RADEON_PAD_RING) - ((n) % (RADEON_PAD_RING))) % (RADEON_PAD_RING)) -# define radeon_pad_ring() do { \ - if (RADEON_VERBOSE) { \ - DRM_INFO("Padding ring from %d (%x) with %d words\n", \ - write, write, radeon_pad_size(write)); \ - } \ - switch (radeon_pad_size(write)) { \ - case 0: /* aligned */ \ - break; \ - case 1: /* 1 word */ \ - OUT_RING(CP_PACKET2()); \ - break; \ - default: /* >= 2 words */ \ - OUT_RING(CP_PACKET3(0x1000, radeon_pad_size(write) - 1));\ - write = (write + radeon_pad_size(write)) & mask; \ - write &= mask; \ - break; \ - } \ -} while(0) -#else -# define radeon_pad_size(n) 0 -# define radeon_pad_ring() -#endif - -#define BEGIN_RING( req_n ) do { \ - int n = req_n + radeon_pad_size(req_n); \ +#define BEGIN_RING( n ) do { \ if ( RADEON_VERBOSE ) { \ - DRM_INFO( "BEGIN_RING( %d (%d) ) in %s\n", \ - n, req_n, __FUNCTION__ ); \ + DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ + n, __FUNCTION__ ); \ } \ if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ COMMIT_RING(); \ @@ -880,7 +836,6 @@ do { \ DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ write, dev_priv->ring.tail ); \ } \ - radeon_pad_ring(); \ if (((dev_priv->ring.tail + _nr) & mask) != write) { \ DRM_ERROR( \ "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ @@ -892,7 +847,7 @@ do { \ #define COMMIT_RING() do { \ /* Flush writes to ring */ \ - DRM_READMEMORYBARRIER(); \ + DRM_READMEMORYBARRIER(dev_priv->mmio); \ GET_RING_HEAD( &dev_priv->ring ); \ RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ /* read from PCI bus to ensure correct posting */ \ -- cgit v1.2.3