From 6bfb9b639ab2ab71969eeeb72105ce7e0c487462 Mon Sep 17 00:00:00 2001 From: George Sapountzis Date: Fri, 25 Jan 2008 16:54:29 +0200 Subject: mach64: fix after vblank-rework don't disable vblank interrupts (similar to r128) --- shared-core/mach64_irq.c | 45 +++++++++++++++++++++++++++++++-------------- 1 file changed, 31 insertions(+), 14 deletions(-) (limited to 'shared-core') diff --git a/shared-core/mach64_irq.c b/shared-core/mach64_irq.c index 2d522a6c..57879e8d 100644 --- a/shared-core/mach64_irq.c +++ b/shared-core/mach64_irq.c @@ -71,11 +71,10 @@ irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS) u32 mach64_get_vblank_counter(struct drm_device * dev, int crtc) { const drm_mach64_private_t *const dev_priv = dev->dev_private; - - if (crtc != 0) { + + if (crtc != 0) return 0; - } - + return atomic_read(&dev_priv->vbl_received); } @@ -83,14 +82,15 @@ int mach64_enable_vblank(struct drm_device * dev, int crtc) { drm_mach64_private_t *dev_priv = dev->dev_private; u32 status = MACH64_READ(MACH64_CRTC_INT_CNTL); - + if (crtc != 0) { - DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", crtc); - return 0; + DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", + crtc); + return -EINVAL; } - + DRM_DEBUG("before enable vblank CRTC_INT_CTNL: 0x%08x\n", status); - + /* Turn on VBLANK interrupt */ MACH64_WRITE(MACH64_CRTC_INT_CNTL, MACH64_READ(MACH64_CRTC_INT_CNTL) | MACH64_CRTC_VBLANK_INT_EN); @@ -98,12 +98,31 @@ int mach64_enable_vblank(struct drm_device * dev, int crtc) return 0; } - void mach64_disable_vblank(struct drm_device * dev, int crtc) +{ + if (crtc != 0) { + DRM_ERROR("tried to disable vblank on non-existent crtc %d\n", + crtc); + return; + } + + /* + * FIXME: implement proper interrupt disable by using the vblank + * counter register (if available). + */ +} + +static void mach64_disable_vblank_local(struct drm_device * dev, int crtc) { drm_mach64_private_t *dev_priv = dev->dev_private; u32 status = MACH64_READ(MACH64_CRTC_INT_CNTL); + if (crtc != 0) { + DRM_ERROR("tried to disable vblank on non-existent crtc %d\n", + crtc); + return; + } + DRM_DEBUG("before disable vblank CRTC_INT_CTNL: 0x%08x\n", status); /* Disable and clear VBLANK interrupt */ @@ -111,8 +130,6 @@ void mach64_disable_vblank(struct drm_device * dev, int crtc) | MACH64_CRTC_VBLANK_INT); } -/* drm_dma.h hooks -*/ void mach64_driver_irq_preinstall(struct drm_device * dev) { drm_mach64_private_t *dev_priv = dev->dev_private; @@ -121,7 +138,7 @@ void mach64_driver_irq_preinstall(struct drm_device * dev) DRM_DEBUG("before install CRTC_INT_CTNL: 0x%08x\n", status); - mach64_disable_vblank(dev,0); + mach64_disable_vblank_local(dev, 0); } int mach64_driver_irq_postinstall(struct drm_device * dev) @@ -135,7 +152,7 @@ void mach64_driver_irq_uninstall(struct drm_device * dev) if (!dev_priv) return; - mach64_disable_vblank(dev, 0); + mach64_disable_vblank_local(dev, 0); DRM_DEBUG("after uninstall CRTC_INT_CTNL: 0x%08x\n", MACH64_READ(MACH64_CRTC_INT_CNTL)); -- cgit v1.2.3 From b8755ff7c33baac2abe5b5fe00897b33a896a098 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sun, 27 Jan 2008 12:50:31 +1000 Subject: drm: add initial rs690 support for drm. This adds support for configuring the RS690 GART. --- shared-core/drm_pciids.txt | 1 + shared-core/radeon_cp.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++ shared-core/radeon_drv.h | 42 ++++++++++++++++++++-- 3 files changed, 127 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index b14b5241..b2bf8eab 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -232,6 +232,7 @@ 0x1002 0x7297 CHIP_RV560|RADEON_NEW_MEMMAP "ATI RV560" 0x1002 0x7834 CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP "ATI Radeon RS350 9000/9100 IGP" 0x1002 0x7835 CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon RS350 Mobility IGP" +0x1002 0x791e CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART "ATI Radeon RS690 X1250 IGP" [r128] 0x1002 0x4c45 0 "ATI Rage 128 Mobility LE (PCI)" diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 3eb81efc..ac46da38 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -825,11 +825,19 @@ static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) return ret; } +static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) +{ + RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); + return RADEON_READ(RS690_MC_DATA); +} + u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) { if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); + else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) + return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); else @@ -840,6 +848,8 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) { if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); + else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) + RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); else @@ -850,6 +860,8 @@ static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_lo { if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); + else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) + RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); else @@ -1362,6 +1374,74 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) } } +/* Enable or disable RS690 GART on the chip */ +static void radeon_set_rs690gart(drm_radeon_private_t * dev_priv, int on) +{ + u32 temp; + + if (on) { + DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n", + dev_priv->gart_vm_start, + (long)dev_priv->gart_info.bus_addr, + dev_priv->gart_size); + + temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL); + RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000); + + RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, + RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); + + temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID); + RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800); + + RS690_WRITE_MCIND(RS690_MC_GART_BASE, + dev_priv->gart_info.bus_addr); + + temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL); + RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000); + + RS690_WRITE_MCIND(RS690_MC_AGP_BASE, + (unsigned int)dev_priv->gart_vm_start); + + dev_priv->gart_size = 32*1024*1024; + temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & + 0xffff0000) | (dev_priv->gart_vm_start >> 16)); + + RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp); + + temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE); + RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, + RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); + + do + { + temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); + if ((temp & RS690_MC_GART_CLEAR_STATUS) == + RS690_MC_GART_CLEAR_DONE) + break; + DRM_UDELAY(1); + } while(1); + + RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, + RS690_MC_GART_CC_CLEAR); + do + { + temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); + if ((temp & RS690_MC_GART_CLEAR_STATUS) == + RS690_MC_GART_CLEAR_DONE) + break; + DRM_UDELAY(1); + } while(1); + + RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, + RS690_MC_GART_CC_NO_CHANGE); + } + else + { + RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS); + } +} + static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) { u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); @@ -1396,6 +1476,12 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) { u32 tmp; + if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) + { + radeon_set_rs690gart(dev_priv, on); + return; + } + if (dev_priv->flags & RADEON_IS_IGPGART) { radeon_set_igpgart(dev_priv, on); return; diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index bd51de14..1cf03415 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -124,6 +124,7 @@ enum radeon_family { CHIP_R420, CHIP_RV410, CHIP_RS400, + CHIP_RS690, CHIP_RV515, CHIP_R520, CHIP_RV530, @@ -471,6 +472,36 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, #define RADEON_IGPGART_ENABLE 0x38 #define RADEON_IGPGART_UNK_39 0x39 +#define RS690_MC_INDEX 0x78 +# define RS690_MC_INDEX_MASK 0x1ff +# define RS690_MC_INDEX_WR_EN (1 << 9) +# define RS690_MC_INDEX_WR_ACK 0x7f +#define RS690_MC_DATA 0x7c + +#define RS690_MC_MISC_CNTL 0x18 +#define RS690_MC_GART_FEATURE_ID 0x2b +#define RS690_MC_GART_BASE 0x2c +#define RS690_MC_GART_CACHE_CNTL 0x2e +# define RS690_MC_GART_CC_NO_CHANGE 0x0 +# define RS690_MC_GART_CC_CLEAR 0x1 +# define RS690_MC_GART_CLEAR_STATUS (1 << 1) +# define RS690_MC_GART_CLEAR_DONE (0 << 1) +# define RS690_MC_GART_CLEAR_PENDING (1 << 1) +#define RS690_MC_AGP_SIZE 0x38 +# define RS690_MC_GART_DIS 0x0 +# define RS690_MC_GART_EN 0x1 +# define RS690_MC_AGP_SIZE_32MB (0 << 1) +# define RS690_MC_AGP_SIZE_64MB (1 << 1) +# define RS690_MC_AGP_SIZE_128MB (2 << 1) +# define RS690_MC_AGP_SIZE_256MB (3 << 1) +# define RS690_MC_AGP_SIZE_512MB (4 << 1) +# define RS690_MC_AGP_SIZE_1GB (5 << 1) +# define RS690_MC_AGP_SIZE_2GB (6 << 1) +#define RS690_MC_AGP_MODE_CONTROL 0x39 +#define RS690_MC_FB_LOCATION 0x100 +#define RS690_MC_AGP_LOCATION 0x101 +#define RS690_MC_AGP_BASE 0x102 + #define R520_MC_IND_INDEX 0x70 #define R520_MC_IND_WR_EN (1<<24) #define R520_MC_IND_DATA 0x74 @@ -1082,8 +1113,8 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, #define RADEON_PCIGART_TABLE_SIZE (32*1024) -#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) -#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) +#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) +#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) @@ -1116,6 +1147,13 @@ do { \ RADEON_WRITE(R520_MC_IND_INDEX, 0); \ } while (0) +#define RS690_WRITE_MCIND( addr, val ) \ +do { \ + RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ + RADEON_WRITE(RS690_MC_DATA, val); \ + RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ +} while (0) + #define CP_PACKET0( reg, n ) \ (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) #define CP_PACKET0_TABLE( reg, n ) \ -- cgit v1.2.3 From 0744cb153aabd290fd4832288a530adeb5561e2c Mon Sep 17 00:00:00 2001 From: Mirko Date: Tue, 29 Jan 2008 10:11:27 -0500 Subject: Add new RV380 pci id bug 14289 --- shared-core/drm_pciids.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'shared-core') diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index b2bf8eab..63b5cd50 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -79,6 +79,7 @@ 0x1002 0x5460 CHIP_RV380|RADEON_IS_MOBILITY "ATI Radeon Mobility X300 M22" 0x1002 0x5462 CHIP_RV380|RADEON_IS_MOBILITY "ATI Radeon Mobility X600 SE M24C" 0x1002 0x5464 CHIP_RV380|RADEON_IS_MOBILITY "ATI FireGL M22 GL 5464" +0x1002 0x5657 CHIP_RV380|RADEON_NEW_MEMMAP "ATI Radeon RV370 X550XTX" 0x1002 0x5548 CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R423 X800" 0x1002 0x5549 CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R423 X800 Pro" 0x1002 0x554A CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R423 X800 XT PE" -- cgit v1.2.3 From 9a7e45858d8faa7afbe31b130d2de1be781085da Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 30 Jan 2008 11:40:13 +1100 Subject: nv40: some more nv67 changes With some luck the drm-side will be OK now for this chipset. --- shared-core/nouveau_fifo.c | 1 - shared-core/nouveau_state.c | 1 + shared-core/nv40_graph.c | 4 +++- 3 files changed, 4 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index d00f1938..0daf9ac4 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -64,7 +64,6 @@ static int nouveau_fifo_instmem_configure(struct drm_device *dev) switch(dev_priv->card_type) { - case NV_50: case NV_40: switch (dev_priv->chipset) { case 0x47: diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 7086a0ab..12162167 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -212,6 +212,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) engine->fifo.save_context = nv10_fifo_save_context; break; case 0x40: + case 0x60: engine->instmem.init = nv04_instmem_init; engine->instmem.takedown= nv04_instmem_takedown; engine->instmem.populate = nv04_instmem_populate; diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index fdf51519..6ef02bf9 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -1511,6 +1511,7 @@ nv40_graph_create_context(struct nouveau_channel *chan) ctx_init = nv4b_graph_context_init; break; case 0x4c: + case 0x67: ctx_size = NV4C_GRCTX_SIZE; ctx_init = nv4c_graph_context_init; break; @@ -2007,7 +2008,8 @@ nv40_graph_init(struct drm_device *dev) case 0x49: ctx_voodoo = nv49_4b_ctx_voodoo; break; case 0x4a: ctx_voodoo = nv4a_ctx_voodoo; break; case 0x4b: ctx_voodoo = nv49_4b_ctx_voodoo; break; - case 0x4c: ctx_voodoo = nv4c_ctx_voodoo; break; + case 0x4c: + case 0x67: ctx_voodoo = nv4c_ctx_voodoo; break; case 0x4e: ctx_voodoo = nv4e_ctx_voodoo; break; default: DRM_ERROR("Unknown ctx_voodoo for chipset 0x%02x\n", -- cgit v1.2.3 From f1edb7ad91d8b92057ffa02eb162e3740d05a147 Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Wed, 30 Jan 2008 22:06:02 +0100 Subject: Simplify the fencing code and differentiate between flushes and waiting types. Add a "command_stream_barrier" method to the bo driver. --- shared-core/i915_dma.c | 5 ++++- shared-core/i915_drv.h | 12 ++++-------- shared-core/via_drv.c | 14 ++++---------- shared-core/via_drv.h | 11 ----------- shared-core/via_map.c | 3 --- 5 files changed, 12 insertions(+), 33 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 287e95ac..15fb8117 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -422,6 +422,9 @@ void i915_emit_breadcrumb(struct drm_device *dev) RING_LOCALS; if (++dev_priv->counter > BREADCRUMB_MASK) { +#ifdef I915_HAVE_FENCE + i915_invalidate_reported_sequence(dev); +#endif dev_priv->counter = 1; DRM_DEBUG("Breadcrumb counter wrapped around\n"); } @@ -1113,7 +1116,7 @@ static int i915_execbuffer(struct drm_device *dev, void *data, fence_arg->handle = fence->base.hash.key; fence_arg->fence_class = fence->fence_class; fence_arg->type = fence->type; - fence_arg->signaled = fence->signaled; + fence_arg->signaled = fence->signaled_types; } } drm_fence_usage_deref_unlocked(&fence); diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index c92758fa..3f6c8066 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -136,6 +136,8 @@ typedef struct drm_i915_private { uint32_t flush_flags; uint32_t flush_pending; uint32_t saved_flush_status; + uint32_t reported_sequence; + int reported_sequence_valid; #endif #ifdef I915_HAVE_BUFFER void *agp_iomap; @@ -290,15 +292,9 @@ extern void i915_mem_release(struct drm_device * dev, struct mem_block *heap); #ifdef I915_HAVE_FENCE /* i915_fence.c */ - - extern void i915_fence_handler(struct drm_device *dev); -extern int i915_fence_emit_sequence(struct drm_device *dev, uint32_t class, - uint32_t flags, - uint32_t *sequence, - uint32_t *native_type); -extern void i915_poke_flush(struct drm_device *dev, uint32_t class); -extern int i915_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t flags); +extern void i915_invalidate_reported_sequence(struct drm_device *dev); + #endif #ifdef I915_HAVE_BUFFER diff --git a/shared-core/via_drv.c b/shared-core/via_drv.c index a802e4ae..dd632c3d 100644 --- a/shared-core/via_drv.c +++ b/shared-core/via_drv.c @@ -40,17 +40,9 @@ static struct pci_device_id pciidlist[] = { #ifdef VIA_HAVE_FENCE -static struct drm_fence_driver via_fence_driver = { - .num_classes = 1, - .wrap_diff = (1 << 30), - .flush_diff = (1 << 20), - .sequence_mask = 0xffffffffU, - .lazy_capable = 1, - .emit = via_fence_emit_sequence, - .poke_flush = via_poke_flush, - .has_irq = via_fence_has_irq, -}; +extern struct drm_fence_driver via_fence_driver; #endif + #ifdef VIA_HAVE_BUFFER /** @@ -76,6 +68,8 @@ static struct drm_bo_driver via_bo_driver = { .init_mem_type = via_init_mem_type, .evict_flags = via_evict_flags, .move = NULL, + .ttm_cache_flush = NULL, + .command_stream_barrier = NULL }; #endif diff --git a/shared-core/via_drv.h b/shared-core/via_drv.h index 8dd4a727..941a2d77 100644 --- a/shared-core/via_drv.h +++ b/shared-core/via_drv.h @@ -196,17 +196,6 @@ extern void via_dmablit_handler(struct drm_device *dev, int engine, int from_irq extern void via_init_dmablit(struct drm_device *dev); #endif -#ifdef VIA_HAVE_FENCE -extern void via_fence_timer(unsigned long data); -extern void via_poke_flush(struct drm_device * dev, uint32_t class); -extern int via_fence_emit_sequence(struct drm_device * dev, uint32_t class, - uint32_t flags, - uint32_t * sequence, - uint32_t * native_type); -extern int via_fence_has_irq(struct drm_device * dev, uint32_t class, - uint32_t flags); -#endif - #ifdef VIA_HAVE_BUFFER extern struct drm_ttm_backend *via_create_ttm_backend_entry(struct drm_device *dev); extern int via_fence_types(struct drm_buffer_object *bo, uint32_t *fclass, diff --git a/shared-core/via_map.c b/shared-core/via_map.c index 11bfa551..54934367 100644 --- a/shared-core/via_map.c +++ b/shared-core/via_map.c @@ -69,9 +69,6 @@ static int via_do_init_map(struct drm_device * dev, drm_via_init_t * init) dev_priv->emit_0_sequence = 0; dev_priv->have_idlelock = 0; spin_lock_init(&dev_priv->fence_lock); - init_timer(&dev_priv->fence_timer); - dev_priv->fence_timer.function = &via_fence_timer; - dev_priv->fence_timer.data = (unsigned long) dev; #endif /* VIA_HAVE_FENCE */ dev->dev_private = (void *)dev_priv; #ifdef VIA_HAVE_BUFFER -- cgit v1.2.3 From 47ee6237fe86a8621744bbd6cecb8b5e58848b05 Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Wed, 30 Jan 2008 22:14:02 +0100 Subject: i915: Avoid calling drm_fence_flush_old excessively. --- shared-core/i915_dma.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 15fb8117..a012f68e 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -494,7 +494,8 @@ static int i915_dispatch_cmdbuffer(struct drm_device * dev, i915_emit_breadcrumb(dev); #ifdef I915_HAVE_FENCE - drm_fence_flush_old(dev, 0, dev_priv->counter); + if (unlikely((dev_priv->counter & 0xFF) == 0)) + drm_fence_flush_old(dev, 0, dev_priv->counter); #endif return 0; } @@ -548,7 +549,8 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev, i915_emit_breadcrumb(dev); #ifdef I915_HAVE_FENCE - drm_fence_flush_old(dev, 0, dev_priv->counter); + if (unlikely((dev_priv->counter & 0xFF) == 0)) + drm_fence_flush_old(dev, 0, dev_priv->counter); #endif return 0; } @@ -621,7 +623,7 @@ void i915_dispatch_flip(struct drm_device * dev, int planes, int sync) i915_emit_breadcrumb(dev); #ifdef I915_HAVE_FENCE - if (!sync) + if (unlikely(!sync && ((dev_priv->counter & 0xFF) == 0))) drm_fence_flush_old(dev, 0, dev_priv->counter); #endif } -- cgit v1.2.3 From 733e07663e50087ca1e9af8e9b5def556521e3b5 Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Sat, 2 Feb 2008 12:46:31 +0100 Subject: nouveau: NV40 can/should now be able to run after the blob. - Moved the fix from the ddx to drm, because it seemed more appropriate. - Don't be shy, report if it works for you or not. --- shared-core/nouveau_reg.h | 1 + shared-core/nv40_fb.c | 7 +++++++ 2 files changed, 8 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index a2506146..283977b3 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -138,6 +138,7 @@ #define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16)) #define NV40_PFB_TSIZE(i) (0x00100608 + (i*16)) #define NV40_PFB_TSTATUS(i) (0x0010060C + (i*16)) +#define NV40_PFB_UNK_800 0x00100800 #define NV04_PGRAPH_DEBUG_0 0x00400080 #define NV04_PGRAPH_DEBUG_1 0x00400084 diff --git a/shared-core/nv40_fb.c b/shared-core/nv40_fb.c index ceae8079..ae784cb8 100644 --- a/shared-core/nv40_fb.c +++ b/shared-core/nv40_fb.c @@ -11,6 +11,13 @@ nv40_fb_init(struct drm_device *dev) int num_tiles; int i; + /* This is strictly a NV4x register (don't know about NV5x). */ + /* The blob sets these to all kinds of values, and they mess up our setup. */ + /* I got value 0x52802 instead. For some cards the blob even sets it back to 0x1. */ + /* Note: the blob doesn't read this value, so i'm pretty sure this is safe for all cards. */ + /* Any idea what this is? */ + NV_WRITE(NV40_PFB_UNK_800, 0x1); + switch (dev_priv->chipset) { case 0x40: case 0x45: -- cgit v1.2.3 From a0781e762295ce3d5f6e839d437a0de505cefa3b Mon Sep 17 00:00:00 2001 From: Stuart Bennett Date: Mon, 28 Jan 2008 22:59:26 +0000 Subject: nouveau: make nv34 work every time, not just every 2nd time And make nv30_graph_init a bit more like mmio-traces --- shared-core/nv20_graph.c | 45 ++++++++++++++++++++++++++++++++------------- 1 file changed, 32 insertions(+), 13 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 37a147b5..ad73ea91 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -804,7 +804,7 @@ void nv20_graph_takedown(struct drm_device *dev) int nv30_graph_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t vramsz, tmp; +// uint32_t vramsz, tmp; int ret, i; NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & @@ -834,6 +834,7 @@ int nv30_graph_init(struct drm_device *dev) NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000); NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); NV_WRITE(0x400B80, 0x1003d888); + NV_WRITE(0x400B84, 0x0c000000); NV_WRITE(0x400098, 0x00000000); NV_WRITE(0x40009C, 0x0005ad00); NV_WRITE(0x400B88, 0x62ff00ff); // suspiciously like PGRAPH_DEBUG_2 @@ -843,30 +844,47 @@ int nv30_graph_init(struct drm_device *dev) NV_WRITE(0x400ba0, 0x002f8685); NV_WRITE(0x400ba4, 0x00231f3f); NV_WRITE(0x4008a4, 0x40000020); - NV_WRITE(0x400B84, 0x0c000000); - NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x62ff0f7f); + + if (dev_priv->chipset == 0x34) { + NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0004); + NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00200201); + NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0008); + NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000008); + NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0000); + NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000032); + NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00004); + NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000002); + } + NV_WRITE(0x4000c0, 0x00000016); /* copy tile info from PFB */ - for (i=0; ichipset != 0x34) { + NV_WRITE(0x400750, 0x00EA0000); + NV_WRITE(0x400754, NV_READ(NV04_PFB_CFG0)); + NV_WRITE(0x400750, 0x00EA0004); + NV_WRITE(0x400754, NV_READ(NV04_PFB_CFG1)); + } + +#if 0 NV_WRITE(0x400820, 0); NV_WRITE(0x400824, 0); NV_WRITE(0x400864, vramsz-1); @@ -885,6 +903,7 @@ int nv30_graph_init(struct drm_device *dev) NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0); NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); +#endif return 0; } -- cgit v1.2.3 From 76748efae2f51409813eeb6b91b783c73cb2845e Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Tue, 5 Feb 2008 10:35:56 +0100 Subject: i915: Re-report breadcrumbs on poll to the fence manager, since a breadcrumb may actually turn up before a corresponding fence object has been placed on the fence ring. --- shared-core/i915_dma.c | 3 --- shared-core/i915_drv.h | 2 -- 2 files changed, 5 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index a012f68e..608723f4 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -422,9 +422,6 @@ void i915_emit_breadcrumb(struct drm_device *dev) RING_LOCALS; if (++dev_priv->counter > BREADCRUMB_MASK) { -#ifdef I915_HAVE_FENCE - i915_invalidate_reported_sequence(dev); -#endif dev_priv->counter = 1; DRM_DEBUG("Breadcrumb counter wrapped around\n"); } diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 3f6c8066..87594670 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -136,8 +136,6 @@ typedef struct drm_i915_private { uint32_t flush_flags; uint32_t flush_pending; uint32_t saved_flush_status; - uint32_t reported_sequence; - int reported_sequence_valid; #endif #ifdef I915_HAVE_BUFFER void *agp_iomap; -- cgit v1.2.3 From 8b6c96dedd4ba5dfbfec6a7c831d566e31d28781 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Thu, 7 Feb 2008 10:48:08 -0800 Subject: i915: save/restore interrupt state On resume, if the interrupt state isn't restored correctly, we may end up with a flood of unexpected or ill-timed interrupts, which could cause the kernel to disable the interrupt or vblank events to happen at the wrong time. So save/restore them properly. --- shared-core/i915_drv.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'shared-core') diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 87594670..d2faee29 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -166,6 +166,7 @@ typedef struct drm_i915_private { u32 saveVBLANK_A; u32 saveVSYNC_A; u32 saveBCLRPAT_A; + u32 savePIPEASTAT; u32 saveDSPASTRIDE; u32 saveDSPASIZE; u32 saveDSPAPOS; @@ -186,6 +187,7 @@ typedef struct drm_i915_private { u32 saveVBLANK_B; u32 saveVSYNC_B; u32 saveBCLRPAT_B; + u32 savePIPEBSTAT; u32 saveDSPBSTRIDE; u32 saveDSPBSIZE; u32 saveDSPBPOS; @@ -214,6 +216,9 @@ typedef struct drm_i915_private { u32 saveFBC_LL_BASE; u32 saveFBC_CONTROL; u32 saveFBC_CONTROL2; + u32 saveIER; + u32 saveIIR; + u32 saveIMR; u32 saveSWF0[16]; u32 saveSWF1[16]; u32 saveSWF2[3]; -- cgit v1.2.3 From 6f19473191ae543fcc199d252c5865c0734d38ad Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Thu, 7 Feb 2008 11:21:09 -0800 Subject: Fix saveGR array size Make sure we have enough room for all the GR registers or we'll end up clobbering the AR index register (which should actually be harmless unless the BIOS is making an assumption about it). --- shared-core/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index d2faee29..d08fdf40 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -224,7 +224,7 @@ typedef struct drm_i915_private { u32 saveSWF2[3]; u8 saveMSR; u8 saveSR[8]; - u8 saveGR[24]; + u8 saveGR[25]; u8 saveAR_INDEX; u8 saveAR[20]; u8 saveDACMASK; -- cgit v1.2.3 From 4feb0638f1a8eb8527647ff47312ee61e3f683f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kristian=20H=C3=B8gsberg?= Date: Tue, 5 Feb 2008 12:25:22 -0500 Subject: i915: Make sarea_priv setup optional. --- shared-core/i915_dma.c | 20 +++++++++++++++----- shared-core/i915_irq.c | 10 +++++++--- 2 files changed, 22 insertions(+), 8 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 608723f4..9619525d 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -128,8 +128,14 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS; #endif - dev_priv->sarea_priv = (drm_i915_sarea_t *) - ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset); + if (init->sarea_priv_offset) + dev_priv->sarea_priv = (drm_i915_sarea_t *) + ((u8 *) dev_priv->sarea->handle + + init->sarea_priv_offset); + else { + /* No sarea_priv for you! */ + dev_priv->sarea_priv = NULL; + } dev_priv->ring.Start = init->ring_start; dev_priv->ring.End = init->ring_end; @@ -154,7 +160,9 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) dev_priv->ring.virtual_start = dev_priv->ring.map.handle; dev_priv->cpp = init->cpp; - dev_priv->sarea_priv->pf_current_page = 0; + + if (dev_priv->sarea_priv) + dev_priv->sarea_priv->pf_current_page = 0; /* We are using separate values as placeholders for mechanisms for * private backbuffer/depthbuffer usage. @@ -426,7 +434,8 @@ void i915_emit_breadcrumb(struct drm_device *dev) DRM_DEBUG("Breadcrumb counter wrapped around\n"); } - dev_priv->sarea_priv->last_enqueue = dev_priv->counter; + if (dev_priv->sarea_priv) + dev_priv->sarea_priv->last_enqueue = dev_priv->counter; BEGIN_LP_RING(4); OUT_RING(CMD_STORE_DWORD_IDX); @@ -1101,7 +1110,8 @@ static int i915_execbuffer(struct drm_device *dev, void *data, if (ret) goto out_err0; - sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); + if (sarea_priv) + sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); /* fence */ ret = drm_fence_buffer_objects(dev, NULL, fence_arg->flags, diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c index d463f6e6..fd08b6e8 100644 --- a/shared-core/i915_irq.c +++ b/shared-core/i915_irq.c @@ -450,7 +450,9 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) temp &= (dev_priv->irq_enable_reg | USER_INT_FLAG | VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG); - dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); + if (dev_priv->sarea_priv) + dev_priv->sarea_priv->last_dispatch = + READ_BREADCRUMB(dev_priv); if (temp & USER_INT_FLAG) { DRM_WAKEUP(&dev_priv->irq_queue); @@ -529,7 +531,9 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr) READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); } - dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); + if (dev_priv->sarea_priv) + dev_priv->sarea_priv->last_dispatch = + READ_BREADCRUMB(dev_priv); return ret; } @@ -693,7 +697,7 @@ int i915_vblank_swap(struct drm_device *dev, void *data, return -EINVAL; } - if (dev_priv->sarea_priv->rotation) { + if (!dev_priv->sarea_priv || dev_priv->sarea_priv->rotation) { DRM_DEBUG("Rotation not supported\n"); return -EINVAL; } -- cgit v1.2.3 From ee15459483d50b2efe630051b45f36cfbb351683 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kristian=20H=C3=B8gsberg?= Date: Tue, 5 Feb 2008 12:27:48 -0500 Subject: i915: Add I915_PARAM_CHIPSET_ID param to get chipset ID. --- shared-core/i915_dma.c | 3 +++ shared-core/i915_drm.h | 1 + 2 files changed, 4 insertions(+) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 9619525d..0682a334 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -1210,6 +1210,9 @@ static int i915_getparam(struct drm_device *dev, void *data, case I915_PARAM_LAST_DISPATCH: value = READ_BREADCRUMB(dev_priv); break; + case I915_PARAM_CHIPSET_ID: + value = dev->pci_device; + break; default: DRM_ERROR("Unknown parameter %d\n", param->param); return -EINVAL; diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h index c8a9cb76..ad0797c2 100644 --- a/shared-core/i915_drm.h +++ b/shared-core/i915_drm.h @@ -232,6 +232,7 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_IRQ_ACTIVE 1 #define I915_PARAM_ALLOW_BATCHBUFFER 2 #define I915_PARAM_LAST_DISPATCH 3 +#define I915_PARAM_CHIPSET_ID 4 typedef struct drm_i915_getparam { int param; -- cgit v1.2.3 From db3f03ae3538bea3d29ef66ac24d9a1f54cff418 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kristian=20H=C3=B8gsberg?= Date: Tue, 12 Feb 2008 16:08:18 -0500 Subject: i915: Only look up dev_priv->mmio_map if it's not already set up --- shared-core/i915_dma.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 0682a334..fc009204 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -117,7 +117,8 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) return -EINVAL; } - dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); + if (init->mmio_offset != 0) + dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); if (!dev_priv->mmio_map) { i915_dma_cleanup(dev); DRM_ERROR("can not find mmio map!\n"); -- cgit v1.2.3 From 373dbcf8b25750967e9ba24433cff872df41cb74 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kristian=20H=C3=B8gsberg?= Date: Tue, 5 Feb 2008 13:27:16 -0500 Subject: i915: Add a dri2 init path that gets the lock from the dri2 sarea. --- shared-core/i915_dma.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++-- shared-core/i915_drm.h | 8 ++++- shared-core/i915_drv.h | 4 +++ 3 files changed, 103 insertions(+), 3 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index fc009204..3874ed58 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -106,9 +106,73 @@ static int i915_dma_cleanup(struct drm_device * dev) return 0; } -static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) + +#define DRI2_SAREA_BLOCK_TYPE(b) ((b) >> 16) +#define DRI2_SAREA_BLOCK_SIZE(b) ((b) & 0xffff) +#define DRI2_SAREA_BLOCK_NEXT(p) \ + ((void *) ((unsigned char *) (p) + \ + DRI2_SAREA_BLOCK_SIZE(*(unsigned int *) p))) + +#define DRI2_SAREA_BLOCK_END 0x0000 +#define DRI2_SAREA_BLOCK_LOCK 0x0001 +#define DRI2_SAREA_BLOCK_EVENT_BUFFER 0x0002 + +static int +setup_dri2_sarea(struct drm_device * dev, + struct drm_file *file_priv, + drm_i915_init_t * init) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + int ret; + unsigned int *p, *end, *next; + + mutex_lock(&dev->struct_mutex); + dev_priv->sarea_bo = + drm_lookup_buffer_object(file_priv, + init->sarea_handle, 1); + mutex_unlock(&dev->struct_mutex); + + if (!dev_priv->sarea_bo) { + DRM_ERROR("did not find sarea bo\n"); + return -EINVAL; + } + + ret = drm_bo_kmap(dev_priv->sarea_bo, 0, + dev_priv->sarea_bo->num_pages, + &dev_priv->sarea_kmap); + if (ret) { + DRM_ERROR("could not map sarea bo\n"); + return ret; + } + + p = dev_priv->sarea_kmap.virtual; + end = (void *) p + (dev_priv->sarea_bo->num_pages << PAGE_SHIFT); + while (p < end && DRI2_SAREA_BLOCK_TYPE(*p) != DRI2_SAREA_BLOCK_END) { + switch (DRI2_SAREA_BLOCK_TYPE(*p)) { + case DRI2_SAREA_BLOCK_LOCK: + dev->lock.hw_lock = (void *) (p + 1); + dev->sigdata.lock = dev->lock.hw_lock; + break; + } + next = DRI2_SAREA_BLOCK_NEXT(p); + if (next <= p || end < next) { + DRM_ERROR("malformed dri2 sarea: next is %p should be within %p-%p\n", + next, p, end); + return -EINVAL; + } + p = next; + } + + return 0; +} + + +static int i915_initialize(struct drm_device * dev, + struct drm_file *file_priv, + drm_i915_init_t * init) { drm_i915_private_t *dev_priv = dev->dev_private; + int ret; dev_priv->sarea = drm_getsarea(dev); if (!dev_priv->sarea) { @@ -201,6 +265,17 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) #ifdef I915_HAVE_BUFFER mutex_init(&dev_priv->cmdbuf_mutex); #endif + + if (init->func == I915_INIT_DMA2) { + ret = setup_dri2_sarea(dev, file_priv, init); + if (ret) { + i915_dma_cleanup(dev); + DRM_ERROR("could not set up dri2 sarea\n"); + return ret; + } + } + + return 0; } @@ -250,7 +325,8 @@ static int i915_dma_init(struct drm_device *dev, void *data, switch (init->func) { case I915_INIT_DMA: - retcode = i915_initialize(dev, init); + case I915_INIT_DMA2: + retcode = i915_initialize(dev, file_priv, init); break; case I915_CLEANUP_DMA: retcode = i915_dma_cleanup(dev); @@ -1415,6 +1491,20 @@ void i915_driver_lastclose(struct drm_device * dev) if (dev_priv->agp_heap) i915_mem_takedown(&(dev_priv->agp_heap)); + if (dev_priv->sarea_kmap.virtual) { + drm_bo_kunmap(&dev_priv->sarea_kmap); + dev_priv->sarea_kmap.virtual = NULL; + dev->lock.hw_lock = NULL; + dev->sigdata.lock = NULL; + } + + if (dev_priv->sarea_bo) { + mutex_lock(&dev->struct_mutex); + drm_bo_usage_deref_locked(&dev_priv->sarea_bo); + mutex_unlock(&dev->struct_mutex); + dev_priv->sarea_bo = NULL; + } + i915_dma_cleanup(dev); } diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h index ad0797c2..b889a303 100644 --- a/shared-core/i915_drm.h +++ b/shared-core/i915_drm.h @@ -43,7 +43,12 @@ typedef struct _drm_i915_init { enum { I915_INIT_DMA = 0x01, I915_CLEANUP_DMA = 0x02, - I915_RESUME_DMA = 0x03 + I915_RESUME_DMA = 0x03, + + /* Since this struct isn't versioned, just used a new + * 'func' code to indicate the presence of dri2 sarea + * info. */ + I915_INIT_DMA2 = 0x04 } func; unsigned int mmio_offset; int sarea_priv_offset; @@ -61,6 +66,7 @@ typedef struct _drm_i915_init { unsigned int depth_pitch; unsigned int cpp; unsigned int chipset; + unsigned int sarea_handle; } drm_i915_init_t; typedef struct _drm_i915_sarea { diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index d08fdf40..76116df5 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -147,6 +147,10 @@ typedef struct drm_i915_private { drm_i915_vbl_swap_t vbl_swaps; unsigned int swaps_pending; + /* DRI2 sarea */ + struct drm_buffer_object *sarea_bo; + struct drm_bo_kmap_obj sarea_kmap; + /* Register state */ u8 saveLBB; u32 saveDSPACNTR; -- cgit v1.2.3 From 15cbde683f5006b541b22c41ff840aefb017ff8e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 16 Feb 2008 04:33:27 +1100 Subject: nv40: actually init all tile regs. --- shared-core/nouveau_reg.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 283977b3..2f7d77cf 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -335,19 +335,19 @@ #define NV04_PGRAPH_BLEND 0x00400824 #define NV04_PGRAPH_STORED_FMT 0x00400830 #define NV04_PGRAPH_PATT_COLORRAM 0x00400900 -#define NV40_PGRAPH_TILE0(i) 0x00400900 -#define NV40_PGRAPH_TLIMIT0(i) 0x00400904 -#define NV40_PGRAPH_TSIZE0(i) 0x00400908 -#define NV40_PGRAPH_TSTATUS0(i) 0x0040090C +#define NV40_PGRAPH_TILE0(i) (0x00400900 + (i*16)) +#define NV40_PGRAPH_TLIMIT0(i) (0x00400904 + (i*16)) +#define NV40_PGRAPH_TSIZE0(i) (0x00400908 + (i*16)) +#define NV40_PGRAPH_TSTATUS0(i) (0x0040090C + (i*16)) #define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16)) #define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16)) #define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16)) #define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16)) #define NV04_PGRAPH_U_RAM 0x00400D00 -#define NV47_PGRAPH_TILE0(i) 0x00400D00 -#define NV47_PGRAPH_TLIMIT0(i) 0x00400D04 -#define NV47_PGRAPH_TSIZE0(i) 0x00400D08 -#define NV47_PGRAPH_TSTATUS0(i) 0x00400D0C +#define NV47_PGRAPH_TILE0(i) (0x00400D00 + (i*16)) +#define NV47_PGRAPH_TLIMIT0(i) (0x00400D04 + (i*16)) +#define NV47_PGRAPH_TSIZE0(i) (0x00400D08 + (i*16)) +#define NV47_PGRAPH_TSTATUS0(i) (0x00400D0C + (i*16)) #define NV04_PGRAPH_V_RAM 0x00400D40 #define NV04_PGRAPH_W_RAM 0x00400D80 #define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40 @@ -395,10 +395,10 @@ #define NV04_PGRAPH_DMA_B_OFFSET 0x00401098 #define NV04_PGRAPH_DMA_B_SIZE 0x0040109C #define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0 -#define NV40_PGRAPH_TILE1(i) 0x00406900 -#define NV40_PGRAPH_TLIMIT1(i) 0x00406904 -#define NV40_PGRAPH_TSIZE1(i) 0x00406908 -#define NV40_PGRAPH_TSTATUS1(i) 0x0040690C +#define NV40_PGRAPH_TILE1(i) (0x00406900 + (i*16)) +#define NV40_PGRAPH_TLIMIT1(i) (0x00406904 + (i*16)) +#define NV40_PGRAPH_TSIZE1(i) (0x00406908 + (i*16)) +#define NV40_PGRAPH_TSTATUS1(i) (0x0040690C + (i*16)) /* It's a guess that this works on NV03. Confirmed on NV04, though */ -- cgit v1.2.3 From cd87e6352bf529ae0bc57e8434ddfccec3660d9a Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Sat, 16 Feb 2008 03:50:10 +0100 Subject: nouveau: no GART on ia64 either. --- shared-core/nouveau_mem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index f4e641b9..3d376aed 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -393,7 +393,7 @@ nouveau_mem_init_ttm(struct drm_device *dev) } /* GART */ -#ifndef __powerpc__ +#if !defined(__powerpc__) && !defined(__ia64__) if (drm_device_is_agp(dev) && dev->agp) { if ((ret = nouveau_mem_init_agp(dev, 1))) DRM_ERROR("Error initialising AGP: %d\n", ret); @@ -462,7 +462,7 @@ int nouveau_mem_init(struct drm_device *dev) dev_priv->fb_nomap_heap=NULL; } -#ifndef __powerpc__ +#if !defined(__powerpc__) && !defined(__ia64__) /* Init AGP / NV50 PCIEGART */ if (drm_device_is_agp(dev) && dev->agp) { if ((ret = nouveau_mem_init_agp(dev, 0))) -- cgit v1.2.3 From 5d8c754bc2c720d70bbdeca6b294660105717a62 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Sat, 16 Feb 2008 19:19:29 -0800 Subject: [915]: more registers for S3 (DSPCLK_GATE_D, CACHE_MODE_0, MI_ARB_STATE) Failing to preserve the MI_ARB_STATE register was causing FIFO underruns on the VGA output on my HP 2510p after resume. --- shared-core/i915_drv.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'shared-core') diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 76116df5..4d3ac0a5 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -223,6 +223,9 @@ typedef struct drm_i915_private { u32 saveIER; u32 saveIIR; u32 saveIMR; + u32 saveCACHE_MODE_0; + u32 saveDSPCLK_GATE_D; + u32 saveMI_ARB_STATE; u32 saveSWF0[16]; u32 saveSWF1[16]; u32 saveSWF2[3]; @@ -576,6 +579,10 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); */ #define DMA_FADD_S 0x20d4 +/* Memory Interface Arbitration State + */ +#define MI_ARB_STATE 0x20e4 + /* Cache mode 0 reg. * - Manipulating render cache behaviour is central * to the concept of zone rendering, tuning this reg can help avoid @@ -586,6 +593,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set. */ #define Cache_Mode_0 0x2120 +#define CACHE_MODE_0 0x2120 #define CM0_MASK_SHIFT 16 #define CM0_IZ_OPT_DISABLE (1<<6) #define CM0_ZR_OPT_DISABLE (1<<5) @@ -775,6 +783,8 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); /** P1 value is 2 greater than this field */ # define VGA0_PD_P1_MASK (0x1f << 0) +#define DSPCLK_GATE_D 0x6200 + /* I830 CRTC registers */ #define HTOTAL_A 0x60000 #define HBLANK_A 0x60004 -- cgit v1.2.3