From d69902db3b1f82dd35f5bbb3327bdf836961850c Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Sat, 3 Feb 2007 05:25:36 +0100 Subject: nouveau: fix nv04 graph routines for new register names. --- shared-core/nouveau_drv.h | 2 +- shared-core/nv04_graph.c | 188 +++++++++++++++++++++++----------------------- shared-core/nv10_graph.c | 16 ++-- 3 files changed, 103 insertions(+), 103 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 41ea9a54..39fe1317 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -91,7 +91,7 @@ struct nouveau_fifo struct nouveau_object *objs; /* XXX dynamic alloc ? */ - uint32_t nv10_pgraph_ctx [340]; + uint32_t pgraph_ctx [340]; }; struct nouveau_config { diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c index 750a7255..47fb8a1d 100644 --- a/shared-core/nv04_graph.c +++ b/shared-core/nv04_graph.c @@ -39,37 +39,37 @@ static int nv04_graph_ctx_regs [] = { NV04_PGRAPH_CTX_CACHE2, 8, NV04_PGRAPH_CTX_CACHE3, 8, NV04_PGRAPH_CTX_CACHE4, 8, - NV_PGRAPH_ABS_X_RAM, 32, - NV_PGRAPH_ABS_Y_RAM, 32, - NV_PGRAPH_X_MISC, 1, - NV_PGRAPH_Y_MISC, 1, - NV_PGRAPH_VALID1, 1, - NV_PGRAPH_SOURCE_COLOR, 1, - NV_PGRAPH_MISC24_0, 1, - NV_PGRAPH_XY_LOGIC_MISC0, 1, - NV_PGRAPH_XY_LOGIC_MISC1, 1, - NV_PGRAPH_XY_LOGIC_MISC2, 1, - NV_PGRAPH_XY_LOGIC_MISC3, 1, - NV_PGRAPH_CLIPX_0, 1, - NV_PGRAPH_CLIPX_1, 1, - NV_PGRAPH_CLIPY_0, 1, - NV_PGRAPH_CLIPY_1, 1, - NV_PGRAPH_ABS_ICLIP_XMAX, 1, - NV_PGRAPH_ABS_ICLIP_YMAX, 1, - NV_PGRAPH_ABS_UCLIP_XMIN, 1, - NV_PGRAPH_ABS_UCLIP_YMIN, 1, - NV_PGRAPH_ABS_UCLIP_XMAX, 1, - NV_PGRAPH_ABS_UCLIP_YMAX, 1, - NV_PGRAPH_ABS_UCLIPA_XMIN, 1, - NV_PGRAPH_ABS_UCLIPA_YMIN, 1, - NV_PGRAPH_ABS_UCLIPA_XMAX, 1, - NV_PGRAPH_ABS_UCLIPA_YMAX, 1, - NV_PGRAPH_MISC24_1, 1, - NV_PGRAPH_MISC24_2, 1, - NV_PGRAPH_VALID2, 1, - NV_PGRAPH_PASSTHRU_0, 1, - NV_PGRAPH_PASSTHRU_1, 1, - NV_PGRAPH_PASSTHRU_2, 1, + NV03_PGRAPH_ABS_X_RAM, 32, + NV03_PGRAPH_ABS_Y_RAM, 32, + NV03_PGRAPH_X_MISC, 1, + NV03_PGRAPH_Y_MISC, 1, + NV04_PGRAPH_VALID1, 1, + NV04_PGRAPH_SOURCE_COLOR, 1, + NV04_PGRAPH_MISC24_0, 1, + NV03_PGRAPH_XY_LOGIC_MISC0, 1, + NV03_PGRAPH_XY_LOGIC_MISC1, 1, + NV03_PGRAPH_XY_LOGIC_MISC2, 1, + NV03_PGRAPH_XY_LOGIC_MISC3, 1, + NV03_PGRAPH_CLIPX_0, 1, + NV03_PGRAPH_CLIPX_1, 1, + NV03_PGRAPH_CLIPY_0, 1, + NV03_PGRAPH_CLIPY_1, 1, + NV03_PGRAPH_ABS_ICLIP_XMAX, 1, + NV03_PGRAPH_ABS_ICLIP_YMAX, 1, + NV03_PGRAPH_ABS_UCLIP_XMIN, 1, + NV03_PGRAPH_ABS_UCLIP_YMIN, 1, + NV03_PGRAPH_ABS_UCLIP_XMAX, 1, + NV03_PGRAPH_ABS_UCLIP_YMAX, 1, + NV03_PGRAPH_ABS_UCLIPA_XMIN, 1, + NV03_PGRAPH_ABS_UCLIPA_YMIN, 1, + NV03_PGRAPH_ABS_UCLIPA_XMAX, 1, + NV03_PGRAPH_ABS_UCLIPA_YMAX, 1, + NV04_PGRAPH_MISC24_1, 1, + NV04_PGRAPH_MISC24_2, 1, + NV04_PGRAPH_VALID2, 1, + NV04_PGRAPH_PASSTHRU_0, 1, + NV04_PGRAPH_PASSTHRU_1, 1, + NV04_PGRAPH_PASSTHRU_2, 1, NV04_PGRAPH_COMBINE_0_ALPHA, 1, NV04_PGRAPH_COMBINE_0_COLOR, 1, NV04_PGRAPH_COMBINE_1_ALPHA, 1, @@ -89,77 +89,77 @@ static int nv04_graph_ctx_regs [] = { 0x004005d8, 1, 0x004005dc, 1, 0x004005e0, 1, - NV_PGRAPH_MONO_COLOR0, 1, - NV_PGRAPH_ROP3, 1, - NV_PGRAPH_BETA_AND, 1, - NV_PGRAPH_BETA_PREMULT, 1, - NV_PGRAPH_FORMATS, 1, - NV_PGRAPH_BOFFSET0, 6, - NV_PGRAPH_BBASE0, 6, - NV_PGRAPH_BPITCH0, 5, - NV_PGRAPH_BLIMIT0, 6, - NV_PGRAPH_BSWIZZLE2, 1, - NV_PGRAPH_BSWIZZLE5, 1, + NV03_PGRAPH_MONO_COLOR0, 1, + NV04_PGRAPH_ROP3, 1, + NV04_PGRAPH_BETA_AND, 1, + NV04_PGRAPH_BETA_PREMULT, 1, + NV04_PGRAPH_FORMATS, 1, + NV04_PGRAPH_BOFFSET0, 6, + NV04_PGRAPH_BBASE0, 6, + NV04_PGRAPH_BPITCH0, 5, + NV04_PGRAPH_BLIMIT0, 6, + NV04_PGRAPH_BSWIZZLE2, 1, + NV04_PGRAPH_BSWIZZLE5, 1, NV04_PGRAPH_SURFACE, 1, - NV_PGRAPH_STATE, 1, - NV_PGRAPH_NOTIFY, 1, - NV_PGRAPH_BPIXEL, 1, + NV04_PGRAPH_STATE, 1, + NV04_PGRAPH_NOTIFY, 1, + NV04_PGRAPH_BPIXEL, 1, NV04_PGRAPH_DMA_PITCH, 1, NV04_PGRAPH_DVD_COLORFMT, 1, NV04_PGRAPH_SCALED_FORMAT, 1, - NV_PGRAPH_PATT_COLOR0, 1, - NV_PGRAPH_PATT_COLOR1, 1, - NV_PGRAPH_PATTERN, 2, - NV_PGRAPH_PATTERN_SHAPE, 1, - NV_PGRAPH_CHROMA, 1, + NV04_PGRAPH_PATT_COLOR0, 1, + NV04_PGRAPH_PATT_COLOR1, 1, + NV04_PGRAPH_PATTERN, 2, + NV04_PGRAPH_PATTERN_SHAPE, 1, + NV04_PGRAPH_CHROMA, 1, NV04_PGRAPH_CONTROL0, 1, NV04_PGRAPH_CONTROL1, 1, NV04_PGRAPH_CONTROL2, 1, NV04_PGRAPH_BLEND, 1, - NV_PGRAPH_STORED_FMT, 1, - NV_PGRAPH_PATT_COLORRAM, 64, + NV04_PGRAPH_STORED_FMT, 1, + NV04_PGRAPH_PATT_COLORRAM, 64, NV04_PGRAPH_U_RAM, 16, NV04_PGRAPH_V_RAM, 16, NV04_PGRAPH_W_RAM, 16, - NV_PGRAPH_DMA_START_0, 1, - NV_PGRAPH_DMA_START_1, 1, - NV_PGRAPH_DMA_LENGTH, 1, - NV_PGRAPH_DMA_MISC, 1, - NV_PGRAPH_DMA_DATA_0, 1, - NV_PGRAPH_DMA_DATA_1, 1, - NV_PGRAPH_DMA_RM, 1, - NV_PGRAPH_DMA_A_XLATE_INST, 1, - NV_PGRAPH_DMA_A_CONTROL, 1, - NV_PGRAPH_DMA_A_LIMIT, 1, - NV_PGRAPH_DMA_A_TLB_PTE, 1, - NV_PGRAPH_DMA_A_TLB_TAG, 1, - NV_PGRAPH_DMA_A_ADJ_OFFSET, 1, - NV_PGRAPH_DMA_A_OFFSET, 1, - NV_PGRAPH_DMA_A_SIZE, 1, - NV_PGRAPH_DMA_A_Y_SIZE, 1, - NV_PGRAPH_DMA_B_XLATE_INST, 1, - NV_PGRAPH_DMA_B_CONTROL, 1, - NV_PGRAPH_DMA_B_LIMIT, 1, - NV_PGRAPH_DMA_B_TLB_PTE, 1, - NV_PGRAPH_DMA_B_TLB_TAG, 1, - NV_PGRAPH_DMA_B_ADJ_OFFSET, 1, - NV_PGRAPH_DMA_B_OFFSET, 1, - NV_PGRAPH_DMA_B_SIZE, 1, - NV_PGRAPH_DMA_B_Y_SIZE, 1, + NV04_PGRAPH_DMA_START_0, 1, + NV04_PGRAPH_DMA_START_1, 1, + NV04_PGRAPH_DMA_LENGTH, 1, + NV04_PGRAPH_DMA_MISC, 1, + NV04_PGRAPH_DMA_DATA_0, 1, + NV04_PGRAPH_DMA_DATA_1, 1, + NV04_PGRAPH_DMA_RM, 1, + NV04_PGRAPH_DMA_A_XLATE_INST, 1, + NV04_PGRAPH_DMA_A_CONTROL, 1, + NV04_PGRAPH_DMA_A_LIMIT, 1, + NV04_PGRAPH_DMA_A_TLB_PTE, 1, + NV04_PGRAPH_DMA_A_TLB_TAG, 1, + NV04_PGRAPH_DMA_A_ADJ_OFFSET, 1, + NV04_PGRAPH_DMA_A_OFFSET, 1, + NV04_PGRAPH_DMA_A_SIZE, 1, + NV04_PGRAPH_DMA_A_Y_SIZE, 1, + NV04_PGRAPH_DMA_B_XLATE_INST, 1, + NV04_PGRAPH_DMA_B_CONTROL, 1, + NV04_PGRAPH_DMA_B_LIMIT, 1, + NV04_PGRAPH_DMA_B_TLB_PTE, 1, + NV04_PGRAPH_DMA_B_TLB_TAG, 1, + NV04_PGRAPH_DMA_B_ADJ_OFFSET, 1, + NV04_PGRAPH_DMA_B_OFFSET, 1, + NV04_PGRAPH_DMA_B_SIZE, 1, + NV04_PGRAPH_DMA_B_Y_SIZE, 1, 0, 0 }; void nouveau_nv04_context_switch(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; - int channel, channel_old, i, j, gpu_type; + int channel, channel_old, i; - channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); - channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); + channel_old = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel); - NV_WRITE(NV_PGRAPH_FIFO,0x0); + NV_WRITE(NV04_PGRAPH_FIFO,0x0); #if 0 NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000); @@ -168,45 +168,45 @@ void nouveau_nv04_context_switch(drm_device_t *dev) // save PGRAPH context for (i = 0; nv04_graph_ctx_regs[i]; i++) - dev_priv->fifos[channel_old].nv04_pgraph_ctx[i] = NV_READ(nv04_graph_ctx_regs[i]); + dev_priv->fifos[channel_old].pgraph_ctx[i] = NV_READ(nv04_graph_ctx_regs[i]); nouveau_wait_for_idle(dev); - NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000000); - NV_WRITE(NV_PGRAPH_CTX_USER, (NV_READ(NV_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24)); + NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10000000); + NV_WRITE(NV04_PGRAPH_CTX_USER, (NV_READ(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24)); nouveau_wait_for_idle(dev); // restore PGRAPH context //XXX not working yet #if 1 for (i = 0; nv04_graph_ctx_regs[i]; i++) - NV_WRITE(nv04_graph_ctx_regs[i], dev_priv->fifos[channel].nv04_pgraph_ctx[i]); + NV_WRITE(nv04_graph_ctx_regs[i], dev_priv->fifos[channel].pgraph_ctx[i]); nouveau_wait_for_idle(dev); #endif - - NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100); - NV_WRITE(NV_PGRAPH_CTX_USER, channel << 24); - NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); + + NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10010100); + NV_WRITE(NV04_PGRAPH_CTX_USER, channel << 24); + //NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); #if 0 NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); NV_WRITE(NV_PFIFO_CACHES, 0x00000001); #endif - NV_WRITE(NV_PGRAPH_FIFO,0x1); + NV_WRITE(NV04_PGRAPH_FIFO,0x1); } int nv04_graph_context_create(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; DRM_DEBUG("nv04_graph_context_create %d\n", channel); - memset(dev_priv->fifos[channel].nv04_pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].nv04_pgraph_ctx)); + memset(dev_priv->fifos[channel].pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].pgraph_ctx)); //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; - dev_priv->fifos[channel].nv04_pgraph_ctx[0] = 0x0001ffff; + dev_priv->fifos[channel].pgraph_ctx[0] = 0x0001ffff; /* is it really needed ??? */ - dev_priv->fifos[channel].nv04_pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4); - dev_priv->fifos[channel].nv04_pgraph_ctx[2] = NV_READ(0x004006b0); + //dev_priv->fifos[channel].pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4); + //dev_priv->fifos[channel].pgraph_ctx[2] = NV_READ(0x004006b0); return 0; } diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index fe9a6a40..ad74b840 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -546,10 +546,10 @@ void nouveau_nv10_context_switch(drm_device_t *dev) // save PGRAPH context for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) - dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); + dev_priv->fifos[channel_old].pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); if (dev_priv->chipset>=0x17) { for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) - dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); + dev_priv->fifos[channel_old].pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); } nouveau_wait_for_idle(dev); @@ -562,10 +562,10 @@ void nouveau_nv10_context_switch(drm_device_t *dev) //XXX not working yet #if 1 for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) - NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); + NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].pgraph_ctx[i]); if (dev_priv->chipset>=0x17) { for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) - NV_WRITE(nv17_graph_ctx_regs[j], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); + NV_WRITE(nv17_graph_ctx_regs[j], dev_priv->fifos[channel].pgraph_ctx[i]); } nouveau_wait_for_idle(dev); #endif @@ -586,14 +586,14 @@ int nv10_graph_context_create(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; DRM_DEBUG("nv10_graph_context_create %d\n", channel); - memset(dev_priv->fifos[channel].nv10_pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].nv10_pgraph_ctx)); + memset(dev_priv->fifos[channel].pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].pgraph_ctx)); //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; - dev_priv->fifos[channel].nv10_pgraph_ctx[0] = 0x0001ffff; + dev_priv->fifos[channel].pgraph_ctx[0] = 0x0001ffff; /* is it really needed ??? */ if (dev_priv->chipset>=0x17) { - dev_priv->fifos[channel].nv10_pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 0] = NV_READ(NV10_PGRAPH_DEBUG_4); - dev_priv->fifos[channel].nv10_pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 1] = NV_READ(0x004006b0); + dev_priv->fifos[channel].pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 0] = NV_READ(NV10_PGRAPH_DEBUG_4); + dev_priv->fifos[channel].pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 1] = NV_READ(0x004006b0); } -- cgit v1.2.3