From caace3692f3121dcc18fa5e9260ffe1a4abbb943 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 13 May 2008 21:02:17 -0400 Subject: RS4xx: separate out RS400 and RS480 IGP chips RS400 (intel based IGP) and RS480 (AMD based IGP) have different MC and GART setups. Currently we only support RS480. --- shared-core/drm_pciids.txt | 14 ++++---- shared-core/radeon_cp.c | 64 ++++++++++++++++----------------- shared-core/radeon_drv.h | 90 +++++++++++++++++++++++----------------------- 3 files changed, 83 insertions(+), 85 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index e78b8945..86408a4b 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -99,20 +99,18 @@ 0x1002 0x5653 CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon Mobility X700 M26" 0x1002 0x5834 CHIP_RS300|RADEON_IS_IGP "ATI Radeon RS300 9100 IGP" 0x1002 0x5835 CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY "ATI Radeon RS300 Mobility IGP" -0x1002 0x5954 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI RS480 XPRESS 200G" -0x1002 0x5955 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon XPRESS 200M 5955" -0x1002 0x5974 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RS482 XPRESS 200" -0x1002 0x5975 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RS485 XPRESS 1100 IGP" +0x1002 0x5954 CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI RS480 XPRESS 200G" +0x1002 0x5955 CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon XPRESS 200M 5955" +0x1002 0x5974 CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RS482 XPRESS 200" +0x1002 0x5975 CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RS485 XPRESS 1100 IGP" 0x1002 0x5960 CHIP_RV280 "ATI Radeon RV280 9250" 0x1002 0x5961 CHIP_RV280 "ATI Radeon RV280 9200" 0x1002 0x5962 CHIP_RV280 "ATI Radeon RV280 9200" 0x1002 0x5964 CHIP_RV280 "ATI Radeon RV280 9200 SE" 0x1002 0x5965 CHIP_RV280 "ATI FireMV 2200 PCI" 0x1002 0x5969 CHIP_RV100 "ATI ES1000 RN50" -0x1002 0x5a41 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RS400 XPRESS 200" -0x1002 0x5a42 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RS400 XPRESS 200M" -0x1002 0x5a61 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RC410 XPRESS 200" -0x1002 0x5a62 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RC410 XPRESS 200M" +0x1002 0x5a61 CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RC410 XPRESS 200" +0x1002 0x5a62 CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RC410 XPRESS 200M" 0x1002 0x5b60 CHIP_RV380|RADEON_NEW_MEMMAP "ATI Radeon RV370 X300 SE" 0x1002 0x5b62 CHIP_RV380|RADEON_NEW_MEMMAP "ATI Radeon RV370 X600 Pro" 0x1002 0x5b63 CHIP_RV380|RADEON_NEW_MEMMAP "ATI Radeon RV370 X550" diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index be57ec78..33c928b1 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -16111,12 +16111,12 @@ static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) return ret; } -static u32 RS400_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) +static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) { u32 ret; - RADEON_WRITE(RS400_NB_MC_INDEX, addr & 0xff); - ret = RADEON_READ(RS400_NB_MC_DATA); - RADEON_WRITE(RS400_NB_MC_INDEX, 0xff); + RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff); + ret = RADEON_READ(RS480_NB_MC_DATA); + RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); return ret; } @@ -16134,7 +16134,7 @@ static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) return RS690_READ_MCIND(dev_priv, addr); else - return RS400_READ_MCIND(dev_priv, addr); + return RS480_READ_MCIND(dev_priv, addr); } u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) @@ -16394,7 +16394,7 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400)) { + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { DRM_INFO("Loading R300 Microcode\n"); for (i = 0; i < 256; i++) { RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, @@ -16759,30 +16759,30 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) (long)dev_priv->gart_info.bus_addr, dev_priv->gart_size); - temp = IGP_READ_MCIND(dev_priv, RS400_MC_MISC_CNTL); + temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) - IGP_WRITE_MCIND(RS400_MC_MISC_CNTL, (RS400_GART_INDEX_REG_EN | + IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN)); else - IGP_WRITE_MCIND(RS400_MC_MISC_CNTL, RS400_GART_INDEX_REG_EN); + IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); - IGP_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN | - RS400_VA_SIZE_32MB)); + IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | + RS480_VA_SIZE_32MB)); - temp = IGP_READ_MCIND(dev_priv, RS400_GART_FEATURE_ID); - IGP_WRITE_MCIND(RS400_GART_FEATURE_ID, (RS400_HANG_EN | - RS400_TLB_ENABLE | - RS400_GTW_LAC_EN | - RS400_1LEVEL_GART)); + temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID); + IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN | + RS480_TLB_ENABLE | + RS480_GTW_LAC_EN | + RS480_1LEVEL_GART)); temp = dev_priv->gart_info.bus_addr & 0xfffff000; temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; - IGP_WRITE_MCIND(RS400_GART_BASE, temp); + IGP_WRITE_MCIND(RS480_GART_BASE, temp); - temp = IGP_READ_MCIND(dev_priv, RS400_AGP_MODE_CNTL); - IGP_WRITE_MCIND(RS400_AGP_MODE_CNTL, ((1 << RS400_REQ_TYPE_SNOOP_SHIFT) | - RS400_REQ_TYPE_SNOOP_DIS)); + temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL); + IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) | + RS480_REQ_TYPE_SNOOP_DIS)); if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { IGP_WRITE_MCIND(RS690_MC_AGP_BASE, @@ -16790,7 +16790,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) IGP_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0); } else { RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start); - RADEON_WRITE(RS400_AGP_BASE_2, 0); + RADEON_WRITE(RS480_AGP_BASE_2, 0); } dev_priv->gart_size = 32*1024*1024; @@ -16799,30 +16799,30 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) radeon_write_agp_location(dev_priv, temp); - temp = IGP_READ_MCIND(dev_priv, RS400_AGP_ADDRESS_SPACE_SIZE); - IGP_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN | - RS400_VA_SIZE_32MB)); + temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE); + IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | + RS480_VA_SIZE_32MB)); do { - temp = IGP_READ_MCIND(dev_priv, RS400_GART_CACHE_CNTRL); - if ((temp & RS400_GART_CACHE_INVALIDATE) == 0) + temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); + if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) break; DRM_UDELAY(1); } while(1); - IGP_WRITE_MCIND(RS400_GART_CACHE_CNTRL, - RS400_GART_CACHE_INVALIDATE); + IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, + RS480_GART_CACHE_INVALIDATE); do { - temp = IGP_READ_MCIND(dev_priv, RS400_GART_CACHE_CNTRL); - if ((temp & RS400_GART_CACHE_INVALIDATE) == 0) + temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); + if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) break; DRM_UDELAY(1); } while(1); - IGP_WRITE_MCIND(RS400_GART_CACHE_CNTRL, 0); + IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0); } else { - IGP_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, 0); + IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0); } } diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index efe702a7..c5a84439 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -123,7 +123,7 @@ enum radeon_family { CHIP_RV380, CHIP_R420, CHIP_RV410, - CHIP_RS400, + CHIP_RS480, CHIP_RS690, CHIP_RV515, CHIP_R520, @@ -463,9 +463,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, #define RADEON_PCIE_TX_GART_END_LO 0x16 #define RADEON_PCIE_TX_GART_END_HI 0x17 -#define RS400_NB_MC_INDEX 0x168 -# define RS400_NB_MC_IND_WR_EN (1 << 8) -#define RS400_NB_MC_DATA 0x16c +#define RS480_NB_MC_INDEX 0x168 +# define RS480_NB_MC_IND_WR_EN (1 << 8) +#define RS480_NB_MC_DATA 0x16c #define RS690_MC_INDEX 0x78 # define RS690_MC_INDEX_MASK 0x1ff @@ -474,42 +474,42 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, #define RS690_MC_DATA 0x7c /* MC indirect registers */ -#define RS400_MC_MISC_CNTL 0x18 -# define RS400_DISABLE_GTW (1 << 1) +#define RS480_MC_MISC_CNTL 0x18 +# define RS480_DISABLE_GTW (1 << 1) /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ -# define RS400_GART_INDEX_REG_EN (1 << 12) +# define RS480_GART_INDEX_REG_EN (1 << 12) # define RS690_BLOCK_GFX_D3_EN (1 << 14) -#define RS400_K8_FB_LOCATION 0x1e -#define RS400_GART_FEATURE_ID 0x2b -# define RS400_HANG_EN (1 << 11) -# define RS400_TLB_ENABLE (1 << 18) -# define RS400_P2P_ENABLE (1 << 19) -# define RS400_GTW_LAC_EN (1 << 25) -# define RS400_2LEVEL_GART (0 << 30) -# define RS400_1LEVEL_GART (1 << 30) -# define RS400_PDC_EN (1 << 31) -#define RS400_GART_BASE 0x2c -#define RS400_GART_CACHE_CNTRL 0x2e -# define RS400_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ -#define RS400_AGP_ADDRESS_SPACE_SIZE 0x38 -# define RS400_GART_EN (1 << 0) -# define RS400_VA_SIZE_32MB (0 << 1) -# define RS400_VA_SIZE_64MB (1 << 1) -# define RS400_VA_SIZE_128MB (2 << 1) -# define RS400_VA_SIZE_256MB (3 << 1) -# define RS400_VA_SIZE_512MB (4 << 1) -# define RS400_VA_SIZE_1GB (5 << 1) -# define RS400_VA_SIZE_2GB (6 << 1) -#define RS400_AGP_MODE_CNTL 0x39 -# define RS400_POST_GART_Q_SIZE (1 << 18) -# define RS400_NONGART_SNOOP (1 << 19) -# define RS400_AGP_RD_BUF_SIZE (1 << 20) -# define RS400_REQ_TYPE_SNOOP_SHIFT 22 -# define RS400_REQ_TYPE_SNOOP_MASK 0x3 -# define RS400_REQ_TYPE_SNOOP_DIS (1 << 24) -#define RS400_MC_MISC_UMA_CNTL 0x5f -#define RS400_MC_MCLK_CNTL 0x7a -#define RS400_MC_UMA_DUALCH_CNTL 0x86 +#define RS480_K8_FB_LOCATION 0x1e +#define RS480_GART_FEATURE_ID 0x2b +# define RS480_HANG_EN (1 << 11) +# define RS480_TLB_ENABLE (1 << 18) +# define RS480_P2P_ENABLE (1 << 19) +# define RS480_GTW_LAC_EN (1 << 25) +# define RS480_2LEVEL_GART (0 << 30) +# define RS480_1LEVEL_GART (1 << 30) +# define RS480_PDC_EN (1 << 31) +#define RS480_GART_BASE 0x2c +#define RS480_GART_CACHE_CNTRL 0x2e +# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ +#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 +# define RS480_GART_EN (1 << 0) +# define RS480_VA_SIZE_32MB (0 << 1) +# define RS480_VA_SIZE_64MB (1 << 1) +# define RS480_VA_SIZE_128MB (2 << 1) +# define RS480_VA_SIZE_256MB (3 << 1) +# define RS480_VA_SIZE_512MB (4 << 1) +# define RS480_VA_SIZE_1GB (5 << 1) +# define RS480_VA_SIZE_2GB (6 << 1) +#define RS480_AGP_MODE_CNTL 0x39 +# define RS480_POST_GART_Q_SIZE (1 << 18) +# define RS480_NONGART_SNOOP (1 << 19) +# define RS480_AGP_RD_BUF_SIZE (1 << 20) +# define RS480_REQ_TYPE_SNOOP_SHIFT 22 +# define RS480_REQ_TYPE_SNOOP_MASK 0x3 +# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) +#define RS480_MC_MISC_UMA_CNTL 0x5f +#define RS480_MC_MCLK_CNTL 0x7a +#define RS480_MC_UMA_DUALCH_CNTL 0x86 #define RS690_MC_FB_LOCATION 0x100 #define RS690_MC_AGP_LOCATION 0x101 @@ -530,7 +530,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, #define RADEON_MEM_CNTL 0x0140 #define RADEON_MEM_SDRAM_MODE_REG 0x0158 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */ -#define RS400_AGP_BASE_2 0x0164 +#define RS480_AGP_BASE_2 0x0164 #define RADEON_AGP_BASE 0x0170 /* pipe config regs */ @@ -1183,12 +1183,12 @@ do { \ RADEON_WRITE(R520_MC_IND_INDEX, 0); \ } while (0) -#define RS400_WRITE_MCIND( addr, val ) \ +#define RS480_WRITE_MCIND( addr, val ) \ do { \ - RADEON_WRITE( RS400_NB_MC_INDEX, \ - ((addr) & 0xff) | RS400_NB_MC_IND_WR_EN); \ - RADEON_WRITE( RS400_NB_MC_DATA, (val) ); \ - RADEON_WRITE( RS400_NB_MC_INDEX, 0xff ); \ + RADEON_WRITE( RS480_NB_MC_INDEX, \ + ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ + RADEON_WRITE( RS480_NB_MC_DATA, (val) ); \ + RADEON_WRITE( RS480_NB_MC_INDEX, 0xff ); \ } while (0) #define RS690_WRITE_MCIND( addr, val ) \ @@ -1203,7 +1203,7 @@ do { \ if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \ RS690_WRITE_MCIND( addr, val ); \ else \ - RS400_WRITE_MCIND( addr, val ); \ + RS480_WRITE_MCIND( addr, val ); \ } while (0) #define CP_PACKET0( reg, n ) \ -- cgit v1.2.3