From b509abe413f74bd08f6415dec8147bd07e78a84b Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Fri, 13 Oct 2006 22:35:22 +0200 Subject: Fix the fifo context size on nv10, nv20 and nv30. --- shared-core/nouveau_fifo.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index bd924f5f..9615e084 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -227,10 +227,22 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, /* disable the fifo caches */ NV_WRITE(NV_PFIFO_CACHES, 0x00000000); - if (dev_priv->card_type <= NV_05) - ctx_size=32; - else - ctx_size=128; + switch(dev_priv->card_type) + { + case NV_03: + case NV_04: + case NV_05: + ctx_size=32; + break; + case NV_10: + case NV_20: + case NV_30: + ctx_size=64; + case NV_40: + case G_70: + default: + ctx_size=128; + } ctx_addr=NV_RAMIN+dev_priv->ramfc_offset+init->channel*ctx_size; // clear the fifo context -- cgit v1.2.3