From 9dd3613073aa2491cef440725fdfa0cf1e8f1a42 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kristian=20H=C3=B8gsberg?= Date: Tue, 17 Nov 2009 09:46:56 -0500 Subject: Drop shared-core, bsd-core, linux-core and scripts subdirs --- shared-core/Makefile.am | 41 - shared-core/drm.h | 887 -- shared-core/drm_internal.h | 40 - shared-core/drm_mode.h | 273 - shared-core/drm_pciids.txt | 594 -- shared-core/drm_sarea.h | 84 - shared-core/i915_dma.c | 1030 -- shared-core/i915_drm.h | 817 -- shared-core/i915_drv.h | 667 -- shared-core/i915_irq.c | 534 - shared-core/i915_mem.c | 386 - shared-core/i915_reg.h | 1422 --- shared-core/i915_suspend.c | 520 - shared-core/imagine_drv.h | 43 - shared-core/mach64_dma.c | 1778 ---- shared-core/mach64_drm.h | 256 - shared-core/mach64_drv.h | 860 -- shared-core/mach64_irq.c | 159 - shared-core/mach64_state.c | 910 -- shared-core/mga_dma.c | 1169 --- shared-core/mga_drm.h | 425 - shared-core/mga_drv.h | 691 -- shared-core/mga_irq.c | 177 - shared-core/mga_state.c | 1139 --- shared-core/mga_ucode.h | 11645 ---------------------- shared-core/mga_warp.c | 198 - shared-core/nouveau_dma.c | 173 - shared-core/nouveau_dma.h | 96 - shared-core/nouveau_drm.h | 220 - shared-core/nouveau_drv.h | 626 -- shared-core/nouveau_fifo.c | 602 -- shared-core/nouveau_irq.c | 588 -- shared-core/nouveau_mem.c | 910 -- shared-core/nouveau_notifier.c | 165 - shared-core/nouveau_object.c | 1173 --- shared-core/nouveau_reg.h | 601 -- shared-core/nouveau_state.c | 897 -- shared-core/nouveau_swmthd.c | 191 - shared-core/nouveau_swmthd.h | 33 - shared-core/nv04_fb.c | 23 - shared-core/nv04_fifo.c | 138 - shared-core/nv04_graph.c | 516 - shared-core/nv04_instmem.c | 159 - shared-core/nv04_mc.c | 22 - shared-core/nv04_timer.c | 53 - shared-core/nv10_fb.c | 25 - shared-core/nv10_fifo.c | 169 - shared-core/nv10_graph.c | 914 -- shared-core/nv20_graph.c | 913 -- shared-core/nv40_fb.c | 62 - shared-core/nv40_fifo.c | 209 - shared-core/nv40_graph.c | 2190 ---- shared-core/nv40_mc.c | 38 - shared-core/nv50_fifo.c | 343 - shared-core/nv50_graph.c | 338 - shared-core/nv50_grctx.h | 20935 --------------------------------------- shared-core/nv50_instmem.c | 331 - shared-core/nv50_mc.c | 43 - shared-core/r128_cce.c | 933 -- shared-core/r128_drm.h | 326 - shared-core/r128_drv.h | 526 - shared-core/r128_irq.c | 116 - shared-core/r128_state.c | 1681 ---- shared-core/r300_cmdbuf.c | 1198 --- shared-core/r300_reg.h | 1778 ---- shared-core/r600_microcode.h | 14275 -------------------------- shared-core/radeon_cp.c | 1793 ---- shared-core/radeon_drm.h | 907 -- shared-core/radeon_drv.h | 1470 --- shared-core/radeon_irq.c | 415 - shared-core/radeon_mem.c | 302 - shared-core/radeon_microcode.h | 1844 ---- shared-core/radeon_state.c | 3263 ------ shared-core/savage_bci.c | 1092 -- shared-core/savage_drm.h | 209 - shared-core/savage_drv.h | 575 -- shared-core/savage_state.c | 1165 --- shared-core/sis_drm.h | 67 - shared-core/sis_drv.h | 90 - shared-core/sis_ds.c | 299 - shared-core/sis_ds.h | 146 - shared-core/sis_mm.c | 386 - shared-core/tdfx_drv.h | 47 - shared-core/via_3d_reg.h | 1650 --- shared-core/via_dma.c | 763 -- shared-core/via_drm.h | 282 - shared-core/via_drv.c | 117 - shared-core/via_drv.h | 197 - shared-core/via_ds.c | 274 - shared-core/via_ds.h | 104 - shared-core/via_irq.c | 402 - shared-core/via_map.c | 139 - shared-core/via_mm.c | 347 - shared-core/via_mm.h | 40 - shared-core/via_verifier.c | 1121 --- shared-core/via_verifier.h | 62 - shared-core/via_video.c | 93 - shared-core/xgi_drm.h | 137 - 98 files changed, 101072 deletions(-) delete mode 100644 shared-core/Makefile.am delete mode 100644 shared-core/drm.h delete mode 100644 shared-core/drm_internal.h delete mode 100644 shared-core/drm_mode.h delete mode 100644 shared-core/drm_pciids.txt delete mode 100644 shared-core/drm_sarea.h delete mode 100644 shared-core/i915_dma.c delete mode 100644 shared-core/i915_drm.h delete mode 100644 shared-core/i915_drv.h delete mode 100644 shared-core/i915_irq.c delete mode 100644 shared-core/i915_mem.c delete mode 100644 shared-core/i915_reg.h delete mode 100644 shared-core/i915_suspend.c delete mode 100644 shared-core/imagine_drv.h delete mode 100644 shared-core/mach64_dma.c delete mode 100644 shared-core/mach64_drm.h delete mode 100644 shared-core/mach64_drv.h delete mode 100644 shared-core/mach64_irq.c delete mode 100644 shared-core/mach64_state.c delete mode 100644 shared-core/mga_dma.c delete mode 100644 shared-core/mga_drm.h delete mode 100644 shared-core/mga_drv.h delete mode 100644 shared-core/mga_irq.c delete mode 100644 shared-core/mga_state.c delete mode 100644 shared-core/mga_ucode.h delete mode 100644 shared-core/mga_warp.c delete mode 100644 shared-core/nouveau_dma.c delete mode 100644 shared-core/nouveau_dma.h delete mode 100644 shared-core/nouveau_drm.h delete mode 100644 shared-core/nouveau_drv.h delete mode 100644 shared-core/nouveau_fifo.c delete mode 100644 shared-core/nouveau_irq.c delete mode 100644 shared-core/nouveau_mem.c delete mode 100644 shared-core/nouveau_notifier.c delete mode 100644 shared-core/nouveau_object.c delete mode 100644 shared-core/nouveau_reg.h delete mode 100644 shared-core/nouveau_state.c delete mode 100644 shared-core/nouveau_swmthd.c delete mode 100644 shared-core/nouveau_swmthd.h delete mode 100644 shared-core/nv04_fb.c delete mode 100644 shared-core/nv04_fifo.c delete mode 100644 shared-core/nv04_graph.c delete mode 100644 shared-core/nv04_instmem.c delete mode 100644 shared-core/nv04_mc.c delete mode 100644 shared-core/nv04_timer.c delete mode 100644 shared-core/nv10_fb.c delete mode 100644 shared-core/nv10_fifo.c delete mode 100644 shared-core/nv10_graph.c delete mode 100644 shared-core/nv20_graph.c delete mode 100644 shared-core/nv40_fb.c delete mode 100644 shared-core/nv40_fifo.c delete mode 100644 shared-core/nv40_graph.c delete mode 100644 shared-core/nv40_mc.c delete mode 100644 shared-core/nv50_fifo.c delete mode 100644 shared-core/nv50_graph.c delete mode 100644 shared-core/nv50_grctx.h delete mode 100644 shared-core/nv50_instmem.c delete mode 100644 shared-core/nv50_mc.c delete mode 100644 shared-core/r128_cce.c delete mode 100644 shared-core/r128_drm.h delete mode 100644 shared-core/r128_drv.h delete mode 100644 shared-core/r128_irq.c delete mode 100644 shared-core/r128_state.c delete mode 100644 shared-core/r300_cmdbuf.c delete mode 100644 shared-core/r300_reg.h delete mode 100644 shared-core/r600_microcode.h delete mode 100644 shared-core/radeon_cp.c delete mode 100644 shared-core/radeon_drm.h delete mode 100644 shared-core/radeon_drv.h delete mode 100644 shared-core/radeon_irq.c delete mode 100644 shared-core/radeon_mem.c delete mode 100644 shared-core/radeon_microcode.h delete mode 100644 shared-core/radeon_state.c delete mode 100644 shared-core/savage_bci.c delete mode 100644 shared-core/savage_drm.h delete mode 100644 shared-core/savage_drv.h delete mode 100644 shared-core/savage_state.c delete mode 100644 shared-core/sis_drm.h delete mode 100644 shared-core/sis_drv.h delete mode 100644 shared-core/sis_ds.c delete mode 100644 shared-core/sis_ds.h delete mode 100644 shared-core/sis_mm.c delete mode 100644 shared-core/tdfx_drv.h delete mode 100644 shared-core/via_3d_reg.h delete mode 100644 shared-core/via_dma.c delete mode 100644 shared-core/via_drm.h delete mode 100644 shared-core/via_drv.c delete mode 100644 shared-core/via_drv.h delete mode 100644 shared-core/via_ds.c delete mode 100644 shared-core/via_ds.h delete mode 100644 shared-core/via_irq.c delete mode 100644 shared-core/via_map.c delete mode 100644 shared-core/via_mm.c delete mode 100644 shared-core/via_mm.h delete mode 100644 shared-core/via_verifier.c delete mode 100644 shared-core/via_verifier.h delete mode 100644 shared-core/via_video.c delete mode 100644 shared-core/xgi_drm.h (limited to 'shared-core') diff --git a/shared-core/Makefile.am b/shared-core/Makefile.am deleted file mode 100644 index 99e90d64..00000000 --- a/shared-core/Makefile.am +++ /dev/null @@ -1,41 +0,0 @@ -# Copyright 2005 Adam Jackson. -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# on the rights to use, copy, modify, merge, publish, distribute, sub -# license, and/or sell copies of the Software, and to permit persons to whom -# the Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -# ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -# XXX airlied says, nothing besides *_drm.h and drm*.h should be necessary. -# however, r300 and via need their reg headers installed in order to build. -# better solutions are welcome. - -klibdrmincludedir = ${includedir}/drm -klibdrminclude_HEADERS = \ - drm.h \ - drm_mode.h \ - drm_sarea.h \ - i915_drm.h \ - mach64_drm.h \ - mga_drm.h \ - nouveau_drm.h \ - r128_drm.h \ - radeon_drm.h \ - savage_drm.h \ - sis_drm.h \ - via_drm.h \ - r300_reg.h \ - via_3d_reg.h \ - xgi_drm.h diff --git a/shared-core/drm.h b/shared-core/drm.h deleted file mode 100644 index 089e184a..00000000 --- a/shared-core/drm.h +++ /dev/null @@ -1,887 +0,0 @@ -/** - * \file drm.h - * Header for the Direct Rendering Manager - * - * \author Rickard E. (Rik) Faith - * - * \par Acknowledgments: - * Dec 1999, Richard Henderson , move to generic \c cmpxchg. - */ - -/* - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/** - * \mainpage - * - * The Direct Rendering Manager (DRM) is a device-independent kernel-level - * device driver that provides support for the XFree86 Direct Rendering - * Infrastructure (DRI). - * - * The DRM supports the Direct Rendering Infrastructure (DRI) in four major - * ways: - * -# The DRM provides synchronized access to the graphics hardware via - * the use of an optimized two-tiered lock. - * -# The DRM enforces the DRI security policy for access to the graphics - * hardware by only allowing authenticated X11 clients access to - * restricted regions of memory. - * -# The DRM provides a generic DMA engine, complete with multiple - * queues and the ability to detect the need for an OpenGL context - * switch. - * -# The DRM is extensible via the use of small device-specific modules - * that rely extensively on the API exported by the DRM module. - * - */ - -#ifndef _DRM_H_ -#define _DRM_H_ - -#ifndef __user -#define __user -#endif -#ifndef __iomem -#define __iomem -#endif - -#ifdef __GNUC__ -# define DEPRECATED __attribute__ ((deprecated)) -#else -# define DEPRECATED -# ifndef __FUNCTION__ -# define __FUNCTION__ __func__ /* C99 */ -# endif -# ifndef __volatile__ -# define __volatile__ volatile -# endif -#endif - -#if defined(__linux__) -#include /* For _IO* macros */ -#define DRM_IOCTL_NR(n) _IOC_NR(n) -#define DRM_IOC_VOID _IOC_NONE -#define DRM_IOC_READ _IOC_READ -#define DRM_IOC_WRITE _IOC_WRITE -#define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE -#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) -#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) -#include -#define DRM_IOCTL_NR(n) ((n) & 0xff) -#define DRM_IOC_VOID IOC_VOID -#define DRM_IOC_READ IOC_OUT -#define DRM_IOC_WRITE IOC_IN -#define DRM_IOC_READWRITE IOC_INOUT -#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) -#endif - -#ifdef __OpenBSD__ -#define DRM_MAJOR 81 -#endif -#if defined(__linux__) || defined(__NetBSD__) -#define DRM_MAJOR 226 -#endif -#define DRM_MAX_MINOR 15 - -#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ -#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ -#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ -#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ - -#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ -#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ -#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) -#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) -#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) - -#if defined(__linux__) -typedef unsigned int drm_handle_t; -#else -#include -typedef unsigned long drm_handle_t; /**< To mapped regions */ -#endif -typedef unsigned int drm_context_t; /**< GLXContext handle */ -typedef unsigned int drm_drawable_t; -typedef unsigned int drm_magic_t; /**< Magic for authentication */ - -/** - * Cliprect. - * - * \warning If you change this structure, make sure you change - * XF86DRIClipRectRec in the server as well - * - * \note KW: Actually it's illegal to change either for - * backwards-compatibility reasons. - */ -struct drm_clip_rect { - unsigned short x1; - unsigned short y1; - unsigned short x2; - unsigned short y2; -}; - -/** - * Texture region, - */ -struct drm_tex_region { - unsigned char next; - unsigned char prev; - unsigned char in_use; - unsigned char padding; - unsigned int age; -}; - -/** - * Hardware lock. - * - * The lock structure is a simple cache-line aligned integer. To avoid - * processor bus contention on a multiprocessor system, there should not be any - * other data stored in the same cache line. - */ -struct drm_hw_lock { - __volatile__ unsigned int lock; /**< lock variable */ - char padding[60]; /**< Pad to cache line */ -}; - -/* This is beyond ugly, and only works on GCC. However, it allows me to use - * drm.h in places (i.e., in the X-server) where I can't use size_t. The real - * fix is to use uint32_t instead of size_t, but that fix will break existing - * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will* - * eventually happen, though. I chose 'unsigned long' to be the fallback type - * because that works on all the platforms I know about. Hopefully, the - * real fix will happen before that bites us. - */ - -#ifdef __SIZE_TYPE__ -# define DRM_SIZE_T __SIZE_TYPE__ -#else -# warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!" -# define DRM_SIZE_T unsigned long -#endif - -/** - * DRM_IOCTL_VERSION ioctl argument type. - * - * \sa drmGetVersion(). - */ -struct drm_version { - int version_major; /**< Major version */ - int version_minor; /**< Minor version */ - int version_patchlevel; /**< Patch level */ - DRM_SIZE_T name_len; /**< Length of name buffer */ - char __user *name; /**< Name of driver */ - DRM_SIZE_T date_len; /**< Length of date buffer */ - char __user *date; /**< User-space buffer to hold date */ - DRM_SIZE_T desc_len; /**< Length of desc buffer */ - char __user *desc; /**< User-space buffer to hold desc */ -}; - -/** - * DRM_IOCTL_GET_UNIQUE ioctl argument type. - * - * \sa drmGetBusid() and drmSetBusId(). - */ -struct drm_unique { - DRM_SIZE_T unique_len; /**< Length of unique */ - char __user *unique; /**< Unique name for driver instantiation */ -}; - -#undef DRM_SIZE_T - -struct drm_list { - int count; /**< Length of user-space structures */ - struct drm_version __user *version; -}; - -struct drm_block { - int unused; -}; - -/** - * DRM_IOCTL_CONTROL ioctl argument type. - * - * \sa drmCtlInstHandler() and drmCtlUninstHandler(). - */ -struct drm_control { - enum { - DRM_ADD_COMMAND, - DRM_RM_COMMAND, - DRM_INST_HANDLER, - DRM_UNINST_HANDLER - } func; - int irq; -}; - -/** - * Type of memory to map. - */ -enum drm_map_type { - _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ - _DRM_REGISTERS = 1, /**< no caching, no core dump */ - _DRM_SHM = 2, /**< shared, cached */ - _DRM_AGP = 3, /**< AGP/GART */ - _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ - _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ - _DRM_GEM = 6, - _DRM_TTM = 7, -}; - -/** - * Memory mapping flags. - */ -enum drm_map_flags { - _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ - _DRM_READ_ONLY = 0x02, - _DRM_LOCKED = 0x04, /**< shared, cached, locked */ - _DRM_KERNEL = 0x08, /**< kernel requires access */ - _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ - _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ - _DRM_REMOVABLE = 0x40, /**< Removable mapping */ - _DRM_DRIVER = 0x80 /**< Managed by driver */ -}; - -struct drm_ctx_priv_map { - unsigned int ctx_id; /**< Context requesting private mapping */ - void *handle; /**< Handle of map */ -}; - -/** - * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls - * argument type. - * - * \sa drmAddMap(). - */ -struct drm_map { - unsigned long offset; /**< Requested physical address (0 for SAREA)*/ - unsigned long size; /**< Requested physical size (bytes) */ - enum drm_map_type type; /**< Type of memory to map */ - enum drm_map_flags flags; /**< Flags */ - void *handle; /**< User-space: "Handle" to pass to mmap() */ - /**< Kernel-space: kernel-virtual address */ - int mtrr; /**< MTRR slot used */ - /* Private data */ -}; - -/** - * DRM_IOCTL_GET_CLIENT ioctl argument type. - */ -struct drm_client { - int idx; /**< Which client desired? */ - int auth; /**< Is client authenticated? */ - unsigned long pid; /**< Process ID */ - unsigned long uid; /**< User ID */ - unsigned long magic; /**< Magic */ - unsigned long iocs; /**< Ioctl count */ -}; - -enum drm_stat_type { - _DRM_STAT_LOCK, - _DRM_STAT_OPENS, - _DRM_STAT_CLOSES, - _DRM_STAT_IOCTLS, - _DRM_STAT_LOCKS, - _DRM_STAT_UNLOCKS, - _DRM_STAT_VALUE, /**< Generic value */ - _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ - _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ - - _DRM_STAT_IRQ, /**< IRQ */ - _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ - _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ - _DRM_STAT_DMA, /**< DMA */ - _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ - _DRM_STAT_MISSED /**< Missed DMA opportunity */ - /* Add to the *END* of the list */ -}; - -/** - * DRM_IOCTL_GET_STATS ioctl argument type. - */ -struct drm_stats { - unsigned long count; - struct { - unsigned long value; - enum drm_stat_type type; - } data[15]; -}; - -/** - * Hardware locking flags. - */ -enum drm_lock_flags { - _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ - _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ - _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ - _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ - /* These *HALT* flags aren't supported yet - -- they will be used to support the - full-screen DGA-like mode. */ - _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ - _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ -}; - -/** - * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. - * - * \sa drmGetLock() and drmUnlock(). - */ -struct drm_lock { - int context; - enum drm_lock_flags flags; -}; - -/** - * DMA flags - * - * \warning - * These values \e must match xf86drm.h. - * - * \sa drm_dma. - */ -enum drm_dma_flags { - /* Flags for DMA buffer dispatch */ - _DRM_DMA_BLOCK = 0x01, /**< - * Block until buffer dispatched. - * - * \note The buffer may not yet have - * been processed by the hardware -- - * getting a hardware lock with the - * hardware quiescent will ensure - * that the buffer has been - * processed. - */ - _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ - _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ - - /* Flags for DMA buffer request */ - _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ - _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ - _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ -}; - -/** - * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. - * - * \sa drmAddBufs(). - */ -struct drm_buf_desc { - int count; /**< Number of buffers of this size */ - int size; /**< Size in bytes */ - int low_mark; /**< Low water mark */ - int high_mark; /**< High water mark */ - enum { - _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ - _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ - _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ - _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ - _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ - } flags; - unsigned long agp_start; /**< - * Start address of where the AGP buffers are - * in the AGP aperture - */ -}; - -/** - * DRM_IOCTL_INFO_BUFS ioctl argument type. - */ -struct drm_buf_info { - int count; /**< Number of buffers described in list */ - struct drm_buf_desc __user *list; /**< List of buffer descriptions */ -}; - -/** - * DRM_IOCTL_FREE_BUFS ioctl argument type. - */ -struct drm_buf_free { - int count; - int __user *list; -}; - -/** - * Buffer information - * - * \sa drm_buf_map. - */ -struct drm_buf_pub { - int idx; /**< Index into the master buffer list */ - int total; /**< Buffer size */ - int used; /**< Amount of buffer in use (for DMA) */ - void __user *address; /**< Address of buffer */ -}; - -/** - * DRM_IOCTL_MAP_BUFS ioctl argument type. - */ -struct drm_buf_map { - int count; /**< Length of the buffer list */ -#if defined(__cplusplus) - void __user *c_virtual; -#else - void __user *virtual; /**< Mmap'd area in user-virtual */ -#endif - struct drm_buf_pub __user *list; /**< Buffer information */ -}; - -/** - * DRM_IOCTL_DMA ioctl argument type. - * - * Indices here refer to the offset into the buffer list in drm_buf_get. - * - * \sa drmDMA(). - */ -struct drm_dma { - int context; /**< Context handle */ - int send_count; /**< Number of buffers to send */ - int __user *send_indices; /**< List of handles to buffers */ - int __user *send_sizes; /**< Lengths of data to send */ - enum drm_dma_flags flags; /**< Flags */ - int request_count; /**< Number of buffers requested */ - int request_size; /**< Desired size for buffers */ - int __user *request_indices; /**< Buffer information */ - int __user *request_sizes; - int granted_count; /**< Number of buffers granted */ -}; - -enum drm_ctx_flags { - _DRM_CONTEXT_PRESERVED = 0x01, - _DRM_CONTEXT_2DONLY = 0x02 -}; - -/** - * DRM_IOCTL_ADD_CTX ioctl argument type. - * - * \sa drmCreateContext() and drmDestroyContext(). - */ -struct drm_ctx { - drm_context_t handle; - enum drm_ctx_flags flags; -}; - -/** - * DRM_IOCTL_RES_CTX ioctl argument type. - */ -struct drm_ctx_res { - int count; - struct drm_ctx __user *contexts; -}; - -/** - * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. - */ -struct drm_draw { - drm_drawable_t handle; -}; - -/** - * DRM_IOCTL_UPDATE_DRAW ioctl argument type. - */ -typedef enum { - DRM_DRAWABLE_CLIPRECTS, -} drm_drawable_info_type_t; - -struct drm_update_draw { - drm_drawable_t handle; - unsigned int type; - unsigned int num; - unsigned long long data; -}; - -/** - * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. - */ -struct drm_auth { - drm_magic_t magic; -}; - -/** - * DRM_IOCTL_IRQ_BUSID ioctl argument type. - * - * \sa drmGetInterruptFromBusID(). - */ -struct drm_irq_busid { - int irq; /**< IRQ number */ - int busnum; /**< bus number */ - int devnum; /**< device number */ - int funcnum; /**< function number */ -}; - -enum drm_vblank_seq_type { - _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ - _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ - _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ - _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ - _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ - _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ -}; - -#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) -#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \ - _DRM_VBLANK_NEXTONMISS) - -struct drm_wait_vblank_request { - enum drm_vblank_seq_type type; - unsigned int sequence; - unsigned long signal; -}; - -struct drm_wait_vblank_reply { - enum drm_vblank_seq_type type; - unsigned int sequence; - long tval_sec; - long tval_usec; -}; - -/** - * DRM_IOCTL_WAIT_VBLANK ioctl argument type. - * - * \sa drmWaitVBlank(). - */ -union drm_wait_vblank { - struct drm_wait_vblank_request request; - struct drm_wait_vblank_reply reply; -}; - - -#define _DRM_PRE_MODESET 1 -#define _DRM_POST_MODESET 2 - -/** - * DRM_IOCTL_MODESET_CTL ioctl argument type - * - * \sa drmModesetCtl(). - */ -struct drm_modeset_ctl { - uint32_t crtc; - uint32_t cmd; -}; - -/** - * DRM_IOCTL_AGP_ENABLE ioctl argument type. - * - * \sa drmAgpEnable(). - */ -struct drm_agp_mode { - unsigned long mode; /**< AGP mode */ -}; - -/** - * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. - * - * \sa drmAgpAlloc() and drmAgpFree(). - */ -struct drm_agp_buffer { - unsigned long size; /**< In bytes -- will round to page boundary */ - unsigned long handle; /**< Used for binding / unbinding */ - unsigned long type; /**< Type of memory to allocate */ - unsigned long physical; /**< Physical used by i810 */ -}; - -/** - * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. - * - * \sa drmAgpBind() and drmAgpUnbind(). - */ -struct drm_agp_binding { - unsigned long handle; /**< From drm_agp_buffer */ - unsigned long offset; /**< In bytes -- will round to page boundary */ -}; - -/** - * DRM_IOCTL_AGP_INFO ioctl argument type. - * - * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), - * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), - * drmAgpVendorId() and drmAgpDeviceId(). - */ -struct drm_agp_info { - int agp_version_major; - int agp_version_minor; - unsigned long mode; - unsigned long aperture_base; /**< physical address */ - unsigned long aperture_size; /**< bytes */ - unsigned long memory_allowed; /**< bytes */ - unsigned long memory_used; - - /** \name PCI information */ - /*@{ */ - unsigned short id_vendor; - unsigned short id_device; - /*@} */ -}; - -/** - * DRM_IOCTL_SG_ALLOC ioctl argument type. - */ -struct drm_scatter_gather { - unsigned long size; /**< In bytes -- will round to page boundary */ - unsigned long handle; /**< Used for mapping / unmapping */ -}; - -/** - * DRM_IOCTL_SET_VERSION ioctl argument type. - */ -struct drm_set_version { - int drm_di_major; - int drm_di_minor; - int drm_dd_major; - int drm_dd_minor; -}; - -struct drm_gem_close { - /** Handle of the object to be closed. */ - uint32_t handle; - uint32_t pad; -}; - -struct drm_gem_flink { - /** Handle for the object being named */ - uint32_t handle; - - /** Returned global name */ - uint32_t name; -}; - -struct drm_gem_open { - /** Name of object being opened */ - uint32_t name; - - /** Returned handle for the object */ - uint32_t handle; - - /** Returned size of the object */ - uint64_t size; -}; - -#include "drm_mode.h" - -/** - * \name Ioctls Definitions - */ -/*@{*/ - -#define DRM_IOCTL_BASE 'd' -#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) -#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) -#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) -#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) - -#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) -#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) -#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) -#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) -#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) -#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) -#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) -#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) -#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) - -#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) -#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) -#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) - -#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) -#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) -#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) -#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) -#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) -#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) -#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) -#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) -#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) -#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) -#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) - -#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) - -#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) -#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) - -#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) -#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) - -#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) -#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) -#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) -#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) -#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) -#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) -#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) -#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) -#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) -#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) -#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) -#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) -#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) - -#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) -#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) -#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) -#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) -#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) -#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) -#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) -#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) - -#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) -#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) - -#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) - -#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) - -#define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, struct drm_mm_init_arg) -#define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, struct drm_mm_type_arg) -#define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, struct drm_mm_type_arg) -#define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg) - -#define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg) -#define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg) -#define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg) -#define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg) -#define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, struct drm_fence_arg) -#define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, struct drm_fence_arg) -#define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, struct drm_fence_arg) -#define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg) - -#define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg) -#define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg) -#define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg) -#define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg) -#define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg) -#define DRM_IOCTL_BO_SETSTATUS DRM_IOWR(0xd3, struct drm_bo_map_wait_idle_arg) -#define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg) -#define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg) -#define DRM_IOCTL_BO_VERSION DRM_IOR(0xd6, struct drm_bo_version_arg) -#define DRM_IOCTL_MM_INFO DRM_IOWR(0xd7, struct drm_mm_info_arg) - -#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) - -#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) -#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) -#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) -#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) -#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) - -#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) - -#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) -#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) -#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) -#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) -#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) -#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) - -#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) -#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) -#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, uint32_t) - -/*@}*/ - -/** - * Device specific ioctls should only be in their respective headers - * The device specific ioctl range is from 0x40 to 0x99. - * Generic IOCTLS restart at 0xA0. - * - * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and - * drmCommandReadWrite(). - */ -#define DRM_COMMAND_BASE 0x40 -#define DRM_COMMAND_END 0xA0 - -/** - * Header for events written back to userspace on the drm fd. The - * type defines the type of event, the length specifies the total - * length of the event (including the header), and user_data is - * typically a 64 bit value passed with the ioctl that triggered the - * event. A read on the drm fd will always only return complete - * events, that is, if for example the read buffer is 100 bytes, and - * there are two 64 byte events pending, only one will be returned. - * - * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and - * up are chipset specific. - */ -struct drm_event { - uint32_t type; - uint32_t length; -}; - -#define DRM_EVENT_VBLANK 0x01 - -struct drm_event_vblank { - struct drm_event base; - uint64_t user_data; - uint32_t tv_sec; - uint32_t tv_usec; - uint32_t sequence; - uint32_t reserved; -}; - -/* typedef area */ -#ifndef __KERNEL__ -typedef struct drm_clip_rect drm_clip_rect_t; -typedef struct drm_tex_region drm_tex_region_t; -typedef struct drm_hw_lock drm_hw_lock_t; -typedef struct drm_version drm_version_t; -typedef struct drm_unique drm_unique_t; -typedef struct drm_list drm_list_t; -typedef struct drm_block drm_block_t; -typedef struct drm_control drm_control_t; -typedef enum drm_map_type drm_map_type_t; -typedef enum drm_map_flags drm_map_flags_t; -typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; -typedef struct drm_map drm_map_t; -typedef struct drm_client drm_client_t; -typedef enum drm_stat_type drm_stat_type_t; -typedef struct drm_stats drm_stats_t; -typedef enum drm_lock_flags drm_lock_flags_t; -typedef struct drm_lock drm_lock_t; -typedef enum drm_dma_flags drm_dma_flags_t; -typedef struct drm_buf_desc drm_buf_desc_t; -typedef struct drm_buf_info drm_buf_info_t; -typedef struct drm_buf_free drm_buf_free_t; -typedef struct drm_buf_pub drm_buf_pub_t; -typedef struct drm_buf_map drm_buf_map_t; -typedef struct drm_dma drm_dma_t; -typedef union drm_wait_vblank drm_wait_vblank_t; -typedef struct drm_agp_mode drm_agp_mode_t; -typedef enum drm_ctx_flags drm_ctx_flags_t; -typedef struct drm_ctx drm_ctx_t; -typedef struct drm_ctx_res drm_ctx_res_t; -typedef struct drm_draw drm_draw_t; -typedef struct drm_update_draw drm_update_draw_t; -typedef struct drm_auth drm_auth_t; -typedef struct drm_irq_busid drm_irq_busid_t; -typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; -typedef struct drm_agp_buffer drm_agp_buffer_t; -typedef struct drm_agp_binding drm_agp_binding_t; -typedef struct drm_agp_info drm_agp_info_t; -typedef struct drm_scatter_gather drm_scatter_gather_t; -typedef struct drm_set_version drm_set_version_t; - -typedef struct drm_fence_arg drm_fence_arg_t; -typedef struct drm_mm_type_arg drm_mm_type_arg_t; -typedef struct drm_mm_init_arg drm_mm_init_arg_t; -#endif - -#endif diff --git a/shared-core/drm_internal.h b/shared-core/drm_internal.h deleted file mode 100644 index b82a189d..00000000 --- a/shared-core/drm_internal.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright 2007 Red Hat, Inc - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* This header file holds function prototypes and data types that are - * internal to the drm (not exported to user space) but shared across - * drivers and platforms */ - -#ifndef __DRM_INTERNAL_H__ -#define __DRM_INTERNAL_H__ - -/** - * Drawable information. - */ -struct drm_drawable_info { - unsigned int num_rects; - struct drm_clip_rect *rects; -}; - -#endif diff --git a/shared-core/drm_mode.h b/shared-core/drm_mode.h deleted file mode 100644 index 9b92733d..00000000 --- a/shared-core/drm_mode.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (c) 2007 Dave Airlie - * Copyright (c) 2007 Jakob Bornecrantz - * Copyright (c) 2008 Red Hat Inc. - * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA - * Copyright (c) 2007-2008 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#ifndef _DRM_MODE_H -#define _DRM_MODE_H - -#ifdef __linux__ -#if !defined(__KERNEL__) && !defined(_KERNEL) -#include -#else -#include -#endif -#endif - -#define DRM_DISPLAY_INFO_LEN 32 -#define DRM_CONNECTOR_NAME_LEN 32 -#define DRM_DISPLAY_MODE_LEN 32 -#define DRM_PROP_NAME_LEN 32 - -#define DRM_MODE_TYPE_BUILTIN (1<<0) -#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) -#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) -#define DRM_MODE_TYPE_PREFERRED (1<<3) -#define DRM_MODE_TYPE_DEFAULT (1<<4) -#define DRM_MODE_TYPE_USERDEF (1<<5) -#define DRM_MODE_TYPE_DRIVER (1<<6) - -/* Video mode flags */ -/* bit compatible with the xorg definitions. */ -#define DRM_MODE_FLAG_PHSYNC (1<<0) -#define DRM_MODE_FLAG_NHSYNC (1<<1) -#define DRM_MODE_FLAG_PVSYNC (1<<2) -#define DRM_MODE_FLAG_NVSYNC (1<<3) -#define DRM_MODE_FLAG_INTERLACE (1<<4) -#define DRM_MODE_FLAG_DBLSCAN (1<<5) -#define DRM_MODE_FLAG_CSYNC (1<<6) -#define DRM_MODE_FLAG_PCSYNC (1<<7) -#define DRM_MODE_FLAG_NCSYNC (1<<8) -#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ -#define DRM_MODE_FLAG_BCAST (1<<10) -#define DRM_MODE_FLAG_PIXMUX (1<<11) -#define DRM_MODE_FLAG_DBLCLK (1<<12) -#define DRM_MODE_FLAG_CLKDIV2 (1<<13) - -/* DPMS flags */ -/* bit compatible with the xorg definitions. */ -#define DRM_MODE_DPMS_ON 0 -#define DRM_MODE_DPMS_STANDBY 1 -#define DRM_MODE_DPMS_SUSPEND 2 -#define DRM_MODE_DPMS_OFF 3 - -/* Scaling mode options */ -#define DRM_MODE_SCALE_NON_GPU 0 -#define DRM_MODE_SCALE_FULLSCREEN 1 -#define DRM_MODE_SCALE_NO_SCALE 2 -#define DRM_MODE_SCALE_ASPECT 3 - -/* Dithering mode options */ -#define DRM_MODE_DITHERING_OFF 0 -#define DRM_MODE_DITHERING_ON 1 - -struct drm_mode_modeinfo { - uint32_t clock; - uint16_t hdisplay, hsync_start, hsync_end, htotal, hskew; - uint16_t vdisplay, vsync_start, vsync_end, vtotal, vscan; - - uint32_t vrefresh; /* vertical refresh * 1000 */ - - uint32_t flags; - uint32_t type; - char name[DRM_DISPLAY_MODE_LEN]; -}; - -struct drm_mode_card_res { - uint64_t fb_id_ptr; - uint64_t crtc_id_ptr; - uint64_t connector_id_ptr; - uint64_t encoder_id_ptr; - uint32_t count_fbs; - uint32_t count_crtcs; - uint32_t count_connectors; - uint32_t count_encoders; - uint32_t min_width, max_width; - uint32_t min_height, max_height; -}; - -struct drm_mode_crtc { - uint64_t set_connectors_ptr; - uint32_t count_connectors; - - uint32_t crtc_id; /**< Id */ - uint32_t fb_id; /**< Id of framebuffer */ - - uint32_t x, y; /**< Position on the frameuffer */ - - uint32_t gamma_size; - uint32_t mode_valid; - struct drm_mode_modeinfo mode; -}; - -#define DRM_MODE_ENCODER_NONE 0 -#define DRM_MODE_ENCODER_DAC 1 -#define DRM_MODE_ENCODER_TMDS 2 -#define DRM_MODE_ENCODER_LVDS 3 -#define DRM_MODE_ENCODER_TVDAC 4 - -struct drm_mode_get_encoder { - uint32_t encoder_id; - uint32_t encoder_type; - - uint32_t crtc_id; /**< Id of crtc */ - - uint32_t possible_crtcs; - uint32_t possible_clones; -}; - -/* This is for connectors with multiple signal types. */ -/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ -#define DRM_MODE_SUBCONNECTOR_Automatic 0 -#define DRM_MODE_SUBCONNECTOR_Unknown 0 -#define DRM_MODE_SUBCONNECTOR_DVID 3 -#define DRM_MODE_SUBCONNECTOR_DVIA 4 -#define DRM_MODE_SUBCONNECTOR_Composite 5 -#define DRM_MODE_SUBCONNECTOR_SVIDEO 6 -#define DRM_MODE_SUBCONNECTOR_Component 8 - -#define DRM_MODE_CONNECTOR_Unknown 0 -#define DRM_MODE_CONNECTOR_VGA 1 -#define DRM_MODE_CONNECTOR_DVII 2 -#define DRM_MODE_CONNECTOR_DVID 3 -#define DRM_MODE_CONNECTOR_DVIA 4 -#define DRM_MODE_CONNECTOR_Composite 5 -#define DRM_MODE_CONNECTOR_SVIDEO 6 -#define DRM_MODE_CONNECTOR_LVDS 7 -#define DRM_MODE_CONNECTOR_Component 8 -#define DRM_MODE_CONNECTOR_9PinDIN 9 -#define DRM_MODE_CONNECTOR_DisplayPort 10 -#define DRM_MODE_CONNECTOR_HDMIA 11 -#define DRM_MODE_CONNECTOR_HDMIB 12 - -struct drm_mode_get_connector { - - uint64_t encoders_ptr; - uint64_t modes_ptr; - uint64_t props_ptr; - uint64_t prop_values_ptr; - - uint32_t count_modes; - uint32_t count_props; - uint32_t count_encoders; - - uint32_t encoder_id; /**< Current Encoder */ - uint32_t connector_id; /**< Id */ - uint32_t connector_type; - uint32_t connector_type_id; - - uint32_t connection; - uint32_t mm_width, mm_height; /**< HxW in millimeters */ - uint32_t subpixel; -}; - -#define DRM_MODE_PROP_PENDING (1<<0) -#define DRM_MODE_PROP_RANGE (1<<1) -#define DRM_MODE_PROP_IMMUTABLE (1<<2) -#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ -#define DRM_MODE_PROP_BLOB (1<<4) - -struct drm_mode_property_enum { - uint64_t value; - char name[DRM_PROP_NAME_LEN]; -}; - -struct drm_mode_get_property { - uint64_t values_ptr; /* values and blob lengths */ - uint64_t enum_blob_ptr; /* enum and blob id ptrs */ - - uint32_t prop_id; - uint32_t flags; - char name[DRM_PROP_NAME_LEN]; - - uint32_t count_values; - uint32_t count_enum_blobs; -}; - -struct drm_mode_connector_set_property { - uint64_t value; - uint32_t prop_id; - uint32_t connector_id; -}; - -struct drm_mode_get_blob { - uint32_t blob_id; - uint32_t length; - uint64_t data; -}; - -struct drm_mode_fb_cmd { - uint32_t fb_id; - uint32_t width, height; - uint32_t pitch; - uint32_t bpp; - uint32_t depth; - /* driver specific handle */ - uint32_t handle; -}; - -struct drm_mode_mode_cmd { - uint32_t connector_id; - struct drm_mode_modeinfo mode; -}; - -#define DRM_MODE_CURSOR_BO (1<<0) -#define DRM_MODE_CURSOR_MOVE (1<<1) - -/* - * depending on the value in flags diffrent members are used. - * - * CURSOR_BO uses - * crtc - * width - * height - * handle - if 0 turns the cursor of - * - * CURSOR_MOVE uses - * crtc - * x - * y - */ -struct drm_mode_cursor { - uint32_t flags; - uint32_t crtc_id; - int32_t x; - int32_t y; - uint32_t width; - uint32_t height; - /* driver specific handle */ - uint32_t handle; -}; - -struct drm_mode_crtc_lut { - uint32_t crtc_id; - uint32_t gamma_size; - - /* pointers to arrays */ - uint64_t red; - uint64_t green; - uint64_t blue; -}; - -#endif diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt deleted file mode 100644 index 5ca04160..00000000 --- a/shared-core/drm_pciids.txt +++ /dev/null @@ -1,594 +0,0 @@ -[radeon] -0x1002 0x3150 CHIP_RV380|RADEON_IS_MOBILITY "ATI Radeon Mobility X600 M24" -0x1002 0x3152 CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon Mobility X300 M24" -0x1002 0x3154 CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI FireGL M24 GL" -0x1002 0x3E50 CHIP_RV380|RADEON_NEW_MEMMAP "ATI Radeon RV380 X600" -0x1002 0x3E54 CHIP_RV380|RADEON_NEW_MEMMAP "ATI FireGL V3200 RV380" -0x1002 0x4136 CHIP_RS100|RADEON_IS_IGP "ATI Radeon RS100 IGP 320" -0x1002 0x4137 CHIP_RS200|RADEON_IS_IGP "ATI Radeon RS200 IGP 340" -0x1002 0x4144 CHIP_R300 "ATI Radeon AD 9500" -0x1002 0x4145 CHIP_R300 "ATI Radeon AE 9700 Pro" -0x1002 0x4146 CHIP_R300 "ATI Radeon AF R300 9600TX" -0x1002 0x4147 CHIP_R300 "ATI FireGL AG Z1" -0x1002 0x4148 CHIP_R350 "ATI Radeon AH 9800 SE" -0x1002 0x4149 CHIP_R350 "ATI Radeon AI 9800" -0x1002 0x414A CHIP_R350 "ATI Radeon AJ 9800" -0x1002 0x414B CHIP_R350 "ATI FireGL AK X2" -0x1002 0x4150 CHIP_RV350 "ATI Radeon AP 9600" -0x1002 0x4151 CHIP_RV350 "ATI Radeon AQ 9600 SE" -0x1002 0x4152 CHIP_RV350 "ATI Radeon AR 9600 XT" -0x1002 0x4153 CHIP_RV350 "ATI Radeon AS 9550" -0x1002 0x4154 CHIP_RV350 "ATI FireGL AT T2" -0x1002 0x4155 CHIP_RV350 "ATI Radeon 9650" -0x1002 0x4156 CHIP_RV350 "ATI FireGL AV RV360 T2" -0x1002 0x4237 CHIP_RS200|RADEON_IS_IGP "ATI Radeon RS250 IGP" -0x1002 0x4242 CHIP_R200 "ATI Radeon BB R200 AIW 8500DV" -0x1002 0x4243 CHIP_R200 "ATI Radeon BC R200" -0x1002 0x4336 CHIP_RS100|RADEON_IS_IGP|RADEON_IS_MOBILITY "ATI Radeon RS100 Mobility U1" -0x1002 0x4337 CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY "ATI Radeon RS200 Mobility IGP 340M" -0x1002 0x4437 CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY "ATI Radeon RS250 Mobility IGP" -0x1002 0x4966 CHIP_RV250 "ATI Radeon If RV250 9000" -0x1002 0x4967 CHIP_RV250 "ATI Radeon Ig RV250 9000" -0x1002 0x4A48 CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon JH R420 X800" -0x1002 0x4A49 CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon JI R420 X800 Pro" -0x1002 0x4A4A CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon JJ R420 X800 SE" -0x1002 0x4A4B CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon JK R420 X800 XT" -0x1002 0x4A4C CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon JL R420 X800" -0x1002 0x4A4D CHIP_R420|RADEON_NEW_MEMMAP "ATI FireGL JM X3-256" -0x1002 0x4A4E CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon JN R420 Mobility M18" -0x1002 0x4A4F CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon JO R420 X800 SE" -0x1002 0x4A50 CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon JP R420 X800 XT PE" -0x1002 0x4A54 CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon JT R420 AIW X800 VE" -0x1002 0x4B49 CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R481 X850 XT" -0x1002 0x4B4A CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R481 X850 SE" -0x1002 0x4B4B CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R481 X850 Pro" -0x1002 0x4B4C CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R481 X850 XT PE" -0x1002 0x4C57 CHIP_RV200|RADEON_IS_MOBILITY "ATI Radeon LW RV200 Mobility 7500 M7" -0x1002 0x4C58 CHIP_RV200|RADEON_IS_MOBILITY "ATI Radeon LX RV200 Mobility FireGL 7800 M7" -0x1002 0x4C59 CHIP_RV100|RADEON_IS_MOBILITY "ATI Radeon LY RV100 Mobility M6" -0x1002 0x4C5A CHIP_RV100|RADEON_IS_MOBILITY "ATI Radeon LZ RV100 Mobility M6" -0x1002 0x4C64 CHIP_RV250|RADEON_IS_MOBILITY "ATI Radeon Ld RV250 Mobility 9000 M9" -0x1002 0x4C66 CHIP_RV250 "ATI Radeon Lf RV250 Mobility 9000 M9 / FireMV 2400 PCI" -0x1002 0x4C67 CHIP_RV250|RADEON_IS_MOBILITY "ATI Radeon Lg RV250 Mobility 9000 M9" -0x1002 0x4E44 CHIP_R300 "ATI Radeon ND R300 9700 Pro" -0x1002 0x4E45 CHIP_R300 "ATI Radeon NE R300 9500 Pro / 9700" -0x1002 0x4E46 CHIP_R300 "ATI Radeon NF R300 9600TX" -0x1002 0x4E47 CHIP_R300 "ATI Radeon NG R300 FireGL X1" -0x1002 0x4E48 CHIP_R350 "ATI Radeon NH R350 9800 Pro" -0x1002 0x4E49 CHIP_R350 "ATI Radeon NI R350 9800" -0x1002 0x4E4A CHIP_R350 "ATI Radeon NJ R360 9800 XT" -0x1002 0x4E4B CHIP_R350 "ATI FireGL NK X2" -0x1002 0x4E50 CHIP_RV350|RADEON_IS_MOBILITY "ATI Radeon RV350 Mobility 9600 M10 NP" -0x1002 0x4E51 CHIP_RV350|RADEON_IS_MOBILITY "ATI Radeon RV350 Mobility 9600 M10 NQ" -0x1002 0x4E52 CHIP_RV350|RADEON_IS_MOBILITY "ATI Radeon RV350 Mobility 9600 M11 NR" -0x1002 0x4E53 CHIP_RV350|RADEON_IS_MOBILITY "ATI Radeon RV350 Mobility 9600 M10 NS" -0x1002 0x4E54 CHIP_RV350|RADEON_IS_MOBILITY "ATI FireGL T2/T2e" -0x1002 0x4E56 CHIP_RV350|RADEON_IS_MOBILITY "ATI Radeon Mobility 9550" -0x1002 0x5144 CHIP_R100|RADEON_SINGLE_CRTC "ATI Radeon QD R100" -0x1002 0x5145 CHIP_R100|RADEON_SINGLE_CRTC "ATI Radeon QE R100" -0x1002 0x5146 CHIP_R100|RADEON_SINGLE_CRTC "ATI Radeon QF R100" -0x1002 0x5147 CHIP_R100|RADEON_SINGLE_CRTC "ATI Radeon QG R100" -0x1002 0x5148 CHIP_R200 "ATI Radeon QH R200 8500" -0x1002 0x514C CHIP_R200 "ATI Radeon QL R200 8500 LE" -0x1002 0x514D CHIP_R200 "ATI Radeon QM R200 9100" -0x1002 0x5157 CHIP_RV200 "ATI Radeon QW RV200 7500" -0x1002 0x5158 CHIP_RV200 "ATI Radeon QX RV200 7500" -0x1002 0x5159 CHIP_RV100 "ATI Radeon QY RV100 7000/VE" -0x1002 0x515A CHIP_RV100 "ATI Radeon QZ RV100 7000/VE" -0x1002 0x515E CHIP_RV100 "ATI ES1000 RN50" -0x1002 0x5460 CHIP_RV380|RADEON_IS_MOBILITY "ATI Radeon Mobility X300 M22" -0x1002 0x5462 CHIP_RV380|RADEON_IS_MOBILITY "ATI Radeon Mobility X600 SE M24C" -0x1002 0x5464 CHIP_RV380|RADEON_IS_MOBILITY "ATI FireGL M22 GL 5464" -0x1002 0x5548 CHIP_R423|RADEON_NEW_MEMMAP "ATI Radeon R423 X800" -0x1002 0x5549 CHIP_R423|RADEON_NEW_MEMMAP "ATI Radeon R423 X800 Pro" -0x1002 0x554A CHIP_R423|RADEON_NEW_MEMMAP "ATI Radeon R423 X800 XT PE" -0x1002 0x554B CHIP_R423|RADEON_NEW_MEMMAP "ATI Radeon R423 X800 SE" -0x1002 0x554C CHIP_R423|RADEON_NEW_MEMMAP "ATI Radeon R430 X800 XTP" -0x1002 0x554D CHIP_R423|RADEON_NEW_MEMMAP "ATI Radeon R430 X800 XL" -0x1002 0x554E CHIP_R423|RADEON_NEW_MEMMAP "ATI Radeon R430 X800 SE" -0x1002 0x554F CHIP_R423|RADEON_NEW_MEMMAP "ATI Radeon R430 X800" -0x1002 0x5550 CHIP_R423|RADEON_NEW_MEMMAP "ATI FireGL V7100 R423" -0x1002 0x5551 CHIP_R423|RADEON_NEW_MEMMAP "ATI FireGL V5100 R423 UQ" -0x1002 0x5552 CHIP_R423|RADEON_NEW_MEMMAP "ATI FireGL unknown R423 UR" -0x1002 0x5554 CHIP_R423|RADEON_NEW_MEMMAP "ATI FireGL unknown R423 UT" -0x1002 0x564A CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility FireGL V5000 M26" -0x1002 0x564B CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility FireGL V5000 M26" -0x1002 0x564F CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon Mobility X700 XL M26" -0x1002 0x5652 CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon Mobility X700 M26" -0x1002 0x5653 CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon Mobility X700 M26" -0x1002 0x5657 CHIP_RV410|RADEON_NEW_MEMMAP "ATI Radeon X550XTX" -0x1002 0x5834 CHIP_RS300|RADEON_IS_IGP "ATI Radeon RS300 9100 IGP" -0x1002 0x5835 CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY "ATI Radeon RS300 Mobility IGP" -0x1002 0x5954 CHIP_RS480|RADEON_IS_IGP|RADEON_IS_IGPGART "ATI RS480 XPRESS 200G" -0x1002 0x5955 CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon XPRESS 200M 5955" -0x1002 0x5974 CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RS482 XPRESS 200" -0x1002 0x5975 CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RS485 XPRESS 1100 IGP" -0x1002 0x5960 CHIP_RV280 "ATI Radeon RV280 9250" -0x1002 0x5961 CHIP_RV280 "ATI Radeon RV280 9200" -0x1002 0x5962 CHIP_RV280 "ATI Radeon RV280 9200" -0x1002 0x5964 CHIP_RV280 "ATI Radeon RV280 9200 SE" -0x1002 0x5965 CHIP_RV280 "ATI FireMV 2200 PCI" -0x1002 0x5969 CHIP_RV100 "ATI ES1000 RN50" -0x1002 0x5a41 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART "ATI Radeon XPRESS 200 5A41 (PCIE)" -0x1002 0x5a42 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon XPRESS 200M 5A42 (PCIE)" -0x1002 0x5a61 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART "ATI Radeon RC410 XPRESS 200" -0x1002 0x5a62 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RC410 XPRESS 200M" -0x1002 0x5b60 CHIP_RV380|RADEON_NEW_MEMMAP "ATI Radeon RV370 X300 SE" -0x1002 0x5b62 CHIP_RV380|RADEON_NEW_MEMMAP "ATI Radeon RV370 X600 Pro" -0x1002 0x5b63 CHIP_RV380|RADEON_NEW_MEMMAP "ATI Radeon RV370 X550" -0x1002 0x5b64 CHIP_RV380|RADEON_NEW_MEMMAP "ATI FireGL V3100 (RV370) 5B64" -0x1002 0x5b65 CHIP_RV380|RADEON_NEW_MEMMAP "ATI FireMV 2200 PCIE (RV370) 5B65" -0x1002 0x5c61 CHIP_RV280|RADEON_IS_MOBILITY "ATI Radeon RV280 Mobility" -0x1002 0x5c63 CHIP_RV280|RADEON_IS_MOBILITY "ATI Radeon RV280 Mobility" -0x1002 0x5d48 CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X800 XT M28" -0x1002 0x5d49 CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility FireGL V5100 M28" -0x1002 0x5d4a CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X800 M28" -0x1002 0x5d4c CHIP_R423|RADEON_NEW_MEMMAP "ATI Radeon R480 X850" -0x1002 0x5d4d CHIP_R423|RADEON_NEW_MEMMAP "ATI Radeon R480 X850 XT PE" -0x1002 0x5d4e CHIP_R423|RADEON_NEW_MEMMAP "ATI Radeon R480 X850 SE" -0x1002 0x5d4f CHIP_R423|RADEON_NEW_MEMMAP "ATI Radeon R480 X850 Pro" -0x1002 0x5d50 CHIP_R423|RADEON_NEW_MEMMAP "ATI unknown Radeon / FireGL R480" -0x1002 0x5d52 CHIP_R423|RADEON_NEW_MEMMAP "ATI Radeon R480 X850 XT" -0x1002 0x5d57 CHIP_R423|RADEON_NEW_MEMMAP "ATI Radeon R423 X800 XT" -0x1002 0x5e48 CHIP_RV410|RADEON_NEW_MEMMAP "ATI FireGL V5000 RV410" -0x1002 0x5e4a CHIP_RV410|RADEON_NEW_MEMMAP "ATI Radeon RV410 X700 XT" -0x1002 0x5e4b CHIP_RV410|RADEON_NEW_MEMMAP "ATI Radeon RV410 X700 Pro" -0x1002 0x5e4c CHIP_RV410|RADEON_NEW_MEMMAP "ATI Radeon RV410 X700 SE" -0x1002 0x5e4d CHIP_RV410|RADEON_NEW_MEMMAP "ATI Radeon RV410 X700" -0x1002 0x5e4f CHIP_RV410|RADEON_NEW_MEMMAP "ATI Radeon RV410 X700 SE" -0x1002 0x7100 CHIP_R520|RADEON_NEW_MEMMAP "ATI Radeon X1800" -0x1002 0x7101 CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1800 XT" -0x1002 0x7102 CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1800" -0x1002 0x7103 CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility FireGL V7200" -0x1002 0x7104 CHIP_R520|RADEON_NEW_MEMMAP "ATI FireGL V7200" -0x1002 0x7105 CHIP_R520|RADEON_NEW_MEMMAP "ATI FireGL V5300" -0x1002 0x7106 CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility FireGL V7100" -0x1002 0x7108 CHIP_R520|RADEON_NEW_MEMMAP "ATI Radeon X1800" -0x1002 0x7109 CHIP_R520|RADEON_NEW_MEMMAP "ATI Radeon X1800" -0x1002 0x710A CHIP_R520|RADEON_NEW_MEMMAP "ATI Radeon X1800" -0x1002 0x710B CHIP_R520|RADEON_NEW_MEMMAP "ATI Radeon X1800" -0x1002 0x710C CHIP_R520|RADEON_NEW_MEMMAP "ATI Radeon X1800" -0x1002 0x710E CHIP_R520|RADEON_NEW_MEMMAP "ATI FireGL V7300" -0x1002 0x710F CHIP_R520|RADEON_NEW_MEMMAP "ATI FireGL V7350" -0x1002 0x7140 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1600" -0x1002 0x7141 CHIP_RV515|RADEON_NEW_MEMMAP "ATI RV505" -0x1002 0x7142 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300/X1550" -0x1002 0x7143 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1550" -0x1002 0x7144 CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI M54-GL" -0x1002 0x7145 CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1400" -0x1002 0x7146 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300/X1550" -0x1002 0x7147 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1550 64-bit" -0x1002 0x7149 CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1300" -0x1002 0x714A CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1300" -0x1002 0x714B CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1300" -0x1002 0x714C CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1300" -0x1002 0x714D CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300" -0x1002 0x714E CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300" -0x1002 0x714F CHIP_RV515|RADEON_NEW_MEMMAP "ATI RV505" -0x1002 0x7151 CHIP_RV515|RADEON_NEW_MEMMAP "ATI RV505" -0x1002 0x7152 CHIP_RV515|RADEON_NEW_MEMMAP "ATI FireGL V3300" -0x1002 0x7153 CHIP_RV515|RADEON_NEW_MEMMAP "ATI FireGL V3350" -0x1002 0x715E CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300" -0x1002 0x715F CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1550 64-bit" -0x1002 0x7180 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300/X1550" -0x1002 0x7181 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1600" -0x1002 0x7183 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300/X1550" -0x1002 0x7186 CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1450" -0x1002 0x7187 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300/X1550" -0x1002 0x7188 CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X2300" -0x1002 0x718A CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X2300" -0x1002 0x718B CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1350" -0x1002 0x718C CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1350" -0x1002 0x718D CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1450" -0x1002 0x718F CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1300" -0x1002 0x7193 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1550" -0x1002 0x7196 CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1350" -0x1002 0x719B CHIP_RV515|RADEON_NEW_MEMMAP "ATI FireMV 2250" -0x1002 0x719F CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X1550 64-bit" -0x1002 0x71C0 CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X1600" -0x1002 0x71C1 CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X1650" -0x1002 0x71C2 CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X1600" -0x1002 0x71C3 CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X1600" -0x1002 0x71C4 CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility FireGL V5200" -0x1002 0x71C5 CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1600" -0x1002 0x71C6 CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X1650" -0x1002 0x71C7 CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X1650" -0x1002 0x71CD CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X1600" -0x1002 0x71CE CHIP_RV530|RADEON_NEW_MEMMAP "ATI Radeon X1300 XT/X1600 Pro" -0x1002 0x71D2 CHIP_RV530|RADEON_NEW_MEMMAP "ATI FireGL V3400" -0x1002 0x71D4 CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility FireGL V5250" -0x1002 0x71D5 CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1700" -0x1002 0x71D6 CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1700 XT" -0x1002 0x71DA CHIP_RV530|RADEON_NEW_MEMMAP "ATI FireGL V5200" -0x1002 0x71DE CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1700" -0x1002 0x7200 CHIP_RV515|RADEON_NEW_MEMMAP "ATI Radeon X2300HD" -0x1002 0x7210 CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 2300" -0x1002 0x7211 CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 2300" -0x1002 0x7240 CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1950" -0x1002 0x7243 CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900" -0x1002 0x7244 CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1950" -0x1002 0x7245 CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900" -0x1002 0x7246 CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900" -0x1002 0x7247 CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900" -0x1002 0x7248 CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900" -0x1002 0x7249 CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900" -0x1002 0x724A CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900" -0x1002 0x724B CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900" -0x1002 0x724C CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900" -0x1002 0x724D CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900" -0x1002 0x724E CHIP_R580|RADEON_NEW_MEMMAP "ATI AMD Stream Processor" -0x1002 0x724F CHIP_R580|RADEON_NEW_MEMMAP "ATI Radeon X1900" -0x1002 0x7280 CHIP_RV570|RADEON_NEW_MEMMAP "ATI Radeon X1950" -0x1002 0x7281 CHIP_RV560|RADEON_NEW_MEMMAP "ATI RV560" -0x1002 0x7283 CHIP_RV560|RADEON_NEW_MEMMAP "ATI RV560" -0x1002 0x7284 CHIP_R580|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X1900" -0x1002 0x7287 CHIP_RV560|RADEON_NEW_MEMMAP "ATI RV560" -0x1002 0x7288 CHIP_RV570|RADEON_NEW_MEMMAP "ATI Radeon X1950 GT" -0x1002 0x7289 CHIP_RV570|RADEON_NEW_MEMMAP "ATI RV570" -0x1002 0x728B CHIP_RV570|RADEON_NEW_MEMMAP "ATI RV570" -0x1002 0x728C CHIP_RV570|RADEON_NEW_MEMMAP "ATI ATI FireGL V7400" -0x1002 0x7290 CHIP_RV560|RADEON_NEW_MEMMAP "ATI RV560" -0x1002 0x7291 CHIP_RV560|RADEON_NEW_MEMMAP "ATI Radeon X1650" -0x1002 0x7293 CHIP_RV560|RADEON_NEW_MEMMAP "ATI Radeon X1650" -0x1002 0x7297 CHIP_RV560|RADEON_NEW_MEMMAP "ATI RV560" -0x1002 0x7834 CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP "ATI Radeon RS350 9000/9100 IGP" -0x1002 0x7835 CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon RS350 Mobility IGP" -0x1002 0x791e CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART "ATI Radeon RS690 X1250 IGP" -0x1002 0x791f CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART "ATI Radeon RS690 X1270 IGP" -0x1002 0x796c CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART "ATI Radeon RS740 HD2100 IGP" -0x1002 0x796d CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART "ATI Radeon RS740 HD2100 IGP" -0x1002 0x796e CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART "ATI Radeon RS740 HD2100 IGP" -0x1002 0x796f CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART "ATI Radeon RS740 HD2100 IGP" - -[r128] -0x1002 0x4c45 0 "ATI Rage 128 Mobility LE (PCI)" -0x1002 0x4c46 0 "ATI Rage 128 Mobility LF (AGP)" -0x1002 0x4d46 0 "ATI Rage 128 Mobility MF (AGP)" -0x1002 0x4d4c 0 "ATI Rage 128 Mobility ML (AGP)" -0x1002 0x5041 0 "ATI Rage 128 Pro PA (PCI)" -0x1002 0x5042 0 "ATI Rage 128 Pro PB (AGP)" -0x1002 0x5043 0 "ATI Rage 128 Pro PC (AGP)" -0x1002 0x5044 0 "ATI Rage 128 Pro PD (PCI)" -0x1002 0x5045 0 "ATI Rage 128 Pro PE (AGP)" -0x1002 0x5046 0 "ATI Rage 128 Pro PF (AGP)" -0x1002 0x5047 0 "ATI Rage 128 Pro PG (PCI)" -0x1002 0x5048 0 "ATI Rage 128 Pro PH (AGP)" -0x1002 0x5049 0 "ATI Rage 128 Pro PI (AGP)" -0x1002 0x504A 0 "ATI Rage 128 Pro PJ (PCI)" -0x1002 0x504B 0 "ATI Rage 128 Pro PK (AGP)" -0x1002 0x504C 0 "ATI Rage 128 Pro PL (AGP)" -0x1002 0x504D 0 "ATI Rage 128 Pro PM (PCI)" -0x1002 0x504E 0 "ATI Rage 128 Pro PN (AGP)" -0x1002 0x504F 0 "ATI Rage 128 Pro PO (AGP)" -0x1002 0x5050 0 "ATI Rage 128 Pro PP (PCI)" -0x1002 0x5051 0 "ATI Rage 128 Pro PQ (AGP)" -0x1002 0x5052 0 "ATI Rage 128 Pro PR (PCI)" -0x1002 0x5053 0 "ATI Rage 128 Pro PS (PCI)" -0x1002 0x5054 0 "ATI Rage 128 Pro PT (AGP)" -0x1002 0x5055 0 "ATI Rage 128 Pro PU (AGP)" -0x1002 0x5056 0 "ATI Rage 128 Pro PV (PCI)" -0x1002 0x5057 0 "ATI Rage 128 Pro PW (AGP)" -0x1002 0x5058 0 "ATI Rage 128 Pro PX (AGP)" -0x1002 0x5245 0 "ATI Rage 128 RE (PCI)" -0x1002 0x5246 0 "ATI Rage 128 RF (AGP)" -0x1002 0x5247 0 "ATI Rage 128 RG (AGP)" -0x1002 0x524b 0 "ATI Rage 128 RK (PCI)" -0x1002 0x524c 0 "ATI Rage 128 RL (AGP)" -0x1002 0x534d 0 "ATI Rage 128 SM (AGP)" -0x1002 0x5446 0 "ATI Rage 128 Pro Ultra TF (AGP)" -0x1002 0x544C 0 "ATI Rage 128 Pro Ultra TL (AGP)" -0x1002 0x5452 0 "ATI Rage 128 Pro Ultra TR (AGP)" - -[mga] -0x102b 0x0520 MGA_CARD_TYPE_G200 "Matrox G200 (PCI)" -0x102b 0x0521 MGA_CARD_TYPE_G200 "Matrox G200 (AGP)" -0x102b 0x0525 MGA_CARD_TYPE_G400 "Matrox G400/G450 (AGP)" -0x102b 0x2527 MGA_CARD_TYPE_G550 "Matrox G550 (AGP)" - -[mach64] -0x1002 0x4749 0 "3D Rage Pro" -0x1002 0x4750 0 "3D Rage Pro 215GP" -0x1002 0x4751 0 "3D Rage Pro 215GQ" -0x1002 0x4742 0 "3D Rage Pro AGP 1X/2X" -0x1002 0x4744 0 "3D Rage Pro AGP 1X" -0x1002 0x4c49 0 "3D Rage LT Pro" -0x1002 0x4c50 0 "3D Rage LT Pro" -0x1002 0x4c51 0 "3D Rage LT Pro" -0x1002 0x4c42 0 "3D Rage LT Pro AGP-133" -0x1002 0x4c44 0 "3D Rage LT Pro AGP-66" -0x1002 0x474c 0 "Rage XC" -0x1002 0x474f 0 "Rage XL" -0x1002 0x4752 0 "Rage XL" -0x1002 0x4753 0 "Rage XC" -0x1002 0x474d 0 "Rage XL AGP 2X" -0x1002 0x474e 0 "Rage XC AGP" -0x1002 0x4c52 0 "Rage Mobility P/M" -0x1002 0x4c53 0 "Rage Mobility L" -0x1002 0x4c4d 0 "Rage Mobility P/M AGP 2X" -0x1002 0x4c4e 0 "Rage Mobility L AGP 2X" - -[sis] -0x1039 0x0300 0 "SiS 300/305" -0x1039 0x5300 0 "SiS 540" -0x1039 0x6300 0 "SiS 630" -0x1039 0x6330 SIS_CHIP_315 "SiS 661" -0x1039 0x7300 0 "SiS 730" -0x18CA 0x0040 SIS_CHIP_315 "Volari V3XT/V5/V8" -0x18CA 0x0042 SIS_CHIP_315 "Volari Unknown" - -[tdfx] -0x121a 0x0003 0 "3dfx Voodoo Banshee" -0x121a 0x0004 0 "3dfx Voodoo3 2000" -0x121a 0x0005 0 "3dfx Voodoo3 3000" -0x121a 0x0007 0 "3dfx Voodoo4 4500" -0x121a 0x0009 0 "3dfx Voodoo5 5500" -0x121a 0x000b 0 "3dfx Voodoo4 4200" - -[viadrv] -0x1106 0x3022 0 "VIA CLE266 3022" -0x1106 0x3118 VIA_PRO_GROUP_A "VIA CN400 / PM8X0" -0x1106 0x3122 0 "VIA CLE266" -0x1106 0x7205 0 "VIA KM400" -0x1106 0x3108 0 "VIA K8M800" -0x1106 0x3344 0 "VIA CN700 / VM800 / P4M800Pro" -0x1106 0x3343 0 "VIA P4M890" -0x1106 0x3230 VIA_DX9_0 "VIA K8M890" -0x1106 0x3157 VIA_PRO_GROUP_A "VIA CX700" -0x1106 0x3371 VIA_DX9_0 "VIA P4M900 / VN896" - -[i810] -0x8086 0x7121 0 "Intel i810 GMCH" -0x8086 0x7123 0 "Intel i810-DC100 GMCH" -0x8086 0x7125 0 "Intel i810E GMCH" -0x8086 0x1132 0 "Intel i815 GMCH" - -[i830] -0x8086 0x3577 0 "Intel i830M GMCH" -0x8086 0x2562 0 "Intel i845G GMCH" -0x8086 0x3582 0 "Intel i852GM/i855GM GMCH" -0x8086 0x2572 0 "Intel i865G GMCH" - -[gamma] -0x3d3d 0x0008 0 "3DLabs GLINT Gamma G1" - -[savage] -0x5333 0x8a20 S3_SAVAGE3D "Savage 3D" -0x5333 0x8a21 S3_SAVAGE3D "Savage 3D/MV" -0x5333 0x8a22 S3_SAVAGE4 "Savage4" -0x5333 0x8a23 S3_SAVAGE4 "Savage4" -0x5333 0x8c10 S3_SAVAGE_MX "Savage/MX-MV" -0x5333 0x8c11 S3_SAVAGE_MX "Savage/MX" -0x5333 0x8c12 S3_SAVAGE_MX "Savage/IX-MV" -0x5333 0x8c13 S3_SAVAGE_MX "Savage/IX" -0x5333 0x8c22 S3_SUPERSAVAGE "SuperSavage MX/128" -0x5333 0x8c24 S3_SUPERSAVAGE "SuperSavage MX/64" -0x5333 0x8c26 S3_SUPERSAVAGE "SuperSavage MX/64C" -0x5333 0x8c2a S3_SUPERSAVAGE "SuperSavage IX/128 SDR" -0x5333 0x8c2b S3_SUPERSAVAGE "SuperSavage IX/128 DDR" -0x5333 0x8c2c S3_SUPERSAVAGE "SuperSavage IX/64 SDR" -0x5333 0x8c2d S3_SUPERSAVAGE "SuperSavage IX/64 DDR" -0x5333 0x8c2e S3_SUPERSAVAGE "SuperSavage IX/C SDR" -0x5333 0x8c2f S3_SUPERSAVAGE "SuperSavage IX/C DDR" -0x5333 0x8a25 S3_PROSAVAGE "ProSavage PM133" -0x5333 0x8a26 S3_PROSAVAGE "ProSavage KM133" -0x5333 0x8d01 S3_TWISTER "ProSavage Twister PN133" -0x5333 0x8d02 S3_TWISTER "ProSavage Twister KN133" -0x5333 0x8d03 S3_PROSAVAGEDDR "ProSavage DDR" -0x5333 0x8d04 S3_PROSAVAGEDDR "ProSavage DDR-K" - -[ffb] - -[i915] -0x8086 0x3577 CHIP_I8XX "Intel i830M GMCH" -0x8086 0x2562 CHIP_I8XX "Intel i845G GMCH" -0x8086 0x3582 CHIP_I8XX "Intel i852GM/i855GM GMCH" -0x8086 0x2572 CHIP_I8XX "Intel i865G GMCH" -0x8086 0x2582 CHIP_I9XX|CHIP_I915 "Intel i915G" -0x8086 0x258a CHIP_I9XX|CHIP_I915 "Intel E7221 (i915)" -0x8086 0x2592 CHIP_I9XX|CHIP_I915 "Intel i915GM" -0x8086 0x2772 CHIP_I9XX|CHIP_I915 "Intel i945G" -0x8086 0x27A2 CHIP_I9XX|CHIP_I915 "Intel i945GM" -0x8086 0x27AE CHIP_I9XX|CHIP_I915 "Intel i945GME" -0x8086 0x2972 CHIP_I9XX|CHIP_I965 "Intel i946GZ" -0x8086 0x2982 CHIP_I9XX|CHIP_I965 "Intel i965G" -0x8086 0x2992 CHIP_I9XX|CHIP_I965 "Intel i965Q" -0x8086 0x29A2 CHIP_I9XX|CHIP_I965 "Intel i965G" -0x8086 0x2A02 CHIP_I9XX|CHIP_I965 "Intel i965GM" -0x8086 0x2A12 CHIP_I9XX|CHIP_I965 "Intel i965GME/GLE" -0x8086 0x29C2 CHIP_I9XX|CHIP_I915 "Intel G33" -0x8086 0x29B2 CHIP_I9XX|CHIP_I915 "Intel Q35" -0x8086 0x29D2 CHIP_I9XX|CHIP_I915 "Intel Q33" -0x8086 0x2A42 CHIP_I9XX|CHIP_I965 "Mobile Intel® GM45 Express Chipset" -0x8086 0x2E02 CHIP_I9XX|CHIP_I965 "Intel Integrated Graphics Device" -0x8086 0x2E12 CHIP_I9XX|CHIP_I965 "Intel Q45/Q43" -0x8086 0x2E22 CHIP_I9XX|CHIP_I965 "Intel G45/G43" - -[imagine] -0x105d 0x2309 IMAGINE_128 "Imagine 128" -0x105d 0x2339 IMAGINE_128_2 "Imagine 128-II" -0x105d 0x493d IMAGINE_T2R "Ticket to Ride" -0x105d 0x5348 IMAGINE_REV4 "Revolution IV" - -[nv] -0x10DE 0x0020 NV04 "NVidia RIVA TNT" -0x10DE 0x0028 NV04 "NVidia RIVA TNT2" -0x10DE 0x002A NV04 "NVidia Unknown TNT2" -0x10DE 0x002C NV04 "NVidia Vanta" -0x10DE 0x0029 NV04 "NVidia RIVA TNT2 Ultra" -0x10DE 0x002D NV04 "NVidia RIVA TNT2 Model 64" -0x10DE 0x00A0 NV04 "NVidia Aladdin TNT2" -0x10DE 0x0100 NV10 "NVidia GeForce 256" -0x10DE 0x0101 NV10 "NVidia GeForce DDR" -0x10DE 0x0103 NV10 "NVidia Quadro" -0x10DE 0x0110 NV10 "NVidia GeForce2 MX/MX 400" -0x10DE 0x0111 NV10 "NVidia GeForce2 MX 100/200" -0x10DE 0x0112 NV10 "NVidia GeForce2 Go" -0x10DE 0x0113 NV10 "NVidia Quadro2 MXR/EX/Go" -0x10DE 0x0150 NV10 "NVidia GeForce2 GTS" -0x10DE 0x0151 NV10 "NVidia GeForce2 Ti" -0x10DE 0x0152 NV10 "NVidia GeForce2 Ultra" -0x10DE 0x0153 NV10 "NVidia Quadro2 Pro" -0x10DE 0x0170 NV10 "NVidia GeForce4 MX 460" -0x10DE 0x0171 NV10 "NVidia GeForce4 MX 440" -0x10DE 0x0172 NV10 "NVidia GeForce4 MX 420" -0x10DE 0x0173 NV10 "NVidia GeForce4 MX 440-SE" -0x10DE 0x0174 NV10 "NVidia GeForce4 440 Go" -0x10DE 0x0175 NV10 "NVidia GeForce4 420 Go" -0x10DE 0x0176 NV10 "NVidia GeForce4 420 Go 32M" -0x10DE 0x0177 NV10 "NVidia GeForce4 460 Go" -0x10DE 0x0178 NV10 "NVidia Quadro4 550 XGL" -0x10DE 0x0179 NV10 "NVidia GeForce4" -0x10DE 0x017A NV10 "NVidia Quadro4 NVS" -0x10DE 0x017C NV10 "NVidia Quadro4 500 GoGL" -0x10DE 0x017D NV10 "NVidia GeForce4 410 Go 16M" -0x10DE 0x0181 NV10 "NVidia GeForce4 MX 440 with AGP8X" -0x10DE 0x0182 NV10 "NVidia GeForce4 MX 440SE with AGP8X" -0x10DE 0x0183 NV10 "NVidia GeForce4 MX 420 with AGP8X" -0x10DE 0x0185 NV10 "NVidia GeForce4 MX 4000" -0x10DE 0x0186 NV10 "NVidia GeForce4 448 Go" -0x10DE 0x0187 NV10 "NVidia GeForce4 488 Go" -0x10DE 0x0188 NV10 "NVidia Quadro4 580 XGL" -0x10DE 0x0189 NV10 "NVidia GeForce4 MX with AGP8X (Mac)" -0x10DE 0x018A NV10 "NVidia Quadro4 280 NVS" -0x10DE 0x018B NV10 "NVidia Quadro4 380 XGL" -0x10DE 0x018C NV10 "NVidia Quadro NVS 50 PCI" -0x10DE 0x018D NV10 "NVidia GeForce4 448 Go" -0x10DE 0x01A0 NV10 "NVidia GeForce2 Integrated GPU" -0x10DE 0x01F0 NV10 "NVidia GeForce4 MX Integrated GPU" -0x10DE 0x0200 NV20 "NVidia GeForce3" -0x10DE 0x0201 NV20 "NVidia GeForce3 Ti 200" -0x10DE 0x0202 NV20 "NVidia GeForce3 Ti 500" -0x10DE 0x0203 NV20 "NVidia Quadro DCC" -0x10DE 0x0250 NV20 "NVidia GeForce4 Ti 4600" -0x10DE 0x0251 NV20 "NVidia GeForce4 Ti 4400" -0x10DE 0x0252 NV20 "NVidia 0x0252" -0x10DE 0x0253 NV20 "NVidia GeForce4 Ti 4200" -0x10DE 0x0258 NV20 "NVidia Quadro4 900 XGL" -0x10DE 0x0259 NV20 "NVidia Quadro4 750 XGL" -0x10DE 0x025B NV20 "NVidia Quadro4 700 XGL" -0x10DE 0x0280 NV20 "NVidia GeForce4 Ti 4800" -0x10DE 0x0281 NV20 "NVidia GeForce4 Ti 4200 with AGP8X" -0x10DE 0x0282 NV20 "NVidia GeForce4 Ti 4800 SE" -0x10DE 0x0286 NV20 "NVidia GeForce4 4200 Go" -0x10DE 0x028C NV20 "NVidia Quadro4 700 GoGL" -0x10DE 0x0288 NV20 "NVidia Quadro4 980 XGL" -0x10DE 0x0289 NV20 "NVidia Quadro4 780 XGL" -0x10DE 0x0301 NV30 "NVidia GeForce FX 5800 Ultra" -0x10DE 0x0302 NV30 "NVidia GeForce FX 5800" -0x10DE 0x0308 NV30 "NVidia Quadro FX 2000" -0x10DE 0x0309 NV30 "NVidia Quadro FX 1000" -0x10DE 0x0311 NV30 "NVidia GeForce FX 5600 Ultra" -0x10DE 0x0312 NV30 "NVidia GeForce FX 5600" -0x10DE 0x0313 NV30 "NVidia 0x0313" -0x10DE 0x0314 NV30 "NVidia GeForce FX 5600SE" -0x10DE 0x0316 NV30 "NVidia 0x0316" -0x10DE 0x0317 NV30 "NVidia 0x0317" -0x10DE 0x031A NV30 "NVidia GeForce FX Go5600" -0x10DE 0x031B NV30 "NVidia GeForce FX Go5650" -0x10DE 0x031C NV30 "NVidia Quadro FX Go700" -0x10DE 0x031D NV30 "NVidia 0x031D" -0x10DE 0x031E NV30 "NVidia 0x031E" -0x10DE 0x031F NV30 "NVidia 0x031F" -0x10DE 0x0320 NV30 "NVidia GeForce FX 5200" -0x10DE 0x0321 NV30 "NVidia GeForce FX 5200 Ultra" -0x10DE 0x0322 NV30 "NVidia GeForce FX 5200" -0x10DE 0x0323 NV30 "NVidia GeForce FX 5200SE" -0x10DE 0x0324 NV30 "NVidia GeForce FX Go5200" -0x10DE 0x0325 NV30 "NVidia GeForce FX Go5250" -0x10DE 0x0326 NV30 "NVidia GeForce FX 5500" -0x10DE 0x0327 NV30 "NVidia GeForce FX 5100" -0x10DE 0x0328 NV30 "NVidia GeForce FX Go5200 32M/64M" -0x10DE 0x0329 NV30 "NVidia GeForce FX 5200 (Mac)" -0x10DE 0x032A NV30 "NVidia Quadro NVS 280 PCI" -0x10DE 0x032B NV30 "NVidia Quadro FX 500/600 PCI" -0x10DE 0x032C NV30 "NVidia GeForce FX Go53xx Series" -0x10DE 0x032D NV30 "NVidia GeForce FX Go5100" -0x10DE 0x032F NV30 "NVidia 0x032F" -0x10DE 0x0330 NV30 "NVidia GeForce FX 5900 Ultra" -0x10DE 0x0331 NV30 "NVidia GeForce FX 5900" -0x10DE 0x0332 NV30 "NVidia GeForce FX 5900XT" -0x10DE 0x0333 NV30 "NVidia GeForce FX 5950 Ultra" -0x10DE 0x033F NV30 "NVidia Quadro FX 700" -0x10DE 0x0334 NV30 "NVidia GeForce FX 5900ZT" -0x10DE 0x0338 NV30 "NVidia Quadro FX 3000" -0x10DE 0x0341 NV30 "NVidia GeForce FX 5700 Ultra" -0x10DE 0x0342 NV30 "NVidia GeForce FX 5700" -0x10DE 0x0343 NV30 "NVidia GeForce FX 5700LE" -0x10DE 0x0344 NV30 "NVidia GeForce FX 5700VE" -0x10DE 0x0345 NV30 "NVidia 0x0345" -0x10DE 0x0347 NV30 "NVidia GeForce FX Go5700" -0x10DE 0x0348 NV30 "NVidia GeForce FX Go5700" -0x10DE 0x0349 NV30 "NVidia 0x0349" -0x10DE 0x034B NV30 "NVidia 0x034B" -0x10DE 0x034C NV30 "NVidia Quadro FX Go1000" -0x10DE 0x034E NV30 "NVidia Quadro FX 1100" -0x10DE 0x034F NV30 "NVidia 0x034F" -0x10DE 0x0040 NV40 "NVidia GeForce 6800 Ultra" -0x10DE 0x0041 NV40 "NVidia GeForce 6800" -0x10DE 0x0042 NV40 "NVidia GeForce 6800 LE" -0x10DE 0x0043 NV40 "NVidia 0x0043" -0x10DE 0x0045 NV40 "NVidia GeForce 6800 GT" -0x10DE 0x0046 NV40 "NVidia GeForce 6800 GT" -0x10DE 0x0049 NV40 "NVidia 0x0049" -0x10DE 0x004E NV40 "NVidia Quadro FX 4000" -0x10DE 0x00C0 NV40 "NVidia 0x00C0" -0x10DE 0x00C1 NV40 "NVidia GeForce 6800" -0x10DE 0x00C2 NV40 "NVidia GeForce 6800 LE" -0x10DE 0x00C8 NV40 "NVidia GeForce Go 6800" -0x10DE 0x00C9 NV40 "NVidia GeForce Go 6800 Ultra" -0x10DE 0x00CC NV40 "NVidia Quadro FX Go1400" -0x10DE 0x00CD NV40 "NVidia Quadro FX 3450/4000 SDI" -0x10DE 0x00CE NV40 "NVidia Quadro FX 1400" -0x10de 0x00f0 NV40 "Nvidia GeForce 6600 GT" -0x10de 0x00f1 NV40 "Nvidia GeForce 6600 GT" -0x10DE 0x0140 NV40 "NVidia GeForce 6600 GT" -0x10DE 0x0141 NV40 "NVidia GeForce 6600" -0x10DE 0x0142 NV40 "NVidia GeForce 6600 LE" -0x10DE 0x0143 NV40 "NVidia 0x0143" -0x10DE 0x0144 NV40 "NVidia GeForce Go 6600" -0x10DE 0x0145 NV40 "NVidia GeForce 6610 XL" -0x10DE 0x0146 NV40 "NVidia GeForce Go 6600 TE/6200 TE" -0x10DE 0x0147 NV40 "NVidia GeForce 6700 XL" -0x10DE 0x0148 NV40 "NVidia GeForce Go 6600" -0x10DE 0x0149 NV40 "NVidia GeForce Go 6600 GT" -0x10DE 0x014B NV40 "NVidia 0x014B" -0x10DE 0x014C NV40 "NVidia 0x014C" -0x10DE 0x014D NV40 "NVidia 0x014D" -0x10DE 0x014E NV40 "NVidia Quadro FX 540" -0x10DE 0x014F NV40 "NVidia GeForce 6200" -0x10DE 0x0160 NV40 "NVidia 0x0160" -0x10DE 0x0161 NV40 "NVidia GeForce 6200 TurboCache(TM)" -0x10DE 0x0162 NV40 "NVidia GeForce 6200SE TurboCache(TM)" -0x10DE 0x0163 NV40 "NVidia 0x0163" -0x10DE 0x0164 NV40 "NVidia GeForce Go 6200" -0x10DE 0x0165 NV40 "NVidia Quadro NVS 285" -0x10DE 0x0166 NV40 "NVidia GeForce Go 6400" -0x10DE 0x0167 NV40 "NVidia GeForce Go 6200" -0x10DE 0x0168 NV40 "NVidia GeForce Go 6400" -0x10DE 0x0169 NV40 "NVidia 0x0169" -0x10DE 0x016B NV40 "NVidia 0x016B" -0x10DE 0x016C NV40 "NVidia 0x016C" -0x10DE 0x016D NV40 "NVidia 0x016D" -0x10DE 0x016E NV40 "NVidia 0x016E" -0x10DE 0x0210 NV40 "NVidia 0x0210" -0x10DE 0x0211 NV40 "NVidia GeForce 6800" -0x10DE 0x0212 NV40 "NVidia GeForce 6800 LE" -0x10DE 0x0215 NV40 "NVidia GeForce 6800 GT" -0x10DE 0x0220 NV40 "NVidia 0x0220" -0x10DE 0x0221 NV40 "NVidia GeForce 6200" -0x10DE 0x0222 NV40 "NVidia 0x0222" -0x10DE 0x0228 NV40 "NVidia 0x0228" -0x10DE 0x0090 NV40 "NVidia 0x0090" -0x10DE 0x0091 NV40 "NVidia GeForce 7800 GTX" -0x10DE 0x0092 NV40 "NVidia 0x0092" -0x10DE 0x0093 NV40 "NVidia 0x0093" -0x10DE 0x0094 NV40 "NVidia 0x0094" -0x10DE 0x0098 NV40 "NVidia 0x0098" -0x10DE 0x0099 NV40 "NVidia GeForce Go 7800 GTX" -0x10DE 0x009C NV40 "NVidia 0x009C" -0x10DE 0x009D NV40 "NVidia Quadro FX 4500" -0x10DE 0x009E NV40 "NVidia 0x009E" - -[xgi] -0x18ca 0x2200 0 "XP5" -0x18ca 0x0047 0 "XP10 / XG47" diff --git a/shared-core/drm_sarea.h b/shared-core/drm_sarea.h deleted file mode 100644 index 8b677522..00000000 --- a/shared-core/drm_sarea.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * \file drm_sarea.h - * \brief SAREA definitions - * - * \author Michel D�zer - */ - -/* - * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DRM_SAREA_H_ -#define _DRM_SAREA_H_ - -#include "drm.h" - -/* SAREA area needs to be at least a page */ -#if defined(__alpha__) -#define SAREA_MAX 0x2000 -#elif defined(__ia64__) -#define SAREA_MAX 0x10000 /* 64kB */ -#else -/* Intel 830M driver needs at least 8k SAREA */ -#define SAREA_MAX 0x2000UL -#endif - -/** Maximum number of drawables in the SAREA */ -#define SAREA_MAX_DRAWABLES 256 - -#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000 - -/** SAREA drawable */ -struct drm_sarea_drawable { - unsigned int stamp; - unsigned int flags; -}; - -/** SAREA frame */ -struct drm_sarea_frame { - unsigned int x; - unsigned int y; - unsigned int width; - unsigned int height; - unsigned int fullscreen; -}; - -/** SAREA */ -struct drm_sarea { - /** first thing is always the DRM locking structure */ - struct drm_hw_lock lock; - /** \todo Use readers/writer lock for drm_sarea::drawable_lock */ - struct drm_hw_lock drawable_lock; - struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ - struct drm_sarea_frame frame; /**< frame */ - drm_context_t dummy_context; -}; - -#ifndef __KERNEL__ -typedef struct drm_sarea_drawable drm_sarea_drawable_t; -typedef struct drm_sarea_frame drm_sarea_frame_t; -typedef struct drm_sarea drm_sarea_t; -#endif - -#endif /* _DRM_SAREA_H_ */ diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c deleted file mode 100644 index 9afb2e84..00000000 --- a/shared-core/i915_dma.c +++ /dev/null @@ -1,1030 +0,0 @@ -/* i915_dma.c -- DMA support for the I915 -*- linux-c -*- - */ -/* - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "drmP.h" -#include "drm.h" -#include "i915_drm.h" -#include "i915_drv.h" - -/* Really want an OS-independent resettable timer. Would like to have - * this loop run for (eg) 3 sec, but have the timer reset every time - * the head pointer changes, so that EBUSY only happens if the ring - * actually stalls for (eg) 3 seconds. - */ -int i915_wait_ring(struct drm_device * dev, int n, const char *caller) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_ring_buffer_t *ring = &(dev_priv->ring); - u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR; - u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD; - u32 last_acthd = I915_READ(acthd_reg); - u32 acthd; - int i; - - for (i = 0; i < 100000; i++) { - ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; - acthd = I915_READ(acthd_reg); - ring->space = ring->head - (ring->tail + 8); - if (ring->space < 0) - ring->space += ring->Size; - if (ring->space >= n) - return 0; - - if (dev_priv->sarea_priv) - dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; - - if (ring->head != last_head) - i = 0; - - if (acthd != last_acthd) - i = 0; - - last_head = ring->head; - last_acthd = acthd; - DRM_UDELAY(10 * 1000); - } - - return -EBUSY; -} - -/** - * Sets up the hardware status page for devices that need a physical address - * in the register. - */ -static int i915_init_phys_hws(struct drm_device *dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - - /* Program Hardware Status Page */ - DRM_UNLOCK(); - dev_priv->status_page_dmah = - drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); - DRM_LOCK(); - if (!dev_priv->status_page_dmah) { - DRM_ERROR("Can not allocate hardware status page\n"); - return -ENOMEM; - } - dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr; - dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; - - memset(dev_priv->hw_status_page, 0, PAGE_SIZE); - - I915_WRITE(HWS_PGA, dev_priv->dma_status_page); - DRM_DEBUG("Enabled hardware status page\n"); - return 0; -} - -/** - * Frees the hardware status page, whether it's a physical address or a virtual - * address set up by the X Server. - */ -static void i915_free_hws(struct drm_device *dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - if (dev_priv->status_page_dmah) { - drm_pci_free(dev, dev_priv->status_page_dmah); - dev_priv->status_page_dmah = NULL; - } - - if (dev_priv->status_gfx_addr) { - dev_priv->status_gfx_addr = 0; - drm_core_ioremapfree(&dev_priv->hws_map, dev); - } - - /* Need to rewrite hardware status page */ - I915_WRITE(HWS_PGA, 0x1ffff000); -} - -void i915_kernel_lost_context(struct drm_device * dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_ring_buffer_t *ring = &(dev_priv->ring); - - ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; - ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; - ring->space = ring->head - (ring->tail + 8); - if (ring->space < 0) - ring->space += ring->Size; - - if (ring->head == ring->tail && dev_priv->sarea_priv) - dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; -} - -static int i915_dma_cleanup(struct drm_device * dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - /* Make sure interrupts are disabled here because the uninstall ioctl - * may not have been called from userspace and after dev_private - * is freed, it's too late. - */ - if (dev->irq_enabled) - drm_irq_uninstall(dev); - - if (dev_priv->ring.virtual_start) { - drm_core_ioremapfree(&dev_priv->ring.map, dev); - dev_priv->ring.virtual_start = NULL; - dev_priv->ring.map.handle = NULL; - dev_priv->ring.map.size = 0; - } - - /* Clear the HWS virtual address at teardown */ - if (I915_NEED_GFX_HWS(dev)) - i915_free_hws(dev); - - return 0; -} - -static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - - dev_priv->sarea = drm_getsarea(dev); - if (!dev_priv->sarea) { - DRM_ERROR("can not find sarea!\n"); - i915_dma_cleanup(dev); - return -EINVAL; - } - - dev_priv->sarea_priv = (drm_i915_sarea_t *) - ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset); - - if (init->ring_size != 0) { - if (dev_priv->ring.ring_obj != NULL) { - i915_dma_cleanup(dev); - DRM_ERROR("Client tried to initialize ringbuffer in " - "GEM mode\n"); - return -EINVAL; - } - - dev_priv->ring.Size = init->ring_size; - dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; - - dev_priv->ring.map.offset = init->ring_start; - dev_priv->ring.map.size = init->ring_size; - dev_priv->ring.map.type = 0; - dev_priv->ring.map.flags = 0; - dev_priv->ring.map.mtrr = 0; - - drm_core_ioremap(&dev_priv->ring.map, dev); - - if (dev_priv->ring.map.handle == NULL) { - i915_dma_cleanup(dev); - DRM_ERROR("can not ioremap virtual address for" - " ring buffer\n"); - return -ENOMEM; - } - } - - dev_priv->ring.virtual_start = dev_priv->ring.map.handle; - - dev_priv->cpp = init->cpp; - dev_priv->back_offset = init->back_offset; - dev_priv->front_offset = init->front_offset; - dev_priv->current_page = 0; - dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; - - /* Allow hardware batchbuffers unless told otherwise. - */ - dev_priv->allow_batchbuffer = 1; - - return 0; -} - -static int i915_dma_resume(struct drm_device * dev) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - - DRM_DEBUG("\n"); - - if (!dev_priv->sarea) { - DRM_ERROR("can not find sarea!\n"); - return -EINVAL; - } - - if (dev_priv->ring.map.handle == NULL) { - DRM_ERROR("can not ioremap virtual address for" - " ring buffer\n"); - return -ENOMEM; - } - - /* Program Hardware Status Page */ - if (!dev_priv->hw_status_page) { - DRM_ERROR("Can not find hardware status page\n"); - return -EINVAL; - } - DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); - - if (dev_priv->status_gfx_addr != 0) - I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); - else - I915_WRITE(HWS_PGA, dev_priv->dma_status_page); - DRM_DEBUG("Enabled hardware status page\n"); - - return 0; -} - -static int i915_dma_init(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_i915_init_t *init = data; - int retcode = 0; - - switch (init->func) { - case I915_INIT_DMA: - retcode = i915_initialize(dev, init); - break; - case I915_CLEANUP_DMA: - retcode = i915_dma_cleanup(dev); - break; - case I915_RESUME_DMA: - retcode = i915_dma_resume(dev); - break; - default: - retcode = -EINVAL; - break; - } - - return retcode; -} - -/* Implement basically the same security restrictions as hardware does - * for MI_BATCH_NON_SECURE. These can be made stricter at any time. - * - * Most of the calculations below involve calculating the size of a - * particular instruction. It's important to get the size right as - * that tells us where the next instruction to check is. Any illegal - * instruction detected will be given a size of zero, which is a - * signal to abort the rest of the buffer. - */ -static int do_validate_cmd(int cmd) -{ - switch (((cmd >> 29) & 0x7)) { - case 0x0: - switch ((cmd >> 23) & 0x3f) { - case 0x0: - return 1; /* MI_NOOP */ - case 0x4: - return 1; /* MI_FLUSH */ - default: - return 0; /* disallow everything else */ - } - break; - case 0x1: - return 0; /* reserved */ - case 0x2: - return (cmd & 0xff) + 2; /* 2d commands */ - case 0x3: - if (((cmd >> 24) & 0x1f) <= 0x18) - return 1; - - switch ((cmd >> 24) & 0x1f) { - case 0x1c: - return 1; - case 0x1d: - switch ((cmd >> 16) & 0xff) { - case 0x3: - return (cmd & 0x1f) + 2; - case 0x4: - return (cmd & 0xf) + 2; - default: - return (cmd & 0xffff) + 2; - } - case 0x1e: - if (cmd & (1 << 23)) - return (cmd & 0xffff) + 1; - else - return 1; - case 0x1f: - if ((cmd & (1 << 23)) == 0) /* inline vertices */ - return (cmd & 0x1ffff) + 2; - else if (cmd & (1 << 17)) /* indirect random */ - if ((cmd & 0xffff) == 0) - return 0; /* unknown length, too hard */ - else - return (((cmd & 0xffff) + 1) / 2) + 1; - else - return 2; /* indirect sequential */ - default: - return 0; - } - default: - return 0; - } - - return 0; -} - -static int validate_cmd(int cmd) -{ - int ret = do_validate_cmd(cmd); - -/* printk("validate_cmd( %x ): %d\n", cmd, ret); */ - - return ret; -} - -static int i915_emit_cmds(struct drm_device *dev, int __user *buffer, - int dwords) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - int i; - RING_LOCALS; - - if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) - return -EINVAL; - - BEGIN_LP_RING((dwords+1)&~1); - - for (i = 0; i < dwords;) { - int cmd, sz; - - if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) - return -EINVAL; - - if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) - return -EINVAL; - - OUT_RING(cmd); - - while (++i, --sz) { - if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], - sizeof(cmd))) { - return -EINVAL; - } - OUT_RING(cmd); - } - } - - if (dwords & 1) - OUT_RING(0); - - ADVANCE_LP_RING(); - - return 0; -} - -int i915_emit_box(struct drm_device * dev, - struct drm_clip_rect __user * boxes, - int i, int DR1, int DR4) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - struct drm_clip_rect box; - RING_LOCALS; - - if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) { - return -EFAULT; - } - - if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { - DRM_ERROR("Bad box %d,%d..%d,%d\n", - box.x1, box.y1, box.x2, box.y2); - return -EINVAL; - } - - if (IS_I965G(dev)) { - BEGIN_LP_RING(4); - OUT_RING(GFX_OP_DRAWRECT_INFO_I965); - OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); - OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); - OUT_RING(DR4); - ADVANCE_LP_RING(); - } else { - BEGIN_LP_RING(6); - OUT_RING(GFX_OP_DRAWRECT_INFO); - OUT_RING(DR1); - OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); - OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); - OUT_RING(DR4); - OUT_RING(0); - ADVANCE_LP_RING(); - } - - return 0; -} - -/* XXX: Emitting the counter should really be moved to part of the IRQ - * emit. For now, do it in both places: - */ - -static void i915_emit_breadcrumb(struct drm_device *dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - RING_LOCALS; - - dev_priv->counter++; - if (dev_priv->counter > 0x7FFFFFFFUL) - dev_priv->counter = 0; - if (dev_priv->sarea_priv) - dev_priv->sarea_priv->last_enqueue = dev_priv->counter; - - BEGIN_LP_RING(4); - OUT_RING(MI_STORE_DWORD_INDEX); - OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); - OUT_RING(dev_priv->counter); - OUT_RING(0); - ADVANCE_LP_RING(); -} - -static int i915_dispatch_cmdbuffer(struct drm_device * dev, - drm_i915_cmdbuffer_t * cmd) -{ - int nbox = cmd->num_cliprects; - int i = 0, count, ret; - - if (cmd->sz & 0x3) { - DRM_ERROR("alignment\n"); - return -EINVAL; - } - - i915_kernel_lost_context(dev); - - count = nbox ? nbox : 1; - - for (i = 0; i < count; i++) { - if (i < nbox) { - ret = i915_emit_box(dev, cmd->cliprects, i, - cmd->DR1, cmd->DR4); - if (ret) - return ret; - } - - ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4); - if (ret) - return ret; - } - - i915_emit_breadcrumb(dev); - return 0; -} - -static int i915_dispatch_batchbuffer(struct drm_device * dev, - drm_i915_batchbuffer_t * batch) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - struct drm_clip_rect __user *boxes = batch->cliprects; - int nbox = batch->num_cliprects; - int i = 0, count; - RING_LOCALS; - - if ((batch->start | batch->used) & 0x7) { - DRM_ERROR("alignment\n"); - return -EINVAL; - } - - i915_kernel_lost_context(dev); - - count = nbox ? nbox : 1; - - for (i = 0; i < count; i++) { - if (i < nbox) { - int ret = i915_emit_box(dev, boxes, i, - batch->DR1, batch->DR4); - if (ret) - return ret; - } - - if (!IS_I830(dev) && !IS_845G(dev)) { - BEGIN_LP_RING(2); - if (IS_I965G(dev)) { - OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); - OUT_RING(batch->start); - } else { - OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); - OUT_RING(batch->start | MI_BATCH_NON_SECURE); - } - ADVANCE_LP_RING(); - } else { - BEGIN_LP_RING(4); - OUT_RING(MI_BATCH_BUFFER); - OUT_RING(batch->start | MI_BATCH_NON_SECURE); - OUT_RING(batch->start + batch->used - 4); - OUT_RING(0); - ADVANCE_LP_RING(); - } - } - - i915_emit_breadcrumb(dev); - - return 0; -} - -static int i915_dispatch_flip(struct drm_device * dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - RING_LOCALS; - - if (!dev_priv->sarea_priv) - return -EINVAL; - - DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", - __func__, - dev_priv->current_page, - dev_priv->sarea_priv->pf_current_page); - - i915_kernel_lost_context(dev); - - BEGIN_LP_RING(2); - OUT_RING(MI_FLUSH | MI_READ_FLUSH); - OUT_RING(0); - ADVANCE_LP_RING(); - - BEGIN_LP_RING(6); - OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); - OUT_RING(0); - if (dev_priv->current_page == 0) { - OUT_RING(dev_priv->back_offset); - dev_priv->current_page = 1; - } else { - OUT_RING(dev_priv->front_offset); - dev_priv->current_page = 0; - } - OUT_RING(0); - ADVANCE_LP_RING(); - - BEGIN_LP_RING(2); - OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); - OUT_RING(0); - ADVANCE_LP_RING(); - - dev_priv->sarea_priv->last_enqueue = dev_priv->counter++; - - BEGIN_LP_RING(4); - OUT_RING(MI_STORE_DWORD_INDEX); - OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); - OUT_RING(dev_priv->counter); - OUT_RING(0); - ADVANCE_LP_RING(); - - dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; - return 0; -} - -static int i915_quiescent(struct drm_device * dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - - i915_kernel_lost_context(dev); - return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__); -} - -static int i915_flush_ioctl(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - int ret; - - RING_LOCK_TEST_WITH_RETURN(dev, file_priv); - - ret = i915_quiescent(dev); - - return ret; -} - -static int i915_batchbuffer(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) - dev_priv->sarea_priv; - drm_i915_batchbuffer_t *batch = data; - size_t cliplen; - int ret; - - if (!dev_priv->allow_batchbuffer) { - DRM_ERROR("Batchbuffer ioctl disabled\n"); - return -EINVAL; - } - - DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n", - batch->start, batch->used, batch->num_cliprects); - - RING_LOCK_TEST_WITH_RETURN(dev, file_priv); - - DRM_UNLOCK(); - cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect); - if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects, - cliplen)) { - DRM_LOCK(); - return -EFAULT; - } - if (batch->num_cliprects) { - ret = vslock(batch->cliprects, cliplen); - if (ret) { - DRM_ERROR("Fault wiring cliprects\n"); - DRM_LOCK(); - return -EFAULT; - } - } - DRM_LOCK(); - - ret = i915_dispatch_batchbuffer(dev, batch); - - if (sarea_priv) - sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); - - DRM_UNLOCK(); - if (batch->num_cliprects) - vsunlock(batch->cliprects, cliplen); - DRM_LOCK(); - - return ret; -} - -static int i915_cmdbuffer(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) - dev_priv->sarea_priv; - drm_i915_cmdbuffer_t *cmdbuf = data; - size_t cliplen; - int ret; - - DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n", - cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); - - RING_LOCK_TEST_WITH_RETURN(dev, file_priv); - - DRM_UNLOCK(); - cliplen = cmdbuf->num_cliprects * sizeof(struct drm_clip_rect); - if (cmdbuf->num_cliprects && DRM_VERIFYAREA_READ(cmdbuf->cliprects, - cliplen)) { - DRM_ERROR("Fault accessing cliprects\n"); - DRM_LOCK(); - return -EFAULT; - } - if (cmdbuf->num_cliprects) { - ret = vslock(cmdbuf->cliprects, cliplen); - if (ret) { - DRM_ERROR("Fault wiring cliprects\n"); - DRM_LOCK(); - return -EFAULT; - } - ret = vslock(cmdbuf->buf, cmdbuf->sz); - if (ret) { - vsunlock(cmdbuf->cliprects, cliplen); - DRM_ERROR("Fault wiring cmds\n"); - DRM_LOCK(); - return -EFAULT; - } - } - DRM_LOCK(); - - ret = i915_dispatch_cmdbuffer(dev, cmdbuf); - DRM_UNLOCK(); - if (cmdbuf->num_cliprects) { - vsunlock(cmdbuf->buf, cmdbuf->sz); - vsunlock(cmdbuf->cliprects, cliplen); - } - DRM_LOCK(); - if (ret) { - DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); - return ret; - } - - if (sarea_priv) - sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); - return 0; -} - -static int i915_flip_bufs(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - int ret; - - DRM_DEBUG("%s\n", __func__); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - ret = i915_dispatch_flip(dev); - - return ret; -} - -static int i915_getparam(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_getparam_t *param = data; - int value; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - switch (param->param) { - case I915_PARAM_IRQ_ACTIVE: - value = dev->irq_enabled ? 1 : 0; - break; - case I915_PARAM_ALLOW_BATCHBUFFER: - value = dev_priv->allow_batchbuffer ? 1 : 0; - break; - case I915_PARAM_LAST_DISPATCH: - value = READ_BREADCRUMB(dev_priv); - break; - case I915_PARAM_CHIPSET_ID: - value = dev->pci_device; - break; - case I915_PARAM_HAS_GEM: - value = 0; - break; - default: - DRM_ERROR("Unknown parameter %d\n", param->param); - return -EINVAL; - } - - if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { - DRM_ERROR("DRM_COPY_TO_USER failed\n"); - return -EFAULT; - } - - return 0; -} - -static int i915_setparam(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_setparam_t *param = data; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - switch (param->param) { - case I915_SETPARAM_USE_MI_BATCHBUFFER_START: - break; - case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: - dev_priv->tex_lru_log_granularity = param->value; - break; - case I915_SETPARAM_ALLOW_BATCHBUFFER: - dev_priv->allow_batchbuffer = param->value; - break; - default: - DRM_ERROR("unknown parameter %d\n", param->param); - return -EINVAL; - } - - return 0; -} - -static int i915_set_status_page(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_hws_addr_t *hws = data; - - if (!I915_NEED_GFX_HWS(dev)) - return -EINVAL; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr); - - dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); - - dev_priv->hws_map.offset = dev->agp->base + hws->addr; - dev_priv->hws_map.size = 4*1024; - dev_priv->hws_map.type = 0; - dev_priv->hws_map.flags = 0; - dev_priv->hws_map.mtrr = 0; - - drm_core_ioremap(&dev_priv->hws_map, dev); - if (dev_priv->hws_map.handle == NULL) { - i915_dma_cleanup(dev); - dev_priv->status_gfx_addr = 0; - DRM_ERROR("can not ioremap virtual address for" - " G33 hw status page\n"); - return -ENOMEM; - } - dev_priv->hw_status_page = dev_priv->hws_map.handle; - - memset(dev_priv->hw_status_page, 0, PAGE_SIZE); - I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); - DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n", - dev_priv->status_gfx_addr); - DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page); - return 0; -} - -int i915_driver_load(struct drm_device *dev, unsigned long flags) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - unsigned long base, size; - int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1; - - /* i915 has 4 more counters */ - dev->counters += 4; - dev->types[6] = _DRM_STAT_IRQ; - dev->types[7] = _DRM_STAT_PRIMARY; - dev->types[8] = _DRM_STAT_SECONDARY; - dev->types[9] = _DRM_STAT_DMA; - - dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER); - if (dev_priv == NULL) - return -ENOMEM; - - memset(dev_priv, 0, sizeof(drm_i915_private_t)); - - dev->dev_private = (void *)dev_priv; - dev_priv->dev = dev; - - /* Add register map (needed for suspend/resume) */ - base = drm_get_resource_start(dev, mmio_bar); - size = drm_get_resource_len(dev, mmio_bar); - - ret = drm_addmap(dev, base, size, _DRM_REGISTERS, - _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map); - - if (IS_GM45(dev)) - dev->driver->get_vblank_counter = gm45_get_vblank_counter; - else - dev->driver->get_vblank_counter = i915_get_vblank_counter; - -#ifdef I915_HAVE_GEM - i915_gem_load(dev); -#endif - /* Init HWS */ - if (!I915_NEED_GFX_HWS(dev)) { - ret = i915_init_phys_hws(dev); - if (ret != 0) - return ret; - } -#ifdef __linux__ - /* On the 945G/GM, the chipset reports the MSI capability on the - * integrated graphics even though the support isn't actually there - * according to the published specs. It doesn't appear to function - * correctly in testing on 945G. - * This may be a side effect of MSI having been made available for PEG - * and the registers being closely associated. - * - * According to chipset errata, on the 965GM, MSI interrupts may - * be lost or delayed - */ - if (!IS_I945G(dev) && !IS_I945GM(dev) && !IS_I965GM(dev)) - if (pci_enable_msi(dev->pdev)) - DRM_ERROR("failed to enable MSI\n"); - - intel_opregion_init(dev); -#endif - DRM_SPININIT(&dev_priv->user_irq_lock, "userirq"); - - ret = drm_vblank_init(dev, I915_NUM_PIPE); - - if (ret) { - (void) i915_driver_unload(dev); - return ret; - } - - return ret; -} - -int i915_driver_unload(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - - i915_free_hws(dev); - - drm_rmmap(dev, dev_priv->mmio_map); -#ifdef __linux__ - intel_opregion_free(dev); -#endif - DRM_SPINUNINIT(&dev_priv->user_irq_lock); - - drm_free(dev->dev_private, sizeof(drm_i915_private_t), - DRM_MEM_DRIVER); - - return 0; -} - -int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) -{ - struct drm_i915_file_private *i915_file_priv; - - DRM_DEBUG("\n"); - i915_file_priv = (struct drm_i915_file_private *) - drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES); - - if (!i915_file_priv) - return -ENOMEM; - - file_priv->driver_priv = i915_file_priv; - - i915_file_priv->mm.last_gem_seqno = 0; - i915_file_priv->mm.last_gem_throttle_seqno = 0; - - return 0; -} - -void i915_driver_lastclose(struct drm_device * dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - - if (!dev_priv) - return; -#ifdef I915_HAVE_GEM - i915_gem_lastclose(dev); -#endif - if (dev_priv->agp_heap) - i915_mem_takedown(&(dev_priv->agp_heap)); - - i915_dma_cleanup(dev); -} - -void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - i915_mem_release(dev, file_priv, dev_priv->agp_heap); -} - -void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) -{ - struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; - - drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES); -} - -struct drm_ioctl_desc i915_ioctls[] = { - DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), - DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), - DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), - DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), - DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), - DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), - DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH), - DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH), - DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), - DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), - DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), - DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), - DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), - DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), -#ifdef I915_HAVE_GEM - DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), - DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH), - DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH), - DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0), - DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0), - DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0), - DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0), - DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0), - DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0), - DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0), - DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0), -#endif -}; - -int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); - -/** - * Determine if the device really is AGP or not. - * - * All Intel graphics chipsets are treated as AGP, even if they are really - * PCI-e. - * - * \param dev The device to be tested. - * - * \returns - * A value of 1 is always retured to indictate every i9x5 is AGP. - */ -int i915_driver_device_is_agp(struct drm_device * dev) -{ - return 1; -} diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h deleted file mode 100644 index 0132e55e..00000000 --- a/shared-core/i915_drm.h +++ /dev/null @@ -1,817 +0,0 @@ -/* - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _I915_DRM_H_ -#define _I915_DRM_H_ - -/* Please note that modifications to all structs defined here are - * subject to backwards-compatibility constraints. - */ - -#include "drm.h" - -/* Each region is a minimum of 16k, and there are at most 255 of them. - */ -#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use - * of chars for next/prev indices */ -#define I915_LOG_MIN_TEX_REGION_SIZE 14 - -typedef struct _drm_i915_init { - enum { - I915_INIT_DMA = 0x01, - I915_CLEANUP_DMA = 0x02, - I915_RESUME_DMA = 0x03, - - /* Since this struct isn't versioned, just used a new - * 'func' code to indicate the presence of dri2 sarea - * info. */ - I915_INIT_DMA2 = 0x04 - } func; - unsigned int mmio_offset; - int sarea_priv_offset; - unsigned int ring_start; - unsigned int ring_end; - unsigned int ring_size; - unsigned int front_offset; - unsigned int back_offset; - unsigned int depth_offset; - unsigned int w; - unsigned int h; - unsigned int pitch; - unsigned int pitch_bits; - unsigned int back_pitch; - unsigned int depth_pitch; - unsigned int cpp; - unsigned int chipset; - unsigned int sarea_handle; -} drm_i915_init_t; - -typedef struct drm_i915_sarea { - struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; - int last_upload; /* last time texture was uploaded */ - int last_enqueue; /* last time a buffer was enqueued */ - int last_dispatch; /* age of the most recently dispatched buffer */ - int ctxOwner; /* last context to upload state */ - int texAge; - int pf_enabled; /* is pageflipping allowed? */ - int pf_active; - int pf_current_page; /* which buffer is being displayed? */ - int perf_boxes; /* performance boxes to be displayed */ - int width, height; /* screen size in pixels */ - - drm_handle_t front_handle; - int front_offset; - int front_size; - - drm_handle_t back_handle; - int back_offset; - int back_size; - - drm_handle_t depth_handle; - int depth_offset; - int depth_size; - - drm_handle_t tex_handle; - int tex_offset; - int tex_size; - int log_tex_granularity; - int pitch; - int rotation; /* 0, 90, 180 or 270 */ - int rotated_offset; - int rotated_size; - int rotated_pitch; - int virtualX, virtualY; - - unsigned int front_tiled; - unsigned int back_tiled; - unsigned int depth_tiled; - unsigned int rotated_tiled; - unsigned int rotated2_tiled; - - /* compat defines for the period of time when pipeA_* got renamed - * to planeA_*. They mean pipe, really. - */ -#define planeA_x pipeA_x -#define planeA_y pipeA_y -#define planeA_w pipeA_w -#define planeA_h pipeA_h -#define planeB_x pipeB_x -#define planeB_y pipeB_y -#define planeB_w pipeB_w -#define planeB_h pipeB_h - int pipeA_x; - int pipeA_y; - int pipeA_w; - int pipeA_h; - int pipeB_x; - int pipeB_y; - int pipeB_w; - int pipeB_h; - - /* Triple buffering */ - drm_handle_t third_handle; - int third_offset; - int third_size; - unsigned int third_tiled; - - /* buffer object handles for the static buffers. May change - * over the lifetime of the client, though it doesn't in our current - * implementation. - */ - unsigned int front_bo_handle; - unsigned int back_bo_handle; - unsigned int third_bo_handle; - unsigned int depth_bo_handle; -} drm_i915_sarea_t; - -/* Driver specific fence types and classes. - */ - -/* The only fence class we support */ -#define DRM_I915_FENCE_CLASS_ACCEL 0 -/* Fence type that guarantees read-write flush */ -#define DRM_I915_FENCE_TYPE_RW 2 -/* MI_FLUSH programmed just before the fence */ -#define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000 - -/* Flags for perf_boxes - */ -#define I915_BOX_RING_EMPTY 0x1 -#define I915_BOX_FLIP 0x2 -#define I915_BOX_WAIT 0x4 -#define I915_BOX_TEXTURE_LOAD 0x8 -#define I915_BOX_LOST_CONTEXT 0x10 - -/* I915 specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ -#define DRM_I915_INIT 0x00 -#define DRM_I915_FLUSH 0x01 -#define DRM_I915_FLIP 0x02 -#define DRM_I915_BATCHBUFFER 0x03 -#define DRM_I915_IRQ_EMIT 0x04 -#define DRM_I915_IRQ_WAIT 0x05 -#define DRM_I915_GETPARAM 0x06 -#define DRM_I915_SETPARAM 0x07 -#define DRM_I915_ALLOC 0x08 -#define DRM_I915_FREE 0x09 -#define DRM_I915_INIT_HEAP 0x0a -#define DRM_I915_CMDBUFFER 0x0b -#define DRM_I915_DESTROY_HEAP 0x0c -#define DRM_I915_SET_VBLANK_PIPE 0x0d -#define DRM_I915_GET_VBLANK_PIPE 0x0e -#define DRM_I915_VBLANK_SWAP 0x0f -#define DRM_I915_MMIO 0x10 -#define DRM_I915_HWS_ADDR 0x11 -#define DRM_I915_EXECBUFFER 0x12 -#define DRM_I915_GEM_INIT 0x13 -#define DRM_I915_GEM_EXECBUFFER 0x14 -#define DRM_I915_GEM_PIN 0x15 -#define DRM_I915_GEM_UNPIN 0x16 -#define DRM_I915_GEM_BUSY 0x17 -#define DRM_I915_GEM_THROTTLE 0x18 -#define DRM_I915_GEM_ENTERVT 0x19 -#define DRM_I915_GEM_LEAVEVT 0x1a -#define DRM_I915_GEM_CREATE 0x1b -#define DRM_I915_GEM_PREAD 0x1c -#define DRM_I915_GEM_PWRITE 0x1d -#define DRM_I915_GEM_MMAP 0x1e -#define DRM_I915_GEM_SET_DOMAIN 0x1f -#define DRM_I915_GEM_SW_FINISH 0x20 -#define DRM_I915_GEM_SET_TILING 0x21 -#define DRM_I915_GEM_GET_TILING 0x22 -#define DRM_I915_GEM_GET_APERTURE 0x23 -#define DRM_I915_GEM_MMAP_GTT 0x24 -#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 -#define DRM_I915_GEM_MADVISE 0x26 -#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 -#define DRM_I915_OVERLAY_ATTRS 0x28 - -#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) -#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) -#define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t) -#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) -#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) -#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) -#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) -#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) -#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) -#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) -#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) -#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) -#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) -#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) -#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) -#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) -#define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio) -#define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer) -#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) -#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) -#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) -#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) -#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) -#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) -#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) -#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) -#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) -#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) -#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) -#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) -#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) -#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) -#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) -#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) -#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) -#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) -#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) -#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) -#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image) -#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) - -/* Asynchronous page flipping: - */ -typedef struct drm_i915_flip { - /* - * This is really talking about planes, and we could rename it - * except for the fact that some of the duplicated i915_drm.h files - * out there check for HAVE_I915_FLIP and so might pick up this - * version. - */ - int pipes; -} drm_i915_flip_t; - -/* Allow drivers to submit batchbuffers directly to hardware, relying - * on the security mechanisms provided by hardware. - */ -typedef struct drm_i915_batchbuffer { - int start; /* agp offset */ - int used; /* nr bytes in use */ - int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ - int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ - int num_cliprects; /* mulitpass with multiple cliprects? */ - struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ -} drm_i915_batchbuffer_t; - -/* As above, but pass a pointer to userspace buffer which can be - * validated by the kernel prior to sending to hardware. - */ -typedef struct _drm_i915_cmdbuffer { - char __user *buf; /* pointer to userspace command buffer */ - int sz; /* nr bytes in buf */ - int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ - int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ - int num_cliprects; /* mulitpass with multiple cliprects? */ - struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ -} drm_i915_cmdbuffer_t; - -/* Userspace can request & wait on irq's: - */ -typedef struct drm_i915_irq_emit { - int __user *irq_seq; -} drm_i915_irq_emit_t; - -typedef struct drm_i915_irq_wait { - int irq_seq; -} drm_i915_irq_wait_t; - -/* Ioctl to query kernel params: - */ -#define I915_PARAM_IRQ_ACTIVE 1 -#define I915_PARAM_ALLOW_BATCHBUFFER 2 -#define I915_PARAM_LAST_DISPATCH 3 -#define I915_PARAM_CHIPSET_ID 4 -#define I915_PARAM_HAS_GEM 5 -#define I915_PARAM_NUM_FENCES_AVAIL 6 -#define I915_PARAM_HAS_OVERLAY 7 - -typedef struct drm_i915_getparam { - int param; - int __user *value; -} drm_i915_getparam_t; - -/* Ioctl to set kernel params: - */ -#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 -#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 -#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 -#define I915_SETPARAM_NUM_USED_FENCES 4 - -typedef struct drm_i915_setparam { - int param; - int value; -} drm_i915_setparam_t; - -/* A memory manager for regions of shared memory: - */ -#define I915_MEM_REGION_AGP 1 - -typedef struct drm_i915_mem_alloc { - int region; - int alignment; - int size; - int __user *region_offset; /* offset from start of fb or agp */ -} drm_i915_mem_alloc_t; - -typedef struct drm_i915_mem_free { - int region; - int region_offset; -} drm_i915_mem_free_t; - -typedef struct drm_i915_mem_init_heap { - int region; - int size; - int start; -} drm_i915_mem_init_heap_t; - -/* Allow memory manager to be torn down and re-initialized (eg on - * rotate): - */ -typedef struct drm_i915_mem_destroy_heap { - int region; -} drm_i915_mem_destroy_heap_t; - -/* Allow X server to configure which pipes to monitor for vblank signals - */ -#define DRM_I915_VBLANK_PIPE_A 1 -#define DRM_I915_VBLANK_PIPE_B 2 - -typedef struct drm_i915_vblank_pipe { - int pipe; -} drm_i915_vblank_pipe_t; - -/* Schedule buffer swap at given vertical blank: - */ -typedef struct drm_i915_vblank_swap { - drm_drawable_t drawable; - enum drm_vblank_seq_type seqtype; - unsigned int sequence; -} drm_i915_vblank_swap_t; - -#define I915_MMIO_READ 0 -#define I915_MMIO_WRITE 1 - -#define I915_MMIO_MAY_READ 0x1 -#define I915_MMIO_MAY_WRITE 0x2 - -#define MMIO_REGS_IA_PRIMATIVES_COUNT 0 -#define MMIO_REGS_IA_VERTICES_COUNT 1 -#define MMIO_REGS_VS_INVOCATION_COUNT 2 -#define MMIO_REGS_GS_PRIMITIVES_COUNT 3 -#define MMIO_REGS_GS_INVOCATION_COUNT 4 -#define MMIO_REGS_CL_PRIMITIVES_COUNT 5 -#define MMIO_REGS_CL_INVOCATION_COUNT 6 -#define MMIO_REGS_PS_INVOCATION_COUNT 7 -#define MMIO_REGS_PS_DEPTH_COUNT 8 - -typedef struct drm_i915_mmio_entry { - unsigned int flag; - unsigned int offset; - unsigned int size; -} drm_i915_mmio_entry_t; - -typedef struct drm_i915_mmio { - unsigned int read_write:1; - unsigned int reg:31; - void __user *data; -} drm_i915_mmio_t; - -typedef struct drm_i915_hws_addr { - uint64_t addr; -} drm_i915_hws_addr_t; - -struct drm_i915_gem_init { - /** - * Beginning offset in the GTT to be managed by the DRM memory - * manager. - */ - uint64_t gtt_start; - /** - * Ending offset in the GTT to be managed by the DRM memory - * manager. - */ - uint64_t gtt_end; -}; - -struct drm_i915_gem_create { - /** - * Requested size for the object. - * - * The (page-aligned) allocated size for the object will be returned. - */ - uint64_t size; - /** - * Returned handle for the object. - * - * Object handles are nonzero. - */ - uint32_t handle; - uint32_t pad; -}; - -struct drm_i915_gem_pread { - /** Handle for the object being read. */ - uint32_t handle; - uint32_t pad; - /** Offset into the object to read from */ - uint64_t offset; - /** Length of data to read */ - uint64_t size; - /** - * Pointer to write the data into. - * - * This is a fixed-size type for 32/64 compatibility. - */ - uint64_t data_ptr; -}; - -struct drm_i915_gem_pwrite { - /** Handle for the object being written to. */ - uint32_t handle; - uint32_t pad; - /** Offset into the object to write to */ - uint64_t offset; - /** Length of data to write */ - uint64_t size; - /** - * Pointer to read the data from. - * - * This is a fixed-size type for 32/64 compatibility. - */ - uint64_t data_ptr; -}; - -struct drm_i915_gem_mmap { - /** Handle for the object being mapped. */ - uint32_t handle; - uint32_t pad; - /** Offset in the object to map. */ - uint64_t offset; - /** - * Length of data to map. - * - * The value will be page-aligned. - */ - uint64_t size; - /** - * Returned pointer the data was mapped at. - * - * This is a fixed-size type for 32/64 compatibility. - */ - uint64_t addr_ptr; -}; - -struct drm_i915_gem_mmap_gtt { - /** Handle for the object being mapped. */ - uint32_t handle; - uint32_t pad; - /** - * Fake offset to use for subsequent mmap call - * - * This is a fixed-size type for 32/64 compatibility. - */ - uint64_t offset; -}; - -struct drm_i915_gem_set_domain { - /** Handle for the object */ - uint32_t handle; - - /** New read domains */ - uint32_t read_domains; - - /** New write domain */ - uint32_t write_domain; -}; - -struct drm_i915_gem_sw_finish { - /** Handle for the object */ - uint32_t handle; -}; - -struct drm_i915_gem_relocation_entry { - /** - * Handle of the buffer being pointed to by this relocation entry. - * - * It's appealing to make this be an index into the mm_validate_entry - * list to refer to the buffer, but this allows the driver to create - * a relocation list for state buffers and not re-write it per - * exec using the buffer. - */ - uint32_t target_handle; - - /** - * Value to be added to the offset of the target buffer to make up - * the relocation entry. - */ - uint32_t delta; - - /** Offset in the buffer the relocation entry will be written into */ - uint64_t offset; - - /** - * Offset value of the target buffer that the relocation entry was last - * written as. - * - * If the buffer has the same offset as last time, we can skip syncing - * and writing the relocation. This value is written back out by - * the execbuffer ioctl when the relocation is written. - */ - uint64_t presumed_offset; - - /** - * Target memory domains read by this operation. - */ - uint32_t read_domains; - - /** - * Target memory domains written by this operation. - * - * Note that only one domain may be written by the whole - * execbuffer operation, so that where there are conflicts, - * the application will get -EINVAL back. - */ - uint32_t write_domain; -}; - -/** @{ - * Intel memory domains - * - * Most of these just align with the various caches in - * the system and are used to flush and invalidate as - * objects end up cached in different domains. - */ -/** CPU cache */ -#define I915_GEM_DOMAIN_CPU 0x00000001 -/** Render cache, used by 2D and 3D drawing */ -#define I915_GEM_DOMAIN_RENDER 0x00000002 -/** Sampler cache, used by texture engine */ -#define I915_GEM_DOMAIN_SAMPLER 0x00000004 -/** Command queue, used to load batch buffers */ -#define I915_GEM_DOMAIN_COMMAND 0x00000008 -/** Instruction cache, used by shader programs */ -#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 -/** Vertex address cache */ -#define I915_GEM_DOMAIN_VERTEX 0x00000020 -/** GTT domain - aperture and scanout */ -#define I915_GEM_DOMAIN_GTT 0x00000040 -/** @} */ - -struct drm_i915_gem_exec_object { - /** - * User's handle for a buffer to be bound into the GTT for this - * operation. - */ - uint32_t handle; - - /** Number of relocations to be performed on this buffer */ - uint32_t relocation_count; - /** - * Pointer to array of struct drm_i915_gem_relocation_entry containing - * the relocations to be performed in this buffer. - */ - uint64_t relocs_ptr; - - /** Required alignment in graphics aperture */ - uint64_t alignment; - - /** - * Returned value of the updated offset of the object, for future - * presumed_offset writes. - */ - uint64_t offset; -}; - -struct drm_i915_gem_execbuffer { - /** - * List of buffers to be validated with their relocations to be - * performend on them. - * - * This is a pointer to an array of struct drm_i915_gem_validate_entry. - * - * These buffers must be listed in an order such that all relocations - * a buffer is performing refer to buffers that have already appeared - * in the validate list. - */ - uint64_t buffers_ptr; - uint32_t buffer_count; - - /** Offset in the batchbuffer to start execution from. */ - uint32_t batch_start_offset; - /** Bytes used in batchbuffer from batch_start_offset */ - uint32_t batch_len; - uint32_t DR1; - uint32_t DR4; - uint32_t num_cliprects; - /** This is a struct drm_clip_rect *cliprects */ - uint64_t cliprects_ptr; -}; - -struct drm_i915_gem_pin { - /** Handle of the buffer to be pinned. */ - uint32_t handle; - uint32_t pad; - - /** alignment required within the aperture */ - uint64_t alignment; - - /** Returned GTT offset of the buffer. */ - uint64_t offset; -}; - -struct drm_i915_gem_unpin { - /** Handle of the buffer to be unpinned. */ - uint32_t handle; - uint32_t pad; -}; - -struct drm_i915_gem_busy { - /** Handle of the buffer to check for busy */ - uint32_t handle; - - /** Return busy status (1 if busy, 0 if idle) */ - uint32_t busy; -}; - -#define I915_TILING_NONE 0 -#define I915_TILING_X 1 -#define I915_TILING_Y 2 - -#define I915_BIT_6_SWIZZLE_NONE 0 -#define I915_BIT_6_SWIZZLE_9 1 -#define I915_BIT_6_SWIZZLE_9_10 2 -#define I915_BIT_6_SWIZZLE_9_11 3 -#define I915_BIT_6_SWIZZLE_9_10_11 4 -/* Not seen by userland */ -#define I915_BIT_6_SWIZZLE_UNKNOWN 5 - -struct drm_i915_gem_set_tiling { - /** Handle of the buffer to have its tiling state updated */ - uint32_t handle; - - /** - * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, - * I915_TILING_Y). - * - * This value is to be set on request, and will be updated by the - * kernel on successful return with the actual chosen tiling layout. - * - * The tiling mode may be demoted to I915_TILING_NONE when the system - * has bit 6 swizzling that can't be managed correctly by GEM. - * - * Buffer contents become undefined when changing tiling_mode. - */ - uint32_t tiling_mode; - - /** - * Stride in bytes for the object when in I915_TILING_X or - * I915_TILING_Y. - */ - uint32_t stride; - - /** - * Returned address bit 6 swizzling required for CPU access through - * mmap mapping. - */ - uint32_t swizzle_mode; -}; - -struct drm_i915_gem_get_tiling { - /** Handle of the buffer to get tiling state for. */ - uint32_t handle; - - /** - * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, - * I915_TILING_Y). - */ - uint32_t tiling_mode; - - /** - * Returned address bit 6 swizzling required for CPU access through - * mmap mapping. - */ - uint32_t swizzle_mode; -}; - -struct drm_i915_gem_get_aperture { - /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ - uint64_t aper_size; - - /** - * Available space in the aperture used by i915_gem_execbuffer, in - * bytes - */ - uint64_t aper_available_size; -}; - -struct drm_i915_get_pipe_from_crtc_id { - /** ID of CRTC being requested **/ - uint32_t crtc_id; - - /** pipe of requested CRTC **/ - uint32_t pipe; -}; - -#define I915_MADV_WILLNEED 0 -#define I915_MADV_DONTNEED 1 - -struct drm_i915_gem_madvise { - /** Handle of the buffer to change the backing store advice. */ - uint32_t handle; - - /** Advice. */ - uint32_t madv; - - /** Whether or not the backing store still exists */ - uint32_t retained; -}; - -/* flags */ -#define I915_OVERLAY_TYPE_MASK 0xff -#define I915_OVERLAY_YUV_PLANAR 0x01 -#define I915_OVERLAY_YUV_PACKED 0x02 -#define I915_OVERLAY_RGB 0x03 - -#define I915_OVERLAY_DEPTH_MASK 0xff00 -#define I915_OVERLAY_RGB24 0x1000 -#define I915_OVERLAY_RGB16 0x2000 -#define I915_OVERLAY_RGB15 0x3000 -#define I915_OVERLAY_YUV422 0x0100 -#define I915_OVERLAY_YUV411 0x0200 -#define I915_OVERLAY_YUV420 0x0300 -#define I915_OVERLAY_YUV410 0x0400 - -#define I915_OVERLAY_SWAP_MASK 0xff0000 -#define I915_OVERLAY_NO_SWAP 0x000000 -#define I915_OVERLAY_UV_SWAP 0x010000 -#define I915_OVERLAY_Y_SWAP 0x020000 -#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 - -#define I915_OVERLAY_FLAGS_MASK 0xff000000 -#define I915_OVERLAY_ENABLE 0x01000000 - -struct drm_intel_overlay_put_image { - /* various flags and src format description */ - uint32_t flags; - /* source picture description */ - uint32_t bo_handle; - /* stride values and offsets are in bytes, buffer relative */ - uint16_t stride_Y; /* stride for packed formats */ - uint16_t stride_UV; - uint32_t offset_Y; /* offset for packet formats */ - uint32_t offset_U; - uint32_t offset_V; - /* in pixels */ - uint16_t src_width; - uint16_t src_height; - /* to compensate the scaling factors for partially covered surfaces */ - uint16_t src_scan_width; - uint16_t src_scan_height; - /* output crtc description */ - uint32_t crtc_id; - uint16_t dst_x; - uint16_t dst_y; - uint16_t dst_width; - uint16_t dst_height; -}; - -/* flags */ -#define I915_OVERLAY_UPDATE_ATTRS (1<<0) -#define I915_OVERLAY_UPDATE_GAMMA (1<<1) -struct drm_intel_overlay_attrs { - uint32_t flags; - uint32_t color_key; - int32_t brightness; - uint32_t contrast; - uint32_t saturation; - uint32_t gamma0; - uint32_t gamma1; - uint32_t gamma2; - uint32_t gamma3; - uint32_t gamma4; - uint32_t gamma5; -}; - -#endif /* _I915_DRM_H_ */ diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h deleted file mode 100644 index 6185bcbf..00000000 --- a/shared-core/i915_drv.h +++ /dev/null @@ -1,667 +0,0 @@ -/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- - */ -/* - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _I915_DRV_H_ -#define _I915_DRV_H_ - -#include "i915_reg.h" - -/* General customization: - */ - -#define DRIVER_AUTHOR "Tungsten Graphics, Inc." - -#define DRIVER_NAME "i915" -#define DRIVER_DESC "Intel Graphics" -#define DRIVER_DATE "20080730" - -enum pipe { - PIPE_A = 0, - PIPE_B, -}; - -#define I915_NUM_PIPE 2 - -/* Interface history: - * - * 1.1: Original. - * 1.2: Add Power Management - * 1.3: Add vblank support - * 1.4: Fix cmdbuffer path, add heap destroy - * 1.5: Add vblank pipe configuration - * 1.6: - New ioctl for scheduling buffer swaps on vertical blank - * - Support vertical blank on secondary display pipe - */ -#define DRIVER_MAJOR 1 -#define DRIVER_MINOR 6 -#define DRIVER_PATCHLEVEL 0 - -#define WATCH_COHERENCY 0 -#define WATCH_BUF 0 -#define WATCH_EXEC 0 -#define WATCH_LRU 0 -#define WATCH_RELOC 0 -#define WATCH_INACTIVE 0 -#define WATCH_PWRITE 0 - -typedef struct _drm_i915_ring_buffer { - int tail_mask; - unsigned long Size; - u8 *virtual_start; - int head; - int tail; - int space; - drm_local_map_t map; - struct drm_gem_object *ring_obj; -} drm_i915_ring_buffer_t; - -struct mem_block { - struct mem_block *next; - struct mem_block *prev; - int start; - int size; - struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ -}; - -struct opregion_header; -struct opregion_acpi; -struct opregion_swsci; -struct opregion_asle; - -struct intel_opregion { - struct opregion_header *header; - struct opregion_acpi *acpi; - struct opregion_swsci *swsci; - struct opregion_asle *asle; - int enabled; -}; - -typedef struct drm_i915_private { - struct drm_device *dev; - - drm_local_map_t *sarea; - drm_local_map_t *mmio_map; - - drm_i915_sarea_t *sarea_priv; - drm_i915_ring_buffer_t ring; - - drm_dma_handle_t *status_page_dmah; - void *hw_status_page; - dma_addr_t dma_status_page; - uint32_t counter; - unsigned int status_gfx_addr; - drm_local_map_t hws_map; - struct drm_gem_object *hws_obj; - - unsigned int cpp; - int back_offset; - int front_offset; - int current_page; - int page_flipping; - - wait_queue_head_t irq_queue; - atomic_t irq_received; - /** Protects user_irq_refcount and irq_mask_reg */ - DRM_SPINTYPE user_irq_lock; - /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ - int user_irq_refcount; - /** Cached value of IER to avoid reads in updating the bitfield */ - u32 irq_mask_reg; - u32 pipestat[2]; - - int tex_lru_log_granularity; - int allow_batchbuffer; - struct mem_block *agp_heap; - unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; - int vblank_pipe; - - struct intel_opregion opregion; - - /* Register state */ - u8 saveLBB; - u32 saveDSPACNTR; - u32 saveDSPBCNTR; - u32 saveDSPARB; - u32 savePIPEACONF; - u32 savePIPEBCONF; - u32 savePIPEASRC; - u32 savePIPEBSRC; - u32 saveFPA0; - u32 saveFPA1; - u32 saveDPLL_A; - u32 saveDPLL_A_MD; - u32 saveHTOTAL_A; - u32 saveHBLANK_A; - u32 saveHSYNC_A; - u32 saveVTOTAL_A; - u32 saveVBLANK_A; - u32 saveVSYNC_A; - u32 saveBCLRPAT_A; - u32 savePIPEASTAT; - u32 saveDSPASTRIDE; - u32 saveDSPASIZE; - u32 saveDSPAPOS; - u32 saveDSPAADDR; - u32 saveDSPASURF; - u32 saveDSPATILEOFF; - u32 savePFIT_PGM_RATIOS; - u32 saveBLC_PWM_CTL; - u32 saveBLC_PWM_CTL2; - u32 saveFPB0; - u32 saveFPB1; - u32 saveDPLL_B; - u32 saveDPLL_B_MD; - u32 saveHTOTAL_B; - u32 saveHBLANK_B; - u32 saveHSYNC_B; - u32 saveVTOTAL_B; - u32 saveVBLANK_B; - u32 saveVSYNC_B; - u32 saveBCLRPAT_B; - u32 savePIPEBSTAT; - u32 saveDSPBSTRIDE; - u32 saveDSPBSIZE; - u32 saveDSPBPOS; - u32 saveDSPBADDR; - u32 saveDSPBSURF; - u32 saveDSPBTILEOFF; - u32 saveVGA0; - u32 saveVGA1; - u32 saveVGA_PD; - u32 saveVGACNTRL; - u32 saveADPA; - u32 saveLVDS; - u32 savePP_ON_DELAYS; - u32 savePP_OFF_DELAYS; - u32 saveDVOA; - u32 saveDVOB; - u32 saveDVOC; - u32 savePP_ON; - u32 savePP_OFF; - u32 savePP_CONTROL; - u32 savePP_DIVISOR; - u32 savePFIT_CONTROL; - u32 save_palette_a[256]; - u32 save_palette_b[256]; - u32 saveFBC_CFB_BASE; - u32 saveFBC_LL_BASE; - u32 saveFBC_CONTROL; - u32 saveFBC_CONTROL2; - u32 saveIER; - u32 saveIIR; - u32 saveIMR; - u32 saveCACHE_MODE_0; - u32 saveD_STATE; - u32 saveCG_2D_DIS; - u32 saveMI_ARB_STATE; - u32 saveSWF0[16]; - u32 saveSWF1[16]; - u32 saveSWF2[3]; - u8 saveMSR; - u8 saveSR[8]; - u8 saveGR[25]; - u8 saveAR_INDEX; - u8 saveAR[21]; - u8 saveDACMASK; - u8 saveDACDATA[256*3]; /* 256 3-byte colors */ - u8 saveCR[37]; - struct { -#ifdef __linux__ - struct drm_mm gtt_space; -#endif - /** - * List of objects currently involved in rendering from the - * ringbuffer. - * - * A reference is held on the buffer while on this list. - */ - struct list_head active_list; - - /** - * List of objects which are not in the ringbuffer but which - * still have a write_domain which needs to be flushed before - * unbinding. - * - * A reference is held on the buffer while on this list. - */ - struct list_head flushing_list; - - /** - * LRU list of objects which are not in the ringbuffer and - * are ready to unbind, but are still in the GTT. - * - * A reference is not held on the buffer while on this list, - * as merely being GTT-bound shouldn't prevent its being - * freed, and we'll pull it off the list in the free path. - */ - struct list_head inactive_list; - - /** - * List of breadcrumbs associated with GPU requests currently - * outstanding. - */ - struct list_head request_list; -#ifdef __linux__ - /** - * We leave the user IRQ off as much as possible, - * but this means that requests will finish and never - * be retired once the system goes idle. Set a timer to - * fire periodically while the ring is running. When it - * fires, go retire requests. - */ - struct delayed_work retire_work; -#endif - uint32_t next_gem_seqno; - - /** - * Waiting sequence number, if any - */ - uint32_t waiting_gem_seqno; - - /** - * Last seq seen at irq time - */ - uint32_t irq_gem_seqno; - - /** - * Flag if the X Server, and thus DRM, is not currently in - * control of the device. - * - * This is set between LeaveVT and EnterVT. It needs to be - * replaced with a semaphore. It also needs to be - * transitioned away from for kernel modesetting. - */ - int suspended; - - /** - * Flag if the hardware appears to be wedged. - * - * This is set when attempts to idle the device timeout. - * It prevents command submission from occuring and makes - * every pending request fail - */ - int wedged; - - /** Bit 6 swizzling required for X tiling */ - uint32_t bit_6_swizzle_x; - /** Bit 6 swizzling required for Y tiling */ - uint32_t bit_6_swizzle_y; - } mm; -} drm_i915_private_t; - -enum intel_chip_family { - CHIP_I8XX = 0x01, - CHIP_I9XX = 0x02, - CHIP_I915 = 0x04, - CHIP_I965 = 0x08, -}; - -/** driver private structure attached to each drm_gem_object */ -struct drm_i915_gem_object { - struct drm_gem_object *obj; - - /** Current space allocated to this object in the GTT, if any. */ - struct drm_mm_node *gtt_space; - - /** This object's place on the active/flushing/inactive lists */ - struct list_head list; - - /** - * This is set if the object is on the active or flushing lists - * (has pending rendering), and is not set if it's on inactive (ready - * to be unbound). - */ - int active; - - /** - * This is set if the object has been written to since last bound - * to the GTT - */ - int dirty; - - /** AGP memory structure for our GTT binding. */ - DRM_AGP_MEM *agp_mem; - - struct page **page_list; - - /** - * Current offset of the object in GTT space. - * - * This is the same as gtt_space->start - */ - uint32_t gtt_offset; - - /** Boolean whether this object has a valid gtt offset. */ - int gtt_bound; - - /** How many users have pinned this object in GTT space */ - int pin_count; - - /** Breadcrumb of last rendering to the buffer. */ - uint32_t last_rendering_seqno; - - /** Current tiling mode for the object. */ - uint32_t tiling_mode; - - /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ - uint32_t agp_type; - - /** - * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when - * GEM_DOMAIN_CPU is not in the object's read domain. - */ - uint8_t *page_cpu_valid; -}; - -/** - * Request queue structure. - * - * The request queue allows us to note sequence numbers that have been emitted - * and may be associated with active buffers to be retired. - * - * By keeping this list, we can avoid having to do questionable - * sequence-number comparisons on buffer last_rendering_seqnos, and associate - * an emission time with seqnos for tracking how far ahead of the GPU we are. - */ -struct drm_i915_gem_request { - /** GEM sequence number associated with this request. */ - uint32_t seqno; - - /** Time at which this request was emitted, in jiffies. */ - unsigned long emitted_jiffies; - - /** Cache domains that were flushed at the start of the request. */ - uint32_t flush_domains; - - struct list_head list; -}; - -struct drm_i915_file_private { - struct { - uint32_t last_gem_seqno; - uint32_t last_gem_throttle_seqno; - } mm; -}; - -extern struct drm_ioctl_desc i915_ioctls[]; -extern int i915_max_ioctl; - - /* i915_dma.c */ -extern void i915_kernel_lost_context(struct drm_device * dev); -extern int i915_driver_load(struct drm_device *, unsigned long flags); -extern int i915_driver_unload(struct drm_device *); -extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); -extern void i915_driver_lastclose(struct drm_device * dev); -extern void i915_driver_preclose(struct drm_device *dev, - struct drm_file *file_priv); -extern void i915_driver_postclose(struct drm_device *dev, - struct drm_file *file_priv); -extern int i915_driver_device_is_agp(struct drm_device * dev); -extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, - unsigned long arg); -extern int i915_emit_box(struct drm_device *dev, - struct drm_clip_rect __user *boxes, - int i, int DR1, int DR4); - -/* i915_irq.c */ -extern int i915_irq_emit(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int i915_irq_wait(struct drm_device *dev, void *data, - struct drm_file *file_priv); -void i915_user_irq_get(struct drm_device *dev); -void i915_user_irq_put(struct drm_device *dev); - -extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); -extern void i915_driver_irq_preinstall(struct drm_device * dev); -extern int i915_driver_irq_postinstall(struct drm_device *dev); -extern void i915_driver_irq_uninstall(struct drm_device * dev); -extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int i915_enable_vblank(struct drm_device *dev, int crtc); -extern void i915_disable_vblank(struct drm_device *dev, int crtc); -extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); -extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); -extern int i915_vblank_swap(struct drm_device *dev, void *data, - struct drm_file *file_priv); - -void -i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); - -void -i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); - - -/* i915_mem.c */ -extern int i915_mem_alloc(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int i915_mem_free(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int i915_mem_init_heap(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern void i915_mem_takedown(struct mem_block **heap); -extern void i915_mem_release(struct drm_device * dev, - struct drm_file *file_priv, struct mem_block *heap); -#ifdef I915_HAVE_GEM -/* i915_gem.c */ -int i915_gem_init_ioctl(struct drm_device *dev, void *data, - struct drm_file *file_priv); -int i915_gem_create_ioctl(struct drm_device *dev, void *data, - struct drm_file *file_priv); -int i915_gem_pread_ioctl(struct drm_device *dev, void *data, - struct drm_file *file_priv); -int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, - struct drm_file *file_priv); -int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, - struct drm_file *file_priv); -int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, - struct drm_file *file_priv); -int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, - struct drm_file *file_priv); -int i915_gem_execbuffer(struct drm_device *dev, void *data, - struct drm_file *file_priv); -int i915_gem_pin_ioctl(struct drm_device *dev, void *data, - struct drm_file *file_priv); -int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, - struct drm_file *file_priv); -int i915_gem_busy_ioctl(struct drm_device *dev, void *data, - struct drm_file *file_priv); -int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, - struct drm_file *file_priv); -int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, - struct drm_file *file_priv); -int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, - struct drm_file *file_priv); -int i915_gem_set_tiling(struct drm_device *dev, void *data, - struct drm_file *file_priv); -int i915_gem_get_tiling(struct drm_device *dev, void *data, - struct drm_file *file_priv); -void i915_gem_load(struct drm_device *dev); -int i915_gem_proc_init(struct drm_minor *minor); -void i915_gem_proc_cleanup(struct drm_minor *minor); -int i915_gem_init_object(struct drm_gem_object *obj); -void i915_gem_free_object(struct drm_gem_object *obj); -int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); -void i915_gem_object_unpin(struct drm_gem_object *obj); -void i915_gem_lastclose(struct drm_device *dev); -uint32_t i915_get_gem_seqno(struct drm_device *dev); -void i915_gem_retire_requests(struct drm_device *dev); -void i915_gem_retire_work_handler(struct work_struct *work); -void i915_gem_clflush_object(struct drm_gem_object *obj); - -/* i915_gem_tiling.c */ -void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); - -/* i915_gem_debug.c */ -void i915_gem_dump_object(struct drm_gem_object *obj, int len, - const char *where, uint32_t mark); -#if WATCH_INACTIVE -void i915_verify_inactive(struct drm_device *dev, char *file, int line); -#else -#define i915_verify_inactive(dev, file, line) -#endif -void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); -void i915_gem_dump_object(struct drm_gem_object *obj, int len, - const char *where, uint32_t mark); -void i915_dump_lru(struct drm_device *dev, const char *where); -#endif /* I915_HAVE_GEM */ - -/* i915_suspend.c */ -extern int i915_save_state(struct drm_device *dev); -extern int i915_restore_state(struct drm_device *dev); - -/* i915_opregion.c */ -extern int intel_opregion_init(struct drm_device *dev); -extern void intel_opregion_free(struct drm_device *dev); -extern void opregion_asle_intr(struct drm_device *dev); -extern void opregion_enable_asle(struct drm_device *dev); - -/** - * Lock test for when it's just for synchronization of ring access. - * - * In that case, we don't need to do it when GEM is initialized as nobody else - * has access to the ring. - */ -#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ - if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \ - LOCK_TEST_WITH_RETURN(dev, file_priv); \ -} while (0) - -#if defined(__FreeBSD__) -typedef boolean_t bool; -#endif - -#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) -#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) -#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) -#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) -#define I915_READ8(reg) DRM_READ8(dev_priv->mmio_map, (reg)) -#define I915_WRITE8(reg,val) DRM_WRITE8(dev_priv->mmio_map, (reg), (val)) - -#define I915_VERBOSE 0 - -#define RING_LOCALS unsigned int outring, ringmask, outcount; \ - volatile char *virt; - -#define BEGIN_LP_RING(n) do { \ - if (I915_VERBOSE) \ - DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ - if (dev_priv->ring.space < (n)*4) \ - i915_wait_ring(dev, (n)*4, __func__); \ - outcount = 0; \ - outring = dev_priv->ring.tail; \ - ringmask = dev_priv->ring.tail_mask; \ - virt = dev_priv->ring.virtual_start; \ -} while (0) - -#define OUT_RING(n) do { \ - if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ - *(volatile unsigned int *)(virt + outring) = (n); \ - outcount++; \ - outring += 4; \ - outring &= ringmask; \ -} while (0) - -#define ADVANCE_LP_RING() do { \ - if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ - dev_priv->ring.tail = outring; \ - dev_priv->ring.space -= outcount * 4; \ - I915_WRITE(PRB0_TAIL, outring); \ -} while(0) - -/** - * Reads a dword out of the status page, which is written to from the command - * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or - * MI_STORE_DATA_IMM. - * - * The following dwords have a reserved meaning: - * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. - * 0x04: ring 0 head pointer - * 0x05: ring 1 head pointer (915-class) - * 0x06: ring 2 head pointer (915-class) - * 0x10-0x1b: Context status DWords (GM45) - * 0x1f: Last written status offset. (GM45) - * - * The area from dword 0x20 to 0x3ff is available for driver usage. - */ -#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) -#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) -#define I915_GEM_HWS_INDEX 0x20 -#define I915_BREADCRUMB_INDEX 0x21 - -extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); - -#define IS_I830(dev) ((dev)->pci_device == 0x3577) -#define IS_845G(dev) ((dev)->pci_device == 0x2562) -#define IS_I85X(dev) ((dev)->pci_device == 0x3582) -#define IS_I855(dev) ((dev)->pci_device == 0x3582) -#define IS_I865G(dev) ((dev)->pci_device == 0x2572) - -#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) -#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) -#define IS_I945G(dev) ((dev)->pci_device == 0x2772) -#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ - (dev)->pci_device == 0x27AE) -#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ - (dev)->pci_device == 0x2982 || \ - (dev)->pci_device == 0x2992 || \ - (dev)->pci_device == 0x29A2 || \ - (dev)->pci_device == 0x2A02 || \ - (dev)->pci_device == 0x2A12 || \ - (dev)->pci_device == 0x2A42 || \ - (dev)->pci_device == 0x2E02 || \ - (dev)->pci_device == 0x2E12 || \ - (dev)->pci_device == 0x2E22) - -#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) - -#define IS_GM45(dev) ((dev)->pci_device == 0x2A42) - -#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ - (dev)->pci_device == 0x2E12 || \ - (dev)->pci_device == 0x2E22) - -#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ - (dev)->pci_device == 0x29B2 || \ - (dev)->pci_device == 0x29D2) - -#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ - IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) - -#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ - IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev)) - -#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) - -#define PRIMARY_RINGBUFFER_SIZE (128*1024) - -#endif diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c deleted file mode 100644 index 51c1a973..00000000 --- a/shared-core/i915_irq.c +++ /dev/null @@ -1,534 +0,0 @@ -/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- - */ -/* - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "drmP.h" -#include "drm.h" -#include "i915_drm.h" -#include "i915_drv.h" - -#define MAX_NOPID ((u32)~0) - -/** - * Interrupts that are always left unmasked. - * - * Since pipe events are edge-triggered from the PIPESTAT register to IIR, - * we leave them always unmasked in IMR and then control enabling them through - * PIPESTAT alone. - */ -#define I915_INTERRUPT_ENABLE_FIX (I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ - I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) - -/** Interrupts that we mask and unmask at runtime. */ -#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) - -/** These are all of the interrupts used by the driver */ -#define I915_INTERRUPT_ENABLE_MASK (I915_INTERRUPT_ENABLE_FIX | \ - I915_INTERRUPT_ENABLE_VAR) - -static inline void -i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) -{ - DRM_DEBUG("irq_enable_reg = 0x%08x, mask = 0x%08x\n", - dev_priv->irq_mask_reg, mask); - mask &= I915_INTERRUPT_ENABLE_VAR; - if ((dev_priv->irq_mask_reg & mask) != 0) { - dev_priv->irq_mask_reg &= ~mask; - I915_WRITE(IMR, dev_priv->irq_mask_reg); - (void) I915_READ(IMR); - } -} - -static inline void -i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) -{ - mask &= I915_INTERRUPT_ENABLE_VAR; - if ((dev_priv->irq_mask_reg & mask) != mask) { - dev_priv->irq_mask_reg |= mask; - I915_WRITE(IMR, dev_priv->irq_mask_reg); - (void) I915_READ(IMR); - } -} - -static inline u32 -i915_pipestat(int pipe) -{ - if (pipe == 0) - return PIPEASTAT; - if (pipe == 1) - return PIPEBSTAT; - return -EINVAL; -} - -void -i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) -{ - if ((dev_priv->pipestat[pipe] & mask) != mask) { - u32 reg = i915_pipestat(pipe); - - dev_priv->pipestat[pipe] |= mask; - /* Enable the interrupt, clear any pending status */ - I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); - (void) I915_READ(reg); - } -} - -void -i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) -{ - if ((dev_priv->pipestat[pipe] & mask) != 0) { - u32 reg = i915_pipestat(pipe); - - dev_priv->pipestat[pipe] &= ~mask; - I915_WRITE(reg, dev_priv->pipestat[pipe]); - (void) I915_READ(reg); - } -} - -/** - * i915_pipe_enabled - check if a pipe is enabled - * @dev: DRM device - * @pipe: pipe to check - * - * Reading certain registers when the pipe is disabled can hang the chip. - * Use this routine to make sure the PLL is running and the pipe is active - * before reading such registers if unsure. - */ -static int -i915_pipe_enabled(struct drm_device *dev, int pipe) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; - - if (I915_READ(pipeconf) & PIPEACONF_ENABLE) - return 1; - - return 0; -} - -/* Called from drm generic code, passed a 'crtc', which - * we use as a pipe index - */ -u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - unsigned long high_frame; - unsigned long low_frame; - u32 high1, high2, low, count; - - high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; - low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; - - if (!i915_pipe_enabled(dev, pipe)) { - DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); - return 0; - } - - /* - * High & low register fields aren't synchronized, so make sure - * we get a low value that's stable across two reads of the high - * register. - */ - do { - high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> - PIPE_FRAME_HIGH_SHIFT); - low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> - PIPE_FRAME_LOW_SHIFT); - high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> - PIPE_FRAME_HIGH_SHIFT); - } while (high1 != high2); - - count = (high1 << 8) | low; - - return count; -} - -u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; - - if (!i915_pipe_enabled(dev, pipe)) { - DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); - return 0; - } - - return I915_READ(reg); -} - -irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) -{ - struct drm_device *dev = (struct drm_device *) arg; - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - u32 iir, new_iir; - u32 pipea_stats, pipeb_stats; - - atomic_inc(&dev_priv->irq_received); - - for (iir = I915_READ(IIR) ; iir != 0 ; iir = new_iir) { - - pipea_stats = pipeb_stats = 0; - - /* - * Clear the PIPE(A|B)STAT regs before the IIR - */ - if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) { - DRM_SPINLOCK(&dev_priv->user_irq_lock); - pipea_stats = I915_READ(PIPEASTAT); - I915_WRITE(PIPEASTAT, pipea_stats); - DRM_SPINUNLOCK(&dev_priv->user_irq_lock); - } - - if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) { - DRM_SPINLOCK(&dev_priv->user_irq_lock); - pipeb_stats = I915_READ(PIPEBSTAT); - I915_WRITE(PIPEBSTAT, pipeb_stats); - DRM_SPINUNLOCK(&dev_priv->user_irq_lock); - } - - I915_WRITE(IIR, iir); - new_iir = I915_READ(IIR); - - DRM_DEBUG("iir = 0x%08x, pipestats a = 0x%08x, b = 0x%08x\n", - iir, pipea_stats, pipeb_stats); - - if (dev_priv->sarea_priv) - dev_priv->sarea_priv->last_dispatch = - READ_BREADCRUMB(dev_priv); - - if (iir & I915_USER_INTERRUPT) { -#ifdef I915_HAVE_GEM - dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev); -#endif - DRM_WAKEUP(&dev_priv->irq_queue); - } - - if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS | - PIPE_VBLANK_INTERRUPT_STATUS)) - drm_handle_vblank(dev, 0); - - if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS | - PIPE_VBLANK_INTERRUPT_STATUS)) - drm_handle_vblank(dev, 1); -#ifdef __linux__ - if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || - (iir & I915_ASLE_INTERRUPT)) - opregion_asle_intr(dev); -#endif - } -} - -static int i915_emit_irq(struct drm_device * dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - RING_LOCALS; - - i915_kernel_lost_context(dev); - - DRM_DEBUG("\n"); - - dev_priv->counter++; - if (dev_priv->counter > 0x7FFFFFFFUL) - dev_priv->counter = 1; - if (dev_priv->sarea_priv) - dev_priv->sarea_priv->last_enqueue = dev_priv->counter; - - BEGIN_LP_RING(4); - OUT_RING(MI_STORE_DWORD_INDEX); - OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); - OUT_RING(dev_priv->counter); - OUT_RING(MI_USER_INTERRUPT); - ADVANCE_LP_RING(); - - return dev_priv->counter; -} - -void i915_user_irq_get(struct drm_device *dev) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - unsigned long irqflags; - - DRM_DEBUG("\n"); - DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags); - if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) - i915_enable_irq(dev_priv, I915_USER_INTERRUPT); - DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags); -} - -void i915_user_irq_put(struct drm_device *dev) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - unsigned long irqflags; - - DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags); -#ifdef __linux__ - BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); -#endif - if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) - i915_disable_irq(dev_priv, I915_USER_INTERRUPT); - DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags); -} - -static int i915_wait_irq(struct drm_device * dev, int irq_nr) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - int ret = 0; - - DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr, - READ_BREADCRUMB(dev_priv)); - - if (READ_BREADCRUMB(dev_priv) >= irq_nr) { - if (dev_priv->sarea_priv) { - dev_priv->sarea_priv->last_dispatch = - READ_BREADCRUMB(dev_priv); - } - return 0; - } - - if (dev_priv->sarea_priv) - dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; - - i915_user_irq_get(dev); - DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, - READ_BREADCRUMB(dev_priv) >= irq_nr); - i915_user_irq_put(dev); - - if (ret == -EBUSY) { - DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", - READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); - } - - if (dev_priv->sarea_priv) - dev_priv->sarea_priv->last_dispatch = - READ_BREADCRUMB(dev_priv); - - return ret; -} - -/* Needs the lock as it touches the ring. - */ -int i915_irq_emit(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_irq_emit_t *emit = data; - int result; - - RING_LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - result = i915_emit_irq(dev); - - if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { - DRM_ERROR("copy_to_user\n"); - return -EFAULT; - } - - return 0; -} - -/* Doesn't need the hardware lock. - */ -int i915_irq_wait(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_irq_wait_t *irqwait = data; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - return i915_wait_irq(dev, irqwait->irq_seq); -} - -/* Called from drm generic code, passed 'crtc' which - * we use as a pipe index - */ -int i915_enable_vblank(struct drm_device *dev, int pipe) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - unsigned long irqflags; - u32 pipestat; - - /* - * Older chips didn't have the start vblank interrupt, - * but - */ - if (IS_I965G (dev)) - pipestat = PIPE_START_VBLANK_INTERRUPT_ENABLE; - else - pipestat = PIPE_VBLANK_INTERRUPT_ENABLE; - - DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags); - i915_enable_pipestat(dev_priv, pipe, pipestat); - DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags); - return 0; -} - -/* Called from drm generic code, passed 'crtc' which - * we use as a pipe index - */ -void i915_disable_vblank(struct drm_device *dev, int pipe) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - unsigned long irqflags; - - DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags); - i915_disable_pipestat(dev_priv, pipe, - PIPE_START_VBLANK_INTERRUPT_ENABLE | PIPE_VBLANK_INTERRUPT_ENABLE); - DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags); -} - -/* Set the vblank monitor pipe - */ -int i915_vblank_pipe_set(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - return 0; -} - -int i915_vblank_pipe_get(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_vblank_pipe_t *pipe = data; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; - - return 0; -} - -/** - * Schedule buffer swap at given vertical blank. - */ -int i915_vblank_swap(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - /* The delayed swap mechanism was fundamentally racy, and has been - * removed. The model was that the client requested a delayed flip/swap - * from the kernel, then waited for vblank before continuing to perform - * rendering. The problem was that the kernel might wake the client - * up before it dispatched the vblank swap (since the lock has to be - * held while touching the ringbuffer), in which case the client would - * clear and start the next frame before the swap occurred, and - * flicker would occur in addition to likely missing the vblank. - * - * In the absence of this ioctl, userland falls back to a correct path - * of waiting for a vblank, then dispatching the swap on its own. - * Context switching to userland and back is plenty fast enough for - * meeting the requirements of vblank swapping. - */ - - return -EINVAL; -} - -/* drm_dma.h hooks -*/ -void i915_driver_irq_preinstall(struct drm_device * dev) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - - I915_WRITE(HWSTAM, 0xeffe); - I915_WRITE(PIPEASTAT, 0); - I915_WRITE(PIPEBSTAT, 0); - I915_WRITE(IMR, 0xffffffff); - I915_WRITE(IER, 0x0); - (void) I915_READ(IER); -} - -int i915_driver_irq_postinstall(struct drm_device *dev) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - - dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; - - dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ - - /* Unmask the interrupts that we always want on. */ - dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; - - dev_priv->pipestat[0] = 0; - dev_priv->pipestat[1] = 0; - - /* Disable pipe interrupt enables, clear pending pipe status */ - I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); - I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); - - /* Clear pending interrupt status */ - I915_WRITE(IIR, I915_READ(IIR)); - - I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK); - I915_WRITE(IMR, dev_priv->irq_mask_reg); - (void) I915_READ(IER); -#ifdef __linux__ - opregion_enable_asle(dev); -#endif - DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); - - i915_enable_vblank(dev, 0); - i915_enable_vblank(dev, 1); - - return 0; -} - -void i915_driver_irq_uninstall(struct drm_device * dev) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - - if (!dev_priv) - return; - - dev_priv->vblank_pipe = 0; - - I915_WRITE(HWSTAM, 0xffffffff); - I915_WRITE(PIPEASTAT, 0); - I915_WRITE(PIPEBSTAT, 0); - I915_WRITE(IMR, 0xffffffff); - I915_WRITE(IER, 0x0); - - I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); - I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); - I915_WRITE(IIR, I915_READ(IIR)); -} diff --git a/shared-core/i915_mem.c b/shared-core/i915_mem.c deleted file mode 100644 index 6126a60d..00000000 --- a/shared-core/i915_mem.c +++ /dev/null @@ -1,386 +0,0 @@ -/* i915_mem.c -- Simple agp/fb memory manager for i915 -*- linux-c -*- - */ -/* - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "drmP.h" -#include "drm.h" -#include "i915_drm.h" -#include "i915_drv.h" - -/* This memory manager is integrated into the global/local lru - * mechanisms used by the clients. Specifically, it operates by - * setting the 'in_use' fields of the global LRU to indicate whether - * this region is privately allocated to a client. - * - * This does require the client to actually respect that field. - * - * Currently no effort is made to allocate 'private' memory in any - * clever way - the LRU information isn't used to determine which - * block to allocate, and the ring is drained prior to allocations -- - * in other words allocation is expensive. - */ -static void mark_block(struct drm_device * dev, struct mem_block *p, int in_use) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; - struct drm_tex_region *list; - unsigned shift, nr; - unsigned start; - unsigned end; - unsigned i; - int age; - - shift = dev_priv->tex_lru_log_granularity; - nr = I915_NR_TEX_REGIONS; - - start = p->start >> shift; - end = (p->start + p->size - 1) >> shift; - - age = ++sarea_priv->texAge; - list = sarea_priv->texList; - - /* Mark the regions with the new flag and update their age. Move - * them to head of list to preserve LRU semantics. - */ - for (i = start; i <= end; i++) { - list[i].in_use = in_use; - list[i].age = age; - - /* remove_from_list(i) - */ - list[(unsigned)list[i].next].prev = list[i].prev; - list[(unsigned)list[i].prev].next = list[i].next; - - /* insert_at_head(list, i) - */ - list[i].prev = nr; - list[i].next = list[nr].next; - list[(unsigned)list[nr].next].prev = i; - list[nr].next = i; - } -} - -/* Very simple allocator for agp memory, working on a static range - * already mapped into each client's address space. - */ - -static struct mem_block *split_block(struct mem_block *p, int start, int size, - struct drm_file *file_priv) -{ - /* Maybe cut off the start of an existing block */ - if (start > p->start) { - struct mem_block *newblock = - drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS); - if (!newblock) - goto out; - newblock->start = start; - newblock->size = p->size - (start - p->start); - newblock->file_priv = NULL; - newblock->next = p->next; - newblock->prev = p; - p->next->prev = newblock; - p->next = newblock; - p->size -= newblock->size; - p = newblock; - } - - /* Maybe cut off the end of an existing block */ - if (size < p->size) { - struct mem_block *newblock = - drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS); - if (!newblock) - goto out; - newblock->start = start + size; - newblock->size = p->size - size; - newblock->file_priv = NULL; - newblock->next = p->next; - newblock->prev = p; - p->next->prev = newblock; - p->next = newblock; - p->size = size; - } - - out: - /* Our block is in the middle */ - p->file_priv = file_priv; - return p; -} - -static struct mem_block *alloc_block(struct mem_block *heap, int size, - int align2, struct drm_file *file_priv) -{ - struct mem_block *p; - int mask = (1 << align2) - 1; - - for (p = heap->next; p != heap; p = p->next) { - int start = (p->start + mask) & ~mask; - if (p->file_priv == NULL && start + size <= p->start + p->size) - return split_block(p, start, size, file_priv); - } - - return NULL; -} - -static struct mem_block *find_block(struct mem_block *heap, int start) -{ - struct mem_block *p; - - for (p = heap->next; p != heap; p = p->next) - if (p->start == start) - return p; - - return NULL; -} - -static void free_block(struct mem_block *p) -{ - p->file_priv = NULL; - - /* Assumes a single contiguous range. Needs a special file_priv in - * 'heap' to stop it being subsumed. - */ - if (p->next->file_priv == NULL) { - struct mem_block *q = p->next; - p->size += q->size; - p->next = q->next; - p->next->prev = p; - drm_free(q, sizeof(*q), DRM_MEM_BUFLISTS); - } - - if (p->prev->file_priv == NULL) { - struct mem_block *q = p->prev; - q->size += p->size; - q->next = p->next; - q->next->prev = q; - drm_free(p, sizeof(*q), DRM_MEM_BUFLISTS); - } -} - -/* Initialize. How to check for an uninitialized heap? - */ -static int init_heap(struct mem_block **heap, int start, int size) -{ - struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFLISTS); - - if (!blocks) - return -ENOMEM; - - *heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFLISTS); - if (!*heap) { - drm_free(blocks, sizeof(*blocks), DRM_MEM_BUFLISTS); - return -ENOMEM; - } - - blocks->start = start; - blocks->size = size; - blocks->file_priv = NULL; - blocks->next = blocks->prev = *heap; - - memset(*heap, 0, sizeof(**heap)); - (*heap)->file_priv = (struct drm_file *) - 1; - (*heap)->next = (*heap)->prev = blocks; - return 0; -} - -/* Free all blocks associated with the releasing file. - */ -void i915_mem_release(struct drm_device * dev, struct drm_file *file_priv, - struct mem_block *heap) -{ - struct mem_block *p; - - if (!heap || !heap->next) - return; - - for (p = heap->next; p != heap; p = p->next) { - if (p->file_priv == file_priv) { - p->file_priv = NULL; - mark_block(dev, p, 0); - } - } - - /* Assumes a single contiguous range. Needs a special file_priv in - * 'heap' to stop it being subsumed. - */ - for (p = heap->next; p != heap; p = p->next) { - while (p->file_priv == NULL && p->next->file_priv == NULL) { - struct mem_block *q = p->next; - p->size += q->size; - p->next = q->next; - p->next->prev = p; - drm_free(q, sizeof(*q), DRM_MEM_BUFLISTS); - } - } -} - -/* Shutdown. - */ -void i915_mem_takedown(struct mem_block **heap) -{ - struct mem_block *p; - - if (!*heap) - return; - - for (p = (*heap)->next; p != *heap;) { - struct mem_block *q = p; - p = p->next; - drm_free(q, sizeof(*q), DRM_MEM_BUFLISTS); - } - - drm_free(*heap, sizeof(**heap), DRM_MEM_BUFLISTS); - *heap = NULL; -} - -static struct mem_block **get_heap(drm_i915_private_t * dev_priv, int region) -{ - switch (region) { - case I915_MEM_REGION_AGP: - return &dev_priv->agp_heap; - default: - return NULL; - } -} - -/* IOCTL HANDLERS */ - -int i915_mem_alloc(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_mem_alloc_t *alloc = data; - struct mem_block *block, **heap; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - heap = get_heap(dev_priv, alloc->region); - if (!heap || !*heap) - return -EFAULT; - - /* Make things easier on ourselves: all allocations at least - * 4k aligned. - */ - if (alloc->alignment < 12) - alloc->alignment = 12; - - block = alloc_block(*heap, alloc->size, alloc->alignment, file_priv); - - if (!block) - return -ENOMEM; - - mark_block(dev, block, 1); - - if (DRM_COPY_TO_USER(alloc->region_offset, &block->start, - sizeof(int))) { - DRM_ERROR("copy_to_user\n"); - return -EFAULT; - } - - return 0; -} - -int i915_mem_free(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_mem_free_t *memfree = data; - struct mem_block *block, **heap; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - heap = get_heap(dev_priv, memfree->region); - if (!heap || !*heap) - return -EFAULT; - - block = find_block(*heap, memfree->region_offset); - if (!block) - return -EFAULT; - - if (block->file_priv != file_priv) - return -EPERM; - - mark_block(dev, block, 0); - free_block(block); - return 0; -} - -int i915_mem_init_heap(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_mem_init_heap_t *initheap = data; - struct mem_block **heap; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - heap = get_heap(dev_priv, initheap->region); - if (!heap) - return -EFAULT; - - if (*heap) { - DRM_ERROR("heap already initialized?"); - return -EFAULT; - } - - return init_heap(heap, initheap->start, initheap->size); -} - -int i915_mem_destroy_heap( struct drm_device *dev, void *data, - struct drm_file *file_priv ) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_mem_destroy_heap_t *destroyheap = data; - struct mem_block **heap; - - if ( !dev_priv ) { - DRM_ERROR( "called with no initialization\n" ); - return -EINVAL; - } - - heap = get_heap( dev_priv, destroyheap->region ); - if (!heap) { - DRM_ERROR("get_heap failed"); - return -EFAULT; - } - - if (!*heap) { - DRM_ERROR("heap not initialized?"); - return -EFAULT; - } - - i915_mem_takedown( heap ); - return 0; -} diff --git a/shared-core/i915_reg.h b/shared-core/i915_reg.h deleted file mode 100644 index 75647757..00000000 --- a/shared-core/i915_reg.h +++ /dev/null @@ -1,1422 +0,0 @@ -/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _I915_REG_H_ -#define _I915_REG_H_ - -/* - * The Bridge device's PCI config space has information about the - * fb aperture size and the amount of pre-reserved memory. - */ -#define INTEL_GMCH_CTRL 0x52 -#define INTEL_GMCH_ENABLED 0x4 -#define INTEL_GMCH_MEM_MASK 0x1 -#define INTEL_GMCH_MEM_64M 0x1 -#define INTEL_GMCH_MEM_128M 0 - -#define INTEL_855_GMCH_GMS_MASK (0x7 << 4) -#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4) -#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4) -#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4) -#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4) -#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4) -#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4) - -#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4) -#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4) - -/* PCI config space */ - -#define HPLLCC 0xc0 /* 855 only */ -#define GC_CLOCK_CONTROL_MASK (3 << 0) -#define GC_CLOCK_133_200 (0 << 0) -#define GC_CLOCK_100_200 (1 << 0) -#define GC_CLOCK_100_133 (2 << 0) -#define GC_CLOCK_166_250 (3 << 0) -#define GCFGC 0xf0 /* 915+ only */ -#define GC_LOW_FREQUENCY_ENABLE (1 << 7) -#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) -#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) -#define GC_DISPLAY_CLOCK_MASK (7 << 4) -#define LBB 0xf4 - -/* VGA stuff */ - -#define VGA_ST01_MDA 0x3ba -#define VGA_ST01_CGA 0x3da - -#define VGA_MSR_WRITE 0x3c2 -#define VGA_MSR_READ 0x3cc -#define VGA_MSR_MEM_EN (1<<1) -#define VGA_MSR_CGA_MODE (1<<0) - -#define VGA_SR_INDEX 0x3c4 -#define VGA_SR_DATA 0x3c5 - -#define VGA_AR_INDEX 0x3c0 -#define VGA_AR_VID_EN (1<<5) -#define VGA_AR_DATA_WRITE 0x3c0 -#define VGA_AR_DATA_READ 0x3c1 - -#define VGA_GR_INDEX 0x3ce -#define VGA_GR_DATA 0x3cf -/* GR05 */ -#define VGA_GR_MEM_READ_MODE_SHIFT 3 -#define VGA_GR_MEM_READ_MODE_PLANE 1 -/* GR06 */ -#define VGA_GR_MEM_MODE_MASK 0xc -#define VGA_GR_MEM_MODE_SHIFT 2 -#define VGA_GR_MEM_A0000_AFFFF 0 -#define VGA_GR_MEM_A0000_BFFFF 1 -#define VGA_GR_MEM_B0000_B7FFF 2 -#define VGA_GR_MEM_B0000_BFFFF 3 - -#define VGA_DACMASK 0x3c6 -#define VGA_DACRX 0x3c7 -#define VGA_DACWX 0x3c8 -#define VGA_DACDATA 0x3c9 - -#define VGA_CR_INDEX_MDA 0x3b4 -#define VGA_CR_DATA_MDA 0x3b5 -#define VGA_CR_INDEX_CGA 0x3d4 -#define VGA_CR_DATA_CGA 0x3d5 - -/* - * Memory interface instructions used by the kernel - */ -#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) - -#define MI_NOOP MI_INSTR(0, 0) -#define MI_USER_INTERRUPT MI_INSTR(0x02, 0) -#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) -#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) -#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) -#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) -#define MI_FLUSH MI_INSTR(0x04, 0) -#define MI_READ_FLUSH (1 << 0) -#define MI_EXE_FLUSH (1 << 1) -#define MI_NO_WRITE_FLUSH (1 << 2) -#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ -#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ -#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) -#define MI_REPORT_HEAD MI_INSTR(0x07, 0) -#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) -#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) -#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ -#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) -#define MI_STORE_DWORD_INDEX_SHIFT 2 -#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1) -#define MI_BATCH_BUFFER MI_INSTR(0x30, 1) -#define MI_BATCH_NON_SECURE (1) -#define MI_BATCH_NON_SECURE_I965 (1<<8) -#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) - -/* - * 3D instructions used by the kernel - */ -#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) - -#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) -#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) -#define SC_UPDATE_SCISSOR (0x1<<1) -#define SC_ENABLE_MASK (0x1<<0) -#define SC_ENABLE (0x1<<0) -#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) -#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) -#define SCI_YMIN_MASK (0xffff<<16) -#define SCI_XMIN_MASK (0xffff<<0) -#define SCI_YMAX_MASK (0xffff<<16) -#define SCI_XMAX_MASK (0xffff<<0) -#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) -#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) -#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) -#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) -#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) -#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) -#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) -#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) -#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) -#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) -#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) -#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) -#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) -#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) -#define BLT_DEPTH_8 (0<<24) -#define BLT_DEPTH_16_565 (1<<24) -#define BLT_DEPTH_16_1555 (2<<24) -#define BLT_DEPTH_32 (3<<24) -#define BLT_ROP_GXCOPY (0xcc<<16) -#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ -#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ -#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) -#define ASYNC_FLIP (1<<22) -#define DISPLAY_PLANE_A (0<<20) -#define DISPLAY_PLANE_B (1<<20) - -/* - * Instruction and interrupt control regs - */ - -#define PRB0_TAIL 0x02030 -#define PRB0_HEAD 0x02034 -#define PRB0_START 0x02038 -#define PRB0_CTL 0x0203c -#define TAIL_ADDR 0x001FFFF8 -#define HEAD_WRAP_COUNT 0xFFE00000 -#define HEAD_WRAP_ONE 0x00200000 -#define HEAD_ADDR 0x001FFFFC -#define RING_NR_PAGES 0x001FF000 -#define RING_REPORT_MASK 0x00000006 -#define RING_REPORT_64K 0x00000002 -#define RING_REPORT_128K 0x00000004 -#define RING_NO_REPORT 0x00000000 -#define RING_VALID_MASK 0x00000001 -#define RING_VALID 0x00000001 -#define RING_INVALID 0x00000000 -#define PRB1_TAIL 0x02040 /* 915+ only */ -#define PRB1_HEAD 0x02044 /* 915+ only */ -#define PRB1_START 0x02048 /* 915+ only */ -#define PRB1_CTL 0x0204c /* 915+ only */ -#define ACTHD_I965 0x02074 -#define HWS_PGA 0x02080 -#define HWS_ADDRESS_MASK 0xfffff000 -#define HWS_START_ADDRESS_SHIFT 4 -#define IPEIR 0x02088 -#define NOPID 0x02094 -#define HWSTAM 0x02098 -#define SCPD0 0x0209c /* 915+ only */ -#define IER 0x020a0 -#define IIR 0x020a4 -#define IMR 0x020a8 -#define ISR 0x020ac -#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) -#define I915_DISPLAY_PORT_INTERRUPT (1<<17) -#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) -#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) -#define I915_HWB_OOM_INTERRUPT (1<<13) -#define I915_SYNC_STATUS_INTERRUPT (1<<12) -#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) -#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) -#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) -#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) -#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) -#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) -#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) -#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) -#define I915_DEBUG_INTERRUPT (1<<2) -#define I915_USER_INTERRUPT (1<<1) -#define I915_ASLE_INTERRUPT (1<<0) -#define EIR 0x020b0 -#define EMR 0x020b4 -#define ESR 0x020b8 -#define INSTPM 0x020c0 -#define ACTHD 0x020c8 -#define FW_BLC 0x020d8 -#define FW_BLC_SELF 0x020e0 /* 915+ only */ -#define MI_ARB_STATE 0x020e4 /* 915+ only */ -#define CACHE_MODE_0 0x02120 /* 915+ only */ -#define CM0_MASK_SHIFT 16 -#define CM0_IZ_OPT_DISABLE (1<<6) -#define CM0_ZR_OPT_DISABLE (1<<5) -#define CM0_DEPTH_EVICT_DISABLE (1<<4) -#define CM0_COLOR_EVICT_DISABLE (1<<3) -#define CM0_DEPTH_WRITE_DISABLE (1<<1) -#define CM0_RC_OP_FLUSH_DISABLE (1<<0) -#define GFX_FLSH_CNTL 0x02170 /* 915+ only */ - -/* - * Framebuffer compression (915+ only) - */ - -#define FBC_CFB_BASE 0x03200 /* 4k page aligned */ -#define FBC_LL_BASE 0x03204 /* 4k page aligned */ -#define FBC_CONTROL 0x03208 -#define FBC_CTL_EN (1<<31) -#define FBC_CTL_PERIODIC (1<<30) -#define FBC_CTL_INTERVAL_SHIFT (16) -#define FBC_CTL_UNCOMPRESSIBLE (1<<14) -#define FBC_CTL_STRIDE_SHIFT (5) -#define FBC_CTL_FENCENO (1<<0) -#define FBC_COMMAND 0x0320c -#define FBC_CMD_COMPRESS (1<<0) -#define FBC_STATUS 0x03210 -#define FBC_STAT_COMPRESSING (1<<31) -#define FBC_STAT_COMPRESSED (1<<30) -#define FBC_STAT_MODIFIED (1<<29) -#define FBC_STAT_CURRENT_LINE (1<<0) -#define FBC_CONTROL2 0x03214 -#define FBC_CTL_FENCE_DBL (0<<4) -#define FBC_CTL_IDLE_IMM (0<<2) -#define FBC_CTL_IDLE_FULL (1<<2) -#define FBC_CTL_IDLE_LINE (2<<2) -#define FBC_CTL_IDLE_DEBUG (3<<2) -#define FBC_CTL_CPU_FENCE (1<<1) -#define FBC_CTL_PLANEA (0<<0) -#define FBC_CTL_PLANEB (1<<0) -#define FBC_FENCE_OFF 0x0321b - -#define FBC_LL_SIZE (1536) - -/* - * GPIO regs - */ -#define GPIOA 0x5010 -#define GPIOB 0x5014 -#define GPIOC 0x5018 -#define GPIOD 0x501c -#define GPIOE 0x5020 -#define GPIOF 0x5024 -#define GPIOG 0x5028 -#define GPIOH 0x502c -# define GPIO_CLOCK_DIR_MASK (1 << 0) -# define GPIO_CLOCK_DIR_IN (0 << 1) -# define GPIO_CLOCK_DIR_OUT (1 << 1) -# define GPIO_CLOCK_VAL_MASK (1 << 2) -# define GPIO_CLOCK_VAL_OUT (1 << 3) -# define GPIO_CLOCK_VAL_IN (1 << 4) -# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) -# define GPIO_DATA_DIR_MASK (1 << 8) -# define GPIO_DATA_DIR_IN (0 << 9) -# define GPIO_DATA_DIR_OUT (1 << 9) -# define GPIO_DATA_VAL_MASK (1 << 10) -# define GPIO_DATA_VAL_OUT (1 << 11) -# define GPIO_DATA_VAL_IN (1 << 12) -# define GPIO_DATA_PULLUP_DISABLE (1 << 13) - -/* - * Clock control & power management - */ - -#define VGA0 0x6000 -#define VGA1 0x6004 -#define VGA_PD 0x6010 -#define VGA0_PD_P2_DIV_4 (1 << 7) -#define VGA0_PD_P1_DIV_2 (1 << 5) -#define VGA0_PD_P1_SHIFT 0 -#define VGA0_PD_P1_MASK (0x1f << 0) -#define VGA1_PD_P2_DIV_4 (1 << 15) -#define VGA1_PD_P1_DIV_2 (1 << 13) -#define VGA1_PD_P1_SHIFT 8 -#define VGA1_PD_P1_MASK (0x1f << 8) -#define DPLL_A 0x06014 -#define DPLL_B 0x06018 -#define DPLL_VCO_ENABLE (1 << 31) -#define DPLL_DVO_HIGH_SPEED (1 << 30) -#define DPLL_SYNCLOCK_ENABLE (1 << 29) -#define DPLL_VGA_MODE_DIS (1 << 28) -#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ -#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ -#define DPLL_MODE_MASK (3 << 26) -#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ -#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ -#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ -#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ -#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ -#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ - -#define I915_FIFO_UNDERRUN_STATUS (1UL<<31) -#define I915_CRC_ERROR_ENABLE (1UL<<29) -#define I915_CRC_DONE_ENABLE (1UL<<28) -#define I915_GMBUS_EVENT_ENABLE (1UL<<27) -#define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25) -#define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) -#define I915_DPST_EVENT_ENABLE (1UL<<23) -#define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22) -#define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) -#define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) -#define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ -#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) -#define I915_OVERLAY_UPDATED_ENABLE (1UL<<16) -#define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) -#define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12) -#define I915_GMBUS_INTERRUPT_STATUS (1UL<<11) -#define I915_VSYNC_INTERRUPT_STATUS (1UL<<9) -#define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) -#define I915_DPST_EVENT_STATUS (1UL<<7) -#define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6) -#define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) -#define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) -#define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ -#define I915_VBLANK_INTERRUPT_STATUS (1UL<<1) -#define I915_OVERLAY_UPDATED_STATUS (1UL<<0) - -#define SRX_INDEX 0x3c4 -#define SRX_DATA 0x3c5 -#define SR01 1 -#define SR01_SCREEN_OFF (1<<5) - -#define PPCR 0x61204 -#define PPCR_ON (1<<0) - -#define DVOB 0x61140 -#define DVOB_ON (1<<31) -#define DVOC 0x61160 -#define DVOC_ON (1<<31) -#define LVDS 0x61180 -#define LVDS_ON (1<<31) - -#define ADPA 0x61100 -#define ADPA_DPMS_MASK (~(3<<10)) -#define ADPA_DPMS_ON (0<<10) -#define ADPA_DPMS_SUSPEND (1<<10) -#define ADPA_DPMS_STANDBY (2<<10) -#define ADPA_DPMS_OFF (3<<10) - -#define RING_TAIL 0x00 -#define TAIL_ADDR 0x001FFFF8 -#define RING_HEAD 0x04 -#define HEAD_WRAP_COUNT 0xFFE00000 -#define HEAD_WRAP_ONE 0x00200000 -#define HEAD_ADDR 0x001FFFFC -#define RING_START 0x08 -#define START_ADDR 0xFFFFF000 -#define RING_LEN 0x0C -#define RING_NR_PAGES 0x001FF000 -#define RING_REPORT_MASK 0x00000006 -#define RING_REPORT_64K 0x00000002 -#define RING_REPORT_128K 0x00000004 -#define RING_NO_REPORT 0x00000000 -#define RING_VALID_MASK 0x00000001 -#define RING_VALID 0x00000001 -#define RING_INVALID 0x00000000 - -/* Scratch pad debug 0 reg: - */ -#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 -/* - * The i830 generation, in LVDS mode, defines P1 as the bit number set within - * this field (only one bit may be set). - */ -#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 -#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 -/* i830, required in DVO non-gang */ -#define PLL_P2_DIVIDE_BY_4 (1 << 23) -#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ -#define PLL_REF_INPUT_DREFCLK (0 << 13) -#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ -#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ -#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) -#define PLL_REF_INPUT_MASK (3 << 13) -#define PLL_LOAD_PULSE_PHASE_SHIFT 9 -/* - * Parallel to Serial Load Pulse phase selection. - * Selects the phase for the 10X DPLL clock for the PCIe - * digital display port. The range is 4 to 13; 10 or more - * is just a flip delay. The default is 6 - */ -#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) -#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) -/* - * SDVO multiplier for 945G/GM. Not used on 965. - */ -#define SDVO_MULTIPLIER_MASK 0x000000ff -#define SDVO_MULTIPLIER_SHIFT_HIRES 4 -#define SDVO_MULTIPLIER_SHIFT_VGA 0 -#define DPLL_A_MD 0x0601c /* 965+ only */ -/* - * UDI pixel divider, controlling how many pixels are stuffed into a packet. - * - * Value is pixels minus 1. Must be set to 1 pixel for SDVO. - */ -#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 -#define DPLL_MD_UDI_DIVIDER_SHIFT 24 -/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ -#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 -#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 -/* - * SDVO/UDI pixel multiplier. - * - * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus - * clock rate is 10 times the DPLL clock. At low resolution/refresh rate - * modes, the bus rate would be below the limits, so SDVO allows for stuffing - * dummy bytes in the datastream at an increased clock rate, with both sides of - * the link knowing how many bytes are fill. - * - * So, for a mode with a dotclock of 65Mhz, we would want to double the clock - * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be - * set to 130Mhz, and the SDVO multiplier set to 2x in this register and - * through an SDVO command. - * - * This register field has values of multiplication factor minus 1, with - * a maximum multiplier of 5 for SDVO. - */ -#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 -#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 -/* - * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. - * This best be set to the default value (3) or the CRT won't work. No, - * I don't entirely understand what this does... - */ -#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f -#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 -#define DPLL_B_MD 0x06020 /* 965+ only */ -#define FPA0 0x06040 -#define FPA1 0x06044 -#define FPB0 0x06048 -#define FPB1 0x0604c -#define FP_N_DIV_MASK 0x003f0000 -#define FP_N_DIV_SHIFT 16 -#define FP_M1_DIV_MASK 0x00003f00 -#define FP_M1_DIV_SHIFT 8 -#define FP_M2_DIV_MASK 0x0000003f -#define FP_M2_DIV_SHIFT 0 -#define DPLL_TEST 0x606c -#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) -#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) -#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) -#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) -#define DPLLB_TEST_N_BYPASS (1 << 19) -#define DPLLB_TEST_M_BYPASS (1 << 18) -#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) -#define DPLLA_TEST_N_BYPASS (1 << 3) -#define DPLLA_TEST_M_BYPASS (1 << 2) -#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) -#define D_STATE 0x6104 -#define CG_2D_DIS 0x6200 -#define CG_3D_DIS 0x6204 - -/* - * Palette regs - */ - -#define PALETTE_A 0x0a000 -#define PALETTE_B 0x0a800 - -/* MCH MMIO space */ - -/* - * MCHBAR mirror. - * - * This mirrors the MCHBAR MMIO space whose location is determined by - * device 0 function 0's pci config register 0x44 or 0x48 and matches it in - * every way. It is not accessible from the CP register read instructions. - * - */ -#define MCHBAR_MIRROR_BASE 0x10000 - -/** 915-945 and GM965 MCH register controlling DRAM channel access */ -#define DCC 0x10200 -#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) -#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) -#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) -#define DCC_ADDRESSING_MODE_MASK (3 << 0) -#define DCC_CHANNEL_XOR_DISABLE (1 << 10) - -/** 965 MCH register controlling DRAM channel configuration */ -#define C0DRB3 0x10206 -#define C1DRB3 0x10606 - -/* - * Overlay regs - */ - -#define OVADD 0x30000 -#define DOVSTA 0x30008 -#define OC_BUF (0x3<<20) -#define OGAMC5 0x30010 -#define OGAMC4 0x30014 -#define OGAMC3 0x30018 -#define OGAMC2 0x3001c -#define OGAMC1 0x30020 -#define OGAMC0 0x30024 - -/* - * Display engine regs - */ - -/* Pipe A timing regs */ -#define HTOTAL_A 0x60000 -#define HBLANK_A 0x60004 -#define HSYNC_A 0x60008 -#define VTOTAL_A 0x6000c -#define VBLANK_A 0x60010 -#define VSYNC_A 0x60014 -#define PIPEASRC 0x6001c -#define BCLRPAT_A 0x60020 - -/* Pipe B timing regs */ -#define HTOTAL_B 0x61000 -#define HBLANK_B 0x61004 -#define HSYNC_B 0x61008 -#define VTOTAL_B 0x6100c -#define VBLANK_B 0x61010 -#define VSYNC_B 0x61014 -#define PIPEBSRC 0x6101c -#define BCLRPAT_B 0x61020 - -/* VGA port control */ -#define ADPA 0x61100 -#define ADPA_DAC_ENABLE (1<<31) -#define ADPA_DAC_DISABLE 0 -#define ADPA_PIPE_SELECT_MASK (1<<30) -#define ADPA_PIPE_A_SELECT 0 -#define ADPA_PIPE_B_SELECT (1<<30) -#define ADPA_USE_VGA_HVPOLARITY (1<<15) -#define ADPA_SETS_HVPOLARITY 0 -#define ADPA_VSYNC_CNTL_DISABLE (1<<11) -#define ADPA_VSYNC_CNTL_ENABLE 0 -#define ADPA_HSYNC_CNTL_DISABLE (1<<10) -#define ADPA_HSYNC_CNTL_ENABLE 0 -#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) -#define ADPA_VSYNC_ACTIVE_LOW 0 -#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) -#define ADPA_HSYNC_ACTIVE_LOW 0 -#define ADPA_DPMS_MASK (~(3<<10)) -#define ADPA_DPMS_ON (0<<10) -#define ADPA_DPMS_SUSPEND (1<<10) -#define ADPA_DPMS_STANDBY (2<<10) -#define ADPA_DPMS_OFF (3<<10) - -/* Hotplug control (945+ only) */ -#define PORT_HOTPLUG_EN 0x61110 -#define SDVOB_HOTPLUG_INT_EN (1 << 26) -#define SDVOC_HOTPLUG_INT_EN (1 << 25) -#define TV_HOTPLUG_INT_EN (1 << 18) -#define CRT_HOTPLUG_INT_EN (1 << 9) -#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) - -#define PORT_HOTPLUG_STAT 0x61114 -#define CRT_HOTPLUG_INT_STATUS (1 << 11) -#define TV_HOTPLUG_INT_STATUS (1 << 10) -#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) -#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) -#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) -#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) -#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) -#define SDVOB_HOTPLUG_INT_STATUS (1 << 6) - -/* SDVO port control */ -#define SDVOB 0x61140 -#define SDVOC 0x61160 -#define SDVO_ENABLE (1 << 31) -#define SDVO_PIPE_B_SELECT (1 << 30) -#define SDVO_STALL_SELECT (1 << 29) -#define SDVO_INTERRUPT_ENABLE (1 << 26) -/** - * 915G/GM SDVO pixel multiplier. - * - * Programmed value is multiplier - 1, up to 5x. - * - * \sa DPLL_MD_UDI_MULTIPLIER_MASK - */ -#define SDVO_PORT_MULTIPLY_MASK (7 << 23) -#define SDVO_PORT_MULTIPLY_SHIFT 23 -#define SDVO_PHASE_SELECT_MASK (15 << 19) -#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) -#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) -#define SDVOC_GANG_MODE (1 << 16) -#define SDVO_BORDER_ENABLE (1 << 7) -#define SDVOB_PCIE_CONCURRENCY (1 << 3) -#define SDVO_DETECTED (1 << 2) -/* Bits to be preserved when writing */ -#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) -#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) - -/* DVO port control */ -#define DVOA 0x61120 -#define DVOB 0x61140 -#define DVOC 0x61160 -#define DVO_ENABLE (1 << 31) -#define DVO_PIPE_B_SELECT (1 << 30) -#define DVO_PIPE_STALL_UNUSED (0 << 28) -#define DVO_PIPE_STALL (1 << 28) -#define DVO_PIPE_STALL_TV (2 << 28) -#define DVO_PIPE_STALL_MASK (3 << 28) -#define DVO_USE_VGA_SYNC (1 << 15) -#define DVO_DATA_ORDER_I740 (0 << 14) -#define DVO_DATA_ORDER_FP (1 << 14) -#define DVO_VSYNC_DISABLE (1 << 11) -#define DVO_HSYNC_DISABLE (1 << 10) -#define DVO_VSYNC_TRISTATE (1 << 9) -#define DVO_HSYNC_TRISTATE (1 << 8) -#define DVO_BORDER_ENABLE (1 << 7) -#define DVO_DATA_ORDER_GBRG (1 << 6) -#define DVO_DATA_ORDER_RGGB (0 << 6) -#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) -#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) -#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) -#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) -#define DVO_BLANK_ACTIVE_HIGH (1 << 2) -#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ -#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ -#define DVO_PRESERVE_MASK (0x7<<24) -#define DVOA_SRCDIM 0x61124 -#define DVOB_SRCDIM 0x61144 -#define DVOC_SRCDIM 0x61164 -#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 -#define DVO_SRCDIM_VERTICAL_SHIFT 0 - -/* LVDS port control */ -#define LVDS 0x61180 -/* - * Enables the LVDS port. This bit must be set before DPLLs are enabled, as - * the DPLL semantics change when the LVDS is assigned to that pipe. - */ -#define LVDS_PORT_EN (1 << 31) -/* Selects pipe B for LVDS data. Must be set on pre-965. */ -#define LVDS_PIPEB_SELECT (1 << 30) -/* - * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per - * pixel. - */ -#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) -#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) -#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) -/* - * Controls the A3 data pair, which contains the additional LSBs for 24 bit - * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be - * on. - */ -#define LVDS_A3_POWER_MASK (3 << 6) -#define LVDS_A3_POWER_DOWN (0 << 6) -#define LVDS_A3_POWER_UP (3 << 6) -/* - * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP - * is set. - */ -#define LVDS_CLKB_POWER_MASK (3 << 4) -#define LVDS_CLKB_POWER_DOWN (0 << 4) -#define LVDS_CLKB_POWER_UP (3 << 4) -/* - * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 - * setting for whether we are in dual-channel mode. The B3 pair will - * additionally only be powered up when LVDS_A3_POWER_UP is set. - */ -#define LVDS_B0B3_POWER_MASK (3 << 2) -#define LVDS_B0B3_POWER_DOWN (0 << 2) -#define LVDS_B0B3_POWER_UP (3 << 2) - -/* Panel power sequencing */ -#define PP_STATUS 0x61200 -#define PP_ON (1 << 31) -/* - * Indicates that all dependencies of the panel are on: - * - * - PLL enabled - * - pipe enabled - * - LVDS/DVOB/DVOC on - */ -#define PP_READY (1 << 30) -#define PP_SEQUENCE_NONE (0 << 28) -#define PP_SEQUENCE_ON (1 << 28) -#define PP_SEQUENCE_OFF (2 << 28) -#define PP_SEQUENCE_MASK 0x30000000 -#define PP_CONTROL 0x61204 -#define POWER_TARGET_ON (1 << 0) -#define PP_ON_DELAYS 0x61208 -#define PP_OFF_DELAYS 0x6120c -#define PP_DIVISOR 0x61210 - -/* Panel fitting */ -#define PFIT_CONTROL 0x61230 -#define PFIT_ENABLE (1 << 31) -#define PFIT_PIPE_MASK (3 << 29) -#define PFIT_PIPE_SHIFT 29 -#define VERT_INTERP_DISABLE (0 << 10) -#define VERT_INTERP_BILINEAR (1 << 10) -#define VERT_INTERP_MASK (3 << 10) -#define VERT_AUTO_SCALE (1 << 9) -#define HORIZ_INTERP_DISABLE (0 << 6) -#define HORIZ_INTERP_BILINEAR (1 << 6) -#define HORIZ_INTERP_MASK (3 << 6) -#define HORIZ_AUTO_SCALE (1 << 5) -#define PANEL_8TO6_DITHER_ENABLE (1 << 3) -#define PFIT_PGM_RATIOS 0x61234 -#define PFIT_VERT_SCALE_MASK 0xfff00000 -#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 -#define PFIT_AUTO_RATIOS 0x61238 - -/* Backlight control */ -#define BLC_PWM_CTL 0x61254 -#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) -#define BLC_PWM_CTL2 0x61250 /* 965+ only */ -#define BLM_COMBINATION_MODE (1 << 30) -/* - * This is the most significant 15 bits of the number of backlight cycles in a - * complete cycle of the modulated backlight control. - * - * The actual value is this field multiplied by two. - */ -#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) -#define BLM_LEGACY_MODE (1 << 16) -/* - * This is the number of cycles out of the backlight modulation cycle for which - * the backlight is on. - * - * This field must be no greater than the number of cycles in the complete - * backlight modulation cycle. - */ -#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) -#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) - -/* TV port control */ -#define TV_CTL 0x68000 -/** Enables the TV encoder */ -# define TV_ENC_ENABLE (1 << 31) -/** Sources the TV encoder input from pipe B instead of A. */ -# define TV_ENC_PIPEB_SELECT (1 << 30) -/** Outputs composite video (DAC A only) */ -# define TV_ENC_OUTPUT_COMPOSITE (0 << 28) -/** Outputs SVideo video (DAC B/C) */ -# define TV_ENC_OUTPUT_SVIDEO (1 << 28) -/** Outputs Component video (DAC A/B/C) */ -# define TV_ENC_OUTPUT_COMPONENT (2 << 28) -/** Outputs Composite and SVideo (DAC A/B/C) */ -# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) -# define TV_TRILEVEL_SYNC (1 << 21) -/** Enables slow sync generation (945GM only) */ -# define TV_SLOW_SYNC (1 << 20) -/** Selects 4x oversampling for 480i and 576p */ -# define TV_OVERSAMPLE_4X (0 << 18) -/** Selects 2x oversampling for 720p and 1080i */ -# define TV_OVERSAMPLE_2X (1 << 18) -/** Selects no oversampling for 1080p */ -# define TV_OVERSAMPLE_NONE (2 << 18) -/** Selects 8x oversampling */ -# define TV_OVERSAMPLE_8X (3 << 18) -/** Selects progressive mode rather than interlaced */ -# define TV_PROGRESSIVE (1 << 17) -/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ -# define TV_PAL_BURST (1 << 16) -/** Field for setting delay of Y compared to C */ -# define TV_YC_SKEW_MASK (7 << 12) -/** Enables a fix for 480p/576p standard definition modes on the 915GM only */ -# define TV_ENC_SDP_FIX (1 << 11) -/** - * Enables a fix for the 915GM only. - * - * Not sure what it does. - */ -# define TV_ENC_C0_FIX (1 << 10) -/** Bits that must be preserved by software */ -# define TV_CTL_SAVE ((3 << 8) | (3 << 6)) -# define TV_FUSE_STATE_MASK (3 << 4) -/** Read-only state that reports all features enabled */ -# define TV_FUSE_STATE_ENABLED (0 << 4) -/** Read-only state that reports that Macrovision is disabled in hardware*/ -# define TV_FUSE_STATE_NO_MACROVISION (1 << 4) -/** Read-only state that reports that TV-out is disabled in hardware. */ -# define TV_FUSE_STATE_DISABLED (2 << 4) -/** Normal operation */ -# define TV_TEST_MODE_NORMAL (0 << 0) -/** Encoder test pattern 1 - combo pattern */ -# define TV_TEST_MODE_PATTERN_1 (1 << 0) -/** Encoder test pattern 2 - full screen vertical 75% color bars */ -# define TV_TEST_MODE_PATTERN_2 (2 << 0) -/** Encoder test pattern 3 - full screen horizontal 75% color bars */ -# define TV_TEST_MODE_PATTERN_3 (3 << 0) -/** Encoder test pattern 4 - random noise */ -# define TV_TEST_MODE_PATTERN_4 (4 << 0) -/** Encoder test pattern 5 - linear color ramps */ -# define TV_TEST_MODE_PATTERN_5 (5 << 0) -/** - * This test mode forces the DACs to 50% of full output. - * - * This is used for load detection in combination with TVDAC_SENSE_MASK - */ -# define TV_TEST_MODE_MONITOR_DETECT (7 << 0) -# define TV_TEST_MODE_MASK (7 << 0) - -#define TV_DAC 0x68004 -/** - * Reports that DAC state change logic has reported change (RO). - * - * This gets cleared when TV_DAC_STATE_EN is cleared -*/ -# define TVDAC_STATE_CHG (1 << 31) -# define TVDAC_SENSE_MASK (7 << 28) -/** Reports that DAC A voltage is above the detect threshold */ -# define TVDAC_A_SENSE (1 << 30) -/** Reports that DAC B voltage is above the detect threshold */ -# define TVDAC_B_SENSE (1 << 29) -/** Reports that DAC C voltage is above the detect threshold */ -# define TVDAC_C_SENSE (1 << 28) -/** - * Enables DAC state detection logic, for load-based TV detection. - * - * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set - * to off, for load detection to work. - */ -# define TVDAC_STATE_CHG_EN (1 << 27) -/** Sets the DAC A sense value to high */ -# define TVDAC_A_SENSE_CTL (1 << 26) -/** Sets the DAC B sense value to high */ -# define TVDAC_B_SENSE_CTL (1 << 25) -/** Sets the DAC C sense value to high */ -# define TVDAC_C_SENSE_CTL (1 << 24) -/** Overrides the ENC_ENABLE and DAC voltage levels */ -# define DAC_CTL_OVERRIDE (1 << 7) -/** Sets the slew rate. Must be preserved in software */ -# define ENC_TVDAC_SLEW_FAST (1 << 6) -# define DAC_A_1_3_V (0 << 4) -# define DAC_A_1_1_V (1 << 4) -# define DAC_A_0_7_V (2 << 4) -# define DAC_A_OFF (3 << 4) -# define DAC_B_1_3_V (0 << 2) -# define DAC_B_1_1_V (1 << 2) -# define DAC_B_0_7_V (2 << 2) -# define DAC_B_OFF (3 << 2) -# define DAC_C_1_3_V (0 << 0) -# define DAC_C_1_1_V (1 << 0) -# define DAC_C_0_7_V (2 << 0) -# define DAC_C_OFF (3 << 0) - -/** - * CSC coefficients are stored in a floating point format with 9 bits of - * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, - * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with - * -1 (0x3) being the only legal negative value. - */ -#define TV_CSC_Y 0x68010 -# define TV_RY_MASK 0x07ff0000 -# define TV_RY_SHIFT 16 -# define TV_GY_MASK 0x00000fff -# define TV_GY_SHIFT 0 - -#define TV_CSC_Y2 0x68014 -# define TV_BY_MASK 0x07ff0000 -# define TV_BY_SHIFT 16 -/** - * Y attenuation for component video. - * - * Stored in 1.9 fixed point. - */ -# define TV_AY_MASK 0x000003ff -# define TV_AY_SHIFT 0 - -#define TV_CSC_U 0x68018 -# define TV_RU_MASK 0x07ff0000 -# define TV_RU_SHIFT 16 -# define TV_GU_MASK 0x000007ff -# define TV_GU_SHIFT 0 - -#define TV_CSC_U2 0x6801c -# define TV_BU_MASK 0x07ff0000 -# define TV_BU_SHIFT 16 -/** - * U attenuation for component video. - * - * Stored in 1.9 fixed point. - */ -# define TV_AU_MASK 0x000003ff -# define TV_AU_SHIFT 0 - -#define TV_CSC_V 0x68020 -# define TV_RV_MASK 0x0fff0000 -# define TV_RV_SHIFT 16 -# define TV_GV_MASK 0x000007ff -# define TV_GV_SHIFT 0 - -#define TV_CSC_V2 0x68024 -# define TV_BV_MASK 0x07ff0000 -# define TV_BV_SHIFT 16 -/** - * V attenuation for component video. - * - * Stored in 1.9 fixed point. - */ -# define TV_AV_MASK 0x000007ff -# define TV_AV_SHIFT 0 - -#define TV_CLR_KNOBS 0x68028 -/** 2s-complement brightness adjustment */ -# define TV_BRIGHTNESS_MASK 0xff000000 -# define TV_BRIGHTNESS_SHIFT 24 -/** Contrast adjustment, as a 2.6 unsigned floating point number */ -# define TV_CONTRAST_MASK 0x00ff0000 -# define TV_CONTRAST_SHIFT 16 -/** Saturation adjustment, as a 2.6 unsigned floating point number */ -# define TV_SATURATION_MASK 0x0000ff00 -# define TV_SATURATION_SHIFT 8 -/** Hue adjustment, as an integer phase angle in degrees */ -# define TV_HUE_MASK 0x000000ff -# define TV_HUE_SHIFT 0 - -#define TV_CLR_LEVEL 0x6802c -/** Controls the DAC level for black */ -# define TV_BLACK_LEVEL_MASK 0x01ff0000 -# define TV_BLACK_LEVEL_SHIFT 16 -/** Controls the DAC level for blanking */ -# define TV_BLANK_LEVEL_MASK 0x000001ff -# define TV_BLANK_LEVEL_SHIFT 0 - -#define TV_H_CTL_1 0x68030 -/** Number of pixels in the hsync. */ -# define TV_HSYNC_END_MASK 0x1fff0000 -# define TV_HSYNC_END_SHIFT 16 -/** Total number of pixels minus one in the line (display and blanking). */ -# define TV_HTOTAL_MASK 0x00001fff -# define TV_HTOTAL_SHIFT 0 - -#define TV_H_CTL_2 0x68034 -/** Enables the colorburst (needed for non-component color) */ -# define TV_BURST_ENA (1 << 31) -/** Offset of the colorburst from the start of hsync, in pixels minus one. */ -# define TV_HBURST_START_SHIFT 16 -# define TV_HBURST_START_MASK 0x1fff0000 -/** Length of the colorburst */ -# define TV_HBURST_LEN_SHIFT 0 -# define TV_HBURST_LEN_MASK 0x0001fff - -#define TV_H_CTL_3 0x68038 -/** End of hblank, measured in pixels minus one from start of hsync */ -# define TV_HBLANK_END_SHIFT 16 -# define TV_HBLANK_END_MASK 0x1fff0000 -/** Start of hblank, measured in pixels minus one from start of hsync */ -# define TV_HBLANK_START_SHIFT 0 -# define TV_HBLANK_START_MASK 0x0001fff - -#define TV_V_CTL_1 0x6803c -/** XXX */ -# define TV_NBR_END_SHIFT 16 -# define TV_NBR_END_MASK 0x07ff0000 -/** XXX */ -# define TV_VI_END_F1_SHIFT 8 -# define TV_VI_END_F1_MASK 0x00003f00 -/** XXX */ -# define TV_VI_END_F2_SHIFT 0 -# define TV_VI_END_F2_MASK 0x0000003f - -#define TV_V_CTL_2 0x68040 -/** Length of vsync, in half lines */ -# define TV_VSYNC_LEN_MASK 0x07ff0000 -# define TV_VSYNC_LEN_SHIFT 16 -/** Offset of the start of vsync in field 1, measured in one less than the - * number of half lines. - */ -# define TV_VSYNC_START_F1_MASK 0x00007f00 -# define TV_VSYNC_START_F1_SHIFT 8 -/** - * Offset of the start of vsync in field 2, measured in one less than the - * number of half lines. - */ -# define TV_VSYNC_START_F2_MASK 0x0000007f -# define TV_VSYNC_START_F2_SHIFT 0 - -#define TV_V_CTL_3 0x68044 -/** Enables generation of the equalization signal */ -# define TV_EQUAL_ENA (1 << 31) -/** Length of vsync, in half lines */ -# define TV_VEQ_LEN_MASK 0x007f0000 -# define TV_VEQ_LEN_SHIFT 16 -/** Offset of the start of equalization in field 1, measured in one less than - * the number of half lines. - */ -# define TV_VEQ_START_F1_MASK 0x0007f00 -# define TV_VEQ_START_F1_SHIFT 8 -/** - * Offset of the start of equalization in field 2, measured in one less than - * the number of half lines. - */ -# define TV_VEQ_START_F2_MASK 0x000007f -# define TV_VEQ_START_F2_SHIFT 0 - -#define TV_V_CTL_4 0x68048 -/** - * Offset to start of vertical colorburst, measured in one less than the - * number of lines from vertical start. - */ -# define TV_VBURST_START_F1_MASK 0x003f0000 -# define TV_VBURST_START_F1_SHIFT 16 -/** - * Offset to the end of vertical colorburst, measured in one less than the - * number of lines from the start of NBR. - */ -# define TV_VBURST_END_F1_MASK 0x000000ff -# define TV_VBURST_END_F1_SHIFT 0 - -#define TV_V_CTL_5 0x6804c -/** - * Offset to start of vertical colorburst, measured in one less than the - * number of lines from vertical start. - */ -# define TV_VBURST_START_F2_MASK 0x003f0000 -# define TV_VBURST_START_F2_SHIFT 16 -/** - * Offset to the end of vertical colorburst, measured in one less than the - * number of lines from the start of NBR. - */ -# define TV_VBURST_END_F2_MASK 0x000000ff -# define TV_VBURST_END_F2_SHIFT 0 - -#define TV_V_CTL_6 0x68050 -/** - * Offset to start of vertical colorburst, measured in one less than the - * number of lines from vertical start. - */ -# define TV_VBURST_START_F3_MASK 0x003f0000 -# define TV_VBURST_START_F3_SHIFT 16 -/** - * Offset to the end of vertical colorburst, measured in one less than the - * number of lines from the start of NBR. - */ -# define TV_VBURST_END_F3_MASK 0x000000ff -# define TV_VBURST_END_F3_SHIFT 0 - -#define TV_V_CTL_7 0x68054 -/** - * Offset to start of vertical colorburst, measured in one less than the - * number of lines from vertical start. - */ -# define TV_VBURST_START_F4_MASK 0x003f0000 -# define TV_VBURST_START_F4_SHIFT 16 -/** - * Offset to the end of vertical colorburst, measured in one less than the - * number of lines from the start of NBR. - */ -# define TV_VBURST_END_F4_MASK 0x000000ff -# define TV_VBURST_END_F4_SHIFT 0 - -#define TV_SC_CTL_1 0x68060 -/** Turns on the first subcarrier phase generation DDA */ -# define TV_SC_DDA1_EN (1 << 31) -/** Turns on the first subcarrier phase generation DDA */ -# define TV_SC_DDA2_EN (1 << 30) -/** Turns on the first subcarrier phase generation DDA */ -# define TV_SC_DDA3_EN (1 << 29) -/** Sets the subcarrier DDA to reset frequency every other field */ -# define TV_SC_RESET_EVERY_2 (0 << 24) -/** Sets the subcarrier DDA to reset frequency every fourth field */ -# define TV_SC_RESET_EVERY_4 (1 << 24) -/** Sets the subcarrier DDA to reset frequency every eighth field */ -# define TV_SC_RESET_EVERY_8 (2 << 24) -/** Sets the subcarrier DDA to never reset the frequency */ -# define TV_SC_RESET_NEVER (3 << 24) -/** Sets the peak amplitude of the colorburst.*/ -# define TV_BURST_LEVEL_MASK 0x00ff0000 -# define TV_BURST_LEVEL_SHIFT 16 -/** Sets the increment of the first subcarrier phase generation DDA */ -# define TV_SCDDA1_INC_MASK 0x00000fff -# define TV_SCDDA1_INC_SHIFT 0 - -#define TV_SC_CTL_2 0x68064 -/** Sets the rollover for the second subcarrier phase generation DDA */ -# define TV_SCDDA2_SIZE_MASK 0x7fff0000 -# define TV_SCDDA2_SIZE_SHIFT 16 -/** Sets the increent of the second subcarrier phase generation DDA */ -# define TV_SCDDA2_INC_MASK 0x00007fff -# define TV_SCDDA2_INC_SHIFT 0 - -#define TV_SC_CTL_3 0x68068 -/** Sets the rollover for the third subcarrier phase generation DDA */ -# define TV_SCDDA3_SIZE_MASK 0x7fff0000 -# define TV_SCDDA3_SIZE_SHIFT 16 -/** Sets the increent of the third subcarrier phase generation DDA */ -# define TV_SCDDA3_INC_MASK 0x00007fff -# define TV_SCDDA3_INC_SHIFT 0 - -#define TV_WIN_POS 0x68070 -/** X coordinate of the display from the start of horizontal active */ -# define TV_XPOS_MASK 0x1fff0000 -# define TV_XPOS_SHIFT 16 -/** Y coordinate of the display from the start of vertical active (NBR) */ -# define TV_YPOS_MASK 0x00000fff -# define TV_YPOS_SHIFT 0 - -#define TV_WIN_SIZE 0x68074 -/** Horizontal size of the display window, measured in pixels*/ -# define TV_XSIZE_MASK 0x1fff0000 -# define TV_XSIZE_SHIFT 16 -/** - * Vertical size of the display window, measured in pixels. - * - * Must be even for interlaced modes. - */ -# define TV_YSIZE_MASK 0x00000fff -# define TV_YSIZE_SHIFT 0 - -#define TV_FILTER_CTL_1 0x68080 -/** - * Enables automatic scaling calculation. - * - * If set, the rest of the registers are ignored, and the calculated values can - * be read back from the register. - */ -# define TV_AUTO_SCALE (1 << 31) -/** - * Disables the vertical filter. - * - * This is required on modes more than 1024 pixels wide */ -# define TV_V_FILTER_BYPASS (1 << 29) -/** Enables adaptive vertical filtering */ -# define TV_VADAPT (1 << 28) -# define TV_VADAPT_MODE_MASK (3 << 26) -/** Selects the least adaptive vertical filtering mode */ -# define TV_VADAPT_MODE_LEAST (0 << 26) -/** Selects the moderately adaptive vertical filtering mode */ -# define TV_VADAPT_MODE_MODERATE (1 << 26) -/** Selects the most adaptive vertical filtering mode */ -# define TV_VADAPT_MODE_MOST (3 << 26) -/** - * Sets the horizontal scaling factor. - * - * This should be the fractional part of the horizontal scaling factor divided - * by the oversampling rate. TV_HSCALE should be less than 1, and set to: - * - * (src width - 1) / ((oversample * dest width) - 1) - */ -# define TV_HSCALE_FRAC_MASK 0x00003fff -# define TV_HSCALE_FRAC_SHIFT 0 - -#define TV_FILTER_CTL_2 0x68084 -/** - * Sets the integer part of the 3.15 fixed-point vertical scaling factor. - * - * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) - */ -# define TV_VSCALE_INT_MASK 0x00038000 -# define TV_VSCALE_INT_SHIFT 15 -/** - * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. - * - * \sa TV_VSCALE_INT_MASK - */ -# define TV_VSCALE_FRAC_MASK 0x00007fff -# define TV_VSCALE_FRAC_SHIFT 0 - -#define TV_FILTER_CTL_3 0x68088 -/** - * Sets the integer part of the 3.15 fixed-point vertical scaling factor. - * - * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) - * - * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. - */ -# define TV_VSCALE_IP_INT_MASK 0x00038000 -# define TV_VSCALE_IP_INT_SHIFT 15 -/** - * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. - * - * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. - * - * \sa TV_VSCALE_IP_INT_MASK - */ -# define TV_VSCALE_IP_FRAC_MASK 0x00007fff -# define TV_VSCALE_IP_FRAC_SHIFT 0 - -#define TV_CC_CONTROL 0x68090 -# define TV_CC_ENABLE (1 << 31) -/** - * Specifies which field to send the CC data in. - * - * CC data is usually sent in field 0. - */ -# define TV_CC_FID_MASK (1 << 27) -# define TV_CC_FID_SHIFT 27 -/** Sets the horizontal position of the CC data. Usually 135. */ -# define TV_CC_HOFF_MASK 0x03ff0000 -# define TV_CC_HOFF_SHIFT 16 -/** Sets the vertical position of the CC data. Usually 21 */ -# define TV_CC_LINE_MASK 0x0000003f -# define TV_CC_LINE_SHIFT 0 - -#define TV_CC_DATA 0x68094 -# define TV_CC_RDY (1 << 31) -/** Second word of CC data to be transmitted. */ -# define TV_CC_DATA_2_MASK 0x007f0000 -# define TV_CC_DATA_2_SHIFT 16 -/** First word of CC data to be transmitted. */ -# define TV_CC_DATA_1_MASK 0x0000007f -# define TV_CC_DATA_1_SHIFT 0 - -#define TV_H_LUMA_0 0x68100 -#define TV_H_LUMA_59 0x681ec -#define TV_H_CHROMA_0 0x68200 -#define TV_H_CHROMA_59 0x682ec -#define TV_V_LUMA_0 0x68300 -#define TV_V_LUMA_42 0x683a8 -#define TV_V_CHROMA_0 0x68400 -#define TV_V_CHROMA_42 0x684a8 - -/* Display & cursor control */ - -/* Pipe A */ -#define PIPEADSL 0x70000 -#define PIPEACONF 0x70008 -#define PIPEACONF_ENABLE (1<<31) -#define PIPEACONF_DISABLE 0 -#define PIPEACONF_DOUBLE_WIDE (1<<30) -#define I965_PIPECONF_ACTIVE (1<<30) -#define PIPEACONF_SINGLE_WIDE 0 -#define PIPEACONF_PIPE_UNLOCKED 0 -#define PIPEACONF_PIPE_LOCKED (1<<25) -#define PIPEACONF_PALETTE 0 -#define PIPEACONF_GAMMA (1<<24) -#define PIPECONF_FORCE_BORDER (1<<25) -#define PIPECONF_PROGRESSIVE (0 << 21) -#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) -#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) -#define PIPEASTAT 0x70024 -#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) -#define PIPE_CRC_ERROR_ENABLE (1UL<<29) -#define PIPE_CRC_DONE_ENABLE (1UL<<28) -#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) -#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) -#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) -#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) -#define PIPE_DPST_EVENT_ENABLE (1UL<<23) -#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) -#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) -#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) -#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ -#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ -#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) -#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) -#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) -#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) -#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) -#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) -#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) -#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) -#define PIPE_DPST_EVENT_STATUS (1UL<<7) -#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) -#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) -#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) -#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ -#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ -#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) -#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) - -#define DSPARB 0x70030 -#define DSPARB_CSTART_MASK (0x7f << 7) -#define DSPARB_CSTART_SHIFT 7 -#define DSPARB_BSTART_MASK (0x7f) -#define DSPARB_BSTART_SHIFT 0 -/* - * The two pipe frame counter registers are not synchronized, so - * reading a stable value is somewhat tricky. The following code - * should work: - * - * do { - * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> - * PIPE_FRAME_HIGH_SHIFT; - * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> - * PIPE_FRAME_LOW_SHIFT); - * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> - * PIPE_FRAME_HIGH_SHIFT); - * } while (high1 != high2); - * frame = (high1 << 8) | low1; - */ -#define PIPEAFRAMEHIGH 0x70040 -#define PIPE_FRAME_HIGH_MASK 0x0000ffff -#define PIPE_FRAME_HIGH_SHIFT 0 -#define PIPEAFRAMEPIXEL 0x70044 -#define PIPE_FRAME_LOW_MASK 0xff000000 -#define PIPE_FRAME_LOW_SHIFT 24 -#define PIPE_PIXEL_MASK 0x00ffffff -#define PIPE_PIXEL_SHIFT 0 -/* GM45+ just has to be different */ -#define PIPEA_FRMCOUNT_GM45 0x70040 -#define PIPEA_FLIPCOUNT_GM45 0x70044 - -/* Cursor A & B regs */ -#define CURACNTR 0x70080 -#define CURSOR_MODE_DISABLE 0x00 -#define CURSOR_MODE_64_32B_AX 0x07 -#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) -#define MCURSOR_GAMMA_ENABLE (1 << 26) -#define CURABASE 0x70084 -#define CURAPOS 0x70088 -#define CURSOR_POS_MASK 0x007FF -#define CURSOR_POS_SIGN 0x8000 -#define CURSOR_X_SHIFT 0 -#define CURSOR_Y_SHIFT 16 -#define CURBCNTR 0x700c0 -#define CURBBASE 0x700c4 -#define CURBPOS 0x700c8 - -/* Display A control */ -#define DSPACNTR 0x70180 -#define DISPLAY_PLANE_ENABLE (1<<31) -#define DISPLAY_PLANE_DISABLE 0 -#define DISPPLANE_GAMMA_ENABLE (1<<30) -#define DISPPLANE_GAMMA_DISABLE 0 -#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) -#define DISPPLANE_8BPP (0x2<<26) -#define DISPPLANE_15_16BPP (0x4<<26) -#define DISPPLANE_16BPP (0x5<<26) -#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) -#define DISPPLANE_32BPP (0x7<<26) -#define DISPPLANE_STEREO_ENABLE (1<<25) -#define DISPPLANE_STEREO_DISABLE 0 -#define DISPPLANE_SEL_PIPE_MASK (1<<24) -#define DISPPLANE_SEL_PIPE_A 0 -#define DISPPLANE_SEL_PIPE_B (1<<24) -#define DISPPLANE_SRC_KEY_ENABLE (1<<22) -#define DISPPLANE_SRC_KEY_DISABLE 0 -#define DISPPLANE_LINE_DOUBLE (1<<20) -#define DISPPLANE_NO_LINE_DOUBLE 0 -#define DISPPLANE_STEREO_POLARITY_FIRST 0 -#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) -#define DSPAADDR 0x70184 -#define DSPASTRIDE 0x70188 -#define DSPAPOS 0x7018C /* reserved */ -#define DSPASIZE 0x70190 -#define DSPASURF 0x7019C /* 965+ only */ -#define DSPATILEOFF 0x701A4 /* 965+ only */ - -/* VBIOS flags */ -#define SWF00 0x71410 -#define SWF01 0x71414 -#define SWF02 0x71418 -#define SWF03 0x7141c -#define SWF04 0x71420 -#define SWF05 0x71424 -#define SWF06 0x71428 -#define SWF10 0x70410 -#define SWF11 0x70414 -#define SWF14 0x71420 -#define SWF30 0x72414 -#define SWF31 0x72418 -#define SWF32 0x7241c - -/* Pipe B */ -#define PIPEBDSL 0x71000 -#define PIPEBCONF 0x71008 -#define PIPEBSTAT 0x71024 -#define PIPEBFRAMEHIGH 0x71040 -#define PIPEBFRAMEPIXEL 0x71044 -#define PIPEB_FRMCOUNT_GM45 0x71040 -#define PIPEB_FLIPCOUNT_GM45 0x71044 - -/* Display B control */ -#define DSPBCNTR 0x71180 -#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) -#define DISPPLANE_ALPHA_TRANS_DISABLE 0 -#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 -#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) -#define DSPBADDR 0x71184 -#define DSPBSTRIDE 0x71188 -#define DSPBPOS 0x7118C -#define DSPBSIZE 0x71190 -#define DSPBSURF 0x7119C -#define DSPBTILEOFF 0x711A4 - -/* VBIOS regs */ -#define VGACNTRL 0x71400 -# define VGA_DISP_DISABLE (1 << 31) -# define VGA_2X_MODE (1 << 30) -# define VGA_PIPE_B_SELECT (1 << 29) - -#endif /* _I915_REG_H_ */ diff --git a/shared-core/i915_suspend.c b/shared-core/i915_suspend.c deleted file mode 100644 index 5e759b15..00000000 --- a/shared-core/i915_suspend.c +++ /dev/null @@ -1,520 +0,0 @@ -/* i915_suspend.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- - */ -/* - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "drmP.h" -#include "drm.h" -#include "i915_drm.h" -#include "i915_drv.h" - -static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - - if (pipe == PIPE_A) - return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE); - else - return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE); -} - -static void i915_save_palette(struct drm_device *dev, enum pipe pipe) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); - u32 *array; - int i; - - if (!i915_pipe_enabled(dev, pipe)) - return; - - if (pipe == PIPE_A) - array = dev_priv->save_palette_a; - else - array = dev_priv->save_palette_b; - - for(i = 0; i < 256; i++) - array[i] = I915_READ(reg + (i << 2)); -} - -static void i915_restore_palette(struct drm_device *dev, enum pipe pipe) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); - u32 *array; - int i; - - if (!i915_pipe_enabled(dev, pipe)) - return; - - if (pipe == PIPE_A) - array = dev_priv->save_palette_a; - else - array = dev_priv->save_palette_b; - - for(i = 0; i < 256; i++) - I915_WRITE(reg + (i << 2), array[i]); -} - -static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - - I915_WRITE8(index_port, reg); - return I915_READ8(data_port); -} - -static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - - I915_READ8(st01); - I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); - return I915_READ8(VGA_AR_DATA_READ); -} - -static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - - I915_READ8(st01); - I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); - I915_WRITE8(VGA_AR_DATA_WRITE, val); -} - -static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - - I915_WRITE8(index_port, reg); - I915_WRITE8(data_port, val); -} - -static void i915_save_vga(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - int i; - u16 cr_index, cr_data, st01; - - /* VGA color palette registers */ - dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK); - /* DACCRX automatically increments during read */ - I915_WRITE8(VGA_DACRX, 0); - /* Read 3 bytes of color data from each index */ - for (i = 0; i < 256 * 3; i++) - dev_priv->saveDACDATA[i] = I915_READ8(VGA_DACDATA); - - /* MSR bits */ - dev_priv->saveMSR = I915_READ8(VGA_MSR_READ); - if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) { - cr_index = VGA_CR_INDEX_CGA; - cr_data = VGA_CR_DATA_CGA; - st01 = VGA_ST01_CGA; - } else { - cr_index = VGA_CR_INDEX_MDA; - cr_data = VGA_CR_DATA_MDA; - st01 = VGA_ST01_MDA; - } - - /* CRT controller regs */ - i915_write_indexed(dev, cr_index, cr_data, 0x11, - i915_read_indexed(dev, cr_index, cr_data, 0x11) & - (~0x80)); - for (i = 0; i <= 0x24; i++) - dev_priv->saveCR[i] = - i915_read_indexed(dev, cr_index, cr_data, i); - /* Make sure we don't turn off CR group 0 writes */ - dev_priv->saveCR[0x11] &= ~0x80; - - /* Attribute controller registers */ - I915_READ8(st01); - dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX); - for (i = 0; i <= 0x14; i++) - dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0); - I915_READ8(st01); - I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX); - I915_READ8(st01); - - /* Graphics controller registers */ - for (i = 0; i < 9; i++) - dev_priv->saveGR[i] = - i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i); - - dev_priv->saveGR[0x10] = - i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10); - dev_priv->saveGR[0x11] = - i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11); - dev_priv->saveGR[0x18] = - i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18); - - /* Sequencer registers */ - for (i = 0; i < 8; i++) - dev_priv->saveSR[i] = - i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i); -} - -static void i915_restore_vga(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - int i; - u16 cr_index, cr_data, st01; - - /* MSR bits */ - I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR); - if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) { - cr_index = VGA_CR_INDEX_CGA; - cr_data = VGA_CR_DATA_CGA; - st01 = VGA_ST01_CGA; - } else { - cr_index = VGA_CR_INDEX_MDA; - cr_data = VGA_CR_DATA_MDA; - st01 = VGA_ST01_MDA; - } - - /* Sequencer registers, don't write SR07 */ - for (i = 0; i < 7; i++) - i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i, - dev_priv->saveSR[i]); - - /* CRT controller regs */ - /* Enable CR group 0 writes */ - i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]); - for (i = 0; i <= 0x24; i++) - i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]); - - /* Graphics controller regs */ - for (i = 0; i < 9; i++) - i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i, - dev_priv->saveGR[i]); - - i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10, - dev_priv->saveGR[0x10]); - i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11, - dev_priv->saveGR[0x11]); - i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18, - dev_priv->saveGR[0x18]); - - /* Attribute controller registers */ - I915_READ8(st01); /* switch back to index mode */ - for (i = 0; i <= 0x14; i++) - i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0); - I915_READ8(st01); /* switch back to index mode */ - I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20); - I915_READ8(st01); - - /* VGA color palette registers */ - I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK); - /* DACCRX automatically increments during read */ - I915_WRITE8(VGA_DACWX, 0); - /* Read 3 bytes of color data from each index */ - for (i = 0; i < 256 * 3; i++) - I915_WRITE8(VGA_DACDATA, dev_priv->saveDACDATA[i]); - -} - -int i915_save_state(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - int i; - -#if defined(__FreeBSD__) - dev_priv->saveLBB = (u8) pci_read_config(dev->device, LBB, 1); -#else - pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); -#endif - - /* Display arbitration control */ - dev_priv->saveDSPARB = I915_READ(DSPARB); - - /* Pipe & plane A info */ - dev_priv->savePIPEACONF = I915_READ(PIPEACONF); - dev_priv->savePIPEASRC = I915_READ(PIPEASRC); - dev_priv->saveFPA0 = I915_READ(FPA0); - dev_priv->saveFPA1 = I915_READ(FPA1); - dev_priv->saveDPLL_A = I915_READ(DPLL_A); - if (IS_I965G(dev)) - dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); - dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A); - dev_priv->saveHBLANK_A = I915_READ(HBLANK_A); - dev_priv->saveHSYNC_A = I915_READ(HSYNC_A); - dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A); - dev_priv->saveVBLANK_A = I915_READ(VBLANK_A); - dev_priv->saveVSYNC_A = I915_READ(VSYNC_A); - dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); - - dev_priv->saveDSPACNTR = I915_READ(DSPACNTR); - dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE); - dev_priv->saveDSPASIZE = I915_READ(DSPASIZE); - dev_priv->saveDSPAPOS = I915_READ(DSPAPOS); - dev_priv->saveDSPAADDR = I915_READ(DSPAADDR); - if (IS_I965G(dev)) { - dev_priv->saveDSPASURF = I915_READ(DSPASURF); - dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF); - } - i915_save_palette(dev, PIPE_A); - dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT); - - /* Pipe & plane B info */ - dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); - dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC); - dev_priv->saveFPB0 = I915_READ(FPB0); - dev_priv->saveFPB1 = I915_READ(FPB1); - dev_priv->saveDPLL_B = I915_READ(DPLL_B); - if (IS_I965G(dev)) - dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD); - dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B); - dev_priv->saveHBLANK_B = I915_READ(HBLANK_B); - dev_priv->saveHSYNC_B = I915_READ(HSYNC_B); - dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B); - dev_priv->saveVBLANK_B = I915_READ(VBLANK_B); - dev_priv->saveVSYNC_B = I915_READ(VSYNC_B); - dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); - - dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR); - dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE); - dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE); - dev_priv->saveDSPBPOS = I915_READ(DSPBPOS); - dev_priv->saveDSPBADDR = I915_READ(DSPBADDR); - if (IS_I965GM(dev) || IS_GM45(dev)) { - dev_priv->saveDSPBSURF = I915_READ(DSPBSURF); - dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF); - } - i915_save_palette(dev, PIPE_B); - dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT); - - /* CRT state */ - dev_priv->saveADPA = I915_READ(ADPA); - - /* LVDS state */ - dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL); - dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); - dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); - if (IS_I965G(dev)) - dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); - if (IS_MOBILE(dev) && !IS_I830(dev)) - dev_priv->saveLVDS = I915_READ(LVDS); - if (!IS_I830(dev) && !IS_845G(dev)) - dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); - dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); - dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); - dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR); - - /* FIXME: save TV & SDVO state */ - - /* FBC state */ - dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE); - dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE); - dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); - dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); - - /* Interrupt state */ - dev_priv->saveIIR = I915_READ(IIR); - dev_priv->saveIER = I915_READ(IER); - dev_priv->saveIMR = I915_READ(IMR); - - /* VGA state */ - dev_priv->saveVGA0 = I915_READ(VGA0); - dev_priv->saveVGA1 = I915_READ(VGA1); - dev_priv->saveVGA_PD = I915_READ(VGA_PD); - dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); - - /* Clock gating state */ - dev_priv->saveD_STATE = I915_READ(D_STATE); - dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS); - - /* Cache mode state */ - dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); - - /* Memory Arbitration state */ - dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); - - /* Scratch space */ - for (i = 0; i < 16; i++) { - dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2)); - dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2)); - } - for (i = 0; i < 3; i++) - dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2)); - - i915_save_vga(dev); - - return 0; -} - -int i915_restore_state(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - int i; - -#if defined(__FreeBSD__) - pci_write_config(dev->device, LBB, dev_priv->saveLBB, 1); -#else - pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); -#endif - - I915_WRITE(DSPARB, dev_priv->saveDSPARB); - - /* Pipe & plane A info */ - /* Prime the clock */ - if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { - I915_WRITE(DPLL_A, dev_priv->saveDPLL_A & - ~DPLL_VCO_ENABLE); - DRM_UDELAY(150); - } - I915_WRITE(FPA0, dev_priv->saveFPA0); - I915_WRITE(FPA1, dev_priv->saveFPA1); - /* Actually enable it */ - I915_WRITE(DPLL_A, dev_priv->saveDPLL_A); - DRM_UDELAY(150); - if (IS_I965G(dev)) - I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); - DRM_UDELAY(150); - - /* Restore mode */ - I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A); - I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A); - I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A); - I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A); - I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A); - I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A); - I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A); - - /* Restore plane info */ - I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE); - I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS); - I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC); - I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR); - I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE); - if (IS_I965G(dev)) { - I915_WRITE(DSPASURF, dev_priv->saveDSPASURF); - I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF); - } - - I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF); - - i915_restore_palette(dev, PIPE_A); - /* Enable the plane */ - I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR); - I915_WRITE(DSPAADDR, I915_READ(DSPAADDR)); - - /* Pipe & plane B info */ - if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { - I915_WRITE(DPLL_B, dev_priv->saveDPLL_B & - ~DPLL_VCO_ENABLE); - DRM_UDELAY(150); - } - I915_WRITE(FPB0, dev_priv->saveFPB0); - I915_WRITE(FPB1, dev_priv->saveFPB1); - /* Actually enable it */ - I915_WRITE(DPLL_B, dev_priv->saveDPLL_B); - DRM_UDELAY(150); - if (IS_I965G(dev)) - I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD); - DRM_UDELAY(150); - - /* Restore mode */ - I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B); - I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B); - I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B); - I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B); - I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B); - I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B); - I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B); - - /* Restore plane info */ - I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE); - I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS); - I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC); - I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR); - I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE); - if (IS_I965G(dev)) { - I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF); - I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF); - } - - I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF); - - i915_restore_palette(dev, PIPE_B); - /* Enable the plane */ - I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR); - I915_WRITE(DSPBADDR, I915_READ(DSPBADDR)); - - /* CRT state */ - I915_WRITE(ADPA, dev_priv->saveADPA); - - /* LVDS state */ - if (IS_I965G(dev)) - I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); - if (IS_MOBILE(dev) && !IS_I830(dev)) - I915_WRITE(LVDS, dev_priv->saveLVDS); - if (!IS_I830(dev) && !IS_845G(dev)) - I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL); - - I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); - I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); - I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); - I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); - I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR); - I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); - - /* FIXME: restore TV & SDVO state */ - - /* FBC info */ - I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE); - I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE); - I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2); - I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL); - - /* VGA state */ - I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); - I915_WRITE(VGA0, dev_priv->saveVGA0); - I915_WRITE(VGA1, dev_priv->saveVGA1); - I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); - DRM_UDELAY(150); - - /* Clock gating state */ - I915_WRITE (D_STATE, dev_priv->saveD_STATE); - I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS); - - /* Cache mode state */ - I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); - - /* Memory arbitration state */ - I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000); - - for (i = 0; i < 16; i++) { - I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]); - I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]); - } - for (i = 0; i < 3; i++) - I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]); - - i915_restore_vga(dev); - - return 0; -} - diff --git a/shared-core/imagine_drv.h b/shared-core/imagine_drv.h deleted file mode 100644 index ebec3067..00000000 --- a/shared-core/imagine_drv.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright 2005 Adam Jackson. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -/* derived from tdfx_drv.h */ - -#ifndef __IMAGINE_DRV_H__ -#define __IMAGINE_DRV_H__ - -#define DRIVER_AUTHOR "Adam Jackson" -#define DRIVER_NAME "imagine" -#define DRIVER_DESC "#9 Imagine128 and Ticket 2 Ride" -#define DRIVER_DATE "20050328" -#define DRIVER_MAJOR 0 -#define DRIVER_MINOR 0 -#define DRIVER_PATCHLEVEL 1 - -enum imagine_family { - IMAGINE_128, - IMAGINE_128_2, - IMAGINE_T2R, - IMAGINE_REV4 -}; - -#endif /* __IMAGINE_DRV_H__ */ diff --git a/shared-core/mach64_dma.c b/shared-core/mach64_dma.c deleted file mode 100644 index 3f2367ba..00000000 --- a/shared-core/mach64_dma.c +++ /dev/null @@ -1,1778 +0,0 @@ -/* mach64_dma.c -- DMA support for mach64 (Rage Pro) driver -*- linux-c -*- */ -/** - * \file mach64_dma.c - * DMA support for mach64 (Rage Pro) driver - * - * \author Gareth Hughes - * \author Frank C. Earl - * \author Leif Delgass - * \author José Fonseca - */ - -/* - * Copyright 2000 Gareth Hughes - * Copyright 2002 Frank C. Earl - * Copyright 2002-2003 Leif Delgass - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "drmP.h" -#include "drm.h" -#include "mach64_drm.h" -#include "mach64_drv.h" - -/*******************************************************************/ -/** \name Engine, FIFO control */ -/*@{*/ - -/** - * Waits for free entries in the FIFO. - * - * \note Most writes to Mach64 registers are automatically routed through - * command FIFO which is 16 entry deep. Prior to writing to any draw engine - * register one has to ensure that enough FIFO entries are available by calling - * this function. Failure to do so may cause the engine to lock. - * - * \param dev_priv pointer to device private data structure. - * \param entries number of free entries in the FIFO to wait for. - * - * \returns zero on success, or -EBUSY if the timeout (specificed by - * drm_mach64_private::usec_timeout) occurs. - */ -int mach64_do_wait_for_fifo(drm_mach64_private_t *dev_priv, int entries) -{ - int slots = 0, i; - - for (i = 0; i < dev_priv->usec_timeout; i++) { - slots = (MACH64_READ(MACH64_FIFO_STAT) & MACH64_FIFO_SLOT_MASK); - if (slots <= (0x8000 >> entries)) - return 0; - DRM_UDELAY(1); - } - - DRM_INFO("failed! slots=%d entries=%d\n", slots, entries); - return -EBUSY; -} - -/** - * Wait for the draw engine to be idle. - */ -int mach64_do_wait_for_idle(drm_mach64_private_t *dev_priv) -{ - int i, ret; - - ret = mach64_do_wait_for_fifo(dev_priv, 16); - if (ret < 0) - return ret; - - for (i = 0; i < dev_priv->usec_timeout; i++) { - if (!(MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE)) - return 0; - DRM_UDELAY(1); - } - - DRM_INFO("failed! GUI_STAT=0x%08x\n", MACH64_READ(MACH64_GUI_STAT)); - mach64_dump_ring_info(dev_priv); - return -EBUSY; -} - -/** - * Wait for free entries in the ring buffer. - * - * The Mach64 bus master can be configured to act as a virtual FIFO, using a - * circular buffer (commonly referred as "ring buffer" in other drivers) with - * pointers to engine commands. This allows the CPU to do other things while - * the graphics engine is busy, i.e., DMA mode. - * - * This function should be called before writing new entries to the ring - * buffer. - * - * \param dev_priv pointer to device private data structure. - * \param n number of free entries in the ring buffer to wait for. - * - * \returns zero on success, or -EBUSY if the timeout (specificed by - * drm_mach64_private_t::usec_timeout) occurs. - * - * \sa mach64_dump_ring_info() - */ -int mach64_wait_ring(drm_mach64_private_t *dev_priv, int n) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - int i; - - for (i = 0; i < dev_priv->usec_timeout; i++) { - mach64_update_ring_snapshot(dev_priv); - if (ring->space >= n) { - if (i > 0) - DRM_DEBUG("%d usecs\n", i); - return 0; - } - DRM_UDELAY(1); - } - - /* FIXME: This is being ignored... */ - DRM_ERROR("failed!\n"); - mach64_dump_ring_info(dev_priv); - return -EBUSY; -} - -/** - * Wait until all DMA requests have been processed... - * - * \sa mach64_wait_ring() - */ -static int mach64_ring_idle(drm_mach64_private_t *dev_priv) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - u32 head; - int i; - - head = ring->head; - i = 0; - while (i < dev_priv->usec_timeout) { - mach64_update_ring_snapshot(dev_priv); - if (ring->head == ring->tail && - !(MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE)) { - if (i > 0) - DRM_DEBUG("%d usecs\n", i); - return 0; - } - if (ring->head == head) { - ++i; - } else { - head = ring->head; - i = 0; - } - DRM_UDELAY(1); - } - - DRM_INFO("failed! GUI_STAT=0x%08x\n", MACH64_READ(MACH64_GUI_STAT)); - mach64_dump_ring_info(dev_priv); - return -EBUSY; -} - -/** - * Reset the the ring buffer descriptors. - * - * \sa mach64_do_engine_reset() - */ -static void mach64_ring_reset(drm_mach64_private_t *dev_priv) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - - mach64_do_release_used_buffers(dev_priv); - ring->head_addr = ring->start_addr; - ring->head = ring->tail = 0; - ring->space = ring->size; - - MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD, - ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB); - - dev_priv->ring_running = 0; -} - -/** - * Ensure the all the queued commands will be processed. - */ -int mach64_do_dma_flush(drm_mach64_private_t *dev_priv) -{ - /* FIXME: It's not necessary to wait for idle when flushing - * we just need to ensure the ring will be completely processed - * in finite time without another ioctl - */ - return mach64_ring_idle(dev_priv); -} - -/** - * Stop all DMA activity. - */ -int mach64_do_dma_idle(drm_mach64_private_t *dev_priv) -{ - int ret; - - /* wait for completion */ - if ((ret = mach64_ring_idle(dev_priv)) < 0) { - DRM_ERROR("failed BM_GUI_TABLE=0x%08x tail: %u\n", - MACH64_READ(MACH64_BM_GUI_TABLE), - dev_priv->ring.tail); - return ret; - } - - mach64_ring_stop(dev_priv); - - /* clean up after pass */ - mach64_do_release_used_buffers(dev_priv); - return 0; -} - -/** - * Reset the engine. This will stop the DMA if it is running. - */ -int mach64_do_engine_reset(drm_mach64_private_t *dev_priv) -{ - u32 tmp; - - DRM_DEBUG("\n"); - - /* Kill off any outstanding DMA transfers. - */ - tmp = MACH64_READ(MACH64_BUS_CNTL); - MACH64_WRITE(MACH64_BUS_CNTL, tmp | MACH64_BUS_MASTER_DIS); - - /* Reset the GUI engine (high to low transition). - */ - tmp = MACH64_READ(MACH64_GEN_TEST_CNTL); - MACH64_WRITE(MACH64_GEN_TEST_CNTL, tmp & ~MACH64_GUI_ENGINE_ENABLE); - /* Enable the GUI engine - */ - tmp = MACH64_READ(MACH64_GEN_TEST_CNTL); - MACH64_WRITE(MACH64_GEN_TEST_CNTL, tmp | MACH64_GUI_ENGINE_ENABLE); - - /* ensure engine is not locked up by clearing any FIFO or HOST errors - */ - tmp = MACH64_READ(MACH64_BUS_CNTL); - MACH64_WRITE(MACH64_BUS_CNTL, tmp | 0x00a00000); - - /* Once GUI engine is restored, disable bus mastering */ - MACH64_WRITE(MACH64_SRC_CNTL, 0); - - /* Reset descriptor ring */ - mach64_ring_reset(dev_priv); - - return 0; -} - -/*@}*/ - - -/*******************************************************************/ -/** \name Debugging output */ -/*@{*/ - -/** - * Dump engine registers values. - */ -void mach64_dump_engine_info(drm_mach64_private_t *dev_priv) -{ - DRM_INFO("\n"); - if (!dev_priv->is_pci) { - DRM_INFO(" AGP_BASE = 0x%08x\n", - MACH64_READ(MACH64_AGP_BASE)); - DRM_INFO(" AGP_CNTL = 0x%08x\n", - MACH64_READ(MACH64_AGP_CNTL)); - } - DRM_INFO(" ALPHA_TST_CNTL = 0x%08x\n", - MACH64_READ(MACH64_ALPHA_TST_CNTL)); - DRM_INFO("\n"); - DRM_INFO(" BM_COMMAND = 0x%08x\n", - MACH64_READ(MACH64_BM_COMMAND)); - DRM_INFO("BM_FRAME_BUF_OFFSET = 0x%08x\n", - MACH64_READ(MACH64_BM_FRAME_BUF_OFFSET)); - DRM_INFO(" BM_GUI_TABLE = 0x%08x\n", - MACH64_READ(MACH64_BM_GUI_TABLE)); - DRM_INFO(" BM_STATUS = 0x%08x\n", - MACH64_READ(MACH64_BM_STATUS)); - DRM_INFO(" BM_SYSTEM_MEM_ADDR = 0x%08x\n", - MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR)); - DRM_INFO(" BM_SYSTEM_TABLE = 0x%08x\n", - MACH64_READ(MACH64_BM_SYSTEM_TABLE)); - DRM_INFO(" BUS_CNTL = 0x%08x\n", - MACH64_READ(MACH64_BUS_CNTL)); - DRM_INFO("\n"); - /* DRM_INFO( " CLOCK_CNTL = 0x%08x\n", MACH64_READ( MACH64_CLOCK_CNTL ) ); */ - DRM_INFO(" CLR_CMP_CLR = 0x%08x\n", - MACH64_READ(MACH64_CLR_CMP_CLR)); - DRM_INFO(" CLR_CMP_CNTL = 0x%08x\n", - MACH64_READ(MACH64_CLR_CMP_CNTL)); - /* DRM_INFO( " CLR_CMP_MSK = 0x%08x\n", MACH64_READ( MACH64_CLR_CMP_MSK ) ); */ - DRM_INFO(" CONFIG_CHIP_ID = 0x%08x\n", - MACH64_READ(MACH64_CONFIG_CHIP_ID)); - DRM_INFO(" CONFIG_CNTL = 0x%08x\n", - MACH64_READ(MACH64_CONFIG_CNTL)); - DRM_INFO(" CONFIG_STAT0 = 0x%08x\n", - MACH64_READ(MACH64_CONFIG_STAT0)); - DRM_INFO(" CONFIG_STAT1 = 0x%08x\n", - MACH64_READ(MACH64_CONFIG_STAT1)); - DRM_INFO(" CONFIG_STAT2 = 0x%08x\n", - MACH64_READ(MACH64_CONFIG_STAT2)); - DRM_INFO(" CRC_SIG = 0x%08x\n", MACH64_READ(MACH64_CRC_SIG)); - DRM_INFO(" CUSTOM_MACRO_CNTL = 0x%08x\n", - MACH64_READ(MACH64_CUSTOM_MACRO_CNTL)); - DRM_INFO("\n"); - /* DRM_INFO( " DAC_CNTL = 0x%08x\n", MACH64_READ( MACH64_DAC_CNTL ) ); */ - /* DRM_INFO( " DAC_REGS = 0x%08x\n", MACH64_READ( MACH64_DAC_REGS ) ); */ - DRM_INFO(" DP_BKGD_CLR = 0x%08x\n", - MACH64_READ(MACH64_DP_BKGD_CLR)); - DRM_INFO(" DP_FRGD_CLR = 0x%08x\n", - MACH64_READ(MACH64_DP_FRGD_CLR)); - DRM_INFO(" DP_MIX = 0x%08x\n", MACH64_READ(MACH64_DP_MIX)); - DRM_INFO(" DP_PIX_WIDTH = 0x%08x\n", - MACH64_READ(MACH64_DP_PIX_WIDTH)); - DRM_INFO(" DP_SRC = 0x%08x\n", MACH64_READ(MACH64_DP_SRC)); - DRM_INFO(" DP_WRITE_MASK = 0x%08x\n", - MACH64_READ(MACH64_DP_WRITE_MASK)); - DRM_INFO(" DSP_CONFIG = 0x%08x\n", - MACH64_READ(MACH64_DSP_CONFIG)); - DRM_INFO(" DSP_ON_OFF = 0x%08x\n", - MACH64_READ(MACH64_DSP_ON_OFF)); - DRM_INFO(" DST_CNTL = 0x%08x\n", - MACH64_READ(MACH64_DST_CNTL)); - DRM_INFO(" DST_OFF_PITCH = 0x%08x\n", - MACH64_READ(MACH64_DST_OFF_PITCH)); - DRM_INFO("\n"); - /* DRM_INFO( " EXT_DAC_REGS = 0x%08x\n", MACH64_READ( MACH64_EXT_DAC_REGS ) ); */ - DRM_INFO(" EXT_MEM_CNTL = 0x%08x\n", - MACH64_READ(MACH64_EXT_MEM_CNTL)); - DRM_INFO("\n"); - DRM_INFO(" FIFO_STAT = 0x%08x\n", - MACH64_READ(MACH64_FIFO_STAT)); - DRM_INFO("\n"); - DRM_INFO(" GEN_TEST_CNTL = 0x%08x\n", - MACH64_READ(MACH64_GEN_TEST_CNTL)); - /* DRM_INFO( " GP_IO = 0x%08x\n", MACH64_READ( MACH64_GP_IO ) ); */ - DRM_INFO(" GUI_CMDFIFO_DATA = 0x%08x\n", - MACH64_READ(MACH64_GUI_CMDFIFO_DATA)); - DRM_INFO(" GUI_CMDFIFO_DEBUG = 0x%08x\n", - MACH64_READ(MACH64_GUI_CMDFIFO_DEBUG)); - DRM_INFO(" GUI_CNTL = 0x%08x\n", - MACH64_READ(MACH64_GUI_CNTL)); - DRM_INFO(" GUI_STAT = 0x%08x\n", - MACH64_READ(MACH64_GUI_STAT)); - DRM_INFO(" GUI_TRAJ_CNTL = 0x%08x\n", - MACH64_READ(MACH64_GUI_TRAJ_CNTL)); - DRM_INFO("\n"); - DRM_INFO(" HOST_CNTL = 0x%08x\n", - MACH64_READ(MACH64_HOST_CNTL)); - DRM_INFO(" HW_DEBUG = 0x%08x\n", - MACH64_READ(MACH64_HW_DEBUG)); - DRM_INFO("\n"); - DRM_INFO(" MEM_ADDR_CONFIG = 0x%08x\n", - MACH64_READ(MACH64_MEM_ADDR_CONFIG)); - DRM_INFO(" MEM_BUF_CNTL = 0x%08x\n", - MACH64_READ(MACH64_MEM_BUF_CNTL)); - DRM_INFO("\n"); - DRM_INFO(" PAT_REG0 = 0x%08x\n", - MACH64_READ(MACH64_PAT_REG0)); - DRM_INFO(" PAT_REG1 = 0x%08x\n", - MACH64_READ(MACH64_PAT_REG1)); - DRM_INFO("\n"); - DRM_INFO(" SC_LEFT = 0x%08x\n", MACH64_READ(MACH64_SC_LEFT)); - DRM_INFO(" SC_RIGHT = 0x%08x\n", - MACH64_READ(MACH64_SC_RIGHT)); - DRM_INFO(" SC_TOP = 0x%08x\n", MACH64_READ(MACH64_SC_TOP)); - DRM_INFO(" SC_BOTTOM = 0x%08x\n", - MACH64_READ(MACH64_SC_BOTTOM)); - DRM_INFO("\n"); - DRM_INFO(" SCALE_3D_CNTL = 0x%08x\n", - MACH64_READ(MACH64_SCALE_3D_CNTL)); - DRM_INFO(" SCRATCH_REG0 = 0x%08x\n", - MACH64_READ(MACH64_SCRATCH_REG0)); - DRM_INFO(" SCRATCH_REG1 = 0x%08x\n", - MACH64_READ(MACH64_SCRATCH_REG1)); - DRM_INFO(" SETUP_CNTL = 0x%08x\n", - MACH64_READ(MACH64_SETUP_CNTL)); - DRM_INFO(" SRC_CNTL = 0x%08x\n", - MACH64_READ(MACH64_SRC_CNTL)); - DRM_INFO("\n"); - DRM_INFO(" TEX_CNTL = 0x%08x\n", - MACH64_READ(MACH64_TEX_CNTL)); - DRM_INFO(" TEX_SIZE_PITCH = 0x%08x\n", - MACH64_READ(MACH64_TEX_SIZE_PITCH)); - DRM_INFO(" TIMER_CONFIG = 0x%08x\n", - MACH64_READ(MACH64_TIMER_CONFIG)); - DRM_INFO("\n"); - DRM_INFO(" Z_CNTL = 0x%08x\n", MACH64_READ(MACH64_Z_CNTL)); - DRM_INFO(" Z_OFF_PITCH = 0x%08x\n", - MACH64_READ(MACH64_Z_OFF_PITCH)); - DRM_INFO("\n"); -} - -#define MACH64_DUMP_CONTEXT 3 - -/** - * Used by mach64_dump_ring_info() to dump the contents of the current buffer - * pointed by the ring head. - */ -static void mach64_dump_buf_info(drm_mach64_private_t *dev_priv, - struct drm_buf *buf) -{ - u32 addr = GETBUFADDR(buf); - u32 used = buf->used >> 2; - u32 sys_addr = MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR); - u32 *p = GETBUFPTR(buf); - int skipped = 0; - - DRM_INFO("buffer contents:\n"); - - while (used) { - u32 reg, count; - - reg = le32_to_cpu(*p++); - if (addr <= GETBUFADDR(buf) + MACH64_DUMP_CONTEXT * 4 || - (addr >= sys_addr - MACH64_DUMP_CONTEXT * 4 && - addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) || - addr >= - GETBUFADDR(buf) + buf->used - MACH64_DUMP_CONTEXT * 4) { - DRM_INFO("%08x: 0x%08x\n", addr, reg); - } - addr += 4; - used--; - - count = (reg >> 16) + 1; - reg = reg & 0xffff; - reg = MMSELECT(reg); - while (count && used) { - if (addr <= GETBUFADDR(buf) + MACH64_DUMP_CONTEXT * 4 || - (addr >= sys_addr - MACH64_DUMP_CONTEXT * 4 && - addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) || - addr >= - GETBUFADDR(buf) + buf->used - - MACH64_DUMP_CONTEXT * 4) { - DRM_INFO("%08x: 0x%04x = 0x%08x\n", addr, - reg, le32_to_cpu(*p)); - skipped = 0; - } else { - if (!skipped) { - DRM_INFO(" ...\n"); - skipped = 1; - } - } - p++; - addr += 4; - used--; - - reg += 4; - count--; - } - } - - DRM_INFO("\n"); -} - -/** - * Dump the ring state and contents, including the contents of the buffer being - * processed by the graphics engine. - */ -void mach64_dump_ring_info(drm_mach64_private_t *dev_priv) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - int i, skipped; - - DRM_INFO("\n"); - - DRM_INFO("ring contents:\n"); - DRM_INFO(" head_addr: 0x%08x head: %u tail: %u\n\n", - ring->head_addr, ring->head, ring->tail); - - skipped = 0; - for (i = 0; i < ring->size / sizeof(u32); i += 4) { - if (i <= MACH64_DUMP_CONTEXT * 4 || - i >= ring->size / sizeof(u32) - MACH64_DUMP_CONTEXT * 4 || - (i >= ring->tail - MACH64_DUMP_CONTEXT * 4 && - i <= ring->tail + MACH64_DUMP_CONTEXT * 4) || - (i >= ring->head - MACH64_DUMP_CONTEXT * 4 && - i <= ring->head + MACH64_DUMP_CONTEXT * 4)) { - DRM_INFO(" 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x%s%s\n", - (u32)(ring->start_addr + i * sizeof(u32)), - le32_to_cpu(((u32 *) ring->start)[i + 0]), - le32_to_cpu(((u32 *) ring->start)[i + 1]), - le32_to_cpu(((u32 *) ring->start)[i + 2]), - le32_to_cpu(((u32 *) ring->start)[i + 3]), - i == ring->head ? " (head)" : "", - i == ring->tail ? " (tail)" : ""); - skipped = 0; - } else { - if (!skipped) { - DRM_INFO(" ...\n"); - skipped = 1; - } - } - } - - DRM_INFO("\n"); - - if (ring->head >= 0 && ring->head < ring->size / sizeof(u32)) { - struct list_head *ptr; - u32 addr = le32_to_cpu(((u32 *) ring->start)[ring->head + 1]); - - list_for_each(ptr, &dev_priv->pending) { - drm_mach64_freelist_t *entry = - list_entry(ptr, drm_mach64_freelist_t, list); - struct drm_buf *buf = entry->buf; - - u32 buf_addr = GETBUFADDR(buf); - - if (buf_addr <= addr && addr < buf_addr + buf->used) - mach64_dump_buf_info(dev_priv, buf); - } - } - - DRM_INFO("\n"); - DRM_INFO(" BM_GUI_TABLE = 0x%08x\n", - MACH64_READ(MACH64_BM_GUI_TABLE)); - DRM_INFO("\n"); - DRM_INFO("BM_FRAME_BUF_OFFSET = 0x%08x\n", - MACH64_READ(MACH64_BM_FRAME_BUF_OFFSET)); - DRM_INFO(" BM_SYSTEM_MEM_ADDR = 0x%08x\n", - MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR)); - DRM_INFO(" BM_COMMAND = 0x%08x\n", - MACH64_READ(MACH64_BM_COMMAND)); - DRM_INFO("\n"); - DRM_INFO(" BM_STATUS = 0x%08x\n", - MACH64_READ(MACH64_BM_STATUS)); - DRM_INFO(" BUS_CNTL = 0x%08x\n", - MACH64_READ(MACH64_BUS_CNTL)); - DRM_INFO(" FIFO_STAT = 0x%08x\n", - MACH64_READ(MACH64_FIFO_STAT)); - DRM_INFO(" GUI_STAT = 0x%08x\n", - MACH64_READ(MACH64_GUI_STAT)); - DRM_INFO(" SRC_CNTL = 0x%08x\n", - MACH64_READ(MACH64_SRC_CNTL)); -} - -/*@}*/ - - -/*******************************************************************/ -/** \name DMA descriptor ring macros */ -/*@{*/ - -/** - * Add the end mark to the ring's new tail position. - * - * The bus master engine will keep processing the DMA buffers listed in the ring - * until it finds this mark, making it stop. - * - * \sa mach64_clear_dma_eol - */ -static __inline__ void mach64_set_dma_eol(volatile u32 *addr) -{ -#if defined(__i386__) - int nr = 31; - - /* Taken from include/asm-i386/bitops.h linux header */ - __asm__ __volatile__("lock;" "btsl %1,%0":"=m"(*addr) - :"Ir"(nr)); -#elif defined(__powerpc__) - u32 old; - u32 mask = cpu_to_le32(MACH64_DMA_EOL); - - /* Taken from the include/asm-ppc/bitops.h linux header */ - __asm__ __volatile__("\n\ -1: lwarx %0,0,%3 \n\ - or %0,%0,%2 \n\ - stwcx. %0,0,%3 \n\ - bne- 1b":"=&r"(old), "=m"(*addr) - :"r"(mask), "r"(addr), "m"(*addr) - :"cc"); -#elif defined(__alpha__) - u32 temp; - u32 mask = MACH64_DMA_EOL; - - /* Taken from the include/asm-alpha/bitops.h linux header */ - __asm__ __volatile__("1: ldl_l %0,%3\n" - " bis %0,%2,%0\n" - " stl_c %0,%1\n" - " beq %0,2f\n" - ".subsection 2\n" - "2: br 1b\n" - ".previous":"=&r"(temp), "=m"(*addr) - :"Ir"(mask), "m"(*addr)); -#else - u32 mask = cpu_to_le32(MACH64_DMA_EOL); - - *addr |= mask; -#endif -} - -/** - * Remove the end mark from the ring's old tail position. - * - * It should be called after calling mach64_set_dma_eol to mark the ring's new - * tail position. - * - * We update the end marks while the bus master engine is in operation. Since - * the bus master engine may potentially be reading from the same position - * that we write, we must change atomically to avoid having intermediary bad - * data. - */ -static __inline__ void mach64_clear_dma_eol(volatile u32 *addr) -{ -#if defined(__i386__) - int nr = 31; - - /* Taken from include/asm-i386/bitops.h linux header */ - __asm__ __volatile__("lock;" "btrl %1,%0":"=m"(*addr) - :"Ir"(nr)); -#elif defined(__powerpc__) - u32 old; - u32 mask = cpu_to_le32(MACH64_DMA_EOL); - - /* Taken from the include/asm-ppc/bitops.h linux header */ - __asm__ __volatile__("\n\ -1: lwarx %0,0,%3 \n\ - andc %0,%0,%2 \n\ - stwcx. %0,0,%3 \n\ - bne- 1b":"=&r"(old), "=m"(*addr) - :"r"(mask), "r"(addr), "m"(*addr) - :"cc"); -#elif defined(__alpha__) - u32 temp; - u32 mask = ~MACH64_DMA_EOL; - - /* Taken from the include/asm-alpha/bitops.h linux header */ - __asm__ __volatile__("1: ldl_l %0,%3\n" - " and %0,%2,%0\n" - " stl_c %0,%1\n" - " beq %0,2f\n" - ".subsection 2\n" - "2: br 1b\n" - ".previous":"=&r"(temp), "=m"(*addr) - :"Ir"(mask), "m"(*addr)); -#else - u32 mask = cpu_to_le32(~MACH64_DMA_EOL); - - *addr &= mask; -#endif -} - -#define RING_LOCALS \ - int _ring_tail, _ring_write; unsigned int _ring_mask; volatile u32 *_ring - -#define RING_WRITE_OFS _ring_write - -#define BEGIN_RING(n) \ - do { \ - if (MACH64_VERBOSE) { \ - DRM_INFO( "BEGIN_RING( %d ) \n", \ - (n) ); \ - } \ - if (dev_priv->ring.space <= (n) * sizeof(u32)) { \ - int ret; \ - if ((ret = mach64_wait_ring( dev_priv, (n) * sizeof(u32))) < 0 ) { \ - DRM_ERROR( "wait_ring failed, resetting engine\n"); \ - mach64_dump_engine_info( dev_priv ); \ - mach64_do_engine_reset( dev_priv ); \ - return ret; \ - } \ - } \ - dev_priv->ring.space -= (n) * sizeof(u32); \ - _ring = (u32 *) dev_priv->ring.start; \ - _ring_tail = _ring_write = dev_priv->ring.tail; \ - _ring_mask = dev_priv->ring.tail_mask; \ - } while (0) - -#define OUT_RING( x ) \ -do { \ - if (MACH64_VERBOSE) { \ - DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ - (unsigned int)(x), _ring_write ); \ - } \ - _ring[_ring_write++] = cpu_to_le32( x ); \ - _ring_write &= _ring_mask; \ -} while (0) - -#define ADVANCE_RING() \ -do { \ - if (MACH64_VERBOSE) { \ - DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ - _ring_write, _ring_tail ); \ - } \ - DRM_MEMORYBARRIER(); \ - mach64_clear_dma_eol( &_ring[(_ring_tail - 2) & _ring_mask] ); \ - DRM_MEMORYBARRIER(); \ - dev_priv->ring.tail = _ring_write; \ - mach64_ring_tick( dev_priv, &(dev_priv)->ring ); \ -} while (0) - -/** - * Queue a DMA buffer of registers writes into the ring buffer. - */ -int mach64_add_buf_to_ring(drm_mach64_private_t *dev_priv, - drm_mach64_freelist_t *entry) -{ - int bytes, pages, remainder; - u32 address, page; - int i; - struct drm_buf *buf = entry->buf; - RING_LOCALS; - - bytes = buf->used; - address = GETBUFADDR( buf ); - pages = (bytes + MACH64_DMA_CHUNKSIZE - 1) / MACH64_DMA_CHUNKSIZE; - - BEGIN_RING( pages * 4 ); - - for ( i = 0 ; i < pages-1 ; i++ ) { - page = address + i * MACH64_DMA_CHUNKSIZE; - OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); - OUT_RING( page ); - OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET ); - OUT_RING( 0 ); - } - - /* generate the final descriptor for any remaining commands in this buffer */ - page = address + i * MACH64_DMA_CHUNKSIZE; - remainder = bytes - i * MACH64_DMA_CHUNKSIZE; - - /* Save dword offset of last descriptor for this buffer. - * This is needed to check for completion of the buffer in freelist_get - */ - entry->ring_ofs = RING_WRITE_OFS; - - OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); - OUT_RING( page ); - OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL ); - OUT_RING( 0 ); - - ADVANCE_RING(); - - return 0; -} - -/** - * Queue DMA buffer controlling host data tranfers (e.g., blit). - * - * Almost identical to mach64_add_buf_to_ring. - */ -int mach64_add_hostdata_buf_to_ring(drm_mach64_private_t *dev_priv, - drm_mach64_freelist_t *entry) -{ - int bytes, pages, remainder; - u32 address, page; - int i; - struct drm_buf *buf = entry->buf; - RING_LOCALS; - - bytes = buf->used - MACH64_HOSTDATA_BLIT_OFFSET; - pages = (bytes + MACH64_DMA_CHUNKSIZE - 1) / MACH64_DMA_CHUNKSIZE; - address = GETBUFADDR( buf ); - - BEGIN_RING( 4 + pages * 4 ); - - OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); - OUT_RING( address ); - OUT_RING( MACH64_HOSTDATA_BLIT_OFFSET | MACH64_DMA_HOLD_OFFSET ); - OUT_RING( 0 ); - address += MACH64_HOSTDATA_BLIT_OFFSET; - - for ( i = 0 ; i < pages-1 ; i++ ) { - page = address + i * MACH64_DMA_CHUNKSIZE; - OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_HOSTDATA ); - OUT_RING( page ); - OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET ); - OUT_RING( 0 ); - } - - /* generate the final descriptor for any remaining commands in this buffer */ - page = address + i * MACH64_DMA_CHUNKSIZE; - remainder = bytes - i * MACH64_DMA_CHUNKSIZE; - - /* Save dword offset of last descriptor for this buffer. - * This is needed to check for completion of the buffer in freelist_get - */ - entry->ring_ofs = RING_WRITE_OFS; - - OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_HOSTDATA ); - OUT_RING( page ); - OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL ); - OUT_RING( 0 ); - - ADVANCE_RING(); - - return 0; -} - -/*@}*/ - - -/*******************************************************************/ -/** \name DMA test and initialization */ -/*@{*/ - -/** - * Perform a simple DMA operation using the pattern registers to test whether - * DMA works. - * - * \return zero if successful. - * - * \note This function was the testbed for many experiences regarding Mach64 - * DMA operation. It is left here since it so tricky to get DMA operating - * properly in some architectures and hardware. - */ -static int mach64_bm_dma_test(struct drm_device * dev) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_dma_handle_t *cpu_addr_dmah; - u32 data_addr; - u32 *table, *data; - u32 expected[2]; - u32 src_cntl, pat_reg0, pat_reg1; - int i, count, failed; - - DRM_DEBUG("\n"); - - table = (u32 *) dev_priv->ring.start; - - /* FIXME: get a dma buffer from the freelist here */ - DRM_DEBUG("Allocating data memory ...\n"); -#ifdef __FreeBSD__ - DRM_UNLOCK(); -#endif - cpu_addr_dmah = - drm_pci_alloc(dev, 0x1000, 0x1000, 0xfffffffful); -#ifdef __FreeBSD__ - DRM_LOCK(); -#endif - if (!cpu_addr_dmah) { - DRM_INFO("data-memory allocation failed!\n"); - return -ENOMEM; - } else { - data = (u32 *) cpu_addr_dmah->vaddr; - data_addr = (u32) cpu_addr_dmah->busaddr; - } - - /* Save the X server's value for SRC_CNTL and restore it - * in case our test fails. This prevents the X server - * from disabling it's cache for this register - */ - src_cntl = MACH64_READ(MACH64_SRC_CNTL); - pat_reg0 = MACH64_READ(MACH64_PAT_REG0); - pat_reg1 = MACH64_READ(MACH64_PAT_REG1); - - mach64_do_wait_for_fifo(dev_priv, 3); - - MACH64_WRITE(MACH64_SRC_CNTL, 0); - MACH64_WRITE(MACH64_PAT_REG0, 0x11111111); - MACH64_WRITE(MACH64_PAT_REG1, 0x11111111); - - mach64_do_wait_for_idle(dev_priv); - - for (i = 0; i < 2; i++) { - u32 reg; - reg = MACH64_READ((MACH64_PAT_REG0 + i * 4)); - DRM_DEBUG("(Before DMA Transfer) reg %d = 0x%08x\n", i, reg); - if (reg != 0x11111111) { - DRM_INFO("Error initializing test registers\n"); - DRM_INFO("resetting engine ...\n"); - mach64_do_engine_reset(dev_priv); - DRM_INFO("freeing data buffer memory.\n"); - drm_pci_free(dev, cpu_addr_dmah); - return -EIO; - } - } - - /* fill up a buffer with sets of 2 consecutive writes starting with PAT_REG0 */ - count = 0; - - data[count++] = cpu_to_le32(DMAREG(MACH64_PAT_REG0) | (1 << 16)); - data[count++] = expected[0] = 0x22222222; - data[count++] = expected[1] = 0xaaaaaaaa; - - while (count < 1020) { - data[count++] = - cpu_to_le32(DMAREG(MACH64_PAT_REG0) | (1 << 16)); - data[count++] = 0x22222222; - data[count++] = 0xaaaaaaaa; - } - data[count++] = cpu_to_le32(DMAREG(MACH64_SRC_CNTL) | (0 << 16)); - data[count++] = 0; - - DRM_DEBUG("Preparing table ...\n"); - table[MACH64_DMA_FRAME_BUF_OFFSET] = cpu_to_le32(MACH64_BM_ADDR + - MACH64_APERTURE_OFFSET); - table[MACH64_DMA_SYS_MEM_ADDR] = cpu_to_le32(data_addr); - table[MACH64_DMA_COMMAND] = cpu_to_le32(count * sizeof(u32) - | MACH64_DMA_HOLD_OFFSET - | MACH64_DMA_EOL); - table[MACH64_DMA_RESERVED] = 0; - - DRM_DEBUG("table[0] = 0x%08x\n", table[0]); - DRM_DEBUG("table[1] = 0x%08x\n", table[1]); - DRM_DEBUG("table[2] = 0x%08x\n", table[2]); - DRM_DEBUG("table[3] = 0x%08x\n", table[3]); - - for (i = 0; i < 6; i++) { - DRM_DEBUG(" data[%d] = 0x%08x\n", i, data[i]); - } - DRM_DEBUG(" ...\n"); - for (i = count - 5; i < count; i++) { - DRM_DEBUG(" data[%d] = 0x%08x\n", i, data[i]); - } - - DRM_MEMORYBARRIER(); - - DRM_DEBUG("waiting for idle...\n"); - if ((i = mach64_do_wait_for_idle(dev_priv))) { - DRM_INFO("mach64_do_wait_for_idle failed (result=%d)\n", i); - DRM_INFO("resetting engine ...\n"); - mach64_do_engine_reset(dev_priv); - mach64_do_wait_for_fifo(dev_priv, 3); - MACH64_WRITE(MACH64_SRC_CNTL, src_cntl); - MACH64_WRITE(MACH64_PAT_REG0, pat_reg0); - MACH64_WRITE(MACH64_PAT_REG1, pat_reg1); - DRM_INFO("freeing data buffer memory.\n"); - drm_pci_free(dev, cpu_addr_dmah); - return i; - } - DRM_DEBUG("waiting for idle...done\n"); - - DRM_DEBUG("BUS_CNTL = 0x%08x\n", MACH64_READ(MACH64_BUS_CNTL)); - DRM_DEBUG("SRC_CNTL = 0x%08x\n", MACH64_READ(MACH64_SRC_CNTL)); - DRM_DEBUG("\n"); - DRM_DEBUG("data bus addr = 0x%08x\n", data_addr); - DRM_DEBUG("table bus addr = 0x%08x\n", dev_priv->ring.start_addr); - - DRM_DEBUG("starting DMA transfer...\n"); - MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD, - dev_priv->ring.start_addr | MACH64_CIRCULAR_BUF_SIZE_16KB); - - MACH64_WRITE(MACH64_SRC_CNTL, - MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC | - MACH64_SRC_BM_OP_SYSTEM_TO_REG); - - /* Kick off the transfer */ - DRM_DEBUG("starting DMA transfer... done.\n"); - MACH64_WRITE(MACH64_DST_HEIGHT_WIDTH, 0); - - DRM_DEBUG("waiting for idle...\n"); - - if ((i = mach64_do_wait_for_idle(dev_priv))) { - /* engine locked up, dump register state and reset */ - DRM_INFO("mach64_do_wait_for_idle failed (result=%d)\n", i); - mach64_dump_engine_info(dev_priv); - DRM_INFO("resetting engine ...\n"); - mach64_do_engine_reset(dev_priv); - mach64_do_wait_for_fifo(dev_priv, 3); - MACH64_WRITE(MACH64_SRC_CNTL, src_cntl); - MACH64_WRITE(MACH64_PAT_REG0, pat_reg0); - MACH64_WRITE(MACH64_PAT_REG1, pat_reg1); - DRM_INFO("freeing data buffer memory.\n"); - drm_pci_free(dev, cpu_addr_dmah); - return i; - } - - DRM_DEBUG("waiting for idle...done\n"); - - /* restore SRC_CNTL */ - mach64_do_wait_for_fifo(dev_priv, 1); - MACH64_WRITE(MACH64_SRC_CNTL, src_cntl); - - failed = 0; - - /* Check register values to see if the GUI master operation succeeded */ - for (i = 0; i < 2; i++) { - u32 reg; - reg = MACH64_READ((MACH64_PAT_REG0 + i * 4)); - DRM_DEBUG("(After DMA Transfer) reg %d = 0x%08x\n", i, reg); - if (reg != expected[i]) { - failed = -1; - } - } - - /* restore pattern registers */ - mach64_do_wait_for_fifo(dev_priv, 2); - MACH64_WRITE(MACH64_PAT_REG0, pat_reg0); - MACH64_WRITE(MACH64_PAT_REG1, pat_reg1); - - DRM_DEBUG("freeing data buffer memory.\n"); - drm_pci_free(dev, cpu_addr_dmah); - DRM_DEBUG("returning ...\n"); - - return failed; -} - -/** - * Called during the DMA initialization ioctl to initialize all the necessary - * software and hardware state for DMA operation. - */ -static int mach64_do_dma_init(struct drm_device * dev, drm_mach64_init_t * init) -{ - drm_mach64_private_t *dev_priv; - u32 tmp; - int i, ret; - - DRM_DEBUG("\n"); - - dev_priv = drm_alloc(sizeof(drm_mach64_private_t), DRM_MEM_DRIVER); - if (dev_priv == NULL) - return -ENOMEM; - - memset(dev_priv, 0, sizeof(drm_mach64_private_t)); - - dev_priv->is_pci = init->is_pci; - - dev_priv->fb_bpp = init->fb_bpp; - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; - - dev_priv->depth_bpp = init->depth_bpp; - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; - - dev_priv->front_offset_pitch = (((dev_priv->front_pitch / 8) << 22) | - (dev_priv->front_offset >> 3)); - dev_priv->back_offset_pitch = (((dev_priv->back_pitch / 8) << 22) | - (dev_priv->back_offset >> 3)); - dev_priv->depth_offset_pitch = (((dev_priv->depth_pitch / 8) << 22) | - (dev_priv->depth_offset >> 3)); - - dev_priv->usec_timeout = 1000000; - - /* Set up the freelist, placeholder list and pending list */ - INIT_LIST_HEAD(&dev_priv->free_list); - INIT_LIST_HEAD(&dev_priv->placeholders); - INIT_LIST_HEAD(&dev_priv->pending); - - dev_priv->sarea = drm_getsarea(dev); - if (!dev_priv->sarea) { - DRM_ERROR("can not find sarea!\n"); - dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma(dev); - return -EINVAL; - } - dev_priv->fb = drm_core_findmap(dev, init->fb_offset); - if (!dev_priv->fb) { - DRM_ERROR("can not find frame buffer map!\n"); - dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma(dev); - return -EINVAL; - } - dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); - if (!dev_priv->mmio) { - DRM_ERROR("can not find mmio map!\n"); - dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma(dev); - return -EINVAL; - } - - dev_priv->ring_map = drm_core_findmap(dev, init->ring_offset); - if (!dev_priv->ring_map) { - DRM_ERROR("can not find ring map!\n"); - dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma(dev); - return -EINVAL; - } - - dev_priv->sarea_priv = (drm_mach64_sarea_t *) - ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset); - - if (!dev_priv->is_pci) { - drm_core_ioremap(dev_priv->ring_map, dev); - if (!dev_priv->ring_map->handle) { - DRM_ERROR("can not ioremap virtual address for" - " descriptor ring\n"); - dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma(dev); - return -ENOMEM; - } - dev->agp_buffer_token = init->buffers_offset; - dev->agp_buffer_map = - drm_core_findmap(dev, init->buffers_offset); - if (!dev->agp_buffer_map) { - DRM_ERROR("can not find dma buffer map!\n"); - dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma(dev); - return -EINVAL; - } - /* there might be a nicer way to do this - - dev isn't passed all the way though the mach64 - DA */ - dev_priv->dev_buffers = dev->agp_buffer_map; - - drm_core_ioremap(dev->agp_buffer_map, dev); - if (!dev->agp_buffer_map->handle) { - DRM_ERROR("can not ioremap virtual address for" - " dma buffer\n"); - dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma(dev); - return -ENOMEM; - } - dev_priv->agp_textures = - drm_core_findmap(dev, init->agp_textures_offset); - if (!dev_priv->agp_textures) { - DRM_ERROR("can not find agp texture region!\n"); - dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma(dev); - return -EINVAL; - } - } - - dev->dev_private = (void *)dev_priv; - - dev_priv->driver_mode = init->dma_mode; - - /* changing the FIFO size from the default causes problems with DMA */ - tmp = MACH64_READ(MACH64_GUI_CNTL); - if ((tmp & MACH64_CMDFIFO_SIZE_MASK) != MACH64_CMDFIFO_SIZE_128) { - DRM_INFO("Setting FIFO size to 128 entries\n"); - /* FIFO must be empty to change the FIFO depth */ - if ((ret = mach64_do_wait_for_idle(dev_priv))) { - DRM_ERROR - ("wait for idle failed before changing FIFO depth!\n"); - mach64_do_cleanup_dma(dev); - return ret; - } - MACH64_WRITE(MACH64_GUI_CNTL, ((tmp & ~MACH64_CMDFIFO_SIZE_MASK) - | MACH64_CMDFIFO_SIZE_128)); - /* need to read GUI_STAT for proper sync according to docs */ - if ((ret = mach64_do_wait_for_idle(dev_priv))) { - DRM_ERROR - ("wait for idle failed when changing FIFO depth!\n"); - mach64_do_cleanup_dma(dev); - return ret; - } - } - - dev_priv->ring.size = 0x4000; /* 16KB */ - dev_priv->ring.start = dev_priv->ring_map->handle; - dev_priv->ring.start_addr = (u32) dev_priv->ring_map->offset; - - memset(dev_priv->ring.start, 0, dev_priv->ring.size); - DRM_INFO("descriptor ring: cpu addr %p, bus addr: 0x%08x\n", - dev_priv->ring.start, dev_priv->ring.start_addr); - - ret = 0; - if (dev_priv->driver_mode != MACH64_MODE_MMIO) { - - /* enable block 1 registers and bus mastering */ - MACH64_WRITE(MACH64_BUS_CNTL, ((MACH64_READ(MACH64_BUS_CNTL) - | MACH64_BUS_EXT_REG_EN) - & ~MACH64_BUS_MASTER_DIS)); - - /* try a DMA GUI-mastering pass and fall back to MMIO if it fails */ - DRM_DEBUG("Starting DMA test...\n"); - if ((ret = mach64_bm_dma_test(dev))) { - dev_priv->driver_mode = MACH64_MODE_MMIO; - } - } - - switch (dev_priv->driver_mode) { - case MACH64_MODE_MMIO: - MACH64_WRITE(MACH64_BUS_CNTL, (MACH64_READ(MACH64_BUS_CNTL) - | MACH64_BUS_EXT_REG_EN - | MACH64_BUS_MASTER_DIS)); - if (init->dma_mode == MACH64_MODE_MMIO) - DRM_INFO("Forcing pseudo-DMA mode\n"); - else - DRM_INFO - ("DMA test failed (ret=%d), using pseudo-DMA mode\n", - ret); - break; - case MACH64_MODE_DMA_SYNC: - DRM_INFO("DMA test succeeded, using synchronous DMA mode\n"); - break; - case MACH64_MODE_DMA_ASYNC: - default: - DRM_INFO("DMA test succeeded, using asynchronous DMA mode\n"); - } - - dev_priv->ring_running = 0; - - /* setup offsets for physical address of table start and end */ - dev_priv->ring.head_addr = dev_priv->ring.start_addr; - dev_priv->ring.head = dev_priv->ring.tail = 0; - dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; - dev_priv->ring.space = dev_priv->ring.size; - - /* setup physical address and size of descriptor table */ - mach64_do_wait_for_fifo(dev_priv, 1); - MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD, - (dev_priv->ring. - head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB)); - - /* init frame counter */ - dev_priv->sarea_priv->frames_queued = 0; - for (i = 0; i < MACH64_MAX_QUEUED_FRAMES; i++) { - dev_priv->frame_ofs[i] = ~0; /* All ones indicates placeholder */ - } - - /* Allocate the DMA buffer freelist */ - if ((ret = mach64_init_freelist(dev))) { - DRM_ERROR("Freelist allocation failed\n"); - mach64_do_cleanup_dma(dev); - return ret; - } - - return 0; -} - -/*******************************************************************/ -/** MMIO Pseudo-DMA (intended primarily for debugging, not performance) - */ - -int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t *dev_priv) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - volatile u32 *ring_read; - struct list_head *ptr; - drm_mach64_freelist_t *entry; - struct drm_buf *buf = NULL; - u32 *buf_ptr; - u32 used, reg, target; - int fifo, count, found, ret, no_idle_wait; - - fifo = count = reg = no_idle_wait = 0; - target = MACH64_BM_ADDR; - - if ((ret = mach64_do_wait_for_idle(dev_priv)) < 0) { - DRM_INFO("idle failed before pseudo-dma dispatch, resetting engine\n"); - mach64_dump_engine_info(dev_priv); - mach64_do_engine_reset(dev_priv); - return ret; - } - - ring_read = (u32 *) ring->start; - - while (ring->tail != ring->head) { - u32 buf_addr, new_target, offset; - u32 bytes, remaining, head, eol; - - head = ring->head; - - new_target = - le32_to_cpu(ring_read[head++]) - MACH64_APERTURE_OFFSET; - buf_addr = le32_to_cpu(ring_read[head++]); - eol = le32_to_cpu(ring_read[head]) & MACH64_DMA_EOL; - bytes = le32_to_cpu(ring_read[head++]) - & ~(MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL); - head++; - head &= ring->tail_mask; - - /* can't wait for idle between a blit setup descriptor - * and a HOSTDATA descriptor or the engine will lock - */ - if (new_target == MACH64_BM_HOSTDATA - && target == MACH64_BM_ADDR) - no_idle_wait = 1; - - target = new_target; - - found = 0; - offset = 0; - list_for_each(ptr, &dev_priv->pending) { - entry = list_entry(ptr, drm_mach64_freelist_t, list); - buf = entry->buf; - offset = buf_addr - GETBUFADDR(buf); - if (offset >= 0 && offset < MACH64_BUFFER_SIZE) { - found = 1; - break; - } - } - - if (!found || buf == NULL) { - DRM_ERROR - ("Couldn't find pending buffer: head: %u tail: %u buf_addr: 0x%08x %s\n", - head, ring->tail, buf_addr, (eol ? "eol" : "")); - mach64_dump_ring_info(dev_priv); - mach64_do_engine_reset(dev_priv); - return -EINVAL; - } - - /* Hand feed the buffer to the card via MMIO, waiting for the fifo - * every 16 writes - */ - DRM_DEBUG("target: (0x%08x) %s\n", target, - (target == - MACH64_BM_HOSTDATA ? "BM_HOSTDATA" : "BM_ADDR")); - DRM_DEBUG("offset: %u bytes: %u used: %u\n", offset, bytes, - buf->used); - - remaining = (buf->used - offset) >> 2; /* dwords remaining in buffer */ - used = bytes >> 2; /* dwords in buffer for this descriptor */ - buf_ptr = (u32 *) ((char *)GETBUFPTR(buf) + offset); - - while (used) { - - if (count == 0) { - if (target == MACH64_BM_HOSTDATA) { - reg = DMAREG(MACH64_HOST_DATA0); - count = - (remaining > 16) ? 16 : remaining; - fifo = 0; - } else { - reg = le32_to_cpu(*buf_ptr++); - used--; - count = (reg >> 16) + 1; - } - - reg = reg & 0xffff; - reg = MMSELECT(reg); - } - while (count && used) { - if (!fifo) { - if (no_idle_wait) { - if ((ret = - mach64_do_wait_for_fifo - (dev_priv, 16)) < 0) { - no_idle_wait = 0; - return ret; - } - } else { - if ((ret = - mach64_do_wait_for_idle - (dev_priv)) < 0) { - return ret; - } - } - fifo = 16; - } - --fifo; - MACH64_WRITE(reg, le32_to_cpu(*buf_ptr++)); - used--; - remaining--; - - reg += 4; - count--; - } - } - ring->head = head; - ring->head_addr = ring->start_addr + (ring->head * sizeof(u32)); - ring->space += (4 * sizeof(u32)); - } - - if ((ret = mach64_do_wait_for_idle(dev_priv)) < 0) { - return ret; - } - MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD, - ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB); - - DRM_DEBUG("completed\n"); - return 0; -} - -/*@}*/ - - -/*******************************************************************/ -/** \name DMA cleanup */ -/*@{*/ - -int mach64_do_cleanup_dma(struct drm_device * dev) -{ - DRM_DEBUG("\n"); - - /* Make sure interrupts are disabled here because the uninstall ioctl - * may not have been called from userspace and after dev_private - * is freed, it's too late. - */ - if (dev->irq) - drm_irq_uninstall(dev); - - if (dev->dev_private) { - drm_mach64_private_t *dev_priv = dev->dev_private; - - if (!dev_priv->is_pci) { - if (dev_priv->ring_map) - drm_core_ioremapfree(dev_priv->ring_map, dev); - - if (dev->agp_buffer_map) { - drm_core_ioremapfree(dev->agp_buffer_map, dev); - dev->agp_buffer_map = NULL; - } - } - - mach64_destroy_freelist(dev); - - drm_free(dev_priv, sizeof(drm_mach64_private_t), - DRM_MEM_DRIVER); - dev->dev_private = NULL; - } - - return 0; -} - -/*@}*/ - - -/*******************************************************************/ -/** \name IOCTL handlers */ -/*@{*/ - -int mach64_dma_init(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_mach64_init_t *init = data; - - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - switch (init->func) { - case DRM_MACH64_INIT_DMA: - return mach64_do_dma_init(dev, init); - case DRM_MACH64_CLEANUP_DMA: - return mach64_do_cleanup_dma(dev); - } - - return -EINVAL; -} - -int mach64_dma_idle(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - return mach64_do_dma_idle(dev_priv); -} - -int mach64_dma_flush(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - return mach64_do_dma_flush(dev_priv); -} - -int mach64_engine_reset(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - return mach64_do_engine_reset(dev_priv); -} - -/*@}*/ - - -/*******************************************************************/ -/** \name Freelist management */ -/*@{*/ - -int mach64_init_freelist(struct drm_device * dev) -{ - struct drm_device_dma *dma = dev->dma; - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_freelist_t *entry; - struct list_head *ptr; - int i; - - DRM_DEBUG("adding %d buffers to freelist\n", dma->buf_count); - - for (i = 0; i < dma->buf_count; i++) { - if ((entry = - (drm_mach64_freelist_t *) - drm_alloc(sizeof(drm_mach64_freelist_t), - DRM_MEM_BUFLISTS)) == NULL) - return -ENOMEM; - memset(entry, 0, sizeof(drm_mach64_freelist_t)); - entry->buf = dma->buflist[i]; - ptr = &entry->list; - list_add_tail(ptr, &dev_priv->free_list); - } - - return 0; -} - -void mach64_destroy_freelist(struct drm_device * dev) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_freelist_t *entry; - struct list_head *ptr; - struct list_head *tmp; - - DRM_DEBUG("\n"); - - list_for_each_safe(ptr, tmp, &dev_priv->pending) { - list_del(ptr); - entry = list_entry(ptr, drm_mach64_freelist_t, list); - drm_free(entry, sizeof(*entry), DRM_MEM_BUFLISTS); - } - list_for_each_safe(ptr, tmp, &dev_priv->placeholders) { - list_del(ptr); - entry = list_entry(ptr, drm_mach64_freelist_t, list); - drm_free(entry, sizeof(*entry), DRM_MEM_BUFLISTS); - } - - list_for_each_safe(ptr, tmp, &dev_priv->free_list) { - list_del(ptr); - entry = list_entry(ptr, drm_mach64_freelist_t, list); - drm_free(entry, sizeof(*entry), DRM_MEM_BUFLISTS); - } -} - -/* IMPORTANT: This function should only be called when the engine is idle or locked up, - * as it assumes all buffers in the pending list have been completed by the hardware. - */ -int mach64_do_release_used_buffers(drm_mach64_private_t *dev_priv) -{ - struct list_head *ptr; - struct list_head *tmp; - drm_mach64_freelist_t *entry; - int i; - - if (list_empty(&dev_priv->pending)) - return 0; - - /* Iterate the pending list and move all buffers into the freelist... */ - i = 0; - list_for_each_safe(ptr, tmp, &dev_priv->pending) { - entry = list_entry(ptr, drm_mach64_freelist_t, list); - if (entry->discard) { - entry->buf->pending = 0; - list_del(ptr); - list_add_tail(ptr, &dev_priv->free_list); - i++; - } - } - - DRM_DEBUG("released %d buffers from pending list\n", i); - - return 0; -} - -static int mach64_do_reclaim_completed(drm_mach64_private_t *dev_priv) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - struct list_head *ptr; - struct list_head *tmp; - drm_mach64_freelist_t *entry; - u32 head, tail, ofs; - - mach64_ring_tick(dev_priv, ring); - head = ring->head; - tail = ring->tail; - - if (head == tail) { -#if MACH64_EXTRA_CHECKING - if (MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE) { - DRM_ERROR("Empty ring with non-idle engine!\n"); - mach64_dump_ring_info(dev_priv); - return -1; - } -#endif - /* last pass is complete, so release everything */ - mach64_do_release_used_buffers(dev_priv); - DRM_DEBUG("idle engine, freed all buffers.\n"); - if (list_empty(&dev_priv->free_list)) { - DRM_ERROR("Freelist empty with idle engine\n"); - return -1; - } - return 0; - } - /* Look for a completed buffer and bail out of the loop - * as soon as we find one -- don't waste time trying - * to free extra bufs here, leave that to do_release_used_buffers - */ - list_for_each_safe(ptr, tmp, &dev_priv->pending) { - entry = list_entry(ptr, drm_mach64_freelist_t, list); - ofs = entry->ring_ofs; - if (entry->discard && - ((head < tail && (ofs < head || ofs >= tail)) || - (head > tail && (ofs < head && ofs >= tail)))) { -#if MACH64_EXTRA_CHECKING - int i; - - for (i = head; i != tail; i = (i + 4) & ring->tail_mask) - { - u32 o1 = le32_to_cpu(((u32 *) ring-> - start)[i + 1]); - u32 o2 = GETBUFADDR(entry->buf); - - if (o1 == o2) { - DRM_ERROR - ("Attempting to free used buffer: " - "i=%d buf=0x%08x\n", - i, o1); - mach64_dump_ring_info(dev_priv); - return -1; - } - } -#endif - /* found a processed buffer */ - entry->buf->pending = 0; - list_del(ptr); - list_add_tail(ptr, &dev_priv->free_list); - DRM_DEBUG - ("freed processed buffer (head=%d tail=%d " - "buf ring ofs=%d).\n", - head, tail, ofs); - return 0; - } - } - - return 1; -} - -struct drm_buf *mach64_freelist_get(drm_mach64_private_t *dev_priv) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - drm_mach64_freelist_t *entry; - struct list_head *ptr; - int t; - - if (list_empty(&dev_priv->free_list)) { - if (list_empty(&dev_priv->pending)) { - DRM_ERROR - ("Couldn't get buffer - pending and free lists empty\n"); - t = 0; - list_for_each(ptr, &dev_priv->placeholders) { - t++; - } - DRM_INFO("Placeholders: %d\n", t); - return NULL; - } - - for (t = 0; t < dev_priv->usec_timeout; t++) { - int ret; - - ret = mach64_do_reclaim_completed(dev_priv); - if (ret == 0) - goto _freelist_entry_found; - if (ret < 0) - return NULL; - - DRM_UDELAY(1); - } - mach64_dump_ring_info(dev_priv); - DRM_ERROR - ("timeout waiting for buffers: ring head_addr: 0x%08x head: %d tail: %d\n", - ring->head_addr, ring->head, ring->tail); - return NULL; - } - - _freelist_entry_found: - ptr = dev_priv->free_list.next; - list_del(ptr); - entry = list_entry(ptr, drm_mach64_freelist_t, list); - entry->buf->used = 0; - list_add_tail(ptr, &dev_priv->placeholders); - return entry->buf; -} - -int mach64_freelist_put(drm_mach64_private_t *dev_priv, struct drm_buf *copy_buf) -{ - struct list_head *ptr; - drm_mach64_freelist_t *entry; - -#if MACH64_EXTRA_CHECKING - list_for_each(ptr, &dev_priv->pending) { - entry = list_entry(ptr, drm_mach64_freelist_t, list); - if (copy_buf == entry->buf) { - DRM_ERROR("Trying to release a pending buf\n"); - return -EFAULT; - } - } -#endif - ptr = dev_priv->placeholders.next; - entry = list_entry(ptr, drm_mach64_freelist_t, list); - copy_buf->pending = 0; - copy_buf->used = 0; - entry->buf = copy_buf; - entry->discard = 1; - list_del(ptr); - list_add_tail(ptr, &dev_priv->free_list); - - return 0; -} - -/*@}*/ - - -/*******************************************************************/ -/** \name DMA buffer request and submission IOCTL handler */ -/*@{*/ - -static int mach64_dma_get_buffers(struct drm_device *dev, - struct drm_file *file_priv, - struct drm_dma * d) -{ - int i; - struct drm_buf *buf; - drm_mach64_private_t *dev_priv = dev->dev_private; - - for (i = d->granted_count; i < d->request_count; i++) { - buf = mach64_freelist_get(dev_priv); -#if MACH64_EXTRA_CHECKING - if (!buf) - return -EFAULT; -#else - if (!buf) - return -EAGAIN; -#endif - - buf->file_priv = file_priv; - - if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, - sizeof(buf->idx))) - return -EFAULT; - if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, - sizeof(buf->total))) - return -EFAULT; - - d->granted_count++; - } - return 0; -} - -int mach64_dma_buffers(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_device_dma *dma = dev->dma; - struct drm_dma *d = data; - int ret = 0; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - /* Please don't send us buffers. - */ - if (d->send_count != 0) { - DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d->send_count); - return -EINVAL; - } - - /* We'll send you buffers. - */ - if (d->request_count < 0 || d->request_count > dma->buf_count) { - DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d->request_count, dma->buf_count); - ret = -EINVAL; - } - - d->granted_count = 0; - - if (d->request_count) { - ret = mach64_dma_get_buffers(dev, file_priv, d); - } - - return ret; -} - -void mach64_driver_lastclose(struct drm_device * dev) -{ - mach64_do_cleanup_dma(dev); -} - -/*@}*/ diff --git a/shared-core/mach64_drm.h b/shared-core/mach64_drm.h deleted file mode 100644 index 1f5fd842..00000000 --- a/shared-core/mach64_drm.h +++ /dev/null @@ -1,256 +0,0 @@ -/* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*- - * Created: Thu Nov 30 20:04:32 2000 by gareth@valinux.com - */ -/* - * Copyright 2000 Gareth Hughes - * Copyright 2002 Frank C. Earl - * Copyright 2002-2003 Leif Delgass - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Frank C. Earl - * Leif Delgass - */ - -#ifndef __MACH64_DRM_H__ -#define __MACH64_DRM_H__ - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (mach64_sarea.h) - */ -#ifndef __MACH64_SAREA_DEFINES__ -#define __MACH64_SAREA_DEFINES__ - -/* What needs to be changed for the current vertex buffer? - * GH: We're going to be pedantic about this. We want the card to do as - * little as possible, so let's avoid having it fetch a whole bunch of - * register values that don't change all that often, if at all. - */ -#define MACH64_UPLOAD_DST_OFF_PITCH 0x0001 -#define MACH64_UPLOAD_Z_OFF_PITCH 0x0002 -#define MACH64_UPLOAD_Z_ALPHA_CNTL 0x0004 -#define MACH64_UPLOAD_SCALE_3D_CNTL 0x0008 -#define MACH64_UPLOAD_DP_FOG_CLR 0x0010 -#define MACH64_UPLOAD_DP_WRITE_MASK 0x0020 -#define MACH64_UPLOAD_DP_PIX_WIDTH 0x0040 -#define MACH64_UPLOAD_SETUP_CNTL 0x0080 -#define MACH64_UPLOAD_MISC 0x0100 -#define MACH64_UPLOAD_TEXTURE 0x0200 -#define MACH64_UPLOAD_TEX0IMAGE 0x0400 -#define MACH64_UPLOAD_TEX1IMAGE 0x0800 -#define MACH64_UPLOAD_CLIPRECTS 0x1000 /* handled client-side */ -#define MACH64_UPLOAD_CONTEXT 0x00ff -#define MACH64_UPLOAD_ALL 0x1fff - -/* DMA buffer size - */ -#define MACH64_BUFFER_SIZE 16384 - -/* Max number of swaps allowed on the ring - * before the client must wait - */ -#define MACH64_MAX_QUEUED_FRAMES 3U - -/* Byte offsets for host blit buffer data - */ -#define MACH64_HOSTDATA_BLIT_OFFSET 104 - -/* Keep these small for testing. - */ -#define MACH64_NR_SAREA_CLIPRECTS 8 - -#define MACH64_CARD_HEAP 0 -#define MACH64_AGP_HEAP 1 -#define MACH64_NR_TEX_HEAPS 2 -#define MACH64_NR_TEX_REGIONS 64 -#define MACH64_LOG_TEX_GRANULARITY 16 - -#define MACH64_TEX_MAXLEVELS 1 - -#define MACH64_NR_CONTEXT_REGS 15 -#define MACH64_NR_TEXTURE_REGS 4 - -#endif /* __MACH64_SAREA_DEFINES__ */ - -typedef struct { - unsigned int dst_off_pitch; - - unsigned int z_off_pitch; - unsigned int z_cntl; - unsigned int alpha_tst_cntl; - - unsigned int scale_3d_cntl; - - unsigned int sc_left_right; - unsigned int sc_top_bottom; - - unsigned int dp_fog_clr; - unsigned int dp_write_mask; - unsigned int dp_pix_width; - unsigned int dp_mix; - unsigned int dp_src; - - unsigned int clr_cmp_cntl; - unsigned int gui_traj_cntl; - - unsigned int setup_cntl; - - unsigned int tex_size_pitch; - unsigned int tex_cntl; - unsigned int secondary_tex_off; - unsigned int tex_offset; -} drm_mach64_context_regs_t; - -typedef struct drm_mach64_sarea { - /* The channel for communication of state information to the kernel - * on firing a vertex dma buffer. - */ - drm_mach64_context_regs_t context_state; - unsigned int dirty; - unsigned int vertsize; - - /* The current cliprects, or a subset thereof. - */ - struct drm_clip_rect boxes[MACH64_NR_SAREA_CLIPRECTS]; - unsigned int nbox; - - /* Counters for client-side throttling of rendering clients. - */ - unsigned int frames_queued; - - /* Texture memory LRU. - */ - struct drm_tex_region tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS + - 1]; - unsigned int tex_age[MACH64_NR_TEX_HEAPS]; - int ctx_owner; -} drm_mach64_sarea_t; - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (mach64_common.h) - */ - -/* Mach64 specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ - -#define DRM_MACH64_INIT 0x00 -#define DRM_MACH64_IDLE 0x01 -#define DRM_MACH64_RESET 0x02 -#define DRM_MACH64_SWAP 0x03 -#define DRM_MACH64_CLEAR 0x04 -#define DRM_MACH64_VERTEX 0x05 -#define DRM_MACH64_BLIT 0x06 -#define DRM_MACH64_FLUSH 0x07 -#define DRM_MACH64_GETPARAM 0x08 - -#define DRM_IOCTL_MACH64_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t) -#define DRM_IOCTL_MACH64_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_IDLE ) -#define DRM_IOCTL_MACH64_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_RESET ) -#define DRM_IOCTL_MACH64_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_SWAP ) -#define DRM_IOCTL_MACH64_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t) -#define DRM_IOCTL_MACH64_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t) -#define DRM_IOCTL_MACH64_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t) -#define DRM_IOCTL_MACH64_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_FLUSH ) -#define DRM_IOCTL_MACH64_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t) - -/* Buffer flags for clears - */ -#define MACH64_FRONT 0x1 -#define MACH64_BACK 0x2 -#define MACH64_DEPTH 0x4 - -/* Primitive types for vertex buffers - */ -#define MACH64_PRIM_POINTS 0x00000000 -#define MACH64_PRIM_LINES 0x00000001 -#define MACH64_PRIM_LINE_LOOP 0x00000002 -#define MACH64_PRIM_LINE_STRIP 0x00000003 -#define MACH64_PRIM_TRIANGLES 0x00000004 -#define MACH64_PRIM_TRIANGLE_STRIP 0x00000005 -#define MACH64_PRIM_TRIANGLE_FAN 0x00000006 -#define MACH64_PRIM_QUADS 0x00000007 -#define MACH64_PRIM_QUAD_STRIP 0x00000008 -#define MACH64_PRIM_POLYGON 0x00000009 - -typedef enum _drm_mach64_dma_mode_t { - MACH64_MODE_DMA_ASYNC, - MACH64_MODE_DMA_SYNC, - MACH64_MODE_MMIO -} drm_mach64_dma_mode_t; - -typedef struct drm_mach64_init { - enum { - DRM_MACH64_INIT_DMA = 0x01, - DRM_MACH64_CLEANUP_DMA = 0x02 - } func; - - unsigned long sarea_priv_offset; - int is_pci; - drm_mach64_dma_mode_t dma_mode; - - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long ring_offset; - unsigned long buffers_offset; - unsigned long agp_textures_offset; -} drm_mach64_init_t; - -typedef struct drm_mach64_clear { - unsigned int flags; - int x, y, w, h; - unsigned int clear_color; - unsigned int clear_depth; -} drm_mach64_clear_t; - -typedef struct drm_mach64_vertex { - int prim; - void *buf; /* Address of vertex buffer */ - unsigned long used; /* Number of bytes in buffer */ - int discard; /* Client finished with buffer? */ -} drm_mach64_vertex_t; - -typedef struct drm_mach64_blit { - void *buf; - int pitch; - int offset; - int format; - unsigned short x, y; - unsigned short width, height; -} drm_mach64_blit_t; - -typedef struct drm_mach64_getparam { - enum { - MACH64_PARAM_FRAMES_QUEUED = 0x01, - MACH64_PARAM_IRQ_NR = 0x02 - } param; - void *value; -} drm_mach64_getparam_t; - -#endif diff --git a/shared-core/mach64_drv.h b/shared-core/mach64_drv.h deleted file mode 100644 index 6b0020ef..00000000 --- a/shared-core/mach64_drv.h +++ /dev/null @@ -1,860 +0,0 @@ -/* mach64_drv.h -- Private header for mach64 driver -*- linux-c -*- - * Created: Fri Nov 24 22:07:58 2000 by gareth@valinux.com - */ -/* - * Copyright 2000 Gareth Hughes - * Copyright 2002 Frank C. Earl - * Copyright 2002-2003 Leif Delgass - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Frank C. Earl - * Leif Delgass - * José Fonseca - */ - -#ifndef __MACH64_DRV_H__ -#define __MACH64_DRV_H__ - -/* General customization: - */ - -#define DRIVER_AUTHOR "Gareth Hughes, Leif Delgass, José Fonseca" - -#define DRIVER_NAME "mach64" -#define DRIVER_DESC "DRM module for the ATI Rage Pro" -#define DRIVER_DATE "20060718" - -#define DRIVER_MAJOR 2 -#define DRIVER_MINOR 0 -#define DRIVER_PATCHLEVEL 0 - -/* FIXME: remove these when not needed */ -/* Development driver options */ -#define MACH64_EXTRA_CHECKING 0 /* Extra sanity checks for DMA/freelist management */ -#define MACH64_VERBOSE 0 /* Verbose debugging output */ - -typedef struct drm_mach64_freelist { - struct list_head list; /* List pointers for free_list, placeholders, or pending list */ - struct drm_buf *buf; /* Pointer to the buffer */ - int discard; /* This flag is set when we're done (re)using a buffer */ - u32 ring_ofs; /* dword offset in ring of last descriptor for this buffer */ -} drm_mach64_freelist_t; - -typedef struct drm_mach64_descriptor_ring { - void *start; /* write pointer (cpu address) to start of descriptor ring */ - u32 start_addr; /* bus address of beginning of descriptor ring */ - int size; /* size of ring in bytes */ - - u32 head_addr; /* bus address of descriptor ring head */ - u32 head; /* dword offset of descriptor ring head */ - u32 tail; /* dword offset of descriptor ring tail */ - u32 tail_mask; /* mask used to wrap ring */ - int space; /* number of free bytes in ring */ -} drm_mach64_descriptor_ring_t; - -typedef struct drm_mach64_private { - drm_mach64_sarea_t *sarea_priv; - - int is_pci; - drm_mach64_dma_mode_t driver_mode; /* Async DMA, sync DMA, or MMIO */ - - int usec_timeout; /* Timeout for the wait functions */ - - drm_mach64_descriptor_ring_t ring; /* DMA descriptor table (ring buffer) */ - int ring_running; /* Is bus mastering is enabled */ - - struct list_head free_list; /* Free-list head */ - struct list_head placeholders; /* Placeholder list for buffers held by clients */ - struct list_head pending; /* Buffers pending completion */ - - u32 frame_ofs[MACH64_MAX_QUEUED_FRAMES]; /* dword ring offsets of most recent frame swaps */ - - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - - atomic_t vbl_received; /**< Number of vblanks received. */ - - u32 front_offset_pitch; - u32 back_offset_pitch; - u32 depth_offset_pitch; - - drm_local_map_t *sarea; - drm_local_map_t *fb; - drm_local_map_t *mmio; - drm_local_map_t *ring_map; - drm_local_map_t *dev_buffers; /* this is a pointer to a structure in dev */ - drm_local_map_t *agp_textures; -} drm_mach64_private_t; - -extern struct drm_ioctl_desc mach64_ioctls[]; -extern int mach64_max_ioctl; - - /* mach64_dma.c */ -extern int mach64_dma_init(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int mach64_dma_idle(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int mach64_dma_flush(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int mach64_engine_reset(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int mach64_dma_buffers(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern void mach64_driver_lastclose(struct drm_device * dev); - -extern int mach64_init_freelist(struct drm_device * dev); -extern void mach64_destroy_freelist(struct drm_device * dev); -extern struct drm_buf *mach64_freelist_get(drm_mach64_private_t * dev_priv); -extern int mach64_freelist_put(drm_mach64_private_t * dev_priv, - struct drm_buf * copy_buf); - -extern int mach64_do_wait_for_fifo(drm_mach64_private_t * dev_priv, - int entries); -extern int mach64_do_wait_for_idle(drm_mach64_private_t * dev_priv); -extern int mach64_wait_ring(drm_mach64_private_t * dev_priv, int n); -extern int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t * dev_priv); -extern int mach64_do_release_used_buffers(drm_mach64_private_t * dev_priv); -extern void mach64_dump_engine_info(drm_mach64_private_t * dev_priv); -extern void mach64_dump_ring_info(drm_mach64_private_t * dev_priv); -extern int mach64_do_engine_reset(drm_mach64_private_t * dev_priv); - -extern int mach64_add_buf_to_ring(drm_mach64_private_t *dev_priv, - drm_mach64_freelist_t *_entry); -extern int mach64_add_hostdata_buf_to_ring(drm_mach64_private_t *dev_priv, - drm_mach64_freelist_t *_entry); - -extern int mach64_do_dma_idle(drm_mach64_private_t * dev_priv); -extern int mach64_do_dma_flush(drm_mach64_private_t * dev_priv); -extern int mach64_do_cleanup_dma(struct drm_device * dev); - - /* mach64_state.c */ -extern int mach64_dma_clear(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int mach64_dma_swap(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int mach64_dma_vertex(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int mach64_dma_blit(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int mach64_get_param(struct drm_device *dev, void *data, - struct drm_file *file_priv); - -extern int mach64_driver_load(struct drm_device * dev, unsigned long flags); -extern u32 mach64_get_vblank_counter(struct drm_device *dev, int crtc); -extern int mach64_enable_vblank(struct drm_device *dev, int crtc); -extern void mach64_disable_vblank(struct drm_device *dev, int crtc); -extern irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS); -extern void mach64_driver_irq_preinstall(struct drm_device *dev); -extern int mach64_driver_irq_postinstall(struct drm_device *dev); -extern void mach64_driver_irq_uninstall(struct drm_device *dev); - -/* ================================================================ - * Registers - */ - -#define MACH64_AGP_BASE 0x0148 -#define MACH64_AGP_CNTL 0x014c -#define MACH64_ALPHA_TST_CNTL 0x0550 - -#define MACH64_DSP_CONFIG 0x0420 -#define MACH64_DSP_ON_OFF 0x0424 -#define MACH64_EXT_MEM_CNTL 0x04ac -#define MACH64_GEN_TEST_CNTL 0x04d0 -#define MACH64_HW_DEBUG 0x047c -#define MACH64_MEM_ADDR_CONFIG 0x0434 -#define MACH64_MEM_BUF_CNTL 0x042c -#define MACH64_MEM_CNTL 0x04b0 - -#define MACH64_BM_ADDR 0x0648 -#define MACH64_BM_COMMAND 0x0188 -#define MACH64_BM_DATA 0x0648 -#define MACH64_BM_FRAME_BUF_OFFSET 0x0180 -#define MACH64_BM_GUI_TABLE 0x01b8 -#define MACH64_BM_GUI_TABLE_CMD 0x064c -# define MACH64_CIRCULAR_BUF_SIZE_16KB (0 << 0) -# define MACH64_CIRCULAR_BUF_SIZE_32KB (1 << 0) -# define MACH64_CIRCULAR_BUF_SIZE_64KB (2 << 0) -# define MACH64_CIRCULAR_BUF_SIZE_128KB (3 << 0) -# define MACH64_LAST_DESCRIPTOR (1 << 31) -#define MACH64_BM_HOSTDATA 0x0644 -#define MACH64_BM_STATUS 0x018c -#define MACH64_BM_SYSTEM_MEM_ADDR 0x0184 -#define MACH64_BM_SYSTEM_TABLE 0x01bc -#define MACH64_BUS_CNTL 0x04a0 -# define MACH64_BUS_MSTR_RESET (1 << 1) -# define MACH64_BUS_APER_REG_DIS (1 << 4) -# define MACH64_BUS_FLUSH_BUF (1 << 2) -# define MACH64_BUS_MASTER_DIS (1 << 6) -# define MACH64_BUS_EXT_REG_EN (1 << 27) - -#define MACH64_CLR_CMP_CLR 0x0700 -#define MACH64_CLR_CMP_CNTL 0x0708 -#define MACH64_CLR_CMP_MASK 0x0704 -#define MACH64_CONFIG_CHIP_ID 0x04e0 -#define MACH64_CONFIG_CNTL 0x04dc -#define MACH64_CONFIG_STAT0 0x04e4 -#define MACH64_CONFIG_STAT1 0x0494 -#define MACH64_CONFIG_STAT2 0x0498 -#define MACH64_CONTEXT_LOAD_CNTL 0x072c -#define MACH64_CONTEXT_MASK 0x0720 -#define MACH64_COMPOSITE_SHADOW_ID 0x0798 -#define MACH64_CRC_SIG 0x04e8 -#define MACH64_CUSTOM_MACRO_CNTL 0x04d4 - -#define MACH64_DP_BKGD_CLR 0x06c0 -#define MACH64_DP_FOG_CLR 0x06c4 -#define MACH64_DP_FGRD_BKGD_CLR 0x06e0 -#define MACH64_DP_FRGD_CLR 0x06c4 -#define MACH64_DP_FGRD_CLR_MIX 0x06dc - -#define MACH64_DP_MIX 0x06d4 -# define BKGD_MIX_NOT_D (0 << 0) -# define BKGD_MIX_ZERO (1 << 0) -# define BKGD_MIX_ONE (2 << 0) -# define MACH64_BKGD_MIX_D (3 << 0) -# define BKGD_MIX_NOT_S (4 << 0) -# define BKGD_MIX_D_XOR_S (5 << 0) -# define BKGD_MIX_NOT_D_XOR_S (6 << 0) -# define MACH64_BKGD_MIX_S (7 << 0) -# define BKGD_MIX_NOT_D_OR_NOT_S (8 << 0) -# define BKGD_MIX_D_OR_NOT_S (9 << 0) -# define BKGD_MIX_NOT_D_OR_S (10 << 0) -# define BKGD_MIX_D_OR_S (11 << 0) -# define BKGD_MIX_D_AND_S (12 << 0) -# define BKGD_MIX_NOT_D_AND_S (13 << 0) -# define BKGD_MIX_D_AND_NOT_S (14 << 0) -# define BKGD_MIX_NOT_D_AND_NOT_S (15 << 0) -# define BKGD_MIX_D_PLUS_S_DIV2 (23 << 0) -# define FRGD_MIX_NOT_D (0 << 16) -# define FRGD_MIX_ZERO (1 << 16) -# define FRGD_MIX_ONE (2 << 16) -# define FRGD_MIX_D (3 << 16) -# define FRGD_MIX_NOT_S (4 << 16) -# define FRGD_MIX_D_XOR_S (5 << 16) -# define FRGD_MIX_NOT_D_XOR_S (6 << 16) -# define MACH64_FRGD_MIX_S (7 << 16) -# define FRGD_MIX_NOT_D_OR_NOT_S (8 << 16) -# define FRGD_MIX_D_OR_NOT_S (9 << 16) -# define FRGD_MIX_NOT_D_OR_S (10 << 16) -# define FRGD_MIX_D_OR_S (11 << 16) -# define FRGD_MIX_D_AND_S (12 << 16) -# define FRGD_MIX_NOT_D_AND_S (13 << 16) -# define FRGD_MIX_D_AND_NOT_S (14 << 16) -# define FRGD_MIX_NOT_D_AND_NOT_S (15 << 16) -# define FRGD_MIX_D_PLUS_S_DIV2 (23 << 16) - -#define MACH64_DP_PIX_WIDTH 0x06d0 -# define MACH64_HOST_TRIPLE_ENABLE (1 << 13) -# define MACH64_BYTE_ORDER_MSB_TO_LSB (0 << 24) -# define MACH64_BYTE_ORDER_LSB_TO_MSB (1 << 24) - -#define MACH64_DP_SRC 0x06d8 -# define MACH64_BKGD_SRC_BKGD_CLR (0 << 0) -# define MACH64_BKGD_SRC_FRGD_CLR (1 << 0) -# define MACH64_BKGD_SRC_HOST (2 << 0) -# define MACH64_BKGD_SRC_BLIT (3 << 0) -# define MACH64_BKGD_SRC_PATTERN (4 << 0) -# define MACH64_BKGD_SRC_3D (5 << 0) -# define MACH64_FRGD_SRC_BKGD_CLR (0 << 8) -# define MACH64_FRGD_SRC_FRGD_CLR (1 << 8) -# define MACH64_FRGD_SRC_HOST (2 << 8) -# define MACH64_FRGD_SRC_BLIT (3 << 8) -# define MACH64_FRGD_SRC_PATTERN (4 << 8) -# define MACH64_FRGD_SRC_3D (5 << 8) -# define MACH64_MONO_SRC_ONE (0 << 16) -# define MACH64_MONO_SRC_PATTERN (1 << 16) -# define MACH64_MONO_SRC_HOST (2 << 16) -# define MACH64_MONO_SRC_BLIT (3 << 16) - -#define MACH64_DP_WRITE_MASK 0x06c8 - -#define MACH64_DST_CNTL 0x0530 -# define MACH64_DST_X_RIGHT_TO_LEFT (0 << 0) -# define MACH64_DST_X_LEFT_TO_RIGHT (1 << 0) -# define MACH64_DST_Y_BOTTOM_TO_TOP (0 << 1) -# define MACH64_DST_Y_TOP_TO_BOTTOM (1 << 1) -# define MACH64_DST_X_MAJOR (0 << 2) -# define MACH64_DST_Y_MAJOR (1 << 2) -# define MACH64_DST_X_TILE (1 << 3) -# define MACH64_DST_Y_TILE (1 << 4) -# define MACH64_DST_LAST_PEL (1 << 5) -# define MACH64_DST_POLYGON_ENABLE (1 << 6) -# define MACH64_DST_24_ROTATION_ENABLE (1 << 7) - -#define MACH64_DST_HEIGHT_WIDTH 0x0518 -#define MACH64_DST_OFF_PITCH 0x0500 -#define MACH64_DST_WIDTH_HEIGHT 0x06ec -#define MACH64_DST_X_Y 0x06e8 -#define MACH64_DST_Y_X 0x050c - -#define MACH64_FIFO_STAT 0x0710 -# define MACH64_FIFO_SLOT_MASK 0x0000ffff -# define MACH64_FIFO_ERR (1 << 31) - -#define MACH64_GEN_TEST_CNTL 0x04d0 -# define MACH64_GUI_ENGINE_ENABLE (1 << 8) -#define MACH64_GUI_CMDFIFO_DEBUG 0x0170 -#define MACH64_GUI_CMDFIFO_DATA 0x0174 -#define MACH64_GUI_CNTL 0x0178 -# define MACH64_CMDFIFO_SIZE_MASK 0x00000003ul -# define MACH64_CMDFIFO_SIZE_192 0x00000000ul -# define MACH64_CMDFIFO_SIZE_128 0x00000001ul -# define MACH64_CMDFIFO_SIZE_64 0x00000002ul -#define MACH64_GUI_STAT 0x0738 -# define MACH64_GUI_ACTIVE (1 << 0) -#define MACH64_GUI_TRAJ_CNTL 0x0730 - -#define MACH64_HOST_CNTL 0x0640 -#define MACH64_HOST_DATA0 0x0600 - -#define MACH64_ONE_OVER_AREA 0x029c -#define MACH64_ONE_OVER_AREA_UC 0x0300 - -#define MACH64_PAT_REG0 0x0680 -#define MACH64_PAT_REG1 0x0684 - -#define MACH64_SC_LEFT 0x06a0 -#define MACH64_SC_RIGHT 0x06a4 -#define MACH64_SC_LEFT_RIGHT 0x06a8 -#define MACH64_SC_TOP 0x06ac -#define MACH64_SC_BOTTOM 0x06b0 -#define MACH64_SC_TOP_BOTTOM 0x06b4 - -#define MACH64_SCALE_3D_CNTL 0x05fc -#define MACH64_SCRATCH_REG0 0x0480 -#define MACH64_SCRATCH_REG1 0x0484 -#define MACH64_SECONDARY_TEX_OFF 0x0778 -#define MACH64_SETUP_CNTL 0x0304 -#define MACH64_SRC_CNTL 0x05b4 -# define MACH64_SRC_BM_ENABLE (1 << 8) -# define MACH64_SRC_BM_SYNC (1 << 9) -# define MACH64_SRC_BM_OP_FRAME_TO_SYSTEM (0 << 10) -# define MACH64_SRC_BM_OP_SYSTEM_TO_FRAME (1 << 10) -# define MACH64_SRC_BM_OP_REG_TO_SYSTEM (2 << 10) -# define MACH64_SRC_BM_OP_SYSTEM_TO_REG (3 << 10) -#define MACH64_SRC_HEIGHT1 0x0594 -#define MACH64_SRC_HEIGHT2 0x05ac -#define MACH64_SRC_HEIGHT1_WIDTH1 0x0598 -#define MACH64_SRC_HEIGHT2_WIDTH2 0x05b0 -#define MACH64_SRC_OFF_PITCH 0x0580 -#define MACH64_SRC_WIDTH1 0x0590 -#define MACH64_SRC_Y_X 0x058c - -#define MACH64_TEX_0_OFF 0x05c0 -#define MACH64_TEX_CNTL 0x0774 -#define MACH64_TEX_SIZE_PITCH 0x0770 -#define MACH64_TIMER_CONFIG 0x0428 - -#define MACH64_VERTEX_1_ARGB 0x0254 -#define MACH64_VERTEX_1_S 0x0240 -#define MACH64_VERTEX_1_SECONDARY_S 0x0328 -#define MACH64_VERTEX_1_SECONDARY_T 0x032c -#define MACH64_VERTEX_1_SECONDARY_W 0x0330 -#define MACH64_VERTEX_1_SPEC_ARGB 0x024c -#define MACH64_VERTEX_1_T 0x0244 -#define MACH64_VERTEX_1_W 0x0248 -#define MACH64_VERTEX_1_X_Y 0x0258 -#define MACH64_VERTEX_1_Z 0x0250 -#define MACH64_VERTEX_2_ARGB 0x0274 -#define MACH64_VERTEX_2_S 0x0260 -#define MACH64_VERTEX_2_SECONDARY_S 0x0334 -#define MACH64_VERTEX_2_SECONDARY_T 0x0338 -#define MACH64_VERTEX_2_SECONDARY_W 0x033c -#define MACH64_VERTEX_2_SPEC_ARGB 0x026c -#define MACH64_VERTEX_2_T 0x0264 -#define MACH64_VERTEX_2_W 0x0268 -#define MACH64_VERTEX_2_X_Y 0x0278 -#define MACH64_VERTEX_2_Z 0x0270 -#define MACH64_VERTEX_3_ARGB 0x0294 -#define MACH64_VERTEX_3_S 0x0280 -#define MACH64_VERTEX_3_SECONDARY_S 0x02a0 -#define MACH64_VERTEX_3_SECONDARY_T 0x02a4 -#define MACH64_VERTEX_3_SECONDARY_W 0x02a8 -#define MACH64_VERTEX_3_SPEC_ARGB 0x028c -#define MACH64_VERTEX_3_T 0x0284 -#define MACH64_VERTEX_3_W 0x0288 -#define MACH64_VERTEX_3_X_Y 0x0298 -#define MACH64_VERTEX_3_Z 0x0290 - -#define MACH64_Z_CNTL 0x054c -#define MACH64_Z_OFF_PITCH 0x0548 - -#define MACH64_CRTC_VLINE_CRNT_VLINE 0x0410 -# define MACH64_CRTC_VLINE_MASK 0x000007ff -# define MACH64_CRTC_CRNT_VLINE_MASK 0x07ff0000 -#define MACH64_CRTC_OFF_PITCH 0x0414 -#define MACH64_CRTC_INT_CNTL 0x0418 -# define MACH64_CRTC_VBLANK (1 << 0) -# define MACH64_CRTC_VBLANK_INT_EN (1 << 1) -# define MACH64_CRTC_VBLANK_INT (1 << 2) -# define MACH64_CRTC_VLINE_INT_EN (1 << 3) -# define MACH64_CRTC_VLINE_INT (1 << 4) -# define MACH64_CRTC_VLINE_SYNC (1 << 5) /* 0=even, 1=odd */ -# define MACH64_CRTC_FRAME (1 << 6) /* 0=even, 1=odd */ -# define MACH64_CRTC_SNAPSHOT_INT_EN (1 << 7) -# define MACH64_CRTC_SNAPSHOT_INT (1 << 8) -# define MACH64_CRTC_I2C_INT_EN (1 << 9) -# define MACH64_CRTC_I2C_INT (1 << 10) -# define MACH64_CRTC2_VBLANK (1 << 11) /* LT Pro */ -# define MACH64_CRTC2_VBLANK_INT_EN (1 << 12) /* LT Pro */ -# define MACH64_CRTC2_VBLANK_INT (1 << 13) /* LT Pro */ -# define MACH64_CRTC2_VLINE_INT_EN (1 << 14) /* LT Pro */ -# define MACH64_CRTC2_VLINE_INT (1 << 15) /* LT Pro */ -# define MACH64_CRTC_CAPBUF0_INT_EN (1 << 16) -# define MACH64_CRTC_CAPBUF0_INT (1 << 17) -# define MACH64_CRTC_CAPBUF1_INT_EN (1 << 18) -# define MACH64_CRTC_CAPBUF1_INT (1 << 19) -# define MACH64_CRTC_OVERLAY_EOF_INT_EN (1 << 20) -# define MACH64_CRTC_OVERLAY_EOF_INT (1 << 21) -# define MACH64_CRTC_ONESHOT_CAP_INT_EN (1 << 22) -# define MACH64_CRTC_ONESHOT_CAP_INT (1 << 23) -# define MACH64_CRTC_BUSMASTER_EOL_INT_EN (1 << 24) -# define MACH64_CRTC_BUSMASTER_EOL_INT (1 << 25) -# define MACH64_CRTC_GP_INT_EN (1 << 26) -# define MACH64_CRTC_GP_INT (1 << 27) -# define MACH64_CRTC2_VLINE_SYNC (1 << 28) /* LT Pro */ /* 0=even, 1=odd */ -# define MACH64_CRTC_SNAPSHOT2_INT_EN (1 << 29) /* LT Pro */ -# define MACH64_CRTC_SNAPSHOT2_INT (1 << 30) /* LT Pro */ -# define MACH64_CRTC_VBLANK2_INT (1 << 31) -# define MACH64_CRTC_INT_ENS \ - ( \ - MACH64_CRTC_VBLANK_INT_EN | \ - MACH64_CRTC_VLINE_INT_EN | \ - MACH64_CRTC_SNAPSHOT_INT_EN | \ - MACH64_CRTC_I2C_INT_EN | \ - MACH64_CRTC2_VBLANK_INT_EN | \ - MACH64_CRTC2_VLINE_INT_EN | \ - MACH64_CRTC_CAPBUF0_INT_EN | \ - MACH64_CRTC_CAPBUF1_INT_EN | \ - MACH64_CRTC_OVERLAY_EOF_INT_EN | \ - MACH64_CRTC_ONESHOT_CAP_INT_EN | \ - MACH64_CRTC_BUSMASTER_EOL_INT_EN | \ - MACH64_CRTC_GP_INT_EN | \ - MACH64_CRTC_SNAPSHOT2_INT_EN | \ - 0 \ - ) -# define MACH64_CRTC_INT_ACKS \ - ( \ - MACH64_CRTC_VBLANK_INT | \ - MACH64_CRTC_VLINE_INT | \ - MACH64_CRTC_SNAPSHOT_INT | \ - MACH64_CRTC_I2C_INT | \ - MACH64_CRTC2_VBLANK_INT | \ - MACH64_CRTC2_VLINE_INT | \ - MACH64_CRTC_CAPBUF0_INT | \ - MACH64_CRTC_CAPBUF1_INT | \ - MACH64_CRTC_OVERLAY_EOF_INT | \ - MACH64_CRTC_ONESHOT_CAP_INT | \ - MACH64_CRTC_BUSMASTER_EOL_INT | \ - MACH64_CRTC_GP_INT | \ - MACH64_CRTC_SNAPSHOT2_INT | \ - MACH64_CRTC_VBLANK2_INT | \ - 0 \ - ) - -#define MACH64_DATATYPE_CI8 2 -#define MACH64_DATATYPE_ARGB1555 3 -#define MACH64_DATATYPE_RGB565 4 -#define MACH64_DATATYPE_ARGB8888 6 -#define MACH64_DATATYPE_RGB332 7 -#define MACH64_DATATYPE_Y8 8 -#define MACH64_DATATYPE_RGB8 9 -#define MACH64_DATATYPE_VYUY422 11 -#define MACH64_DATATYPE_YVYU422 12 -#define MACH64_DATATYPE_AYUV444 14 -#define MACH64_DATATYPE_ARGB4444 15 - -#define MACH64_READ(reg) DRM_READ32(dev_priv->mmio, (reg) ) -#define MACH64_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio, (reg), (val) ) - -#define DWMREG0 0x0400 -#define DWMREG0_END 0x07ff -#define DWMREG1 0x0000 -#define DWMREG1_END 0x03ff - -#define ISREG0(r) (((r) >= DWMREG0) && ((r) <= DWMREG0_END)) -#define DMAREG0(r) (((r) - DWMREG0) >> 2) -#define DMAREG1(r) ((((r) - DWMREG1) >> 2 ) | 0x0100) -#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) - -#define MMREG0 0x0000 -#define MMREG0_END 0x00ff - -#define ISMMREG0(r) (((r) >= MMREG0) && ((r) <= MMREG0_END)) -#define MMSELECT0(r) (((r) << 2) + DWMREG0) -#define MMSELECT1(r) (((((r) & 0xff) << 2) + DWMREG1)) -#define MMSELECT(r) (ISMMREG0(r) ? MMSELECT0(r) : MMSELECT1(r)) - -/* ================================================================ - * DMA constants - */ - -/* DMA descriptor field indices: - * The descriptor fields are loaded into the read-only - * BM_* system bus master registers during a bus-master operation - */ -#define MACH64_DMA_FRAME_BUF_OFFSET 0 /* BM_FRAME_BUF_OFFSET */ -#define MACH64_DMA_SYS_MEM_ADDR 1 /* BM_SYSTEM_MEM_ADDR */ -#define MACH64_DMA_COMMAND 2 /* BM_COMMAND */ -#define MACH64_DMA_RESERVED 3 /* BM_STATUS */ - -/* BM_COMMAND descriptor field flags */ -#define MACH64_DMA_HOLD_OFFSET (1<<30) /* Don't increment DMA_FRAME_BUF_OFFSET */ -#define MACH64_DMA_EOL (1<<31) /* End of descriptor list flag */ - -#define MACH64_DMA_CHUNKSIZE 0x1000 /* 4kB per DMA descriptor */ -#define MACH64_APERTURE_OFFSET 0x7ff800 /* frame-buffer offset for gui-masters */ - -/* ================================================================ - * Ring operations - * - * Since the Mach64 bus master engine requires polling, these functions end - * up being called frequently, hence being inline. - */ - -static __inline__ void mach64_ring_start(drm_mach64_private_t * dev_priv) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - - DRM_DEBUG("head_addr: 0x%08x head: %d tail: %d space: %d\n", - ring->head_addr, ring->head, ring->tail, ring->space); - - if (mach64_do_wait_for_idle(dev_priv) < 0) { - mach64_do_engine_reset(dev_priv); - } - - if (dev_priv->driver_mode != MACH64_MODE_MMIO) { - /* enable bus mastering and block 1 registers */ - MACH64_WRITE(MACH64_BUS_CNTL, - (MACH64_READ(MACH64_BUS_CNTL) & - ~MACH64_BUS_MASTER_DIS) - | MACH64_BUS_EXT_REG_EN); - mach64_do_wait_for_idle(dev_priv); - } - - /* reset descriptor table ring head */ - MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD, - ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB); - - dev_priv->ring_running = 1; -} - -static __inline__ void mach64_ring_resume(drm_mach64_private_t * dev_priv, - drm_mach64_descriptor_ring_t * ring) -{ - DRM_DEBUG("head_addr: 0x%08x head: %d tail: %d space: %d\n", - ring->head_addr, ring->head, ring->tail, ring->space); - - /* reset descriptor table ring head */ - MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD, - ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB); - - if (dev_priv->driver_mode == MACH64_MODE_MMIO) { - mach64_do_dispatch_pseudo_dma(dev_priv); - } else { - /* enable GUI bus mastering, and sync the bus master to the GUI */ - MACH64_WRITE(MACH64_SRC_CNTL, - MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC | - MACH64_SRC_BM_OP_SYSTEM_TO_REG); - - /* kick off the transfer */ - MACH64_WRITE(MACH64_DST_HEIGHT_WIDTH, 0); - if (dev_priv->driver_mode == MACH64_MODE_DMA_SYNC) { - if ((mach64_do_wait_for_idle(dev_priv)) < 0) { - DRM_ERROR("idle failed, resetting engine\n"); - mach64_dump_engine_info(dev_priv); - mach64_do_engine_reset(dev_priv); - return; - } - mach64_do_release_used_buffers(dev_priv); - } - } -} - -/** - * Poll the ring head and make sure the bus master is alive. - * - * Mach64's bus master engine will stop if there are no more entries to process. - * This function polls the engine for the last processed entry and calls - * mach64_ring_resume if there is an unprocessed entry. - * - * Note also that, since we update the ring tail while the bus master engine is - * in operation, it is possible that the last tail update was too late to be - * processed, and the bus master engine stops at the previous tail position. - * Therefore it is important to call this function frequently. - */ -static __inline__ void mach64_ring_tick(drm_mach64_private_t * dev_priv, - drm_mach64_descriptor_ring_t * ring) -{ - DRM_DEBUG("head_addr: 0x%08x head: %d tail: %d space: %d\n", - ring->head_addr, ring->head, ring->tail, ring->space); - - if (!dev_priv->ring_running) { - mach64_ring_start(dev_priv); - - if (ring->head != ring->tail) { - mach64_ring_resume(dev_priv, ring); - } - } else { - /* GUI_ACTIVE must be read before BM_GUI_TABLE to - * correctly determine the ring head - */ - int gui_active = - MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE; - - ring->head_addr = MACH64_READ(MACH64_BM_GUI_TABLE) & 0xfffffff0; - - if (gui_active) { - /* If not idle, BM_GUI_TABLE points one descriptor - * past the current head - */ - if (ring->head_addr == ring->start_addr) { - ring->head_addr += ring->size; - } - ring->head_addr -= 4 * sizeof(u32); - } - - if (ring->head_addr < ring->start_addr || - ring->head_addr >= ring->start_addr + ring->size) { - DRM_ERROR("bad ring head address: 0x%08x\n", - ring->head_addr); - mach64_dump_ring_info(dev_priv); - mach64_do_engine_reset(dev_priv); - return; - } - - ring->head = (ring->head_addr - ring->start_addr) / sizeof(u32); - - if (!gui_active && ring->head != ring->tail) { - mach64_ring_resume(dev_priv, ring); - } - } -} - -static __inline__ void mach64_ring_stop(drm_mach64_private_t * dev_priv) -{ - DRM_DEBUG("head_addr: 0x%08x head: %d tail: %d space: %d\n", - dev_priv->ring.head_addr, dev_priv->ring.head, - dev_priv->ring.tail, dev_priv->ring.space); - - /* restore previous SRC_CNTL to disable busmastering */ - mach64_do_wait_for_fifo(dev_priv, 1); - MACH64_WRITE(MACH64_SRC_CNTL, 0); - - /* disable busmastering but keep the block 1 registers enabled */ - mach64_do_wait_for_idle(dev_priv); - MACH64_WRITE(MACH64_BUS_CNTL, MACH64_READ(MACH64_BUS_CNTL) - | MACH64_BUS_MASTER_DIS | MACH64_BUS_EXT_REG_EN); - - dev_priv->ring_running = 0; -} - -static __inline__ void -mach64_update_ring_snapshot(drm_mach64_private_t * dev_priv) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - - DRM_DEBUG("\n"); - - mach64_ring_tick(dev_priv, ring); - - ring->space = (ring->head - ring->tail) * sizeof(u32); - if (ring->space <= 0) { - ring->space += ring->size; - } -} - -/* ================================================================ - * DMA macros - * - * Mach64's ring buffer doesn't take register writes directly. These - * have to be written indirectly in DMA buffers. These macros simplify - * the task of setting up a buffer, writing commands to it, and - * queuing the buffer in the ring. - */ - -#define DMALOCALS \ - drm_mach64_freelist_t *_entry = NULL; \ - struct drm_buf *_buf = NULL; \ - u32 *_buf_wptr; int _outcount - -#define GETBUFPTR( __buf ) \ -((dev_priv->is_pci) ? \ - ((u32 *)(__buf)->address) : \ - ((u32 *)((char *)dev_priv->dev_buffers->handle + (__buf)->offset))) - -#define GETBUFADDR( __buf ) ((u32)(__buf)->bus_address) - -#define GETRINGOFFSET() (_entry->ring_ofs) - -static __inline__ int mach64_find_pending_buf_entry(drm_mach64_private_t * - dev_priv, - drm_mach64_freelist_t ** - entry, struct drm_buf * buf) -{ - struct list_head *ptr; -#if MACH64_EXTRA_CHECKING - if (list_empty(&dev_priv->pending)) { - DRM_ERROR("Empty pending list in \n"); - return -EINVAL; - } -#endif - ptr = dev_priv->pending.prev; - *entry = list_entry(ptr, drm_mach64_freelist_t, list); - while ((*entry)->buf != buf) { - if (ptr == &dev_priv->pending) { - return -EFAULT; - } - ptr = ptr->prev; - *entry = list_entry(ptr, drm_mach64_freelist_t, list); - } - return 0; -} - -#define DMASETPTR( _p ) \ -do { \ - _buf = (_p); \ - _outcount = 0; \ - _buf_wptr = GETBUFPTR( _buf ); \ -} while(0) - -/* FIXME: use a private set of smaller buffers for state emits, clears, and swaps? */ -#define DMAGETPTR( file_priv, dev_priv, n ) \ -do { \ - if ( MACH64_VERBOSE ) { \ - DRM_INFO( "DMAGETPTR( %d )\n", (n) ); \ - } \ - _buf = mach64_freelist_get( dev_priv ); \ - if (_buf == NULL) { \ - DRM_ERROR("couldn't get buffer in DMAGETPTR\n"); \ - return -EAGAIN; \ - } \ - if (_buf->pending) { \ - DRM_ERROR("pending buf in DMAGETPTR\n"); \ - return -EFAULT; \ - } \ - _buf->file_priv = file_priv; \ - _outcount = 0; \ - \ - _buf_wptr = GETBUFPTR( _buf ); \ -} while (0) - -#define DMAOUTREG( reg, val ) \ -do { \ - if ( MACH64_VERBOSE ) { \ - DRM_INFO( " DMAOUTREG( 0x%x = 0x%08x )\n", \ - reg, val ); \ - } \ - _buf_wptr[_outcount++] = cpu_to_le32(DMAREG(reg)); \ - _buf_wptr[_outcount++] = cpu_to_le32((val)); \ - _buf->used += 8; \ -} while (0) - -#define DMAADVANCE( dev_priv, _discard ) \ - do { \ - struct list_head *ptr; \ - int ret; \ - \ - if ( MACH64_VERBOSE ) { \ - DRM_INFO( "DMAADVANCE() in \n" ); \ - } \ - \ - if (_buf->used <= 0) { \ - DRM_ERROR( "DMAADVANCE(): sending empty buf %d\n", \ - _buf->idx ); \ - return -EFAULT; \ - } \ - if (_buf->pending) { \ - /* This is a resued buffer, so we need to find it in the pending list */ \ - if ((ret = mach64_find_pending_buf_entry(dev_priv, &_entry, _buf))) { \ - DRM_ERROR( "DMAADVANCE(): couldn't find pending buf %d\n", _buf->idx ); \ - return ret; \ - } \ - if (_entry->discard) { \ - DRM_ERROR( "DMAADVANCE(): sending discarded pending buf %d\n", _buf->idx ); \ - return -EFAULT; \ - } \ - } else { \ - if (list_empty(&dev_priv->placeholders)) { \ - DRM_ERROR( "DMAADVANCE(): empty placeholder list\n"); \ - return -EFAULT; \ - } \ - ptr = dev_priv->placeholders.next; \ - list_del(ptr); \ - _entry = list_entry(ptr, drm_mach64_freelist_t, list); \ - _buf->pending = 1; \ - _entry->buf = _buf; \ - list_add_tail(ptr, &dev_priv->pending); \ - } \ - _entry->discard = (_discard); \ - if ((ret = mach64_add_buf_to_ring( dev_priv, _entry ))) \ - return ret; \ - } while (0) - -#define DMADISCARDBUF() \ - do { \ - if (_entry == NULL) { \ - int ret; \ - if ((ret = mach64_find_pending_buf_entry(dev_priv, &_entry, _buf))) { \ - DRM_ERROR( "couldn't find pending buf %d\n", \ - _buf->idx ); \ - return ret; \ - } \ - } \ - _entry->discard = 1; \ - } while(0) - -#define DMAADVANCEHOSTDATA( dev_priv ) \ - do { \ - struct list_head *ptr; \ - int ret; \ - \ - if ( MACH64_VERBOSE ) { \ - DRM_INFO( "DMAADVANCEHOSTDATA() in \n" ); \ - } \ - \ - if (_buf->used <= 0) { \ - DRM_ERROR( "DMAADVANCEHOSTDATA(): sending empty buf %d\n", _buf->idx ); \ - return -EFAULT; \ - } \ - if (list_empty(&dev_priv->placeholders)) { \ - DRM_ERROR( "empty placeholder list in DMAADVANCEHOSTDATA()\n" ); \ - return -EFAULT; \ - } \ - \ - ptr = dev_priv->placeholders.next; \ - list_del(ptr); \ - _entry = list_entry(ptr, drm_mach64_freelist_t, list); \ - _entry->buf = _buf; \ - _entry->buf->pending = 1; \ - list_add_tail(ptr, &dev_priv->pending); \ - _entry->discard = 1; \ - if ((ret = mach64_add_hostdata_buf_to_ring( dev_priv, _entry ))) \ - return ret; \ - } while (0) - -#endif /* __MACH64_DRV_H__ */ diff --git a/shared-core/mach64_irq.c b/shared-core/mach64_irq.c deleted file mode 100644 index 149d970a..00000000 --- a/shared-core/mach64_irq.c +++ /dev/null @@ -1,159 +0,0 @@ -/* mach64_irq.c -- IRQ handling for ATI Mach64 -*- linux-c -*- - * Created: Tue Feb 25, 2003 by Leif Delgass, based on radeon_irq.c/r128_irq.c - */ -/*- - * Copyright (C) The Weather Channel, Inc. 2002. - * Copyright 2003 Leif Delgass - * All Rights Reserved. - * - * The Weather Channel (TM) funded Tungsten Graphics to develop the - * initial release of the Radeon 8500 driver under the XFree86 license. - * This notice must be preserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Keith Whitwell - * Eric Anholt - * Leif Delgass - */ - -#include "drmP.h" -#include "drm.h" -#include "mach64_drm.h" -#include "mach64_drv.h" - -irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS) -{ - struct drm_device *dev = arg; - drm_mach64_private_t *dev_priv = dev->dev_private; - int status; - - status = MACH64_READ(MACH64_CRTC_INT_CNTL); - - /* VBLANK interrupt */ - if (status & MACH64_CRTC_VBLANK_INT) { - /* Mask off all interrupt ack bits before setting the ack bit, since - * there may be other handlers outside the DRM. - * - * NOTE: On mach64, you need to keep the enable bits set when doing - * the ack, despite what the docs say about not acking and enabling - * in a single write. - */ - MACH64_WRITE(MACH64_CRTC_INT_CNTL, - (status & ~MACH64_CRTC_INT_ACKS) - | MACH64_CRTC_VBLANK_INT); - - atomic_inc(&dev_priv->vbl_received); - drm_handle_vblank(dev, 0); - return IRQ_HANDLED; - } - return IRQ_NONE; -} - -u32 mach64_get_vblank_counter(struct drm_device * dev, int crtc) -{ - const drm_mach64_private_t *const dev_priv = dev->dev_private; - - if (crtc != 0) - return 0; - - return atomic_read(&dev_priv->vbl_received); -} - -int mach64_enable_vblank(struct drm_device * dev, int crtc) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - u32 status = MACH64_READ(MACH64_CRTC_INT_CNTL); - - if (crtc != 0) { - DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", - crtc); - return -EINVAL; - } - - DRM_DEBUG("before enable vblank CRTC_INT_CTNL: 0x%08x\n", status); - - /* Turn on VBLANK interrupt */ - MACH64_WRITE(MACH64_CRTC_INT_CNTL, MACH64_READ(MACH64_CRTC_INT_CNTL) - | MACH64_CRTC_VBLANK_INT_EN); - - return 0; -} - -void mach64_disable_vblank(struct drm_device * dev, int crtc) -{ - if (crtc != 0) { - DRM_ERROR("tried to disable vblank on non-existent crtc %d\n", - crtc); - return; - } - - /* - * FIXME: implement proper interrupt disable by using the vblank - * counter register (if available). - */ -} - -static void mach64_disable_vblank_local(struct drm_device * dev, int crtc) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - u32 status = MACH64_READ(MACH64_CRTC_INT_CNTL); - - if (crtc != 0) { - DRM_ERROR("tried to disable vblank on non-existent crtc %d\n", - crtc); - return; - } - - DRM_DEBUG("before disable vblank CRTC_INT_CTNL: 0x%08x\n", status); - - /* Disable and clear VBLANK interrupt */ - MACH64_WRITE(MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_VBLANK_INT_EN) - | MACH64_CRTC_VBLANK_INT); -} - -void mach64_driver_irq_preinstall(struct drm_device * dev) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - - u32 status = MACH64_READ(MACH64_CRTC_INT_CNTL); - - DRM_DEBUG("before install CRTC_INT_CTNL: 0x%08x\n", status); - - mach64_disable_vblank_local(dev, 0); -} - -int mach64_driver_irq_postinstall(struct drm_device * dev) -{ - return 0; -} - -void mach64_driver_irq_uninstall(struct drm_device * dev) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - if (!dev_priv) - return; - - mach64_disable_vblank_local(dev, 0); - - DRM_DEBUG("after uninstall CRTC_INT_CTNL: 0x%08x\n", - MACH64_READ(MACH64_CRTC_INT_CNTL)); -} diff --git a/shared-core/mach64_state.c b/shared-core/mach64_state.c deleted file mode 100644 index c82f38bb..00000000 --- a/shared-core/mach64_state.c +++ /dev/null @@ -1,910 +0,0 @@ -/* mach64_state.c -- State support for mach64 (Rage Pro) driver -*- linux-c -*- - * Created: Sun Dec 03 19:20:26 2000 by gareth@valinux.com - */ -/* - * Copyright 2000 Gareth Hughes - * Copyright 2002-2003 Leif Delgass - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Leif Delgass - * José Fonseca - */ - -#include "drmP.h" -#include "drm.h" -#include "mach64_drm.h" -#include "mach64_drv.h" - -/* Interface history: - * - * 1.0 - Initial mach64 DRM - * - */ -struct drm_ioctl_desc mach64_ioctls[] = { - DRM_IOCTL_DEF(DRM_MACH64_INIT, mach64_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_MACH64_CLEAR, mach64_dma_clear, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MACH64_SWAP, mach64_dma_swap, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MACH64_IDLE, mach64_dma_idle, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MACH64_RESET, mach64_engine_reset, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MACH64_VERTEX, mach64_dma_vertex, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MACH64_BLIT, mach64_dma_blit, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MACH64_FLUSH, mach64_dma_flush, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MACH64_GETPARAM, mach64_get_param, DRM_AUTH), -}; - -int mach64_max_ioctl = DRM_ARRAY_SIZE(mach64_ioctls); - -/* ================================================================ - * DMA hardware state programming functions - */ - -static void mach64_print_dirty(const char *msg, unsigned int flags) -{ - DRM_DEBUG("%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s\n", - msg, - flags, - (flags & MACH64_UPLOAD_DST_OFF_PITCH) ? "dst_off_pitch, " : - "", - (flags & MACH64_UPLOAD_Z_ALPHA_CNTL) ? "z_alpha_cntl, " : "", - (flags & MACH64_UPLOAD_SCALE_3D_CNTL) ? "scale_3d_cntl, " : - "", (flags & MACH64_UPLOAD_DP_FOG_CLR) ? "dp_fog_clr, " : "", - (flags & MACH64_UPLOAD_DP_WRITE_MASK) ? "dp_write_mask, " : - "", - (flags & MACH64_UPLOAD_DP_PIX_WIDTH) ? "dp_pix_width, " : "", - (flags & MACH64_UPLOAD_SETUP_CNTL) ? "setup_cntl, " : "", - (flags & MACH64_UPLOAD_MISC) ? "misc, " : "", - (flags & MACH64_UPLOAD_TEXTURE) ? "texture, " : "", - (flags & MACH64_UPLOAD_TEX0IMAGE) ? "tex0 image, " : "", - (flags & MACH64_UPLOAD_TEX1IMAGE) ? "tex1 image, " : "", - (flags & MACH64_UPLOAD_CLIPRECTS) ? "cliprects, " : ""); -} - -/* Mach64 doesn't have hardware cliprects, just one hardware scissor, - * so the GL scissor is intersected with each cliprect here - */ -/* This function returns 0 on success, 1 for no intersection, and - * negative for an error - */ -static int mach64_emit_cliprect(struct drm_file *file_priv, - drm_mach64_private_t * dev_priv, - struct drm_clip_rect * box) -{ - u32 sc_left_right, sc_top_bottom; - struct drm_clip_rect scissor; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mach64_context_regs_t *regs = &sarea_priv->context_state; - DMALOCALS; - - DRM_DEBUG("box=%p\n", box); - - /* Get GL scissor */ - /* FIXME: store scissor in SAREA as a cliprect instead of in - * hardware format, or do intersection client-side - */ - scissor.x1 = regs->sc_left_right & 0xffff; - scissor.x2 = (regs->sc_left_right & 0xffff0000) >> 16; - scissor.y1 = regs->sc_top_bottom & 0xffff; - scissor.y2 = (regs->sc_top_bottom & 0xffff0000) >> 16; - - /* Intersect GL scissor with cliprect */ - if (box->x1 > scissor.x1) - scissor.x1 = box->x1; - if (box->y1 > scissor.y1) - scissor.y1 = box->y1; - if (box->x2 < scissor.x2) - scissor.x2 = box->x2; - if (box->y2 < scissor.y2) - scissor.y2 = box->y2; - /* positive return means skip */ - if (scissor.x1 >= scissor.x2) - return 1; - if (scissor.y1 >= scissor.y2) - return 1; - - DMAGETPTR(file_priv, dev_priv, 2); /* returns on failure to get buffer */ - - sc_left_right = ((scissor.x1 << 0) | (scissor.x2 << 16)); - sc_top_bottom = ((scissor.y1 << 0) | (scissor.y2 << 16)); - - DMAOUTREG(MACH64_SC_LEFT_RIGHT, sc_left_right); - DMAOUTREG(MACH64_SC_TOP_BOTTOM, sc_top_bottom); - - DMAADVANCE(dev_priv, 1); - - return 0; -} - -static __inline__ int mach64_emit_state(struct drm_file *file_priv, - drm_mach64_private_t * dev_priv) -{ - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mach64_context_regs_t *regs = &sarea_priv->context_state; - unsigned int dirty = sarea_priv->dirty; - u32 offset = ((regs->tex_size_pitch & 0xf0) >> 2); - DMALOCALS; - - if (MACH64_VERBOSE) { - mach64_print_dirty(__FUNCTION__, dirty); - } else { - DRM_DEBUG("dirty=0x%08x\n", dirty); - } - - DMAGETPTR(file_priv, dev_priv, 17); /* returns on failure to get buffer */ - - if (dirty & MACH64_UPLOAD_MISC) { - DMAOUTREG(MACH64_DP_MIX, regs->dp_mix); - DMAOUTREG(MACH64_DP_SRC, regs->dp_src); - DMAOUTREG(MACH64_CLR_CMP_CNTL, regs->clr_cmp_cntl); - DMAOUTREG(MACH64_GUI_TRAJ_CNTL, regs->gui_traj_cntl); - sarea_priv->dirty &= ~MACH64_UPLOAD_MISC; - } - - if (dirty & MACH64_UPLOAD_DST_OFF_PITCH) { - DMAOUTREG(MACH64_DST_OFF_PITCH, regs->dst_off_pitch); - sarea_priv->dirty &= ~MACH64_UPLOAD_DST_OFF_PITCH; - } - if (dirty & MACH64_UPLOAD_Z_OFF_PITCH) { - DMAOUTREG(MACH64_Z_OFF_PITCH, regs->z_off_pitch); - sarea_priv->dirty &= ~MACH64_UPLOAD_Z_OFF_PITCH; - } - if (dirty & MACH64_UPLOAD_Z_ALPHA_CNTL) { - DMAOUTREG(MACH64_Z_CNTL, regs->z_cntl); - DMAOUTREG(MACH64_ALPHA_TST_CNTL, regs->alpha_tst_cntl); - sarea_priv->dirty &= ~MACH64_UPLOAD_Z_ALPHA_CNTL; - } - if (dirty & MACH64_UPLOAD_SCALE_3D_CNTL) { - DMAOUTREG(MACH64_SCALE_3D_CNTL, regs->scale_3d_cntl); - sarea_priv->dirty &= ~MACH64_UPLOAD_SCALE_3D_CNTL; - } - if (dirty & MACH64_UPLOAD_DP_FOG_CLR) { - DMAOUTREG(MACH64_DP_FOG_CLR, regs->dp_fog_clr); - sarea_priv->dirty &= ~MACH64_UPLOAD_DP_FOG_CLR; - } - if (dirty & MACH64_UPLOAD_DP_WRITE_MASK) { - DMAOUTREG(MACH64_DP_WRITE_MASK, regs->dp_write_mask); - sarea_priv->dirty &= ~MACH64_UPLOAD_DP_WRITE_MASK; - } - if (dirty & MACH64_UPLOAD_DP_PIX_WIDTH) { - DMAOUTREG(MACH64_DP_PIX_WIDTH, regs->dp_pix_width); - sarea_priv->dirty &= ~MACH64_UPLOAD_DP_PIX_WIDTH; - } - if (dirty & MACH64_UPLOAD_SETUP_CNTL) { - DMAOUTREG(MACH64_SETUP_CNTL, regs->setup_cntl); - sarea_priv->dirty &= ~MACH64_UPLOAD_SETUP_CNTL; - } - - if (dirty & MACH64_UPLOAD_TEXTURE) { - DMAOUTREG(MACH64_TEX_SIZE_PITCH, regs->tex_size_pitch); - DMAOUTREG(MACH64_TEX_CNTL, regs->tex_cntl); - DMAOUTREG(MACH64_SECONDARY_TEX_OFF, regs->secondary_tex_off); - DMAOUTREG(MACH64_TEX_0_OFF + offset, regs->tex_offset); - sarea_priv->dirty &= ~MACH64_UPLOAD_TEXTURE; - } - - DMAADVANCE(dev_priv, 1); - - sarea_priv->dirty &= MACH64_UPLOAD_CLIPRECTS; - - return 0; - -} - -/* ================================================================ - * DMA command dispatch functions - */ - -static int mach64_dma_dispatch_clear(struct drm_device * dev, - struct drm_file *file_priv, - unsigned int flags, - int cx, int cy, int cw, int ch, - unsigned int clear_color, - unsigned int clear_depth) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mach64_context_regs_t *ctx = &sarea_priv->context_state; - int nbox = sarea_priv->nbox; - struct drm_clip_rect *pbox = sarea_priv->boxes; - u32 fb_bpp, depth_bpp; - int i; - DMALOCALS; - - DRM_DEBUG("\n"); - - switch (dev_priv->fb_bpp) { - case 16: - fb_bpp = MACH64_DATATYPE_RGB565; - break; - case 32: - fb_bpp = MACH64_DATATYPE_ARGB8888; - break; - default: - return -EINVAL; - } - switch (dev_priv->depth_bpp) { - case 16: - depth_bpp = MACH64_DATATYPE_RGB565; - break; - case 24: - case 32: - depth_bpp = MACH64_DATATYPE_ARGB8888; - break; - default: - return -EINVAL; - } - - if (!nbox) - return 0; - - DMAGETPTR(file_priv, dev_priv, nbox * 31); /* returns on failure to get buffer */ - - for (i = 0; i < nbox; i++) { - int x = pbox[i].x1; - int y = pbox[i].y1; - int w = pbox[i].x2 - x; - int h = pbox[i].y2 - y; - - DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n", - pbox[i].x1, pbox[i].y1, - pbox[i].x2, pbox[i].y2, flags); - - if (flags & (MACH64_FRONT | MACH64_BACK)) { - /* Setup for color buffer clears - */ - - DMAOUTREG(MACH64_Z_CNTL, 0); - DMAOUTREG(MACH64_SCALE_3D_CNTL, 0); - - DMAOUTREG(MACH64_SC_LEFT_RIGHT, ctx->sc_left_right); - DMAOUTREG(MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom); - - DMAOUTREG(MACH64_CLR_CMP_CNTL, 0); - DMAOUTREG(MACH64_GUI_TRAJ_CNTL, - (MACH64_DST_X_LEFT_TO_RIGHT | - MACH64_DST_Y_TOP_TO_BOTTOM)); - - DMAOUTREG(MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) | - (fb_bpp << 4) | - (fb_bpp << 8) | - (fb_bpp << 16) | - (fb_bpp << 28))); - - DMAOUTREG(MACH64_DP_FRGD_CLR, clear_color); - DMAOUTREG(MACH64_DP_WRITE_MASK, ctx->dp_write_mask); - DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D | - MACH64_FRGD_MIX_S)); - DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR | - MACH64_FRGD_SRC_FRGD_CLR | - MACH64_MONO_SRC_ONE)); - - } - - if (flags & MACH64_FRONT) { - - DMAOUTREG(MACH64_DST_OFF_PITCH, - dev_priv->front_offset_pitch); - DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x); - DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w); - - } - - if (flags & MACH64_BACK) { - - DMAOUTREG(MACH64_DST_OFF_PITCH, - dev_priv->back_offset_pitch); - DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x); - DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w); - - } - - if (flags & MACH64_DEPTH) { - /* Setup for depth buffer clear - */ - DMAOUTREG(MACH64_Z_CNTL, 0); - DMAOUTREG(MACH64_SCALE_3D_CNTL, 0); - - DMAOUTREG(MACH64_SC_LEFT_RIGHT, ctx->sc_left_right); - DMAOUTREG(MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom); - - DMAOUTREG(MACH64_CLR_CMP_CNTL, 0); - DMAOUTREG(MACH64_GUI_TRAJ_CNTL, - (MACH64_DST_X_LEFT_TO_RIGHT | - MACH64_DST_Y_TOP_TO_BOTTOM)); - - DMAOUTREG(MACH64_DP_PIX_WIDTH, ((depth_bpp << 0) | - (depth_bpp << 4) | - (depth_bpp << 8) | - (depth_bpp << 16) | - (depth_bpp << 28))); - - DMAOUTREG(MACH64_DP_FRGD_CLR, clear_depth); - DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff); - DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D | - MACH64_FRGD_MIX_S)); - DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR | - MACH64_FRGD_SRC_FRGD_CLR | - MACH64_MONO_SRC_ONE)); - - DMAOUTREG(MACH64_DST_OFF_PITCH, - dev_priv->depth_offset_pitch); - DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x); - DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w); - } - } - - DMAADVANCE(dev_priv, 1); - - return 0; -} - -static int mach64_dma_dispatch_swap(struct drm_device * dev, - struct drm_file *file_priv) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - int nbox = sarea_priv->nbox; - struct drm_clip_rect *pbox = sarea_priv->boxes; - u32 fb_bpp; - int i; - DMALOCALS; - - DRM_DEBUG("\n"); - - switch (dev_priv->fb_bpp) { - case 16: - fb_bpp = MACH64_DATATYPE_RGB565; - break; - case 32: - default: - fb_bpp = MACH64_DATATYPE_ARGB8888; - break; - } - - if (!nbox) - return 0; - - DMAGETPTR(file_priv, dev_priv, 13 + nbox * 4); /* returns on failure to get buffer */ - - DMAOUTREG(MACH64_Z_CNTL, 0); - DMAOUTREG(MACH64_SCALE_3D_CNTL, 0); - - DMAOUTREG(MACH64_SC_LEFT_RIGHT, 0 | (8191 << 16)); /* no scissor */ - DMAOUTREG(MACH64_SC_TOP_BOTTOM, 0 | (16383 << 16)); - - DMAOUTREG(MACH64_CLR_CMP_CNTL, 0); - DMAOUTREG(MACH64_GUI_TRAJ_CNTL, (MACH64_DST_X_LEFT_TO_RIGHT | - MACH64_DST_Y_TOP_TO_BOTTOM)); - - DMAOUTREG(MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) | - (fb_bpp << 4) | - (fb_bpp << 8) | - (fb_bpp << 16) | (fb_bpp << 28))); - - DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff); - DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D | MACH64_FRGD_MIX_S)); - DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_BKGD_CLR | - MACH64_FRGD_SRC_BLIT | MACH64_MONO_SRC_ONE)); - - DMAOUTREG(MACH64_SRC_OFF_PITCH, dev_priv->back_offset_pitch); - DMAOUTREG(MACH64_DST_OFF_PITCH, dev_priv->front_offset_pitch); - - for (i = 0; i < nbox; i++) { - int x = pbox[i].x1; - int y = pbox[i].y1; - int w = pbox[i].x2 - x; - int h = pbox[i].y2 - y; - - DRM_DEBUG("dispatch swap %d,%d-%d,%d\n", - pbox[i].x1, pbox[i].y1, pbox[i].x2, pbox[i].y2); - - DMAOUTREG(MACH64_SRC_WIDTH1, w); - DMAOUTREG(MACH64_SRC_Y_X, (x << 16) | y); - DMAOUTREG(MACH64_DST_Y_X, (x << 16) | y); - DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w); - - } - - DMAADVANCE(dev_priv, 1); - - if (dev_priv->driver_mode == MACH64_MODE_DMA_ASYNC) { - for (i = 0; i < MACH64_MAX_QUEUED_FRAMES - 1; i++) { - dev_priv->frame_ofs[i] = dev_priv->frame_ofs[i + 1]; - } - dev_priv->frame_ofs[i] = GETRINGOFFSET(); - - dev_priv->sarea_priv->frames_queued++; - } - - return 0; -} - -static int mach64_do_get_frames_queued(drm_mach64_private_t * dev_priv) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - int i, start; - u32 head, tail, ofs; - - DRM_DEBUG("\n"); - - if (sarea_priv->frames_queued == 0) - return 0; - - tail = ring->tail; - mach64_ring_tick(dev_priv, ring); - head = ring->head; - - start = (MACH64_MAX_QUEUED_FRAMES - - DRM_MIN(MACH64_MAX_QUEUED_FRAMES, sarea_priv->frames_queued)); - - if (head == tail) { - sarea_priv->frames_queued = 0; - for (i = start; i < MACH64_MAX_QUEUED_FRAMES; i++) { - dev_priv->frame_ofs[i] = ~0; - } - return 0; - } - - for (i = start; i < MACH64_MAX_QUEUED_FRAMES; i++) { - ofs = dev_priv->frame_ofs[i]; - DRM_DEBUG("frame_ofs[%d] ofs: %d\n", i, ofs); - if (ofs == ~0 || - (head < tail && (ofs < head || ofs >= tail)) || - (head > tail && (ofs < head && ofs >= tail))) { - sarea_priv->frames_queued = - (MACH64_MAX_QUEUED_FRAMES - 1) - i; - dev_priv->frame_ofs[i] = ~0; - } - } - - return sarea_priv->frames_queued; -} - -/* Copy and verify a client submited buffer. - * FIXME: Make an assembly optimized version - */ -static __inline__ int copy_from_user_vertex(u32 *to, - const u32 __user *ufrom, - unsigned long bytes) -{ - unsigned long n = bytes; /* dwords remaining in buffer */ - u32 *from, *orig_from; - - from = drm_alloc(bytes, DRM_MEM_DRIVER); - if (from == NULL) - return -ENOMEM; - - if (DRM_COPY_FROM_USER(from, ufrom, bytes)) { - drm_free(from, bytes, DRM_MEM_DRIVER); - return -EFAULT; - } - orig_from = from; /* we'll be modifying the "from" ptr, so save it */ - - n >>= 2; - - while (n > 1) { - u32 data, reg, count; - - data = *from++; - - n--; - - reg = le32_to_cpu(data); - count = (reg >> 16) + 1; - if (count <= n) { - n -= count; - reg &= 0xffff; - - /* This is an exact match of Mach64's Setup Engine registers, - * excluding SETUP_CNTL (1_C1). - */ - if ((reg >= 0x0190 && reg < 0x01c1) || - (reg >= 0x01ca && reg <= 0x01cf)) { - *to++ = data; - memcpy(to, from, count << 2); - from += count; - to += count; - } else { - DRM_ERROR("Got bad command: 0x%04x\n", reg); - drm_free(orig_from, bytes, DRM_MEM_DRIVER); - return -EACCES; - } - } else { - DRM_ERROR - ("Got bad command count(=%u) dwords remaining=%lu\n", - count, n); - drm_free(orig_from, bytes, DRM_MEM_DRIVER); - return -EINVAL; - } - } - - drm_free(orig_from, bytes, DRM_MEM_DRIVER); - if (n == 0) - return 0; - else { - DRM_ERROR("Bad buf->used(=%lu)\n", bytes); - return -EINVAL; - } -} - -static int mach64_dma_dispatch_vertex(struct drm_device * dev, - struct drm_file *file_priv, - drm_mach64_vertex_t * vertex) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - struct drm_buf *copy_buf; - void *buf = vertex->buf; - unsigned long used = vertex->used; - int ret = 0; - int i = 0; - int done = 0; - int verify_ret = 0; - DMALOCALS; - - DRM_DEBUG("buf=%p used=%lu nbox=%d\n", - buf, used, sarea_priv->nbox); - - if (!used) - goto _vertex_done; - - copy_buf = mach64_freelist_get(dev_priv); - if (copy_buf == NULL) { - DRM_ERROR("couldn't get buffer\n"); - return -EAGAIN; - } - - /* Mach64's vertex data is actually register writes. To avoid security - * compromises these register writes have to be verified and copied from - * user space into a private DMA buffer. - */ - verify_ret = copy_from_user_vertex(GETBUFPTR(copy_buf), buf, used); - - if (verify_ret != 0) { - mach64_freelist_put(dev_priv, copy_buf); - goto _vertex_done; - } - - copy_buf->used = used; - - DMASETPTR(copy_buf); - - if (sarea_priv->dirty & ~MACH64_UPLOAD_CLIPRECTS) { - ret = mach64_emit_state(file_priv, dev_priv); - if (ret < 0) - return ret; - } - - do { - /* Emit the next cliprect */ - if (i < sarea_priv->nbox) { - ret = mach64_emit_cliprect(file_priv, dev_priv, - &sarea_priv->boxes[i]); - if (ret < 0) { - /* failed to get buffer */ - return ret; - } else if (ret != 0) { - /* null intersection with scissor */ - continue; - } - } - if ((i >= sarea_priv->nbox - 1)) - done = 1; - - /* Add the buffer to the DMA queue */ - DMAADVANCE(dev_priv, done); - - } while (++i < sarea_priv->nbox); - - if (!done) { - if (copy_buf->pending) { - DMADISCARDBUF(); - } else { - /* This buffer wasn't used (no cliprects), so place it - * back on the free list - */ - mach64_freelist_put(dev_priv, copy_buf); - } - } - -_vertex_done: - sarea_priv->dirty &= ~MACH64_UPLOAD_CLIPRECTS; - sarea_priv->nbox = 0; - - return verify_ret; -} - -static __inline__ int copy_from_user_blit(u32 *to, - const u32 __user *ufrom, - unsigned long bytes) -{ - to = (u32 *)((char *)to + MACH64_HOSTDATA_BLIT_OFFSET); - - if (DRM_COPY_FROM_USER(to, ufrom, bytes)) { - return -EFAULT; - } - - return 0; -} - -static int mach64_dma_dispatch_blit(struct drm_device * dev, - struct drm_file *file_priv, - drm_mach64_blit_t * blit) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - int dword_shift, dwords; - unsigned long used; - struct drm_buf *copy_buf; - int verify_ret = 0; - DMALOCALS; - - /* The compiler won't optimize away a division by a variable, - * even if the only legal values are powers of two. Thus, we'll - * use a shift instead. - */ - switch (blit->format) { - case MACH64_DATATYPE_ARGB8888: - dword_shift = 0; - break; - case MACH64_DATATYPE_ARGB1555: - case MACH64_DATATYPE_RGB565: - case MACH64_DATATYPE_VYUY422: - case MACH64_DATATYPE_YVYU422: - case MACH64_DATATYPE_ARGB4444: - dword_shift = 1; - break; - case MACH64_DATATYPE_CI8: - case MACH64_DATATYPE_RGB8: - dword_shift = 2; - break; - default: - DRM_ERROR("invalid blit format %d\n", blit->format); - return -EINVAL; - } - - /* Set buf->used to the bytes of blit data based on the blit dimensions - * and verify the size. When the setup is emitted to the buffer with - * the DMA* macros below, buf->used is incremented to include the bytes - * used for setup as well as the blit data. - */ - dwords = (blit->width * blit->height) >> dword_shift; - used = dwords << 2; - if (used <= 0 || - used > MACH64_BUFFER_SIZE - MACH64_HOSTDATA_BLIT_OFFSET) { - DRM_ERROR("Invalid blit size: %lu bytes\n", used); - return -EINVAL; - } - - copy_buf = mach64_freelist_get(dev_priv); - if (copy_buf == NULL) { - DRM_ERROR("couldn't get buffer\n"); - return -EAGAIN; - } - - /* Copy the blit data from userspace. - * - * XXX: This is overkill. The most efficient solution would be having - * two sets of buffers (one set private for vertex data, the other set - * client-writable for blits). However that would bring more complexity - * and would break backward compatability. The solution currently - * implemented is keeping all buffers private, allowing to secure the - * driver, without increasing complexity at the expense of some speed - * transfering data. - */ - verify_ret = copy_from_user_blit(GETBUFPTR(copy_buf), blit->buf, used); - - if (verify_ret != 0) { - mach64_freelist_put(dev_priv, copy_buf); - goto _blit_done; - } - - copy_buf->used = used; - - /* FIXME: Use a last buffer flag and reduce the state emitted for subsequent, - * continuation buffers? - */ - - /* Blit via BM_HOSTDATA (gui-master) - like HOST_DATA[0-15], but doesn't require - * a register command every 16 dwords. State setup is added at the start of the - * buffer -- the client leaves space for this based on MACH64_HOSTDATA_BLIT_OFFSET - */ - DMASETPTR(copy_buf); - - DMAOUTREG(MACH64_Z_CNTL, 0); - DMAOUTREG(MACH64_SCALE_3D_CNTL, 0); - - DMAOUTREG(MACH64_SC_LEFT_RIGHT, 0 | (8191 << 16)); /* no scissor */ - DMAOUTREG(MACH64_SC_TOP_BOTTOM, 0 | (16383 << 16)); - - DMAOUTREG(MACH64_CLR_CMP_CNTL, 0); /* disable */ - DMAOUTREG(MACH64_GUI_TRAJ_CNTL, - MACH64_DST_X_LEFT_TO_RIGHT | MACH64_DST_Y_TOP_TO_BOTTOM); - - DMAOUTREG(MACH64_DP_PIX_WIDTH, (blit->format << 0) /* dst pix width */ - |(blit->format << 4) /* composite pix width */ - |(blit->format << 8) /* src pix width */ - |(blit->format << 16) /* host data pix width */ - |(blit->format << 28) /* scaler/3D pix width */ - ); - - DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff); /* enable all planes */ - DMAOUTREG(MACH64_DP_MIX, MACH64_BKGD_MIX_D | MACH64_FRGD_MIX_S); - DMAOUTREG(MACH64_DP_SRC, - MACH64_BKGD_SRC_BKGD_CLR - | MACH64_FRGD_SRC_HOST | MACH64_MONO_SRC_ONE); - - DMAOUTREG(MACH64_DST_OFF_PITCH, - (blit->pitch << 22) | (blit->offset >> 3)); - DMAOUTREG(MACH64_DST_X_Y, (blit->y << 16) | blit->x); - DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (blit->height << 16) | blit->width); - - DRM_DEBUG("%lu bytes\n", used); - - /* Add the buffer to the queue */ - DMAADVANCEHOSTDATA(dev_priv); - -_blit_done: - return verify_ret; -} - -/* ================================================================ - * IOCTL functions - */ - -int mach64_dma_clear(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mach64_clear_t *clear = data; - int ret; - - DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS) - sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS; - - ret = mach64_dma_dispatch_clear(dev, file_priv, clear->flags, - clear->x, clear->y, clear->w, clear->h, - clear->clear_color, - clear->clear_depth); - - /* Make sure we restore the 3D state next time. - */ - sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | MACH64_UPLOAD_MISC); - return ret; -} - -int mach64_dma_swap(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - int ret; - - DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS) - sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS; - - ret = mach64_dma_dispatch_swap(dev, file_priv); - - /* Make sure we restore the 3D state next time. - */ - sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | MACH64_UPLOAD_MISC); - return ret; -} - -int mach64_dma_vertex(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mach64_vertex_t *vertex = data; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - DRM_DEBUG("pid=%d buf=%p used=%lu discard=%d\n", - DRM_CURRENTPID, - vertex->buf, vertex->used, vertex->discard); - - if (vertex->prim < 0 || vertex->prim > MACH64_PRIM_POLYGON) { - DRM_ERROR("buffer prim %d\n", vertex->prim); - return -EINVAL; - } - - if (vertex->used > MACH64_BUFFER_SIZE || (vertex->used & 3) != 0) { - DRM_ERROR("Invalid vertex buffer size: %lu bytes\n", - vertex->used); - return -EINVAL; - } - - if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS) - sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS; - - return mach64_dma_dispatch_vertex(dev, file_priv, vertex); -} - -int mach64_dma_blit(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mach64_blit_t *blit = data; - int ret; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - ret = mach64_dma_dispatch_blit(dev, file_priv, blit); - - /* Make sure we restore the 3D state next time. - */ - sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | - MACH64_UPLOAD_MISC | MACH64_UPLOAD_CLIPRECTS); - - return ret; -} - -int mach64_get_param(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_getparam_t *param = data; - int value; - - DRM_DEBUG("\n"); - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - switch (param->param) { - case MACH64_PARAM_FRAMES_QUEUED: - /* Needs lock since it calls mach64_ring_tick() */ - LOCK_TEST_WITH_RETURN(dev, file_priv); - value = mach64_do_get_frames_queued(dev_priv); - break; - case MACH64_PARAM_IRQ_NR: - value = dev->irq; - break; - default: - return -EINVAL; - } - - if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { - DRM_ERROR("copy_to_user\n"); - return -EFAULT; - } - - return 0; -} diff --git a/shared-core/mga_dma.c b/shared-core/mga_dma.c deleted file mode 100644 index dab94034..00000000 --- a/shared-core/mga_dma.c +++ /dev/null @@ -1,1169 +0,0 @@ -/* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*- - * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com - */ -/* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -/** - * \file mga_dma.c - * DMA support for MGA G200 / G400. - * - * \author Rickard E. (Rik) Faith - * \author Jeff Hartmann - * \author Keith Whitwell - * \author Gareth Hughes - */ - -#include "drmP.h" -#include "drm.h" -#include "drm_sarea.h" -#include "mga_drm.h" -#include "mga_drv.h" - -#define MGA_DEFAULT_USEC_TIMEOUT 10000 -#define MGA_FREELIST_DEBUG 0 - -#define MINIMAL_CLEANUP 0 -#define FULL_CLEANUP 1 -static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup); - -/* ================================================================ - * Engine control - */ - -int mga_do_wait_for_idle(drm_mga_private_t * dev_priv) -{ - u32 status = 0; - int i; - DRM_DEBUG("\n"); - - for (i = 0; i < dev_priv->usec_timeout; i++) { - status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; - if (status == MGA_ENDPRDMASTS) { - MGA_WRITE8(MGA_CRTC_INDEX, 0); - return 0; - } - DRM_UDELAY(1); - } - -#if MGA_DMA_DEBUG - DRM_ERROR("failed!\n"); - DRM_INFO(" status=0x%08x\n", status); -#endif - return -EBUSY; -} - -static int mga_do_dma_reset(drm_mga_private_t * dev_priv) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_primary_buffer_t *primary = &dev_priv->prim; - - DRM_DEBUG("\n"); - - /* The primary DMA stream should look like new right about now. - */ - primary->tail = 0; - primary->space = primary->size; - primary->last_flush = 0; - - sarea_priv->last_wrap = 0; - - /* FIXME: Reset counters, buffer ages etc... - */ - - /* FIXME: What else do we need to reinitialize? WARP stuff? - */ - - return 0; -} - -/* ================================================================ - * Primary DMA stream - */ - -void mga_do_dma_flush(drm_mga_private_t * dev_priv) -{ - drm_mga_primary_buffer_t *primary = &dev_priv->prim; - u32 head, tail; - u32 status = 0; - int i; - DMA_LOCALS; - DRM_DEBUG("\n"); - - /* We need to wait so that we can do an safe flush */ - for (i = 0; i < dev_priv->usec_timeout; i++) { - status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; - if (status == MGA_ENDPRDMASTS) - break; - DRM_UDELAY(1); - } - - if (primary->tail == primary->last_flush) { - DRM_DEBUG(" bailing out...\n"); - return; - } - - tail = primary->tail + dev_priv->primary->offset; - - /* We need to pad the stream between flushes, as the card - * actually (partially?) reads the first of these commands. - * See page 4-16 in the G400 manual, middle of the page or so. - */ - BEGIN_DMA(1); - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); - - ADVANCE_DMA(); - - primary->last_flush = primary->tail; - - head = MGA_READ(MGA_PRIMADDRESS); - - if (head <= tail) { - primary->space = primary->size - primary->tail; - } else { - primary->space = head - tail; - } - - DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset); - DRM_DEBUG(" tail = 0x%06lx\n", tail - dev_priv->primary->offset); - DRM_DEBUG(" space = 0x%06x\n", primary->space); - - mga_flush_write_combine(); - MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); - - DRM_DEBUG("done.\n"); -} - -void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv) -{ - drm_mga_primary_buffer_t *primary = &dev_priv->prim; - u32 head, tail; - DMA_LOCALS; - DRM_DEBUG("\n"); - - BEGIN_DMA_WRAP(); - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); - - ADVANCE_DMA(); - - tail = primary->tail + dev_priv->primary->offset; - - primary->tail = 0; - primary->last_flush = 0; - primary->last_wrap++; - - head = MGA_READ(MGA_PRIMADDRESS); - - if (head == dev_priv->primary->offset) { - primary->space = primary->size; - } else { - primary->space = head - dev_priv->primary->offset; - } - - DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset); - DRM_DEBUG(" tail = 0x%06x\n", primary->tail); - DRM_DEBUG(" wrap = %d\n", primary->last_wrap); - DRM_DEBUG(" space = 0x%06x\n", primary->space); - - mga_flush_write_combine(); - MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); - - set_bit(0, &primary->wrapped); - DRM_DEBUG("done.\n"); -} - -void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv) -{ - drm_mga_primary_buffer_t *primary = &dev_priv->prim; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - u32 head = dev_priv->primary->offset; - DRM_DEBUG("\n"); - - sarea_priv->last_wrap++; - DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap); - - mga_flush_write_combine(); - MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL); - - clear_bit(0, &primary->wrapped); - DRM_DEBUG("done.\n"); -} - -/* ================================================================ - * Freelist management - */ - -#define MGA_BUFFER_USED ~0 -#define MGA_BUFFER_FREE 0 - -#if MGA_FREELIST_DEBUG -static void mga_freelist_print(struct drm_device * dev) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_freelist_t *entry; - - DRM_INFO("\n"); - DRM_INFO("current dispatch: last=0x%x done=0x%x\n", - dev_priv->sarea_priv->last_dispatch, - (unsigned int)(MGA_READ(MGA_PRIMADDRESS) - - dev_priv->primary->offset)); - DRM_INFO("current freelist:\n"); - - for (entry = dev_priv->head->next; entry; entry = entry->next) { - DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n", - entry, entry->buf->idx, entry->age.head, - entry->age.head - dev_priv->primary->offset); - } - DRM_INFO("\n"); -} -#endif - -static int mga_freelist_init(struct drm_device * dev, drm_mga_private_t * dev_priv) -{ - struct drm_device_dma *dma = dev->dma; - struct drm_buf *buf; - drm_mga_buf_priv_t *buf_priv; - drm_mga_freelist_t *entry; - int i; - DRM_DEBUG("count=%d\n", dma->buf_count); - - dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); - if (dev_priv->head == NULL) - return -ENOMEM; - - memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t)); - SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0); - - for (i = 0; i < dma->buf_count; i++) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - - entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); - if (entry == NULL) - return -ENOMEM; - - memset(entry, 0, sizeof(drm_mga_freelist_t)); - - entry->next = dev_priv->head->next; - entry->prev = dev_priv->head; - SET_AGE(&entry->age, MGA_BUFFER_FREE, 0); - entry->buf = buf; - - if (dev_priv->head->next != NULL) - dev_priv->head->next->prev = entry; - if (entry->next == NULL) - dev_priv->tail = entry; - - buf_priv->list_entry = entry; - buf_priv->discard = 0; - buf_priv->dispatched = 0; - - dev_priv->head->next = entry; - } - - return 0; -} - -static void mga_freelist_cleanup(struct drm_device * dev) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_freelist_t *entry; - drm_mga_freelist_t *next; - DRM_DEBUG("\n"); - - entry = dev_priv->head; - while (entry) { - next = entry->next; - drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); - entry = next; - } - - dev_priv->head = dev_priv->tail = NULL; -} - -#if 0 -/* FIXME: Still needed? - */ -static void mga_freelist_reset(struct drm_device * dev) -{ - drm_device_dma_t *dma = dev->dma; - struct drm_buf *buf; - drm_mga_buf_priv_t *buf_priv; - int i; - - for (i = 0; i < dma->buf_count; i++) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0); - } -} -#endif - -static struct drm_buf *mga_freelist_get(struct drm_device * dev) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_freelist_t *next; - drm_mga_freelist_t *prev; - drm_mga_freelist_t *tail = dev_priv->tail; - u32 head, wrap; - DRM_DEBUG("\n"); - - head = MGA_READ(MGA_PRIMADDRESS); - wrap = dev_priv->sarea_priv->last_wrap; - - DRM_DEBUG(" tail=0x%06lx %d\n", - tail->age.head ? - tail->age.head - dev_priv->primary->offset : 0, - tail->age.wrap); - DRM_DEBUG(" head=0x%06lx %d\n", - head - dev_priv->primary->offset, wrap); - - if (TEST_AGE(&tail->age, head, wrap)) { - prev = dev_priv->tail->prev; - next = dev_priv->tail; - prev->next = NULL; - next->prev = next->next = NULL; - dev_priv->tail = prev; - SET_AGE(&next->age, MGA_BUFFER_USED, 0); - return next->buf; - } - - DRM_DEBUG("returning NULL!\n"); - return NULL; -} - -int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_buf_priv_t *buf_priv = buf->dev_private; - drm_mga_freelist_t *head, *entry, *prev; - - DRM_DEBUG("age=0x%06lx wrap=%d\n", - buf_priv->list_entry->age.head - - dev_priv->primary->offset, buf_priv->list_entry->age.wrap); - - entry = buf_priv->list_entry; - head = dev_priv->head; - - if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) { - SET_AGE(&entry->age, MGA_BUFFER_FREE, 0); - prev = dev_priv->tail; - prev->next = entry; - entry->prev = prev; - entry->next = NULL; - } else { - prev = head->next; - head->next = entry; - prev->prev = entry; - entry->prev = head; - entry->next = prev; - } - - return 0; -} - -/* ================================================================ - * DMA initialization, cleanup - */ - -int mga_driver_load(struct drm_device *dev, unsigned long flags) -{ - drm_mga_private_t *dev_priv; - int ret; - - dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER); - if (!dev_priv) - return -ENOMEM; - - dev->dev_private = (void *)dev_priv; - memset(dev_priv, 0, sizeof(drm_mga_private_t)); - - dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT; - dev_priv->chipset = flags; - - dev_priv->mmio_base = drm_get_resource_start(dev, 1); - dev_priv->mmio_size = drm_get_resource_len(dev, 1); - - dev->counters += 3; - dev->types[6] = _DRM_STAT_IRQ; - dev->types[7] = _DRM_STAT_PRIMARY; - dev->types[8] = _DRM_STAT_SECONDARY; - - ret = drm_vblank_init(dev, 1); - - if (ret) { - (void) mga_driver_unload(dev); - return ret; - } - - return 0; -} - -/** - * Bootstrap the driver for AGP DMA. - * - * \todo - * Investigate whether there is any benifit to storing the WARP microcode in - * AGP memory. If not, the microcode may as well always be put in PCI - * memory. - * - * \todo - * This routine needs to set dma_bs->agp_mode to the mode actually configured - * in the hardware. Looking just at the Linux AGP driver code, I don't see - * an easy way to determine this. - * - * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap - */ -static int mga_do_agp_dma_bootstrap(struct drm_device *dev, - drm_mga_dma_bootstrap_t * dma_bs) -{ - drm_mga_private_t *const dev_priv = - (drm_mga_private_t *)dev->dev_private; - unsigned int warp_size = mga_warp_microcode_size(dev_priv); - int err; - unsigned offset; - const unsigned secondary_size = dma_bs->secondary_bin_count - * dma_bs->secondary_bin_size; - const unsigned agp_size = (dma_bs->agp_size << 20); - struct drm_buf_desc req; - struct drm_agp_mode mode; - struct drm_agp_info info; - struct drm_agp_buffer agp_req; - struct drm_agp_binding bind_req; - - /* Acquire AGP. */ - err = drm_agp_acquire(dev); - if (err) { - DRM_ERROR("Unable to acquire AGP: %d\n", err); - return err; - } - - err = drm_agp_info(dev, &info); - if (err) { - DRM_ERROR("Unable to get AGP info: %d\n", err); - return err; - } - - mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode; - err = drm_agp_enable(dev, mode); - if (err) { - DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode); - return err; - } - - /* In addition to the usual AGP mode configuration, the G200 AGP cards - * need to have the AGP mode "manually" set. - */ - - if (dev_priv->chipset == MGA_CARD_TYPE_G200) { - if (mode.mode & 0x02) { - MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE); - } else { - MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE); - } - } - - /* Allocate and bind AGP memory. */ - agp_req.size = agp_size; - agp_req.type = 0; - err = drm_agp_alloc(dev, &agp_req); - if (err) { - dev_priv->agp_size = 0; - DRM_ERROR("Unable to allocate %uMB AGP memory\n", - dma_bs->agp_size); - return err; - } - - dev_priv->agp_size = agp_size; - dev_priv->agp_handle = agp_req.handle; - - bind_req.handle = agp_req.handle; - bind_req.offset = 0; - err = drm_agp_bind( dev, &bind_req ); - if (err) { - DRM_ERROR("Unable to bind AGP memory: %d\n", err); - return err; - } - - /* Make drm_addbufs happy by not trying to create a mapping for less - * than a page. - */ - if (warp_size < PAGE_SIZE) - warp_size = PAGE_SIZE; - - offset = 0; - err = drm_addmap(dev, offset, warp_size, - _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp); - if (err) { - DRM_ERROR("Unable to map WARP microcode: %d\n", err); - return err; - } - - offset += warp_size; - err = drm_addmap(dev, offset, dma_bs->primary_size, - _DRM_AGP, _DRM_READ_ONLY, & dev_priv->primary); - if (err) { - DRM_ERROR("Unable to map primary DMA region: %d\n", err); - return err; - } - - offset += dma_bs->primary_size; - err = drm_addmap(dev, offset, secondary_size, - _DRM_AGP, 0, & dev->agp_buffer_map); - if (err) { - DRM_ERROR("Unable to map secondary DMA region: %d\n", err); - return err; - } - - (void)memset( &req, 0, sizeof(req) ); - req.count = dma_bs->secondary_bin_count; - req.size = dma_bs->secondary_bin_size; - req.flags = _DRM_AGP_BUFFER; - req.agp_start = offset; - - err = drm_addbufs_agp(dev, &req); - if (err) { - DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err); - return err; - } - -#ifdef __linux__ - { - struct drm_map_list *_entry; - unsigned long agp_token = 0; - - list_for_each_entry(_entry, &dev->maplist, head) { - if (_entry->map == dev->agp_buffer_map) - agp_token = _entry->user_token; - } - if (!agp_token) - return -EFAULT; - - dev->agp_buffer_token = agp_token; - } -#endif - - offset += secondary_size; - err = drm_addmap(dev, offset, agp_size - offset, - _DRM_AGP, 0, & dev_priv->agp_textures); - if (err) { - DRM_ERROR("Unable to map AGP texture region: %d\n", err); - return err; - } - - drm_core_ioremap(dev_priv->warp, dev); - drm_core_ioremap(dev_priv->primary, dev); - drm_core_ioremap(dev->agp_buffer_map, dev); - - if (!dev_priv->warp->handle || - !dev_priv->primary->handle || !dev->agp_buffer_map->handle) { - DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n", - dev_priv->warp->handle, dev_priv->primary->handle, - dev->agp_buffer_map->handle); - return -ENOMEM; - } - - dev_priv->dma_access = MGA_PAGPXFER; - dev_priv->wagp_enable = MGA_WAGP_ENABLE; - - DRM_INFO("Initialized card for AGP DMA.\n"); - return 0; -} - -/** - * Bootstrap the driver for PCI DMA. - * - * \todo - * The algorithm for decreasing the size of the primary DMA buffer could be - * better. The size should be rounded up to the nearest page size, then - * decrease the request size by a single page each pass through the loop. - * - * \todo - * Determine whether the maximum address passed to drm_pci_alloc is correct. - * The same goes for drm_addbufs_pci. - * - * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap - */ -static int mga_do_pci_dma_bootstrap(struct drm_device * dev, - drm_mga_dma_bootstrap_t * dma_bs) -{ - drm_mga_private_t *const dev_priv = - (drm_mga_private_t *) dev->dev_private; - unsigned int warp_size = mga_warp_microcode_size(dev_priv); - unsigned int primary_size; - unsigned int bin_count; - int err; - struct drm_buf_desc req; - - - if (dev->dma == NULL) { - DRM_ERROR("dev->dma is NULL\n"); - return -EFAULT; - } - - /* Make drm_addbufs happy by not trying to create a mapping for less - * than a page. - */ - if (warp_size < PAGE_SIZE) - warp_size = PAGE_SIZE; - - /* The proper alignment is 0x100 for this mapping */ - err = drm_addmap(dev, 0, warp_size, _DRM_CONSISTENT, - _DRM_READ_ONLY, &dev_priv->warp); - if (err != 0) { - DRM_ERROR("Unable to create mapping for WARP microcode: %d\n", - err); - return err; - } - - /* Other than the bottom two bits being used to encode other - * information, there don't appear to be any restrictions on the - * alignment of the primary or secondary DMA buffers. - */ - - for (primary_size = dma_bs->primary_size; primary_size != 0; - primary_size >>= 1 ) { - /* The proper alignment for this mapping is 0x04 */ - err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT, - _DRM_READ_ONLY, &dev_priv->primary); - if (!err) - break; - } - - if (err != 0) { - DRM_ERROR("Unable to allocate primary DMA region: %d\n", err); - return -ENOMEM; - } - - if (dev_priv->primary->size != dma_bs->primary_size) { - DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n", - dma_bs->primary_size, - (unsigned)dev_priv->primary->size); - dma_bs->primary_size = dev_priv->primary->size; - } - - for (bin_count = dma_bs->secondary_bin_count; bin_count > 0; - bin_count-- ) { - (void)memset(&req, 0, sizeof(req)); - req.count = bin_count; - req.size = dma_bs->secondary_bin_size; - - err = drm_addbufs_pci(dev, &req); - if (!err) { - break; - } - } - - if (bin_count == 0) { - DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err); - return err; - } - - if (bin_count != dma_bs->secondary_bin_count) { - DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u " - "to %u.\n", dma_bs->secondary_bin_count, bin_count); - - dma_bs->secondary_bin_count = bin_count; - } - - dev_priv->dma_access = 0; - dev_priv->wagp_enable = 0; - - dma_bs->agp_mode = 0; - - DRM_INFO("Initialized card for PCI DMA.\n"); - return 0; -} - - -static int mga_do_dma_bootstrap(struct drm_device *dev, - drm_mga_dma_bootstrap_t *dma_bs) -{ - const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev); - int err; - drm_mga_private_t *const dev_priv = - (drm_mga_private_t *) dev->dev_private; - - - dev_priv->used_new_dma_init = 1; - - /* The first steps are the same for both PCI and AGP based DMA. Map - * the cards MMIO registers and map a status page. - */ - err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size, - _DRM_REGISTERS, _DRM_READ_ONLY, & dev_priv->mmio); - if (err) { - DRM_ERROR("Unable to map MMIO region: %d\n", err); - return err; - } - - - err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM, - _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL, - & dev_priv->status); - if (err) { - DRM_ERROR("Unable to map status region: %d\n", err); - return err; - } - - - /* The DMA initialization procedure is slightly different for PCI and - * AGP cards. AGP cards just allocate a large block of AGP memory and - * carve off portions of it for internal uses. The remaining memory - * is returned to user-mode to be used for AGP textures. - */ - - if (is_agp) { - err = mga_do_agp_dma_bootstrap(dev, dma_bs); - } - - /* If we attempted to initialize the card for AGP DMA but failed, - * clean-up any mess that may have been created. - */ - - if (err) { - mga_do_cleanup_dma(dev, MINIMAL_CLEANUP); - } - - - /* Not only do we want to try and initialized PCI cards for PCI DMA, - * but we also try to initialized AGP cards that could not be - * initialized for AGP DMA. This covers the case where we have an AGP - * card in a system with an unsupported AGP chipset. In that case the - * card will be detected as AGP, but we won't be able to allocate any - * AGP memory, etc. - */ - - if (!is_agp || err) { - err = mga_do_pci_dma_bootstrap(dev, dma_bs); - } - - - return err; -} - -int mga_dma_bootstrap(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_mga_dma_bootstrap_t *bootstrap = data; - int err; - static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 }; - const drm_mga_private_t *const dev_priv = - (drm_mga_private_t *) dev->dev_private; - - - err = mga_do_dma_bootstrap(dev, bootstrap); - if (err) { - mga_do_cleanup_dma(dev, FULL_CLEANUP); - return err; - } - - if (dev_priv->agp_textures != NULL) { - bootstrap->texture_handle = dev_priv->agp_textures->offset; - bootstrap->texture_size = dev_priv->agp_textures->size; - } else { - bootstrap->texture_handle = 0; - bootstrap->texture_size = 0; - } - - bootstrap->agp_mode = modes[bootstrap->agp_mode & 0x07]; - - return 0; -} - - -static int mga_do_init_dma(struct drm_device * dev, drm_mga_init_t * init) -{ - drm_mga_private_t *dev_priv; - int ret; - DRM_DEBUG("\n"); - - - dev_priv = dev->dev_private; - - if (init->sgram) { - dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK; - } else { - dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR; - } - dev_priv->maccess = init->maccess; - - dev_priv->fb_cpp = init->fb_cpp; - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; - - dev_priv->depth_cpp = init->depth_cpp; - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; - - /* FIXME: Need to support AGP textures... - */ - dev_priv->texture_offset = init->texture_offset[0]; - dev_priv->texture_size = init->texture_size[0]; - - dev_priv->sarea = drm_getsarea(dev); - if (!dev_priv->sarea) { - DRM_ERROR("failed to find sarea!\n"); - return -EINVAL; - } - - if (!dev_priv->used_new_dma_init) { - - dev_priv->dma_access = MGA_PAGPXFER; - dev_priv->wagp_enable = MGA_WAGP_ENABLE; - - dev_priv->status = drm_core_findmap(dev, init->status_offset); - if (!dev_priv->status) { - DRM_ERROR("failed to find status page!\n"); - return -EINVAL; - } - dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); - if (!dev_priv->mmio) { - DRM_ERROR("failed to find mmio region!\n"); - return -EINVAL; - } - dev_priv->warp = drm_core_findmap(dev, init->warp_offset); - if (!dev_priv->warp) { - DRM_ERROR("failed to find warp microcode region!\n"); - return -EINVAL; - } - dev_priv->primary = drm_core_findmap(dev, init->primary_offset); - if (!dev_priv->primary) { - DRM_ERROR("failed to find primary dma region!\n"); - return -EINVAL; - } - dev->agp_buffer_token = init->buffers_offset; - dev->agp_buffer_map = - drm_core_findmap(dev, init->buffers_offset); - if (!dev->agp_buffer_map) { - DRM_ERROR("failed to find dma buffer region!\n"); - return -EINVAL; - } - - drm_core_ioremap(dev_priv->warp, dev); - drm_core_ioremap(dev_priv->primary, dev); - drm_core_ioremap(dev->agp_buffer_map, dev); - } - - dev_priv->sarea_priv = - (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle + - init->sarea_priv_offset); - - if (!dev_priv->warp->handle || - !dev_priv->primary->handle || - ((dev_priv->dma_access != 0) && - ((dev->agp_buffer_map == NULL) || - (dev->agp_buffer_map->handle == NULL)))) { - DRM_ERROR("failed to ioremap agp regions!\n"); - return -ENOMEM; - } - - ret = mga_warp_install_microcode(dev_priv); - if (ret != 0) { - DRM_ERROR("failed to install WARP ucode: %d!\n", ret); - return ret; - } - - ret = mga_warp_init(dev_priv); - if (ret != 0) { - DRM_ERROR("failed to init WARP engine: %d!\n", ret); - return ret; - } - - dev_priv->prim.status = (u32 *) dev_priv->status->handle; - - mga_do_wait_for_idle(dev_priv); - - /* Init the primary DMA registers. - */ - MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL); - - dev_priv->prim.start = (u8 *) dev_priv->primary->handle; - dev_priv->prim.end = ((u8 *) dev_priv->primary->handle - + dev_priv->primary->size); - dev_priv->prim.size = dev_priv->primary->size; - - dev_priv->prim.tail = 0; - dev_priv->prim.space = dev_priv->prim.size; - dev_priv->prim.wrapped = 0; - - dev_priv->prim.last_flush = 0; - dev_priv->prim.last_wrap = 0; - - dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE; - - dev_priv->prim.status[0] = dev_priv->primary->offset; - dev_priv->prim.status[1] = 0; - - dev_priv->sarea_priv->last_wrap = 0; - dev_priv->sarea_priv->last_frame.head = 0; - dev_priv->sarea_priv->last_frame.wrap = 0; - - if (mga_freelist_init(dev, dev_priv) < 0) { - DRM_ERROR("could not initialize freelist\n"); - return -ENOMEM; - } - - return 0; -} - -static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup) -{ - int err = 0; - DRM_DEBUG("\n"); - - /* Make sure interrupts are disabled here because the uninstall ioctl - * may not have been called from userspace and after dev_private - * is freed, it's too late. - */ - if (dev->irq_enabled) - drm_irq_uninstall(dev); - - if (dev->dev_private) { - drm_mga_private_t *dev_priv = dev->dev_private; - - if ((dev_priv->warp != NULL) - && (dev_priv->warp->type != _DRM_CONSISTENT)) - drm_core_ioremapfree(dev_priv->warp, dev); - - if ((dev_priv->primary != NULL) - && (dev_priv->primary->type != _DRM_CONSISTENT)) - drm_core_ioremapfree(dev_priv->primary, dev); - - if (dev->agp_buffer_map != NULL) - drm_core_ioremapfree(dev->agp_buffer_map, dev); - - if (dev_priv->used_new_dma_init) { - if (dev_priv->agp_handle != 0) { - struct drm_agp_binding unbind_req; - struct drm_agp_buffer free_req; - - unbind_req.handle = dev_priv->agp_handle; - drm_agp_unbind(dev, &unbind_req); - - free_req.handle = dev_priv->agp_handle; - drm_agp_free(dev, &free_req); - - dev_priv->agp_textures = NULL; - dev_priv->agp_size = 0; - dev_priv->agp_handle = 0; - } - - if ((dev->agp != NULL) && dev->agp->acquired) { - err = drm_agp_release(dev); - } - } - - dev_priv->warp = NULL; - dev_priv->primary = NULL; - dev_priv->sarea = NULL; - dev_priv->sarea_priv = NULL; - dev->agp_buffer_map = NULL; - - if (full_cleanup) { - dev_priv->mmio = NULL; - dev_priv->status = NULL; - dev_priv->used_new_dma_init = 0; - } - - memset(&dev_priv->prim, 0, sizeof(dev_priv->prim)); - dev_priv->warp_pipe = 0; - memset(dev_priv->warp_pipe_phys, 0, - sizeof(dev_priv->warp_pipe_phys)); - - if (dev_priv->head != NULL) { - mga_freelist_cleanup(dev); - } - } - - return err; -} - -int mga_dma_init(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_mga_init_t *init = data; - int err; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - switch (init->func) { - case MGA_INIT_DMA: - err = mga_do_init_dma(dev, init); - if (err) { - (void)mga_do_cleanup_dma(dev, FULL_CLEANUP); - } - return err; - case MGA_CLEANUP_DMA: - return mga_do_cleanup_dma(dev, FULL_CLEANUP); - } - - return -EINVAL; -} - -/* ================================================================ - * Primary DMA stream management - */ - -int mga_dma_flush(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - struct drm_lock *lock = data; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - DRM_DEBUG("%s%s%s\n", - (lock->flags & _DRM_LOCK_FLUSH) ? "flush, " : "", - (lock->flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", - (lock->flags & _DRM_LOCK_QUIESCENT) ? "idle, " : ""); - - WRAP_WAIT_WITH_RETURN(dev_priv); - - if (lock->flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) { - mga_do_dma_flush(dev_priv); - } - - if (lock->flags & _DRM_LOCK_QUIESCENT) { -#if MGA_DMA_DEBUG - int ret = mga_do_wait_for_idle(dev_priv); - if (ret < 0) - DRM_INFO("-EBUSY\n"); - return ret; -#else - return mga_do_wait_for_idle(dev_priv); -#endif - } else { - return 0; - } -} - -int mga_dma_reset(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - return mga_do_dma_reset(dev_priv); -} - -/* ================================================================ - * DMA buffer management - */ - -static int mga_dma_get_buffers(struct drm_device * dev, - struct drm_file *file_priv, struct drm_dma * d) -{ - struct drm_buf *buf; - int i; - - for (i = d->granted_count; i < d->request_count; i++) { - buf = mga_freelist_get(dev); - if (!buf) - return -EAGAIN; - - buf->file_priv = file_priv; - - if (DRM_COPY_TO_USER(&d->request_indices[i], - &buf->idx, sizeof(buf->idx))) - return -EFAULT; - if (DRM_COPY_TO_USER(&d->request_sizes[i], - &buf->total, sizeof(buf->total))) - return -EFAULT; - - d->granted_count++; - } - return 0; -} - -int mga_dma_buffers(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_device_dma *dma = dev->dma; - drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - struct drm_dma *d = data; - int ret = 0; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - /* Please don't send us buffers. - */ - if (d->send_count != 0) { - DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d->send_count); - return -EINVAL; - } - - /* We'll send you buffers. - */ - if (d->request_count < 0 || d->request_count > dma->buf_count) { - DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d->request_count, dma->buf_count); - return -EINVAL; - } - - WRAP_TEST_WITH_RETURN(dev_priv); - - d->granted_count = 0; - - if (d->request_count) { - ret = mga_dma_get_buffers(dev, file_priv, d); - } - - return ret; -} - -/** - * Called just before the module is unloaded. - */ -int mga_driver_unload(struct drm_device * dev) -{ - drm_free(dev->dev_private, sizeof(drm_mga_private_t), DRM_MEM_DRIVER); - dev->dev_private = NULL; - - return 0; -} - -/** - * Called when the last opener of the device is closed. - */ -void mga_driver_lastclose(struct drm_device * dev) -{ - mga_do_cleanup_dma(dev, FULL_CLEANUP); -} - -int mga_driver_dma_quiescent(struct drm_device * dev) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - return mga_do_wait_for_idle(dev_priv); -} diff --git a/shared-core/mga_drm.h b/shared-core/mga_drm.h deleted file mode 100644 index c03d3220..00000000 --- a/shared-core/mga_drm.h +++ /dev/null @@ -1,425 +0,0 @@ -/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*- - * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jeff Hartmann - * Keith Whitwell - * - * Rewritten by: - * Gareth Hughes - */ - -#ifndef __MGA_DRM_H__ -#define __MGA_DRM_H__ - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (mga_sarea.h) - */ - -#ifndef __MGA_SAREA_DEFINES__ -#define __MGA_SAREA_DEFINES__ - -/* WARP pipe flags - */ -#define MGA_F 0x1 /* fog */ -#define MGA_A 0x2 /* alpha */ -#define MGA_S 0x4 /* specular */ -#define MGA_T2 0x8 /* multitexture */ - -#define MGA_WARP_TGZ 0 -#define MGA_WARP_TGZF (MGA_F) -#define MGA_WARP_TGZA (MGA_A) -#define MGA_WARP_TGZAF (MGA_F|MGA_A) -#define MGA_WARP_TGZS (MGA_S) -#define MGA_WARP_TGZSF (MGA_S|MGA_F) -#define MGA_WARP_TGZSA (MGA_S|MGA_A) -#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A) -#define MGA_WARP_T2GZ (MGA_T2) -#define MGA_WARP_T2GZF (MGA_T2|MGA_F) -#define MGA_WARP_T2GZA (MGA_T2|MGA_A) -#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F) -#define MGA_WARP_T2GZS (MGA_T2|MGA_S) -#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F) -#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) -#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) - -#define MGA_MAX_G200_PIPES 8 /* no multitex */ -#define MGA_MAX_G400_PIPES 16 -#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES -#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ - -#define MGA_CARD_TYPE_G200 1 -#define MGA_CARD_TYPE_G400 2 -#define MGA_CARD_TYPE_G450 3 /* not currently used */ -#define MGA_CARD_TYPE_G550 4 - -#define MGA_FRONT 0x1 -#define MGA_BACK 0x2 -#define MGA_DEPTH 0x4 - -/* What needs to be changed for the current vertex dma buffer? - */ -#define MGA_UPLOAD_CONTEXT 0x1 -#define MGA_UPLOAD_TEX0 0x2 -#define MGA_UPLOAD_TEX1 0x4 -#define MGA_UPLOAD_PIPE 0x8 -#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ -#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ -#define MGA_UPLOAD_2D 0x40 -#define MGA_WAIT_AGE 0x80 /* handled client-side */ -#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ -#if 0 -#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock - quiescent */ -#endif - -/* 32 buffers of 64k each, total 2 meg. - */ -#define MGA_BUFFER_SIZE (1 << 16) -#define MGA_NUM_BUFFERS 128 - -/* Keep these small for testing. - */ -#define MGA_NR_SAREA_CLIPRECTS 8 - -/* 2 heaps (1 for card, 1 for agp), each divided into upto 128 - * regions, subject to a minimum region size of (1<<16) == 64k. - * - * Clients may subdivide regions internally, but when sharing between - * clients, the region size is the minimum granularity. - */ - -#define MGA_CARD_HEAP 0 -#define MGA_AGP_HEAP 1 -#define MGA_NR_TEX_HEAPS 2 -#define MGA_NR_TEX_REGIONS 16 -#define MGA_LOG_MIN_TEX_REGION_SIZE 16 - -#define DRM_MGA_IDLE_RETRY 2048 - -#endif /* __MGA_SAREA_DEFINES__ */ - -/* Setup registers for 3D context - */ -typedef struct { - unsigned int dstorg; - unsigned int maccess; - unsigned int plnwt; - unsigned int dwgctl; - unsigned int alphactrl; - unsigned int fogcolor; - unsigned int wflag; - unsigned int tdualstage0; - unsigned int tdualstage1; - unsigned int fcol; - unsigned int stencil; - unsigned int stencilctl; -} drm_mga_context_regs_t; - -/* Setup registers for 2D, X server - */ -typedef struct { - unsigned int pitch; -} drm_mga_server_regs_t; - -/* Setup registers for each texture unit - */ -typedef struct { - unsigned int texctl; - unsigned int texctl2; - unsigned int texfilter; - unsigned int texbordercol; - unsigned int texorg; - unsigned int texwidth; - unsigned int texheight; - unsigned int texorg1; - unsigned int texorg2; - unsigned int texorg3; - unsigned int texorg4; -} drm_mga_texture_regs_t; - -/* General aging mechanism - */ -typedef struct { - unsigned int head; /* Position of head pointer */ - unsigned int wrap; /* Primary DMA wrap count */ -} drm_mga_age_t; - -typedef struct _drm_mga_sarea { - /* The channel for communication of state information to the kernel - * on firing a vertex dma buffer. - */ - drm_mga_context_regs_t context_state; - drm_mga_server_regs_t server_state; - drm_mga_texture_regs_t tex_state[2]; - unsigned int warp_pipe; - unsigned int dirty; - unsigned int vertsize; - - /* The current cliprects, or a subset thereof. - */ - struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS]; - unsigned int nbox; - - /* Information about the most recently used 3d drawable. The - * client fills in the req_* fields, the server fills in the - * exported_ fields and puts the cliprects into boxes, above. - * - * The client clears the exported_drawable field before - * clobbering the boxes data. - */ - unsigned int req_drawable; /* the X drawable id */ - unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ - - unsigned int exported_drawable; - unsigned int exported_index; - unsigned int exported_stamp; - unsigned int exported_buffers; - unsigned int exported_nfront; - unsigned int exported_nback; - int exported_back_x, exported_front_x, exported_w; - int exported_back_y, exported_front_y, exported_h; - struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS]; - - /* Counters for aging textures and for client-side throttling. - */ - unsigned int status[4]; - unsigned int last_wrap; - - drm_mga_age_t last_frame; - unsigned int last_enqueue; /* last time a buffer was enqueued */ - unsigned int last_dispatch; /* age of the most recently dispatched buffer */ - unsigned int last_quiescent; /* */ - - /* LRU lists for texture memory in agp space and on the card. - */ - struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; - unsigned int texAge[MGA_NR_TEX_HEAPS]; - - /* Mechanism to validate card state. - */ - int ctxOwner; -} drm_mga_sarea_t; - - -/* MGA specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ -#define DRM_MGA_INIT 0x00 -#define DRM_MGA_FLUSH 0x01 -#define DRM_MGA_RESET 0x02 -#define DRM_MGA_SWAP 0x03 -#define DRM_MGA_CLEAR 0x04 -#define DRM_MGA_VERTEX 0x05 -#define DRM_MGA_INDICES 0x06 -#define DRM_MGA_ILOAD 0x07 -#define DRM_MGA_BLIT 0x08 -#define DRM_MGA_GETPARAM 0x09 - -/* 3.2: - * ioctls for operating on fences. - */ -#define DRM_MGA_SET_FENCE 0x0a -#define DRM_MGA_WAIT_FENCE 0x0b -#define DRM_MGA_DMA_BOOTSTRAP 0x0c - - -#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) -#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t) -#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) -#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP) -#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t) -#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t) -#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t) -#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) -#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) -#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) -#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t) -#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t) -#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) - -typedef struct _drm_mga_warp_index { - int installed; - unsigned long phys_addr; - int size; -} drm_mga_warp_index_t; - -typedef struct drm_mga_init { - enum { - MGA_INIT_DMA = 0x01, - MGA_CLEANUP_DMA = 0x02 - } func; - - unsigned long sarea_priv_offset; - - int chipset; - int sgram; - - unsigned int maccess; - - unsigned int fb_cpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - - unsigned int depth_cpp; - unsigned int depth_offset, depth_pitch; - - unsigned int texture_offset[MGA_NR_TEX_HEAPS]; - unsigned int texture_size[MGA_NR_TEX_HEAPS]; - - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long status_offset; - unsigned long warp_offset; - unsigned long primary_offset; - unsigned long buffers_offset; -} drm_mga_init_t; - - -typedef struct drm_mga_dma_bootstrap { - /** - * \name AGP texture region - * - * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will - * be filled in with the actual AGP texture settings. - * - * \warning - * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode - * is zero, it means that PCI memory (most likely through the use of - * an IOMMU) is being used for "AGP" textures. - */ - /*@{*/ - unsigned long texture_handle; /**< Handle used to map AGP textures. */ - uint32_t texture_size; /**< Size of the AGP texture region. */ - /*@}*/ - - - /** - * Requested size of the primary DMA region. - * - * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be - * filled in with the actual AGP mode. If AGP was not available - */ - uint32_t primary_size; - - - /** - * Requested number of secondary DMA buffers. - * - * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be - * filled in with the actual number of secondary DMA buffers - * allocated. Particularly when PCI DMA is used, this may be - * (subtantially) less than the number requested. - */ - uint32_t secondary_bin_count; - - - /** - * Requested size of each secondary DMA buffer. - * - * While the kernel \b is free to reduce - * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed - * to reduce dma_mga_dma_bootstrap::secondary_bin_size. - */ - uint32_t secondary_bin_size; - - - /** - * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X, - * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is - * zero, it means that PCI DMA should be used, even if AGP is - * possible. - * - * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be - * filled in with the actual AGP mode. If AGP was not available - * (i.e., PCI DMA was used), this value will be zero. - */ - uint32_t agp_mode; - - - /** - * Desired AGP GART size, measured in megabytes. - */ - uint8_t agp_size; -} drm_mga_dma_bootstrap_t; - -typedef struct drm_mga_clear { - unsigned int flags; - unsigned int clear_color; - unsigned int clear_depth; - unsigned int color_mask; - unsigned int depth_mask; -} drm_mga_clear_t; - -typedef struct drm_mga_vertex { - int idx; /* buffer to queue */ - int used; /* bytes in use */ - int discard; /* client finished with buffer? */ -} drm_mga_vertex_t; - -typedef struct drm_mga_indices { - int idx; /* buffer to queue */ - unsigned int start; - unsigned int end; - int discard; /* client finished with buffer? */ -} drm_mga_indices_t; - -typedef struct drm_mga_iload { - int idx; - unsigned int dstorg; - unsigned int length; -} drm_mga_iload_t; - -typedef struct _drm_mga_blit { - unsigned int planemask; - unsigned int srcorg; - unsigned int dstorg; - int src_pitch, dst_pitch; - int delta_sx, delta_sy; - int delta_dx, delta_dy; - int height, ydir; /* flip image vertically */ - int source_pitch, dest_pitch; -} drm_mga_blit_t; - -/* 3.1: An ioctl to get parameters that aren't available to the 3d - * client any other way. - */ -#define MGA_PARAM_IRQ_NR 1 - -/* 3.2: Query the actual card type. The DDX only distinguishes between - * G200 chips and non-G200 chips, which it calls G400. It turns out that - * there are some very sublte differences between the G4x0 chips and the G550 - * chips. Using this parameter query, a client-side driver can detect the - * difference between a G4x0 and a G550. - */ -#define MGA_PARAM_CARD_TYPE 2 - -typedef struct drm_mga_getparam { - int param; - void __user *value; -} drm_mga_getparam_t; - -#endif diff --git a/shared-core/mga_drv.h b/shared-core/mga_drv.h deleted file mode 100644 index bf3be808..00000000 --- a/shared-core/mga_drv.h +++ /dev/null @@ -1,691 +0,0 @@ -/* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*- - * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - */ - -#ifndef __MGA_DRV_H__ -#define __MGA_DRV_H__ - -/* General customization: - */ - -#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." - -#define DRIVER_NAME "mga" -#define DRIVER_DESC "Matrox G200/G400" -#define DRIVER_DATE "20060319" - -#define DRIVER_MAJOR 3 -#define DRIVER_MINOR 2 -#define DRIVER_PATCHLEVEL 2 - -typedef struct drm_mga_primary_buffer { - u8 *start; - u8 *end; - int size; - - u32 tail; - int space; - volatile long wrapped; - - volatile u32 *status; - - u32 last_flush; - u32 last_wrap; - - u32 high_mark; -} drm_mga_primary_buffer_t; - -typedef struct drm_mga_freelist { - struct drm_mga_freelist *next; - struct drm_mga_freelist *prev; - drm_mga_age_t age; - struct drm_buf *buf; -} drm_mga_freelist_t; - -typedef struct { - drm_mga_freelist_t *list_entry; - int discard; - int dispatched; -} drm_mga_buf_priv_t; - -typedef struct drm_mga_private { - drm_mga_primary_buffer_t prim; - drm_mga_sarea_t *sarea_priv; - - drm_mga_freelist_t *head; - drm_mga_freelist_t *tail; - - unsigned int warp_pipe; - unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES]; - - int chipset; - int usec_timeout; - - /** - * If set, the new DMA initialization sequence was used. This is - * primarilly used to select how the driver should uninitialized its - * internal DMA structures. - */ - int used_new_dma_init; - - /** - * If AGP memory is used for DMA buffers, this will be the value - * \c MGA_PAGPXFER. Otherwise, it will be zero (for a PCI transfer). - */ - u32 dma_access; - - /** - * If AGP memory is used for DMA buffers, this will be the value - * \c MGA_WAGP_ENABLE. Otherwise, it will be zero (for a PCI - * transfer). - */ - u32 wagp_enable; - - /** - * \name MMIO region parameters. - * - * \sa drm_mga_private_t::mmio - */ - /*@{*/ - u32 mmio_base; /**< Bus address of base of MMIO. */ - u32 mmio_size; /**< Size of the MMIO region. */ - /*@}*/ - - u32 clear_cmd; - u32 maccess; - - atomic_t vbl_received; /**< Number of vblanks received. */ - wait_queue_head_t fence_queue; - atomic_t last_fence_retired; - u32 next_fence_to_post; - - unsigned int fb_cpp; - unsigned int front_offset; - unsigned int front_pitch; - unsigned int back_offset; - unsigned int back_pitch; - - unsigned int depth_cpp; - unsigned int depth_offset; - unsigned int depth_pitch; - - unsigned int texture_offset; - unsigned int texture_size; - - drm_local_map_t *sarea; - drm_local_map_t *mmio; - drm_local_map_t *status; - drm_local_map_t *warp; - drm_local_map_t *primary; - drm_local_map_t *agp_textures; - - unsigned long agp_handle; - unsigned int agp_size; -} drm_mga_private_t; - -extern struct drm_ioctl_desc mga_ioctls[]; -extern int mga_max_ioctl; - - /* mga_dma.c */ -extern int mga_dma_bootstrap(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int mga_dma_init(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int mga_dma_flush(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int mga_dma_reset(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int mga_dma_buffers(struct drm_device *dev, void *data, - struct drm_file *file_priv); -extern int mga_driver_load(struct drm_device *dev, unsigned long flags); -extern int mga_driver_unload(struct drm_device * dev); -extern void mga_driver_lastclose(struct drm_device * dev); -extern int mga_driver_dma_quiescent(struct drm_device * dev); - -extern int mga_do_wait_for_idle(drm_mga_private_t * dev_priv); - -extern void mga_do_dma_flush(drm_mga_private_t * dev_priv); -extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv); -extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv); - -extern int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf); - - /* mga_warp.c */ -extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv); -extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv); -extern int mga_warp_init(drm_mga_private_t * dev_priv); - - /* mga_irq.c */ -extern int mga_enable_vblank(struct drm_device *dev, int crtc); -extern void mga_disable_vblank(struct drm_device *dev, int crtc); -extern u32 mga_get_vblank_counter(struct drm_device *dev, int crtc); -extern int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence); -extern int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence); -extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS); -extern void mga_driver_irq_preinstall(struct drm_device * dev); -extern int mga_driver_irq_postinstall(struct drm_device * dev); -extern void mga_driver_irq_uninstall(struct drm_device * dev); -extern long mga_compat_ioctl(struct file *filp, unsigned int cmd, - unsigned long arg); - -#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() - -#if defined(__linux__) && defined(__alpha__) -#define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) -#define MGA_ADDR( reg ) (MGA_BASE(reg) + reg) - -#define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg ) -#define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg ) - -#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) -#define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg))) -#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) -#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) - -static inline u32 _MGA_READ(u32 * addr) -{ - DRM_MEMORYBARRIER(); - return *(volatile u32 *)addr; -} -#else -#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg)) -#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg)) -#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val)) -#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val)) -#endif - -#define DWGREG0 0x1c00 -#define DWGREG0_END 0x1dff -#define DWGREG1 0x2c00 -#define DWGREG1_END 0x2dff - -#define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END) -#define DMAREG0(r) (u8)((r - DWGREG0) >> 2) -#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) -#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) - -/* ================================================================ - * Helper macross... - */ - -#define MGA_EMIT_STATE( dev_priv, dirty ) \ -do { \ - if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \ - if ( dev_priv->chipset >= MGA_CARD_TYPE_G400 ) { \ - mga_g400_emit_state( dev_priv ); \ - } else { \ - mga_g200_emit_state( dev_priv ); \ - } \ - } \ -} while (0) - -#define WRAP_TEST_WITH_RETURN( dev_priv ) \ -do { \ - if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ - if ( mga_is_idle( dev_priv ) ) { \ - mga_do_dma_wrap_end( dev_priv ); \ - } else if ( dev_priv->prim.space < \ - dev_priv->prim.high_mark ) { \ - if ( MGA_DMA_DEBUG ) \ - DRM_INFO( "wrap...\n"); \ - return -EBUSY; \ - } \ - } \ -} while (0) - -#define WRAP_WAIT_WITH_RETURN( dev_priv ) \ -do { \ - if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ - if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \ - if ( MGA_DMA_DEBUG ) \ - DRM_INFO( "wrap...\n"); \ - return -EBUSY; \ - } \ - mga_do_dma_wrap_end( dev_priv ); \ - } \ -} while (0) - -/* ================================================================ - * Primary DMA command stream - */ - -#define MGA_VERBOSE 0 - -#define DMA_LOCALS unsigned int write; volatile u8 *prim; - -#define DMA_BLOCK_SIZE (5 * sizeof(u32)) - -#define BEGIN_DMA( n ) \ -do { \ - if ( MGA_VERBOSE ) { \ - DRM_INFO( "BEGIN_DMA( %d )\n", (n) ); \ - DRM_INFO( " space=0x%x req=0x%Zx\n", \ - dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \ - } \ - prim = dev_priv->prim.start; \ - write = dev_priv->prim.tail; \ -} while (0) - -#define BEGIN_DMA_WRAP() \ -do { \ - if ( MGA_VERBOSE ) { \ - DRM_INFO( "BEGIN_DMA()\n" ); \ - DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \ - } \ - prim = dev_priv->prim.start; \ - write = dev_priv->prim.tail; \ -} while (0) - -#define ADVANCE_DMA() \ -do { \ - dev_priv->prim.tail = write; \ - if ( MGA_VERBOSE ) { \ - DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \ - write, dev_priv->prim.space ); \ - } \ -} while (0) - -#define FLUSH_DMA() \ -do { \ - if ( 0 ) { \ - DRM_INFO( "\n" ); \ - DRM_INFO( " tail=0x%06x head=0x%06lx\n", \ - dev_priv->prim.tail, \ - MGA_READ( MGA_PRIMADDRESS ) - \ - dev_priv->primary->offset ); \ - } \ - if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \ - if ( dev_priv->prim.space < \ - dev_priv->prim.high_mark ) { \ - mga_do_dma_wrap_start( dev_priv ); \ - } else { \ - mga_do_dma_flush( dev_priv ); \ - } \ - } \ -} while (0) - -/* Never use this, always use DMA_BLOCK(...) for primary DMA output. - */ -#define DMA_WRITE( offset, val ) \ -do { \ - if ( MGA_VERBOSE ) { \ - DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \ - (u32)(val), write + (offset) * sizeof(u32) ); \ - } \ - *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \ -} while (0) - -#define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \ -do { \ - DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \ - (DMAREG( reg1 ) << 8) | \ - (DMAREG( reg2 ) << 16) | \ - (DMAREG( reg3 ) << 24)) ); \ - DMA_WRITE( 1, val0 ); \ - DMA_WRITE( 2, val1 ); \ - DMA_WRITE( 3, val2 ); \ - DMA_WRITE( 4, val3 ); \ - write += DMA_BLOCK_SIZE; \ -} while (0) - -/* Buffer aging via primary DMA stream head pointer. - */ - -#define SET_AGE( age, h, w ) \ -do { \ - (age)->head = h; \ - (age)->wrap = w; \ -} while (0) - -#define TEST_AGE( age, h, w ) ( (age)->wrap < w || \ - ( (age)->wrap == w && \ - (age)->head < h ) ) - -#define AGE_BUFFER( buf_priv ) \ -do { \ - drm_mga_freelist_t *entry = (buf_priv)->list_entry; \ - if ( (buf_priv)->dispatched ) { \ - entry->age.head = (dev_priv->prim.tail + \ - dev_priv->primary->offset); \ - entry->age.wrap = dev_priv->sarea_priv->last_wrap; \ - } else { \ - entry->age.head = 0; \ - entry->age.wrap = 0; \ - } \ -} while (0) - -#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ - MGA_DWGENGSTS | \ - MGA_ENDPRDMASTS) -#define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \ - MGA_ENDPRDMASTS) - -#define MGA_DMA_DEBUG 0 - -/* A reduced set of the mga registers. - */ -#define MGA_CRTC_INDEX 0x1fd4 -#define MGA_CRTC_DATA 0x1fd5 - -/* CRTC11 */ -#define MGA_VINTCLR (1 << 4) -#define MGA_VINTEN (1 << 5) - -#define MGA_ALPHACTRL 0x2c7c -#define MGA_AR0 0x1c60 -#define MGA_AR1 0x1c64 -#define MGA_AR2 0x1c68 -#define MGA_AR3 0x1c6c -#define MGA_AR4 0x1c70 -#define MGA_AR5 0x1c74 -#define MGA_AR6 0x1c78 - -#define MGA_CXBNDRY 0x1c80 -#define MGA_CXLEFT 0x1ca0 -#define MGA_CXRIGHT 0x1ca4 - -#define MGA_DMAPAD 0x1c54 -#define MGA_DSTORG 0x2cb8 -#define MGA_DWGCTL 0x1c00 -# define MGA_OPCOD_MASK (15 << 0) -# define MGA_OPCOD_TRAP (4 << 0) -# define MGA_OPCOD_TEXTURE_TRAP (6 << 0) -# define MGA_OPCOD_BITBLT (8 << 0) -# define MGA_OPCOD_ILOAD (9 << 0) -# define MGA_ATYPE_MASK (7 << 4) -# define MGA_ATYPE_RPL (0 << 4) -# define MGA_ATYPE_RSTR (1 << 4) -# define MGA_ATYPE_ZI (3 << 4) -# define MGA_ATYPE_BLK (4 << 4) -# define MGA_ATYPE_I (7 << 4) -# define MGA_LINEAR (1 << 7) -# define MGA_ZMODE_MASK (7 << 8) -# define MGA_ZMODE_NOZCMP (0 << 8) -# define MGA_ZMODE_ZE (2 << 8) -# define MGA_ZMODE_ZNE (3 << 8) -# define MGA_ZMODE_ZLT (4 << 8) -# define MGA_ZMODE_ZLTE (5 << 8) -# define MGA_ZMODE_ZGT (6 << 8) -# define MGA_ZMODE_ZGTE (7 << 8) -# define MGA_SOLID (1 << 11) -# define MGA_ARZERO (1 << 12) -# define MGA_SGNZERO (1 << 13) -# define MGA_SHIFTZERO (1 << 14) -# define MGA_BOP_MASK (15 << 16) -# define MGA_BOP_ZERO (0 << 16) -# define MGA_BOP_DST (10 << 16) -# define MGA_BOP_SRC (12 << 16) -# define MGA_BOP_ONE (15 << 16) -# define MGA_TRANS_SHIFT 20 -# define MGA_TRANS_MASK (15 << 20) -# define MGA_BLTMOD_MASK (15 << 25) -# define MGA_BLTMOD_BMONOLEF (0 << 25) -# define MGA_BLTMOD_BMONOWF (4 << 25) -# define MGA_BLTMOD_PLAN (1 << 25) -# define MGA_BLTMOD_BFCOL (2 << 25) -# define MGA_BLTMOD_BU32BGR (3 << 25) -# define MGA_BLTMOD_BU32RGB (7 << 25) -# define MGA_BLTMOD_BU24BGR (11 << 25) -# define MGA_BLTMOD_BU24RGB (15 << 25) -# define MGA_PATTERN (1 << 29) -# define MGA_TRANSC (1 << 30) -# define MGA_CLIPDIS (1 << 31) -#define MGA_DWGSYNC 0x2c4c - -#define MGA_FCOL 0x1c24 -#define MGA_FIFOSTATUS 0x1e10 -#define MGA_FOGCOL 0x1cf4 -#define MGA_FXBNDRY 0x1c84 -#define MGA_FXLEFT 0x1ca8 -#define MGA_FXRIGHT 0x1cac - -#define MGA_ICLEAR 0x1e18 -# define MGA_SOFTRAPICLR (1 << 0) -# define MGA_VLINEICLR (1 << 5) -#define MGA_IEN 0x1e1c -# define MGA_SOFTRAPIEN (1 << 0) -# define MGA_VLINEIEN (1 << 5) - -#define MGA_LEN 0x1c5c - -#define MGA_MACCESS 0x1c04 - -#define MGA_PITCH 0x1c8c -#define MGA_PLNWT 0x1c1c -#define MGA_PRIMADDRESS 0x1e58 -# define MGA_DMA_GENERAL (0 << 0) -# define MGA_DMA_BLIT (1 << 0) -# define MGA_DMA_VECTOR (2 << 0) -# define MGA_DMA_VERTEX (3 << 0) -#define MGA_PRIMEND 0x1e5c -# define MGA_PRIMNOSTART (1 << 0) -# define MGA_PAGPXFER (1 << 1) -#define MGA_PRIMPTR 0x1e50 -# define MGA_PRIMPTREN0 (1 << 0) -# define MGA_PRIMPTREN1 (1 << 1) - -#define MGA_RST 0x1e40 -# define MGA_SOFTRESET (1 << 0) -# define MGA_SOFTEXTRST (1 << 1) - -#define MGA_SECADDRESS 0x2c40 -#define MGA_SECEND 0x2c44 -#define MGA_SETUPADDRESS 0x2cd0 -#define MGA_SETUPEND 0x2cd4 -#define MGA_SGN 0x1c58 -#define MGA_SOFTRAP 0x2c48 -#define MGA_SRCORG 0x2cb4 -# define MGA_SRMMAP_MASK (1 << 0) -# define MGA_SRCMAP_FB (0 << 0) -# define MGA_SRCMAP_SYSMEM (1 << 0) -# define MGA_SRCACC_MASK (1 << 1) -# define MGA_SRCACC_PCI (0 << 1) -# define MGA_SRCACC_AGP (1 << 1) -#define MGA_STATUS 0x1e14 -# define MGA_SOFTRAPEN (1 << 0) -# define MGA_VSYNCPEN (1 << 4) -# define MGA_VLINEPEN (1 << 5) -# define MGA_DWGENGSTS (1 << 16) -# define MGA_ENDPRDMASTS (1 << 17) -#define MGA_STENCIL 0x2cc8 -#define MGA_STENCILCTL 0x2ccc - -#define MGA_TDUALSTAGE0 0x2cf8 -#define MGA_TDUALSTAGE1 0x2cfc -#define MGA_TEXBORDERCOL 0x2c5c -#define MGA_TEXCTL 0x2c30 -#define MGA_TEXCTL2 0x2c3c -# define MGA_DUALTEX (1 << 7) -# define MGA_G400_TC2_MAGIC (1 << 15) -# define MGA_MAP1_ENABLE (1 << 31) -#define MGA_TEXFILTER 0x2c58 -#define MGA_TEXHEIGHT 0x2c2c -#define MGA_TEXORG 0x2c24 -# define MGA_TEXORGMAP_MASK (1 << 0) -# define MGA_TEXORGMAP_FB (0 << 0) -# define MGA_TEXORGMAP_SYSMEM (1 << 0) -# define MGA_TEXORGACC_MASK (1 << 1) -# define MGA_TEXORGACC_PCI (0 << 1) -# define MGA_TEXORGACC_AGP (1 << 1) -#define MGA_TEXORG1 0x2ca4 -#define MGA_TEXORG2 0x2ca8 -#define MGA_TEXORG3 0x2cac -#define MGA_TEXORG4 0x2cb0 -#define MGA_TEXTRANS 0x2c34 -#define MGA_TEXTRANSHIGH 0x2c38 -#define MGA_TEXWIDTH 0x2c28 - -#define MGA_WACCEPTSEQ 0x1dd4 -#define MGA_WCODEADDR 0x1e6c -#define MGA_WFLAG 0x1dc4 -#define MGA_WFLAG1 0x1de0 -#define MGA_WFLAGNB 0x1e64 -#define MGA_WFLAGNB1 0x1e08 -#define MGA_WGETMSB 0x1dc8 -#define MGA_WIADDR 0x1dc0 -#define MGA_WIADDR2 0x1dd8 -# define MGA_WMODE_SUSPEND (0 << 0) -# define MGA_WMODE_RESUME (1 << 0) -# define MGA_WMODE_JUMP (2 << 0) -# define MGA_WMODE_START (3 << 0) -# define MGA_WAGP_ENABLE (1 << 2) -#define MGA_WMISC 0x1e70 -# define MGA_WUCODECACHE_ENABLE (1 << 0) -# define MGA_WMASTER_ENABLE (1 << 1) -# define MGA_WCACHEFLUSH_ENABLE (1 << 3) -#define MGA_WVRTXSZ 0x1dcc - -#define MGA_YBOT 0x1c9c -#define MGA_YDST 0x1c90 -#define MGA_YDSTLEN 0x1c88 -#define MGA_YDSTORG 0x1c94 -#define MGA_YTOP 0x1c98 - -#define MGA_ZORG 0x1c0c - -/* This finishes the current batch of commands - */ -#define MGA_EXEC 0x0100 - -/* AGP PLL encoding (for G200 only). - */ -#define MGA_AGP_PLL 0x1e4c -# define MGA_AGP2XPLL_DISABLE (0 << 0) -# define MGA_AGP2XPLL_ENABLE (1 << 0) - -/* Warp registers - */ -#define MGA_WR0 0x2d00 -#define MGA_WR1 0x2d04 -#define MGA_WR2 0x2d08 -#define MGA_WR3 0x2d0c -#define MGA_WR4 0x2d10 -#define MGA_WR5 0x2d14 -#define MGA_WR6 0x2d18 -#define MGA_WR7 0x2d1c -#define MGA_WR8 0x2d20 -#define MGA_WR9 0x2d24 -#define MGA_WR10 0x2d28 -#define MGA_WR11 0x2d2c -#define MGA_WR12 0x2d30 -#define MGA_WR13 0x2d34 -#define MGA_WR14 0x2d38 -#define MGA_WR15 0x2d3c -#define MGA_WR16 0x2d40 -#define MGA_WR17 0x2d44 -#define MGA_WR18 0x2d48 -#define MGA_WR19 0x2d4c -#define MGA_WR20 0x2d50 -#define MGA_WR21 0x2d54 -#define MGA_WR22 0x2d58 -#define MGA_WR23 0x2d5c -#define MGA_WR24 0x2d60 -#define MGA_WR25 0x2d64 -#define MGA_WR26 0x2d68 -#define MGA_WR27 0x2d6c -#define MGA_WR28 0x2d70 -#define MGA_WR29 0x2d74 -#define MGA_WR30 0x2d78 -#define MGA_WR31 0x2d7c -#define MGA_WR32 0x2d80 -#define MGA_WR33 0x2d84 -#define MGA_WR34 0x2d88 -#define MGA_WR35 0x2d8c -#define MGA_WR36 0x2d90 -#define MGA_WR37 0x2d94 -#define MGA_WR38 0x2d98 -#define MGA_WR39 0x2d9c -#define MGA_WR40 0x2da0 -#define MGA_WR41 0x2da4 -#define MGA_WR42 0x2da8 -#define MGA_WR43 0x2dac -#define MGA_WR44 0x2db0 -#define MGA_WR45 0x2db4 -#define MGA_WR46 0x2db8 -#define MGA_WR47 0x2dbc -#define MGA_WR48 0x2dc0 -#define MGA_WR49 0x2dc4 -#define MGA_WR50 0x2dc8 -#define MGA_WR51 0x2dcc -#define MGA_WR52 0x2dd0 -#define MGA_WR53 0x2dd4 -#define MGA_WR54 0x2dd8 -#define MGA_WR55 0x2ddc -#define MGA_WR56 0x2de0 -#define MGA_WR57 0x2de4 -#define MGA_WR58 0x2de8 -#define MGA_WR59 0x2dec -#define MGA_WR60 0x2df0 -#define MGA_WR61 0x2df4 -#define MGA_WR62 0x2df8 -#define MGA_WR63 0x2dfc -# define MGA_G400_WR_MAGIC (1 << 6) -# define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */ - -#define MGA_ILOAD_ALIGN 64 -#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1) - -#define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \ - MGA_ATYPE_I | \ - MGA_ZMODE_NOZCMP | \ - MGA_ARZERO | \ - MGA_SGNZERO | \ - MGA_BOP_SRC | \ - (15 << MGA_TRANS_SHIFT)) - -#define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \ - MGA_ZMODE_NOZCMP | \ - MGA_SOLID | \ - MGA_ARZERO | \ - MGA_SGNZERO | \ - MGA_SHIFTZERO | \ - MGA_BOP_SRC | \ - (0 << MGA_TRANS_SHIFT) | \ - MGA_BLTMOD_BMONOLEF | \ - MGA_TRANSC | \ - MGA_CLIPDIS) - -#define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \ - MGA_ATYPE_RPL | \ - MGA_SGNZERO | \ - MGA_SHIFTZERO | \ - MGA_BOP_SRC | \ - (0 << MGA_TRANS_SHIFT) | \ - MGA_BLTMOD_BFCOL | \ - MGA_CLIPDIS) - -/* Simple idle test. - */ -static __inline__ int mga_is_idle(drm_mga_private_t * dev_priv) -{ - u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; - return (status == MGA_ENDPRDMASTS); -} - -#endif diff --git a/shared-core/mga_irq.c b/shared-core/mga_irq.c deleted file mode 100644 index 6986ac85..00000000 --- a/shared-core/mga_irq.c +++ /dev/null @@ -1,177 +0,0 @@ -/* mga_irq.c -- IRQ handling for radeon -*- linux-c -*- - */ -/* - * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * - * The Weather Channel (TM) funded Tungsten Graphics to develop the - * initial release of the Radeon 8500 driver under the XFree86 license. - * This notice must be preserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Keith Whitwell - * Eric Anholt - */ - -#include "drmP.h" -#include "drm.h" -#include "mga_drm.h" -#include "mga_drv.h" - -u32 mga_get_vblank_counter(struct drm_device *dev, int crtc) -{ - const drm_mga_private_t *const dev_priv = - (drm_mga_private_t *) dev->dev_private; - - if (crtc != 0) { - return 0; - } - - - return atomic_read(&dev_priv->vbl_received); -} - - -irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS) -{ - struct drm_device *dev = (struct drm_device *) arg; - drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - int status; - int handled = 0; - - status = MGA_READ(MGA_STATUS); - - /* VBLANK interrupt */ - if (status & MGA_VLINEPEN) { - MGA_WRITE(MGA_ICLEAR, MGA_VLINEICLR); - atomic_inc(&dev_priv->vbl_received); - drm_handle_vblank(dev, 0); - handled = 1; - } - - /* SOFTRAP interrupt */ - if (status & MGA_SOFTRAPEN) { - const u32 prim_start = MGA_READ(MGA_PRIMADDRESS); - const u32 prim_end = MGA_READ(MGA_PRIMEND); - - - MGA_WRITE(MGA_ICLEAR, MGA_SOFTRAPICLR); - - /* In addition to clearing the interrupt-pending bit, we - * have to write to MGA_PRIMEND to re-start the DMA operation. - */ - if ((prim_start & ~0x03) != (prim_end & ~0x03)) { - MGA_WRITE(MGA_PRIMEND, prim_end); - } - - atomic_inc(&dev_priv->last_fence_retired); - DRM_WAKEUP(&dev_priv->fence_queue); - handled = 1; - } - - if (handled) - return IRQ_HANDLED; - return IRQ_NONE; -} - -int mga_enable_vblank(struct drm_device *dev, int crtc) -{ - drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - - if (crtc != 0) { - DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", - crtc); - return 0; - } - - MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN); - return 0; -} - - -void mga_disable_vblank(struct drm_device *dev, int crtc) -{ - if (crtc != 0) { - DRM_ERROR("tried to disable vblank on non-existent crtc %d\n", - crtc); - } - - /* Do *NOT* disable the vertical refresh interrupt. MGA doesn't have - * a nice hardware counter that tracks the number of refreshes when - * the interrupt is disabled, and the kernel doesn't know the refresh - * rate to calculate an estimate. - */ - /* MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN); */ -} - -int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence) -{ - drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - unsigned int cur_fence; - int ret = 0; - - /* Assume that the user has missed the current sequence number - * by about a day rather than she wants to wait for years - * using fences. - */ - DRM_WAIT_ON(ret, dev_priv->fence_queue, 3 * DRM_HZ, - (((cur_fence = atomic_read(&dev_priv->last_fence_retired)) - - *sequence) <= (1 << 23))); - - *sequence = cur_fence; - - return ret; -} - -void mga_driver_irq_preinstall(struct drm_device * dev) -{ - drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - - /* Disable *all* interrupts */ - MGA_WRITE(MGA_IEN, 0); - /* Clear bits if they're already high */ - MGA_WRITE(MGA_ICLEAR, ~0); -} - -int mga_driver_irq_postinstall(struct drm_device * dev) -{ - drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - - DRM_INIT_WAITQUEUE(&dev_priv->fence_queue); - - /* Turn on soft trap interrupt. Vertical blank interrupts are enabled - * in mga_enable_vblank. - */ - MGA_WRITE(MGA_IEN, MGA_SOFTRAPEN); - return 0; -} - -void mga_driver_irq_uninstall(struct drm_device * dev) -{ - drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - if (!dev_priv) - return; - - /* Disable *all* interrupts */ - MGA_WRITE(MGA_IEN, 0); - - dev->irq_enabled = 0; -} diff --git a/shared-core/mga_state.c b/shared-core/mga_state.c deleted file mode 100644 index 2da108be..00000000 --- a/shared-core/mga_state.c +++ /dev/null @@ -1,1139 +0,0 @@ -/* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*- - * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com - */ -/* - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jeff Hartmann - * Keith Whitwell - * - * Rewritten by: - * Gareth Hughes - */ - -#include "drmP.h" -#include "drm.h" -#include "mga_drm.h" -#include "mga_drv.h" - -/* ================================================================ - * DMA hardware state programming functions - */ - -static void mga_emit_clip_rect(drm_mga_private_t * dev_priv, - struct drm_clip_rect * box) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - unsigned int pitch = dev_priv->front_pitch; - DMA_LOCALS; - - BEGIN_DMA(2); - - /* Force reset of DWGCTL on G400 (eliminates clip disable bit). - */ - if (dev_priv->chipset >= MGA_CARD_TYPE_G400) { - DMA_BLOCK(MGA_DWGCTL, ctx->dwgctl, - MGA_LEN + MGA_EXEC, 0x80000000, - MGA_DWGCTL, ctx->dwgctl, - MGA_LEN + MGA_EXEC, 0x80000000); - } - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1, - MGA_YTOP, box->y1 * pitch, MGA_YBOT, (box->y2 - 1) * pitch); - - ADVANCE_DMA(); -} - -static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - DMA_LOCALS; - - BEGIN_DMA(3); - - DMA_BLOCK(MGA_DSTORG, ctx->dstorg, - MGA_MACCESS, ctx->maccess, - MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl); - - DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl, - MGA_FOGCOL, ctx->fogcolor, - MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset); - - DMA_BLOCK(MGA_FCOL, ctx->fcol, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); - - ADVANCE_DMA(); -} - -static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - DMA_LOCALS; - - BEGIN_DMA(4); - - DMA_BLOCK(MGA_DSTORG, ctx->dstorg, - MGA_MACCESS, ctx->maccess, - MGA_PLNWT, ctx->plnwt, - MGA_DWGCTL, ctx->dwgctl); - - DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl, - MGA_FOGCOL, ctx->fogcolor, - MGA_WFLAG, ctx->wflag, - MGA_ZORG, dev_priv->depth_offset); - - DMA_BLOCK(MGA_WFLAG1, ctx->wflag, - MGA_TDUALSTAGE0, ctx->tdualstage0, - MGA_TDUALSTAGE1, ctx->tdualstage1, - MGA_FCOL, ctx->fcol); - - DMA_BLOCK(MGA_STENCIL, ctx->stencil, - MGA_STENCILCTL, ctx->stencilctl, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000); - - ADVANCE_DMA(); -} - -static __inline__ void mga_g200_emit_tex0(drm_mga_private_t * dev_priv) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; - DMA_LOCALS; - - BEGIN_DMA(4); - - DMA_BLOCK(MGA_TEXCTL2, tex->texctl2, - MGA_TEXCTL, tex->texctl, - MGA_TEXFILTER, tex->texfilter, - MGA_TEXBORDERCOL, tex->texbordercol); - - DMA_BLOCK(MGA_TEXORG, tex->texorg, - MGA_TEXORG1, tex->texorg1, - MGA_TEXORG2, tex->texorg2, - MGA_TEXORG3, tex->texorg3); - - DMA_BLOCK(MGA_TEXORG4, tex->texorg4, - MGA_TEXWIDTH, tex->texwidth, - MGA_TEXHEIGHT, tex->texheight, - MGA_WR24, tex->texwidth); - - DMA_BLOCK(MGA_WR34, tex->texheight, - MGA_TEXTRANS, 0x0000ffff, - MGA_TEXTRANSHIGH, 0x0000ffff, - MGA_DMAPAD, 0x00000000); - - ADVANCE_DMA(); -} - -static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; - DMA_LOCALS; - -/* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */ -/* tex->texctl, tex->texctl2); */ - - BEGIN_DMA(6); - - DMA_BLOCK(MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC, - MGA_TEXCTL, tex->texctl, - MGA_TEXFILTER, tex->texfilter, - MGA_TEXBORDERCOL, tex->texbordercol); - - DMA_BLOCK(MGA_TEXORG, tex->texorg, - MGA_TEXORG1, tex->texorg1, - MGA_TEXORG2, tex->texorg2, - MGA_TEXORG3, tex->texorg3); - - DMA_BLOCK(MGA_TEXORG4, tex->texorg4, - MGA_TEXWIDTH, tex->texwidth, - MGA_TEXHEIGHT, tex->texheight, - MGA_WR49, 0x00000000); - - DMA_BLOCK(MGA_WR57, 0x00000000, - MGA_WR53, 0x00000000, - MGA_WR61, 0x00000000, - MGA_WR52, MGA_G400_WR_MAGIC); - - DMA_BLOCK(MGA_WR60, MGA_G400_WR_MAGIC, - MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC, - MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC, - MGA_DMAPAD, 0x00000000); - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_TEXTRANS, 0x0000ffff, - MGA_TEXTRANSHIGH, 0x0000ffff); - - ADVANCE_DMA(); -} - -static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1]; - DMA_LOCALS; - -/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */ -/* tex->texctl, tex->texctl2); */ - - BEGIN_DMA(5); - - DMA_BLOCK(MGA_TEXCTL2, (tex->texctl2 | - MGA_MAP1_ENABLE | - MGA_G400_TC2_MAGIC), - MGA_TEXCTL, tex->texctl, - MGA_TEXFILTER, tex->texfilter, - MGA_TEXBORDERCOL, tex->texbordercol); - - DMA_BLOCK(MGA_TEXORG, tex->texorg, - MGA_TEXORG1, tex->texorg1, - MGA_TEXORG2, tex->texorg2, - MGA_TEXORG3, tex->texorg3); - - DMA_BLOCK(MGA_TEXORG4, tex->texorg4, - MGA_TEXWIDTH, tex->texwidth, - MGA_TEXHEIGHT, tex->texheight, - MGA_WR49, 0x00000000); - - DMA_BLOCK(MGA_WR57, 0x00000000, - MGA_WR53, 0x00000000, - MGA_WR61, 0x00000000, - MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC); - - DMA_BLOCK(MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC, - MGA_TEXTRANS, 0x0000ffff, - MGA_TEXTRANSHIGH, 0x0000ffff, - MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC); - - ADVANCE_DMA(); -} - -static __inline__ void mga_g200_emit_pipe(drm_mga_private_t * dev_priv) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int pipe = sarea_priv->warp_pipe; - DMA_LOCALS; - - BEGIN_DMA(3); - - DMA_BLOCK(MGA_WIADDR, MGA_WMODE_SUSPEND, - MGA_WVRTXSZ, 0x00000007, - MGA_WFLAG, 0x00000000, - MGA_WR24, 0x00000000); - - DMA_BLOCK(MGA_WR25, 0x00000100, - MGA_WR34, 0x00000000, - MGA_WR42, 0x0000ffff, - MGA_WR60, 0x0000ffff); - - /* Padding required to to hardware bug. - */ - DMA_BLOCK(MGA_DMAPAD, 0xffffffff, - MGA_DMAPAD, 0xffffffff, - MGA_DMAPAD, 0xffffffff, - MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] | - MGA_WMODE_START | dev_priv->wagp_enable)); - - ADVANCE_DMA(); -} - -static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int pipe = sarea_priv->warp_pipe; - DMA_LOCALS; - -/* printk("mga_g400_emit_pipe %x\n", pipe); */ - - BEGIN_DMA(10); - - DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000); - - if (pipe & MGA_T2) { - DMA_BLOCK(MGA_WVRTXSZ, 0x00001e09, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000); - - DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x1e000000); - } else { - if (dev_priv->warp_pipe & MGA_T2) { - /* Flush the WARP pipe */ - DMA_BLOCK(MGA_YDST, 0x00000000, - MGA_FXLEFT, 0x00000000, - MGA_FXRIGHT, 0x00000001, - MGA_DWGCTL, MGA_DWGCTL_FLUSH); - - DMA_BLOCK(MGA_LEN + MGA_EXEC, 0x00000001, - MGA_DWGSYNC, 0x00007000, - MGA_TEXCTL2, MGA_G400_TC2_MAGIC, - MGA_LEN + MGA_EXEC, 0x00000000); - - DMA_BLOCK(MGA_TEXCTL2, (MGA_DUALTEX | - MGA_G400_TC2_MAGIC), - MGA_LEN + MGA_EXEC, 0x00000000, - MGA_TEXCTL2, MGA_G400_TC2_MAGIC, - MGA_DMAPAD, 0x00000000); - } - - DMA_BLOCK(MGA_WVRTXSZ, 0x00001807, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000); - - DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x18000000); - } - - DMA_BLOCK(MGA_WFLAG, 0x00000000, - MGA_WFLAG1, 0x00000000, - MGA_WR56, MGA_G400_WR56_MAGIC, - MGA_DMAPAD, 0x00000000); - - DMA_BLOCK(MGA_WR49, 0x00000000, /* tex0 */ - MGA_WR57, 0x00000000, /* tex0 */ - MGA_WR53, 0x00000000, /* tex1 */ - MGA_WR61, 0x00000000); /* tex1 */ - - DMA_BLOCK(MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */ - MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */ - MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */ - MGA_WR60, MGA_G400_WR_MAGIC); /* tex1 height */ - - /* Padding required to to hardware bug */ - DMA_BLOCK(MGA_DMAPAD, 0xffffffff, - MGA_DMAPAD, 0xffffffff, - MGA_DMAPAD, 0xffffffff, - MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] | - MGA_WMODE_START | dev_priv->wagp_enable)); - - ADVANCE_DMA(); -} - -static void mga_g200_emit_state(drm_mga_private_t * dev_priv) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int dirty = sarea_priv->dirty; - - if (sarea_priv->warp_pipe != dev_priv->warp_pipe) { - mga_g200_emit_pipe(dev_priv); - dev_priv->warp_pipe = sarea_priv->warp_pipe; - } - - if (dirty & MGA_UPLOAD_CONTEXT) { - mga_g200_emit_context(dev_priv); - sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; - } - - if (dirty & MGA_UPLOAD_TEX0) { - mga_g200_emit_tex0(dev_priv); - sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; - } -} - -static void mga_g400_emit_state(drm_mga_private_t * dev_priv) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int dirty = sarea_priv->dirty; - int multitex = sarea_priv->warp_pipe & MGA_T2; - - if (sarea_priv->warp_pipe != dev_priv->warp_pipe) { - mga_g400_emit_pipe(dev_priv); - dev_priv->warp_pipe = sarea_priv->warp_pipe; - } - - if (dirty & MGA_UPLOAD_CONTEXT) { - mga_g400_emit_context(dev_priv); - sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; - } - - if (dirty & MGA_UPLOAD_TEX0) { - mga_g400_emit_tex0(dev_priv); - sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; - } - - if ((dirty & MGA_UPLOAD_TEX1) && multitex) { - mga_g400_emit_tex1(dev_priv); - sarea_priv->dirty &= ~MGA_UPLOAD_TEX1; - } -} - -/* ================================================================ - * SAREA state verification - */ - -/* Disallow all write destinations except the front and backbuffer. - */ -static int mga_verify_context(drm_mga_private_t * dev_priv) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - - if (ctx->dstorg != dev_priv->front_offset && - ctx->dstorg != dev_priv->back_offset) { - DRM_ERROR("*** bad DSTORG: %x (front %x, back %x)\n\n", - ctx->dstorg, dev_priv->front_offset, - dev_priv->back_offset); - ctx->dstorg = 0; - return -EINVAL; - } - - return 0; -} - -/* Disallow texture reads from PCI space. - */ -static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit]; - unsigned int org; - - org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK); - - if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) { - DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit); - tex->texorg = 0; - return -EINVAL; - } - - return 0; -} - -static int mga_verify_state(drm_mga_private_t * dev_priv) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int dirty = sarea_priv->dirty; - int ret = 0; - - if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) - sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - - if (dirty & MGA_UPLOAD_CONTEXT) - ret |= mga_verify_context(dev_priv); - - if (dirty & MGA_UPLOAD_TEX0) - ret |= mga_verify_tex(dev_priv, 0); - - if (dev_priv->chipset >= MGA_CARD_TYPE_G400) { - if (dirty & MGA_UPLOAD_TEX1) - ret |= mga_verify_tex(dev_priv, 1); - - if (dirty & MGA_UPLOAD_PIPE) - ret |= (sarea_priv->warp_pipe > MGA_MAX_G400_PIPES); - } else { - if (dirty & MGA_UPLOAD_PIPE) - ret |= (sarea_priv->warp_pipe > MGA_MAX_G200_PIPES); - } - - return (ret == 0); -} - -static int mga_verify_iload(drm_mga_private_t * dev_priv, - unsigned int dstorg, unsigned int length) -{ - if (dstorg < dev_priv->texture_offset || - dstorg + length > (dev_priv->texture_offset + - dev_priv->texture_size)) { - DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg); - return -EINVAL; - } - - if (length & MGA_ILOAD_MASK) { - DRM_ERROR("*** bad iload length: 0x%x\n", - length & MGA_ILOAD_MASK); - return -EINVAL; - } - - return 0; -} - -static int mga_verify_blit(drm_mga_private_t * dev_priv, - unsigned int srcorg, unsigned int dstorg) -{ - if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) || - (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) { - DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg); - return -EINVAL; - } - return 0; -} - -/* ================================================================ - * - */ - -static void mga_dma_dispatch_clear(struct drm_device * dev, drm_mga_clear_t * clear) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - struct drm_clip_rect *pbox = sarea_priv->boxes; - int nbox = sarea_priv->nbox; - int i; - DMA_LOCALS; - DRM_DEBUG("\n"); - - BEGIN_DMA(1); - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DWGSYNC, 0x00007100, - MGA_DWGSYNC, 0x00007000); - - ADVANCE_DMA(); - - for (i = 0; i < nbox; i++) { - struct drm_clip_rect *box = &pbox[i]; - u32 height = box->y2 - box->y1; - - DRM_DEBUG(" from=%d,%d to=%d,%d\n", - box->x1, box->y1, box->x2, box->y2); - - if (clear->flags & MGA_FRONT) { - BEGIN_DMA(2); - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_PLNWT, clear->color_mask, - MGA_YDSTLEN, (box->y1 << 16) | height, - MGA_FXBNDRY, (box->x2 << 16) | box->x1); - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_FCOL, clear->clear_color, - MGA_DSTORG, dev_priv->front_offset, - MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd); - - ADVANCE_DMA(); - } - - if (clear->flags & MGA_BACK) { - BEGIN_DMA(2); - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_PLNWT, clear->color_mask, - MGA_YDSTLEN, (box->y1 << 16) | height, - MGA_FXBNDRY, (box->x2 << 16) | box->x1); - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_FCOL, clear->clear_color, - MGA_DSTORG, dev_priv->back_offset, - MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd); - - ADVANCE_DMA(); - } - - if (clear->flags & MGA_DEPTH) { - BEGIN_DMA(2); - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_PLNWT, clear->depth_mask, - MGA_YDSTLEN, (box->y1 << 16) | height, - MGA_FXBNDRY, (box->x2 << 16) | box->x1); - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_FCOL, clear->clear_depth, - MGA_DSTORG, dev_priv->depth_offset, - MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd); - - ADVANCE_DMA(); - } - - } - - BEGIN_DMA(1); - - /* Force reset of DWGCTL */ - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_PLNWT, ctx->plnwt, - MGA_DWGCTL, ctx->dwgctl); - - ADVANCE_DMA(); - - FLUSH_DMA(); -} - -static void mga_dma_dispatch_swap(struct drm_device * dev) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - struct drm_clip_rect *pbox = sarea_priv->boxes; - int nbox = sarea_priv->nbox; - int i; - DMA_LOCALS; - DRM_DEBUG("\n"); - - sarea_priv->last_frame.head = dev_priv->prim.tail; - sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap; - - BEGIN_DMA(4 + nbox); - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DWGSYNC, 0x00007100, - MGA_DWGSYNC, 0x00007000); - - DMA_BLOCK(MGA_DSTORG, dev_priv->front_offset, - MGA_MACCESS, dev_priv->maccess, - MGA_SRCORG, dev_priv->back_offset, - MGA_AR5, dev_priv->front_pitch); - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_PLNWT, 0xffffffff, - MGA_DWGCTL, MGA_DWGCTL_COPY); - - for (i = 0; i < nbox; i++) { - struct drm_clip_rect *box = &pbox[i]; - u32 height = box->y2 - box->y1; - u32 start = box->y1 * dev_priv->front_pitch; - - DRM_DEBUG(" from=%d,%d to=%d,%d\n", - box->x1, box->y1, box->x2, box->y2); - - DMA_BLOCK(MGA_AR0, start + box->x2 - 1, - MGA_AR3, start + box->x1, - MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1, - MGA_YDSTLEN + MGA_EXEC, (box->y1 << 16) | height); - } - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_PLNWT, ctx->plnwt, - MGA_SRCORG, dev_priv->front_offset, - MGA_DWGCTL, ctx->dwgctl); - - ADVANCE_DMA(); - - FLUSH_DMA(); - - DRM_DEBUG("... done.\n"); -} - -static void mga_dma_dispatch_vertex(struct drm_device * dev, struct drm_buf * buf) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_buf_priv_t *buf_priv = buf->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - u32 address = (u32) buf->bus_address; - u32 length = (u32) buf->used; - int i = 0; - DMA_LOCALS; - DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used); - - if (buf->used) { - buf_priv->dispatched = 1; - - MGA_EMIT_STATE(dev_priv, sarea_priv->dirty); - - do { - if (i < sarea_priv->nbox) { - mga_emit_clip_rect(dev_priv, - &sarea_priv->boxes[i]); - } - - BEGIN_DMA(1); - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_SECADDRESS, (address | - MGA_DMA_VERTEX), - MGA_SECEND, ((address + length) | - dev_priv->dma_access)); - - ADVANCE_DMA(); - } while (++i < sarea_priv->nbox); - } - - if (buf_priv->discard) { - AGE_BUFFER(buf_priv); - buf->pending = 0; - buf->used = 0; - buf_priv->dispatched = 0; - - mga_freelist_put(dev, buf); - } - - FLUSH_DMA(); -} - -static void mga_dma_dispatch_indices(struct drm_device * dev, struct drm_buf * buf, - unsigned int start, unsigned int end) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_buf_priv_t *buf_priv = buf->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - u32 address = (u32) buf->bus_address; - int i = 0; - DMA_LOCALS; - DRM_DEBUG("buf=%d start=%d end=%d\n", buf->idx, start, end); - - if (start != end) { - buf_priv->dispatched = 1; - - MGA_EMIT_STATE(dev_priv, sarea_priv->dirty); - - do { - if (i < sarea_priv->nbox) { - mga_emit_clip_rect(dev_priv, - &sarea_priv->boxes[i]); - } - - BEGIN_DMA(1); - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_SETUPADDRESS, address + start, - MGA_SETUPEND, ((address + end) | - dev_priv->dma_access)); - - ADVANCE_DMA(); - } while (++i < sarea_priv->nbox); - } - - if (buf_priv->discard) { - AGE_BUFFER(buf_priv); - buf->pending = 0; - buf->used = 0; - buf_priv->dispatched = 0; - - mga_freelist_put(dev, buf); - } - - FLUSH_DMA(); -} - -/* This copies a 64 byte aligned agp region to the frambuffer with a - * standard blit, the ioctl needs to do checking. - */ -static void mga_dma_dispatch_iload(struct drm_device * dev, struct drm_buf * buf, - unsigned int dstorg, unsigned int length) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_buf_priv_t *buf_priv = buf->dev_private; - drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state; - u32 srcorg = buf->bus_address | dev_priv->dma_access | MGA_SRCMAP_SYSMEM; - u32 y2; - DMA_LOCALS; - DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used); - - y2 = length / 64; - - BEGIN_DMA(5); - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DWGSYNC, 0x00007100, - MGA_DWGSYNC, 0x00007000); - - DMA_BLOCK(MGA_DSTORG, dstorg, - MGA_MACCESS, 0x00000000, - MGA_SRCORG, srcorg, - MGA_AR5, 64); - - DMA_BLOCK(MGA_PITCH, 64, - MGA_PLNWT, 0xffffffff, - MGA_DMAPAD, 0x00000000, - MGA_DWGCTL, MGA_DWGCTL_COPY); - - DMA_BLOCK(MGA_AR0, 63, - MGA_AR3, 0, - MGA_FXBNDRY, (63 << 16) | 0, - MGA_YDSTLEN + MGA_EXEC, y2); - - DMA_BLOCK(MGA_PLNWT, ctx->plnwt, - MGA_SRCORG, dev_priv->front_offset, - MGA_PITCH, dev_priv->front_pitch, - MGA_DWGSYNC, 0x00007000); - - ADVANCE_DMA(); - - AGE_BUFFER(buf_priv); - - buf->pending = 0; - buf->used = 0; - buf_priv->dispatched = 0; - - mga_freelist_put(dev, buf); - - FLUSH_DMA(); -} - -static void mga_dma_dispatch_blit(struct drm_device * dev, drm_mga_blit_t * blit) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - struct drm_clip_rect *pbox = sarea_priv->boxes; - int nbox = sarea_priv->nbox; - u32 scandir = 0, i; - DMA_LOCALS; - DRM_DEBUG("\n"); - - BEGIN_DMA(4 + nbox); - - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DWGSYNC, 0x00007100, - MGA_DWGSYNC, 0x00007000); - - DMA_BLOCK(MGA_DWGCTL, MGA_DWGCTL_COPY, - MGA_PLNWT, blit->planemask, - MGA_SRCORG, blit->srcorg, - MGA_DSTORG, blit->dstorg); - - DMA_BLOCK(MGA_SGN, scandir, - MGA_MACCESS, dev_priv->maccess, - MGA_AR5, blit->ydir * blit->src_pitch, - MGA_PITCH, blit->dst_pitch); - - for (i = 0; i < nbox; i++) { - int srcx = pbox[i].x1 + blit->delta_sx; - int srcy = pbox[i].y1 + blit->delta_sy; - int dstx = pbox[i].x1 + blit->delta_dx; - int dsty = pbox[i].y1 + blit->delta_dy; - int h = pbox[i].y2 - pbox[i].y1; - int w = pbox[i].x2 - pbox[i].x1 - 1; - int start; - - if (blit->ydir == -1) { - srcy = blit->height - srcy - 1; - } - - start = srcy * blit->src_pitch + srcx; - - DMA_BLOCK(MGA_AR0, start + w, - MGA_AR3, start, - MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff), - MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h); - } - - /* Do something to flush AGP? - */ - - /* Force reset of DWGCTL */ - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_PLNWT, ctx->plnwt, - MGA_PITCH, dev_priv->front_pitch, - MGA_DWGCTL, ctx->dwgctl); - - ADVANCE_DMA(); -} - -/* ================================================================ - * - */ - -static int mga_dma_clear(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_clear_t *clear = data; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) - sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - - WRAP_TEST_WITH_RETURN(dev_priv); - - mga_dma_dispatch_clear(dev, clear); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; - - return 0; -} - -static int mga_dma_swap(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) - sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - - WRAP_TEST_WITH_RETURN(dev_priv); - - mga_dma_dispatch_swap(dev); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; - - return 0; -} - -static int mga_dma_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - struct drm_device_dma *dma = dev->dma; - struct drm_buf *buf; - drm_mga_buf_priv_t *buf_priv; - drm_mga_vertex_t *vertex = data; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (vertex->idx < 0 || vertex->idx > dma->buf_count) - return -EINVAL; - buf = dma->buflist[vertex->idx]; - buf_priv = buf->dev_private; - - buf->used = vertex->used; - buf_priv->discard = vertex->discard; - - if (!mga_verify_state(dev_priv)) { - if (vertex->discard) { - if (buf_priv->dispatched == 1) - AGE_BUFFER(buf_priv); - buf_priv->dispatched = 0; - mga_freelist_put(dev, buf); - } - return -EINVAL; - } - - WRAP_TEST_WITH_RETURN(dev_priv); - - mga_dma_dispatch_vertex(dev, buf); - - return 0; -} - -static int mga_dma_indices(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - struct drm_device_dma *dma = dev->dma; - struct drm_buf *buf; - drm_mga_buf_priv_t *buf_priv; - drm_mga_indices_t *indices = data; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (indices->idx < 0 || indices->idx > dma->buf_count) - return -EINVAL; - - buf = dma->buflist[indices->idx]; - buf_priv = buf->dev_private; - - buf_priv->discard = indices->discard; - - if (!mga_verify_state(dev_priv)) { - if (indices->discard) { - if (buf_priv->dispatched == 1) - AGE_BUFFER(buf_priv); - buf_priv->dispatched = 0; - mga_freelist_put(dev, buf); - } - return -EINVAL; - } - - WRAP_TEST_WITH_RETURN(dev_priv); - - mga_dma_dispatch_indices(dev, buf, indices->start, indices->end); - - return 0; -} - -static int mga_dma_iload(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - struct drm_device_dma *dma = dev->dma; - drm_mga_private_t *dev_priv = dev->dev_private; - struct drm_buf *buf; - drm_mga_buf_priv_t *buf_priv; - drm_mga_iload_t *iload = data; - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - -#if 0 - if (mga_do_wait_for_idle(dev_priv) < 0) { - if (MGA_DMA_DEBUG) - DRM_INFO("-EBUSY\n"); - return -EBUSY; - } -#endif - if (iload->idx < 0 || iload->idx > dma->buf_count) - return -EINVAL; - - buf = dma->buflist[iload->idx]; - buf_priv = buf->dev_private; - - if (mga_verify_iload(dev_priv, iload->dstorg, iload->length)) { - mga_freelist_put(dev, buf); - return -EINVAL; - } - - WRAP_TEST_WITH_RETURN(dev_priv); - - mga_dma_dispatch_iload(dev, buf, iload->dstorg, iload->length); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; - - return 0; -} - -static int mga_dma_blit(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_blit_t *blit = data; - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) - sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - - if (mga_verify_blit(dev_priv, blit->srcorg, blit->dstorg)) - return -EINVAL; - - WRAP_TEST_WITH_RETURN(dev_priv); - - mga_dma_dispatch_blit(dev, blit); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; - - return 0; -} - -static int mga_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_getparam_t *param = data; - int value; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - - switch (param->param) { - case MGA_PARAM_IRQ_NR: - value = dev->irq; - break; - case MGA_PARAM_CARD_TYPE: - value = dev_priv->chipset; - break; - default: - return -EINVAL; - } - - if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { - DRM_ERROR("copy_to_user\n"); - return -EFAULT; - } - - return 0; -} - -static int mga_set_fence(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - u32 *fence = data; - DMA_LOCALS; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - - /* I would normal do this assignment in the declaration of fence, - * but dev_priv may be NULL. - */ - - *fence = dev_priv->next_fence_to_post; - dev_priv->next_fence_to_post++; - - BEGIN_DMA(1); - DMA_BLOCK(MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_SOFTRAP, 0x00000000); - ADVANCE_DMA(); - - return 0; -} - -static int mga_wait_fence(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - u32 *fence = data; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - - mga_driver_fence_wait(dev, fence); - - return 0; -} - -struct drm_ioctl_desc mga_ioctls[] = { - DRM_IOCTL_DEF(DRM_MGA_INIT, mga_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_MGA_FLUSH, mga_dma_flush, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MGA_RESET, mga_dma_reset, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MGA_SWAP, mga_dma_swap, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MGA_CLEAR, mga_dma_clear, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MGA_VERTEX, mga_dma_vertex, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MGA_INDICES, mga_dma_indices, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MGA_ILOAD, mga_dma_iload, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MGA_BLIT, mga_dma_blit, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MGA_GETPARAM, mga_getparam, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MGA_SET_FENCE, mga_set_fence, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MGA_WAIT_FENCE, mga_wait_fence, DRM_AUTH), - DRM_IOCTL_DEF(DRM_MGA_DMA_BOOTSTRAP, mga_dma_bootstrap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - -}; - -int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls); diff --git a/shared-core/mga_ucode.h b/shared-core/mga_ucode.h deleted file mode 100644 index b611e274..00000000 --- a/shared-core/mga_ucode.h +++ /dev/null @@ -1,11645 +0,0 @@ -/* mga_ucode.h -- Matrox G200/G400 WARP engine microcode -*- linux-c -*- - * Created: Thu Jan 11 21:20:43 2001 by gareth@valinux.com - * - * Copyright 1999 Matrox Graphics Inc. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * MATROX GRAPHICS INC., OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE - * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Kernel-based WARP engine management: - * Gareth Hughes - */ - -/* - * WARP pipes are named according to the functions they perform, where: - * - * - T stands for computation of texture stage 0 - * - T2 stands for computation of both texture stage 0 and texture stage 1 - * - G stands for computation of triangle intensity (Gouraud interpolation) - * - Z stands for computation of Z buffer interpolation - * - S stands for computation of specular highlight - * - A stands for computation of the alpha channel - * - F stands for computation of vertex fog interpolation - */ - -static unsigned char warp_g200_tgz[] = { - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x72, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x60, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 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- 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x03, 0x80, 0x0A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x57, 0x39, 0x20, 0xE9, - 0x28, 0x19, 0x60, 0xEC, - - 0x2B, 0x32, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0xB3, 0x05, - 0x00, 0xE0, - 0x16, 0x28, 0x20, 0xE9, - - 0x23, 0x3B, 0x33, 0xAD, - 0x1E, 0x2B, 0x20, 0xE9, - - 0x1C, 0x80, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x85, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x84, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x82, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x7F, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g200_tgza[] = { - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x7D, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - 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0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x78, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_t2gzs[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x85, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - 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- 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0x9D, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xC5, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x8B, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; diff --git a/shared-core/mga_warp.c b/shared-core/mga_warp.c deleted file mode 100644 index 9a44bddb..00000000 --- a/shared-core/mga_warp.c +++ /dev/null @@ -1,198 +0,0 @@ -/* mga_warp.c -- Matrox G200/G400 WARP engine management -*- linux-c -*- - * Created: Thu Jan 11 21:29:32 2001 by gareth@valinux.com - */ -/* - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - */ - -#include "drmP.h" -#include "drm.h" -#include "mga_drm.h" -#include "mga_drv.h" -#include "mga_ucode.h" - -#define MGA_WARP_CODE_ALIGN 256 /* in bytes */ - -#define WARP_UCODE_SIZE( which ) \ - ((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN) - -#define WARP_UCODE_INSTALL( which, where ) \ -do { \ - DRM_DEBUG( " pcbase = 0x%08lx vcbase = %p\n", pcbase, vcbase );\ - dev_priv->warp_pipe_phys[where] = pcbase; \ - memcpy( vcbase, which, sizeof(which) ); \ - pcbase += WARP_UCODE_SIZE( which ); \ - vcbase += WARP_UCODE_SIZE( which ); \ -} while (0) - -static const unsigned int mga_warp_g400_microcode_size = - (WARP_UCODE_SIZE(warp_g400_tgz) + - WARP_UCODE_SIZE(warp_g400_tgza) + - WARP_UCODE_SIZE(warp_g400_tgzaf) + - WARP_UCODE_SIZE(warp_g400_tgzf) + - WARP_UCODE_SIZE(warp_g400_tgzs) + - WARP_UCODE_SIZE(warp_g400_tgzsa) + - WARP_UCODE_SIZE(warp_g400_tgzsaf) + - WARP_UCODE_SIZE(warp_g400_tgzsf) + - WARP_UCODE_SIZE(warp_g400_t2gz) + - WARP_UCODE_SIZE(warp_g400_t2gza) + - WARP_UCODE_SIZE(warp_g400_t2gzaf) + - WARP_UCODE_SIZE(warp_g400_t2gzf) + - WARP_UCODE_SIZE(warp_g400_t2gzs) + - WARP_UCODE_SIZE(warp_g400_t2gzsa) + - WARP_UCODE_SIZE(warp_g400_t2gzsaf) + - WARP_UCODE_SIZE(warp_g400_t2gzsf)); - -static const unsigned int mga_warp_g200_microcode_size = - (WARP_UCODE_SIZE(warp_g200_tgz) + - WARP_UCODE_SIZE(warp_g200_tgza) + - WARP_UCODE_SIZE(warp_g200_tgzaf) + - WARP_UCODE_SIZE(warp_g200_tgzf) + - WARP_UCODE_SIZE(warp_g200_tgzs) + - WARP_UCODE_SIZE(warp_g200_tgzsa) + - WARP_UCODE_SIZE(warp_g200_tgzsaf) + - WARP_UCODE_SIZE(warp_g200_tgzsf)); - - -unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv) -{ - switch (dev_priv->chipset) { - case MGA_CARD_TYPE_G400: - case MGA_CARD_TYPE_G550: - return PAGE_ALIGN(mga_warp_g400_microcode_size); - case MGA_CARD_TYPE_G200: - return PAGE_ALIGN(mga_warp_g200_microcode_size); - default: - DRM_ERROR("Unknown chipset value: 0x%x\n", dev_priv->chipset); - return 0; - } -} - -static int mga_warp_install_g400_microcode(drm_mga_private_t * dev_priv) -{ - unsigned char *vcbase = dev_priv->warp->handle; - unsigned long pcbase = dev_priv->warp->offset; - - memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); - - WARP_UCODE_INSTALL(warp_g400_tgz, MGA_WARP_TGZ); - WARP_UCODE_INSTALL(warp_g400_tgzf, MGA_WARP_TGZF); - WARP_UCODE_INSTALL(warp_g400_tgza, MGA_WARP_TGZA); - WARP_UCODE_INSTALL(warp_g400_tgzaf, MGA_WARP_TGZAF); - WARP_UCODE_INSTALL(warp_g400_tgzs, MGA_WARP_TGZS); - WARP_UCODE_INSTALL(warp_g400_tgzsf, MGA_WARP_TGZSF); - WARP_UCODE_INSTALL(warp_g400_tgzsa, MGA_WARP_TGZSA); - WARP_UCODE_INSTALL(warp_g400_tgzsaf, MGA_WARP_TGZSAF); - - WARP_UCODE_INSTALL(warp_g400_t2gz, MGA_WARP_T2GZ); - WARP_UCODE_INSTALL(warp_g400_t2gzf, MGA_WARP_T2GZF); - WARP_UCODE_INSTALL(warp_g400_t2gza, MGA_WARP_T2GZA); - WARP_UCODE_INSTALL(warp_g400_t2gzaf, MGA_WARP_T2GZAF); - WARP_UCODE_INSTALL(warp_g400_t2gzs, MGA_WARP_T2GZS); - WARP_UCODE_INSTALL(warp_g400_t2gzsf, MGA_WARP_T2GZSF); - WARP_UCODE_INSTALL(warp_g400_t2gzsa, MGA_WARP_T2GZSA); - WARP_UCODE_INSTALL(warp_g400_t2gzsaf, MGA_WARP_T2GZSAF); - - return 0; -} - -static int mga_warp_install_g200_microcode(drm_mga_private_t * dev_priv) -{ - unsigned char *vcbase = dev_priv->warp->handle; - unsigned long pcbase = dev_priv->warp->offset; - - memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); - - WARP_UCODE_INSTALL(warp_g200_tgz, MGA_WARP_TGZ); - WARP_UCODE_INSTALL(warp_g200_tgzf, MGA_WARP_TGZF); - WARP_UCODE_INSTALL(warp_g200_tgza, MGA_WARP_TGZA); - WARP_UCODE_INSTALL(warp_g200_tgzaf, MGA_WARP_TGZAF); - WARP_UCODE_INSTALL(warp_g200_tgzs, MGA_WARP_TGZS); - WARP_UCODE_INSTALL(warp_g200_tgzsf, MGA_WARP_TGZSF); - WARP_UCODE_INSTALL(warp_g200_tgzsa, MGA_WARP_TGZSA); - WARP_UCODE_INSTALL(warp_g200_tgzsaf, MGA_WARP_TGZSAF); - - return 0; -} - -int mga_warp_install_microcode(drm_mga_private_t * dev_priv) -{ - const unsigned int size = mga_warp_microcode_size(dev_priv); - - DRM_DEBUG("MGA ucode size = %d bytes\n", size); - if (size > dev_priv->warp->size) { - DRM_ERROR("microcode too large! (%u > %lu)\n", - size, dev_priv->warp->size); - return -ENOMEM; - } - - switch (dev_priv->chipset) { - case MGA_CARD_TYPE_G400: - case MGA_CARD_TYPE_G550: - return mga_warp_install_g400_microcode(dev_priv); - case MGA_CARD_TYPE_G200: - return mga_warp_install_g200_microcode(dev_priv); - default: - return -EINVAL; - } -} - -#define WMISC_EXPECTED (MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE) - -int mga_warp_init(drm_mga_private_t * dev_priv) -{ - u32 wmisc; - - /* FIXME: Get rid of these damned magic numbers... - */ - switch (dev_priv->chipset) { - case MGA_CARD_TYPE_G400: - case MGA_CARD_TYPE_G550: - MGA_WRITE(MGA_WIADDR2, MGA_WMODE_SUSPEND); - MGA_WRITE(MGA_WGETMSB, 0x00000E00); - MGA_WRITE(MGA_WVRTXSZ, 0x00001807); - MGA_WRITE(MGA_WACCEPTSEQ, 0x18000000); - break; - case MGA_CARD_TYPE_G200: - MGA_WRITE(MGA_WIADDR, MGA_WMODE_SUSPEND); - MGA_WRITE(MGA_WGETMSB, 0x1606); - MGA_WRITE(MGA_WVRTXSZ, 7); - break; - default: - return -EINVAL; - } - - MGA_WRITE(MGA_WMISC, (MGA_WUCODECACHE_ENABLE | - MGA_WMASTER_ENABLE | MGA_WCACHEFLUSH_ENABLE)); - wmisc = MGA_READ(MGA_WMISC); - if (wmisc != WMISC_EXPECTED) { - DRM_ERROR("WARP engine config failed! 0x%x != 0x%x\n", - wmisc, WMISC_EXPECTED); - return -EINVAL; - } - - return 0; -} diff --git a/shared-core/nouveau_dma.c b/shared-core/nouveau_dma.c deleted file mode 100644 index 8b1549c7..00000000 --- a/shared-core/nouveau_dma.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright (C) 2007 Ben Skeggs. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" -#include "nouveau_dma.h" - -int -nouveau_dma_channel_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_drm_channel *dchan = &dev_priv->channel; - struct nouveau_gpuobj *gpuobj = NULL; - struct mem_block *pushbuf; - int grclass, ret, i; - - DRM_DEBUG("\n"); - - pushbuf = nouveau_mem_alloc(dev, 0, 0x8000, - NOUVEAU_MEM_FB | NOUVEAU_MEM_MAPPED, - (struct drm_file *)-2); - if (!pushbuf) { - DRM_ERROR("Failed to allocate DMA push buffer\n"); - return -ENOMEM; - } - - /* Allocate channel */ - ret = nouveau_fifo_alloc(dev, &dchan->chan, (struct drm_file *)-2, - pushbuf, NvDmaFB, NvDmaTT); - if (ret) { - DRM_ERROR("Error allocating GPU channel: %d\n", ret); - return ret; - } - DRM_DEBUG("Using FIFO channel %d\n", dchan->chan->id); - - /* Map push buffer */ - drm_core_ioremap(dchan->chan->pushbuf_mem->map, dev); - if (!dchan->chan->pushbuf_mem->map->handle) { - DRM_ERROR("Failed to ioremap push buffer\n"); - return -EINVAL; - } - dchan->pushbuf = (void*)dchan->chan->pushbuf_mem->map->handle; - - /* Initialise DMA vars */ - dchan->max = (dchan->chan->pushbuf_mem->size >> 2) - 2; - dchan->put = dchan->chan->pushbuf_base >> 2; - dchan->cur = dchan->put; - dchan->free = dchan->max - dchan->cur; - - /* Insert NOPS for NOUVEAU_DMA_SKIPS */ - dchan->free -= NOUVEAU_DMA_SKIPS; - dchan->push_free = NOUVEAU_DMA_SKIPS; - for (i=0; i < NOUVEAU_DMA_SKIPS; i++) - OUT_RING(0); - - /* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier */ - if ((ret = nouveau_notifier_alloc(dchan->chan, NvNotify0, 1, - &dchan->notify0_offset))) { - DRM_ERROR("Error allocating NvNotify0: %d\n", ret); - return ret; - } - - /* We use NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */ - if (dev_priv->card_type < NV_50) grclass = NV_MEMORY_TO_MEMORY_FORMAT; - else grclass = NV50_MEMORY_TO_MEMORY_FORMAT; - if ((ret = nouveau_gpuobj_gr_new(dchan->chan, grclass, &gpuobj))) { - DRM_ERROR("Error creating NvM2MF: %d\n", ret); - return ret; - } - - if ((ret = nouveau_gpuobj_ref_add(dev, dchan->chan, NvM2MF, - gpuobj, NULL))) { - DRM_ERROR("Error referencing NvM2MF: %d\n", ret); - return ret; - } - dchan->m2mf_dma_source = NvDmaFB; - dchan->m2mf_dma_destin = NvDmaFB; - - BEGIN_RING(NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1); - OUT_RING (NvM2MF); - BEGIN_RING(NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_SET_DMA_NOTIFY, 1); - OUT_RING (NvNotify0); - BEGIN_RING(NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_SET_DMA_SOURCE, 2); - OUT_RING (dchan->m2mf_dma_source); - OUT_RING (dchan->m2mf_dma_destin); - FIRE_RING(); - - return 0; -} - -void -nouveau_dma_channel_takedown(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_drm_channel *dchan = &dev_priv->channel; - - DRM_DEBUG("\n"); - - if (dchan->chan) { - drm_core_ioremapfree(dchan->chan->pushbuf_mem->map, dev); - nouveau_fifo_free(dchan->chan); - dchan->chan = NULL; - } -} - -#define READ_GET() ((NV_READ(dchan->chan->get) - \ - dchan->chan->pushbuf_base) >> 2) -#define WRITE_PUT(val) do { \ - NV_WRITE(dchan->chan->put, \ - ((val) << 2) + dchan->chan->pushbuf_base); \ -} while(0) - -int -nouveau_dma_wait(struct drm_device *dev, int size) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_drm_channel *dchan = &dev_priv->channel; - uint32_t get; - - while (dchan->free < size) { - get = READ_GET(); - - if (dchan->put >= get) { - dchan->free = dchan->max - dchan->cur; - - if (dchan->free < size) { - dchan->push_free = 1; - OUT_RING(0x20000000|dchan->chan->pushbuf_base); - if (get <= NOUVEAU_DMA_SKIPS) { - /*corner case - will be idle*/ - if (dchan->put <= NOUVEAU_DMA_SKIPS) - WRITE_PUT(NOUVEAU_DMA_SKIPS + 1); - - do { - get = READ_GET(); - } while (get <= NOUVEAU_DMA_SKIPS); - } - - WRITE_PUT(NOUVEAU_DMA_SKIPS); - dchan->cur = dchan->put = NOUVEAU_DMA_SKIPS; - dchan->free = get - (NOUVEAU_DMA_SKIPS + 1); - } - } else { - dchan->free = get - dchan->cur - 1; - } - } - - return 0; -} diff --git a/shared-core/nouveau_dma.h b/shared-core/nouveau_dma.h deleted file mode 100644 index ce3c58cb..00000000 --- a/shared-core/nouveau_dma.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (C) 2007 Ben Skeggs. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef __NOUVEAU_DMA_H__ -#define __NOUVEAU_DMA_H__ - -typedef enum { - NvSubM2MF = 0, -} nouveau_subchannel_id_t; - -typedef enum { - NvM2MF = 0x80039001, - NvDmaFB = 0x8003d001, - NvDmaTT = 0x8003d002, - NvNotify0 = 0x8003d003 -} nouveau_object_handle_t; - -#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 -#define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000 -#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001 -#define NV_MEMORY_TO_MEMORY_FORMAT_SET_DMA_NOTIFY 0x00000180 -#define NV_MEMORY_TO_MEMORY_FORMAT_SET_DMA_SOURCE 0x00000184 -#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c - -#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 -#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200 -#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c -#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238 -#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c - -#define BEGIN_RING(subc, mthd, cnt) do { \ - int push_size = (cnt) + 1; \ - if (dchan->push_free) { \ - DRM_ERROR("prior packet incomplete: %d\n", dchan->push_free); \ - break; \ - } \ - if (dchan->free < push_size) { \ - if (nouveau_dma_wait(dev, push_size)) { \ - DRM_ERROR("FIFO timeout\n"); \ - break; \ - } \ - } \ - dchan->free -= push_size; \ - dchan->push_free = push_size; \ - OUT_RING(((cnt)<<18) | ((subc)<<15) | mthd); \ -} while(0) - -#define OUT_RING(data) do { \ - if (dchan->push_free == 0) { \ - DRM_ERROR("no space left in packet\n"); \ - break; \ - } \ - dchan->pushbuf[dchan->cur++] = (data); \ - dchan->push_free--; \ -} while(0) - -#define FIRE_RING() do { \ - if (dchan->push_free) { \ - DRM_ERROR("packet incomplete: %d\n", dchan->push_free); \ - break; \ - } \ - if (dchan->cur != dchan->put) { \ - DRM_MEMORYBARRIER(); \ - dchan->put = dchan->cur; \ - NV_WRITE(dchan->chan->put, dchan->put << 2); \ - } \ -} while(0) - -#endif diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h deleted file mode 100644 index 1e67c441..00000000 --- a/shared-core/nouveau_drm.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright 2005 Stephane Marchesin. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NOUVEAU_DRM_H__ -#define __NOUVEAU_DRM_H__ - -#define NOUVEAU_DRM_HEADER_PATCHLEVEL 15 - -struct drm_nouveau_channel_alloc { - uint32_t fb_ctxdma_handle; - uint32_t tt_ctxdma_handle; - - int channel; - - /* Notifier memory */ - uint32_t notifier_handle; - - /* DRM-enforced subchannel assignments */ - struct { - uint32_t handle; - uint32_t grclass; - } subchan[8]; - uint32_t nr_subchan; -}; - -struct drm_nouveau_channel_free { - int channel; -}; - -struct drm_nouveau_grobj_alloc { - int channel; - uint32_t handle; - int class; -}; - -struct drm_nouveau_notifierobj_alloc { - uint32_t channel; - uint32_t handle; - uint32_t size; - uint32_t offset; -}; - -struct drm_nouveau_gpuobj_free { - int channel; - uint32_t handle; -}; - -/* FIXME : maybe unify {GET,SET}PARAMs */ -#define NOUVEAU_GETPARAM_PCI_VENDOR 3 -#define NOUVEAU_GETPARAM_PCI_DEVICE 4 -#define NOUVEAU_GETPARAM_BUS_TYPE 5 -#define NOUVEAU_GETPARAM_FB_PHYSICAL 6 -#define NOUVEAU_GETPARAM_AGP_PHYSICAL 7 -#define NOUVEAU_GETPARAM_FB_SIZE 8 -#define NOUVEAU_GETPARAM_AGP_SIZE 9 -#define NOUVEAU_GETPARAM_PCI_PHYSICAL 10 -#define NOUVEAU_GETPARAM_CHIPSET_ID 11 -#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 -struct drm_nouveau_getparam { - uint64_t param; - uint64_t value; -}; - -struct drm_nouveau_setparam { - uint64_t param; - uint64_t value; -}; - -#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) -#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) -#define NOUVEAU_GEM_DOMAIN_GART (1 << 2) -#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) - -struct drm_nouveau_gem_info { - uint32_t handle; - uint32_t domain; - uint64_t size; - uint64_t offset; - uint64_t map_handle; - uint32_t tile_mode; - uint32_t tile_flags; -}; - -struct drm_nouveau_gem_new { - struct drm_nouveau_gem_info info; - uint32_t channel_hint; - uint32_t align; -}; - -struct drm_nouveau_gem_pushbuf_bo { - uint64_t user_priv; - uint32_t handle; - uint32_t read_domains; - uint32_t write_domains; - uint32_t valid_domains; - uint32_t presumed_ok; - uint32_t presumed_domain; - uint64_t presumed_offset; -}; - -#define NOUVEAU_GEM_RELOC_LOW (1 << 0) -#define NOUVEAU_GEM_RELOC_HIGH (1 << 1) -#define NOUVEAU_GEM_RELOC_OR (1 << 2) -struct drm_nouveau_gem_pushbuf_reloc { - uint32_t bo_index; - uint32_t reloc_index; - uint32_t flags; - uint32_t data; - uint32_t vor; - uint32_t tor; -}; - -#define NOUVEAU_GEM_MAX_BUFFERS 1024 -#define NOUVEAU_GEM_MAX_RELOCS 1024 - -struct drm_nouveau_gem_pushbuf { - uint32_t channel; - uint32_t nr_dwords; - uint32_t nr_buffers; - uint32_t nr_relocs; - uint64_t dwords; - uint64_t buffers; - uint64_t relocs; -}; - -struct drm_nouveau_gem_pushbuf_call { - uint32_t channel; - uint32_t handle; - uint32_t offset; - uint32_t nr_buffers; - uint32_t nr_relocs; - uint32_t nr_dwords; - uint64_t buffers; - uint64_t relocs; - uint32_t suffix0; - uint32_t suffix1; - /* below only accessed for CALL2 */ - uint64_t vram_available; - uint64_t gart_available; -}; - -struct drm_nouveau_gem_pin { - uint32_t handle; - uint32_t domain; - uint64_t offset; -}; - -struct drm_nouveau_gem_unpin { - uint32_t handle; -}; - -#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 -#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002 -#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 -struct drm_nouveau_gem_cpu_prep { - uint32_t handle; - uint32_t flags; -}; - -struct drm_nouveau_gem_cpu_fini { - uint32_t handle; -}; - -struct drm_nouveau_gem_tile { - uint32_t handle; - uint32_t offset; - uint32_t size; - uint32_t tile_mode; - uint32_t tile_flags; -}; - -enum nouveau_bus_type { - NV_AGP = 0, - NV_PCI = 1, - NV_PCIE = 2, -}; - -struct drm_nouveau_sarea { -}; - -#define DRM_NOUVEAU_CARD_INIT 0x00 -#define DRM_NOUVEAU_GETPARAM 0x01 -#define DRM_NOUVEAU_SETPARAM 0x02 -#define DRM_NOUVEAU_CHANNEL_ALLOC 0x03 -#define DRM_NOUVEAU_CHANNEL_FREE 0x04 -#define DRM_NOUVEAU_GROBJ_ALLOC 0x05 -#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x06 -#define DRM_NOUVEAU_GPUOBJ_FREE 0x07 -#define DRM_NOUVEAU_GEM_NEW 0x40 -#define DRM_NOUVEAU_GEM_PUSHBUF 0x41 -#define DRM_NOUVEAU_GEM_PUSHBUF_CALL 0x42 -#define DRM_NOUVEAU_GEM_PIN 0x43 /* !KMS only */ -#define DRM_NOUVEAU_GEM_UNPIN 0x44 /* !KMS only */ -#define DRM_NOUVEAU_GEM_CPU_PREP 0x45 -#define DRM_NOUVEAU_GEM_CPU_FINI 0x46 -#define DRM_NOUVEAU_GEM_INFO 0x47 -#define DRM_NOUVEAU_GEM_PUSHBUF_CALL2 0x48 - -#endif /* __NOUVEAU_DRM_H__ */ diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h deleted file mode 100644 index 841cbf53..00000000 --- a/shared-core/nouveau_drv.h +++ /dev/null @@ -1,626 +0,0 @@ -/* - * Copyright 2005 Stephane Marchesin. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NOUVEAU_DRV_H__ -#define __NOUVEAU_DRV_H__ - -#define DRIVER_AUTHOR "Stephane Marchesin" -#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" - -#define DRIVER_NAME "nouveau" -#define DRIVER_DESC "nVidia Riva/TNT/GeForce" -#define DRIVER_DATE "20060213" - -#define DRIVER_MAJOR 0 -#define DRIVER_MINOR 0 -#define DRIVER_PATCHLEVEL 14 - -#define NOUVEAU_FAMILY 0x0000FFFF -#define NOUVEAU_FLAGS 0xFFFF0000 - -#include "nouveau_drm.h" -#include "nouveau_reg.h" - -struct mem_block { - struct mem_block *next; - struct mem_block *prev; - uint64_t start; - uint64_t size; - struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ - int flags; - drm_local_map_t *map; - drm_handle_t map_handle; -}; - -enum nouveau_flags { - NV_NFORCE =0x10000000, - NV_NFORCE2 =0x20000000 -}; - -#define NVOBJ_ENGINE_SW 0 -#define NVOBJ_ENGINE_GR 1 -#define NVOBJ_ENGINE_INT 0xdeadbeef - -#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0) -#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) -#define NVOBJ_FLAG_ZERO_FREE (1 << 2) -#define NVOBJ_FLAG_FAKE (1 << 3) -struct nouveau_gpuobj { - struct list_head list; - - int im_channel; - struct mem_block *im_pramin; - struct mem_block *im_backing; - int im_bound; - - uint32_t flags; - int refcount; - - uint32_t engine; - uint32_t class; - - void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); - void *priv; -}; - -struct nouveau_gpuobj_ref { - struct list_head list; - - struct nouveau_gpuobj *gpuobj; - uint32_t instance; - - int channel; - int handle; -}; - -struct nouveau_channel -{ - struct drm_device *dev; - int id; - - /* owner of this fifo */ - struct drm_file *file_priv; - /* mapping of the fifo itself */ - drm_local_map_t *map; - /* mapping of the regs controling the fifo */ - drm_local_map_t *regs; - - /* Fencing */ - uint32_t next_sequence; - - /* DMA push buffer */ - struct nouveau_gpuobj_ref *pushbuf; - struct mem_block *pushbuf_mem; - uint32_t pushbuf_base; - - /* FIFO user control regs */ - uint32_t user, user_size; - uint32_t put; - uint32_t get; - uint32_t ref_cnt; - - /* Notifier memory */ - struct mem_block *notifier_block; - struct mem_block *notifier_heap; - drm_local_map_t *notifier_map; - - /* PFIFO context */ - struct nouveau_gpuobj_ref *ramfc; - - /* PGRAPH context */ - /* XXX may be merge 2 pointers as private data ??? */ - struct nouveau_gpuobj_ref *ramin_grctx; - void *pgraph_ctx; - - /* NV50 VM */ - struct nouveau_gpuobj *vm_pd; - struct nouveau_gpuobj_ref *vm_gart_pt; - struct nouveau_gpuobj_ref *vm_vram_pt; - - /* Objects */ - struct nouveau_gpuobj_ref *ramin; /* Private instmem */ - struct mem_block *ramin_heap; /* Private PRAMIN heap */ - struct nouveau_gpuobj_ref *ramht; /* Hash table */ - struct list_head ramht_refs; /* Objects referenced by RAMHT */ -}; - -struct nouveau_drm_channel { - struct nouveau_channel *chan; - - /* DMA state */ - int max, put, cur, free; - int push_free; - volatile uint32_t *pushbuf; - - /* Notifiers */ - uint32_t notify0_offset; - - /* Buffer moves */ - uint32_t m2mf_dma_source; - uint32_t m2mf_dma_destin; -}; - -struct nouveau_config { - struct { - int location; - int size; - } cmdbuf; -}; - -struct nouveau_instmem_engine { - void *priv; - - int (*init)(struct drm_device *dev); - void (*takedown)(struct drm_device *dev); - - int (*populate)(struct drm_device *, struct nouveau_gpuobj *, - uint32_t *size); - void (*clear)(struct drm_device *, struct nouveau_gpuobj *); - int (*bind)(struct drm_device *, struct nouveau_gpuobj *); - int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); -}; - -struct nouveau_mc_engine { - int (*init)(struct drm_device *dev); - void (*takedown)(struct drm_device *dev); -}; - -struct nouveau_timer_engine { - int (*init)(struct drm_device *dev); - void (*takedown)(struct drm_device *dev); - uint64_t (*read)(struct drm_device *dev); -}; - -struct nouveau_fb_engine { - int (*init)(struct drm_device *dev); - void (*takedown)(struct drm_device *dev); -}; - -struct nouveau_fifo_engine { - void *priv; - - int channels; - - int (*init)(struct drm_device *); - void (*takedown)(struct drm_device *); - - int (*channel_id)(struct drm_device *); - - int (*create_context)(struct nouveau_channel *); - void (*destroy_context)(struct nouveau_channel *); - int (*load_context)(struct nouveau_channel *); - int (*save_context)(struct nouveau_channel *); -}; - -struct nouveau_pgraph_engine { - int (*init)(struct drm_device *); - void (*takedown)(struct drm_device *); - - int (*create_context)(struct nouveau_channel *); - void (*destroy_context)(struct nouveau_channel *); - int (*load_context)(struct nouveau_channel *); - int (*save_context)(struct nouveau_channel *); -}; - -struct nouveau_engine { - struct nouveau_instmem_engine instmem; - struct nouveau_mc_engine mc; - struct nouveau_timer_engine timer; - struct nouveau_fb_engine fb; - struct nouveau_pgraph_engine graph; - struct nouveau_fifo_engine fifo; -}; - -#define NOUVEAU_MAX_CHANNEL_NR 128 -struct drm_nouveau_private { - enum { - NOUVEAU_CARD_INIT_DOWN, - NOUVEAU_CARD_INIT_DONE, - NOUVEAU_CARD_INIT_FAILED - } init_state; - - int ttm; - - /* the card type, takes NV_* as values */ - int card_type; - /* exact chipset, derived from NV_PMC_BOOT_0 */ - int chipset; - int flags; - - drm_local_map_t *mmio; - drm_local_map_t *fb; - drm_local_map_t *ramin; /* NV40 onwards */ - - int fifo_alloc_count; - struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; - - struct nouveau_engine Engine; - struct nouveau_drm_channel channel; - - /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ - struct nouveau_gpuobj *ramht; - uint32_t ramin_rsvd_vram; - uint32_t ramht_offset; - uint32_t ramht_size; - uint32_t ramht_bits; - uint32_t ramfc_offset; - uint32_t ramfc_size; - uint32_t ramro_offset; - uint32_t ramro_size; - - /* base physical adresses */ - uint64_t fb_phys; - uint64_t fb_available_size; - - struct { - enum { - NOUVEAU_GART_NONE = 0, - NOUVEAU_GART_AGP, - NOUVEAU_GART_SGDMA - } type; - uint64_t aper_base; - uint64_t aper_size; - - struct nouveau_gpuobj *sg_ctxdma; - struct page *sg_dummy_page; - dma_addr_t sg_dummy_bus; - - /* nottm hack */ - struct drm_ttm_backend *sg_be; - unsigned long sg_handle; - } gart_info; - - /* G8x global VRAM page table */ - struct nouveau_gpuobj *vm_vram_pt; - - /* the mtrr covering the FB */ - int fb_mtrr; - - struct mem_block *agp_heap; - struct mem_block *fb_heap; - struct mem_block *fb_nomap_heap; - struct mem_block *ramin_heap; - struct mem_block *pci_heap; - - /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */ - uint32_t ctx_table_size; - struct nouveau_gpuobj_ref *ctx_table; - - struct nouveau_config config; - - struct list_head gpuobj_list; - - struct nouveau_suspend_resume { - uint32_t fifo_mode; - uint32_t graph_ctx_control; - uint32_t graph_state; - uint32_t *ramin_copy; - uint64_t ramin_size; - } susres; - struct backlight_device *backlight; -}; - -#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \ - struct drm_nouveau_private *nv = dev->dev_private; \ - if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \ - DRM_ERROR("called without init\n"); \ - return -EINVAL; \ - } \ -} while(0) - -#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id,cl,ch) do { \ - struct drm_nouveau_private *nv = dev->dev_private; \ - if (!nouveau_fifo_owner(dev, (cl), (id))) { \ - DRM_ERROR("pid %d doesn't own channel %d\n", \ - DRM_CURRENTPID, (id)); \ - return -EPERM; \ - } \ - (ch) = nv->fifos[(id)]; \ -} while(0) - -/* nouveau_state.c */ -extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); -extern int nouveau_load(struct drm_device *, unsigned long flags); -extern int nouveau_firstopen(struct drm_device *); -extern void nouveau_lastclose(struct drm_device *); -extern int nouveau_unload(struct drm_device *); -extern int nouveau_ioctl_getparam(struct drm_device *, void *data, - struct drm_file *); -extern int nouveau_ioctl_setparam(struct drm_device *, void *data, - struct drm_file *); -extern void nouveau_wait_for_idle(struct drm_device *); -extern int nouveau_card_init(struct drm_device *); -extern int nouveau_ioctl_card_init(struct drm_device *, void *data, - struct drm_file *); -extern int nouveau_ioctl_suspend(struct drm_device *, void *data, - struct drm_file *); -extern int nouveau_ioctl_resume(struct drm_device *, void *data, - struct drm_file *); - -/* nouveau_mem.c */ -extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start, - uint64_t size); -extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *, - uint64_t size, int align2, - struct drm_file *, int tail); -extern void nouveau_mem_takedown(struct mem_block **heap); -extern void nouveau_mem_free_block(struct mem_block *); -extern uint64_t nouveau_mem_fb_amount(struct drm_device *); -extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap); -extern int nouveau_ioctl_mem_alloc(struct drm_device *, void *data, - struct drm_file *); -extern int nouveau_ioctl_mem_free(struct drm_device *, void *data, - struct drm_file *); -extern int nouveau_ioctl_mem_tile(struct drm_device *, void *data, - struct drm_file *); -extern struct mem_block* nouveau_mem_alloc(struct drm_device *, - int alignment, uint64_t size, - int flags, struct drm_file *); -extern void nouveau_mem_free(struct drm_device *dev, struct mem_block*); -extern int nouveau_mem_init(struct drm_device *); -extern int nouveau_mem_init_ttm(struct drm_device *); -extern void nouveau_mem_close(struct drm_device *); - -/* nouveau_notifier.c */ -extern int nouveau_notifier_init_channel(struct nouveau_channel *); -extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); -extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, - int cout, uint32_t *offset); -extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, - struct drm_file *); -extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, - struct drm_file *); - -/* nouveau_fifo.c */ -extern int nouveau_fifo_init(struct drm_device *); -extern int nouveau_fifo_ctx_size(struct drm_device *); -extern void nouveau_fifo_cleanup(struct drm_device *, struct drm_file *); -extern int nouveau_fifo_owner(struct drm_device *, struct drm_file *, - int channel); -extern int nouveau_fifo_alloc(struct drm_device *dev, - struct nouveau_channel **chan, - struct drm_file *file_priv, - struct mem_block *pushbuf, - uint32_t fb_ctxdma, uint32_t tt_ctxdma); -extern void nouveau_fifo_free(struct nouveau_channel *); -extern int nouveau_channel_idle(struct nouveau_channel *chan); - -/* nouveau_object.c */ -extern int nouveau_gpuobj_early_init(struct drm_device *); -extern int nouveau_gpuobj_init(struct drm_device *); -extern void nouveau_gpuobj_takedown(struct drm_device *); -extern void nouveau_gpuobj_late_takedown(struct drm_device *); -extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, - uint32_t vram_h, uint32_t tt_h); -extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); -extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, - int size, int align, uint32_t flags, - struct nouveau_gpuobj **); -extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **); -extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *, - uint32_t handle, struct nouveau_gpuobj *, - struct nouveau_gpuobj_ref **); -extern int nouveau_gpuobj_ref_del(struct drm_device *, - struct nouveau_gpuobj_ref **); -extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle, - struct nouveau_gpuobj_ref **ref_ret); -extern int nouveau_gpuobj_new_ref(struct drm_device *, - struct nouveau_channel *alloc_chan, - struct nouveau_channel *ref_chan, - uint32_t handle, int size, int align, - uint32_t flags, struct nouveau_gpuobj_ref **); -extern int nouveau_gpuobj_new_fake(struct drm_device *, - uint32_t p_offset, uint32_t b_offset, - uint32_t size, uint32_t flags, - struct nouveau_gpuobj **, - struct nouveau_gpuobj_ref**); -extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, - uint64_t offset, uint64_t size, int access, - int target, struct nouveau_gpuobj **); -extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, - uint64_t offset, uint64_t size, - int access, struct nouveau_gpuobj **, - uint32_t *o_ret); -extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, - struct nouveau_gpuobj **); -extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, - struct drm_file *); -extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, - struct drm_file *); - -/* nouveau_irq.c */ -extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); -extern void nouveau_irq_preinstall(struct drm_device *); -extern int nouveau_irq_postinstall(struct drm_device *); -extern void nouveau_irq_uninstall(struct drm_device *); - -/* nouveau_sgdma.c */ -extern int nouveau_sgdma_init(struct drm_device *); -extern void nouveau_sgdma_takedown(struct drm_device *); -extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, - uint32_t *page); -extern struct drm_ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); -extern int nouveau_sgdma_nottm_hack_init(struct drm_device *); -extern void nouveau_sgdma_nottm_hack_takedown(struct drm_device *); - -/* nouveau_dma.c */ -extern int nouveau_dma_channel_init(struct drm_device *); -extern void nouveau_dma_channel_takedown(struct drm_device *); -extern int nouveau_dma_wait(struct drm_device *, int size); - -/* nouveau_backlight.c */ -extern int nouveau_backlight_init(struct drm_device *); -extern void nouveau_backlight_exit(struct drm_device *); - -/* nv04_fb.c */ -extern int nv04_fb_init(struct drm_device *); -extern void nv04_fb_takedown(struct drm_device *); - -/* nv10_fb.c */ -extern int nv10_fb_init(struct drm_device *); -extern void nv10_fb_takedown(struct drm_device *); - -/* nv40_fb.c */ -extern int nv40_fb_init(struct drm_device *); -extern void nv40_fb_takedown(struct drm_device *); - -/* nv04_fifo.c */ -extern int nv04_fifo_channel_id(struct drm_device *); -extern int nv04_fifo_create_context(struct nouveau_channel *); -extern void nv04_fifo_destroy_context(struct nouveau_channel *); -extern int nv04_fifo_load_context(struct nouveau_channel *); -extern int nv04_fifo_save_context(struct nouveau_channel *); - -/* nv10_fifo.c */ -extern int nv10_fifo_channel_id(struct drm_device *); -extern int nv10_fifo_create_context(struct nouveau_channel *); -extern void nv10_fifo_destroy_context(struct nouveau_channel *); -extern int nv10_fifo_load_context(struct nouveau_channel *); -extern int nv10_fifo_save_context(struct nouveau_channel *); - -/* nv40_fifo.c */ -extern int nv40_fifo_init(struct drm_device *); -extern int nv40_fifo_create_context(struct nouveau_channel *); -extern void nv40_fifo_destroy_context(struct nouveau_channel *); -extern int nv40_fifo_load_context(struct nouveau_channel *); -extern int nv40_fifo_save_context(struct nouveau_channel *); - -/* nv50_fifo.c */ -extern int nv50_fifo_init(struct drm_device *); -extern void nv50_fifo_takedown(struct drm_device *); -extern int nv50_fifo_channel_id(struct drm_device *); -extern int nv50_fifo_create_context(struct nouveau_channel *); -extern void nv50_fifo_destroy_context(struct nouveau_channel *); -extern int nv50_fifo_load_context(struct nouveau_channel *); -extern int nv50_fifo_save_context(struct nouveau_channel *); - -/* nv04_graph.c */ -extern void nouveau_nv04_context_switch(struct drm_device *); -extern int nv04_graph_init(struct drm_device *); -extern void nv04_graph_takedown(struct drm_device *); -extern int nv04_graph_create_context(struct nouveau_channel *); -extern void nv04_graph_destroy_context(struct nouveau_channel *); -extern int nv04_graph_load_context(struct nouveau_channel *); -extern int nv04_graph_save_context(struct nouveau_channel *); - -/* nv10_graph.c */ -extern void nouveau_nv10_context_switch(struct drm_device *); -extern int nv10_graph_init(struct drm_device *); -extern void nv10_graph_takedown(struct drm_device *); -extern int nv10_graph_create_context(struct nouveau_channel *); -extern void nv10_graph_destroy_context(struct nouveau_channel *); -extern int nv10_graph_load_context(struct nouveau_channel *); -extern int nv10_graph_save_context(struct nouveau_channel *); - -/* nv20_graph.c */ -extern int nv20_graph_create_context(struct nouveau_channel *); -extern void nv20_graph_destroy_context(struct nouveau_channel *); -extern int nv20_graph_load_context(struct nouveau_channel *); -extern int nv20_graph_save_context(struct nouveau_channel *); -extern int nv20_graph_init(struct drm_device *); -extern void nv20_graph_takedown(struct drm_device *); -extern int nv30_graph_init(struct drm_device *); - -/* nv40_graph.c */ -extern int nv40_graph_init(struct drm_device *); -extern void nv40_graph_takedown(struct drm_device *); -extern int nv40_graph_create_context(struct nouveau_channel *); -extern void nv40_graph_destroy_context(struct nouveau_channel *); -extern int nv40_graph_load_context(struct nouveau_channel *); -extern int nv40_graph_save_context(struct nouveau_channel *); - -/* nv50_graph.c */ -extern int nv50_graph_init(struct drm_device *); -extern void nv50_graph_takedown(struct drm_device *); -extern int nv50_graph_create_context(struct nouveau_channel *); -extern void nv50_graph_destroy_context(struct nouveau_channel *); -extern int nv50_graph_load_context(struct nouveau_channel *); -extern int nv50_graph_save_context(struct nouveau_channel *); - -/* nv04_instmem.c */ -extern int nv04_instmem_init(struct drm_device *); -extern void nv04_instmem_takedown(struct drm_device *); -extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, - uint32_t *size); -extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); -extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); -extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); - -/* nv50_instmem.c */ -extern int nv50_instmem_init(struct drm_device *); -extern void nv50_instmem_takedown(struct drm_device *); -extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, - uint32_t *size); -extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); -extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); -extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); - -/* nv04_mc.c */ -extern int nv04_mc_init(struct drm_device *); -extern void nv04_mc_takedown(struct drm_device *); - -/* nv40_mc.c */ -extern int nv40_mc_init(struct drm_device *); -extern void nv40_mc_takedown(struct drm_device *); - -/* nv50_mc.c */ -extern int nv50_mc_init(struct drm_device *); -extern void nv50_mc_takedown(struct drm_device *); - -/* nv04_timer.c */ -extern int nv04_timer_init(struct drm_device *); -extern uint64_t nv04_timer_read(struct drm_device *); -extern void nv04_timer_takedown(struct drm_device *); - -extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, - unsigned long arg); - -/* nouveau_buffer.c */ -extern struct drm_bo_driver nouveau_bo_driver; - -/* nouveau_fence.c */ -extern struct drm_fence_driver nouveau_fence_driver; -extern void nouveau_fence_handler(struct drm_device *dev, int channel); - -#if defined(__powerpc__) -#define NV_READ(reg) in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) ) -#define NV_WRITE(reg,val) out_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) , (val) ) -#else -#define NV_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) -#define NV_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) -#endif - -/* PRAMIN access */ -#if defined(__powerpc__) -#define NV_RI32(o) in_be32((void __iomem *)(dev_priv->ramin)->handle+(o)) -#define NV_WI32(o,v) out_be32((void __iomem*)(dev_priv->ramin)->handle+(o), (v)) -#else -#define NV_RI32(o) DRM_READ32(dev_priv->ramin, (o)) -#define NV_WI32(o,v) DRM_WRITE32(dev_priv->ramin, (o), (v)) -#endif - -#define INSTANCE_RD(o,i) NV_RI32((o)->im_pramin->start + ((i)<<2)) -#define INSTANCE_WR(o,i,v) NV_WI32((o)->im_pramin->start + ((i)<<2), (v)) - -#endif /* __NOUVEAU_DRV_H__ */ diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c deleted file mode 100644 index 114ed29b..00000000 --- a/shared-core/nouveau_fifo.c +++ /dev/null @@ -1,602 +0,0 @@ -/* - * Copyright 2005-2006 Stephane Marchesin - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" -#include "nouveau_drm.h" - - -/* returns the size of fifo context */ -int nouveau_fifo_ctx_size(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv=dev->dev_private; - - if (dev_priv->card_type >= NV_40) - return 128; - else if (dev_priv->card_type >= NV_17) - return 64; - else - return 32; -} - -/*********************************** - * functions doing the actual work - ***********************************/ - -static int nouveau_fifo_instmem_configure(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - NV_WRITE(NV03_PFIFO_RAMHT, - (0x03 << 24) /* search 128 */ | - ((dev_priv->ramht_bits - 9) << 16) | - (dev_priv->ramht_offset >> 8) - ); - - NV_WRITE(NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8); - - switch(dev_priv->card_type) - { - case NV_40: - switch (dev_priv->chipset) { - case 0x47: - case 0x49: - case 0x4b: - NV_WRITE(0x2230, 1); - break; - default: - break; - } - NV_WRITE(NV40_PFIFO_RAMFC, 0x30002); - break; - case NV_44: - NV_WRITE(NV40_PFIFO_RAMFC, ((nouveau_mem_fb_amount(dev)-512*1024+dev_priv->ramfc_offset)>>16) | - (2 << 16)); - break; - case NV_30: - case NV_20: - case NV_17: - NV_WRITE(NV03_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) | - (1 << 16) /* 64 Bytes entry*/); - /* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */ - break; - case NV_11: - case NV_10: - case NV_04: - NV_WRITE(NV03_PFIFO_RAMFC, dev_priv->ramfc_offset>>8); - break; - } - - return 0; -} - -int nouveau_fifo_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int ret; - - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & - ~NV_PMC_ENABLE_PFIFO); - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | - NV_PMC_ENABLE_PFIFO); - - /* Enable PFIFO error reporting */ - NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF); - NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF); - - NV_WRITE(NV03_PFIFO_CACHES, 0x00000000); - - ret = nouveau_fifo_instmem_configure(dev); - if (ret) { - DRM_ERROR("Failed to configure instance memory\n"); - return ret; - } - - /* FIXME remove all the stuff that's done in nouveau_fifo_alloc */ - - DRM_DEBUG("Setting defaults for remaining PFIFO regs\n"); - - /* All channels into PIO mode */ - NV_WRITE(NV04_PFIFO_MODE, 0x00000000); - - NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000); - NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000); - /* Channel 0 active, PIO mode */ - NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00000000); - /* PUT and GET to 0 */ - NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0x00000000); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, 0x00000000); - /* No cmdbuf object */ - NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, 0x00000000); - NV_WRITE(NV03_PFIFO_CACHE0_PUSH0, 0x00000000); - NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x00000000); - NV_WRITE(NV04_PFIFO_SIZE, 0x0000FFFF); - NV_WRITE(NV04_PFIFO_CACHE1_HASH, 0x0000FFFF); - NV_WRITE(NV04_PFIFO_CACHE0_PULL1, 0x00000001); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, 0x00000000); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000); - NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, 0x00000000); - - NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 | -#ifdef __BIG_ENDIAN - NV_PFIFO_CACHE1_BIG_ENDIAN | -#endif - 0x00000000); - - NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001); - NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001); - NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001); - NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001); - - /* FIXME on NV04 */ - if (dev_priv->card_type >= NV_10) { - NV_WRITE(NV10_PGRAPH_CTX_USER, 0x0); - NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ ); - if (dev_priv->card_type >= NV_40) - NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x00002001); - else - NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10110000); - } else { - NV_WRITE(NV04_PGRAPH_CTX_USER, 0x0); - NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ ); - NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10110000); - } - - NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x001fffff); - NV_WRITE(NV03_PFIFO_CACHES, 0x00000001); - return 0; -} - -static int -nouveau_fifo_pushbuf_ctxdma_init(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct mem_block *pb = chan->pushbuf_mem; - struct nouveau_gpuobj *pushbuf = NULL; - int ret; - - if (pb->flags & NOUVEAU_MEM_AGP) { - ret = nouveau_gpuobj_gart_dma_new(chan, pb->start, pb->size, - NV_DMA_ACCESS_RO, - &pushbuf, - &chan->pushbuf_base); - } else - if (pb->flags & NOUVEAU_MEM_PCI) { - ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, - pb->start, pb->size, - NV_DMA_ACCESS_RO, - NV_DMA_TARGET_PCI_NONLINEAR, - &pushbuf); - chan->pushbuf_base = 0; - } else if (dev_priv->card_type != NV_04) { - ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, - pb->start, pb->size, - NV_DMA_ACCESS_RO, - NV_DMA_TARGET_VIDMEM, &pushbuf); - chan->pushbuf_base = 0; - } else { - /* NV04 cmdbuf hack, from original ddx.. not sure of it's - * exact reason for existing :) PCI access to cmdbuf in - * VRAM. - */ - ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, - pb->start + - drm_get_resource_start(dev, 1), - pb->size, NV_DMA_ACCESS_RO, - NV_DMA_TARGET_PCI, &pushbuf); - chan->pushbuf_base = 0; - } - - if ((ret = nouveau_gpuobj_ref_add(dev, chan, 0, pushbuf, - &chan->pushbuf))) { - DRM_ERROR("Error referencing push buffer ctxdma: %d\n", ret); - if (pushbuf != dev_priv->gart_info.sg_ctxdma) - nouveau_gpuobj_del(dev, &pushbuf); - return ret; - } - - return 0; -} - -static struct mem_block * -nouveau_fifo_user_pushbuf_alloc(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_config *config = &dev_priv->config; - struct mem_block *pb; - int pb_min_size = max(NV03_FIFO_SIZE,PAGE_SIZE); - - /* Defaults for unconfigured values */ - if (!config->cmdbuf.location) - config->cmdbuf.location = NOUVEAU_MEM_FB; - if (!config->cmdbuf.size || config->cmdbuf.size < pb_min_size) - config->cmdbuf.size = pb_min_size; - - pb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size, - config->cmdbuf.location | NOUVEAU_MEM_MAPPED, - (struct drm_file *)-2); - if (!pb) - DRM_ERROR("Couldn't allocate DMA push buffer.\n"); - - return pb; -} - -/* allocates and initializes a fifo for user space consumption */ -int -nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, - struct drm_file *file_priv, struct mem_block *pushbuf, - uint32_t vram_handle, uint32_t tt_handle) -{ - int ret; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine *engine = &dev_priv->Engine; - struct nouveau_channel *chan; - int channel; - - /* - * Alright, here is the full story - * Nvidia cards have multiple hw fifo contexts (praise them for that, - * no complicated crash-prone context switches) - * We allocate a new context for each app and let it write to it directly - * (woo, full userspace command submission !) - * When there are no more contexts, you lost - */ - for (channel = 0; channel < engine->fifo.channels; channel++) { - if (dev_priv->fifos[channel] == NULL) - break; - } - - /* no more fifos. you lost. */ - if (channel == engine->fifo.channels) - return -EINVAL; - - dev_priv->fifos[channel] = drm_calloc(1, sizeof(struct nouveau_channel), - DRM_MEM_DRIVER); - if (!dev_priv->fifos[channel]) - return -ENOMEM; - dev_priv->fifo_alloc_count++; - chan = dev_priv->fifos[channel]; - chan->dev = dev; - chan->id = channel; - chan->file_priv = file_priv; - chan->pushbuf_mem = pushbuf; - - DRM_INFO("Allocating FIFO number %d\n", channel); - - /* Locate channel's user control regs */ - if (dev_priv->card_type < NV_40) { - chan->user = NV03_USER(channel); - chan->user_size = NV03_USER_SIZE; - chan->put = NV03_USER_DMA_PUT(channel); - chan->get = NV03_USER_DMA_GET(channel); - chan->ref_cnt = NV03_USER_REF_CNT(channel); - } else - if (dev_priv->card_type < NV_50) { - chan->user = NV40_USER(channel); - chan->user_size = NV40_USER_SIZE; - chan->put = NV40_USER_DMA_PUT(channel); - chan->get = NV40_USER_DMA_GET(channel); - chan->ref_cnt = NV40_USER_REF_CNT(channel); - } else { - chan->user = NV50_USER(channel); - chan->user_size = NV50_USER_SIZE; - chan->put = NV50_USER_DMA_PUT(channel); - chan->get = NV50_USER_DMA_GET(channel); - chan->ref_cnt = NV50_USER_REF_CNT(channel); - } - - /* Allocate space for per-channel fixed notifier memory */ - ret = nouveau_notifier_init_channel(chan); - if (ret) { - nouveau_fifo_free(chan); - return ret; - } - - /* Setup channel's default objects */ - ret = nouveau_gpuobj_channel_init(chan, vram_handle, tt_handle); - if (ret) { - nouveau_fifo_free(chan); - return ret; - } - - /* Create a dma object for the push buffer */ - ret = nouveau_fifo_pushbuf_ctxdma_init(chan); - if (ret) { - nouveau_fifo_free(chan); - return ret; - } - - nouveau_wait_for_idle(dev); - - /* disable the fifo caches */ - NV_WRITE(NV03_PFIFO_CACHES, 0x00000000); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1)); - NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000); - NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000); - - /* Create a graphics context for new channel */ - ret = engine->graph.create_context(chan); - if (ret) { - nouveau_fifo_free(chan); - return ret; - } - - /* Construct inital RAMFC for new channel */ - ret = engine->fifo.create_context(chan); - if (ret) { - nouveau_fifo_free(chan); - return ret; - } - - /* setup channel's default get/put values - * XXX: quite possibly extremely pointless.. - */ - NV_WRITE(chan->get, chan->pushbuf_base); - NV_WRITE(chan->put, chan->pushbuf_base); - - /* If this is the first channel, setup PFIFO ourselves. For any - * other case, the GPU will handle this when it switches contexts. - */ - if (dev_priv->card_type < NV_50 && - dev_priv->fifo_alloc_count == 1) { - ret = engine->fifo.load_context(chan); - if (ret) { - nouveau_fifo_free(chan); - return ret; - } - - ret = engine->graph.load_context(chan); - if (ret) { - nouveau_fifo_free(chan); - return ret; - } - } - - NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, - NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) | 1); - NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001); - NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001); - NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001); - - /* reenable the fifo caches */ - NV_WRITE(NV03_PFIFO_CACHES, 1); - - DRM_INFO("%s: initialised FIFO %d\n", __func__, channel); - *chan_ret = chan; - return 0; -} - -int -nouveau_channel_idle(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine *engine = &dev_priv->Engine; - uint32_t caches; - int idle; - - caches = NV_READ(NV03_PFIFO_CACHES); - NV_WRITE(NV03_PFIFO_CACHES, caches & ~1); - - if (engine->fifo.channel_id(dev) != chan->id) { - struct nouveau_gpuobj *ramfc = chan->ramfc->gpuobj; - - if (INSTANCE_RD(ramfc, 0) != INSTANCE_RD(ramfc, 1)) - idle = 0; - else - idle = 1; - } else { - idle = (NV_READ(NV04_PFIFO_CACHE1_DMA_GET) == - NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); - } - - NV_WRITE(NV03_PFIFO_CACHES, caches); - return idle; -} - -/* stops a fifo */ -void nouveau_fifo_free(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine *engine = &dev_priv->Engine; - uint64_t t_start; - - DRM_INFO("%s: freeing fifo %d\n", __func__, chan->id); - - /* Give the channel a chance to idle, wait 2s (hopefully) */ - t_start = engine->timer.read(dev); - while (!nouveau_channel_idle(chan)) { - if (engine->timer.read(dev) - t_start > 2000000000ULL) { - DRM_ERROR("Failed to idle channel %d before destroy." - "Prepare for strangeness..\n", chan->id); - break; - } - } - - /*XXX: Maybe should wait for PGRAPH to finish with the stuff it fetched - * from CACHE1 too? - */ - - /* disable the fifo caches */ - NV_WRITE(NV03_PFIFO_CACHES, 0x00000000); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1)); - NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000); - NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000); - - // FIXME XXX needs more code - - engine->fifo.destroy_context(chan); - - /* Cleanup PGRAPH state */ - engine->graph.destroy_context(chan); - - /* reenable the fifo caches */ - NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, - NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) | 1); - NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001); - NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001); - NV_WRITE(NV03_PFIFO_CACHES, 0x00000001); - - /* Deallocate push buffer */ - nouveau_gpuobj_ref_del(dev, &chan->pushbuf); - if (chan->pushbuf_mem) { - nouveau_mem_free(dev, chan->pushbuf_mem); - chan->pushbuf_mem = NULL; - } - - /* Destroy objects belonging to the channel */ - nouveau_gpuobj_channel_takedown(chan); - - nouveau_notifier_takedown_channel(chan); - - dev_priv->fifos[chan->id] = NULL; - dev_priv->fifo_alloc_count--; - drm_free(chan, sizeof(*chan), DRM_MEM_DRIVER); -} - -/* cleanups all the fifos from file_priv */ -void nouveau_fifo_cleanup(struct drm_device *dev, struct drm_file *file_priv) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine *engine = &dev_priv->Engine; - int i; - - DRM_DEBUG("clearing FIFO enables from file_priv\n"); - for(i = 0; i < engine->fifo.channels; i++) { - struct nouveau_channel *chan = dev_priv->fifos[i]; - - if (chan && chan->file_priv == file_priv) - nouveau_fifo_free(chan); - } -} - -int -nouveau_fifo_owner(struct drm_device *dev, struct drm_file *file_priv, - int channel) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine *engine = &dev_priv->Engine; - - if (channel >= engine->fifo.channels) - return 0; - if (dev_priv->fifos[channel] == NULL) - return 0; - return (dev_priv->fifos[channel]->file_priv == file_priv); -} - -/*********************************** - * ioctls wrapping the functions - ***********************************/ - -static int nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct drm_nouveau_channel_alloc *init = data; - struct drm_map_list *entry; - struct nouveau_channel *chan; - struct mem_block *pushbuf; - int res; - - NOUVEAU_CHECK_INITIALISED_WITH_RETURN; - - if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0) - return -EINVAL; - - pushbuf = nouveau_fifo_user_pushbuf_alloc(dev); - if (!pushbuf) - return -ENOMEM; - - res = nouveau_fifo_alloc(dev, &chan, file_priv, pushbuf, - init->fb_ctxdma_handle, - init->tt_ctxdma_handle); - if (res) - return res; - init->channel = chan->id; - init->put_base = chan->pushbuf_base; - - /* make the fifo available to user space */ - /* first, the fifo control regs */ - init->ctrl = dev_priv->mmio->offset + chan->user; - init->ctrl_size = chan->user_size; - res = drm_addmap(dev, init->ctrl, init->ctrl_size, _DRM_REGISTERS, - 0, &chan->regs); - if (res != 0) - return res; - - entry = drm_find_matching_map(dev, chan->regs); - if (!entry) - return -EINVAL; - init->ctrl = entry->user_token; - - /* pass back FIFO map info to the caller */ - init->cmdbuf = chan->pushbuf_mem->map_handle; - init->cmdbuf_size = chan->pushbuf_mem->size; - - /* and the notifier block */ - init->notifier = chan->notifier_block->map_handle; - init->notifier_size = chan->notifier_block->size; - - return 0; -} - -static int nouveau_ioctl_fifo_free(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_nouveau_channel_free *cfree = data; - struct nouveau_channel *chan; - - NOUVEAU_CHECK_INITIALISED_WITH_RETURN; - NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(cfree->channel, file_priv, chan); - - nouveau_fifo_free(chan); - return 0; -} - -/*********************************** - * finally, the ioctl table - ***********************************/ - -struct drm_ioctl_desc nouveau_ioctls[] = { - DRM_IOCTL_DEF(DRM_NOUVEAU_CARD_INIT, nouveau_ioctl_card_init, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_MEM_ALLOC, nouveau_ioctl_mem_alloc, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_MEM_FREE, nouveau_ioctl_mem_free, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_MEM_TILE, nouveau_ioctl_mem_tile, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_SUSPEND, nouveau_ioctl_suspend, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_RESUME, nouveau_ioctl_resume, DRM_AUTH), -}; - -int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls); diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c deleted file mode 100644 index f4eb72b8..00000000 --- a/shared-core/nouveau_irq.c +++ /dev/null @@ -1,588 +0,0 @@ -/* - * Copyright (C) 2006 Ben Skeggs. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/* - * Authors: - * Ben Skeggs - */ - -#include "drmP.h" -#include "drm.h" -#include "nouveau_drm.h" -#include "nouveau_drv.h" -#include "nouveau_reg.h" -#include "nouveau_swmthd.h" - -void -nouveau_irq_preinstall(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - /* Master disable */ - NV_WRITE(NV03_PMC_INTR_EN_0, 0); -} - -int -nouveau_irq_postinstall(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - /* Master enable */ - NV_WRITE(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE); - - return 0; -} - -void -nouveau_irq_uninstall(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - /* Master disable */ - NV_WRITE(NV03_PMC_INTR_EN_0, 0); -} - -static void -nouveau_fifo_irq_handler(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine *engine = &dev_priv->Engine; - uint32_t status, reassign; - - reassign = NV_READ(NV03_PFIFO_CACHES) & 1; - while ((status = NV_READ(NV03_PFIFO_INTR_0))) { - uint32_t chid, get; - - NV_WRITE(NV03_PFIFO_CACHES, 0); - - chid = engine->fifo.channel_id(dev); - get = NV_READ(NV03_PFIFO_CACHE1_GET); - - if (status & NV_PFIFO_INTR_CACHE_ERROR) { - uint32_t mthd, data; - int ptr; - - ptr = get >> 2; - if (dev_priv->card_type < NV_40) { - mthd = NV_READ(NV04_PFIFO_CACHE1_METHOD(ptr)); - data = NV_READ(NV04_PFIFO_CACHE1_DATA(ptr)); - } else { - mthd = NV_READ(NV40_PFIFO_CACHE1_METHOD(ptr)); - data = NV_READ(NV40_PFIFO_CACHE1_DATA(ptr)); - } - - DRM_INFO("PFIFO_CACHE_ERROR - " - "Ch %d/%d Mthd 0x%04x Data 0x%08x\n", - chid, (mthd >> 13) & 7, mthd & 0x1ffc, data); - - NV_WRITE(NV03_PFIFO_CACHE1_GET, get + 4); - NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 1); - - status &= ~NV_PFIFO_INTR_CACHE_ERROR; - NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); - } - - if (status & NV_PFIFO_INTR_DMA_PUSHER) { - DRM_INFO("PFIFO_DMA_PUSHER - Ch %d\n", chid); - - status &= ~NV_PFIFO_INTR_DMA_PUSHER; - NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_DMA_PUSHER); - - NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000); - if (NV_READ(NV04_PFIFO_CACHE1_DMA_PUT) != get) - NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, get + 4); - } - - if (status) { - DRM_INFO("Unhandled PFIFO_INTR - 0x%08x\n", status); - NV_WRITE(NV03_PFIFO_INTR_0, status); - NV_WRITE(NV03_PMC_INTR_EN_0, 0); - } - - NV_WRITE(NV03_PFIFO_CACHES, reassign); - } - - NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING); -} - -struct nouveau_bitfield_names { - uint32_t mask; - const char * name; -}; - -static struct nouveau_bitfield_names nouveau_nstatus_names[] = -{ - { NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" }, - { NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" }, - { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" }, - { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" } -}; - -static struct nouveau_bitfield_names nouveau_nstatus_names_nv10[] = -{ - { NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" }, - { NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" }, - { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" }, - { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" } -}; - -static struct nouveau_bitfield_names nouveau_nsource_names[] = -{ - { NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" }, - { NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" }, - { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" }, - { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" }, - { NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" }, - { NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" }, - { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" }, - { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" }, - { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" }, - { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" }, - { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" }, - { NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" }, - { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" }, - { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" }, - { NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" }, - { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" }, - { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" }, - { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" }, - { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" }, -}; - -static void -nouveau_print_bitfield_names(uint32_t value, - const struct nouveau_bitfield_names *namelist, - const int namelist_len) -{ - int i; - for(i=0; idev_private; - uint32_t inst; - int i; - - if (dev_priv->card_type < NV_40) - return dev_priv->Engine.fifo.channels; - else - if (dev_priv->card_type < NV_50) - inst = (NV_READ(0x40032c) & 0xfffff) << 4; - else - inst = NV_READ(0x40032c) & 0xfffff; - - for (i = 0; i < dev_priv->Engine.fifo.channels; i++) { - struct nouveau_channel *chan = dev_priv->fifos[i]; - - if (!chan || !chan->ramin_grctx) - continue; - - if (dev_priv->card_type < NV_50) { - if (inst == chan->ramin_grctx->instance) - break; - } else { - if (inst == INSTANCE_RD(chan->ramin_grctx->gpuobj, 0)) - break; - } - } - - return i; -} - -static int -nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine *engine = &dev_priv->Engine; - int channel; - - if (dev_priv->card_type < NV_10) - channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf; - else - if (dev_priv->card_type < NV_40) - channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f; - else - channel = nouveau_graph_chid_from_grctx(dev); - - if (channel >= engine->fifo.channels || !dev_priv->fifos[channel]) { - DRM_ERROR("AIII, invalid/inactive channel id %d\n", channel); - return -EINVAL; - } - - *channel_ret = channel; - return 0; -} - -struct nouveau_pgraph_trap { - int channel; - int class; - int subc, mthd, size; - uint32_t data, data2; - uint32_t nsource, nstatus; -}; - -static void -nouveau_graph_trap_info(struct drm_device *dev, - struct nouveau_pgraph_trap *trap) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t address; - - trap->nsource = trap->nstatus = 0; - if (dev_priv->card_type < NV_50) { - trap->nsource = NV_READ(NV03_PGRAPH_NSOURCE); - trap->nstatus = NV_READ(NV03_PGRAPH_NSTATUS); - } - - if (nouveau_graph_trapped_channel(dev, &trap->channel)) - trap->channel = -1; - address = NV_READ(NV04_PGRAPH_TRAPPED_ADDR); - - trap->mthd = address & 0x1FFC; - trap->data = NV_READ(NV04_PGRAPH_TRAPPED_DATA); - if (dev_priv->card_type < NV_10) { - trap->subc = (address >> 13) & 0x7; - } else { - trap->subc = (address >> 16) & 0x7; - trap->data2 = NV_READ(NV10_PGRAPH_TRAPPED_DATA_HIGH); - } - - if (dev_priv->card_type < NV_10) { - trap->class = NV_READ(0x400180 + trap->subc*4) & 0xFF; - } else if (dev_priv->card_type < NV_40) { - trap->class = NV_READ(0x400160 + trap->subc*4) & 0xFFF; - } else if (dev_priv->card_type < NV_50) { - trap->class = NV_READ(0x400160 + trap->subc*4) & 0xFFFF; - } else { - trap->class = NV_READ(0x400814); - } -} - -static void -nouveau_graph_dump_trap_info(struct drm_device *dev, const char *id, - struct nouveau_pgraph_trap *trap) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t nsource = trap->nsource, nstatus = trap->nstatus; - - DRM_INFO("%s - nSource:", id); - nouveau_print_bitfield_names(nsource, nouveau_nsource_names, - ARRAY_SIZE(nouveau_nsource_names)); - printk(", nStatus:"); - if (dev_priv->card_type < NV_10) - nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names, - ARRAY_SIZE(nouveau_nstatus_names)); - else - nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names_nv10, - ARRAY_SIZE(nouveau_nstatus_names_nv10)); - printk("\n"); - - DRM_INFO("%s - Ch %d/%d Class 0x%04x Mthd 0x%04x Data 0x%08x:0x%08x\n", - id, trap->channel, trap->subc, trap->class, trap->mthd, - trap->data2, trap->data); -} - -static inline void -nouveau_pgraph_intr_notify(struct drm_device *dev, uint32_t nsource) -{ - struct nouveau_pgraph_trap trap; - int unhandled = 0; - - nouveau_graph_trap_info(dev, &trap); - - if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { - /* NV4 (nvidia TNT 1) reports software methods with - * PGRAPH NOTIFY ILLEGAL_MTHD - */ - DRM_DEBUG("Got NV04 software method method %x for class %#x\n", - trap.mthd, trap.class); - - if (nouveau_sw_method_execute(dev, trap.class, trap.mthd)) { - DRM_ERROR("Unable to execute NV04 software method %x " - "for object class %x. Please report.\n", - trap.mthd, trap.class); - unhandled = 1; - } - } else { - unhandled = 1; - } - - if (unhandled) - nouveau_graph_dump_trap_info(dev, "PGRAPH_NOTIFY", &trap); -} - -static inline void -nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource) -{ - struct nouveau_pgraph_trap trap; - int unhandled = 0; - - nouveau_graph_trap_info(dev, &trap); - trap.nsource = nsource; - - if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { - if (trap.channel >= 0 && trap.mthd == 0x0150) { - nouveau_fence_handler(dev, trap.channel); - } else - if (nouveau_sw_method_execute(dev, trap.class, trap.mthd)) { - unhandled = 1; - } - } else { - unhandled = 1; - } - - if (unhandled) - nouveau_graph_dump_trap_info(dev, "PGRAPH_ERROR", &trap); -} - -static inline void -nouveau_pgraph_intr_context_switch(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine *engine = &dev_priv->Engine; - uint32_t chid; - - chid = engine->fifo.channel_id(dev); - DRM_DEBUG("PGRAPH context switch interrupt channel %x\n", chid); - - switch(dev_priv->card_type) { - case NV_04: - case NV_05: - nouveau_nv04_context_switch(dev); - break; - case NV_10: - case NV_11: - case NV_17: - nouveau_nv10_context_switch(dev); - break; - default: - DRM_ERROR("Context switch not implemented\n"); - break; - } -} - -static void -nouveau_pgraph_irq_handler(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t status; - - while ((status = NV_READ(NV03_PGRAPH_INTR))) { - uint32_t nsource = NV_READ(NV03_PGRAPH_NSOURCE); - - if (status & NV_PGRAPH_INTR_NOTIFY) { - nouveau_pgraph_intr_notify(dev, nsource); - - status &= ~NV_PGRAPH_INTR_NOTIFY; - NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY); - } - - if (status & NV_PGRAPH_INTR_ERROR) { - nouveau_pgraph_intr_error(dev, nsource); - - status &= ~NV_PGRAPH_INTR_ERROR; - NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR); - } - - if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) { - nouveau_pgraph_intr_context_switch(dev); - - status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; - NV_WRITE(NV03_PGRAPH_INTR, - NV_PGRAPH_INTR_CONTEXT_SWITCH); - } - - if (status) { - DRM_INFO("Unhandled PGRAPH_INTR - 0x%08x\n", status); - NV_WRITE(NV03_PGRAPH_INTR, status); - } - - if ((NV_READ(NV04_PGRAPH_FIFO) & (1 << 0)) == 0) - NV_WRITE(NV04_PGRAPH_FIFO, 1); - } - - NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING); -} - -static void -nv50_pgraph_irq_handler(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t status, nsource; - - status = NV_READ(NV03_PGRAPH_INTR); - nsource = NV_READ(NV03_PGRAPH_NSOURCE); - - if (status & 0x00000020) { - nouveau_pgraph_intr_error(dev, - NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD); - - status &= ~0x00000020; - NV_WRITE(NV03_PGRAPH_INTR, 0x00000020); - } - - if (status & 0x00100000) { - nouveau_pgraph_intr_error(dev, - NV03_PGRAPH_NSOURCE_DATA_ERROR); - - status &= ~0x00100000; - NV_WRITE(NV03_PGRAPH_INTR, 0x00100000); - } - - if (status & 0x00200000) { - int r; - - nouveau_pgraph_intr_error(dev, nsource | - NV03_PGRAPH_NSOURCE_PROTECTION_ERROR); - - DRM_ERROR("magic set 1:\n"); - for (r = 0x408900; r <= 0x408910; r += 4) - DRM_ERROR("\t0x%08x: 0x%08x\n", r, NV_READ(r)); - NV_WRITE(0x408900, NV_READ(0x408904) | 0xc0000000); - for (r = 0x408e08; r <= 0x408e24; r += 4) - DRM_ERROR("\t0x%08x: 0x%08x\n", r, NV_READ(r)); - NV_WRITE(0x408e08, NV_READ(0x408e08) | 0xc0000000); - - DRM_ERROR("magic set 2:\n"); - for (r = 0x409900; r <= 0x409910; r += 4) - DRM_ERROR("\t0x%08x: 0x%08x\n", r, NV_READ(r)); - NV_WRITE(0x409900, NV_READ(0x409904) | 0xc0000000); - for (r = 0x409e08; r <= 0x409e24; r += 4) - DRM_ERROR("\t0x%08x: 0x%08x\n", r, NV_READ(r)); - NV_WRITE(0x409e08, NV_READ(0x409e08) | 0xc0000000); - - status &= ~0x00200000; - NV_WRITE(NV03_PGRAPH_NSOURCE, nsource); - NV_WRITE(NV03_PGRAPH_INTR, 0x00200000); - } - - if (status) { - DRM_INFO("Unhandled PGRAPH_INTR - 0x%08x\n", status); - NV_WRITE(NV03_PGRAPH_INTR, status); - } - - { - const int isb = (1 << 16) | (1 << 0); - - if ((NV_READ(0x400500) & isb) != isb) - NV_WRITE(0x400500, NV_READ(0x400500) | isb); - } - - NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING); -} - -static void -nouveau_crtc_irq_handler(struct drm_device *dev, int crtc) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - if (crtc&1) { - NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK); - } - - if (crtc&2) { - NV_WRITE(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK); - } -} - -static void -nouveau_nv50_display_irq_handler(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t val = NV_READ(NV50_DISPLAY_SUPERVISOR); - - DRM_INFO("NV50_DISPLAY_INTR - 0x%08X\n", val); - - NV_WRITE(NV50_DISPLAY_SUPERVISOR, val); -} - -static void -nouveau_nv50_i2c_irq_handler(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - DRM_INFO("NV50_I2C_INTR - 0x%08X\n", NV_READ(NV50_I2C_CONTROLLER)); - - /* This seems to be the way to acknowledge an interrupt. */ - NV_WRITE(NV50_I2C_CONTROLLER, 0x7FFF7FFF); -} - -irqreturn_t -nouveau_irq_handler(DRM_IRQ_ARGS) -{ - struct drm_device *dev = (struct drm_device*)arg; - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t status; - - status = NV_READ(NV03_PMC_INTR_0); - if (!status) - return IRQ_NONE; - - if (status & NV_PMC_INTR_0_PFIFO_PENDING) { - nouveau_fifo_irq_handler(dev); - status &= ~NV_PMC_INTR_0_PFIFO_PENDING; - } - - if (status & NV_PMC_INTR_0_PGRAPH_PENDING) { - if (dev_priv->card_type >= NV_50) - nv50_pgraph_irq_handler(dev); - else - nouveau_pgraph_irq_handler(dev); - - status &= ~NV_PMC_INTR_0_PGRAPH_PENDING; - } - - if (status & NV_PMC_INTR_0_CRTCn_PENDING) { - nouveau_crtc_irq_handler(dev, (status>>24)&3); - status &= ~NV_PMC_INTR_0_CRTCn_PENDING; - } - - if (status & NV_PMC_INTR_0_NV50_DISPLAY_PENDING) { - nouveau_nv50_display_irq_handler(dev); - status &= ~NV_PMC_INTR_0_NV50_DISPLAY_PENDING; - } - - if (status & NV_PMC_INTR_0_NV50_I2C_PENDING) { - nouveau_nv50_i2c_irq_handler(dev); - status &= ~NV_PMC_INTR_0_NV50_I2C_PENDING; - } - - if (status) - DRM_ERROR("Unhandled PMC INTR status bits 0x%08x\n", status); - - return IRQ_HANDLED; -} diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c deleted file mode 100644 index 627b9178..00000000 --- a/shared-core/nouveau_mem.c +++ /dev/null @@ -1,910 +0,0 @@ -/* - * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * Copyright 2005 Stephane Marchesin - * - * The Weather Channel (TM) funded Tungsten Graphics to develop the - * initial release of the Radeon 8500 driver under the XFree86 license. - * This notice must be preserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Keith Whitwell - */ - - -#include "drmP.h" -#include "drm.h" -#include "drm_sarea.h" -#include "nouveau_drv.h" - -static struct mem_block * -split_block(struct mem_block *p, uint64_t start, uint64_t size, - struct drm_file *file_priv) -{ - /* Maybe cut off the start of an existing block */ - if (start > p->start) { - struct mem_block *newblock = - drm_alloc(sizeof(*newblock), DRM_MEM_BUFS); - if (!newblock) - goto out; - newblock->start = start; - newblock->size = p->size - (start - p->start); - newblock->file_priv = NULL; - newblock->next = p->next; - newblock->prev = p; - p->next->prev = newblock; - p->next = newblock; - p->size -= newblock->size; - p = newblock; - } - - /* Maybe cut off the end of an existing block */ - if (size < p->size) { - struct mem_block *newblock = - drm_alloc(sizeof(*newblock), DRM_MEM_BUFS); - if (!newblock) - goto out; - newblock->start = start + size; - newblock->size = p->size - size; - newblock->file_priv = NULL; - newblock->next = p->next; - newblock->prev = p; - p->next->prev = newblock; - p->next = newblock; - p->size = size; - } - -out: - /* Our block is in the middle */ - p->file_priv = file_priv; - return p; -} - -struct mem_block * -nouveau_mem_alloc_block(struct mem_block *heap, uint64_t size, - int align2, struct drm_file *file_priv, int tail) -{ - struct mem_block *p; - uint64_t mask = (1 << align2) - 1; - - if (!heap) - return NULL; - - if (tail) { - list_for_each_prev(p, heap) { - uint64_t start = ((p->start + p->size) - size) & ~mask; - - if (p->file_priv == 0 && start >= p->start && - start + size <= p->start + p->size) - return split_block(p, start, size, file_priv); - } - } else { - list_for_each(p, heap) { - uint64_t start = (p->start + mask) & ~mask; - - if (p->file_priv == 0 && - start + size <= p->start + p->size) - return split_block(p, start, size, file_priv); - } - } - - return NULL; -} - -static struct mem_block *find_block(struct mem_block *heap, uint64_t start) -{ - struct mem_block *p; - - list_for_each(p, heap) - if (p->start == start) - return p; - - return NULL; -} - -void nouveau_mem_free_block(struct mem_block *p) -{ - p->file_priv = NULL; - - /* Assumes a single contiguous range. Needs a special file_priv in - * 'heap' to stop it being subsumed. - */ - if (p->next->file_priv == 0) { - struct mem_block *q = p->next; - p->size += q->size; - p->next = q->next; - p->next->prev = p; - drm_free(q, sizeof(*q), DRM_MEM_BUFS); - } - - if (p->prev->file_priv == 0) { - struct mem_block *q = p->prev; - q->size += p->size; - q->next = p->next; - q->next->prev = q; - drm_free(p, sizeof(*q), DRM_MEM_BUFS); - } -} - -/* Initialize. How to check for an uninitialized heap? - */ -int nouveau_mem_init_heap(struct mem_block **heap, uint64_t start, - uint64_t size) -{ - struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFS); - - if (!blocks) - return -ENOMEM; - - *heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFS); - if (!*heap) { - drm_free(blocks, sizeof(*blocks), DRM_MEM_BUFS); - return -ENOMEM; - } - - blocks->start = start; - blocks->size = size; - blocks->file_priv = NULL; - blocks->next = blocks->prev = *heap; - - memset(*heap, 0, sizeof(**heap)); - (*heap)->file_priv = (struct drm_file *) - 1; - (*heap)->next = (*heap)->prev = blocks; - return 0; -} - -/* - * Free all blocks associated with the releasing file_priv - */ -void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap) -{ - struct mem_block *p; - - if (!heap || !heap->next) - return; - - list_for_each(p, heap) { - if (p->file_priv == file_priv) - p->file_priv = NULL; - } - - /* Assumes a single contiguous range. Needs a special file_priv in - * 'heap' to stop it being subsumed. - */ - list_for_each(p, heap) { - while ((p->file_priv == 0) && (p->next->file_priv == 0) && - (p->next!=heap)) { - struct mem_block *q = p->next; - p->size += q->size; - p->next = q->next; - p->next->prev = p; - drm_free(q, sizeof(*q), DRM_MEM_DRIVER); - } - } -} - -/* - * Cleanup everything - */ -void nouveau_mem_takedown(struct mem_block **heap) -{ - struct mem_block *p; - - if (!*heap) - return; - - for (p = (*heap)->next; p != *heap;) { - struct mem_block *q = p; - p = p->next; - drm_free(q, sizeof(*q), DRM_MEM_DRIVER); - } - - drm_free(*heap, sizeof(**heap), DRM_MEM_DRIVER); - *heap = NULL; -} - -void nouveau_mem_close(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - nouveau_mem_takedown(&dev_priv->agp_heap); - nouveau_mem_takedown(&dev_priv->fb_heap); - if (dev_priv->pci_heap) - nouveau_mem_takedown(&dev_priv->pci_heap); -} - -/*XXX BSD needs compat functions for pci access - * #define DRM_PCI_DEV struct device - * #define drm_pci_get_bsf pci_get_bsf - * and a small inline to do *val = pci_read_config(pdev->device, where, 4); - * might work - */ -static int nforce_pci_fn_read_config_dword(int devfn, int where, uint32_t *val) -{ -#ifdef __linux__ - DRM_PCI_DEV *pdev; - - if (!(pdev = drm_pci_get_bsf(0, 0, devfn))) { - DRM_ERROR("nForce PCI device function 0x%02x not found\n", - devfn); - return -ENODEV; - } - - return drm_pci_read_config_dword(pdev, where, val); -#else - DRM_ERROR("BSD compat for checking IGP memory amount needed\n"); - return 0; -#endif -} - -static void nouveau_mem_check_nforce_dimms(struct drm_device *dev) -{ - uint32_t mem_ctrlr_pciid; - - nforce_pci_fn_read_config_dword(3, 0x00, &mem_ctrlr_pciid); - mem_ctrlr_pciid >>= 16; - - if (mem_ctrlr_pciid == 0x01a9 || mem_ctrlr_pciid == 0x01ab || - mem_ctrlr_pciid == 0x01ed) { - uint32_t dimm[3]; - int i; - - for (i = 0; i < 3; i++) { - nforce_pci_fn_read_config_dword(2, 0x40 + i * 4, &dimm[i]); - dimm[i] = (dimm[i] >> 8) & 0x4f; - } - - if (dimm[0] + dimm[1] != dimm[2]) - DRM_INFO("Your nForce DIMMs are not arranged in " - "optimal banks!\n"); - } -} - -static uint32_t -nouveau_mem_fb_amount_igp(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t mem = 0; - - if (dev_priv->flags & NV_NFORCE) { - nforce_pci_fn_read_config_dword(1, 0x7C, &mem); - return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024; - } - if (dev_priv->flags & NV_NFORCE2) { - nforce_pci_fn_read_config_dword(1, 0x84, &mem); - return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024; - } - - DRM_ERROR("impossible!\n"); - - return 0; -} - -/* returns the amount of FB ram in bytes */ -uint64_t nouveau_mem_fb_amount(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv=dev->dev_private; - switch(dev_priv->card_type) - { - case NV_04: - case NV_05: - if (NV_READ(NV03_BOOT_0) & 0x00000100) { - return (((NV_READ(NV03_BOOT_0) >> 12) & 0xf)*2+2)*1024*1024; - } else - switch(NV_READ(NV03_BOOT_0)&NV03_BOOT_0_RAM_AMOUNT) - { - case NV04_BOOT_0_RAM_AMOUNT_32MB: - return 32*1024*1024; - case NV04_BOOT_0_RAM_AMOUNT_16MB: - return 16*1024*1024; - case NV04_BOOT_0_RAM_AMOUNT_8MB: - return 8*1024*1024; - case NV04_BOOT_0_RAM_AMOUNT_4MB: - return 4*1024*1024; - } - break; - case NV_10: - case NV_11: - case NV_17: - case NV_20: - case NV_30: - case NV_40: - case NV_44: - case NV_50: - default: - if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) { - return nouveau_mem_fb_amount_igp(dev); - } else { - uint64_t mem; - - mem = (NV_READ(NV10_PFB_CSTATUS) & - NV10_PFB_CSTATUS_RAM_AMOUNT_MB_MASK) >> - NV10_PFB_CSTATUS_RAM_AMOUNT_MB_SHIFT; - return mem*1024*1024; - } - break; - } - - DRM_ERROR("Unable to detect video ram size. Please report your setup to " DRIVER_EMAIL "\n"); - return 0; -} - -static void nouveau_mem_reset_agp(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t saved_pci_nv_1, saved_pci_nv_19, pmc_enable; - - saved_pci_nv_1 = NV_READ(NV04_PBUS_PCI_NV_1); - saved_pci_nv_19 = NV_READ(NV04_PBUS_PCI_NV_19); - - /* clear busmaster bit */ - NV_WRITE(NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4); - /* clear SBA and AGP bits */ - NV_WRITE(NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffff0ff); - - /* power cycle pgraph, if enabled */ - pmc_enable = NV_READ(NV03_PMC_ENABLE); - if (pmc_enable & NV_PMC_ENABLE_PGRAPH) { - NV_WRITE(NV03_PMC_ENABLE, pmc_enable & ~NV_PMC_ENABLE_PGRAPH); - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | - NV_PMC_ENABLE_PGRAPH); - } - - /* and restore (gives effect of resetting AGP) */ - NV_WRITE(NV04_PBUS_PCI_NV_19, saved_pci_nv_19); - NV_WRITE(NV04_PBUS_PCI_NV_1, saved_pci_nv_1); -} - -static int -nouveau_mem_init_agp(struct drm_device *dev, int ttm) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct drm_agp_info info; - struct drm_agp_mode mode; - int ret; - - nouveau_mem_reset_agp(dev); - - ret = drm_agp_acquire(dev); - if (ret) { - DRM_ERROR("Unable to acquire AGP: %d\n", ret); - return ret; - } - - ret = drm_agp_info(dev, &info); - if (ret) { - DRM_ERROR("Unable to get AGP info: %d\n", ret); - return ret; - } - - /* see agp.h for the AGPSTAT_* modes available */ - mode.mode = info.mode; - ret = drm_agp_enable(dev, mode); - if (ret) { - DRM_ERROR("Unable to enable AGP: %d\n", ret); - return ret; - } - - if (!ttm) { - struct drm_agp_buffer agp_req; - struct drm_agp_binding bind_req; - - agp_req.size = info.aperture_size; - agp_req.type = 0; - ret = drm_agp_alloc(dev, &agp_req); - if (ret) { - DRM_ERROR("Unable to alloc AGP: %d\n", ret); - return ret; - } - - bind_req.handle = agp_req.handle; - bind_req.offset = 0; - ret = drm_agp_bind(dev, &bind_req); - if (ret) { - DRM_ERROR("Unable to bind AGP: %d\n", ret); - return ret; - } - } - - dev_priv->gart_info.type = NOUVEAU_GART_AGP; - dev_priv->gart_info.aper_base = info.aperture_base; - dev_priv->gart_info.aper_size = info.aperture_size; - return 0; -} - -#define HACK_OLD_MM -int -nouveau_mem_init_ttm(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t vram_size, bar1_size; - int ret; - - dev_priv->agp_heap = dev_priv->pci_heap = dev_priv->fb_heap = NULL; - dev_priv->fb_phys = drm_get_resource_start(dev,1); - dev_priv->gart_info.type = NOUVEAU_GART_NONE; - - drm_bo_driver_init(dev); - - /* non-mappable vram */ - dev_priv->fb_available_size = nouveau_mem_fb_amount(dev); - dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram; - vram_size = dev_priv->fb_available_size >> PAGE_SHIFT; - bar1_size = drm_get_resource_len(dev, 1) >> PAGE_SHIFT; - if (bar1_size < vram_size) { - if ((ret = drm_bo_init_mm(dev, DRM_BO_MEM_PRIV0, - bar1_size, vram_size - bar1_size, 1))) { - DRM_ERROR("Failed PRIV0 mm init: %d\n", ret); - return ret; - } - vram_size = bar1_size; - } - - /* mappable vram */ -#ifdef HACK_OLD_MM - vram_size /= 4; -#endif - if ((ret = drm_bo_init_mm(dev, DRM_BO_MEM_VRAM, 0, vram_size, 1))) { - DRM_ERROR("Failed VRAM mm init: %d\n", ret); - return ret; - } - - /* GART */ -#if !defined(__powerpc__) && !defined(__ia64__) - if (drm_device_is_agp(dev) && dev->agp) { - if ((ret = nouveau_mem_init_agp(dev, 1))) - DRM_ERROR("Error initialising AGP: %d\n", ret); - } -#endif - - if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) { - if ((ret = nouveau_sgdma_init(dev))) - DRM_ERROR("Error initialising PCI SGDMA: %d\n", ret); - } - - if ((ret = drm_bo_init_mm(dev, DRM_BO_MEM_TT, 0, - dev_priv->gart_info.aper_size >> - PAGE_SHIFT, 1))) { - DRM_ERROR("Failed TT mm init: %d\n", ret); - return ret; - } - -#ifdef HACK_OLD_MM - vram_size <<= PAGE_SHIFT; - DRM_INFO("Old MM using %dKiB VRAM\n", (vram_size * 3) >> 10); - if (nouveau_mem_init_heap(&dev_priv->fb_heap, vram_size, vram_size * 3)) - return -ENOMEM; -#endif - - return 0; -} - -int nouveau_mem_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t fb_size; - int ret = 0; - - dev_priv->agp_heap = dev_priv->pci_heap = dev_priv->fb_heap = NULL; - dev_priv->fb_phys = 0; - dev_priv->gart_info.type = NOUVEAU_GART_NONE; - - if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) - nouveau_mem_check_nforce_dimms(dev); - - /* setup a mtrr over the FB */ - dev_priv->fb_mtrr = drm_mtrr_add(drm_get_resource_start(dev, 1), - nouveau_mem_fb_amount(dev), - DRM_MTRR_WC); - - /* Init FB */ - dev_priv->fb_phys=drm_get_resource_start(dev,1); - fb_size = nouveau_mem_fb_amount(dev); - /* On G80, limit VRAM to 512MiB temporarily due to limits in how - * we handle VRAM page tables. - */ - if (dev_priv->card_type >= NV_50 && fb_size > (512 * 1024 * 1024)) - fb_size = (512 * 1024 * 1024); - fb_size -= dev_priv->ramin_rsvd_vram; - dev_priv->fb_available_size = fb_size; - DRM_DEBUG("Available VRAM: %dKiB\n", fb_size>>10); - - if (fb_size>256*1024*1024) { - /* On cards with > 256Mb, you can't map everything. - * So we create a second FB heap for that type of memory */ - if (nouveau_mem_init_heap(&dev_priv->fb_heap, - 0, 256*1024*1024)) - return -ENOMEM; - if (nouveau_mem_init_heap(&dev_priv->fb_nomap_heap, - 256*1024*1024, fb_size-256*1024*1024)) - return -ENOMEM; - } else { - if (nouveau_mem_init_heap(&dev_priv->fb_heap, 0, fb_size)) - return -ENOMEM; - dev_priv->fb_nomap_heap=NULL; - } - -#if !defined(__powerpc__) && !defined(__ia64__) - /* Init AGP / NV50 PCIEGART */ - if (drm_device_is_agp(dev) && dev->agp) { - if ((ret = nouveau_mem_init_agp(dev, 0))) - DRM_ERROR("Error initialising AGP: %d\n", ret); - } -#endif - - /*Note: this is *not* just NV50 code, but only used on NV50 for now */ - if (dev_priv->gart_info.type == NOUVEAU_GART_NONE && - dev_priv->card_type >= NV_50) { - ret = nouveau_sgdma_init(dev); - if (!ret) { - ret = nouveau_sgdma_nottm_hack_init(dev); - if (ret) - nouveau_sgdma_takedown(dev); - } - - if (ret) - DRM_ERROR("Error initialising SG DMA: %d\n", ret); - } - - if (dev_priv->gart_info.type != NOUVEAU_GART_NONE) { - if (nouveau_mem_init_heap(&dev_priv->agp_heap, - 0, dev_priv->gart_info.aper_size)) { - if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA) { - nouveau_sgdma_nottm_hack_takedown(dev); - nouveau_sgdma_takedown(dev); - } - } - } - - /* NV04-NV40 PCIEGART */ - if (!dev_priv->agp_heap && dev_priv->card_type < NV_50) { - struct drm_scatter_gather sgreq; - - DRM_DEBUG("Allocating sg memory for PCI DMA\n"); - sgreq.size = 16 << 20; //16MB of PCI scatter-gather zone - - if (drm_sg_alloc(dev, &sgreq)) { - DRM_ERROR("Unable to allocate %ldMB of scatter-gather" - " pages for PCI DMA!",sgreq.size>>20); - } else { - if (nouveau_mem_init_heap(&dev_priv->pci_heap, 0, - dev->sg->pages * PAGE_SIZE)) { - DRM_ERROR("Unable to initialize pci_heap!"); - } - } - } - - /* G8x: Allocate shared page table to map real VRAM pages into */ - if (dev_priv->card_type >= NV_50) { - unsigned size = ((512 * 1024 * 1024) / 65536) * 8; - - ret = nouveau_gpuobj_new(dev, NULL, size, 0, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ALLOW_NO_REFS, - &dev_priv->vm_vram_pt); - if (ret) { - DRM_ERROR("Error creating VRAM page table: %d\n", ret); - return ret; - } - } - - - return 0; -} - -struct mem_block * -nouveau_mem_alloc(struct drm_device *dev, int alignment, uint64_t size, - int flags, struct drm_file *file_priv) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct mem_block *block; - int type, tail = !(flags & NOUVEAU_MEM_USER); - - /* - * Make things easier on ourselves: all allocations are page-aligned. - * We need that to map allocated regions into the user space - */ - if (alignment < PAGE_SIZE) - alignment = PAGE_SIZE; - - /* Align allocation sizes to 64KiB blocks on G8x. We use a 64KiB - * page size in the GPU VM. - */ - if (flags & NOUVEAU_MEM_FB && dev_priv->card_type >= NV_50) { - size = (size + 65535) & ~65535; - if (alignment < 65536) - alignment = 65536; - } - - /* Further down wants alignment in pages, not bytes */ - alignment >>= PAGE_SHIFT; - - /* - * Warn about 0 sized allocations, but let it go through. It'll return 1 page - */ - if (size == 0) - DRM_INFO("warning : 0 byte allocation\n"); - - /* - * Keep alloc size a multiple of the page size to keep drm_addmap() happy - */ - if (size & (~PAGE_MASK)) - size = ((size/PAGE_SIZE) + 1) * PAGE_SIZE; - - -#define NOUVEAU_MEM_ALLOC_AGP {\ - type=NOUVEAU_MEM_AGP;\ - block = nouveau_mem_alloc_block(dev_priv->agp_heap, size,\ - alignment, file_priv, tail); \ - if (block) goto alloc_ok;\ - } - -#define NOUVEAU_MEM_ALLOC_PCI {\ - type = NOUVEAU_MEM_PCI;\ - block = nouveau_mem_alloc_block(dev_priv->pci_heap, size, \ - alignment, file_priv, tail); \ - if ( block ) goto alloc_ok;\ - } - -#define NOUVEAU_MEM_ALLOC_FB {\ - type=NOUVEAU_MEM_FB;\ - if (!(flags&NOUVEAU_MEM_MAPPED)) {\ - block = nouveau_mem_alloc_block(dev_priv->fb_nomap_heap,\ - size, alignment, \ - file_priv, tail); \ - if (block) goto alloc_ok;\ - }\ - block = nouveau_mem_alloc_block(dev_priv->fb_heap, size,\ - alignment, file_priv, tail);\ - if (block) goto alloc_ok;\ - } - - - if (flags&NOUVEAU_MEM_FB) NOUVEAU_MEM_ALLOC_FB - if (flags&NOUVEAU_MEM_AGP) NOUVEAU_MEM_ALLOC_AGP - if (flags&NOUVEAU_MEM_PCI) NOUVEAU_MEM_ALLOC_PCI - if (flags&NOUVEAU_MEM_FB_ACCEPTABLE) NOUVEAU_MEM_ALLOC_FB - if (flags&NOUVEAU_MEM_AGP_ACCEPTABLE) NOUVEAU_MEM_ALLOC_AGP - if (flags&NOUVEAU_MEM_PCI_ACCEPTABLE) NOUVEAU_MEM_ALLOC_PCI - - - return NULL; - -alloc_ok: - block->flags=type; - - /* On G8x, map memory into VM */ - if (block->flags & NOUVEAU_MEM_FB && dev_priv->card_type >= NV_50 && - !(flags & NOUVEAU_MEM_NOVM)) { - struct nouveau_gpuobj *pt = dev_priv->vm_vram_pt; - unsigned offset = block->start; - unsigned count = block->size / 65536; - unsigned tile = 0; - - if (!pt) { - DRM_ERROR("vm alloc without vm pt\n"); - nouveau_mem_free_block(block); - return NULL; - } - - /* The tiling stuff is *not* what NVIDIA does - but both the - * 2D and 3D engines seem happy with this simpler method. - * Should look into why NVIDIA do what they do at some point. - */ - if (flags & NOUVEAU_MEM_TILE) { - if (flags & NOUVEAU_MEM_TILE_ZETA) - tile = 0x00002800; - else - tile = 0x00007000; - } - - while (count--) { - unsigned pte = offset / 65536; - - INSTANCE_WR(pt, (pte * 2) + 0, offset | 1); - INSTANCE_WR(pt, (pte * 2) + 1, 0x00000000 | tile); - offset += 65536; - } - } else { - block->flags |= NOUVEAU_MEM_NOVM; - } - - if (flags&NOUVEAU_MEM_MAPPED) - { - struct drm_map_list *entry; - int ret = 0; - block->flags|=NOUVEAU_MEM_MAPPED; - - if (type == NOUVEAU_MEM_AGP) { - if (dev_priv->gart_info.type != NOUVEAU_GART_SGDMA) - ret = drm_addmap(dev, block->start, block->size, - _DRM_AGP, 0, &block->map); - else - ret = drm_addmap(dev, block->start, block->size, - _DRM_SCATTER_GATHER, 0, &block->map); - } - else if (type == NOUVEAU_MEM_FB) - ret = drm_addmap(dev, block->start + dev_priv->fb_phys, - block->size, _DRM_FRAME_BUFFER, - 0, &block->map); - else if (type == NOUVEAU_MEM_PCI) - ret = drm_addmap(dev, block->start, block->size, - _DRM_SCATTER_GATHER, 0, &block->map); - - if (ret) { - nouveau_mem_free_block(block); - return NULL; - } - - entry = drm_find_matching_map(dev, block->map); - if (!entry) { - nouveau_mem_free_block(block); - return NULL; - } - block->map_handle = entry->user_token; - } - - DRM_DEBUG("allocated %lld bytes at 0x%llx type=0x%08x\n", block->size, block->start, block->flags); - return block; -} - -void nouveau_mem_free(struct drm_device* dev, struct mem_block* block) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - DRM_DEBUG("freeing 0x%llx type=0x%08x\n", block->start, block->flags); - - if (block->flags&NOUVEAU_MEM_MAPPED) - drm_rmmap(dev, block->map); - - /* G8x: Remove pages from vm */ - if (block->flags & NOUVEAU_MEM_FB && dev_priv->card_type >= NV_50 && - !(block->flags & NOUVEAU_MEM_NOVM)) { - struct nouveau_gpuobj *pt = dev_priv->vm_vram_pt; - unsigned offset = block->start; - unsigned count = block->size / 65536; - - if (!pt) { - DRM_ERROR("vm free without vm pt\n"); - goto out_free; - } - - while (count--) { - unsigned pte = offset / 65536; - INSTANCE_WR(pt, (pte * 2) + 0, 0); - INSTANCE_WR(pt, (pte * 2) + 1, 0); - offset += 65536; - } - } - -out_free: - nouveau_mem_free_block(block); -} - -/* - * Ioctls - */ - -int -nouveau_ioctl_mem_alloc(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct drm_nouveau_mem_alloc *alloc = data; - struct mem_block *block; - - NOUVEAU_CHECK_INITIALISED_WITH_RETURN; - - if (alloc->flags & NOUVEAU_MEM_INTERNAL) - return -EINVAL; - - block = nouveau_mem_alloc(dev, alloc->alignment, alloc->size, - alloc->flags | NOUVEAU_MEM_USER, file_priv); - if (!block) - return -ENOMEM; - alloc->map_handle=block->map_handle; - alloc->offset=block->start; - alloc->flags=block->flags; - - if (dev_priv->card_type >= NV_50 && alloc->flags & NOUVEAU_MEM_FB) - alloc->offset += 512*1024*1024; - - return 0; -} - -int -nouveau_ioctl_mem_free(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct drm_nouveau_mem_free *memfree = data; - struct mem_block *block; - - NOUVEAU_CHECK_INITIALISED_WITH_RETURN; - - if (dev_priv->card_type >= NV_50 && memfree->flags & NOUVEAU_MEM_FB) - memfree->offset -= 512*1024*1024; - - block=NULL; - if (dev_priv->fb_heap && memfree->flags & NOUVEAU_MEM_FB) - block = find_block(dev_priv->fb_heap, memfree->offset); - else if (dev_priv->agp_heap && memfree->flags & NOUVEAU_MEM_AGP) - block = find_block(dev_priv->agp_heap, memfree->offset); - else if (dev_priv->pci_heap && memfree->flags & NOUVEAU_MEM_PCI) - block = find_block(dev_priv->pci_heap, memfree->offset); - if (!block) - return -EFAULT; - if (block->file_priv != file_priv) - return -EPERM; - - nouveau_mem_free(dev, block); - return 0; -} - -int -nouveau_ioctl_mem_tile(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct drm_nouveau_mem_tile *memtile = data; - struct mem_block *block = NULL; - - NOUVEAU_CHECK_INITIALISED_WITH_RETURN; - - if (dev_priv->card_type < NV_50) - return -EINVAL; - - if (memtile->flags & NOUVEAU_MEM_FB) { - memtile->offset -= 512*1024*1024; - block = find_block(dev_priv->fb_heap, memtile->offset); - } - - if (!block) - return -EINVAL; - - if (block->file_priv != file_priv) - return -EPERM; - - { - struct nouveau_gpuobj *pt = dev_priv->vm_vram_pt; - unsigned offset = block->start + memtile->delta; - unsigned count = memtile->size / 65536; - unsigned tile = 0; - - if (memtile->flags & NOUVEAU_MEM_TILE) { - if (memtile->flags & NOUVEAU_MEM_TILE_ZETA) - tile = 0x00002800; - else - tile = 0x00007000; - } - - while (count--) { - unsigned pte = offset / 65536; - - INSTANCE_WR(pt, (pte * 2) + 0, offset | 1); - INSTANCE_WR(pt, (pte * 2) + 1, 0x00000000 | tile); - offset += 65536; - } - } - - return 0; -} - diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c deleted file mode 100644 index edece4da..00000000 --- a/shared-core/nouveau_notifier.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (C) 2007 Ben Skeggs. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" - -int -nouveau_notifier_init_channel(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - int flags, ret; - - flags = (NOUVEAU_MEM_PCI | NOUVEAU_MEM_MAPPED | - NOUVEAU_MEM_FB_ACCEPTABLE); - - chan->notifier_block = nouveau_mem_alloc(dev, 0, PAGE_SIZE, flags, - (struct drm_file *)-2); - if (!chan->notifier_block) - return -ENOMEM; - DRM_DEBUG("Allocated notifier block in 0x%08x\n", - chan->notifier_block->flags); - - ret = nouveau_mem_init_heap(&chan->notifier_heap, - 0, chan->notifier_block->size); - if (ret) - return ret; - - return 0; -} - -void -nouveau_notifier_takedown_channel(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - - if (chan->notifier_block) { - nouveau_mem_free(dev, chan->notifier_block); - chan->notifier_block = NULL; - } - - nouveau_mem_takedown(&chan->notifier_heap); -} - -static void -nouveau_notifier_gpuobj_dtor(struct drm_device *dev, - struct nouveau_gpuobj *gpuobj) -{ - DRM_DEBUG("\n"); - - if (gpuobj->priv) - nouveau_mem_free_block(gpuobj->priv); -} - -int -nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle, - int count, uint32_t *b_offset) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_gpuobj *nobj = NULL; - struct mem_block *mem; - uint32_t offset; - int target, ret; - - if (!chan->notifier_heap) { - DRM_ERROR("Channel %d doesn't have a notifier heap!\n", - chan->id); - return -EINVAL; - } - - mem = nouveau_mem_alloc_block(chan->notifier_heap, count*32, 0, - (struct drm_file *)-2, 0); - if (!mem) { - DRM_ERROR("Channel %d notifier block full\n", chan->id); - return -ENOMEM; - } - mem->flags = NOUVEAU_MEM_NOTIFIER; - - offset = chan->notifier_block->start; - if (chan->notifier_block->flags & NOUVEAU_MEM_FB) { - target = NV_DMA_TARGET_VIDMEM; - } else - if (chan->notifier_block->flags & NOUVEAU_MEM_AGP) { - if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA && - dev_priv->card_type < NV_50) { - ret = nouveau_sgdma_get_page(dev, offset, &offset); - if (ret) - return ret; - target = NV_DMA_TARGET_PCI; - } else { - target = NV_DMA_TARGET_AGP; - } - } else - if (chan->notifier_block->flags & NOUVEAU_MEM_PCI) { - target = NV_DMA_TARGET_PCI_NONLINEAR; - } else { - DRM_ERROR("Bad DMA target, flags 0x%08x!\n", - chan->notifier_block->flags); - return -EINVAL; - } - offset += mem->start; - - if ((ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, - offset, mem->size, - NV_DMA_ACCESS_RW, target, &nobj))) { - nouveau_mem_free_block(mem); - DRM_ERROR("Error creating notifier ctxdma: %d\n", ret); - return ret; - } - nobj->dtor = nouveau_notifier_gpuobj_dtor; - nobj->priv = mem; - - if ((ret = nouveau_gpuobj_ref_add(dev, chan, handle, nobj, NULL))) { - nouveau_gpuobj_del(dev, &nobj); - nouveau_mem_free_block(mem); - DRM_ERROR("Error referencing notifier ctxdma: %d\n", ret); - return ret; - } - - *b_offset = mem->start; - return 0; -} - -int -nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_nouveau_notifierobj_alloc *na = data; - struct nouveau_channel *chan; - int ret; - - NOUVEAU_CHECK_INITIALISED_WITH_RETURN; - NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(na->channel, file_priv, chan); - - ret = nouveau_notifier_alloc(chan, na->handle, na->count, &na->offset); - if (ret) - return ret; - - return 0; -} diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c deleted file mode 100644 index 19325f37..00000000 --- a/shared-core/nouveau_object.c +++ /dev/null @@ -1,1173 +0,0 @@ -/* - * Copyright (C) 2006 Ben Skeggs. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/* - * Authors: - * Ben Skeggs - */ - -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" -#include "nouveau_drm.h" - -/* NVidia uses context objects to drive drawing operations. - - Context objects can be selected into 8 subchannels in the FIFO, - and then used via DMA command buffers. - - A context object is referenced by a user defined handle (CARD32). The HW - looks up graphics objects in a hash table in the instance RAM. - - An entry in the hash table consists of 2 CARD32. The first CARD32 contains - the handle, the second one a bitfield, that contains the address of the - object in instance RAM. - - The format of the second CARD32 seems to be: - - NV4 to NV30: - - 15: 0 instance_addr >> 4 - 17:16 engine (here uses 1 = graphics) - 28:24 channel id (here uses 0) - 31 valid (use 1) - - NV40: - - 15: 0 instance_addr >> 4 (maybe 19-0) - 21:20 engine (here uses 1 = graphics) - I'm unsure about the other bits, but using 0 seems to work. - - The key into the hash table depends on the object handle and channel id and - is given as: -*/ -static uint32_t -nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle) -{ - struct drm_nouveau_private *dev_priv=dev->dev_private; - uint32_t hash = 0; - int i; - - DRM_DEBUG("ch%d handle=0x%08x\n", channel, handle); - - for (i=32;i>0;i-=dev_priv->ramht_bits) { - hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1)); - handle >>= dev_priv->ramht_bits; - } - if (dev_priv->card_type < NV_50) - hash ^= channel << (dev_priv->ramht_bits - 4); - hash <<= 3; - - DRM_DEBUG("hash=0x%08x\n", hash); - return hash; -} - -static int -nouveau_ramht_entry_valid(struct drm_device *dev, struct nouveau_gpuobj *ramht, - uint32_t offset) -{ - struct drm_nouveau_private *dev_priv=dev->dev_private; - uint32_t ctx = INSTANCE_RD(ramht, (offset + 4)/4); - - if (dev_priv->card_type < NV_40) - return ((ctx & NV_RAMHT_CONTEXT_VALID) != 0); - return (ctx != 0); -} - -static int -nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) -{ - struct drm_nouveau_private *dev_priv=dev->dev_private; - struct nouveau_channel *chan = dev_priv->fifos[ref->channel]; - struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL; - struct nouveau_gpuobj *gpuobj = ref->gpuobj; - uint32_t ctx, co, ho; - - if (!ramht) { - DRM_ERROR("No hash table!\n"); - return -EINVAL; - } - - if (dev_priv->card_type < NV_40) { - ctx = NV_RAMHT_CONTEXT_VALID | (ref->instance >> 4) | - (ref->channel << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) | - (gpuobj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT); - } else - if (dev_priv->card_type < NV_50) { - ctx = (ref->instance >> 4) | - (ref->channel << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) | - (gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT); - } else { - ctx = (ref->instance >> 4) | - (gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT); - } - - co = ho = nouveau_ramht_hash_handle(dev, ref->channel, ref->handle); - do { - if (!nouveau_ramht_entry_valid(dev, ramht, co)) { - DRM_DEBUG("insert ch%d 0x%08x: h=0x%08x, c=0x%08x\n", - ref->channel, co, ref->handle, ctx); - INSTANCE_WR(ramht, (co + 0)/4, ref->handle); - INSTANCE_WR(ramht, (co + 4)/4, ctx); - - list_add_tail(&ref->list, &chan->ramht_refs); - return 0; - } - DRM_DEBUG("collision ch%d 0x%08x: h=0x%08x\n", - ref->channel, co, INSTANCE_RD(ramht, co/4)); - - co += 8; - if (co >= dev_priv->ramht_size) - co = 0; - } while (co != ho); - - DRM_ERROR("RAMHT space exhausted. ch=%d\n", ref->channel); - return -ENOMEM; -} - -static void -nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_channel *chan = dev_priv->fifos[ref->channel]; - struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL; - uint32_t co, ho; - - if (!ramht) { - DRM_ERROR("No hash table!\n"); - return; - } - - co = ho = nouveau_ramht_hash_handle(dev, ref->channel, ref->handle); - do { - if (nouveau_ramht_entry_valid(dev, ramht, co) && - (ref->handle == INSTANCE_RD(ramht, (co/4)))) { - DRM_DEBUG("remove ch%d 0x%08x: h=0x%08x, c=0x%08x\n", - ref->channel, co, ref->handle, - INSTANCE_RD(ramht, (co + 4))); - INSTANCE_WR(ramht, (co + 0)/4, 0x00000000); - INSTANCE_WR(ramht, (co + 4)/4, 0x00000000); - - list_del(&ref->list); - return; - } - - co += 8; - if (co >= dev_priv->ramht_size) - co = 0; - } while (co != ho); - - DRM_ERROR("RAMHT entry not found. ch=%d, handle=0x%08x\n", - ref->channel, ref->handle); -} - -int -nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan, - int size, int align, uint32_t flags, - struct nouveau_gpuobj **gpuobj_ret) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine *engine = &dev_priv->Engine; - struct nouveau_gpuobj *gpuobj; - struct mem_block *pramin = NULL; - int ret; - - DRM_DEBUG("ch%d size=%d align=%d flags=0x%08x\n", - chan ? chan->id : -1, size, align, flags); - - if (!dev_priv || !gpuobj_ret || *gpuobj_ret != NULL) - return -EINVAL; - - gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER); - if (!gpuobj) - return -ENOMEM; - DRM_DEBUG("gpuobj %p\n", gpuobj); - gpuobj->flags = flags; - gpuobj->im_channel = chan ? chan->id : -1; - - list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list); - - /* Choose between global instmem heap, and per-channel private - * instmem heap. On ramin_heap) { - DRM_DEBUG("private heap\n"); - pramin = chan->ramin_heap; - } else - if (dev_priv->card_type < NV_50) { - DRM_DEBUG("global heap fallback\n"); - pramin = dev_priv->ramin_heap; - } - } else { - DRM_DEBUG("global heap\n"); - pramin = dev_priv->ramin_heap; - } - - if (!pramin) { - DRM_ERROR("No PRAMIN heap!\n"); - return -EINVAL; - } - - if (!chan && (ret = engine->instmem.populate(dev, gpuobj, &size))) { - nouveau_gpuobj_del(dev, &gpuobj); - return ret; - } - - /* Allocate a chunk of the PRAMIN aperture */ - gpuobj->im_pramin = nouveau_mem_alloc_block(pramin, size, - drm_order(align), - (struct drm_file *)-2, 0); - if (!gpuobj->im_pramin) { - nouveau_gpuobj_del(dev, &gpuobj); - return -ENOMEM; - } - gpuobj->im_pramin->flags = NOUVEAU_MEM_INSTANCE; - - if (!chan && (ret = engine->instmem.bind(dev, gpuobj))) { - nouveau_gpuobj_del(dev, &gpuobj); - return ret; - } - - if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) { - int i; - - for (i = 0; i < gpuobj->im_pramin->size; i += 4) - INSTANCE_WR(gpuobj, i/4, 0); - } - - *gpuobj_ret = gpuobj; - return 0; -} - -int -nouveau_gpuobj_early_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - DRM_DEBUG("\n"); - - INIT_LIST_HEAD(&dev_priv->gpuobj_list); - - return 0; -} - -int -nouveau_gpuobj_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int ret; - - DRM_DEBUG("\n"); - - if (dev_priv->card_type < NV_50) { - if ((ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramht_offset, - ~0, dev_priv->ramht_size, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ALLOW_NO_REFS, - &dev_priv->ramht, NULL))) - return ret; - } - - return 0; -} - -void -nouveau_gpuobj_takedown(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - DRM_DEBUG("\n"); - - nouveau_gpuobj_del(dev, &dev_priv->ramht); -} - -void -nouveau_gpuobj_late_takedown(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_gpuobj *gpuobj = NULL; - struct list_head *entry, *tmp; - - DRM_DEBUG("\n"); - - list_for_each_safe(entry, tmp, &dev_priv->gpuobj_list) { - gpuobj = list_entry(entry, struct nouveau_gpuobj, list); - - DRM_ERROR("gpuobj %p still exists at takedown, refs=%d\n", - gpuobj, gpuobj->refcount); - gpuobj->refcount = 0; - nouveau_gpuobj_del(dev, &gpuobj); - } -} - -int -nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine *engine = &dev_priv->Engine; - struct nouveau_gpuobj *gpuobj; - - DRM_DEBUG("gpuobj %p\n", pgpuobj ? *pgpuobj : NULL); - - if (!dev_priv || !pgpuobj || !(*pgpuobj)) - return -EINVAL; - gpuobj = *pgpuobj; - - if (gpuobj->refcount != 0) { - DRM_ERROR("gpuobj refcount is %d\n", gpuobj->refcount); - return -EINVAL; - } - - if (gpuobj->dtor) - gpuobj->dtor(dev, gpuobj); - - if (gpuobj->im_backing) { - if (gpuobj->flags & NVOBJ_FLAG_FAKE) - drm_free(gpuobj->im_backing, - sizeof(*gpuobj->im_backing), DRM_MEM_DRIVER); - else - engine->instmem.clear(dev, gpuobj); - } - - if (gpuobj->im_pramin) { - if (gpuobj->flags & NVOBJ_FLAG_FAKE) - drm_free(gpuobj->im_pramin, sizeof(*gpuobj->im_pramin), - DRM_MEM_DRIVER); - else - nouveau_mem_free_block(gpuobj->im_pramin); - } - - list_del(&gpuobj->list); - - *pgpuobj = NULL; - drm_free(gpuobj, sizeof(*gpuobj), DRM_MEM_DRIVER); - return 0; -} - -static int -nouveau_gpuobj_instance_get(struct drm_device *dev, - struct nouveau_channel *chan, - struct nouveau_gpuobj *gpuobj, uint32_t *inst) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_gpuobj *cpramin; - - /* card_type < NV_50) { - *inst = gpuobj->im_pramin->start; - return 0; - } - - if (chan && gpuobj->im_channel != chan->id) { - DRM_ERROR("Channel mismatch: obj %d, ref %d\n", - gpuobj->im_channel, chan->id); - return -EINVAL; - } - - /* NV50 channel-local instance */ - if (chan > 0) { - cpramin = chan->ramin->gpuobj; - *inst = gpuobj->im_pramin->start - cpramin->im_pramin->start; - return 0; - } - - /* NV50 global (VRAM) instance */ - if (gpuobj->im_channel < 0) { - /* ...from global heap */ - if (!gpuobj->im_backing) { - DRM_ERROR("AII, no VRAM backing gpuobj\n"); - return -EINVAL; - } - *inst = gpuobj->im_backing->start; - return 0; - } else { - /* ...from local heap */ - cpramin = dev_priv->fifos[gpuobj->im_channel]->ramin->gpuobj; - *inst = cpramin->im_backing->start + - (gpuobj->im_pramin->start - cpramin->im_pramin->start); - return 0; - } - - return -EINVAL; -} - -int -nouveau_gpuobj_ref_add(struct drm_device *dev, struct nouveau_channel *chan, - uint32_t handle, struct nouveau_gpuobj *gpuobj, - struct nouveau_gpuobj_ref **ref_ret) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_gpuobj_ref *ref; - uint32_t instance; - int ret; - - DRM_DEBUG("ch%d h=0x%08x gpuobj=%p\n", - chan ? chan->id : -1, handle, gpuobj); - - if (!dev_priv || !gpuobj || (ref_ret && *ref_ret != NULL)) - return -EINVAL; - - if (!chan && !ref_ret) - return -EINVAL; - - ret = nouveau_gpuobj_instance_get(dev, chan, gpuobj, &instance); - if (ret) - return ret; - - ref = drm_calloc(1, sizeof(*ref), DRM_MEM_DRIVER); - if (!ref) - return -ENOMEM; - ref->gpuobj = gpuobj; - ref->channel = chan ? chan->id : -1; - ref->instance = instance; - - if (!ref_ret) { - ref->handle = handle; - - ret = nouveau_ramht_insert(dev, ref); - if (ret) { - drm_free(ref, sizeof(*ref), DRM_MEM_DRIVER); - return ret; - } - } else { - ref->handle = ~0; - *ref_ret = ref; - } - - ref->gpuobj->refcount++; - return 0; -} - -int nouveau_gpuobj_ref_del(struct drm_device *dev, struct nouveau_gpuobj_ref **pref) -{ - struct nouveau_gpuobj_ref *ref; - - DRM_DEBUG("ref %p\n", pref ? *pref : NULL); - - if (!dev || !pref || *pref == NULL) - return -EINVAL; - ref = *pref; - - if (ref->handle != ~0) - nouveau_ramht_remove(dev, ref); - - if (ref->gpuobj) { - ref->gpuobj->refcount--; - - if (ref->gpuobj->refcount == 0) { - if (!(ref->gpuobj->flags & NVOBJ_FLAG_ALLOW_NO_REFS)) - nouveau_gpuobj_del(dev, &ref->gpuobj); - } - } - - *pref = NULL; - drm_free(ref, sizeof(ref), DRM_MEM_DRIVER); - return 0; -} - -int -nouveau_gpuobj_new_ref(struct drm_device *dev, - struct nouveau_channel *oc, struct nouveau_channel *rc, - uint32_t handle, int size, int align, uint32_t flags, - struct nouveau_gpuobj_ref **ref) -{ - struct nouveau_gpuobj *gpuobj = NULL; - int ret; - - if ((ret = nouveau_gpuobj_new(dev, oc, size, align, flags, &gpuobj))) - return ret; - - if ((ret = nouveau_gpuobj_ref_add(dev, rc, handle, gpuobj, ref))) { - nouveau_gpuobj_del(dev, &gpuobj); - return ret; - } - - return 0; -} - -int -nouveau_gpuobj_ref_find(struct nouveau_channel *chan, uint32_t handle, - struct nouveau_gpuobj_ref **ref_ret) -{ - struct nouveau_gpuobj_ref *ref; - struct list_head *entry, *tmp; - - list_for_each_safe(entry, tmp, &chan->ramht_refs) { - ref = list_entry(entry, struct nouveau_gpuobj_ref, list); - - if (ref->handle == handle) { - if (ref_ret) - *ref_ret = ref; - return 0; - } - } - - return -EINVAL; -} - -int -nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t p_offset, - uint32_t b_offset, uint32_t size, - uint32_t flags, struct nouveau_gpuobj **pgpuobj, - struct nouveau_gpuobj_ref **pref) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_gpuobj *gpuobj = NULL; - int i; - - DRM_DEBUG("p_offset=0x%08x b_offset=0x%08x size=0x%08x flags=0x%08x\n", - p_offset, b_offset, size, flags); - - gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER); - if (!gpuobj) - return -ENOMEM; - DRM_DEBUG("gpuobj %p\n", gpuobj); - gpuobj->im_channel = -1; - gpuobj->flags = flags | NVOBJ_FLAG_FAKE; - - list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list); - - if (p_offset != ~0) { - gpuobj->im_pramin = drm_calloc(1, sizeof(struct mem_block), - DRM_MEM_DRIVER); - if (!gpuobj->im_pramin) { - nouveau_gpuobj_del(dev, &gpuobj); - return -ENOMEM; - } - gpuobj->im_pramin->start = p_offset; - gpuobj->im_pramin->size = size; - } - - if (b_offset != ~0) { - gpuobj->im_backing = drm_calloc(1, sizeof(struct mem_block), - DRM_MEM_DRIVER); - if (!gpuobj->im_backing) { - nouveau_gpuobj_del(dev, &gpuobj); - return -ENOMEM; - } - gpuobj->im_backing->start = b_offset; - gpuobj->im_backing->size = size; - } - - if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) { - for (i = 0; i < gpuobj->im_pramin->size; i += 4) - INSTANCE_WR(gpuobj, i/4, 0); - } - - if (pref) { - if ((i = nouveau_gpuobj_ref_add(dev, NULL, 0, gpuobj, pref))) { - nouveau_gpuobj_del(dev, &gpuobj); - return i; - } - } - - if (pgpuobj) - *pgpuobj = gpuobj; - return 0; -} - - -static int -nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - /*XXX: dodgy hack for now */ - if (dev_priv->card_type >= NV_50) - return 24; - if (dev_priv->card_type >= NV_40) - return 32; - return 16; -} - -/* - DMA objects are used to reference a piece of memory in the - framebuffer, PCI or AGP address space. Each object is 16 bytes big - and looks as follows: - - entry[0] - 11:0 class (seems like I can always use 0 here) - 12 page table present? - 13 page entry linear? - 15:14 access: 0 rw, 1 ro, 2 wo - 17:16 target: 0 NV memory, 1 NV memory tiled, 2 PCI, 3 AGP - 31:20 dma adjust (bits 0-11 of the address) - entry[1] - dma limit (size of transfer) - entry[X] - 1 0 readonly, 1 readwrite - 31:12 dma frame address of the page (bits 12-31 of the address) - entry[N] - page table terminator, same value as the first pte, as does nvidia - rivatv uses 0xffffffff - - Non linear page tables need a list of frame addresses afterwards, - the rivatv project has some info on this. - - The method below creates a DMA object in instance RAM and returns a handle - to it that can be used to set up context objects. -*/ -int -nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, - uint64_t offset, uint64_t size, int access, - int target, struct nouveau_gpuobj **gpuobj) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - int ret; - uint32_t is_scatter_gather = 0; - - /* Total number of pages covered by the request. - */ - const unsigned int page_count = (size + PAGE_SIZE - 1) / PAGE_SIZE; - - - DRM_DEBUG("ch%d class=0x%04x offset=0x%llx size=0x%llx\n", - chan->id, class, offset, size); - DRM_DEBUG("access=%d target=%d\n", access, target); - - switch (target) { - case NV_DMA_TARGET_AGP: - offset += dev_priv->gart_info.aper_base; - break; - case NV_DMA_TARGET_PCI_NONLINEAR: - /*assume the "offset" is a virtual memory address*/ - is_scatter_gather = 1; - /*put back the right value*/ - target = NV_DMA_TARGET_PCI; - break; - default: - break; - } - - ret = nouveau_gpuobj_new(dev, chan, - is_scatter_gather ? ((page_count << 2) + 12) : nouveau_gpuobj_class_instmem_size(dev, class), - 16, - NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, - gpuobj); - if (ret) { - DRM_ERROR("Error creating gpuobj: %d\n", ret); - return ret; - } - - if (dev_priv->card_type < NV_50) { - uint32_t frame, adjust, pte_flags = 0; - adjust = offset & 0x00000fff; - if (access != NV_DMA_ACCESS_RO) - pte_flags |= (1<<1); - - if ( ! is_scatter_gather ) - { - frame = offset & ~0x00000fff; - - INSTANCE_WR(*gpuobj, 0, ((1<<12) | (1<<13) | - (adjust << 20) | - (access << 14) | - (target << 16) | - class)); - INSTANCE_WR(*gpuobj, 1, size - 1); - INSTANCE_WR(*gpuobj, 2, frame | pte_flags); - INSTANCE_WR(*gpuobj, 3, frame | pte_flags); - } - else - { - /* Intial page entry in the scatter-gather area that - * corresponds to the base offset - */ - unsigned int idx = offset / PAGE_SIZE; - - uint32_t instance_offset; - unsigned int i; - - if ((idx + page_count) > dev->sg->pages) { - DRM_ERROR("Requested page range exceedes " - "allocated scatter-gather range!"); - return -E2BIG; - } - - DRM_DEBUG("Creating PCI DMA object using virtual zone starting at %#llx, size %d\n", offset, (uint32_t)size); - INSTANCE_WR(*gpuobj, 0, ((1<<12) | (0<<13) | - (adjust << 20) | - (access << 14) | - (target << 16) | - class)); - INSTANCE_WR(*gpuobj, 1, (uint32_t) size-1); - - - /*write starting at the third dword*/ - instance_offset = 2; - - /*for each PAGE, get its bus address, fill in the page table entry, and advance*/ - for (i = 0; i < page_count; i++) { - if (dev->sg->busaddr[idx] == 0) { - dev->sg->busaddr[idx] = - pci_map_page(dev->pdev, - dev->sg->pagelist[idx], - 0, - PAGE_SIZE, - DMA_BIDIRECTIONAL); - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)) - /* Not a 100% sure this is the right kdev in all cases. */ - if (dma_mapping_error(&dev->primary->kdev, dev->sg->busaddr[idx])) { -#else - if (dma_mapping_error(dev->sg->busaddr[idx])) { -#endif - return -ENOMEM; - } - } - - frame = (uint32_t) dev->sg->busaddr[idx]; - INSTANCE_WR(*gpuobj, instance_offset, - frame | pte_flags); - - idx++; - instance_offset ++; - } - } - } else { - uint32_t flags0, flags5; - - if (target == NV_DMA_TARGET_VIDMEM) { - flags0 = 0x00190000; - flags5 = 0x00010000; - } else { - flags0 = 0x7fc00000; - flags5 = 0x00080000; - } - - INSTANCE_WR(*gpuobj, 0, flags0 | class); - INSTANCE_WR(*gpuobj, 1, offset + size - 1); - INSTANCE_WR(*gpuobj, 2, offset); - INSTANCE_WR(*gpuobj, 5, flags5); - } - - (*gpuobj)->engine = NVOBJ_ENGINE_SW; - (*gpuobj)->class = class; - return 0; -} - -int -nouveau_gpuobj_gart_dma_new(struct nouveau_channel *chan, - uint64_t offset, uint64_t size, int access, - struct nouveau_gpuobj **gpuobj, - uint32_t *o_ret) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - int ret; - - if (dev_priv->gart_info.type == NOUVEAU_GART_AGP || - (dev_priv->card_type >= NV_50 && - dev_priv->gart_info.type == NOUVEAU_GART_SGDMA)) { - ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, - offset, size, access, - NV_DMA_TARGET_AGP, gpuobj); - if (o_ret) - *o_ret = 0; - } else - if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA) { - *gpuobj = dev_priv->gart_info.sg_ctxdma; - if (offset & ~0xffffffffULL) { - DRM_ERROR("obj offset exceeds 32-bits\n"); - return -EINVAL; - } - if (o_ret) - *o_ret = (uint32_t)offset; - ret = (*gpuobj != NULL) ? 0 : -EINVAL; - } else { - DRM_ERROR("Invalid GART type %d\n", dev_priv->gart_info.type); - return -EINVAL; - } - - return ret; -} - -/* Context objects in the instance RAM have the following structure. - * On NV40 they are 32 byte long, on NV30 and smaller 16 bytes. - - NV4 - NV30: - - entry[0] - 11:0 class - 12 chroma key enable - 13 user clip enable - 14 swizzle enable - 17:15 patch config: - scrcopy_and, rop_and, blend_and, scrcopy, srccopy_pre, blend_pre - 18 synchronize enable - 19 endian: 1 big, 0 little - 21:20 dither mode - 23 single step enable - 24 patch status: 0 invalid, 1 valid - 25 context_surface 0: 1 valid - 26 context surface 1: 1 valid - 27 context pattern: 1 valid - 28 context rop: 1 valid - 29,30 context beta, beta4 - entry[1] - 7:0 mono format - 15:8 color format - 31:16 notify instance address - entry[2] - 15:0 dma 0 instance address - 31:16 dma 1 instance address - entry[3] - dma method traps - - NV40: - No idea what the exact format is. Here's what can be deducted: - - entry[0]: - 11:0 class (maybe uses more bits here?) - 17 user clip enable - 21:19 patch config - 25 patch status valid ? - entry[1]: - 15:0 DMA notifier (maybe 20:0) - entry[2]: - 15:0 DMA 0 instance (maybe 20:0) - 24 big endian - entry[3]: - 15:0 DMA 1 instance (maybe 20:0) - entry[4]: - entry[5]: - set to 0? -*/ -int -nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class, - struct nouveau_gpuobj **gpuobj) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - int ret; - - DRM_DEBUG("ch%d class=0x%04x\n", chan->id, class); - - ret = nouveau_gpuobj_new(dev, chan, - nouveau_gpuobj_class_instmem_size(dev, class), - 16, - NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, - gpuobj); - if (ret) { - DRM_ERROR("Error creating gpuobj: %d\n", ret); - return ret; - } - - if (dev_priv->card_type >= NV_50) { - INSTANCE_WR(*gpuobj, 0, class); - INSTANCE_WR(*gpuobj, 5, 0x00010000); - } else { - switch (class) { - case NV_CLASS_NULL: - INSTANCE_WR(*gpuobj, 0, 0x00001030); - INSTANCE_WR(*gpuobj, 1, 0xFFFFFFFF); - break; - default: - if (dev_priv->card_type >= NV_40) { - INSTANCE_WR(*gpuobj, 0, class); -#ifdef __BIG_ENDIAN - INSTANCE_WR(*gpuobj, 2, 0x01000000); -#endif - } else { -#ifdef __BIG_ENDIAN - INSTANCE_WR(*gpuobj, 0, class | 0x00080000); -#else - INSTANCE_WR(*gpuobj, 0, class); -#endif - } - } - } - - (*gpuobj)->engine = NVOBJ_ENGINE_GR; - (*gpuobj)->class = class; - return 0; -} - -static int -nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_gpuobj *pramin = NULL; - int size, base, ret; - - DRM_DEBUG("ch%d\n", chan->id); - - /* Base amount for object storage (4KiB enough?) */ - size = 0x1000; - base = 0; - - /* PGRAPH context */ - - if (dev_priv->card_type == NV_50) { - /* Various fixed table thingos */ - size += 0x1400; /* mostly unknown stuff */ - size += 0x4000; /* vm pd */ - base = 0x6000; - /* RAMHT, not sure about setting size yet, 32KiB to be safe */ - size += 0x8000; - /* RAMFC */ - size += 0x1000; - /* PGRAPH context */ - size += 0x70000; - } - - DRM_DEBUG("ch%d PRAMIN size: 0x%08x bytes, base alloc=0x%08x\n", - chan->id, size, base); - ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, size, 0x1000, 0, - &chan->ramin); - if (ret) { - DRM_ERROR("Error allocating channel PRAMIN: %d\n", ret); - return ret; - } - pramin = chan->ramin->gpuobj; - - ret = nouveau_mem_init_heap(&chan->ramin_heap, - pramin->im_pramin->start + base, size); - if (ret) { - DRM_ERROR("Error creating PRAMIN heap: %d\n", ret); - nouveau_gpuobj_ref_del(dev, &chan->ramin); - return ret; - } - - return 0; -} - -int -nouveau_gpuobj_channel_init(struct nouveau_channel *chan, - uint32_t vram_h, uint32_t tt_h) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_gpuobj *vram = NULL, *tt = NULL; - int ret, i; - - INIT_LIST_HEAD(&chan->ramht_refs); - - DRM_DEBUG("ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h); - - /* Reserve a block of PRAMIN for the channel - *XXX: maybe on card_type == NV_50) { - ret = nouveau_gpuobj_channel_init_pramin(chan); - if (ret) - return ret; - } - - /* NV50 VM - * - Allocate per-channel page-directory - * - Point offset 0-512MiB at shared PCIEGART table - * - Point offset 512-1024MiB at shared VRAM table - */ - if (dev_priv->card_type >= NV_50) { - uint32_t vm_offset; - - vm_offset = (dev_priv->chipset & 0xf0) == 0x50 ? 0x1400 : 0x200; - vm_offset += chan->ramin->gpuobj->im_pramin->start; - if ((ret = nouveau_gpuobj_new_fake(dev, vm_offset, ~0, 0x4000, - 0, &chan->vm_pd, NULL))) - return ret; - for (i=0; i<0x4000; i+=8) { - INSTANCE_WR(chan->vm_pd, (i+0)/4, 0x00000000); - INSTANCE_WR(chan->vm_pd, (i+4)/4, 0xdeadcafe); - } - - if ((ret = nouveau_gpuobj_ref_add(dev, NULL, 0, - dev_priv->gart_info.sg_ctxdma, - &chan->vm_gart_pt))) - return ret; - INSTANCE_WR(chan->vm_pd, (0+0)/4, - chan->vm_gart_pt->instance | 0x03); - INSTANCE_WR(chan->vm_pd, (0+4)/4, 0x00000000); - - if ((ret = nouveau_gpuobj_ref_add(dev, NULL, 0, - dev_priv->vm_vram_pt, - &chan->vm_vram_pt))) - return ret; - INSTANCE_WR(chan->vm_pd, (8+0)/4, - chan->vm_vram_pt->instance | 0x61); - INSTANCE_WR(chan->vm_pd, (8+4)/4, 0x00000000); - } - - /* RAMHT */ - if (dev_priv->card_type < NV_50) { - ret = nouveau_gpuobj_ref_add(dev, NULL, 0, dev_priv->ramht, - &chan->ramht); - if (ret) - return ret; - } else { - ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, - 0x8000, 16, - NVOBJ_FLAG_ZERO_ALLOC, - &chan->ramht); - if (ret) - return ret; - } - - /* VRAM ctxdma */ - if (dev_priv->card_type >= NV_50) { - ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, - 0, 0x100000000ULL, - NV_DMA_ACCESS_RW, - NV_DMA_TARGET_AGP, &vram); - if (ret) { - DRM_ERROR("Error creating VRAM ctxdma: %d\n", ret); - return ret; - } - } else - if ((ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, - 0, dev_priv->fb_available_size, - NV_DMA_ACCESS_RW, - NV_DMA_TARGET_VIDMEM, &vram))) { - DRM_ERROR("Error creating VRAM ctxdma: %d\n", ret); - return ret; - } - - if ((ret = nouveau_gpuobj_ref_add(dev, chan, vram_h, vram, NULL))) { - DRM_ERROR("Error referencing VRAM ctxdma: %d\n", ret); - return ret; - } - - /* TT memory ctxdma */ - if (dev_priv->card_type >= NV_50) { - tt = vram; - } else - if (dev_priv->gart_info.type != NOUVEAU_GART_NONE) { - ret = nouveau_gpuobj_gart_dma_new(chan, 0, - dev_priv->gart_info.aper_size, - NV_DMA_ACCESS_RW, &tt, NULL); - } else - if (dev_priv->pci_heap) { - ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, - 0, dev->sg->pages * PAGE_SIZE, - NV_DMA_ACCESS_RW, - NV_DMA_TARGET_PCI_NONLINEAR, &tt); - } else { - DRM_ERROR("Invalid GART type %d\n", dev_priv->gart_info.type); - ret = -EINVAL; - } - - if (ret) { - DRM_ERROR("Error creating TT ctxdma: %d\n", ret); - return ret; - } - - ret = nouveau_gpuobj_ref_add(dev, chan, tt_h, tt, NULL); - if (ret) { - DRM_ERROR("Error referencing TT ctxdma: %d\n", ret); - return ret; - } - - return 0; -} - -void -nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct list_head *entry, *tmp; - struct nouveau_gpuobj_ref *ref; - - DRM_DEBUG("ch%d\n", chan->id); - - list_for_each_safe(entry, tmp, &chan->ramht_refs) { - ref = list_entry(entry, struct nouveau_gpuobj_ref, list); - - nouveau_gpuobj_ref_del(dev, &ref); - } - - nouveau_gpuobj_ref_del(dev, &chan->ramht); - - nouveau_gpuobj_del(dev, &chan->vm_pd); - nouveau_gpuobj_ref_del(dev, &chan->vm_gart_pt); - nouveau_gpuobj_ref_del(dev, &chan->vm_vram_pt); - - if (chan->ramin_heap) - nouveau_mem_takedown(&chan->ramin_heap); - if (chan->ramin) - nouveau_gpuobj_ref_del(dev, &chan->ramin); - -} - -int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct nouveau_channel *chan; - struct drm_nouveau_grobj_alloc *init = data; - struct nouveau_gpuobj *gr = NULL; - int ret; - - NOUVEAU_CHECK_INITIALISED_WITH_RETURN; - NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(init->channel, file_priv, chan); - - //FIXME: check args, only allow trusted objects to be created - - if (init->handle == ~0) - return -EINVAL; - - if (nouveau_gpuobj_ref_find(chan, init->handle, NULL) == 0) - return -EEXIST; - - ret = nouveau_gpuobj_gr_new(chan, init->class, &gr); - if (ret) { - DRM_ERROR("Error creating gr object: %d (%d/0x%08x)\n", - ret, init->channel, init->handle); - return ret; - } - - if ((ret = nouveau_gpuobj_ref_add(dev, chan, init->handle, gr, NULL))) { - DRM_ERROR("Error referencing gr object: %d (%d/0x%08x\n)", - ret, init->channel, init->handle); - nouveau_gpuobj_del(dev, &gr); - return ret; - } - - return 0; -} - -int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_nouveau_gpuobj_free *objfree = data; - struct nouveau_gpuobj_ref *ref; - struct nouveau_channel *chan; - int ret; - - NOUVEAU_CHECK_INITIALISED_WITH_RETURN; - NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(objfree->channel, file_priv, chan); - - if ((ret = nouveau_gpuobj_ref_find(chan, objfree->handle, &ref))) - return ret; - nouveau_gpuobj_ref_del(dev, &ref); - - return 0; -} diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h deleted file mode 100644 index 695bf5d7..00000000 --- a/shared-core/nouveau_reg.h +++ /dev/null @@ -1,601 +0,0 @@ - - -#define NV03_BOOT_0 0x00100000 -# define NV03_BOOT_0_RAM_AMOUNT 0x00000003 -# define NV03_BOOT_0_RAM_AMOUNT_8MB 0x00000000 -# define NV03_BOOT_0_RAM_AMOUNT_2MB 0x00000001 -# define NV03_BOOT_0_RAM_AMOUNT_4MB 0x00000002 -# define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM 0x00000003 -# define NV04_BOOT_0_RAM_AMOUNT_32MB 0x00000000 -# define NV04_BOOT_0_RAM_AMOUNT_4MB 0x00000001 -# define NV04_BOOT_0_RAM_AMOUNT_8MB 0x00000002 -# define NV04_BOOT_0_RAM_AMOUNT_16MB 0x00000003 - -#define NV_RAMIN 0x00700000 - -#define NV_RAMHT_HANDLE_OFFSET 0 -#define NV_RAMHT_CONTEXT_OFFSET 4 -# define NV_RAMHT_CONTEXT_VALID (1<<31) -# define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24 -# define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16 -# define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0 -# define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1 -# define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0 -# define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23 -# define NV40_RAMHT_CONTEXT_ENGINE_SHIFT 20 -# define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT 0 - -/* DMA object defines */ -#define NV_DMA_ACCESS_RW 0 -#define NV_DMA_ACCESS_RO 1 -#define NV_DMA_ACCESS_WO 2 -#define NV_DMA_TARGET_VIDMEM 0 -#define NV_DMA_TARGET_PCI 2 -#define NV_DMA_TARGET_AGP 3 -/*The following is not a real value used by nvidia cards, it's changed by nouveau_object_dma_create*/ -#define NV_DMA_TARGET_PCI_NONLINEAR 8 - -/* Some object classes we care about in the drm */ -#define NV_CLASS_DMA_FROM_MEMORY 0x00000002 -#define NV_CLASS_DMA_TO_MEMORY 0x00000003 -#define NV_CLASS_NULL 0x00000030 -#define NV_CLASS_DMA_IN_MEMORY 0x0000003D - -#define NV03_USER(i) (0x00800000+(i*NV03_USER_SIZE)) -#define NV03_USER__SIZE 16 -#define NV10_USER__SIZE 32 -#define NV03_USER_SIZE 0x00010000 -#define NV03_USER_DMA_PUT(i) (0x00800040+(i*NV03_USER_SIZE)) -#define NV03_USER_DMA_PUT__SIZE 16 -#define NV10_USER_DMA_PUT__SIZE 32 -#define NV03_USER_DMA_GET(i) (0x00800044+(i*NV03_USER_SIZE)) -#define NV03_USER_DMA_GET__SIZE 16 -#define NV10_USER_DMA_GET__SIZE 32 -#define NV03_USER_REF_CNT(i) (0x00800048+(i*NV03_USER_SIZE)) -#define NV03_USER_REF_CNT__SIZE 16 -#define NV10_USER_REF_CNT__SIZE 32 - -#define NV40_USER(i) (0x00c00000+(i*NV40_USER_SIZE)) -#define NV40_USER_SIZE 0x00001000 -#define NV40_USER_DMA_PUT(i) (0x00c00040+(i*NV40_USER_SIZE)) -#define NV40_USER_DMA_PUT__SIZE 32 -#define NV40_USER_DMA_GET(i) (0x00c00044+(i*NV40_USER_SIZE)) -#define NV40_USER_DMA_GET__SIZE 32 -#define NV40_USER_REF_CNT(i) (0x00c00048+(i*NV40_USER_SIZE)) -#define NV40_USER_REF_CNT__SIZE 32 - -#define NV50_USER(i) (0x00c00000+(i*NV50_USER_SIZE)) -#define NV50_USER_SIZE 0x00002000 -#define NV50_USER_DMA_PUT(i) (0x00c00040+(i*NV50_USER_SIZE)) -#define NV50_USER_DMA_PUT__SIZE 128 -#define NV50_USER_DMA_GET(i) (0x00c00044+(i*NV50_USER_SIZE)) -#define NV50_USER_DMA_GET__SIZE 128 -/*XXX: I don't think this actually exists.. */ -#define NV50_USER_REF_CNT(i) (0x00c00048+(i*NV50_USER_SIZE)) -#define NV50_USER_REF_CNT__SIZE 128 - -#define NV03_FIFO_SIZE 0x8000UL - -#define NV03_PMC_BOOT_0 0x00000000 -#define NV03_PMC_BOOT_1 0x00000004 -#define NV03_PMC_INTR_0 0x00000100 -# define NV_PMC_INTR_0_PFIFO_PENDING (1<< 8) -# define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12) -# define NV_PMC_INTR_0_NV50_I2C_PENDING (1<<21) -# define NV_PMC_INTR_0_CRTC0_PENDING (1<<24) -# define NV_PMC_INTR_0_CRTC1_PENDING (1<<25) -# define NV_PMC_INTR_0_NV50_DISPLAY_PENDING (1<<26) -# define NV_PMC_INTR_0_CRTCn_PENDING (3<<24) -#define NV03_PMC_INTR_EN_0 0x00000140 -# define NV_PMC_INTR_EN_0_MASTER_ENABLE (1<< 0) -#define NV03_PMC_ENABLE 0x00000200 -# define NV_PMC_ENABLE_PFIFO (1<< 8) -# define NV_PMC_ENABLE_PGRAPH (1<<12) -/* Disabling the below bit breaks newer (G7X only?) mobile chipsets, - * the card will hang early on in the X init process. - */ -# define NV_PMC_ENABLE_UNK13 (1<<13) - -#define NV_PBUS_DEBUG_DUALHEAD_CTL 0x000010F0 - -#define NV40_PMC_BACKLIGHT 0x000015f0 -# define NV40_PMC_BACKLIGHT_MASK 0x001f0000 -#define NV40_PMC_1700 0x00001700 -#define NV40_PMC_1704 0x00001704 -#define NV40_PMC_1708 0x00001708 -#define NV40_PMC_170C 0x0000170C - -/* probably PMC ? */ -#define NV50_PUNK_BAR0_PRAMIN 0x00001700 -#define NV50_PUNK_BAR_CFG_BASE 0x00001704 -#define NV50_PUNK_BAR_CFG_BASE_VALID (1<<30) -#define NV50_PUNK_BAR1_CTXDMA 0x00001708 -#define NV50_PUNK_BAR1_CTXDMA_VALID (1<<31) -#define NV50_PUNK_BAR3_CTXDMA 0x0000170C -#define NV50_PUNK_BAR3_CTXDMA_VALID (1<<31) -#define NV50_PUNK_UNK1710 0x00001710 - -#define NV04_PBUS_PCI_NV_1 0x00001804 -#define NV04_PBUS_PCI_NV_19 0x0000184C - -#define NV04_PTIMER_INTR_0 0x00009100 -#define NV04_PTIMER_INTR_EN_0 0x00009140 -#define NV04_PTIMER_NUMERATOR 0x00009200 -#define NV04_PTIMER_DENOMINATOR 0x00009210 -#define NV04_PTIMER_TIME_0 0x00009400 -#define NV04_PTIMER_TIME_1 0x00009410 -#define NV04_PTIMER_ALARM_0 0x00009420 - -#define NV50_I2C_CONTROLLER 0x0000E054 - -#define NV04_PFB_CFG0 0x00100200 -#define NV04_PFB_CFG1 0x00100204 -#define NV10_PFB_CSTATUS 0x0010020C -# define NV10_PFB_CSTATUS_RAM_AMOUNT_MB_MASK 0xfff00000 -# define NV10_PFB_CSTATUS_RAM_AMOUNT_MB_SHIFT 20 -#define NV10_PFB_TILE(i) (0x00100240 + (i*16)) -#define NV10_PFB_TILE__SIZE 8 -#define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16)) -#define NV10_PFB_TSIZE(i) (0x00100248 + (i*16)) -#define NV10_PFB_TSTATUS(i) (0x0010024C + (i*16)) -#define NV10_PFB_CLOSE_PAGE2 0x0010033C -#define NV40_PFB_TILE(i) (0x00100600 + (i*16)) -#define NV40_PFB_TILE__SIZE_0 12 -#define NV40_PFB_TILE__SIZE_1 15 -#define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16)) -#define NV40_PFB_TSIZE(i) (0x00100608 + (i*16)) -#define NV40_PFB_TSTATUS(i) (0x0010060C + (i*16)) -#define NV40_PFB_UNK_800 0x00100800 - -#define NV04_PGRAPH_DEBUG_0 0x00400080 -#define NV04_PGRAPH_DEBUG_1 0x00400084 -#define NV04_PGRAPH_DEBUG_2 0x00400088 -#define NV04_PGRAPH_DEBUG_3 0x0040008c -#define NV10_PGRAPH_DEBUG_4 0x00400090 -#define NV03_PGRAPH_INTR 0x00400100 -#define NV03_PGRAPH_NSTATUS 0x00400104 -# define NV04_PGRAPH_NSTATUS_STATE_IN_USE (1<<11) -# define NV04_PGRAPH_NSTATUS_INVALID_STATE (1<<12) -# define NV04_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<13) -# define NV04_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<14) -# define NV10_PGRAPH_NSTATUS_STATE_IN_USE (1<<23) -# define NV10_PGRAPH_NSTATUS_INVALID_STATE (1<<24) -# define NV10_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<25) -# define NV10_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<26) -#define NV03_PGRAPH_NSOURCE 0x00400108 -# define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<< 0) -# define NV03_PGRAPH_NSOURCE_DATA_ERROR (1<< 1) -# define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR (1<< 2) -# define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION (1<< 3) -# define NV03_PGRAPH_NSOURCE_LIMIT_COLOR (1<< 4) -# define NV03_PGRAPH_NSOURCE_LIMIT_ZETA (1<< 5) -# define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD (1<< 6) -# define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION (1<< 7) -# define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION (1<< 8) -# define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION (1<< 9) -# define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION (1<<10) -# define NV03_PGRAPH_NSOURCE_STATE_INVALID (1<<11) -# define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY (1<<12) -# define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE (1<<13) -# define NV03_PGRAPH_NSOURCE_METHOD_CNT (1<<14) -# define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION (1<<15) -# define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION (1<<16) -# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A (1<<17) -# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B (1<<18) -#define NV03_PGRAPH_INTR_EN 0x00400140 -#define NV40_PGRAPH_INTR_EN 0x0040013C -# define NV_PGRAPH_INTR_NOTIFY (1<< 0) -# define NV_PGRAPH_INTR_MISSING_HW (1<< 4) -# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12) -# define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16) -# define NV_PGRAPH_INTR_ERROR (1<<20) -#define NV10_PGRAPH_CTX_CONTROL 0x00400144 -#define NV10_PGRAPH_CTX_USER 0x00400148 -#define NV10_PGRAPH_CTX_SWITCH1 0x0040014C -#define NV10_PGRAPH_CTX_SWITCH2 0x00400150 -#define NV10_PGRAPH_CTX_SWITCH3 0x00400154 -#define NV10_PGRAPH_CTX_SWITCH4 0x00400158 -#define NV10_PGRAPH_CTX_SWITCH5 0x0040015C -#define NV04_PGRAPH_CTX_SWITCH1 0x00400160 -#define NV10_PGRAPH_CTX_CACHE1 0x00400160 -#define NV04_PGRAPH_CTX_SWITCH2 0x00400164 -#define NV04_PGRAPH_CTX_SWITCH3 0x00400168 -#define NV04_PGRAPH_CTX_SWITCH4 0x0040016C -#define NV04_PGRAPH_CTX_CONTROL 0x00400170 -#define NV04_PGRAPH_CTX_USER 0x00400174 -#define NV04_PGRAPH_CTX_CACHE1 0x00400180 -#define NV10_PGRAPH_CTX_CACHE2 0x00400180 -#define NV03_PGRAPH_CTX_CONTROL 0x00400190 -#define NV03_PGRAPH_CTX_USER 0x00400194 -#define NV04_PGRAPH_CTX_CACHE2 0x004001A0 -#define NV10_PGRAPH_CTX_CACHE3 0x004001A0 -#define NV04_PGRAPH_CTX_CACHE3 0x004001C0 -#define NV10_PGRAPH_CTX_CACHE4 0x004001C0 -#define NV04_PGRAPH_CTX_CACHE4 0x004001E0 -#define NV10_PGRAPH_CTX_CACHE5 0x004001E0 -#define NV40_PGRAPH_CTXCTL_0304 0x00400304 -#define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001 -#define NV40_PGRAPH_CTXCTL_UCODE_STAT 0x00400308 -#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK 0xff000000 -#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT 24 -#define NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK 0x00ffffff -#define NV40_PGRAPH_CTXCTL_0310 0x00400310 -#define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE 0x00000020 -#define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD 0x00000040 -#define NV40_PGRAPH_CTXCTL_030C 0x0040030c -#define NV40_PGRAPH_CTXCTL_UCODE_INDEX 0x00400324 -#define NV40_PGRAPH_CTXCTL_UCODE_DATA 0x00400328 -#define NV40_PGRAPH_CTXCTL_CUR 0x0040032c -#define NV40_PGRAPH_CTXCTL_CUR_LOADED 0x01000000 -#define NV40_PGRAPH_CTXCTL_CUR_INST_MASK 0x000FFFFF -#define NV03_PGRAPH_ABS_X_RAM 0x00400400 -#define NV03_PGRAPH_ABS_Y_RAM 0x00400480 -#define NV03_PGRAPH_X_MISC 0x00400500 -#define NV03_PGRAPH_Y_MISC 0x00400504 -#define NV04_PGRAPH_VALID1 0x00400508 -#define NV04_PGRAPH_SOURCE_COLOR 0x0040050C -#define NV04_PGRAPH_MISC24_0 0x00400510 -#define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514 -#define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518 -#define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C -#define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520 -#define NV03_PGRAPH_CLIPX_0 0x00400524 -#define NV03_PGRAPH_CLIPX_1 0x00400528 -#define NV03_PGRAPH_CLIPY_0 0x0040052C -#define NV03_PGRAPH_CLIPY_1 0x00400530 -#define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534 -#define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538 -#define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C -#define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540 -#define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544 -#define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548 -#define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 -#define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 -#define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 -#define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C -#define NV04_PGRAPH_MISC24_1 0x00400570 -#define NV04_PGRAPH_MISC24_2 0x00400574 -#define NV04_PGRAPH_VALID2 0x00400578 -#define NV04_PGRAPH_PASSTHRU_0 0x0040057C -#define NV04_PGRAPH_PASSTHRU_1 0x00400580 -#define NV04_PGRAPH_PASSTHRU_2 0x00400584 -#define NV10_PGRAPH_DIMX_TEXTURE 0x00400588 -#define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C -#define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590 -#define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594 -#define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598 -#define NV04_PGRAPH_COMBINE_1_COLOR 0x0040059C -#define NV04_PGRAPH_FORMAT_0 0x004005A8 -#define NV04_PGRAPH_FORMAT_1 0x004005AC -#define NV04_PGRAPH_FILTER_0 0x004005B0 -#define NV04_PGRAPH_FILTER_1 0x004005B4 -#define NV03_PGRAPH_MONO_COLOR0 0x00400600 -#define NV04_PGRAPH_ROP3 0x00400604 -#define NV04_PGRAPH_BETA_AND 0x00400608 -#define NV04_PGRAPH_BETA_PREMULT 0x0040060C -#define NV04_PGRAPH_LIMIT_VIOL_PIX 0x00400610 -#define NV04_PGRAPH_FORMATS 0x00400618 -#define NV10_PGRAPH_DEBUG_2 0x00400620 -#define NV04_PGRAPH_BOFFSET0 0x00400640 -#define NV04_PGRAPH_BOFFSET1 0x00400644 -#define NV04_PGRAPH_BOFFSET2 0x00400648 -#define NV04_PGRAPH_BOFFSET3 0x0040064C -#define NV04_PGRAPH_BOFFSET4 0x00400650 -#define NV04_PGRAPH_BOFFSET5 0x00400654 -#define NV04_PGRAPH_BBASE0 0x00400658 -#define NV04_PGRAPH_BBASE1 0x0040065C -#define NV04_PGRAPH_BBASE2 0x00400660 -#define NV04_PGRAPH_BBASE3 0x00400664 -#define NV04_PGRAPH_BBASE4 0x00400668 -#define NV04_PGRAPH_BBASE5 0x0040066C -#define NV04_PGRAPH_BPITCH0 0x00400670 -#define NV04_PGRAPH_BPITCH1 0x00400674 -#define NV04_PGRAPH_BPITCH2 0x00400678 -#define NV04_PGRAPH_BPITCH3 0x0040067C -#define NV04_PGRAPH_BPITCH4 0x00400680 -#define NV04_PGRAPH_BLIMIT0 0x00400684 -#define NV04_PGRAPH_BLIMIT1 0x00400688 -#define NV04_PGRAPH_BLIMIT2 0x0040068C -#define NV04_PGRAPH_BLIMIT3 0x00400690 -#define NV04_PGRAPH_BLIMIT4 0x00400694 -#define NV04_PGRAPH_BLIMIT5 0x00400698 -#define NV04_PGRAPH_BSWIZZLE2 0x0040069C -#define NV04_PGRAPH_BSWIZZLE5 0x004006A0 -#define NV03_PGRAPH_STATUS 0x004006B0 -#define NV04_PGRAPH_STATUS 0x00400700 -#define NV04_PGRAPH_TRAPPED_ADDR 0x00400704 -#define NV04_PGRAPH_TRAPPED_DATA 0x00400708 -#define NV04_PGRAPH_SURFACE 0x0040070C -#define NV10_PGRAPH_TRAPPED_DATA_HIGH 0x0040070C -#define NV04_PGRAPH_STATE 0x00400710 -#define NV10_PGRAPH_SURFACE 0x00400710 -#define NV04_PGRAPH_NOTIFY 0x00400714 -#define NV10_PGRAPH_STATE 0x00400714 -#define NV10_PGRAPH_NOTIFY 0x00400718 - -#define NV04_PGRAPH_FIFO 0x00400720 - -#define NV04_PGRAPH_BPIXEL 0x00400724 -#define NV10_PGRAPH_RDI_INDEX 0x00400750 -#define NV04_PGRAPH_FFINTFC_ST2 0x00400754 -#define NV10_PGRAPH_RDI_DATA 0x00400754 -#define NV04_PGRAPH_DMA_PITCH 0x00400760 -#define NV10_PGRAPH_FFINTFC_ST2 0x00400764 -#define NV04_PGRAPH_DVD_COLORFMT 0x00400764 -#define NV04_PGRAPH_SCALED_FORMAT 0x00400768 -#define NV10_PGRAPH_DMA_PITCH 0x00400770 -#define NV10_PGRAPH_DVD_COLORFMT 0x00400774 -#define NV10_PGRAPH_SCALED_FORMAT 0x00400778 -#define NV20_PGRAPH_CHANNEL_CTX_TABLE 0x00400780 -#define NV20_PGRAPH_CHANNEL_CTX_POINTER 0x00400784 -#define NV20_PGRAPH_CHANNEL_CTX_XFER 0x00400788 -#define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD 0x00000001 -#define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE 0x00000002 -#define NV04_PGRAPH_PATT_COLOR0 0x00400800 -#define NV04_PGRAPH_PATT_COLOR1 0x00400804 -#define NV04_PGRAPH_PATTERN 0x00400808 -#define NV04_PGRAPH_PATTERN_SHAPE 0x00400810 -#define NV04_PGRAPH_CHROMA 0x00400814 -#define NV04_PGRAPH_CONTROL0 0x00400818 -#define NV04_PGRAPH_CONTROL1 0x0040081C -#define NV04_PGRAPH_CONTROL2 0x00400820 -#define NV04_PGRAPH_BLEND 0x00400824 -#define NV04_PGRAPH_STORED_FMT 0x00400830 -#define NV04_PGRAPH_PATT_COLORRAM 0x00400900 -#define NV40_PGRAPH_TILE0(i) (0x00400900 + (i*16)) -#define NV40_PGRAPH_TLIMIT0(i) (0x00400904 + (i*16)) -#define NV40_PGRAPH_TSIZE0(i) (0x00400908 + (i*16)) -#define NV40_PGRAPH_TSTATUS0(i) (0x0040090C + (i*16)) -#define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16)) -#define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16)) -#define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16)) -#define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16)) -#define NV04_PGRAPH_U_RAM 0x00400D00 -#define NV47_PGRAPH_TILE0(i) (0x00400D00 + (i*16)) -#define NV47_PGRAPH_TLIMIT0(i) (0x00400D04 + (i*16)) -#define NV47_PGRAPH_TSIZE0(i) (0x00400D08 + (i*16)) -#define NV47_PGRAPH_TSTATUS0(i) (0x00400D0C + (i*16)) -#define NV04_PGRAPH_V_RAM 0x00400D40 -#define NV04_PGRAPH_W_RAM 0x00400D80 -#define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40 -#define NV10_PGRAPH_COMBINER1_IN_ALPHA 0x00400E44 -#define NV10_PGRAPH_COMBINER0_IN_RGB 0x00400E48 -#define NV10_PGRAPH_COMBINER1_IN_RGB 0x00400E4C -#define NV10_PGRAPH_COMBINER_COLOR0 0x00400E50 -#define NV10_PGRAPH_COMBINER_COLOR1 0x00400E54 -#define NV10_PGRAPH_COMBINER0_OUT_ALPHA 0x00400E58 -#define NV10_PGRAPH_COMBINER1_OUT_ALPHA 0x00400E5C -#define NV10_PGRAPH_COMBINER0_OUT_RGB 0x00400E60 -#define NV10_PGRAPH_COMBINER1_OUT_RGB 0x00400E64 -#define NV10_PGRAPH_COMBINER_FINAL0 0x00400E68 -#define NV10_PGRAPH_COMBINER_FINAL1 0x00400E6C -#define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00 -#define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20 -#define NV10_PGRAPH_XFMODE0 0x00400F40 -#define NV10_PGRAPH_XFMODE1 0x00400F44 -#define NV10_PGRAPH_GLOBALSTATE0 0x00400F48 -#define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C -#define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50 -#define NV10_PGRAPH_PIPE_DATA 0x00400F54 -#define NV04_PGRAPH_DMA_START_0 0x00401000 -#define NV04_PGRAPH_DMA_START_1 0x00401004 -#define NV04_PGRAPH_DMA_LENGTH 0x00401008 -#define NV04_PGRAPH_DMA_MISC 0x0040100C -#define NV04_PGRAPH_DMA_DATA_0 0x00401020 -#define NV04_PGRAPH_DMA_DATA_1 0x00401024 -#define NV04_PGRAPH_DMA_RM 0x00401030 -#define NV04_PGRAPH_DMA_A_XLATE_INST 0x00401040 -#define NV04_PGRAPH_DMA_A_CONTROL 0x00401044 -#define NV04_PGRAPH_DMA_A_LIMIT 0x00401048 -#define NV04_PGRAPH_DMA_A_TLB_PTE 0x0040104C -#define NV04_PGRAPH_DMA_A_TLB_TAG 0x00401050 -#define NV04_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054 -#define NV04_PGRAPH_DMA_A_OFFSET 0x00401058 -#define NV04_PGRAPH_DMA_A_SIZE 0x0040105C -#define NV04_PGRAPH_DMA_A_Y_SIZE 0x00401060 -#define NV04_PGRAPH_DMA_B_XLATE_INST 0x00401080 -#define NV04_PGRAPH_DMA_B_CONTROL 0x00401084 -#define NV04_PGRAPH_DMA_B_LIMIT 0x00401088 -#define NV04_PGRAPH_DMA_B_TLB_PTE 0x0040108C -#define NV04_PGRAPH_DMA_B_TLB_TAG 0x00401090 -#define NV04_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094 -#define NV04_PGRAPH_DMA_B_OFFSET 0x00401098 -#define NV04_PGRAPH_DMA_B_SIZE 0x0040109C -#define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0 -#define NV40_PGRAPH_TILE1(i) (0x00406900 + (i*16)) -#define NV40_PGRAPH_TLIMIT1(i) (0x00406904 + (i*16)) -#define NV40_PGRAPH_TSIZE1(i) (0x00406908 + (i*16)) -#define NV40_PGRAPH_TSTATUS1(i) (0x0040690C + (i*16)) - -#define NV_PCRTC_GPIO_EXT 0x0060081C - -/* It's a guess that this works on NV03. Confirmed on NV04, though */ -#define NV04_PFIFO_DELAY_0 0x00002040 -#define NV04_PFIFO_DMA_TIMESLICE 0x00002044 -#define NV04_PFIFO_NEXT_CHANNEL 0x00002050 -#define NV03_PFIFO_INTR_0 0x00002100 -#define NV03_PFIFO_INTR_EN_0 0x00002140 -# define NV_PFIFO_INTR_CACHE_ERROR (1<< 0) -# define NV_PFIFO_INTR_RUNOUT (1<< 4) -# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<< 8) -# define NV_PFIFO_INTR_DMA_PUSHER (1<<12) -# define NV_PFIFO_INTR_DMA_PT (1<<16) -# define NV_PFIFO_INTR_SEMAPHORE (1<<20) -# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24) -#define NV03_PFIFO_RAMHT 0x00002210 -#define NV03_PFIFO_RAMFC 0x00002214 -#define NV03_PFIFO_RAMRO 0x00002218 -#define NV40_PFIFO_RAMFC 0x00002220 -#define NV03_PFIFO_CACHES 0x00002500 -#define NV04_PFIFO_MODE 0x00002504 -#define NV04_PFIFO_DMA 0x00002508 -#define NV04_PFIFO_SIZE 0x0000250c -#define NV50_PFIFO_CTX_TABLE(c) (0x2600+(c)*4) -#define NV50_PFIFO_CTX_TABLE__SIZE 128 -#define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED (1<<31) -#define NV50_PFIFO_CTX_TABLE_UNK30_BAD (1<<30) -#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 0x0FFFFFFF -#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 0x00FFFFFF -#define NV03_PFIFO_CACHE0_PUSH0 0x00003000 -#define NV03_PFIFO_CACHE0_PULL0 0x00003040 -#define NV04_PFIFO_CACHE0_PULL0 0x00003050 -#define NV04_PFIFO_CACHE0_PULL1 0x00003054 -#define NV03_PFIFO_CACHE1_PUSH0 0x00003200 -#define NV03_PFIFO_CACHE1_PUSH1 0x00003204 -#define NV03_PFIFO_CACHE1_PUSH1_DMA (1<<8) -#define NV40_PFIFO_CACHE1_PUSH1_DMA (1<<16) -#define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000000f -#define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000001f -#define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000007f -#define NV03_PFIFO_CACHE1_PUT 0x00003210 -#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220 -#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000 -# define NV_PFIFO_CACHE1_ENDIAN 0x80000000 -# define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF -# define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000 -#define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228 -#define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c -#define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230 -#define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240 -#define NV04_PFIFO_CACHE1_DMA_GET 0x00003244 -#define NV10_PFIFO_CACHE1_REF_CNT 0x00003248 -#define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C -#define NV03_PFIFO_CACHE1_PULL0 0x00003240 -#define NV04_PFIFO_CACHE1_PULL0 0x00003250 -#define NV03_PFIFO_CACHE1_PULL1 0x00003250 -#define NV04_PFIFO_CACHE1_PULL1 0x00003254 -#define NV04_PFIFO_CACHE1_HASH 0x00003258 -#define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260 -#define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264 -#define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268 -#define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C -#define NV03_PFIFO_CACHE1_GET 0x00003270 -#define NV04_PFIFO_CACHE1_ENGINE 0x00003280 -#define NV04_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0 -#define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0 -#define NV40_PFIFO_UNK32E4 0x000032E4 -#define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8)) -#define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8)) -#define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8)) -#define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8)) - -#define NV_CRTC0_INTSTAT 0x00600100 -#define NV_CRTC0_INTEN 0x00600140 -#define NV_CRTC1_INTSTAT 0x00602100 -#define NV_CRTC1_INTEN 0x00602140 -# define NV_CRTC_INTR_VBLANK (1<<0) - -/* This name is a partial guess. */ -#define NV50_DISPLAY_SUPERVISOR 0x00610024 - -#define NV50_PDISPLAY_BACKLIGHT 0x0061c084 -# define NV50_PDISPLAY_BACKLIGHT_ENABLE 0x80000000 - -/* Fifo commands. These are not regs, neither masks */ -#define NV03_FIFO_CMD_JUMP 0x20000000 -#define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc -#define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK)) - -/* RAMFC offsets */ -#define NV04_RAMFC_DMA_PUT 0x00 -#define NV04_RAMFC_DMA_GET 0x04 -#define NV04_RAMFC_DMA_INSTANCE 0x08 -#define NV04_RAMFC_DMA_STATE 0x0C -#define NV04_RAMFC_DMA_FETCH 0x10 -#define NV04_RAMFC_ENGINE 0x14 -#define NV04_RAMFC_PULL1_ENGINE 0x18 - -#define NV10_RAMFC_DMA_PUT 0x00 -#define NV10_RAMFC_DMA_GET 0x04 -#define NV10_RAMFC_REF_CNT 0x08 -#define NV10_RAMFC_DMA_INSTANCE 0x0C -#define NV10_RAMFC_DMA_STATE 0x10 -#define NV10_RAMFC_DMA_FETCH 0x14 -#define NV10_RAMFC_ENGINE 0x18 -#define NV10_RAMFC_PULL1_ENGINE 0x1C -#define NV10_RAMFC_ACQUIRE_VALUE 0x20 -#define NV10_RAMFC_ACQUIRE_TIMESTAMP 0x24 -#define NV10_RAMFC_ACQUIRE_TIMEOUT 0x28 -#define NV10_RAMFC_SEMAPHORE 0x2C -#define NV10_RAMFC_DMA_SUBROUTINE 0x30 - -#define NV40_RAMFC_DMA_PUT 0x00 -#define NV40_RAMFC_DMA_GET 0x04 -#define NV40_RAMFC_REF_CNT 0x08 -#define NV40_RAMFC_DMA_INSTANCE 0x0C -#define NV40_RAMFC_DMA_DCOUNT /* ? */ 0x10 -#define NV40_RAMFC_DMA_STATE 0x14 -#define NV40_RAMFC_DMA_FETCH 0x18 -#define NV40_RAMFC_ENGINE 0x1C -#define NV40_RAMFC_PULL1_ENGINE 0x20 -#define NV40_RAMFC_ACQUIRE_VALUE 0x24 -#define NV40_RAMFC_ACQUIRE_TIMESTAMP 0x28 -#define NV40_RAMFC_ACQUIRE_TIMEOUT 0x2C -#define NV40_RAMFC_SEMAPHORE 0x30 -#define NV40_RAMFC_DMA_SUBROUTINE 0x34 -#define NV40_RAMFC_GRCTX_INSTANCE /* guess */ 0x38 -#define NV40_RAMFC_DMA_TIMESLICE 0x3C -#define NV40_RAMFC_UNK_40 0x40 -#define NV40_RAMFC_UNK_44 0x44 -#define NV40_RAMFC_UNK_48 0x48 -#define NV40_RAMFC_UNK_4C 0x4C -#define NV40_RAMFC_UNK_50 0x50 - diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c deleted file mode 100644 index b2ad747a..00000000 --- a/shared-core/nouveau_state.c +++ /dev/null @@ -1,897 +0,0 @@ -/* - * Copyright 2005 Stephane Marchesin - * Copyright 2008 Stuart Bennett - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "drmP.h" -#include "drm.h" -#include "drm_sarea.h" -#include "nouveau_drv.h" -#include "nouveau_drm.h" - -static int nouveau_init_card_mappings(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int ret; - - /* resource 0 is mmio regs */ - /* resource 1 is linear FB */ - /* resource 2 is RAMIN (mmio regs + 0x1000000) */ - /* resource 6 is bios */ - - /* map the mmio regs */ - ret = drm_addmap(dev, drm_get_resource_start(dev, 0), - drm_get_resource_len(dev, 0), - _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio); - if (ret) { - DRM_ERROR("Unable to initialize the mmio mapping (%d). " - "Please report your setup to " DRIVER_EMAIL "\n", - ret); - return -EINVAL; - } - DRM_DEBUG("regs mapped ok at 0x%lx\n", dev_priv->mmio->offset); - - /* map larger RAMIN aperture on NV40 cards */ - dev_priv->ramin = NULL; - if (dev_priv->card_type >= NV_40) { - int ramin_resource = 2; - if (drm_get_resource_len(dev, ramin_resource) == 0) - ramin_resource = 3; - - ret = drm_addmap(dev, - drm_get_resource_start(dev, ramin_resource), - drm_get_resource_len(dev, ramin_resource), - _DRM_REGISTERS, _DRM_READ_ONLY, - &dev_priv->ramin); - if (ret) { - DRM_ERROR("Failed to init RAMIN mapping, " - "limited instance memory available\n"); - dev_priv->ramin = NULL; - } - } - - /* On older cards (or if the above failed), create a map covering - * the BAR0 PRAMIN aperture */ - if (!dev_priv->ramin) { - ret = drm_addmap(dev, - drm_get_resource_start(dev, 0) + NV_RAMIN, - (1*1024*1024), - _DRM_REGISTERS, _DRM_READ_ONLY, - &dev_priv->ramin); - if (ret) { - DRM_ERROR("Failed to map BAR0 PRAMIN: %d\n", ret); - return ret; - } - } - - return 0; -} - -static int nouveau_stub_init(struct drm_device *dev) { return 0; } -static void nouveau_stub_takedown(struct drm_device *dev) {} - -static int nouveau_init_engine_ptrs(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine *engine = &dev_priv->Engine; - - switch (dev_priv->chipset & 0xf0) { - case 0x00: - engine->instmem.init = nv04_instmem_init; - engine->instmem.takedown= nv04_instmem_takedown; - engine->instmem.populate = nv04_instmem_populate; - engine->instmem.clear = nv04_instmem_clear; - engine->instmem.bind = nv04_instmem_bind; - engine->instmem.unbind = nv04_instmem_unbind; - engine->mc.init = nv04_mc_init; - engine->mc.takedown = nv04_mc_takedown; - engine->timer.init = nv04_timer_init; - engine->timer.read = nv04_timer_read; - engine->timer.takedown = nv04_timer_takedown; - engine->fb.init = nv04_fb_init; - engine->fb.takedown = nv04_fb_takedown; - engine->graph.init = nv04_graph_init; - engine->graph.takedown = nv04_graph_takedown; - engine->graph.create_context = nv04_graph_create_context; - engine->graph.destroy_context = nv04_graph_destroy_context; - engine->graph.load_context = nv04_graph_load_context; - engine->graph.save_context = nv04_graph_save_context; - engine->fifo.channels = 16; - engine->fifo.init = nouveau_fifo_init; - engine->fifo.takedown = nouveau_stub_takedown; - engine->fifo.channel_id = nv04_fifo_channel_id; - engine->fifo.create_context = nv04_fifo_create_context; - engine->fifo.destroy_context = nv04_fifo_destroy_context; - engine->fifo.load_context = nv04_fifo_load_context; - engine->fifo.save_context = nv04_fifo_save_context; - break; - case 0x10: - engine->instmem.init = nv04_instmem_init; - engine->instmem.takedown= nv04_instmem_takedown; - engine->instmem.populate = nv04_instmem_populate; - engine->instmem.clear = nv04_instmem_clear; - engine->instmem.bind = nv04_instmem_bind; - engine->instmem.unbind = nv04_instmem_unbind; - engine->mc.init = nv04_mc_init; - engine->mc.takedown = nv04_mc_takedown; - engine->timer.init = nv04_timer_init; - engine->timer.read = nv04_timer_read; - engine->timer.takedown = nv04_timer_takedown; - engine->fb.init = nv10_fb_init; - engine->fb.takedown = nv10_fb_takedown; - engine->graph.init = nv10_graph_init; - engine->graph.takedown = nv10_graph_takedown; - engine->graph.create_context = nv10_graph_create_context; - engine->graph.destroy_context = nv10_graph_destroy_context; - engine->graph.load_context = nv10_graph_load_context; - engine->graph.save_context = nv10_graph_save_context; - engine->fifo.channels = 32; - engine->fifo.init = nouveau_fifo_init; - engine->fifo.takedown = nouveau_stub_takedown; - engine->fifo.channel_id = nv10_fifo_channel_id; - engine->fifo.create_context = nv10_fifo_create_context; - engine->fifo.destroy_context = nv10_fifo_destroy_context; - engine->fifo.load_context = nv10_fifo_load_context; - engine->fifo.save_context = nv10_fifo_save_context; - break; - case 0x20: - engine->instmem.init = nv04_instmem_init; - engine->instmem.takedown= nv04_instmem_takedown; - engine->instmem.populate = nv04_instmem_populate; - engine->instmem.clear = nv04_instmem_clear; - engine->instmem.bind = nv04_instmem_bind; - engine->instmem.unbind = nv04_instmem_unbind; - engine->mc.init = nv04_mc_init; - engine->mc.takedown = nv04_mc_takedown; - engine->timer.init = nv04_timer_init; - engine->timer.read = nv04_timer_read; - engine->timer.takedown = nv04_timer_takedown; - engine->fb.init = nv10_fb_init; - engine->fb.takedown = nv10_fb_takedown; - engine->graph.init = nv20_graph_init; - engine->graph.takedown = nv20_graph_takedown; - engine->graph.create_context = nv20_graph_create_context; - engine->graph.destroy_context = nv20_graph_destroy_context; - engine->graph.load_context = nv20_graph_load_context; - engine->graph.save_context = nv20_graph_save_context; - engine->fifo.channels = 32; - engine->fifo.init = nouveau_fifo_init; - engine->fifo.takedown = nouveau_stub_takedown; - engine->fifo.channel_id = nv10_fifo_channel_id; - engine->fifo.create_context = nv10_fifo_create_context; - engine->fifo.destroy_context = nv10_fifo_destroy_context; - engine->fifo.load_context = nv10_fifo_load_context; - engine->fifo.save_context = nv10_fifo_save_context; - break; - case 0x30: - engine->instmem.init = nv04_instmem_init; - engine->instmem.takedown= nv04_instmem_takedown; - engine->instmem.populate = nv04_instmem_populate; - engine->instmem.clear = nv04_instmem_clear; - engine->instmem.bind = nv04_instmem_bind; - engine->instmem.unbind = nv04_instmem_unbind; - engine->mc.init = nv04_mc_init; - engine->mc.takedown = nv04_mc_takedown; - engine->timer.init = nv04_timer_init; - engine->timer.read = nv04_timer_read; - engine->timer.takedown = nv04_timer_takedown; - engine->fb.init = nv10_fb_init; - engine->fb.takedown = nv10_fb_takedown; - engine->graph.init = nv30_graph_init; - engine->graph.takedown = nv20_graph_takedown; - engine->graph.create_context = nv20_graph_create_context; - engine->graph.destroy_context = nv20_graph_destroy_context; - engine->graph.load_context = nv20_graph_load_context; - engine->graph.save_context = nv20_graph_save_context; - engine->fifo.channels = 32; - engine->fifo.init = nouveau_fifo_init; - engine->fifo.takedown = nouveau_stub_takedown; - engine->fifo.channel_id = nv10_fifo_channel_id; - engine->fifo.create_context = nv10_fifo_create_context; - engine->fifo.destroy_context = nv10_fifo_destroy_context; - engine->fifo.load_context = nv10_fifo_load_context; - engine->fifo.save_context = nv10_fifo_save_context; - break; - case 0x40: - case 0x60: - engine->instmem.init = nv04_instmem_init; - engine->instmem.takedown= nv04_instmem_takedown; - engine->instmem.populate = nv04_instmem_populate; - engine->instmem.clear = nv04_instmem_clear; - engine->instmem.bind = nv04_instmem_bind; - engine->instmem.unbind = nv04_instmem_unbind; - engine->mc.init = nv40_mc_init; - engine->mc.takedown = nv40_mc_takedown; - engine->timer.init = nv04_timer_init; - engine->timer.read = nv04_timer_read; - engine->timer.takedown = nv04_timer_takedown; - engine->fb.init = nv40_fb_init; - engine->fb.takedown = nv40_fb_takedown; - engine->graph.init = nv40_graph_init; - engine->graph.takedown = nv40_graph_takedown; - engine->graph.create_context = nv40_graph_create_context; - engine->graph.destroy_context = nv40_graph_destroy_context; - engine->graph.load_context = nv40_graph_load_context; - engine->graph.save_context = nv40_graph_save_context; - engine->fifo.channels = 32; - engine->fifo.init = nv40_fifo_init; - engine->fifo.takedown = nouveau_stub_takedown; - engine->fifo.channel_id = nv10_fifo_channel_id; - engine->fifo.create_context = nv40_fifo_create_context; - engine->fifo.destroy_context = nv40_fifo_destroy_context; - engine->fifo.load_context = nv40_fifo_load_context; - engine->fifo.save_context = nv40_fifo_save_context; - break; - case 0x50: - case 0x80: /* gotta love NVIDIA's consistency.. */ - case 0x90: - case 0xA0: - engine->instmem.init = nv50_instmem_init; - engine->instmem.takedown= nv50_instmem_takedown; - engine->instmem.populate = nv50_instmem_populate; - engine->instmem.clear = nv50_instmem_clear; - engine->instmem.bind = nv50_instmem_bind; - engine->instmem.unbind = nv50_instmem_unbind; - engine->mc.init = nv50_mc_init; - engine->mc.takedown = nv50_mc_takedown; - engine->timer.init = nv04_timer_init; - engine->timer.read = nv04_timer_read; - engine->timer.takedown = nv04_timer_takedown; - engine->fb.init = nouveau_stub_init; - engine->fb.takedown = nouveau_stub_takedown; - engine->graph.init = nv50_graph_init; - engine->graph.takedown = nv50_graph_takedown; - engine->graph.create_context = nv50_graph_create_context; - engine->graph.destroy_context = nv50_graph_destroy_context; - engine->graph.load_context = nv50_graph_load_context; - engine->graph.save_context = nv50_graph_save_context; - engine->fifo.channels = 128; - engine->fifo.init = nv50_fifo_init; - engine->fifo.takedown = nv50_fifo_takedown; - engine->fifo.channel_id = nv50_fifo_channel_id; - engine->fifo.create_context = nv50_fifo_create_context; - engine->fifo.destroy_context = nv50_fifo_destroy_context; - engine->fifo.load_context = nv50_fifo_load_context; - engine->fifo.save_context = nv50_fifo_save_context; - break; - default: - DRM_ERROR("NV%02x unsupported\n", dev_priv->chipset); - return 1; - } - - return 0; -} - -int -nouveau_card_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine *engine; - int ret; - - DRM_DEBUG("prev state = %d\n", dev_priv->init_state); - - if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE) - return 0; - dev_priv->ttm = 0; - - /* Determine exact chipset we're running on */ - if (dev_priv->card_type < NV_10) - dev_priv->chipset = dev_priv->card_type; - else - dev_priv->chipset = - (NV_READ(NV03_PMC_BOOT_0) & 0x0ff00000) >> 20; - - /* Initialise internal driver API hooks */ - ret = nouveau_init_engine_ptrs(dev); - if (ret) return ret; - engine = &dev_priv->Engine; - dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED; - - ret = nouveau_gpuobj_early_init(dev); - if (ret) return ret; - - /* Initialise instance memory, must happen before mem_init so we - * know exactly how much VRAM we're able to use for "normal" - * purposes. - */ - ret = engine->instmem.init(dev); - if (ret) return ret; - - /* Setup the memory manager */ - if (dev_priv->ttm) { - ret = nouveau_mem_init_ttm(dev); - if (ret) return ret; - } else { - ret = nouveau_mem_init(dev); - if (ret) return ret; - } - - ret = nouveau_gpuobj_init(dev); - if (ret) return ret; - - /* Parse BIOS tables / Run init tables? */ - - /* PMC */ - ret = engine->mc.init(dev); - if (ret) return ret; - - /* PTIMER */ - ret = engine->timer.init(dev); - if (ret) return ret; - - /* PFB */ - ret = engine->fb.init(dev); - if (ret) return ret; - - /* PGRAPH */ - ret = engine->graph.init(dev); - if (ret) return ret; - - /* PFIFO */ - ret = engine->fifo.init(dev); - if (ret) return ret; - - /* this call irq_preinstall, register irq handler and - * call irq_postinstall - */ - ret = drm_irq_install(dev); - if (ret) return ret; - - /* what about PVIDEO/PCRTC/PRAMDAC etc? */ - - ret = nouveau_dma_channel_init(dev); - if (ret) return ret; - - ret = nouveau_backlight_init(dev); - if (ret) - DRM_ERROR("Error code %d when trying to register backlight\n", - ret); - - dev_priv->init_state = NOUVEAU_CARD_INIT_DONE; - return 0; -} - -static void nouveau_card_takedown(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine *engine = &dev_priv->Engine; - - DRM_DEBUG("prev state = %d\n", dev_priv->init_state); - - if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) { - nouveau_backlight_exit(dev); - - nouveau_dma_channel_takedown(dev); - - engine->fifo.takedown(dev); - engine->graph.takedown(dev); - engine->fb.takedown(dev); - engine->timer.takedown(dev); - engine->mc.takedown(dev); - - nouveau_sgdma_nottm_hack_takedown(dev); - nouveau_sgdma_takedown(dev); - - nouveau_gpuobj_takedown(dev); - nouveau_gpuobj_del(dev, &dev_priv->vm_vram_pt); - - nouveau_mem_close(dev); - engine->instmem.takedown(dev); - - drm_irq_uninstall(dev); - - nouveau_gpuobj_late_takedown(dev); - - dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN; - } -} - -/* here a client dies, release the stuff that was allocated for its - * file_priv */ -void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - nouveau_fifo_cleanup(dev, file_priv); - nouveau_mem_release(file_priv,dev_priv->fb_heap); - nouveau_mem_release(file_priv,dev_priv->agp_heap); - nouveau_mem_release(file_priv,dev_priv->pci_heap); -} - -/* first module load, setup the mmio/fb mapping */ -int nouveau_firstopen(struct drm_device *dev) -{ -#if defined(__powerpc__) - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct device_node *dn; -#endif - int ret; - /* Map any PCI resources we need on the card */ - ret = nouveau_init_card_mappings(dev); - if (ret) return ret; - -#if defined(__powerpc__) - /* Put the card in BE mode if it's not */ - if (NV_READ(NV03_PMC_BOOT_1)) - NV_WRITE(NV03_PMC_BOOT_1,0x00000001); - - DRM_MEMORYBARRIER(); -#endif - -#if defined(__linux__) && defined(__powerpc__) - /* if we have an OF card, copy vbios to RAMIN */ - dn = pci_device_to_OF_node(dev->pdev); - if (dn) - { - int size; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)) - const uint32_t *bios = of_get_property(dn, "NVDA,BMP", &size); -#else - const uint32_t *bios = get_property(dn, "NVDA,BMP", &size); -#endif - if (bios) - { - int i; - for(i=0;iflags = flags & NOUVEAU_FLAGS; - dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN; - - DRM_DEBUG("vendor: 0x%X device: 0x%X class: 0x%X\n", dev->pci_vendor, dev->pci_device, dev->pdev->class); - - /* Time to determine the card architecture */ - regs = ioremap_nocache(pci_resource_start(dev->pdev, 0), 0x8); - if (!regs) { - DRM_ERROR("Could not ioremap to determine register\n"); - return -ENOMEM; - } - - reg0 = readl(regs+NV03_PMC_BOOT_0); - reg1 = readl(regs+NV03_PMC_BOOT_1); -#if defined(__powerpc__) - if (reg1) - reg0=__swab32(reg0); -#endif - - /* We're dealing with >=NV10 */ - if ((reg0 & 0x0f000000) > 0 ) { - /* Bit 27-20 contain the architecture in hex */ - architecture = (reg0 & 0xff00000) >> 20; - /* NV04 or NV05 */ - } else if ((reg0 & 0xff00fff0) == 0x20004000) { - architecture = 0x04; - } - - iounmap(regs); - - if (architecture >= 0x80) { - dev_priv->card_type = NV_50; - } else if (architecture >= 0x60) { - /* FIXME we need to figure out who's who for NV6x */ - dev_priv->card_type = NV_44; - } else if (architecture >= 0x50) { - dev_priv->card_type = NV_50; - } else if (architecture >= 0x40) { - uint8_t subarch = architecture & 0xf; - /* Selection criteria borrowed from NV40EXA */ - if (NV40_CHIPSET_MASK & (1 << subarch)) { - dev_priv->card_type = NV_40; - } else if (NV44_CHIPSET_MASK & (1 << subarch)) { - dev_priv->card_type = NV_44; - } else { - dev_priv->card_type = NV_UNKNOWN; - } - } else if (architecture >= 0x30) { - dev_priv->card_type = NV_30; - } else if (architecture >= 0x20) { - dev_priv->card_type = NV_20; - } else if (architecture >= 0x17) { - dev_priv->card_type = NV_17; - } else if (architecture >= 0x11) { - dev_priv->card_type = NV_11; - } else if (architecture >= 0x10) { - dev_priv->card_type = NV_10; - } else if (architecture >= 0x04) { - dev_priv->card_type = NV_04; - } else { - dev_priv->card_type = NV_UNKNOWN; - } - - DRM_INFO("Detected an NV%d generation card (0x%08x)\n", dev_priv->card_type,reg0); - - if (dev_priv->card_type == NV_UNKNOWN) { - return -EINVAL; - } - - /* Special flags */ - if (dev->pci_device == 0x01a0) { - dev_priv->flags |= NV_NFORCE; - } else if (dev->pci_device == 0x01f0) { - dev_priv->flags |= NV_NFORCE2; - } - - dev->dev_private = (void *)dev_priv; - - return 0; -} - -void nouveau_lastclose(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - /* In the case of an error dev_priv may not be be allocated yet */ - if (dev_priv && dev_priv->card_type) { - nouveau_card_takedown(dev); - - if(dev_priv->fb_mtrr>0) - { - drm_mtrr_del(dev_priv->fb_mtrr, drm_get_resource_start(dev, 1),nouveau_mem_fb_amount(dev), DRM_MTRR_WC); - dev_priv->fb_mtrr=0; - } - } -} - -int nouveau_unload(struct drm_device *dev) -{ - drm_free(dev->dev_private, sizeof(*dev->dev_private), DRM_MEM_DRIVER); - dev->dev_private = NULL; - return 0; -} - -int -nouveau_ioctl_card_init(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - return nouveau_card_init(dev); -} - -int nouveau_ioctl_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct drm_nouveau_getparam *getparam = data; - - NOUVEAU_CHECK_INITIALISED_WITH_RETURN; - - switch (getparam->param) { - case NOUVEAU_GETPARAM_CHIPSET_ID: - getparam->value = dev_priv->chipset; - break; - case NOUVEAU_GETPARAM_PCI_VENDOR: - getparam->value=dev->pci_vendor; - break; - case NOUVEAU_GETPARAM_PCI_DEVICE: - getparam->value=dev->pci_device; - break; - case NOUVEAU_GETPARAM_BUS_TYPE: - if (drm_device_is_agp(dev)) - getparam->value=NV_AGP; - else if (drm_device_is_pcie(dev)) - getparam->value=NV_PCIE; - else - getparam->value=NV_PCI; - break; - case NOUVEAU_GETPARAM_FB_PHYSICAL: - getparam->value=dev_priv->fb_phys; - break; - case NOUVEAU_GETPARAM_AGP_PHYSICAL: - getparam->value=dev_priv->gart_info.aper_base; - break; - case NOUVEAU_GETPARAM_PCI_PHYSICAL: - if ( dev -> sg ) - getparam->value=(unsigned long)dev->sg->virtual; - else - { - DRM_ERROR("Requested PCIGART address, while no PCIGART was created\n"); - return -EINVAL; - } - break; - case NOUVEAU_GETPARAM_FB_SIZE: - getparam->value=dev_priv->fb_available_size; - break; - case NOUVEAU_GETPARAM_AGP_SIZE: - getparam->value=dev_priv->gart_info.aper_size; - break; - case NOUVEAU_GETPARAM_MM_ENABLED: - getparam->value = 0; - break; - case NOUVEAU_GETPARAM_VM_VRAM_BASE: - if (dev_priv->card_type >= NV_50) - getparam->value = 0x20000000; - else - getparam->value = 0; - break; - default: - DRM_ERROR("unknown parameter %lld\n", getparam->param); - return -EINVAL; - } - - return 0; -} - -int nouveau_ioctl_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct drm_nouveau_setparam *setparam = data; - - NOUVEAU_CHECK_INITIALISED_WITH_RETURN; - - switch (setparam->param) { - case NOUVEAU_SETPARAM_CMDBUF_LOCATION: - switch (setparam->value) { - case NOUVEAU_MEM_AGP: - case NOUVEAU_MEM_FB: - case NOUVEAU_MEM_PCI: - case NOUVEAU_MEM_AGP | NOUVEAU_MEM_PCI_ACCEPTABLE: - break; - default: - DRM_ERROR("invalid CMDBUF_LOCATION value=%lld\n", - setparam->value); - return -EINVAL; - } - dev_priv->config.cmdbuf.location = setparam->value; - break; - case NOUVEAU_SETPARAM_CMDBUF_SIZE: - dev_priv->config.cmdbuf.size = setparam->value; - break; - default: - DRM_ERROR("unknown parameter %lld\n", setparam->param); - return -EINVAL; - } - - return 0; -} - -/* waits for idle */ -void nouveau_wait_for_idle(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv=dev->dev_private; - switch(dev_priv->card_type) { - case NV_50: - break; - default: { - /* This stuff is more or less a copy of what is seen - * in nv28 kmmio dump. - */ - uint64_t started = dev_priv->Engine.timer.read(dev); - uint64_t stopped = started; - uint32_t status; - do { - uint32_t pmc_e = NV_READ(NV03_PMC_ENABLE); - (void)pmc_e; - status = NV_READ(NV04_PGRAPH_STATUS); - if (!status) - break; - stopped = dev_priv->Engine.timer.read(dev); - /* It'll never wrap anyway... */ - } while (stopped - started < 1000000000ULL); - if (status) - DRM_ERROR("timed out with status 0x%08x\n", - status); - } - } -} - -static int nouveau_suspend(struct drm_device *dev) -{ - struct mem_block *p; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_suspend_resume *susres = &dev_priv->susres; - struct nouveau_engine *engine = &dev_priv->Engine; - struct nouveau_channel *current_fifo; - int i; - - if (dev_priv->card_type >= NV_50) { - DRM_DEBUG("Suspend not supported for NV50+\n"); - return -ENODEV; - } - - drm_free(susres->ramin_copy, susres->ramin_size, DRM_MEM_DRIVER); - susres->ramin_size = 0; - list_for_each(p, dev_priv->ramin_heap) - if (p->file_priv && (p->start + p->size) > susres->ramin_size) - susres->ramin_size = p->start + p->size; - if (!(susres->ramin_copy = drm_alloc(susres->ramin_size, DRM_MEM_DRIVER))) { - DRM_ERROR("Couldn't alloc RAMIN backing for suspend\n"); - return -ENOMEM; - } - - for (i = 0; i < engine->fifo.channels; i++) { - uint64_t t_start = engine->timer.read(dev); - - if (dev_priv->fifos[i] == NULL) - continue; - - /* Give the channel a chance to idle, wait 2s (hopefully) */ - while (!nouveau_channel_idle(dev_priv->fifos[i])) - if (engine->timer.read(dev) - t_start > 2000000000ULL) { - DRM_ERROR("Failed to idle channel %d before" - "suspend.", dev_priv->fifos[i]->id); - return -EBUSY; - } - } - nouveau_wait_for_idle(dev); - - NV_WRITE(NV04_PGRAPH_FIFO, 0); - /* disable the fifo caches */ - NV_WRITE(NV03_PFIFO_CACHES, 0x00000000); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, - NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) & ~1); - NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000); - NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000); - - susres->fifo_mode = NV_READ(NV04_PFIFO_MODE); - - if (dev_priv->card_type >= NV_10) { - susres->graph_state = NV_READ(NV10_PGRAPH_STATE); - susres->graph_ctx_control = NV_READ(NV10_PGRAPH_CTX_CONTROL); - } else { - susres->graph_state = NV_READ(NV04_PGRAPH_STATE); - susres->graph_ctx_control = NV_READ(NV04_PGRAPH_CTX_CONTROL); - } - - current_fifo = dev_priv->fifos[engine->fifo.channel_id(dev)]; - /* channel may have been deleted but no replacement yet loaded */ - if (current_fifo) { - engine->fifo.save_context(current_fifo); - engine->graph.save_context(current_fifo); - } - nouveau_wait_for_idle(dev); - - for (i = 0; i < susres->ramin_size / 4; i++) - susres->ramin_copy[i] = NV_RI32(i << 2); - - /* reenable the fifo caches */ - NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, - NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) | 1); - NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001); - NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001); - NV_WRITE(NV03_PFIFO_CACHES, 0x00000001); - NV_WRITE(NV04_PGRAPH_FIFO, 1); - - return 0; -} - -static int nouveau_resume(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_suspend_resume *susres = &dev_priv->susres; - struct nouveau_engine *engine = &dev_priv->Engine; - int i; - - if (!susres->ramin_copy) - return -EINVAL; - - DRM_DEBUG("Doing resume\n"); - - if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) { - struct drm_agp_info info; - struct drm_agp_mode mode; - - /* agp bridge drivers don't re-enable agp on resume. lame. */ - if ((i = drm_agp_info(dev, &info))) { - DRM_ERROR("Unable to get AGP info: %d\n", i); - return i; - } - mode.mode = info.mode; - if ((i = drm_agp_enable(dev, mode))) { - DRM_ERROR("Unable to enable AGP: %d\n", i); - return i; - } - } - - for (i = 0; i < susres->ramin_size / 4; i++) - NV_WI32(i << 2, susres->ramin_copy[i]); - - engine->mc.init(dev); - engine->timer.init(dev); - engine->fb.init(dev); - engine->graph.init(dev); - engine->fifo.init(dev); - - NV_WRITE(NV04_PGRAPH_FIFO, 0); - /* disable the fifo caches */ - NV_WRITE(NV03_PFIFO_CACHES, 0x00000000); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, - NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) & ~1); - NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000); - NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000); - - /* PMC power cycling PFIFO in init clobbers some of the stuff stored in - * PRAMIN (such as NV04_PFIFO_CACHE1_DMA_INSTANCE). this is unhelpful - */ - for (i = 0; i < susres->ramin_size / 4; i++) - NV_WI32(i << 2, susres->ramin_copy[i]); - - engine->fifo.load_context(dev_priv->fifos[0]); - NV_WRITE(NV04_PFIFO_MODE, susres->fifo_mode); - - engine->graph.load_context(dev_priv->fifos[0]); - nouveau_wait_for_idle(dev); - - if (dev_priv->card_type >= NV_10) { - NV_WRITE(NV10_PGRAPH_STATE, susres->graph_state); - NV_WRITE(NV10_PGRAPH_CTX_CONTROL, susres->graph_ctx_control); - } else { - NV_WRITE(NV04_PGRAPH_STATE, susres->graph_state); - NV_WRITE(NV04_PGRAPH_CTX_CONTROL, susres->graph_ctx_control); - } - - /* reenable the fifo caches */ - NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, - NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) | 1); - NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001); - NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001); - NV_WRITE(NV03_PFIFO_CACHES, 0x00000001); - NV_WRITE(NV04_PGRAPH_FIFO, 0x1); - - if (dev->irq_enabled) - nouveau_irq_postinstall(dev); - - drm_free(susres->ramin_copy, susres->ramin_size, DRM_MEM_DRIVER); - susres->ramin_copy = NULL; - susres->ramin_size = 0; - - return 0; -} - -int nouveau_ioctl_suspend(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - NOUVEAU_CHECK_INITIALISED_WITH_RETURN; - - return nouveau_suspend(dev); -} - -int nouveau_ioctl_resume(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - NOUVEAU_CHECK_INITIALISED_WITH_RETURN; - - return nouveau_resume(dev); -} diff --git a/shared-core/nouveau_swmthd.c b/shared-core/nouveau_swmthd.c deleted file mode 100644 index c3666bfd..00000000 --- a/shared-core/nouveau_swmthd.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (C) 2007 Arthur Huillet. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/* - * Authors: - * Arthur Huillet - */ - -#include "drmP.h" -#include "drm.h" -#include "nouveau_drm.h" -#include "nouveau_drv.h" -#include "nouveau_reg.h" - -/*TODO: add a "card_type" attribute*/ -typedef struct{ - uint32_t oclass; /* object class for this software method */ - uint32_t mthd; /* method number */ - void (*method_code)(struct drm_device *dev, uint32_t oclass, uint32_t mthd); /* pointer to the function that does the work */ - } nouveau_software_method_t; - - - /* This function handles the NV04 setcontext software methods. -One function for all because they are very similar.*/ -static void nouveau_NV04_setcontext_sw_method(struct drm_device *dev, uint32_t oclass, uint32_t mthd) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t inst_loc = NV_READ(NV04_PGRAPH_CTX_SWITCH4) & 0xFFFF; - uint32_t value_to_set = 0, bit_to_set = 0; - - switch ( oclass ) { - case 0x4a: - switch ( mthd ) { - case 0x188 : - case 0x18c : - bit_to_set = 0; - break; - case 0x198 : - bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/ - break; - case 0x2fc : - bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/ - break; - default : ; - }; - break; - case 0x5c: - switch ( mthd ) { - case 0x184: - bit_to_set = 1 << 13; /*USER_CLIP_ENABLE*/ - break; - case 0x188: - case 0x18c: - bit_to_set = 0; - break; - case 0x198: - bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/ - break; - case 0x2fc : - bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/ - break; - }; - break; - case 0x5f: - switch ( mthd ) { - case 0x184 : - bit_to_set = 1 << 12; /*CHROMA_KEY_ENABLE*/ - break; - case 0x188 : - bit_to_set = 1 << 13; /*USER_CLIP_ENABLE*/ - break; - case 0x18c : - case 0x190 : - bit_to_set = 0; - break; - case 0x19c : - bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/ - break; - case 0x2fc : - bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/ - break; - }; - break; - case 0x61: - switch ( mthd ) { - case 0x188 : - bit_to_set = 1 << 13; /*USER_CLIP_ENABLE*/ - break; - case 0x18c : - case 0x190 : - bit_to_set = 0; - break; - case 0x19c : - bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/ - break; - case 0x2fc : - bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/ - break; - }; - break; - case 0x77: - switch ( mthd ) { - case 0x198 : - bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/ - break; - case 0x304 : - bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; //PATCH_CONFIG - break; - }; - break; - default :; - }; - - value_to_set = (NV_READ(0x00700000 | inst_loc << 4))| bit_to_set; - - /*RAMIN*/ - nouveau_wait_for_idle(dev); - NV_WRITE(0x00700000 | inst_loc << 4, value_to_set); - - /*DRM_DEBUG("CTX_SWITCH1 value is %#x\n", NV_READ(NV04_PGRAPH_CTX_SWITCH1));*/ - NV_WRITE(NV04_PGRAPH_CTX_SWITCH1, value_to_set); - - /*DRM_DEBUG("CTX_CACHE1 + xxx value is %#x\n", NV_READ(NV04_PGRAPH_CTX_CACHE1 + (((NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7) << 2)));*/ - NV_WRITE(NV04_PGRAPH_CTX_CACHE1 + (((NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7) << 2), value_to_set); -} - - nouveau_software_method_t nouveau_sw_methods[] = { - /*NV04 context software methods*/ - { 0x4a, 0x188, nouveau_NV04_setcontext_sw_method }, - { 0x4a, 0x18c, nouveau_NV04_setcontext_sw_method }, - { 0x4a, 0x198, nouveau_NV04_setcontext_sw_method }, - { 0x4a, 0x2fc, nouveau_NV04_setcontext_sw_method }, - { 0x5c, 0x184, nouveau_NV04_setcontext_sw_method }, - { 0x5c, 0x188, nouveau_NV04_setcontext_sw_method }, - { 0x5c, 0x18c, nouveau_NV04_setcontext_sw_method }, - { 0x5c, 0x198, nouveau_NV04_setcontext_sw_method }, - { 0x5c, 0x2fc, nouveau_NV04_setcontext_sw_method }, - { 0x5f, 0x184, nouveau_NV04_setcontext_sw_method }, - { 0x5f, 0x188, nouveau_NV04_setcontext_sw_method }, - { 0x5f, 0x18c, nouveau_NV04_setcontext_sw_method }, - { 0x5f, 0x190, nouveau_NV04_setcontext_sw_method }, - { 0x5f, 0x19c, nouveau_NV04_setcontext_sw_method }, - { 0x5f, 0x2fc, nouveau_NV04_setcontext_sw_method }, - { 0x61, 0x188, nouveau_NV04_setcontext_sw_method }, - { 0x61, 0x18c, nouveau_NV04_setcontext_sw_method }, - { 0x61, 0x190, nouveau_NV04_setcontext_sw_method }, - { 0x61, 0x19c, nouveau_NV04_setcontext_sw_method }, - { 0x61, 0x2fc, nouveau_NV04_setcontext_sw_method }, - { 0x77, 0x198, nouveau_NV04_setcontext_sw_method }, - { 0x77, 0x304, nouveau_NV04_setcontext_sw_method }, - /*terminator*/ - { 0x0, 0x0, NULL, }, - }; - - int nouveau_sw_method_execute(struct drm_device *dev, uint32_t oclass, uint32_t method) { - int i = 0; - while ( nouveau_sw_methods[ i ] . method_code != NULL ) - { - if ( nouveau_sw_methods[ i ] . oclass == oclass && nouveau_sw_methods[ i ] . mthd == method ) - { - nouveau_sw_methods[ i ] . method_code(dev, oclass, method); - return 0; - } - i ++; - } - - return 1; - } diff --git a/shared-core/nouveau_swmthd.h b/shared-core/nouveau_swmthd.h deleted file mode 100644 index 5b9409fb..00000000 --- a/shared-core/nouveau_swmthd.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (C) 2007 Arthur Huillet. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/* - * Authors: - * Arthur Huillet - */ - -int nouveau_sw_method_execute(struct drm_device *dev, uint32_t oclass, uint32_t method); /* execute the given software method, returns 0 on success */ diff --git a/shared-core/nv04_fb.c b/shared-core/nv04_fb.c deleted file mode 100644 index 58a92470..00000000 --- a/shared-core/nv04_fb.c +++ /dev/null @@ -1,23 +0,0 @@ -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" -#include "nouveau_drm.h" - -int -nv04_fb_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - /* This is what the DDX did for NV_ARCH_04, but a mmio-trace shows - * nvidia reading PFB_CFG_0, then writing back its original value. - * (which was 0x701114 in this case) - */ - NV_WRITE(NV04_PFB_CFG0, 0x1114); - - return 0; -} - -void -nv04_fb_takedown(struct drm_device *dev) -{ -} diff --git a/shared-core/nv04_fifo.c b/shared-core/nv04_fifo.c deleted file mode 100644 index 88186fe3..00000000 --- a/shared-core/nv04_fifo.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (C) 2007 Ben Skeggs. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" - -#define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \ - NV04_RAMFC_##offset/4, (val)) -#define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \ - NV04_RAMFC_##offset/4) -#define NV04_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV04_RAMFC__SIZE)) -#define NV04_RAMFC__SIZE 32 - -int -nv04_fifo_channel_id(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) & - NV03_PFIFO_CACHE1_PUSH1_CHID_MASK); -} - -int -nv04_fifo_create_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - int ret; - - if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), ~0, - NV04_RAMFC__SIZE, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ZERO_FREE, - NULL, &chan->ramfc))) - return ret; - - /* Setup initial state */ - RAMFC_WR(DMA_PUT, chan->pushbuf_base); - RAMFC_WR(DMA_GET, chan->pushbuf_base); - RAMFC_WR(DMA_INSTANCE, chan->pushbuf->instance >> 4); - RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | -#ifdef __BIG_ENDIAN - NV_PFIFO_CACHE1_BIG_ENDIAN | -#endif - 0)); - - /* enable the fifo dma operation */ - NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE) | (1<id)); - return 0; -} - -void -nv04_fifo_destroy_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - - NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<id)); - - nouveau_gpuobj_ref_del(dev, &chan->ramfc); -} - -int -nv04_fifo_load_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t tmp; - - NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, - NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id); - - NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET)); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT)); - - tmp = RAMFC_RD(DMA_INSTANCE); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16); - - NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, RAMFC_RD(DMA_STATE)); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, RAMFC_RD(DMA_FETCH)); - NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, RAMFC_RD(ENGINE)); - NV_WRITE(NV04_PFIFO_CACHE1_PULL1, RAMFC_RD(PULL1_ENGINE)); - - /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */ - tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp); - - return 0; -} - -int -nv04_fifo_save_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t tmp; - - RAMFC_WR(DMA_PUT, NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); - RAMFC_WR(DMA_GET, NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); - - tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16; - tmp |= NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE); - RAMFC_WR(DMA_INSTANCE, tmp); - - RAMFC_WR(DMA_STATE, NV_READ(NV04_PFIFO_CACHE1_DMA_STATE)); - RAMFC_WR(DMA_FETCH, NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH)); - RAMFC_WR(ENGINE, NV_READ(NV04_PFIFO_CACHE1_ENGINE)); - RAMFC_WR(PULL1_ENGINE, NV_READ(NV04_PFIFO_CACHE1_PULL1)); - - return 0; -} diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c deleted file mode 100644 index 6caae257..00000000 --- a/shared-core/nv04_graph.c +++ /dev/null @@ -1,516 +0,0 @@ -/* - * Copyright 2007 Stephane Marchesin - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "drmP.h" -#include "drm.h" -#include "nouveau_drm.h" -#include "nouveau_drv.h" - -static uint32_t nv04_graph_ctx_regs [] = { - NV04_PGRAPH_CTX_SWITCH1, - NV04_PGRAPH_CTX_SWITCH2, - NV04_PGRAPH_CTX_SWITCH3, - NV04_PGRAPH_CTX_SWITCH4, - NV04_PGRAPH_CTX_CACHE1, - NV04_PGRAPH_CTX_CACHE2, - NV04_PGRAPH_CTX_CACHE3, - NV04_PGRAPH_CTX_CACHE4, - 0x00400184, - 0x004001a4, - 0x004001c4, - 0x004001e4, - 0x00400188, - 0x004001a8, - 0x004001c8, - 0x004001e8, - 0x0040018c, - 0x004001ac, - 0x004001cc, - 0x004001ec, - 0x00400190, - 0x004001b0, - 0x004001d0, - 0x004001f0, - 0x00400194, - 0x004001b4, - 0x004001d4, - 0x004001f4, - 0x00400198, - 0x004001b8, - 0x004001d8, - 0x004001f8, - 0x0040019c, - 0x004001bc, - 0x004001dc, - 0x004001fc, - 0x00400174, - NV04_PGRAPH_DMA_START_0, - NV04_PGRAPH_DMA_START_1, - NV04_PGRAPH_DMA_LENGTH, - NV04_PGRAPH_DMA_MISC, - NV04_PGRAPH_DMA_PITCH, - NV04_PGRAPH_BOFFSET0, - NV04_PGRAPH_BBASE0, - NV04_PGRAPH_BLIMIT0, - NV04_PGRAPH_BOFFSET1, - NV04_PGRAPH_BBASE1, - NV04_PGRAPH_BLIMIT1, - NV04_PGRAPH_BOFFSET2, - NV04_PGRAPH_BBASE2, - NV04_PGRAPH_BLIMIT2, - NV04_PGRAPH_BOFFSET3, - NV04_PGRAPH_BBASE3, - NV04_PGRAPH_BLIMIT3, - NV04_PGRAPH_BOFFSET4, - NV04_PGRAPH_BBASE4, - NV04_PGRAPH_BLIMIT4, - NV04_PGRAPH_BOFFSET5, - NV04_PGRAPH_BBASE5, - NV04_PGRAPH_BLIMIT5, - NV04_PGRAPH_BPITCH0, - NV04_PGRAPH_BPITCH1, - NV04_PGRAPH_BPITCH2, - NV04_PGRAPH_BPITCH3, - NV04_PGRAPH_BPITCH4, - NV04_PGRAPH_SURFACE, - NV04_PGRAPH_STATE, - NV04_PGRAPH_BSWIZZLE2, - NV04_PGRAPH_BSWIZZLE5, - NV04_PGRAPH_BPIXEL, - NV04_PGRAPH_NOTIFY, - NV04_PGRAPH_PATT_COLOR0, - NV04_PGRAPH_PATT_COLOR1, - NV04_PGRAPH_PATT_COLORRAM+0x00, - NV04_PGRAPH_PATT_COLORRAM+0x01, - NV04_PGRAPH_PATT_COLORRAM+0x02, - NV04_PGRAPH_PATT_COLORRAM+0x03, - NV04_PGRAPH_PATT_COLORRAM+0x04, - NV04_PGRAPH_PATT_COLORRAM+0x05, - NV04_PGRAPH_PATT_COLORRAM+0x06, - NV04_PGRAPH_PATT_COLORRAM+0x07, - NV04_PGRAPH_PATT_COLORRAM+0x08, - NV04_PGRAPH_PATT_COLORRAM+0x09, - NV04_PGRAPH_PATT_COLORRAM+0x0A, - NV04_PGRAPH_PATT_COLORRAM+0x0B, - NV04_PGRAPH_PATT_COLORRAM+0x0C, - NV04_PGRAPH_PATT_COLORRAM+0x0D, - NV04_PGRAPH_PATT_COLORRAM+0x0E, - NV04_PGRAPH_PATT_COLORRAM+0x0F, - NV04_PGRAPH_PATT_COLORRAM+0x10, - NV04_PGRAPH_PATT_COLORRAM+0x11, - NV04_PGRAPH_PATT_COLORRAM+0x12, - NV04_PGRAPH_PATT_COLORRAM+0x13, - NV04_PGRAPH_PATT_COLORRAM+0x14, - NV04_PGRAPH_PATT_COLORRAM+0x15, - NV04_PGRAPH_PATT_COLORRAM+0x16, - NV04_PGRAPH_PATT_COLORRAM+0x17, - NV04_PGRAPH_PATT_COLORRAM+0x18, - NV04_PGRAPH_PATT_COLORRAM+0x19, - NV04_PGRAPH_PATT_COLORRAM+0x1A, - NV04_PGRAPH_PATT_COLORRAM+0x1B, - NV04_PGRAPH_PATT_COLORRAM+0x1C, - NV04_PGRAPH_PATT_COLORRAM+0x1D, - NV04_PGRAPH_PATT_COLORRAM+0x1E, - NV04_PGRAPH_PATT_COLORRAM+0x1F, - NV04_PGRAPH_PATT_COLORRAM+0x20, - NV04_PGRAPH_PATT_COLORRAM+0x21, - NV04_PGRAPH_PATT_COLORRAM+0x22, - NV04_PGRAPH_PATT_COLORRAM+0x23, - NV04_PGRAPH_PATT_COLORRAM+0x24, - NV04_PGRAPH_PATT_COLORRAM+0x25, - NV04_PGRAPH_PATT_COLORRAM+0x26, - NV04_PGRAPH_PATT_COLORRAM+0x27, - NV04_PGRAPH_PATT_COLORRAM+0x28, - NV04_PGRAPH_PATT_COLORRAM+0x29, - NV04_PGRAPH_PATT_COLORRAM+0x2A, - NV04_PGRAPH_PATT_COLORRAM+0x2B, - NV04_PGRAPH_PATT_COLORRAM+0x2C, - NV04_PGRAPH_PATT_COLORRAM+0x2D, - NV04_PGRAPH_PATT_COLORRAM+0x2E, - NV04_PGRAPH_PATT_COLORRAM+0x2F, - NV04_PGRAPH_PATT_COLORRAM+0x30, - NV04_PGRAPH_PATT_COLORRAM+0x31, - NV04_PGRAPH_PATT_COLORRAM+0x32, - NV04_PGRAPH_PATT_COLORRAM+0x33, - NV04_PGRAPH_PATT_COLORRAM+0x34, - NV04_PGRAPH_PATT_COLORRAM+0x35, - NV04_PGRAPH_PATT_COLORRAM+0x36, - NV04_PGRAPH_PATT_COLORRAM+0x37, - NV04_PGRAPH_PATT_COLORRAM+0x38, - NV04_PGRAPH_PATT_COLORRAM+0x39, - NV04_PGRAPH_PATT_COLORRAM+0x3A, - NV04_PGRAPH_PATT_COLORRAM+0x3B, - NV04_PGRAPH_PATT_COLORRAM+0x3C, - NV04_PGRAPH_PATT_COLORRAM+0x3D, - NV04_PGRAPH_PATT_COLORRAM+0x3E, - NV04_PGRAPH_PATT_COLORRAM+0x3F, - NV04_PGRAPH_PATTERN, - 0x0040080c, - NV04_PGRAPH_PATTERN_SHAPE, - 0x00400600, - NV04_PGRAPH_ROP3, - NV04_PGRAPH_CHROMA, - NV04_PGRAPH_BETA_AND, - NV04_PGRAPH_BETA_PREMULT, - NV04_PGRAPH_CONTROL0, - NV04_PGRAPH_CONTROL1, - NV04_PGRAPH_CONTROL2, - NV04_PGRAPH_BLEND, - NV04_PGRAPH_STORED_FMT, - NV04_PGRAPH_SOURCE_COLOR, - 0x00400560, - 0x00400568, - 0x00400564, - 0x0040056c, - 0x00400400, - 0x00400480, - 0x00400404, - 0x00400484, - 0x00400408, - 0x00400488, - 0x0040040c, - 0x0040048c, - 0x00400410, - 0x00400490, - 0x00400414, - 0x00400494, - 0x00400418, - 0x00400498, - 0x0040041c, - 0x0040049c, - 0x00400420, - 0x004004a0, - 0x00400424, - 0x004004a4, - 0x00400428, - 0x004004a8, - 0x0040042c, - 0x004004ac, - 0x00400430, - 0x004004b0, - 0x00400434, - 0x004004b4, - 0x00400438, - 0x004004b8, - 0x0040043c, - 0x004004bc, - 0x00400440, - 0x004004c0, - 0x00400444, - 0x004004c4, - 0x00400448, - 0x004004c8, - 0x0040044c, - 0x004004cc, - 0x00400450, - 0x004004d0, - 0x00400454, - 0x004004d4, - 0x00400458, - 0x004004d8, - 0x0040045c, - 0x004004dc, - 0x00400460, - 0x004004e0, - 0x00400464, - 0x004004e4, - 0x00400468, - 0x004004e8, - 0x0040046c, - 0x004004ec, - 0x00400470, - 0x004004f0, - 0x00400474, - 0x004004f4, - 0x00400478, - 0x004004f8, - 0x0040047c, - 0x004004fc, - 0x0040053c, - 0x00400544, - 0x00400540, - 0x00400548, - 0x00400560, - 0x00400568, - 0x00400564, - 0x0040056c, - 0x00400534, - 0x00400538, - 0x00400514, - 0x00400518, - 0x0040051c, - 0x00400520, - 0x00400524, - 0x00400528, - 0x0040052c, - 0x00400530, - 0x00400d00, - 0x00400d40, - 0x00400d80, - 0x00400d04, - 0x00400d44, - 0x00400d84, - 0x00400d08, - 0x00400d48, - 0x00400d88, - 0x00400d0c, - 0x00400d4c, - 0x00400d8c, - 0x00400d10, - 0x00400d50, - 0x00400d90, - 0x00400d14, - 0x00400d54, - 0x00400d94, - 0x00400d18, - 0x00400d58, - 0x00400d98, - 0x00400d1c, - 0x00400d5c, - 0x00400d9c, - 0x00400d20, - 0x00400d60, - 0x00400da0, - 0x00400d24, - 0x00400d64, - 0x00400da4, - 0x00400d28, - 0x00400d68, - 0x00400da8, - 0x00400d2c, - 0x00400d6c, - 0x00400dac, - 0x00400d30, - 0x00400d70, - 0x00400db0, - 0x00400d34, - 0x00400d74, - 0x00400db4, - 0x00400d38, - 0x00400d78, - 0x00400db8, - 0x00400d3c, - 0x00400d7c, - 0x00400dbc, - 0x00400590, - 0x00400594, - 0x00400598, - 0x0040059c, - 0x004005a8, - 0x004005ac, - 0x004005b0, - 0x004005b4, - 0x004005c0, - 0x004005c4, - 0x004005c8, - 0x004005cc, - 0x004005d0, - 0x004005d4, - 0x004005d8, - 0x004005dc, - 0x004005e0, - NV04_PGRAPH_PASSTHRU_0, - NV04_PGRAPH_PASSTHRU_1, - NV04_PGRAPH_PASSTHRU_2, - NV04_PGRAPH_DVD_COLORFMT, - NV04_PGRAPH_SCALED_FORMAT, - NV04_PGRAPH_MISC24_0, - NV04_PGRAPH_MISC24_1, - NV04_PGRAPH_MISC24_2, - 0x00400500, - 0x00400504, - NV04_PGRAPH_VALID1, - NV04_PGRAPH_VALID2 - - -}; - -struct graph_state { - int nv04[sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0])]; -}; - -void nouveau_nv04_context_switch(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine *engine = &dev_priv->Engine; - struct nouveau_channel *next, *last; - int chid; - - if (!dev) { - DRM_DEBUG("Invalid drm_device\n"); - return; - } - dev_priv = dev->dev_private; - if (!dev_priv) { - DRM_DEBUG("Invalid drm_nouveau_private\n"); - return; - } - if (!dev_priv->fifos) { - DRM_DEBUG("Invalid drm_nouveau_private->fifos\n"); - return; - } - - chid = engine->fifo.channel_id(dev); - next = dev_priv->fifos[chid]; - - if (!next) { - DRM_DEBUG("Invalid next channel\n"); - return; - } - - chid = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (engine->fifo.channels - 1); - last = dev_priv->fifos[chid]; - - if (!last) { - DRM_DEBUG("WARNING: Invalid last channel, switch to %x\n", - next->id); - } else { - DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n", - last->id, next->id); - } - -/* NV_WRITE(NV03_PFIFO_CACHES, 0x0); - NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0); - NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0);*/ - NV_WRITE(NV04_PGRAPH_FIFO,0x0); - - if (last) - nv04_graph_save_context(last); - - nouveau_wait_for_idle(dev); - - NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10000000); - NV_WRITE(NV04_PGRAPH_CTX_USER, (NV_READ(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x0f << 24)); - - nouveau_wait_for_idle(dev); - - nv04_graph_load_context(next); - - NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100); - NV_WRITE(NV04_PGRAPH_CTX_USER, next->id << 24); - NV_WRITE(NV04_PGRAPH_FFINTFC_ST2, NV_READ(NV04_PGRAPH_FFINTFC_ST2)&0x000FFFFF); - -/* NV_WRITE(NV04_PGRAPH_FIFO,0x0); - NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0); - NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x1); - NV_WRITE(NV03_PFIFO_CACHES, 0x1);*/ - NV_WRITE(NV04_PGRAPH_FIFO,0x1); -} - -int nv04_graph_create_context(struct nouveau_channel *chan) { - struct graph_state* pgraph_ctx; - DRM_DEBUG("nv04_graph_context_create %d\n", chan->id); - - chan->pgraph_ctx = pgraph_ctx = drm_calloc(1, sizeof(*pgraph_ctx), - DRM_MEM_DRIVER); - - if (pgraph_ctx == NULL) - return -ENOMEM; - - //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; - pgraph_ctx->nv04[0] = 0x0001ffff; - /* is it really needed ??? */ - //dev_priv->fifos[channel].pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4); - //dev_priv->fifos[channel].pgraph_ctx[2] = NV_READ(0x004006b0); - - return 0; -} - -void nv04_graph_destroy_context(struct nouveau_channel *chan) -{ - struct graph_state* pgraph_ctx = chan->pgraph_ctx; - - drm_free(pgraph_ctx, sizeof(*pgraph_ctx), DRM_MEM_DRIVER); - chan->pgraph_ctx = NULL; -} - -int nv04_graph_load_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct graph_state* pgraph_ctx = chan->pgraph_ctx; - int i; - - for (i = 0; i < sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++) - NV_WRITE(nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]); - - return 0; -} - -int nv04_graph_save_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct graph_state* pgraph_ctx = chan->pgraph_ctx; - int i; - - for (i = 0; i < sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++) - pgraph_ctx->nv04[i] = NV_READ(nv04_graph_ctx_regs[i]); - - return 0; -} - -int nv04_graph_init(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & - ~NV_PMC_ENABLE_PGRAPH); - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | - NV_PMC_ENABLE_PGRAPH); - - /* Enable PGRAPH interrupts */ - NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF); - NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - NV_WRITE(NV04_PGRAPH_VALID1, 0); - NV_WRITE(NV04_PGRAPH_VALID2, 0); - /*NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x000001FF); - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/ - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x1231c000); - /*1231C000 blob, 001 haiku*/ - //*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/ - NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x72111100); - /*0x72111100 blob , 01 haiku*/ - /*NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/ - NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x11d5f071); - /*haiku same*/ - - /*NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/ - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xf0d4ff31); - /*haiku and blob 10d4*/ - - NV_WRITE(NV04_PGRAPH_STATE , 0xFFFFFFFF); - NV_WRITE(NV04_PGRAPH_CTX_CONTROL , 0x10010100); - NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001); - - /* These don't belong here, they're part of a per-channel context */ - NV_WRITE(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000); - NV_WRITE(NV04_PGRAPH_BETA_AND , 0xFFFFFFFF); - - return 0; -} - -void nv04_graph_takedown(struct drm_device *dev) -{ -} diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c deleted file mode 100644 index 713b02d0..00000000 --- a/shared-core/nv04_instmem.c +++ /dev/null @@ -1,159 +0,0 @@ -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" - -static void -nv04_instmem_determine_amount(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - /* Figure out how much instance memory we need */ - if (dev_priv->card_type >= NV_40) { - /* We'll want more instance memory than this on some NV4x cards. - * There's a 16MB aperture to play with that maps onto the end - * of vram. For now, only reserve a small piece until we know - * more about what each chipset requires. - */ - dev_priv->ramin_rsvd_vram = (1*1024* 1024); - } else { - /*XXX: what *are* the limits on ramin_rsvd_vram = (512*1024); - } - DRM_DEBUG("RAMIN size: %dKiB\n", dev_priv->ramin_rsvd_vram>>10); - - /* Clear all of it, except the BIOS image that's in the first 64KiB */ - for (i=(64*1024); iramin_rsvd_vram; i+=4) - NV_WI32(i, 0x00000000); -} - -static void -nv04_instmem_configure_fixed_tables(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine *engine = &dev_priv->Engine; - - /* FIFO hash table (RAMHT) - * use 4k hash table at RAMIN+0x10000 - * TODO: extend the hash table - */ - dev_priv->ramht_offset = 0x10000; - dev_priv->ramht_bits = 9; - dev_priv->ramht_size = (1 << dev_priv->ramht_bits); /* nr entries */ - dev_priv->ramht_size *= 8; /* 2 32-bit values per entry in RAMHT */ - DRM_DEBUG("RAMHT offset=0x%x, size=%d\n", dev_priv->ramht_offset, - dev_priv->ramht_size); - - /* FIFO runout table (RAMRO) - 512k at 0x11200 */ - dev_priv->ramro_offset = 0x11200; - dev_priv->ramro_size = 512; - DRM_DEBUG("RAMRO offset=0x%x, size=%d\n", dev_priv->ramro_offset, - dev_priv->ramro_size); - - /* FIFO context table (RAMFC) - * NV40 : Not sure exactly how to position RAMFC on some cards, - * 0x30002 seems to position it at RAMIN+0x20000 on these - * cards. RAMFC is 4kb (32 fifos, 128byte entries). - * Others: Position RAMFC at RAMIN+0x11400 - */ - switch(dev_priv->card_type) - { - case NV_40: - case NV_44: - dev_priv->ramfc_offset = 0x20000; - dev_priv->ramfc_size = engine->fifo.channels * - nouveau_fifo_ctx_size(dev); - break; - case NV_30: - case NV_20: - case NV_17: - case NV_11: - case NV_10: - case NV_04: - default: - dev_priv->ramfc_offset = 0x11400; - dev_priv->ramfc_size = engine->fifo.channels * - nouveau_fifo_ctx_size(dev); - break; - } - DRM_DEBUG("RAMFC offset=0x%x, size=%d\n", dev_priv->ramfc_offset, - dev_priv->ramfc_size); -} - -int nv04_instmem_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t offset; - int ret = 0; - - nv04_instmem_determine_amount(dev); - nv04_instmem_configure_fixed_tables(dev); - - /* Create a heap to manage RAMIN allocations, we don't allocate - * the space that was reserved for RAMHT/FC/RO. - */ - offset = dev_priv->ramfc_offset + dev_priv->ramfc_size; - - /* On my NV4E, there's *something* clobbering the 16KiB just after - * where we setup these fixed tables. No idea what it is just yet, - * so reserve this space on all NV4X cards for now. - */ - if (dev_priv->card_type >= NV_40) - offset += 16*1024; - - ret = nouveau_mem_init_heap(&dev_priv->ramin_heap, - offset, dev_priv->ramin_rsvd_vram - offset); - if (ret) { - dev_priv->ramin_heap = NULL; - DRM_ERROR("Failed to init RAMIN heap\n"); - } - - return ret; -} - -void -nv04_instmem_takedown(struct drm_device *dev) -{ -} - -int -nv04_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz) -{ - if (gpuobj->im_backing) - return -EINVAL; - - return 0; -} - -void -nv04_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - if (gpuobj && gpuobj->im_backing) { - if (gpuobj->im_bound) - dev_priv->Engine.instmem.unbind(dev, gpuobj); - gpuobj->im_backing = NULL; - } -} - -int -nv04_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) -{ - if (!gpuobj->im_pramin || gpuobj->im_bound) - return -EINVAL; - - gpuobj->im_bound = 1; - return 0; -} - -int -nv04_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) -{ - if (gpuobj->im_bound == 0) - return -EINVAL; - - gpuobj->im_bound = 0; - return 0; -} diff --git a/shared-core/nv04_mc.c b/shared-core/nv04_mc.c deleted file mode 100644 index 24c1f7b3..00000000 --- a/shared-core/nv04_mc.c +++ /dev/null @@ -1,22 +0,0 @@ -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" -#include "nouveau_drm.h" - -int -nv04_mc_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - /* Power up everything, resetting each individual unit will - * be done later if needed. - */ - NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF); - - return 0; -} - -void -nv04_mc_takedown(struct drm_device *dev) -{ -} diff --git a/shared-core/nv04_timer.c b/shared-core/nv04_timer.c deleted file mode 100644 index 616f197b..00000000 --- a/shared-core/nv04_timer.c +++ /dev/null @@ -1,53 +0,0 @@ -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" -#include "nouveau_drm.h" - -int -nv04_timer_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - NV_WRITE(NV04_PTIMER_INTR_EN_0, 0x00000000); - NV_WRITE(NV04_PTIMER_INTR_0, 0xFFFFFFFF); - - /* Just use the pre-existing values when possible for now; these regs - * are not written in nv (driver writer missed a /4 on the address), and - * writing 8 and 3 to the correct regs breaks the timings on the LVDS - * hardware sequencing microcode. - * A correct solution (involving calculations with the GPU PLL) can - * be done when kernel modesetting lands - */ - if (!NV_READ(NV04_PTIMER_NUMERATOR) || !NV_READ(NV04_PTIMER_DENOMINATOR)) { - NV_WRITE(NV04_PTIMER_NUMERATOR, 0x00000008); - NV_WRITE(NV04_PTIMER_DENOMINATOR, 0x00000003); - } - - return 0; -} - -uint64_t -nv04_timer_read(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t low; - /* From kmmio dumps on nv28 this looks like how the blob does this. - * It reads the high dword twice, before and after. - * The only explanation seems to be that the 64-bit timer counter - * advances between high and low dword reads and may corrupt the - * result. Not confirmed. - */ - uint32_t high2 = NV_READ(NV04_PTIMER_TIME_1); - uint32_t high1; - do { - high1 = high2; - low = NV_READ(NV04_PTIMER_TIME_0); - high2 = NV_READ(NV04_PTIMER_TIME_1); - } while(high1 != high2); - return (((uint64_t)high2) << 32) | (uint64_t)low; -} - -void -nv04_timer_takedown(struct drm_device *dev) -{ -} diff --git a/shared-core/nv10_fb.c b/shared-core/nv10_fb.c deleted file mode 100644 index 6e0773ac..00000000 --- a/shared-core/nv10_fb.c +++ /dev/null @@ -1,25 +0,0 @@ -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" -#include "nouveau_drm.h" - -int -nv10_fb_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t fb_bar_size; - int i; - - fb_bar_size = drm_get_resource_len(dev, 0) - 1; - for (i=0; iramfc->gpuobj, \ - NV10_RAMFC_##offset/4, (val)) -#define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \ - NV10_RAMFC_##offset/4) -#define NV10_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV10_RAMFC__SIZE)) -#define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32) - -int -nv10_fifo_channel_id(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) & - NV10_PFIFO_CACHE1_PUSH1_CHID_MASK); -} - -int -nv10_fifo_create_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - int ret; - - if ((ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id), ~0, - NV10_RAMFC__SIZE, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ZERO_FREE, - NULL, &chan->ramfc))) - return ret; - - /* Fill entries that are seen filled in dumps of nvidia driver just - * after channel's is put into DMA mode - */ - RAMFC_WR(DMA_PUT , chan->pushbuf_base); - RAMFC_WR(DMA_GET , chan->pushbuf_base); - RAMFC_WR(DMA_INSTANCE , chan->pushbuf->instance >> 4); - RAMFC_WR(DMA_FETCH , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | -#ifdef __BIG_ENDIAN - NV_PFIFO_CACHE1_BIG_ENDIAN | -#endif - 0); - - /* enable the fifo dma operation */ - NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<id)); - return 0; -} - -void -nv10_fifo_destroy_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - - NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<id)); - - nouveau_gpuobj_ref_del(dev, &chan->ramfc); -} - -int -nv10_fifo_load_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t tmp; - - NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, - NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id); - - NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET)); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT , RAMFC_RD(DMA_PUT)); - NV_WRITE(NV10_PFIFO_CACHE1_REF_CNT , RAMFC_RD(REF_CNT)); - - tmp = RAMFC_RD(DMA_INSTANCE); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE , tmp & 0xFFFF); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT , tmp >> 16); - - NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE , RAMFC_RD(DMA_STATE)); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH , RAMFC_RD(DMA_FETCH)); - NV_WRITE(NV04_PFIFO_CACHE1_ENGINE , RAMFC_RD(ENGINE)); - NV_WRITE(NV04_PFIFO_CACHE1_PULL1 , RAMFC_RD(PULL1_ENGINE)); - - if (dev_priv->chipset >= 0x17) { - NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE, - RAMFC_RD(ACQUIRE_VALUE)); - NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, - RAMFC_RD(ACQUIRE_TIMESTAMP)); - NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT, - RAMFC_RD(ACQUIRE_TIMEOUT)); - NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE, - RAMFC_RD(SEMAPHORE)); - NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE, - RAMFC_RD(DMA_SUBROUTINE)); - } - - /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */ - tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp); - - return 0; -} - -int -nv10_fifo_save_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t tmp; - - RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); - RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); - RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT)); - - tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE) & 0xFFFF; - tmp |= (NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16); - RAMFC_WR(DMA_INSTANCE , tmp); - - RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE)); - RAMFC_WR(DMA_FETCH , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH)); - RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE)); - RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1)); - - if (dev_priv->chipset >= 0x17) { - RAMFC_WR(ACQUIRE_VALUE, - NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE)); - RAMFC_WR(ACQUIRE_TIMESTAMP, - NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP)); - RAMFC_WR(ACQUIRE_TIMEOUT, - NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT)); - RAMFC_WR(SEMAPHORE, - NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE)); - RAMFC_WR(DMA_SUBROUTINE, - NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); - } - - return 0; -} diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c deleted file mode 100644 index d0c2285f..00000000 --- a/shared-core/nv10_graph.c +++ /dev/null @@ -1,914 +0,0 @@ -/* - * Copyright 2007 Matthieu CASTET - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "drmP.h" -#include "drm.h" -#include "nouveau_drm.h" -#include "nouveau_drv.h" - -#define NV10_FIFO_NUMBER 32 - -struct pipe_state { - uint32_t pipe_0x0000[0x040/4]; - uint32_t pipe_0x0040[0x010/4]; - uint32_t pipe_0x0200[0x0c0/4]; - uint32_t pipe_0x4400[0x080/4]; - uint32_t pipe_0x6400[0x3b0/4]; - uint32_t pipe_0x6800[0x2f0/4]; - uint32_t pipe_0x6c00[0x030/4]; - uint32_t pipe_0x7000[0x130/4]; - uint32_t pipe_0x7400[0x0c0/4]; - uint32_t pipe_0x7800[0x0c0/4]; -}; - -static int nv10_graph_ctx_regs [] = { -NV10_PGRAPH_CTX_SWITCH1, -NV10_PGRAPH_CTX_SWITCH2, -NV10_PGRAPH_CTX_SWITCH3, -NV10_PGRAPH_CTX_SWITCH4, -NV10_PGRAPH_CTX_SWITCH5, -NV10_PGRAPH_CTX_CACHE1, /* 8 values from 0x400160 to 0x40017c */ -NV10_PGRAPH_CTX_CACHE2, /* 8 values from 0x400180 to 0x40019c */ -NV10_PGRAPH_CTX_CACHE3, /* 8 values from 0x4001a0 to 0x4001bc */ -NV10_PGRAPH_CTX_CACHE4, /* 8 values from 0x4001c0 to 0x4001dc */ -NV10_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */ -0x00400164, -0x00400184, -0x004001a4, -0x004001c4, -0x004001e4, -0x00400168, -0x00400188, -0x004001a8, -0x004001c8, -0x004001e8, -0x0040016c, -0x0040018c, -0x004001ac, -0x004001cc, -0x004001ec, -0x00400170, -0x00400190, -0x004001b0, -0x004001d0, -0x004001f0, -0x00400174, -0x00400194, -0x004001b4, -0x004001d4, -0x004001f4, -0x00400178, -0x00400198, -0x004001b8, -0x004001d8, -0x004001f8, -0x0040017c, -0x0040019c, -0x004001bc, -0x004001dc, -0x004001fc, -NV10_PGRAPH_CTX_USER, -NV04_PGRAPH_DMA_START_0, -NV04_PGRAPH_DMA_START_1, -NV04_PGRAPH_DMA_LENGTH, -NV04_PGRAPH_DMA_MISC, -NV10_PGRAPH_DMA_PITCH, -NV04_PGRAPH_BOFFSET0, -NV04_PGRAPH_BBASE0, -NV04_PGRAPH_BLIMIT0, -NV04_PGRAPH_BOFFSET1, -NV04_PGRAPH_BBASE1, -NV04_PGRAPH_BLIMIT1, -NV04_PGRAPH_BOFFSET2, -NV04_PGRAPH_BBASE2, -NV04_PGRAPH_BLIMIT2, -NV04_PGRAPH_BOFFSET3, -NV04_PGRAPH_BBASE3, -NV04_PGRAPH_BLIMIT3, -NV04_PGRAPH_BOFFSET4, -NV04_PGRAPH_BBASE4, -NV04_PGRAPH_BLIMIT4, -NV04_PGRAPH_BOFFSET5, -NV04_PGRAPH_BBASE5, -NV04_PGRAPH_BLIMIT5, -NV04_PGRAPH_BPITCH0, -NV04_PGRAPH_BPITCH1, -NV04_PGRAPH_BPITCH2, -NV04_PGRAPH_BPITCH3, -NV04_PGRAPH_BPITCH4, -NV10_PGRAPH_SURFACE, -NV10_PGRAPH_STATE, -NV04_PGRAPH_BSWIZZLE2, -NV04_PGRAPH_BSWIZZLE5, -NV04_PGRAPH_BPIXEL, -NV10_PGRAPH_NOTIFY, -NV04_PGRAPH_PATT_COLOR0, -NV04_PGRAPH_PATT_COLOR1, -NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */ -0x00400904, -0x00400908, -0x0040090c, -0x00400910, -0x00400914, -0x00400918, -0x0040091c, -0x00400920, -0x00400924, -0x00400928, -0x0040092c, -0x00400930, -0x00400934, -0x00400938, -0x0040093c, -0x00400940, -0x00400944, -0x00400948, -0x0040094c, -0x00400950, -0x00400954, -0x00400958, -0x0040095c, -0x00400960, -0x00400964, -0x00400968, -0x0040096c, -0x00400970, -0x00400974, -0x00400978, -0x0040097c, -0x00400980, -0x00400984, -0x00400988, -0x0040098c, -0x00400990, -0x00400994, -0x00400998, -0x0040099c, -0x004009a0, -0x004009a4, -0x004009a8, -0x004009ac, -0x004009b0, -0x004009b4, -0x004009b8, -0x004009bc, -0x004009c0, -0x004009c4, -0x004009c8, -0x004009cc, -0x004009d0, -0x004009d4, -0x004009d8, -0x004009dc, -0x004009e0, -0x004009e4, -0x004009e8, -0x004009ec, -0x004009f0, -0x004009f4, -0x004009f8, -0x004009fc, -NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */ -0x0040080c, -NV04_PGRAPH_PATTERN_SHAPE, -NV03_PGRAPH_MONO_COLOR0, -NV04_PGRAPH_ROP3, -NV04_PGRAPH_CHROMA, -NV04_PGRAPH_BETA_AND, -NV04_PGRAPH_BETA_PREMULT, -0x00400e70, -0x00400e74, -0x00400e78, -0x00400e7c, -0x00400e80, -0x00400e84, -0x00400e88, -0x00400e8c, -0x00400ea0, -0x00400ea4, -0x00400ea8, -0x00400e90, -0x00400e94, -0x00400e98, -0x00400e9c, -NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00 to 0x400f1c */ -NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20 to 0x400f3c */ -0x00400f04, -0x00400f24, -0x00400f08, -0x00400f28, -0x00400f0c, -0x00400f2c, -0x00400f10, -0x00400f30, -0x00400f14, -0x00400f34, -0x00400f18, -0x00400f38, -0x00400f1c, -0x00400f3c, -NV10_PGRAPH_XFMODE0, -NV10_PGRAPH_XFMODE1, -NV10_PGRAPH_GLOBALSTATE0, -NV10_PGRAPH_GLOBALSTATE1, -NV04_PGRAPH_STORED_FMT, -NV04_PGRAPH_SOURCE_COLOR, -NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */ -NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */ -0x00400404, -0x00400484, -0x00400408, -0x00400488, -0x0040040c, -0x0040048c, -0x00400410, -0x00400490, -0x00400414, -0x00400494, -0x00400418, -0x00400498, -0x0040041c, -0x0040049c, -0x00400420, -0x004004a0, -0x00400424, -0x004004a4, -0x00400428, -0x004004a8, -0x0040042c, -0x004004ac, -0x00400430, -0x004004b0, -0x00400434, -0x004004b4, -0x00400438, -0x004004b8, -0x0040043c, -0x004004bc, -0x00400440, -0x004004c0, -0x00400444, -0x004004c4, -0x00400448, -0x004004c8, -0x0040044c, -0x004004cc, -0x00400450, -0x004004d0, -0x00400454, -0x004004d4, -0x00400458, -0x004004d8, -0x0040045c, -0x004004dc, -0x00400460, -0x004004e0, -0x00400464, -0x004004e4, -0x00400468, -0x004004e8, -0x0040046c, -0x004004ec, -0x00400470, -0x004004f0, -0x00400474, -0x004004f4, -0x00400478, -0x004004f8, -0x0040047c, -0x004004fc, -NV03_PGRAPH_ABS_UCLIP_XMIN, -NV03_PGRAPH_ABS_UCLIP_XMAX, -NV03_PGRAPH_ABS_UCLIP_YMIN, -NV03_PGRAPH_ABS_UCLIP_YMAX, -0x00400550, -0x00400558, -0x00400554, -0x0040055c, -NV03_PGRAPH_ABS_UCLIPA_XMIN, -NV03_PGRAPH_ABS_UCLIPA_XMAX, -NV03_PGRAPH_ABS_UCLIPA_YMIN, -NV03_PGRAPH_ABS_UCLIPA_YMAX, -NV03_PGRAPH_ABS_ICLIP_XMAX, -NV03_PGRAPH_ABS_ICLIP_YMAX, -NV03_PGRAPH_XY_LOGIC_MISC0, -NV03_PGRAPH_XY_LOGIC_MISC1, -NV03_PGRAPH_XY_LOGIC_MISC2, -NV03_PGRAPH_XY_LOGIC_MISC3, -NV03_PGRAPH_CLIPX_0, -NV03_PGRAPH_CLIPX_1, -NV03_PGRAPH_CLIPY_0, -NV03_PGRAPH_CLIPY_1, -NV10_PGRAPH_COMBINER0_IN_ALPHA, -NV10_PGRAPH_COMBINER1_IN_ALPHA, -NV10_PGRAPH_COMBINER0_IN_RGB, -NV10_PGRAPH_COMBINER1_IN_RGB, -NV10_PGRAPH_COMBINER_COLOR0, -NV10_PGRAPH_COMBINER_COLOR1, -NV10_PGRAPH_COMBINER0_OUT_ALPHA, -NV10_PGRAPH_COMBINER1_OUT_ALPHA, -NV10_PGRAPH_COMBINER0_OUT_RGB, -NV10_PGRAPH_COMBINER1_OUT_RGB, -NV10_PGRAPH_COMBINER_FINAL0, -NV10_PGRAPH_COMBINER_FINAL1, -0x00400e00, -0x00400e04, -0x00400e08, -0x00400e0c, -0x00400e10, -0x00400e14, -0x00400e18, -0x00400e1c, -0x00400e20, -0x00400e24, -0x00400e28, -0x00400e2c, -0x00400e30, -0x00400e34, -0x00400e38, -0x00400e3c, -NV04_PGRAPH_PASSTHRU_0, -NV04_PGRAPH_PASSTHRU_1, -NV04_PGRAPH_PASSTHRU_2, -NV10_PGRAPH_DIMX_TEXTURE, -NV10_PGRAPH_WDIMX_TEXTURE, -NV10_PGRAPH_DVD_COLORFMT, -NV10_PGRAPH_SCALED_FORMAT, -NV04_PGRAPH_MISC24_0, -NV04_PGRAPH_MISC24_1, -NV04_PGRAPH_MISC24_2, -NV03_PGRAPH_X_MISC, -NV03_PGRAPH_Y_MISC, -NV04_PGRAPH_VALID1, -NV04_PGRAPH_VALID2, -}; - -static int nv17_graph_ctx_regs [] = { -NV10_PGRAPH_DEBUG_4, -0x004006b0, -0x00400eac, -0x00400eb0, -0x00400eb4, -0x00400eb8, -0x00400ebc, -0x00400ec0, -0x00400ec4, -0x00400ec8, -0x00400ecc, -0x00400ed0, -0x00400ed4, -0x00400ed8, -0x00400edc, -0x00400ee0, -0x00400a00, -0x00400a04, -}; - -struct graph_state { - int nv10[sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0])]; - int nv17[sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0])]; - struct pipe_state pipe_state; -}; - -static void nv10_graph_save_pipe(struct nouveau_channel *chan) { - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct graph_state* pgraph_ctx = chan->pgraph_ctx; - struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state; - int i; -#define PIPE_SAVE(addr) \ - do { \ - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, addr); \ - for (i=0; i < sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]); i++) \ - fifo_pipe_state->pipe_##addr[i] = NV_READ(NV10_PGRAPH_PIPE_DATA); \ - } while (0) - - PIPE_SAVE(0x4400); - PIPE_SAVE(0x0200); - PIPE_SAVE(0x6400); - PIPE_SAVE(0x6800); - PIPE_SAVE(0x6c00); - PIPE_SAVE(0x7000); - PIPE_SAVE(0x7400); - PIPE_SAVE(0x7800); - PIPE_SAVE(0x0040); - PIPE_SAVE(0x0000); - -#undef PIPE_SAVE -} - -static void nv10_graph_load_pipe(struct nouveau_channel *chan) { - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct graph_state* pgraph_ctx = chan->pgraph_ctx; - struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state; - int i; - uint32_t xfmode0, xfmode1; -#define PIPE_RESTORE(addr) \ - do { \ - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, addr); \ - for (i=0; i < sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]); i++) \ - NV_WRITE(NV10_PGRAPH_PIPE_DATA, fifo_pipe_state->pipe_##addr[i]); \ - } while (0) - - - nouveau_wait_for_idle(dev); - /* XXX check haiku comments */ - xfmode0 = NV_READ(NV10_PGRAPH_XFMODE0); - xfmode1 = NV_READ(NV10_PGRAPH_XFMODE1); - NV_WRITE(NV10_PGRAPH_XFMODE0, 0x10000000); - NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); - for (i = 0; i < 4; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); - for (i = 0; i < 4; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); - for (i = 0; i < 3; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); - - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); - for (i = 0; i < 3; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000008); - - - PIPE_RESTORE(0x0200); - nouveau_wait_for_idle(dev); - - /* restore XFMODE */ - NV_WRITE(NV10_PGRAPH_XFMODE0, xfmode0); - NV_WRITE(NV10_PGRAPH_XFMODE1, xfmode1); - PIPE_RESTORE(0x6400); - PIPE_RESTORE(0x6800); - PIPE_RESTORE(0x6c00); - PIPE_RESTORE(0x7000); - PIPE_RESTORE(0x7400); - PIPE_RESTORE(0x7800); - PIPE_RESTORE(0x4400); - PIPE_RESTORE(0x0000); - PIPE_RESTORE(0x0040); - nouveau_wait_for_idle(dev); - -#undef PIPE_RESTORE -} - -static void nv10_graph_create_pipe(struct nouveau_channel *chan) { - struct graph_state* pgraph_ctx = chan->pgraph_ctx; - struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state; - uint32_t *fifo_pipe_state_addr; - int i; -#define PIPE_INIT(addr) \ - do { \ - fifo_pipe_state_addr = fifo_pipe_state->pipe_##addr; \ - } while (0) -#define PIPE_INIT_END(addr) \ - do { \ - if (fifo_pipe_state_addr != \ - sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]) + fifo_pipe_state->pipe_##addr) \ - DRM_ERROR("incomplete pipe init for 0x%x : %p/%p\n", addr, fifo_pipe_state_addr, \ - sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]) + fifo_pipe_state->pipe_##addr); \ - } while (0) -#define NV_WRITE_PIPE_INIT(value) *(fifo_pipe_state_addr++) = value - - PIPE_INIT(0x0200); - for (i = 0; i < 48; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x0200); - - PIPE_INIT(0x6400); - for (i = 0; i < 211; i++) - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x40000000); - NV_WRITE_PIPE_INIT(0x40000000); - NV_WRITE_PIPE_INIT(0x40000000); - NV_WRITE_PIPE_INIT(0x40000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f000000); - NV_WRITE_PIPE_INIT(0x3f000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x3f800000); - PIPE_INIT_END(0x6400); - - PIPE_INIT(0x6800); - for (i = 0; i < 162; i++) - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f800000); - for (i = 0; i < 25; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x6800); - - PIPE_INIT(0x6c00); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0xbf800000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x6c00); - - PIPE_INIT(0x7000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - for (i = 0; i < 35; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x7000); - - PIPE_INIT(0x7400); - for (i = 0; i < 48; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x7400); - - PIPE_INIT(0x7800); - for (i = 0; i < 48; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x7800); - - PIPE_INIT(0x4400); - for (i = 0; i < 32; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x4400); - - PIPE_INIT(0x0000); - for (i = 0; i < 16; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x0000); - - PIPE_INIT(0x0040); - for (i = 0; i < 4; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x0040); - -#undef PIPE_INIT -#undef PIPE_INIT_END -#undef NV_WRITE_PIPE_INIT -} - -static int nv10_graph_ctx_regs_find_offset(struct drm_device *dev, int reg) -{ - int i; - for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) { - if (nv10_graph_ctx_regs[i] == reg) - return i; - } - DRM_ERROR("unknow offset nv10_ctx_regs %d\n", reg); - return -1; -} - -static int nv17_graph_ctx_regs_find_offset(struct drm_device *dev, int reg) -{ - int i; - for (i = 0; i < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++) { - if (nv17_graph_ctx_regs[i] == reg) - return i; - } - DRM_ERROR("unknow offset nv17_ctx_regs %d\n", reg); - return -1; -} - -int nv10_graph_load_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct graph_state* pgraph_ctx = chan->pgraph_ctx; - int i; - - for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) - NV_WRITE(nv10_graph_ctx_regs[i], pgraph_ctx->nv10[i]); - if (dev_priv->chipset>=0x17) { - for (i = 0; i < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++) - NV_WRITE(nv17_graph_ctx_regs[i], pgraph_ctx->nv17[i]); - } - - nv10_graph_load_pipe(chan); - - return 0; -} - -int nv10_graph_save_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct graph_state* pgraph_ctx = chan->pgraph_ctx; - int i; - - for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) - pgraph_ctx->nv10[i] = NV_READ(nv10_graph_ctx_regs[i]); - if (dev_priv->chipset>=0x17) { - for (i = 0; i < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++) - pgraph_ctx->nv17[i] = NV_READ(nv17_graph_ctx_regs[i]); - } - - nv10_graph_save_pipe(chan); - - return 0; -} - -void nouveau_nv10_context_switch(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv; - struct nouveau_engine *engine; - struct nouveau_channel *next, *last; - int chid; - - if (!dev) { - DRM_DEBUG("Invalid drm_device\n"); - return; - } - dev_priv = dev->dev_private; - if (!dev_priv) { - DRM_DEBUG("Invalid drm_nouveau_private\n"); - return; - } - if (!dev_priv->fifos) { - DRM_DEBUG("Invalid drm_nouveau_private->fifos\n"); - return; - } - engine = &dev_priv->Engine; - - chid = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20) & - (engine->fifo.channels - 1); - next = dev_priv->fifos[chid]; - - if (!next) { - DRM_ERROR("Invalid next channel\n"); - return; - } - - chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & - (engine->fifo.channels - 1); - last = dev_priv->fifos[chid]; - - if (!last) { - DRM_INFO("WARNING: Invalid last channel, switch to %x\n", - next->id); - } else { - DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n", - last->id, next->id); - } - - NV_WRITE(NV04_PGRAPH_FIFO,0x0); - if (last) { - nouveau_wait_for_idle(dev); - nv10_graph_save_context(last); - } - - nouveau_wait_for_idle(dev); - - NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000000); - - nouveau_wait_for_idle(dev); - - nv10_graph_load_context(next); - - NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100); - NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); - NV_WRITE(NV04_PGRAPH_FIFO,0x1); -} - -#define NV_WRITE_CTX(reg, val) do { \ - int offset = nv10_graph_ctx_regs_find_offset(dev, reg); \ - if (offset > 0) \ - pgraph_ctx->nv10[offset] = val; \ - } while (0) - -#define NV17_WRITE_CTX(reg, val) do { \ - int offset = nv17_graph_ctx_regs_find_offset(dev, reg); \ - if (offset > 0) \ - pgraph_ctx->nv17[offset] = val; \ - } while (0) - -int nv10_graph_create_context(struct nouveau_channel *chan) { - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct graph_state* pgraph_ctx; - - DRM_DEBUG("nv10_graph_context_create %d\n", chan->id); - - chan->pgraph_ctx = pgraph_ctx = drm_calloc(1, sizeof(*pgraph_ctx), - DRM_MEM_DRIVER); - - if (pgraph_ctx == NULL) - return -ENOMEM; - - /* mmio trace suggest that should be done in ddx with methods/objects */ -#if 0 - uint32_t tmp, vramsz; - /* per channel init from ddx */ - tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; - /*XXX the original ddx code, does this in 2 steps : - * tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; - * NV_WRITE(NV10_PGRAPH_SURFACE, tmp); - * tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100; - * NV_WRITE(NV10_PGRAPH_SURFACE, tmp); - */ - tmp |= 0x00020100; - NV_WRITE_CTX(NV10_PGRAPH_SURFACE, tmp); - - vramsz = drm_get_resource_len(dev, 0) - 1; - NV_WRITE_CTX(NV04_PGRAPH_BOFFSET0, 0); - NV_WRITE_CTX(NV04_PGRAPH_BOFFSET1, 0); - NV_WRITE_CTX(NV04_PGRAPH_BLIMIT0 , vramsz); - NV_WRITE_CTX(NV04_PGRAPH_BLIMIT1 , vramsz); - - NV_WRITE_CTX(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000); - NV_WRITE_CTX(NV04_PGRAPH_BETA_AND , 0xFFFFFFFF); - - NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_XMIN, 0); - NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_YMIN, 0); - NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); - NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); -#endif - - NV_WRITE_CTX(0x00400e88, 0x08000000); - NV_WRITE_CTX(0x00400e9c, 0x4b7fffff); - NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff); - NV_WRITE_CTX(0x00400e10, 0x00001000); - NV_WRITE_CTX(0x00400e14, 0x00001000); - NV_WRITE_CTX(0x00400e30, 0x00080008); - NV_WRITE_CTX(0x00400e34, 0x00080008); - if (dev_priv->chipset>=0x17) { - /* is it really needed ??? */ - NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4, NV_READ(NV10_PGRAPH_DEBUG_4)); - NV17_WRITE_CTX(0x004006b0, NV_READ(0x004006b0)); - NV17_WRITE_CTX(0x00400eac, 0x0fff0000); - NV17_WRITE_CTX(0x00400eb0, 0x0fff0000); - NV17_WRITE_CTX(0x00400ec0, 0x00000080); - NV17_WRITE_CTX(0x00400ed0, 0x00000080); - } - NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->id << 24); - - nv10_graph_create_pipe(chan); - return 0; -} - -void nv10_graph_destroy_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine *engine = &dev_priv->Engine; - struct graph_state* pgraph_ctx = chan->pgraph_ctx; - int chid; - - drm_free(pgraph_ctx, sizeof(*pgraph_ctx), DRM_MEM_DRIVER); - chan->pgraph_ctx = NULL; - - chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (engine->fifo.channels - 1); - - /* This code seems to corrupt the 3D pipe, but blob seems to do similar things ???? - */ -#if 0 - /* does this avoid a potential context switch while we are written graph - * reg, or we should mask graph interrupt ??? - */ - NV_WRITE(NV04_PGRAPH_FIFO,0x0); - if (chid == chan->id) { - DRM_INFO("cleanning a channel with graph in current context\n"); - nouveau_wait_for_idle(dev); - DRM_INFO("reseting current graph context\n"); - /* can't be call here because of dynamic mem alloc */ - //nv10_graph_create_context(chan); - nv10_graph_load_context(chan); - } - NV_WRITE(NV04_PGRAPH_FIFO, 0x1); -#else - if (chid == chan->id) { - DRM_INFO("cleanning a channel with graph in current context\n"); - } -#endif -} - -int nv10_graph_init(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & - ~NV_PMC_ENABLE_PGRAPH); - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | - NV_PMC_ENABLE_PGRAPH); - - NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); - NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); - NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700); - //NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x24E00810); /* 0x25f92ad9 */ - NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x25f92ad9); - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x55DE0830 | - (1<<29) | - (1<<31)); - if (dev_priv->chipset>=0x17) { - NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x1f000000); - NV_WRITE(0x004006b0, 0x40000020); - } - else - NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000); - - /* copy tile info from PFB */ - for (i=0; idev_private; - int i; -/* -write32 #1 block at +0x00740adc NV_PRAMIN+0x40adc of 3369 (0xd29) elements: -+0x00740adc: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740b3c: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000 -+0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740bbc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740bdc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740bfc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 - -+0x00740c1c: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000 -+0x00740c3c: 00000000 00000000 00000000 44400000 00000000 00000000 00000000 00000000 -+0x00740c5c: 00000000 00000000 00000000 00000000 00000000 00000000 00030303 00030303 -+0x00740c7c: 00030303 00030303 00000000 00000000 00000000 00000000 00080000 00080000 -+0x00740c9c: 00080000 00080000 00000000 00000000 01012000 01012000 01012000 01012000 -+0x00740cbc: 000105b8 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008 -+0x00740cdc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740cfc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 -+0x00740d1c: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 -+0x00740d3c: 00000000 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000 - -+0x00740d5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740d7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740d9c: 00000001 00000000 00004000 00000000 00000000 00000001 00000000 00040000 -+0x00740dbc: 00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740ddc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -... -*/ - INSTANCE_WR(ctx, (0x33c/4)+0, 0xffff0000); - INSTANCE_WR(ctx, (0x33c/4)+25, 0x0fff0000); - INSTANCE_WR(ctx, (0x33c/4)+26, 0x0fff0000); - INSTANCE_WR(ctx, (0x33c/4)+80, 0x00000101); - INSTANCE_WR(ctx, (0x33c/4)+85, 0x00000111); - INSTANCE_WR(ctx, (0x33c/4)+91, 0x44400000); - for (i = 0; i < 4; ++i) - INSTANCE_WR(ctx, (0x33c/4)+102+i, 0x00030303); - for (i = 0; i < 4; ++i) - INSTANCE_WR(ctx, (0x33c/4)+110+i, 0x00080000); - for (i = 0; i < 4; ++i) - INSTANCE_WR(ctx, (0x33c/4)+116+i, 0x01012000); - for (i = 0; i < 4; ++i) - INSTANCE_WR(ctx, (0x33c/4)+120+i, 0x000105b8); - for (i = 0; i < 4; ++i) - INSTANCE_WR(ctx, (0x33c/4)+124+i, 0x00080008); - for (i = 0; i < 16; ++i) - INSTANCE_WR(ctx, (0x33c/4)+136+i, 0x07ff0000); - INSTANCE_WR(ctx, (0x33c/4)+154, 0x4b7fffff); - INSTANCE_WR(ctx, (0x33c/4)+176, 0x00000001); - INSTANCE_WR(ctx, (0x33c/4)+178, 0x00004000); - INSTANCE_WR(ctx, (0x33c/4)+181, 0x00000001); - INSTANCE_WR(ctx, (0x33c/4)+183, 0x00040000); - INSTANCE_WR(ctx, (0x33c/4)+184, 0x00010000); - -/* -... -+0x0074239c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x007423bc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -+0x007423dc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -+0x007423fc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -... -+0x00742bdc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -+0x00742bfc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -+0x00742c1c: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -+0x00742c3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -... -*/ - for (i = 0; i < 0x880; i += 0x10) { - INSTANCE_WR(ctx, ((0x1c1c + i)/4)+0, 0x10700ff9); - INSTANCE_WR(ctx, ((0x1c1c + i)/4)+1, 0x0436086c); - INSTANCE_WR(ctx, ((0x1c1c + i)/4)+2, 0x000c001b); - } - -/* -write32 #1 block at +0x00742fbc NV_PRAMIN+0x42fbc of 4 (0x4) elements: -+0x00742fbc: 3f800000 00000000 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x281c/4), 0x3f800000); - -/* -write32 #1 block at +0x00742ffc NV_PRAMIN+0x42ffc of 12 (0xc) elements: -+0x00742ffc: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000 -+0x0074301c: 00000000 bf800000 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x285c/4)+0, 0x40000000); - INSTANCE_WR(ctx, (0x285c/4)+1, 0x3f800000); - INSTANCE_WR(ctx, (0x285c/4)+2, 0x3f000000); - INSTANCE_WR(ctx, (0x285c/4)+4, 0x40000000); - INSTANCE_WR(ctx, (0x285c/4)+5, 0x3f800000); - INSTANCE_WR(ctx, (0x285c/4)+7, 0xbf800000); - INSTANCE_WR(ctx, (0x285c/4)+9, 0xbf800000); - -/* -write32 #1 block at +0x00742fcc NV_PRAMIN+0x42fcc of 4 (0x4) elements: -+0x00742fcc: 00000000 3f800000 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x282c/4)+1, 0x3f800000); - -/* -write32 #1 block at +0x0074302c NV_PRAMIN+0x4302c of 4 (0x4) elements: -+0x0074302c: 00000000 00000000 00000000 00000000 -write32 #1 block at +0x00743c9c NV_PRAMIN+0x43c9c of 4 (0x4) elements: -+0x00743c9c: 00000000 00000000 00000000 00000000 -write32 #1 block at +0x00743c3c NV_PRAMIN+0x43c3c of 8 (0x8) elements: -+0x00743c3c: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x349c/4)+2, 0x000fe000); - -/* -write32 #1 block at +0x00743c6c NV_PRAMIN+0x43c6c of 4 (0x4) elements: -+0x00743c6c: 00000000 00000000 00000000 00000000 -write32 #1 block at +0x00743ccc NV_PRAMIN+0x43ccc of 4 (0x4) elements: -+0x00743ccc: 00000000 000003f8 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x352c/4)+1, 0x000003f8); - -/* write32 #1 NV_PRAMIN+0x43ce0 <- 0x002fe000 */ - INSTANCE_WR(ctx, 0x3540/4, 0x002fe000); - -/* -write32 #1 block at +0x00743cfc NV_PRAMIN+0x43cfc of 8 (0x8) elements: -+0x00743cfc: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c -*/ - for (i = 0; i < 8; ++i) - INSTANCE_WR(ctx, (0x355c/4)+i, 0x001c527c); -} - -static void nv2a_graph_context_init(struct drm_device *dev, - struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - INSTANCE_WR(ctx, 0x33c/4, 0xffff0000); - for(i = 0x3a0; i< 0x3a8; i += 4) - INSTANCE_WR(ctx, i/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x47c/4, 0x00000101); - INSTANCE_WR(ctx, 0x490/4, 0x00000111); - INSTANCE_WR(ctx, 0x4a8/4, 0x44400000); - for(i = 0x4d4; i< 0x4e4; i += 4) - INSTANCE_WR(ctx, i/4, 0x00030303); - for(i = 0x4f4; i< 0x504; i += 4) - INSTANCE_WR(ctx, i/4, 0x00080000); - for(i = 0x50c; i< 0x51c; i += 4) - INSTANCE_WR(ctx, i/4, 0x01012000); - for(i = 0x51c; i< 0x52c; i += 4) - INSTANCE_WR(ctx, i/4, 0x000105b8); - for(i = 0x52c; i< 0x53c; i += 4) - INSTANCE_WR(ctx, i/4, 0x00080008); - for(i = 0x55c; i< 0x59c; i += 4) - INSTANCE_WR(ctx, i/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x5a4/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x5fc/4, 0x00000001); - INSTANCE_WR(ctx, 0x604/4, 0x00004000); - INSTANCE_WR(ctx, 0x610/4, 0x00000001); - INSTANCE_WR(ctx, 0x618/4, 0x00040000); - INSTANCE_WR(ctx, 0x61c/4, 0x00010000); - - for (i=0x1a9c; i <= 0x22fc/4; i += 32) { - INSTANCE_WR(ctx, i/4 , 0x10700ff9); - INSTANCE_WR(ctx, i/4 + 1, 0x0436086c); - INSTANCE_WR(ctx, i/4 + 2, 0x000c001b); - } - - INSTANCE_WR(ctx, 0x269c/4, 0x3f800000); - INSTANCE_WR(ctx, 0x26b0/4, 0x3f800000); - INSTANCE_WR(ctx, 0x26dc/4, 0x40000000); - INSTANCE_WR(ctx, 0x26e0/4, 0x3f800000); - INSTANCE_WR(ctx, 0x26e4/4, 0x3f000000); - INSTANCE_WR(ctx, 0x26ec/4, 0x40000000); - INSTANCE_WR(ctx, 0x26f0/4, 0x3f800000); - INSTANCE_WR(ctx, 0x26f8/4, 0xbf800000); - INSTANCE_WR(ctx, 0x2700/4, 0xbf800000); - INSTANCE_WR(ctx, 0x3024/4, 0x000fe000); - INSTANCE_WR(ctx, 0x30a0/4, 0x000003f8); - INSTANCE_WR(ctx, 0x33fc/4, 0x002fe000); - for(i = 0x341c; i< 0x343c; i += 4) - INSTANCE_WR(ctx, i/4, 0x001c527c); -} - -static void nv25_graph_context_init(struct drm_device *dev, - struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; -/* -write32 #1 block at +0x00740a7c NV_PRAMIN.GRCTX0+0x35c of 173 (0xad) elements: -+0x00740a7c: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740a9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740abc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740adc: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000 -+0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740b3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 - -+0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740bbc: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000 -+0x00740bdc: 00000000 00000000 00000000 00000080 ffff0000 00000001 00000000 00000000 -+0x00740bfc: 00000000 00000000 44400000 00000000 00000000 00000000 00000000 00000000 -+0x00740c1c: 4b800000 00000000 00000000 00000000 00000000 00030303 00030303 00030303 -+0x00740c3c: 00030303 00000000 00000000 00000000 00000000 00080000 00080000 00080000 -+0x00740c5c: 00080000 00000000 00000000 01012000 01012000 01012000 01012000 000105b8 - -+0x00740c7c: 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008 00000000 -+0x00740c9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 07ff0000 -+0x00740cbc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 -+0x00740cdc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 00000000 -+0x00740cfc: 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740d1c: 00000000 00000000 00000000 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x35c/4)+0, 0xffff0000); - INSTANCE_WR(ctx, (0x35c/4)+25, 0x0fff0000); - INSTANCE_WR(ctx, (0x35c/4)+26, 0x0fff0000); - INSTANCE_WR(ctx, (0x35c/4)+80, 0x00000101); - INSTANCE_WR(ctx, (0x35c/4)+85, 0x00000111); - INSTANCE_WR(ctx, (0x35c/4)+91, 0x00000080); - INSTANCE_WR(ctx, (0x35c/4)+92, 0xffff0000); - INSTANCE_WR(ctx, (0x35c/4)+93, 0x00000001); - INSTANCE_WR(ctx, (0x35c/4)+98, 0x44400000); - INSTANCE_WR(ctx, (0x35c/4)+104, 0x4b800000); - INSTANCE_WR(ctx, (0x35c/4)+109, 0x00030303); - INSTANCE_WR(ctx, (0x35c/4)+110, 0x00030303); - INSTANCE_WR(ctx, (0x35c/4)+111, 0x00030303); - INSTANCE_WR(ctx, (0x35c/4)+112, 0x00030303); - INSTANCE_WR(ctx, (0x35c/4)+117, 0x00080000); - INSTANCE_WR(ctx, (0x35c/4)+118, 0x00080000); - INSTANCE_WR(ctx, (0x35c/4)+119, 0x00080000); - INSTANCE_WR(ctx, (0x35c/4)+120, 0x00080000); - INSTANCE_WR(ctx, (0x35c/4)+123, 0x01012000); - INSTANCE_WR(ctx, (0x35c/4)+124, 0x01012000); - INSTANCE_WR(ctx, (0x35c/4)+125, 0x01012000); - INSTANCE_WR(ctx, (0x35c/4)+126, 0x01012000); - INSTANCE_WR(ctx, (0x35c/4)+127, 0x000105b8); - INSTANCE_WR(ctx, (0x35c/4)+128, 0x000105b8); - INSTANCE_WR(ctx, (0x35c/4)+129, 0x000105b8); - INSTANCE_WR(ctx, (0x35c/4)+130, 0x000105b8); - INSTANCE_WR(ctx, (0x35c/4)+131, 0x00080008); - INSTANCE_WR(ctx, (0x35c/4)+132, 0x00080008); - INSTANCE_WR(ctx, (0x35c/4)+133, 0x00080008); - INSTANCE_WR(ctx, (0x35c/4)+134, 0x00080008); - for (i=0; i<16; ++i) - INSTANCE_WR(ctx, (0x35c/4)+143+i, 0x07ff0000); - INSTANCE_WR(ctx, (0x35c/4)+161, 0x4b7fffff); - -/* -write32 #1 block at +0x00740d34 NV_PRAMIN.GRCTX0+0x614 of 3136 (0xc40) elements: -+0x00740d34: 00000000 00000000 00000000 00000080 30201000 70605040 b0a09080 f0e0d0c0 -+0x00740d54: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740d74: 00000000 00000000 00000000 00000000 00000001 00000000 00004000 00000000 -+0x00740d94: 00000000 00000001 00000000 00040000 00010000 00000000 00000000 00000000 -+0x00740db4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -... -+0x00742214: 00000000 00000000 00000000 00000000 10700ff9 0436086c 000c001b 00000000 -+0x00742234: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -+0x00742254: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -+0x00742274: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -... -+0x00742a34: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -+0x00742a54: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -+0x00742a74: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -+0x00742a94: 10700ff9 0436086c 000c001b 00000000 00000000 00000000 00000000 00000000 -+0x00742ab4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00742ad4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x614/4)+3, 0x00000080); - INSTANCE_WR(ctx, (0x614/4)+4, 0x30201000); - INSTANCE_WR(ctx, (0x614/4)+5, 0x70605040); - INSTANCE_WR(ctx, (0x614/4)+6, 0xb0a09080); - INSTANCE_WR(ctx, (0x614/4)+7, 0xf0e0d0c0); - INSTANCE_WR(ctx, (0x614/4)+20, 0x00000001); - INSTANCE_WR(ctx, (0x614/4)+22, 0x00004000); - INSTANCE_WR(ctx, (0x614/4)+25, 0x00000001); - INSTANCE_WR(ctx, (0x614/4)+27, 0x00040000); - INSTANCE_WR(ctx, (0x614/4)+28, 0x00010000); - for (i=0; i < 0x880/4; i+=4) { - INSTANCE_WR(ctx, (0x1b04/4)+i+0, 0x10700ff9); - INSTANCE_WR(ctx, (0x1b04/4)+i+1, 0x0436086c); - INSTANCE_WR(ctx, (0x1b04/4)+i+2, 0x000c001b); - } - -/* -write32 #1 block at +0x00742e24 NV_PRAMIN.GRCTX0+0x2704 of 4 (0x4) elements: -+0x00742e24: 3f800000 00000000 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x2704/4), 0x3f800000); - -/* -write32 #1 block at +0x00742e64 NV_PRAMIN.GRCTX0+0x2744 of 12 (0xc) elements: -+0x00742e64: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000 -+0x00742e84: 00000000 bf800000 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x2744/4)+0, 0x40000000); - INSTANCE_WR(ctx, (0x2744/4)+1, 0x3f800000); - INSTANCE_WR(ctx, (0x2744/4)+2, 0x3f000000); - INSTANCE_WR(ctx, (0x2744/4)+4, 0x40000000); - INSTANCE_WR(ctx, (0x2744/4)+5, 0x3f800000); - INSTANCE_WR(ctx, (0x2744/4)+7, 0xbf800000); - INSTANCE_WR(ctx, (0x2744/4)+9, 0xbf800000); - -/* -write32 #1 block at +0x00742e34 NV_PRAMIN.GRCTX0+0x2714 of 4 (0x4) elements: -+0x00742e34: 00000000 3f800000 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x2714/4)+1, 0x3f800000); - -/* -write32 #1 block at +0x00742e94 NV_PRAMIN.GRCTX0+0x2774 of 4 (0x4) elements: -+0x00742e94: 00000000 00000000 00000000 00000000 -write32 #1 block at +0x00743804 NV_PRAMIN.GRCTX0+0x30e4 of 4 (0x4) elements: -+0x00743804: 00000000 00000000 00000000 00000000 -write32 #1 block at +0x007437a4 NV_PRAMIN.GRCTX0+0x3084 of 8 (0x8) elements: -+0x007437a4: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x3084/4)+2, 0x000fe000); - -/* -write32 #1 block at +0x007437d4 NV_PRAMIN.GRCTX0+0x30b4 of 4 (0x4) elements: -+0x007437d4: 00000000 00000000 00000000 00000000 -write32 #1 block at +0x00743824 NV_PRAMIN.GRCTX0+0x3104 of 4 (0x4) elements: -+0x00743824: 00000000 000003f8 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x3104/4)+1, 0x000003f8); - -/* write32 #1 NV_PRAMIN.GRCTX0+0x3468 <- 0x002fe000 */ - INSTANCE_WR(ctx, 0x3468/4, 0x002fe000); - -/* -write32 #1 block at +0x00743ba4 NV_PRAMIN.GRCTX0+0x3484 of 8 (0x8) elements: -+0x00743ba4: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c -*/ - for (i=0; i<8; ++i) - INSTANCE_WR(ctx, (0x3484/4)+i, 0x001c527c); -} - -static void nv30_31_graph_context_init(struct drm_device *dev, - struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - INSTANCE_WR(ctx, 0x410/4, 0x00000101); - INSTANCE_WR(ctx, 0x424/4, 0x00000111); - INSTANCE_WR(ctx, 0x428/4, 0x00000060); - INSTANCE_WR(ctx, 0x444/4, 0x00000080); - INSTANCE_WR(ctx, 0x448/4, 0xffff0000); - INSTANCE_WR(ctx, 0x44c/4, 0x00000001); - INSTANCE_WR(ctx, 0x460/4, 0x44400000); - INSTANCE_WR(ctx, 0x48c/4, 0xffff0000); - for(i = 0x4e0; i< 0x4e8; i += 4) - INSTANCE_WR(ctx, i/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x4ec/4, 0x00011100); - for(i = 0x508; i< 0x548; i += 4) - INSTANCE_WR(ctx, i/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x550/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x58c/4, 0x00000080); - INSTANCE_WR(ctx, 0x590/4, 0x30201000); - INSTANCE_WR(ctx, 0x594/4, 0x70605040); - INSTANCE_WR(ctx, 0x598/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x59c/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x5b0/4, 0xb0000000); - for(i = 0x600; i< 0x640; i += 4) - INSTANCE_WR(ctx, i/4, 0x00010588); - for(i = 0x640; i< 0x680; i += 4) - INSTANCE_WR(ctx, i/4, 0x00030303); - for(i = 0x6c0; i< 0x700; i += 4) - INSTANCE_WR(ctx, i/4, 0x0008aae4); - for(i = 0x700; i< 0x740; i += 4) - INSTANCE_WR(ctx, i/4, 0x01012000); - for(i = 0x740; i< 0x780; i += 4) - INSTANCE_WR(ctx, i/4, 0x00080008); - INSTANCE_WR(ctx, 0x85c/4, 0x00040000); - INSTANCE_WR(ctx, 0x860/4, 0x00010000); - for(i = 0x864; i< 0x874; i += 4) - INSTANCE_WR(ctx, i/4, 0x00040004); - for(i = 0x1f18; i<= 0x3088 ; i+= 16) { - INSTANCE_WR(ctx, i/4 + 0, 0x10700ff9); - INSTANCE_WR(ctx, i/4 + 1, 0x0436086c); - INSTANCE_WR(ctx, i/4 + 2, 0x000c001b); - } - for(i = 0x30b8; i< 0x30c8; i += 4) - INSTANCE_WR(ctx, i/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x344c/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3808/4, 0x3f800000); - INSTANCE_WR(ctx, 0x381c/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3848/4, 0x40000000); - INSTANCE_WR(ctx, 0x384c/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3850/4, 0x3f000000); - INSTANCE_WR(ctx, 0x3858/4, 0x40000000); - INSTANCE_WR(ctx, 0x385c/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3864/4, 0xbf800000); - INSTANCE_WR(ctx, 0x386c/4, 0xbf800000); -} - -static void nv34_graph_context_init(struct drm_device *dev, - struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - INSTANCE_WR(ctx, 0x40c/4, 0x01000101); - INSTANCE_WR(ctx, 0x420/4, 0x00000111); - INSTANCE_WR(ctx, 0x424/4, 0x00000060); - INSTANCE_WR(ctx, 0x440/4, 0x00000080); - INSTANCE_WR(ctx, 0x444/4, 0xffff0000); - INSTANCE_WR(ctx, 0x448/4, 0x00000001); - INSTANCE_WR(ctx, 0x45c/4, 0x44400000); - INSTANCE_WR(ctx, 0x480/4, 0xffff0000); - for(i = 0x4d4; i< 0x4dc; i += 4) - INSTANCE_WR(ctx, i/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x4e0/4, 0x00011100); - for(i = 0x4fc; i< 0x53c; i += 4) - INSTANCE_WR(ctx, i/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x544/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x57c/4, 0x00000080); - INSTANCE_WR(ctx, 0x580/4, 0x30201000); - INSTANCE_WR(ctx, 0x584/4, 0x70605040); - INSTANCE_WR(ctx, 0x588/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x58c/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x5a0/4, 0xb0000000); - for(i = 0x5f0; i< 0x630; i += 4) - INSTANCE_WR(ctx, i/4, 0x00010588); - for(i = 0x630; i< 0x670; i += 4) - INSTANCE_WR(ctx, i/4, 0x00030303); - for(i = 0x6b0; i< 0x6f0; i += 4) - INSTANCE_WR(ctx, i/4, 0x0008aae4); - for(i = 0x6f0; i< 0x730; i += 4) - INSTANCE_WR(ctx, i/4, 0x01012000); - for(i = 0x730; i< 0x770; i += 4) - INSTANCE_WR(ctx, i/4, 0x00080008); - INSTANCE_WR(ctx, 0x850/4, 0x00040000); - INSTANCE_WR(ctx, 0x854/4, 0x00010000); - for(i = 0x858; i< 0x868; i += 4) - INSTANCE_WR(ctx, i/4, 0x00040004); - for(i = 0x15ac; i<= 0x271c ; i+= 16) { - INSTANCE_WR(ctx, i/4 + 0, 0x10700ff9); - INSTANCE_WR(ctx, i/4 + 1, 0x0436086c); - INSTANCE_WR(ctx, i/4 + 2, 0x000c001b); - } - for(i = 0x274c; i< 0x275c; i += 4) - INSTANCE_WR(ctx, i/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x2ae0/4, 0x3f800000); - INSTANCE_WR(ctx, 0x2e9c/4, 0x3f800000); - INSTANCE_WR(ctx, 0x2eb0/4, 0x3f800000); - INSTANCE_WR(ctx, 0x2edc/4, 0x40000000); - INSTANCE_WR(ctx, 0x2ee0/4, 0x3f800000); - INSTANCE_WR(ctx, 0x2ee4/4, 0x3f000000); - INSTANCE_WR(ctx, 0x2eec/4, 0x40000000); - INSTANCE_WR(ctx, 0x2ef0/4, 0x3f800000); - INSTANCE_WR(ctx, 0x2ef8/4, 0xbf800000); - INSTANCE_WR(ctx, 0x2f00/4, 0xbf800000); -} - -static void nv35_36_graph_context_init(struct drm_device *dev, - struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - INSTANCE_WR(ctx, 0x40c/4, 0x00000101); - INSTANCE_WR(ctx, 0x420/4, 0x00000111); - INSTANCE_WR(ctx, 0x424/4, 0x00000060); - INSTANCE_WR(ctx, 0x440/4, 0x00000080); - INSTANCE_WR(ctx, 0x444/4, 0xffff0000); - INSTANCE_WR(ctx, 0x448/4, 0x00000001); - INSTANCE_WR(ctx, 0x45c/4, 0x44400000); - INSTANCE_WR(ctx, 0x488/4, 0xffff0000); - for(i = 0x4dc; i< 0x4e4; i += 4) - INSTANCE_WR(ctx, i/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x4e8/4, 0x00011100); - for(i = 0x504; i< 0x544; i += 4) - INSTANCE_WR(ctx, i/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x54c/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x588/4, 0x00000080); - INSTANCE_WR(ctx, 0x58c/4, 0x30201000); - INSTANCE_WR(ctx, 0x590/4, 0x70605040); - INSTANCE_WR(ctx, 0x594/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x598/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x5ac/4, 0xb0000000); - for(i = 0x604; i< 0x644; i += 4) - INSTANCE_WR(ctx, i/4, 0x00010588); - for(i = 0x644; i< 0x684; i += 4) - INSTANCE_WR(ctx, i/4, 0x00030303); - for(i = 0x6c4; i< 0x704; i += 4) - INSTANCE_WR(ctx, i/4, 0x0008aae4); - for(i = 0x704; i< 0x744; i += 4) - INSTANCE_WR(ctx, i/4, 0x01012000); - for(i = 0x744; i< 0x784; i += 4) - INSTANCE_WR(ctx, i/4, 0x00080008); - INSTANCE_WR(ctx, 0x860/4, 0x00040000); - INSTANCE_WR(ctx, 0x864/4, 0x00010000); - for(i = 0x868; i< 0x878; i += 4) - INSTANCE_WR(ctx, i/4, 0x00040004); - for(i = 0x1f1c; i<= 0x308c ; i+= 16) { - INSTANCE_WR(ctx, i/4 + 0, 0x10700ff9); - INSTANCE_WR(ctx, i/4 + 1, 0x0436086c); - INSTANCE_WR(ctx, i/4 + 2, 0x000c001b); - } - for(i = 0x30bc; i< 0x30cc; i += 4) - INSTANCE_WR(ctx, i/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x3450/4, 0x3f800000); - INSTANCE_WR(ctx, 0x380c/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3820/4, 0x3f800000); - INSTANCE_WR(ctx, 0x384c/4, 0x40000000); - INSTANCE_WR(ctx, 0x3850/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3854/4, 0x3f000000); - INSTANCE_WR(ctx, 0x385c/4, 0x40000000); - INSTANCE_WR(ctx, 0x3860/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3868/4, 0xbf800000); - INSTANCE_WR(ctx, 0x3870/4, 0xbf800000); -} - -int nv20_graph_create_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *); - unsigned int ctx_size; - unsigned int idoffs = 0x28/4; - int ret; - - switch (dev_priv->chipset) { - case 0x20: - ctx_size = NV20_GRCTX_SIZE; - ctx_init = nv20_graph_context_init; - idoffs = 0; - break; - case 0x25: - case 0x28: - ctx_size = NV25_GRCTX_SIZE; - ctx_init = nv25_graph_context_init; - break; - case 0x2a: - ctx_size = NV2A_GRCTX_SIZE; - ctx_init = nv2a_graph_context_init; - idoffs = 0; - break; - case 0x30: - case 0x31: - ctx_size = NV30_31_GRCTX_SIZE; - ctx_init = nv30_31_graph_context_init; - break; - case 0x34: - ctx_size = NV34_GRCTX_SIZE; - ctx_init = nv34_graph_context_init; - break; - case 0x35: - case 0x36: - ctx_size = NV35_36_GRCTX_SIZE; - ctx_init = nv35_36_graph_context_init; - break; - default: - ctx_size = 0; - ctx_init = nv35_36_graph_context_init; - DRM_ERROR("Please contact the devs if you want your NV%x" - " card to work\n", dev_priv->chipset); - return -ENOSYS; - break; - } - - if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16, - NVOBJ_FLAG_ZERO_ALLOC, - &chan->ramin_grctx))) - return ret; - - /* Initialise default context values */ - ctx_init(dev, chan->ramin_grctx->gpuobj); - - /* nv20: INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); */ - INSTANCE_WR(chan->ramin_grctx->gpuobj, idoffs, (chan->id<<24)|0x1); - /* CTX_USER */ - - INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, - chan->ramin_grctx->instance >> 4); - - return 0; -} - -void nv20_graph_destroy_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - - if (chan->ramin_grctx) - nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); - - INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0); -} - -int nv20_graph_load_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t inst; - - if (!chan->ramin_grctx) - return -EINVAL; - inst = chan->ramin_grctx->instance >> 4; - - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER, - NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD); - NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100); - - nouveau_wait_for_idle(dev); - return 0; -} - -int nv20_graph_save_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t inst; - - if (!chan->ramin_grctx) - return -EINVAL; - inst = chan->ramin_grctx->instance >> 4; - - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER, - NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE); - - nouveau_wait_for_idle(dev); - return 0; -} - -static void nv20_graph_rdi(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i, writecount = 32; - uint32_t rdi_index = 0x2c80000; - - if (dev_priv->chipset == 0x20) { - rdi_index = 0x3d0000; - writecount = 15; - } - - NV_WRITE(NV10_PGRAPH_RDI_INDEX, rdi_index); - for (i = 0; i < writecount; i++) - NV_WRITE(NV10_PGRAPH_RDI_DATA, 0); - - nouveau_wait_for_idle(dev); -} - -int nv20_graph_init(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = - (struct drm_nouveau_private *)dev->dev_private; - uint32_t tmp, vramsz; - int ret, i; - - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & - ~NV_PMC_ENABLE_PGRAPH); - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | - NV_PMC_ENABLE_PGRAPH); - - if (!dev_priv->ctx_table) { - /* Create Context Pointer Table */ - dev_priv->ctx_table_size = 32 * 4; - if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, - dev_priv->ctx_table_size, 16, - NVOBJ_FLAG_ZERO_ALLOC, - &dev_priv->ctx_table))) - return ret; - } - - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_TABLE, - dev_priv->ctx_table->instance >> 4); - - nv20_graph_rdi(dev); - - NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); - NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); - NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700); - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */ - NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000); - NV_WRITE(0x40009C , 0x00000040); - - if (dev_priv->chipset >= 0x25) { - NV_WRITE(0x400890, 0x00080000); - NV_WRITE(0x400610, 0x304B1FB6); - NV_WRITE(0x400B80, 0x18B82880); - NV_WRITE(0x400B84, 0x44000000); - NV_WRITE(0x400098, 0x40000080); - NV_WRITE(0x400B88, 0x000000ff); - } else { - NV_WRITE(0x400880, 0x00080000); /* 0x0008c7df */ - NV_WRITE(0x400094, 0x00000005); - NV_WRITE(0x400B80, 0x45CAA208); /* 0x45eae20e */ - NV_WRITE(0x400B84, 0x24000000); - NV_WRITE(0x400098, 0x00000040); - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00038); - NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030); - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E10038); - NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030); - } - - /* copy tile info from PFB */ - for (i = 0; i < NV10_PFB_TILE__SIZE; i++) { - NV_WRITE(0x00400904 + i*0x10, NV_READ(NV10_PFB_TLIMIT(i))); - /* which is NV40_PGRAPH_TLIMIT0(i) ?? */ - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0030+i*4); - NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(NV10_PFB_TLIMIT(i))); - NV_WRITE(0x00400908 + i*0x10, NV_READ(NV10_PFB_TSIZE(i))); - /* which is NV40_PGRAPH_TSIZE0(i) ?? */ - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0050+i*4); - NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(NV10_PFB_TSIZE(i))); - NV_WRITE(0x00400900 + i*0x10, NV_READ(NV10_PFB_TILE(i))); - /* which is NV40_PGRAPH_TILE0(i) ?? */ - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0010+i*4); - NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(NV10_PFB_TILE(i))); - } - for (i = 0; i < 8; i++) { - NV_WRITE(0x400980+i*4, NV_READ(0x100300+i*4)); - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0090+i*4); - NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(0x100300+i*4)); - } - NV_WRITE(0x4009a0, NV_READ(0x100324)); - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA000C); - NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(0x100324)); - - NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000100); - NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF); - NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001); - - tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; - NV_WRITE(NV10_PGRAPH_SURFACE, tmp); - tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100; - NV_WRITE(NV10_PGRAPH_SURFACE, tmp); - - /* begin RAM config */ - vramsz = drm_get_resource_len(dev, 0) - 1; - NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0)); - NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1)); - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0000); - NV_WRITE(NV10_PGRAPH_RDI_DATA , NV_READ(NV04_PFB_CFG0)); - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0004); - NV_WRITE(NV10_PGRAPH_RDI_DATA , NV_READ(NV04_PFB_CFG1)); - NV_WRITE(0x400820, 0); - NV_WRITE(0x400824, 0); - NV_WRITE(0x400864, vramsz-1); - NV_WRITE(0x400868, vramsz-1); - - /* interesting.. the below overwrites some of the tile setup above.. */ - NV_WRITE(0x400B20, 0x00000000); - NV_WRITE(0x400B04, 0xFFFFFFFF); - - NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0); - NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0); - NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); - NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); - - return 0; -} - -void nv20_graph_takedown(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - nouveau_gpuobj_ref_del(dev, &dev_priv->ctx_table); -} - -int nv30_graph_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; -// uint32_t vramsz, tmp; - int ret, i; - - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & - ~NV_PMC_ENABLE_PGRAPH); - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | - NV_PMC_ENABLE_PGRAPH); - - if (!dev_priv->ctx_table) { - /* Create Context Pointer Table */ - dev_priv->ctx_table_size = 32 * 4; - if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, - dev_priv->ctx_table_size, 16, - NVOBJ_FLAG_ZERO_ALLOC, - &dev_priv->ctx_table))) - return ret; - } - - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_TABLE, - dev_priv->ctx_table->instance >> 4); - - NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); - NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); - NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x401287c0); - NV_WRITE(0x400890, 0x01b463ff); - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xf2de0475); - NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000); - NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); - NV_WRITE(0x400B80, 0x1003d888); - NV_WRITE(0x400B84, 0x0c000000); - NV_WRITE(0x400098, 0x00000000); - NV_WRITE(0x40009C, 0x0005ad00); - NV_WRITE(0x400B88, 0x62ff00ff); // suspiciously like PGRAPH_DEBUG_2 - NV_WRITE(0x4000a0, 0x00000000); - NV_WRITE(0x4000a4, 0x00000008); - NV_WRITE(0x4008a8, 0xb784a400); - NV_WRITE(0x400ba0, 0x002f8685); - NV_WRITE(0x400ba4, 0x00231f3f); - NV_WRITE(0x4008a4, 0x40000020); - - if (dev_priv->chipset == 0x34) { - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0004); - NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00200201); - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0008); - NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000008); - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0000); - NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000032); - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00004); - NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000002); - } - - NV_WRITE(0x4000c0, 0x00000016); - - /* copy tile info from PFB */ - for (i = 0; i < NV10_PFB_TILE__SIZE; i++) { - NV_WRITE(0x00400904 + i*0x10, NV_READ(NV10_PFB_TLIMIT(i))); - /* which is NV40_PGRAPH_TLIMIT0(i) ?? */ - NV_WRITE(0x00400908 + i*0x10, NV_READ(NV10_PFB_TSIZE(i))); - /* which is NV40_PGRAPH_TSIZE0(i) ?? */ - NV_WRITE(0x00400900 + i*0x10, NV_READ(NV10_PFB_TILE(i))); - /* which is NV40_PGRAPH_TILE0(i) ?? */ - } - - NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000100); - NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF); - NV_WRITE(0x0040075c , 0x00000001); - NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001); - - /* begin RAM config */ -// vramsz = drm_get_resource_len(dev, 0) - 1; - NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0)); - NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1)); - if (dev_priv->chipset != 0x34) { - NV_WRITE(0x400750, 0x00EA0000); - NV_WRITE(0x400754, NV_READ(NV04_PFB_CFG0)); - NV_WRITE(0x400750, 0x00EA0004); - NV_WRITE(0x400754, NV_READ(NV04_PFB_CFG1)); - } - -#if 0 - NV_WRITE(0x400820, 0); - NV_WRITE(0x400824, 0); - NV_WRITE(0x400864, vramsz-1); - NV_WRITE(0x400868, vramsz-1); - - NV_WRITE(0x400B20, 0x00000000); - NV_WRITE(0x400B04, 0xFFFFFFFF); - - /* per-context state, doesn't belong here */ - tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; - NV_WRITE(NV10_PGRAPH_SURFACE, tmp); - tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100; - NV_WRITE(NV10_PGRAPH_SURFACE, tmp); - - NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0); - NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0); - NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); - NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); -#endif - - return 0; -} diff --git a/shared-core/nv40_fb.c b/shared-core/nv40_fb.c deleted file mode 100644 index ae784cb8..00000000 --- a/shared-core/nv40_fb.c +++ /dev/null @@ -1,62 +0,0 @@ -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" -#include "nouveau_drm.h" - -int -nv40_fb_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t fb_bar_size, tmp; - int num_tiles; - int i; - - /* This is strictly a NV4x register (don't know about NV5x). */ - /* The blob sets these to all kinds of values, and they mess up our setup. */ - /* I got value 0x52802 instead. For some cards the blob even sets it back to 0x1. */ - /* Note: the blob doesn't read this value, so i'm pretty sure this is safe for all cards. */ - /* Any idea what this is? */ - NV_WRITE(NV40_PFB_UNK_800, 0x1); - - switch (dev_priv->chipset) { - case 0x40: - case 0x45: - tmp = NV_READ(NV10_PFB_CLOSE_PAGE2); - NV_WRITE(NV10_PFB_CLOSE_PAGE2, tmp & ~(1<<15)); - num_tiles = NV10_PFB_TILE__SIZE; - break; - case 0x46: /* G72 */ - case 0x47: /* G70 */ - case 0x49: /* G71 */ - case 0x4b: /* G73 */ - case 0x4c: /* C51 (G7X version) */ - num_tiles = NV40_PFB_TILE__SIZE_1; - break; - default: - num_tiles = NV40_PFB_TILE__SIZE_0; - break; - } - - fb_bar_size = drm_get_resource_len(dev, 0) - 1; - switch (dev_priv->chipset) { - case 0x40: - for (i=0; iramfc->gpuobj, \ - NV40_RAMFC_##offset/4, (val)) -#define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \ - NV40_RAMFC_##offset/4) -#define NV40_RAMFC(c) (dev_priv->ramfc_offset + ((c)*NV40_RAMFC__SIZE)) -#define NV40_RAMFC__SIZE 128 - -int -nv40_fifo_create_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - int ret; - - if ((ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), ~0, - NV40_RAMFC__SIZE, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ZERO_FREE, - NULL, &chan->ramfc))) - return ret; - - /* Fill entries that are seen filled in dumps of nvidia driver just - * after channel's is put into DMA mode - */ - RAMFC_WR(DMA_PUT , chan->pushbuf_base); - RAMFC_WR(DMA_GET , chan->pushbuf_base); - RAMFC_WR(DMA_INSTANCE , chan->pushbuf->instance >> 4); - RAMFC_WR(DMA_FETCH , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | -#ifdef __BIG_ENDIAN - NV_PFIFO_CACHE1_BIG_ENDIAN | -#endif - 0x30000000 /* no idea.. */); - RAMFC_WR(DMA_SUBROUTINE, 0); - RAMFC_WR(GRCTX_INSTANCE, chan->ramin_grctx->instance >> 4); - RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF); - - /* enable the fifo dma operation */ - NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<id)); - return 0; -} - -void -nv40_fifo_destroy_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - - NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<id)); - - if (chan->ramfc) - nouveau_gpuobj_ref_del(dev, &chan->ramfc); -} - -int -nv40_fifo_load_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t tmp, tmp2; - - NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET)); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT , RAMFC_RD(DMA_PUT)); - NV_WRITE(NV10_PFIFO_CACHE1_REF_CNT , RAMFC_RD(REF_CNT)); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE , RAMFC_RD(DMA_INSTANCE)); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT , RAMFC_RD(DMA_DCOUNT)); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE , RAMFC_RD(DMA_STATE)); - - /* No idea what 0x2058 is.. */ - tmp = RAMFC_RD(DMA_FETCH); - tmp2 = NV_READ(0x2058) & 0xFFF; - tmp2 |= (tmp & 0x30000000); - NV_WRITE(0x2058, tmp2); - tmp &= ~0x30000000; - NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH , tmp); - - NV_WRITE(NV04_PFIFO_CACHE1_ENGINE , RAMFC_RD(ENGINE)); - NV_WRITE(NV04_PFIFO_CACHE1_PULL1 , RAMFC_RD(PULL1_ENGINE)); - NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE , RAMFC_RD(ACQUIRE_VALUE)); - NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, RAMFC_RD(ACQUIRE_TIMESTAMP)); - NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT , RAMFC_RD(ACQUIRE_TIMEOUT)); - NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE , RAMFC_RD(SEMAPHORE)); - NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE , RAMFC_RD(DMA_SUBROUTINE)); - NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE , RAMFC_RD(GRCTX_INSTANCE)); - NV_WRITE(0x32e4, RAMFC_RD(UNK_40)); - /* NVIDIA does this next line twice... */ - NV_WRITE(0x32e8, RAMFC_RD(UNK_44)); - NV_WRITE(0x2088, RAMFC_RD(UNK_4C)); - NV_WRITE(0x3300, RAMFC_RD(UNK_50)); - - /* not sure what part is PUT, and which is GET.. never seen a non-zero - * value appear in a mmio-trace yet.. - */ -#if 0 - tmp = NV_READ(UNK_84); - NV_WRITE(NV_PFIFO_CACHE1_GET, tmp ???); - NV_WRITE(NV_PFIFO_CACHE1_PUT, tmp ???); -#endif - - /* Don't clobber the TIMEOUT_ENABLED flag when restoring from RAMFC */ - tmp = NV_READ(NV04_PFIFO_DMA_TIMESLICE) & ~0x1FFFF; - tmp |= RAMFC_RD(DMA_TIMESLICE) & 0x1FFFF; - NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, tmp); - - /* Set channel active, and in DMA mode */ - NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, - NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id); - - /* Reset DMA_CTL_AT_INFO to INVALID */ - tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp); - - return 0; -} - -int -nv40_fifo_save_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t tmp; - - RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); - RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); - RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT)); - RAMFC_WR(DMA_INSTANCE , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE)); - RAMFC_WR(DMA_DCOUNT , NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT)); - RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE)); - - tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH); - tmp |= NV_READ(0x2058) & 0x30000000; - RAMFC_WR(DMA_FETCH , tmp); - - RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE)); - RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1)); - RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE)); - tmp = NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP); - RAMFC_WR(ACQUIRE_TIMESTAMP, tmp); - RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT)); - RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE)); - - /* NVIDIA read 0x3228 first, then write DMA_GET here.. maybe something - * more involved depending on the value of 0x3228? - */ - RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); - - RAMFC_WR(GRCTX_INSTANCE , NV_READ(NV40_PFIFO_GRCTX_INSTANCE)); - - /* No idea what the below is for exactly, ripped from a mmio-trace */ - RAMFC_WR(UNK_40 , NV_READ(NV40_PFIFO_UNK32E4)); - - /* NVIDIA do this next line twice.. bug? */ - RAMFC_WR(UNK_44 , NV_READ(0x32e8)); - RAMFC_WR(UNK_4C , NV_READ(0x2088)); - RAMFC_WR(UNK_50 , NV_READ(0x3300)); - -#if 0 /* no real idea which is PUT/GET in UNK_48.. */ - tmp = NV_READ(NV04_PFIFO_CACHE1_GET); - tmp |= (NV_READ(NV04_PFIFO_CACHE1_PUT) << 16); - RAMFC_WR(UNK_48 , tmp); -#endif - - return 0; -} - -int -nv40_fifo_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int ret; - - if ((ret = nouveau_fifo_init(dev))) - return ret; - - NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff); - return 0; -} diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c deleted file mode 100644 index 4c378a05..00000000 --- a/shared-core/nv40_graph.c +++ /dev/null @@ -1,2190 +0,0 @@ -/* - * Copyright (C) 2007 Ben Skeggs. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" - -/*TODO: deciper what each offset in the context represents. The below - * contexts are taken from dumps just after the 3D object is - * created. - */ -static void -nv40_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - /* Always has the "instance address" of itself at offset 0 */ - INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); - /* unknown */ - INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00030/4, 0x00000001); - INSTANCE_WR(ctx, 0x0011c/4, 0x20010001); - INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00); - INSTANCE_WR(ctx, 0x00128/4, 0x02008821); - INSTANCE_WR(ctx, 0x0016c/4, 0x00000040); - INSTANCE_WR(ctx, 0x00170/4, 0x00000040); - INSTANCE_WR(ctx, 0x00174/4, 0x00000040); - INSTANCE_WR(ctx, 0x0017c/4, 0x80000000); - INSTANCE_WR(ctx, 0x00180/4, 0x80000000); - INSTANCE_WR(ctx, 0x00184/4, 0x80000000); - INSTANCE_WR(ctx, 0x00188/4, 0x80000000); - INSTANCE_WR(ctx, 0x0018c/4, 0x80000000); - INSTANCE_WR(ctx, 0x0019c/4, 0x00000040); - INSTANCE_WR(ctx, 0x001a0/4, 0x80000000); - INSTANCE_WR(ctx, 0x001b0/4, 0x80000000); - INSTANCE_WR(ctx, 0x001c0/4, 0x80000000); - INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c); - INSTANCE_WR(ctx, 0x00340/4, 0x00040000); - INSTANCE_WR(ctx, 0x00350/4, 0x55555555); - INSTANCE_WR(ctx, 0x00354/4, 0x55555555); - INSTANCE_WR(ctx, 0x00358/4, 0x55555555); - INSTANCE_WR(ctx, 0x0035c/4, 0x55555555); - INSTANCE_WR(ctx, 0x00388/4, 0x00000008); - INSTANCE_WR(ctx, 0x0039c/4, 0x00000010); - INSTANCE_WR(ctx, 0x00480/4, 0x00000100); - INSTANCE_WR(ctx, 0x00494/4, 0x00000111); - INSTANCE_WR(ctx, 0x00498/4, 0x00080060); - INSTANCE_WR(ctx, 0x004b4/4, 0x00000080); - INSTANCE_WR(ctx, 0x004b8/4, 0xffff0000); - INSTANCE_WR(ctx, 0x004bc/4, 0x00000001); - INSTANCE_WR(ctx, 0x004d0/4, 0x46400000); - INSTANCE_WR(ctx, 0x004ec/4, 0xffff0000); - INSTANCE_WR(ctx, 0x004f8/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x004fc/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x00504/4, 0x00011100); - for (i=0x00520; i<=0x0055c; i+=4) - INSTANCE_WR(ctx, i/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x00568/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x00594/4, 0x30201000); - INSTANCE_WR(ctx, 0x00598/4, 0x70605040); - INSTANCE_WR(ctx, 0x0059c/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x005a0/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x005b4/4, 0x40100000); - INSTANCE_WR(ctx, 0x005cc/4, 0x00000004); - INSTANCE_WR(ctx, 0x005d8/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x0060c/4, 0x435185d6); - INSTANCE_WR(ctx, 0x00610/4, 0x2155b699); - INSTANCE_WR(ctx, 0x00614/4, 0xfedcba98); - INSTANCE_WR(ctx, 0x00618/4, 0x00000098); - INSTANCE_WR(ctx, 0x00628/4, 0xffffffff); - INSTANCE_WR(ctx, 0x0062c/4, 0x00ff7000); - INSTANCE_WR(ctx, 0x00630/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00640/4, 0x00ff0000); - INSTANCE_WR(ctx, 0x0067c/4, 0x00ffff00); - /* 0x680-0x6BC - NV30_TCL_PRIMITIVE_3D_TX_ADDRESS_UNIT(0-15) */ - /* 0x6C0-0x6FC - NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT(0-15) */ - for (i=0x006C0; i<=0x006fc; i+=4) - INSTANCE_WR(ctx, i/4, 0x00018488); - /* 0x700-0x73C - NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT(0-15) */ - for (i=0x00700; i<=0x0073c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00028202); - /* 0x740-0x77C - NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT(0-15) */ - /* 0x780-0x7BC - NV30_TCL_PRIMITIVE_3D_TX_SWIZZLE_UNIT(0-15) */ - for (i=0x00780; i<=0x007bc; i+=4) - INSTANCE_WR(ctx, i/4, 0x0000aae4); - /* 0x7C0-0x7FC - NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT(0-15) */ - for (i=0x007c0; i<=0x007fc; i+=4) - INSTANCE_WR(ctx, i/4, 0x01012000); - /* 0x800-0x83C - NV30_TCL_PRIMITIVE_3D_TX_XY_DIM_UNIT(0-15) */ - for (i=0x00800; i<=0x0083c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - /* 0x840-0x87C - NV30_TCL_PRIMITIVE_3D_TX_UNK07_UNIT(0-15) */ - /* 0x880-0x8BC - NV30_TCL_PRIMITIVE_3D_TX_DEPTH_UNIT(0-15) */ - for (i=0x00880; i<=0x008bc; i+=4) - INSTANCE_WR(ctx, i/4, 0x00100008); - /* unknown */ - for (i=0x00910; i<=0x0091c; i+=4) - INSTANCE_WR(ctx, i/4, 0x0001bc80); - for (i=0x00920; i<=0x0092c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000202); - for (i=0x00940; i<=0x0094c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000008); - for (i=0x00960; i<=0x0096c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - INSTANCE_WR(ctx, 0x00980/4, 0x00000002); - INSTANCE_WR(ctx, 0x009b4/4, 0x00000001); - INSTANCE_WR(ctx, 0x009c0/4, 0x3e020200); - INSTANCE_WR(ctx, 0x009c4/4, 0x00ffffff); - INSTANCE_WR(ctx, 0x009c8/4, 0x60103f00); - INSTANCE_WR(ctx, 0x009d4/4, 0x00020000); - INSTANCE_WR(ctx, 0x00a08/4, 0x00008100); - INSTANCE_WR(ctx, 0x00aac/4, 0x00000001); - INSTANCE_WR(ctx, 0x00af0/4, 0x00000001); - INSTANCE_WR(ctx, 0x00af8/4, 0x80800001); - INSTANCE_WR(ctx, 0x00bcc/4, 0x00000005); - INSTANCE_WR(ctx, 0x00bf8/4, 0x00005555); - INSTANCE_WR(ctx, 0x00bfc/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c00/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c04/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c08/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c0c/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c44/4, 0x00000001); - for (i=0x03008; i<=0x03080; i+=8) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x05288; i<=0x08570; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x08628; i<=0x08e18; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x0bd28; i<=0x0f010; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x0f0c8; i<=0x0f8b8; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x127c8; i<=0x15ab0; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x15b68; i<=0x16358; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x19268; i<=0x1c550; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x1c608; i<=0x1cdf8; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x1fd08; i<=0x22ff0; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x230a8; i<=0x23898; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x267a8; i<=0x29a90; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x29b48; i<=0x2a338; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); -} - -static void -nv41_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); - INSTANCE_WR(ctx, 0x00000024/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00000028/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00000030/4, 0x00000001); - INSTANCE_WR(ctx, 0x0000011c/4, 0x20010001); - INSTANCE_WR(ctx, 0x00000120/4, 0x0f73ef00); - INSTANCE_WR(ctx, 0x00000128/4, 0x02008821); - for (i = 0x00000178; i <= 0x00000180; i += 4) - INSTANCE_WR(ctx, i/4, 0x00000040); - INSTANCE_WR(ctx, 0x00000188/4, 0x00000040); - for (i = 0x00000194; i <= 0x000001b0; i += 4) - INSTANCE_WR(ctx, i/4, 0x80000000); - INSTANCE_WR(ctx, 0x000001d0/4, 0x0b0b0b0c); - INSTANCE_WR(ctx, 0x00000340/4, 0x00040000); - for (i = 0x00000350; i <= 0x0000035c; i += 4) - INSTANCE_WR(ctx, i/4, 0x55555555); - INSTANCE_WR(ctx, 0x00000388/4, 0x00000008); - INSTANCE_WR(ctx, 0x0000039c/4, 0x00001010); - INSTANCE_WR(ctx, 0x000003cc/4, 0x00000111); - INSTANCE_WR(ctx, 0x000003d0/4, 0x00080060); - INSTANCE_WR(ctx, 0x000003ec/4, 0x00000080); - INSTANCE_WR(ctx, 0x000003f0/4, 0xffff0000); - INSTANCE_WR(ctx, 0x000003f4/4, 0x00000001); - INSTANCE_WR(ctx, 0x00000408/4, 0x46400000); - INSTANCE_WR(ctx, 0x00000418/4, 0xffff0000); - INSTANCE_WR(ctx, 0x00000424/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x00000428/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x00000430/4, 0x00011100); - for (i = 0x0000044c; i <= 0x00000488; i += 4) - INSTANCE_WR(ctx, i/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x00000494/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x000004bc/4, 0x30201000); - INSTANCE_WR(ctx, 0x000004c0/4, 0x70605040); - INSTANCE_WR(ctx, 0x000004c4/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x000004c8/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x000004dc/4, 0x40100000); - INSTANCE_WR(ctx, 0x000004f8/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x0000052c/4, 0x435185d6); - INSTANCE_WR(ctx, 0x00000530/4, 0x2155b699); - INSTANCE_WR(ctx, 0x00000534/4, 0xfedcba98); - INSTANCE_WR(ctx, 0x00000538/4, 0x00000098); - INSTANCE_WR(ctx, 0x00000548/4, 0xffffffff); - INSTANCE_WR(ctx, 0x0000054c/4, 0x00ff7000); - INSTANCE_WR(ctx, 0x00000550/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00000560/4, 0x00ff0000); - INSTANCE_WR(ctx, 0x00000598/4, 0x00ffff00); - for (i = 0x000005dc; i <= 0x00000618; i += 4) - INSTANCE_WR(ctx, i/4, 0x00018488); - for (i = 0x0000061c; i <= 0x00000658; i += 4) - INSTANCE_WR(ctx, i/4, 0x00028202); - for (i = 0x0000069c; i <= 0x000006d8; i += 4) - INSTANCE_WR(ctx, i/4, 0x0000aae4); - for (i = 0x000006dc; i <= 0x00000718; i += 4) - INSTANCE_WR(ctx, i/4, 0x01012000); - for (i = 0x0000071c; i <= 0x00000758; i += 4) - INSTANCE_WR(ctx, i/4, 0x00080008); - for (i = 0x0000079c; i <= 0x000007d8; i += 4) - INSTANCE_WR(ctx, i/4, 0x00100008); - for (i = 0x0000082c; i <= 0x00000838; i += 4) - INSTANCE_WR(ctx, i/4, 0x0001bc80); - for (i = 0x0000083c; i <= 0x00000848; i += 4) - INSTANCE_WR(ctx, i/4, 0x00000202); - for (i = 0x0000085c; i <= 0x00000868; i += 4) - INSTANCE_WR(ctx, i/4, 0x00000008); - for (i = 0x0000087c; i <= 0x00000888; i += 4) - INSTANCE_WR(ctx, i/4, 0x00080008); - INSTANCE_WR(ctx, 0x0000089c/4, 0x00000002); - INSTANCE_WR(ctx, 0x000008d0/4, 0x00000021); - INSTANCE_WR(ctx, 0x000008d4/4, 0x030c30c3); - INSTANCE_WR(ctx, 0x000008e0/4, 0x3e020200); - INSTANCE_WR(ctx, 0x000008e4/4, 0x00ffffff); - INSTANCE_WR(ctx, 0x000008e8/4, 0x20103f00); - INSTANCE_WR(ctx, 0x000008f4/4, 0x00020000); - INSTANCE_WR(ctx, 0x0000092c/4, 0x00008100); - INSTANCE_WR(ctx, 0x000009b8/4, 0x00000001); - INSTANCE_WR(ctx, 0x000009fc/4, 0x00001001); - INSTANCE_WR(ctx, 0x00000a04/4, 0x00000003); - INSTANCE_WR(ctx, 0x00000a08/4, 0x00888001); - INSTANCE_WR(ctx, 0x00000aac/4, 0x00000005); - INSTANCE_WR(ctx, 0x00000ab8/4, 0x0000ffff); - for (i = 0x00000ad4; i <= 0x00000ae4; i += 4) - INSTANCE_WR(ctx, i/4, 0x00005555); - INSTANCE_WR(ctx, 0x00000ae8/4, 0x00000001); - INSTANCE_WR(ctx, 0x00000b20/4, 0x00000001); - for (i = 0x00002ee8; i <= 0x00002f60; i += 8) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i = 0x00005168; i <= 0x00007358; i += 24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i = 0x00007368; i <= 0x00007758; i += 16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i = 0x0000a068; i <= 0x0000c258; i += 24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i = 0x0000c268; i <= 0x0000c658; i += 16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i = 0x0000ef68; i <= 0x00011158; i += 24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i = 0x00011168; i <= 0x00011558; i += 16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i = 0x00013e68; i <= 0x00016058; i += 24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i = 0x00016068; i <= 0x00016458; i += 16) - INSTANCE_WR(ctx, i/4, 0x3f800000); -}; - -static void -nv43_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); - INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00030/4, 0x00000001); - INSTANCE_WR(ctx, 0x0011c/4, 0x20010001); - INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00); - INSTANCE_WR(ctx, 0x00128/4, 0x02008821); - INSTANCE_WR(ctx, 0x00178/4, 0x00000040); - INSTANCE_WR(ctx, 0x0017c/4, 0x00000040); - INSTANCE_WR(ctx, 0x00180/4, 0x00000040); - INSTANCE_WR(ctx, 0x00188/4, 0x00000040); - INSTANCE_WR(ctx, 0x00194/4, 0x80000000); - INSTANCE_WR(ctx, 0x00198/4, 0x80000000); - INSTANCE_WR(ctx, 0x0019c/4, 0x80000000); - INSTANCE_WR(ctx, 0x001a0/4, 0x80000000); - INSTANCE_WR(ctx, 0x001a4/4, 0x80000000); - INSTANCE_WR(ctx, 0x001a8/4, 0x80000000); - INSTANCE_WR(ctx, 0x001ac/4, 0x80000000); - INSTANCE_WR(ctx, 0x001b0/4, 0x80000000); - INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c); - INSTANCE_WR(ctx, 0x00340/4, 0x00040000); - INSTANCE_WR(ctx, 0x00350/4, 0x55555555); - INSTANCE_WR(ctx, 0x00354/4, 0x55555555); - INSTANCE_WR(ctx, 0x00358/4, 0x55555555); - INSTANCE_WR(ctx, 0x0035c/4, 0x55555555); - INSTANCE_WR(ctx, 0x00388/4, 0x00000008); - INSTANCE_WR(ctx, 0x0039c/4, 0x00001010); - INSTANCE_WR(ctx, 0x003cc/4, 0x00000111); - INSTANCE_WR(ctx, 0x003d0/4, 0x00080060); - INSTANCE_WR(ctx, 0x003ec/4, 0x00000080); - INSTANCE_WR(ctx, 0x003f0/4, 0xffff0000); - INSTANCE_WR(ctx, 0x003f4/4, 0x00000001); - INSTANCE_WR(ctx, 0x00408/4, 0x46400000); - INSTANCE_WR(ctx, 0x00418/4, 0xffff0000); - INSTANCE_WR(ctx, 0x00424/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x00428/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x00430/4, 0x00011100); - for (i=0x0044c; i<=0x00488; i+=4) - INSTANCE_WR(ctx, i/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x00494/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x004bc/4, 0x30201000); - INSTANCE_WR(ctx, 0x004c0/4, 0x70605040); - INSTANCE_WR(ctx, 0x004c4/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x004c8/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x004dc/4, 0x40100000); - INSTANCE_WR(ctx, 0x004f8/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x0052c/4, 0x435185d6); - INSTANCE_WR(ctx, 0x00530/4, 0x2155b699); - INSTANCE_WR(ctx, 0x00534/4, 0xfedcba98); - INSTANCE_WR(ctx, 0x00538/4, 0x00000098); - INSTANCE_WR(ctx, 0x00548/4, 0xffffffff); - INSTANCE_WR(ctx, 0x0054c/4, 0x00ff7000); - INSTANCE_WR(ctx, 0x00550/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00560/4, 0x00ff0000); - INSTANCE_WR(ctx, 0x00598/4, 0x00ffff00); - for (i=0x005dc; i<=0x00618; i+=4) - INSTANCE_WR(ctx, i/4, 0x00018488); - for (i=0x0061c; i<=0x00658; i+=4) - INSTANCE_WR(ctx, i/4, 0x00028202); - for (i=0x0069c; i<=0x006d8; i+=4) - INSTANCE_WR(ctx, i/4, 0x0000aae4); - for (i=0x006dc; i<=0x00718; i+=4) - INSTANCE_WR(ctx, i/4, 0x01012000); - for (i=0x0071c; i<=0x00758; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - for (i=0x0079c; i<=0x007d8; i+=4) - INSTANCE_WR(ctx, i/4, 0x00100008); - for (i=0x0082c; i<=0x00838; i+=4) - INSTANCE_WR(ctx, i/4, 0x0001bc80); - for (i=0x0083c; i<=0x00848; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000202); - for (i=0x0085c; i<=0x00868; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000008); - for (i=0x0087c; i<=0x00888; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - INSTANCE_WR(ctx, 0x0089c/4, 0x00000002); - INSTANCE_WR(ctx, 0x008d0/4, 0x00000021); - INSTANCE_WR(ctx, 0x008d4/4, 0x030c30c3); - INSTANCE_WR(ctx, 0x008e0/4, 0x3e020200); - INSTANCE_WR(ctx, 0x008e4/4, 0x00ffffff); - INSTANCE_WR(ctx, 0x008e8/4, 0x0c103f00); - INSTANCE_WR(ctx, 0x008f4/4, 0x00020000); - INSTANCE_WR(ctx, 0x0092c/4, 0x00008100); - INSTANCE_WR(ctx, 0x009b8/4, 0x00000001); - INSTANCE_WR(ctx, 0x009fc/4, 0x00001001); - INSTANCE_WR(ctx, 0x00a04/4, 0x00000003); - INSTANCE_WR(ctx, 0x00a08/4, 0x00888001); - INSTANCE_WR(ctx, 0x00a8c/4, 0x00000005); - INSTANCE_WR(ctx, 0x00a98/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00ab4/4, 0x00005555); - INSTANCE_WR(ctx, 0x00ab8/4, 0x00005555); - INSTANCE_WR(ctx, 0x00abc/4, 0x00005555); - INSTANCE_WR(ctx, 0x00ac0/4, 0x00000001); - INSTANCE_WR(ctx, 0x00af8/4, 0x00000001); - for (i=0x02ec0; i<=0x02f38; i+=8) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x04c80; i<=0x06e70; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x06e80; i<=0x07270; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x096c0; i<=0x0b8b0; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x0b8c0; i<=0x0bcb0; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x0e100; i<=0x102f0; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x10300; i<=0x106f0; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); -}; - -static void -nv46_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); - INSTANCE_WR(ctx, 0x00040/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00044/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x0004c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00138/4, 0x20010001); - INSTANCE_WR(ctx, 0x0013c/4, 0x0f73ef00); - INSTANCE_WR(ctx, 0x00144/4, 0x02008821); - INSTANCE_WR(ctx, 0x00174/4, 0x00000001); - INSTANCE_WR(ctx, 0x00178/4, 0x00000001); - INSTANCE_WR(ctx, 0x0017c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00180/4, 0x00000001); - INSTANCE_WR(ctx, 0x00184/4, 0x00000001); - INSTANCE_WR(ctx, 0x00188/4, 0x00000001); - INSTANCE_WR(ctx, 0x0018c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00190/4, 0x00000001); - INSTANCE_WR(ctx, 0x00194/4, 0x00000040); - INSTANCE_WR(ctx, 0x00198/4, 0x00000040); - INSTANCE_WR(ctx, 0x0019c/4, 0x00000040); - INSTANCE_WR(ctx, 0x001a4/4, 0x00000040); - INSTANCE_WR(ctx, 0x001ec/4, 0x0b0b0b0c); - INSTANCE_WR(ctx, 0x0035c/4, 0x00040000); - INSTANCE_WR(ctx, 0x0036c/4, 0x55555555); - INSTANCE_WR(ctx, 0x00370/4, 0x55555555); - INSTANCE_WR(ctx, 0x00374/4, 0x55555555); - INSTANCE_WR(ctx, 0x00378/4, 0x55555555); - INSTANCE_WR(ctx, 0x003a4/4, 0x00000008); - INSTANCE_WR(ctx, 0x003b8/4, 0x00003010); - INSTANCE_WR(ctx, 0x003dc/4, 0x00000111); - INSTANCE_WR(ctx, 0x003e0/4, 0x00000111); - INSTANCE_WR(ctx, 0x003e4/4, 0x00000111); - INSTANCE_WR(ctx, 0x003e8/4, 0x00000111); - INSTANCE_WR(ctx, 0x003ec/4, 0x00000111); - INSTANCE_WR(ctx, 0x003f0/4, 0x00000111); - INSTANCE_WR(ctx, 0x003f4/4, 0x00000111); - INSTANCE_WR(ctx, 0x003f8/4, 0x00000111); - INSTANCE_WR(ctx, 0x003fc/4, 0x00000111); - INSTANCE_WR(ctx, 0x00400/4, 0x00000111); - INSTANCE_WR(ctx, 0x00404/4, 0x00000111); - INSTANCE_WR(ctx, 0x00408/4, 0x00000111); - INSTANCE_WR(ctx, 0x0040c/4, 0x00000111); - INSTANCE_WR(ctx, 0x00410/4, 0x00000111); - INSTANCE_WR(ctx, 0x00414/4, 0x00000111); - INSTANCE_WR(ctx, 0x00418/4, 0x00000111); - INSTANCE_WR(ctx, 0x004b0/4, 0x00000111); - INSTANCE_WR(ctx, 0x004b4/4, 0x00080060); - INSTANCE_WR(ctx, 0x004d0/4, 0x00000080); - INSTANCE_WR(ctx, 0x004d4/4, 0xffff0000); - INSTANCE_WR(ctx, 0x004d8/4, 0x00000001); - INSTANCE_WR(ctx, 0x004ec/4, 0x46400000); - INSTANCE_WR(ctx, 0x004fc/4, 0xffff0000); - INSTANCE_WR(ctx, 0x00500/4, 0x88888888); - INSTANCE_WR(ctx, 0x00504/4, 0x88888888); - INSTANCE_WR(ctx, 0x00508/4, 0x88888888); - INSTANCE_WR(ctx, 0x0050c/4, 0x88888888); - INSTANCE_WR(ctx, 0x00510/4, 0x88888888); - INSTANCE_WR(ctx, 0x00514/4, 0x88888888); - INSTANCE_WR(ctx, 0x00518/4, 0x88888888); - INSTANCE_WR(ctx, 0x0051c/4, 0x88888888); - INSTANCE_WR(ctx, 0x00520/4, 0x88888888); - INSTANCE_WR(ctx, 0x00524/4, 0x88888888); - INSTANCE_WR(ctx, 0x00528/4, 0x88888888); - INSTANCE_WR(ctx, 0x0052c/4, 0x88888888); - INSTANCE_WR(ctx, 0x00530/4, 0x88888888); - INSTANCE_WR(ctx, 0x00534/4, 0x88888888); - INSTANCE_WR(ctx, 0x00538/4, 0x88888888); - INSTANCE_WR(ctx, 0x0053c/4, 0x88888888); - INSTANCE_WR(ctx, 0x00550/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x00554/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x0055c/4, 0x00011100); - for (i=0x00578; i<0x005b4; i+=4) - INSTANCE_WR(ctx, i/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005c0/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x005e8/4, 0x30201000); - INSTANCE_WR(ctx, 0x005ec/4, 0x70605040); - INSTANCE_WR(ctx, 0x005f0/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x005f4/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x00608/4, 0x40100000); - INSTANCE_WR(ctx, 0x00624/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00658/4, 0x435185d6); - INSTANCE_WR(ctx, 0x0065c/4, 0x2155b699); - INSTANCE_WR(ctx, 0x00660/4, 0xfedcba98); - INSTANCE_WR(ctx, 0x00664/4, 0x00000098); - INSTANCE_WR(ctx, 0x00674/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00678/4, 0x00ff7000); - INSTANCE_WR(ctx, 0x0067c/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x0068c/4, 0x00ff0000); - INSTANCE_WR(ctx, 0x006c8/4, 0x00ffff00); - for (i=0x0070c; i<=0x00748; i+=4) - INSTANCE_WR(ctx, i/4, 0x00018488); - for (i=0x0074c; i<=0x00788; i+=4) - INSTANCE_WR(ctx, i/4, 0x00028202); - for (i=0x007cc; i<=0x00808; i+=4) - INSTANCE_WR(ctx, i/4, 0x0000aae4); - for (i=0x0080c; i<=0x00848; i+=4) - INSTANCE_WR(ctx, i/4, 0x01012000); - for (i=0x0084c; i<=0x00888; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - for (i=0x008cc; i<=0x00908; i+=4) - INSTANCE_WR(ctx, i/4, 0x00100008); - for (i=0x0095c; i<=0x00968; i+=4) - INSTANCE_WR(ctx, i/4, 0x0001bc80); - for (i=0x0096c; i<=0x00978; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000202); - for (i=0x0098c; i<=0x00998; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000008); - for (i=0x009ac; i<=0x009b8; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - INSTANCE_WR(ctx, 0x009cc/4, 0x00000002); - INSTANCE_WR(ctx, 0x00a00/4, 0x00000421); - INSTANCE_WR(ctx, 0x00a04/4, 0x030c30c3); - INSTANCE_WR(ctx, 0x00a08/4, 0x00011001); - INSTANCE_WR(ctx, 0x00a14/4, 0x3e020200); - INSTANCE_WR(ctx, 0x00a18/4, 0x00ffffff); - INSTANCE_WR(ctx, 0x00a1c/4, 0x0c103f00); - INSTANCE_WR(ctx, 0x00a28/4, 0x00040000); - INSTANCE_WR(ctx, 0x00a60/4, 0x00008100); - INSTANCE_WR(ctx, 0x00aec/4, 0x00000001); - INSTANCE_WR(ctx, 0x00b30/4, 0x00001001); - INSTANCE_WR(ctx, 0x00b38/4, 0x00000003); - INSTANCE_WR(ctx, 0x00b3c/4, 0x00888001); - INSTANCE_WR(ctx, 0x00bc0/4, 0x00000005); - INSTANCE_WR(ctx, 0x00bcc/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00be8/4, 0x00005555); - INSTANCE_WR(ctx, 0x00bec/4, 0x00005555); - INSTANCE_WR(ctx, 0x00bf0/4, 0x00005555); - INSTANCE_WR(ctx, 0x00bf4/4, 0x00000001); - INSTANCE_WR(ctx, 0x00c2c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00c30/4, 0x08e00001); - INSTANCE_WR(ctx, 0x00c34/4, 0x000e3000); - for (i=0x017f8; i<=0x01870; i+=8) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x035b8; i<=0x057a8; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x057b8; i<=0x05ba8; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x07f38; i<=0x0a128; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x0a138; i<=0x0a528; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x0c8b8; i<=0x0eaa8; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x0eab8; i<=0x0eea8; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); -} - -/* This may only work on 7800 AGP cards, will include a warning */ -static void -nv47_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - INSTANCE_WR(ctx, 0x00000000/4, ctx->im_pramin->start); - INSTANCE_WR(ctx, 0x00000024/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00000028/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00000030/4, 0x00000001); - INSTANCE_WR(ctx, 0x0000011c/4, 0x20010001); - INSTANCE_WR(ctx, 0x00000120/4, 0x0f73ef00); - INSTANCE_WR(ctx, 0x00000128/4, 0x02008821); - INSTANCE_WR(ctx, 0x00000178/4, 0x00000040); - INSTANCE_WR(ctx, 0x0000017c/4, 0x00000040); - INSTANCE_WR(ctx, 0x00000180/4, 0x00000040); - INSTANCE_WR(ctx, 0x00000188/4, 0x00000040); - for (i=0x00000194; i<=0x000001b0; i+=4) - INSTANCE_WR(ctx, i/4, 0x80000000); - INSTANCE_WR(ctx, 0x000001d0/4, 0x0b0b0b0c); - INSTANCE_WR(ctx, 0x00000340/4, 0x00040000); - INSTANCE_WR(ctx, 0x00000350/4, 0x55555555); - INSTANCE_WR(ctx, 0x00000354/4, 0x55555555); - INSTANCE_WR(ctx, 0x00000358/4, 0x55555555); - INSTANCE_WR(ctx, 0x0000035c/4, 0x55555555); - INSTANCE_WR(ctx, 0x00000388/4, 0x00000008); - INSTANCE_WR(ctx, 0x0000039c/4, 0x00001010); - for (i=0x000003c0; i<=0x000003fc; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000111); - INSTANCE_WR(ctx, 0x00000454/4, 0x00000111); - INSTANCE_WR(ctx, 0x00000458/4, 0x00080060); - INSTANCE_WR(ctx, 0x00000474/4, 0x00000080); - INSTANCE_WR(ctx, 0x00000478/4, 0xffff0000); - INSTANCE_WR(ctx, 0x0000047c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00000490/4, 0x46400000); - INSTANCE_WR(ctx, 0x000004a0/4, 0xffff0000); - for (i=0x000004a4; i<=0x000004e0; i+=4) - INSTANCE_WR(ctx, i/4, 0x88888888); - INSTANCE_WR(ctx, 0x000004f4/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x000004f8/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x00000500/4, 0x00011100); - for (i=0x0000051c; i<=0x00000558; i+=4) - INSTANCE_WR(ctx, i/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x00000564/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x0000058c/4, 0x30201000); - INSTANCE_WR(ctx, 0x00000590/4, 0x70605040); - INSTANCE_WR(ctx, 0x00000594/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x00000598/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x000005ac/4, 0x40100000); - INSTANCE_WR(ctx, 0x000005c8/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x000005fc/4, 0x435185d6); - INSTANCE_WR(ctx, 0x00000600/4, 0x2155b699); - INSTANCE_WR(ctx, 0x00000604/4, 0xfedcba98); - INSTANCE_WR(ctx, 0x00000608/4, 0x00000098); - INSTANCE_WR(ctx, 0x00000618/4, 0xffffffff); - INSTANCE_WR(ctx, 0x0000061c/4, 0x00ff7000); - INSTANCE_WR(ctx, 0x00000620/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00000630/4, 0x00ff0000); - INSTANCE_WR(ctx, 0x0000066c/4, 0x00ffff00); - for (i=0x000006b0; i<=0x000006ec; i+=4) - INSTANCE_WR(ctx, i/4, 0x00018488); - for (i=0x000006f0; i<=0x0000072c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00028202); - for (i=0x00000770; i<=0x000007ac; i+=4) - INSTANCE_WR(ctx, i/4, 0x0000aae4); - for (i=0x000007b0; i<=0x000007ec; i+=4) - INSTANCE_WR(ctx, i/4, 0x01012000); - for (i=0x000007f0; i<=0x0000082c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - for (i=0x00000870; i<=0x000008ac; i+=4) - INSTANCE_WR(ctx, i/4, 0x00100008); - INSTANCE_WR(ctx, 0x00000900/4, 0x0001bc80); - INSTANCE_WR(ctx, 0x00000904/4, 0x0001bc80); - INSTANCE_WR(ctx, 0x00000908/4, 0x0001bc80); - INSTANCE_WR(ctx, 0x0000090c/4, 0x0001bc80); - INSTANCE_WR(ctx, 0x00000910/4, 0x00000202); - INSTANCE_WR(ctx, 0x00000914/4, 0x00000202); - INSTANCE_WR(ctx, 0x00000918/4, 0x00000202); - INSTANCE_WR(ctx, 0x0000091c/4, 0x00000202); - for (i=0x00000930; i<=0x0000095c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000008); - INSTANCE_WR(ctx, 0x00000970/4, 0x00000002); - INSTANCE_WR(ctx, 0x000009a4/4, 0x00000021); - INSTANCE_WR(ctx, 0x000009a8/4, 0x030c30c3); - INSTANCE_WR(ctx, 0x000009b4/4, 0x3e020200); - INSTANCE_WR(ctx, 0x000009b8/4, 0x00ffffff); - INSTANCE_WR(ctx, 0x000009bc/4, 0x40103f00); - INSTANCE_WR(ctx, 0x000009c8/4, 0x00040000); - INSTANCE_WR(ctx, 0x00000a00/4, 0x00008100); - INSTANCE_WR(ctx, 0x00000a8c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00000ad0/4, 0x00001001); - INSTANCE_WR(ctx, 0x00000adc/4, 0x00000003); - INSTANCE_WR(ctx, 0x00000ae0/4, 0x00888001); - for (i=0x00000b10; i<=0x00000b8c; i+=4) - INSTANCE_WR(ctx, i/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00000bb4/4, 0x00000005); - INSTANCE_WR(ctx, 0x00000bc0/4, 0x0000ffff); - for (i=0x00000bdc; i<=0x00000bf8; i+=4) - INSTANCE_WR(ctx, i/4, 0x00005555); - INSTANCE_WR(ctx, 0x00000bfc/4, 0x00000001); - INSTANCE_WR(ctx, 0x00000c34/4, 0x00000001); - INSTANCE_WR(ctx, 0x00000c38/4, 0x08e00001); - INSTANCE_WR(ctx, 0x00000c3c/4, 0x000e3000); - for (i=0x00003000; i<=0x00003078; i+=8) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x00004dc0; i<=0x00006fb0; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x00006fc0; i<=0x000073b0; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x00009800; i<=0x0000b9f0; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x0000ba00; i<=0x00010430; i+=24) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x00010440; i<=0x00010830; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x00012c80; i<=0x00014e70; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x00014e80; i<=0x00015270; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x000176c0; i<=0x000198b0; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x000198c0; i<=0x00019cb0; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x0001c100; i<=0x0001e2f0; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x0001e300; i<=0x0001e6f0; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); -} - -static void -nv49_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); - INSTANCE_WR(ctx, 0x00004/4, 0x0000c040); - INSTANCE_WR(ctx, 0x00008/4, 0x0000c040); - INSTANCE_WR(ctx, 0x0000c/4, 0x0000c040); - INSTANCE_WR(ctx, 0x00010/4, 0x0000c040); - INSTANCE_WR(ctx, 0x00014/4, 0x0000c040); - INSTANCE_WR(ctx, 0x00018/4, 0x0000c040); - INSTANCE_WR(ctx, 0x0001c/4, 0x0000c040); - INSTANCE_WR(ctx, 0x00020/4, 0x0000c040); - INSTANCE_WR(ctx, 0x000c4/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x000c8/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x000d0/4, 0x00000001); - INSTANCE_WR(ctx, 0x001bc/4, 0x20010001); - INSTANCE_WR(ctx, 0x001c0/4, 0x0f73ef00); - INSTANCE_WR(ctx, 0x001c8/4, 0x02008821); - INSTANCE_WR(ctx, 0x00218/4, 0x00000040); - INSTANCE_WR(ctx, 0x0021c/4, 0x00000040); - INSTANCE_WR(ctx, 0x00220/4, 0x00000040); - INSTANCE_WR(ctx, 0x00228/4, 0x00000040); - INSTANCE_WR(ctx, 0x00234/4, 0x80000000); - INSTANCE_WR(ctx, 0x00238/4, 0x80000000); - INSTANCE_WR(ctx, 0x0023c/4, 0x80000000); - INSTANCE_WR(ctx, 0x00240/4, 0x80000000); - INSTANCE_WR(ctx, 0x00244/4, 0x80000000); - INSTANCE_WR(ctx, 0x00248/4, 0x80000000); - INSTANCE_WR(ctx, 0x0024c/4, 0x80000000); - INSTANCE_WR(ctx, 0x00250/4, 0x80000000); - INSTANCE_WR(ctx, 0x00270/4, 0x0b0b0b0c); - INSTANCE_WR(ctx, 0x003e0/4, 0x00040000); - INSTANCE_WR(ctx, 0x003f0/4, 0x55555555); - INSTANCE_WR(ctx, 0x003f4/4, 0x55555555); - INSTANCE_WR(ctx, 0x003f8/4, 0x55555555); - INSTANCE_WR(ctx, 0x003fc/4, 0x55555555); - INSTANCE_WR(ctx, 0x00428/4, 0x00000008); - INSTANCE_WR(ctx, 0x0043c/4, 0x00001010); - INSTANCE_WR(ctx, 0x00460/4, 0x00000111); - INSTANCE_WR(ctx, 0x00464/4, 0x00000111); - INSTANCE_WR(ctx, 0x00468/4, 0x00000111); - INSTANCE_WR(ctx, 0x0046c/4, 0x00000111); - INSTANCE_WR(ctx, 0x00470/4, 0x00000111); - INSTANCE_WR(ctx, 0x00474/4, 0x00000111); - INSTANCE_WR(ctx, 0x00478/4, 0x00000111); - INSTANCE_WR(ctx, 0x0047c/4, 0x00000111); - INSTANCE_WR(ctx, 0x00480/4, 0x00000111); - INSTANCE_WR(ctx, 0x00484/4, 0x00000111); - INSTANCE_WR(ctx, 0x00488/4, 0x00000111); - INSTANCE_WR(ctx, 0x0048c/4, 0x00000111); - INSTANCE_WR(ctx, 0x00490/4, 0x00000111); - INSTANCE_WR(ctx, 0x00494/4, 0x00000111); - INSTANCE_WR(ctx, 0x00498/4, 0x00000111); - INSTANCE_WR(ctx, 0x0049c/4, 0x00000111); - INSTANCE_WR(ctx, 0x004f4/4, 0x00000111); - INSTANCE_WR(ctx, 0x004f8/4, 0x00080060); - INSTANCE_WR(ctx, 0x00514/4, 0x00000080); - INSTANCE_WR(ctx, 0x00518/4, 0xffff0000); - INSTANCE_WR(ctx, 0x0051c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00530/4, 0x46400000); - INSTANCE_WR(ctx, 0x00540/4, 0xffff0000); - INSTANCE_WR(ctx, 0x00544/4, 0x88888888); - INSTANCE_WR(ctx, 0x00548/4, 0x88888888); - INSTANCE_WR(ctx, 0x0054c/4, 0x88888888); - INSTANCE_WR(ctx, 0x00550/4, 0x88888888); - INSTANCE_WR(ctx, 0x00554/4, 0x88888888); - INSTANCE_WR(ctx, 0x00558/4, 0x88888888); - INSTANCE_WR(ctx, 0x0055c/4, 0x88888888); - INSTANCE_WR(ctx, 0x00560/4, 0x88888888); - INSTANCE_WR(ctx, 0x00564/4, 0x88888888); - INSTANCE_WR(ctx, 0x00568/4, 0x88888888); - INSTANCE_WR(ctx, 0x0056c/4, 0x88888888); - INSTANCE_WR(ctx, 0x00570/4, 0x88888888); - INSTANCE_WR(ctx, 0x00574/4, 0x88888888); - INSTANCE_WR(ctx, 0x00578/4, 0x88888888); - INSTANCE_WR(ctx, 0x0057c/4, 0x88888888); - INSTANCE_WR(ctx, 0x00580/4, 0x88888888); - INSTANCE_WR(ctx, 0x00594/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x00598/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x005a0/4, 0x00011100); - INSTANCE_WR(ctx, 0x005bc/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005c0/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005c4/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005c8/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005cc/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005d0/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005d4/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005d8/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005dc/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005e0/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005e4/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005e8/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005ec/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005f0/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005f4/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005f8/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x00604/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x0062c/4, 0x30201000); - INSTANCE_WR(ctx, 0x00630/4, 0x70605040); - INSTANCE_WR(ctx, 0x00634/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x00638/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x0064c/4, 0x40100000); - INSTANCE_WR(ctx, 0x00668/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x0069c/4, 0x435185d6); - INSTANCE_WR(ctx, 0x006a0/4, 0x2155b699); - INSTANCE_WR(ctx, 0x006a4/4, 0xfedcba98); - INSTANCE_WR(ctx, 0x006a8/4, 0x00000098); - INSTANCE_WR(ctx, 0x006b8/4, 0xffffffff); - INSTANCE_WR(ctx, 0x006bc/4, 0x00ff7000); - INSTANCE_WR(ctx, 0x006c0/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x006d0/4, 0x00ff0000); - INSTANCE_WR(ctx, 0x0070c/4, 0x00ffff00); - for (i=0x00750; i<=0x0078c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00018488); - for (i=0x00790; i<=0x007cc; i+=4) - INSTANCE_WR(ctx, i/4, 0x00028202); - for (i=0x00810; i<=0x0084c; i+=4) - INSTANCE_WR(ctx, i/4, 0x0000aae4); - for (i=0x00850; i<=0x0088c; i+=4) - INSTANCE_WR(ctx, i/4, 0x01012000); - for (i=0x00890; i<=0x008cc; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - for (i=0x00910; i<=0x0094c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00100008); - for (i=0x009a0; i<=0x009ac; i+=4) - INSTANCE_WR(ctx, i/4, 0x0001bc80); - for (i=0x009b0; i<=0x009bc; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000202); - for (i=0x009d0; i<=0x009dc; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000008); - for (i=0x009f0; i<=0x009fc; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - INSTANCE_WR(ctx, 0x00a10/4, 0x00000002); - INSTANCE_WR(ctx, 0x00a44/4, 0x00000421); - INSTANCE_WR(ctx, 0x00a48/4, 0x030c30c3); - INSTANCE_WR(ctx, 0x00a54/4, 0x3e020200); - INSTANCE_WR(ctx, 0x00a58/4, 0x00ffffff); - INSTANCE_WR(ctx, 0x00a5c/4, 0x20103f00); - INSTANCE_WR(ctx, 0x00a68/4, 0x00040000); - INSTANCE_WR(ctx, 0x00aa0/4, 0x00008100); - INSTANCE_WR(ctx, 0x00b2c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00b70/4, 0x00001001); - INSTANCE_WR(ctx, 0x00b7c/4, 0x00000003); - INSTANCE_WR(ctx, 0x00b80/4, 0x00888001); - INSTANCE_WR(ctx, 0x00bb0/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bb4/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bb8/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bbc/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bc0/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bc4/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bc8/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bcc/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bd0/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bd4/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bd8/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bdc/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00be0/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00be4/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00be8/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bec/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bf0/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bf4/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bf8/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bfc/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c00/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c04/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c08/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c0c/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c10/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c14/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c18/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c1c/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c20/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c24/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c28/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c2c/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c54/4, 0x00000005); - INSTANCE_WR(ctx, 0x00c60/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00c7c/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c80/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c84/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c88/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c8c/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c90/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c94/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c98/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c9c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00cd4/4, 0x00000001); - INSTANCE_WR(ctx, 0x00cd8/4, 0x08e00001); - INSTANCE_WR(ctx, 0x00cdc/4, 0x000e3000); - for(i=0x030a0; i<=0x03118; i+=8) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for(i=0x098a0; i<=0x0ba90; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for(i=0x0baa0; i<=0x0be90; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for(i=0x0e2e0; i<=0x0fff0; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for(i=0x10008; i<=0x104d0; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for(i=0x104e0; i<=0x108d0; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for(i=0x12d20; i<=0x14f10; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for(i=0x14f20; i<=0x15310; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for(i=0x17760; i<=0x19950; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for(i=0x19960; i<=0x19d50; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for(i=0x1c1a0; i<=0x1e390; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for(i=0x1e3a0; i<=0x1e790; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for(i=0x20be0; i<=0x22dd0; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for(i=0x22de0; i<=0x231d0; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); -} - -static void -nv4a_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); - INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00030/4, 0x00000001); - INSTANCE_WR(ctx, 0x0011c/4, 0x20010001); - INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00); - INSTANCE_WR(ctx, 0x00128/4, 0x02008821); - INSTANCE_WR(ctx, 0x00158/4, 0x00000001); - INSTANCE_WR(ctx, 0x0015c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00160/4, 0x00000001); - INSTANCE_WR(ctx, 0x00164/4, 0x00000001); - INSTANCE_WR(ctx, 0x00168/4, 0x00000001); - INSTANCE_WR(ctx, 0x0016c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00170/4, 0x00000001); - INSTANCE_WR(ctx, 0x00174/4, 0x00000001); - INSTANCE_WR(ctx, 0x00178/4, 0x00000040); - INSTANCE_WR(ctx, 0x0017c/4, 0x00000040); - INSTANCE_WR(ctx, 0x00180/4, 0x00000040); - INSTANCE_WR(ctx, 0x00188/4, 0x00000040); - INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c); - INSTANCE_WR(ctx, 0x00340/4, 0x00040000); - INSTANCE_WR(ctx, 0x00350/4, 0x55555555); - INSTANCE_WR(ctx, 0x00354/4, 0x55555555); - INSTANCE_WR(ctx, 0x00358/4, 0x55555555); - INSTANCE_WR(ctx, 0x0035c/4, 0x55555555); - INSTANCE_WR(ctx, 0x00388/4, 0x00000008); - INSTANCE_WR(ctx, 0x0039c/4, 0x00003010); - INSTANCE_WR(ctx, 0x003cc/4, 0x00000111); - INSTANCE_WR(ctx, 0x003d0/4, 0x00080060); - INSTANCE_WR(ctx, 0x003ec/4, 0x00000080); - INSTANCE_WR(ctx, 0x003f0/4, 0xffff0000); - INSTANCE_WR(ctx, 0x003f4/4, 0x00000001); - INSTANCE_WR(ctx, 0x00408/4, 0x46400000); - INSTANCE_WR(ctx, 0x00418/4, 0xffff0000); - INSTANCE_WR(ctx, 0x00424/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x00428/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x00430/4, 0x00011100); - for (i=0x0044c; i<=0x00488; i+=4) - INSTANCE_WR(ctx, i/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x00494/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x004bc/4, 0x30201000); - INSTANCE_WR(ctx, 0x004c0/4, 0x70605040); - INSTANCE_WR(ctx, 0x004c4/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x004c8/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x004dc/4, 0x40100000); - INSTANCE_WR(ctx, 0x004f8/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x0052c/4, 0x435185d6); - INSTANCE_WR(ctx, 0x00530/4, 0x2155b699); - INSTANCE_WR(ctx, 0x00534/4, 0xfedcba98); - INSTANCE_WR(ctx, 0x00538/4, 0x00000098); - INSTANCE_WR(ctx, 0x00548/4, 0xffffffff); - INSTANCE_WR(ctx, 0x0054c/4, 0x00ff7000); - INSTANCE_WR(ctx, 0x00550/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x0055c/4, 0x00ff0000); - INSTANCE_WR(ctx, 0x00594/4, 0x00ffff00); - for (i=0x005d8; i<=0x00614; i+=4) - INSTANCE_WR(ctx, i/4, 0x00018488); - for (i=0x00618; i<=0x00654; i+=4) - INSTANCE_WR(ctx, i/4, 0x00028202); - for (i=0x00698; i<=0x006d4; i+=4) - INSTANCE_WR(ctx, i/4, 0x0000aae4); - for (i=0x006d8; i<=0x00714; i+=4) - INSTANCE_WR(ctx, i/4, 0x01012000); - for (i=0x00718; i<=0x00754; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - for (i=0x00798; i<=0x007d4; i+=4) - INSTANCE_WR(ctx, i/4, 0x00100008); - for (i=0x00828; i<=0x00834; i+=4) - INSTANCE_WR(ctx, i/4, 0x0001bc80); - for (i=0x00838; i<=0x00844; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000202); - for (i=0x00858; i<=0x00864; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000008); - for (i=0x00878; i<=0x00884; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - INSTANCE_WR(ctx, 0x00898/4, 0x00000002); - INSTANCE_WR(ctx, 0x008cc/4, 0x00000021); - INSTANCE_WR(ctx, 0x008d0/4, 0x030c30c3); - INSTANCE_WR(ctx, 0x008d4/4, 0x00011001); - INSTANCE_WR(ctx, 0x008e0/4, 0x3e020200); - INSTANCE_WR(ctx, 0x008e4/4, 0x00ffffff); - INSTANCE_WR(ctx, 0x008e8/4, 0x0c103f00); - INSTANCE_WR(ctx, 0x008f4/4, 0x00040000); - INSTANCE_WR(ctx, 0x0092c/4, 0x00008100); - INSTANCE_WR(ctx, 0x009b8/4, 0x00000001); - INSTANCE_WR(ctx, 0x009fc/4, 0x00001001); - INSTANCE_WR(ctx, 0x00a04/4, 0x00000003); - INSTANCE_WR(ctx, 0x00a08/4, 0x00888001); - INSTANCE_WR(ctx, 0x00a8c/4, 0x00000005); - INSTANCE_WR(ctx, 0x00a98/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00ab4/4, 0x00005555); - INSTANCE_WR(ctx, 0x00ab8/4, 0x00005555); - INSTANCE_WR(ctx, 0x00abc/4, 0x00005555); - INSTANCE_WR(ctx, 0x00ac0/4, 0x00000001); - INSTANCE_WR(ctx, 0x00af8/4, 0x00000001); - for (i=0x016c0; i<=0x01738; i+=8) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x03840; i<=0x05670; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x05680; i<=0x05a70; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x07e00; i<=0x09ff0; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x0a000; i<=0x0a3f0; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x0c780; i<=0x0e970; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x0e980; i<=0x0ed70; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); -} - -static void -nv4b_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); - INSTANCE_WR(ctx, 0x00004/4, 0x0000c040); - INSTANCE_WR(ctx, 0x00008/4, 0x0000c040); - INSTANCE_WR(ctx, 0x0000c/4, 0x0000c040); - INSTANCE_WR(ctx, 0x00010/4, 0x0000c040); - INSTANCE_WR(ctx, 0x00014/4, 0x0000c040); - INSTANCE_WR(ctx, 0x00018/4, 0x0000c040); - INSTANCE_WR(ctx, 0x0001c/4, 0x0000c040); - INSTANCE_WR(ctx, 0x00020/4, 0x0000c040); - INSTANCE_WR(ctx, 0x000c4/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x000c8/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x000d0/4, 0x00000001); - INSTANCE_WR(ctx, 0x001bc/4, 0x20010001); - INSTANCE_WR(ctx, 0x001c0/4, 0x0f73ef00); - INSTANCE_WR(ctx, 0x001c8/4, 0x02008821); - INSTANCE_WR(ctx, 0x00218/4, 0x00000040); - INSTANCE_WR(ctx, 0x0021c/4, 0x00000040); - INSTANCE_WR(ctx, 0x00220/4, 0x00000040); - INSTANCE_WR(ctx, 0x00228/4, 0x00000040); - INSTANCE_WR(ctx, 0x00234/4, 0x80000000); - INSTANCE_WR(ctx, 0x00238/4, 0x80000000); - INSTANCE_WR(ctx, 0x0023c/4, 0x80000000); - INSTANCE_WR(ctx, 0x00240/4, 0x80000000); - INSTANCE_WR(ctx, 0x00244/4, 0x80000000); - INSTANCE_WR(ctx, 0x00248/4, 0x80000000); - INSTANCE_WR(ctx, 0x0024c/4, 0x80000000); - INSTANCE_WR(ctx, 0x00250/4, 0x80000000); - INSTANCE_WR(ctx, 0x00270/4, 0x0b0b0b0c); - INSTANCE_WR(ctx, 0x003e0/4, 0x00040000); - INSTANCE_WR(ctx, 0x003f0/4, 0x55555555); - INSTANCE_WR(ctx, 0x003f4/4, 0x55555555); - INSTANCE_WR(ctx, 0x003f8/4, 0x55555555); - INSTANCE_WR(ctx, 0x003fc/4, 0x55555555); - INSTANCE_WR(ctx, 0x00428/4, 0x00000008); - INSTANCE_WR(ctx, 0x0043c/4, 0x00001010); - INSTANCE_WR(ctx, 0x00460/4, 0x00000111); - INSTANCE_WR(ctx, 0x00464/4, 0x00000111); - INSTANCE_WR(ctx, 0x00468/4, 0x00000111); - INSTANCE_WR(ctx, 0x0046c/4, 0x00000111); - INSTANCE_WR(ctx, 0x00470/4, 0x00000111); - INSTANCE_WR(ctx, 0x00474/4, 0x00000111); - INSTANCE_WR(ctx, 0x00478/4, 0x00000111); - INSTANCE_WR(ctx, 0x0047c/4, 0x00000111); - INSTANCE_WR(ctx, 0x00480/4, 0x00000111); - INSTANCE_WR(ctx, 0x00484/4, 0x00000111); - INSTANCE_WR(ctx, 0x00488/4, 0x00000111); - INSTANCE_WR(ctx, 0x0048c/4, 0x00000111); - INSTANCE_WR(ctx, 0x00490/4, 0x00000111); - INSTANCE_WR(ctx, 0x00494/4, 0x00000111); - INSTANCE_WR(ctx, 0x00498/4, 0x00000111); - INSTANCE_WR(ctx, 0x0049c/4, 0x00000111); - INSTANCE_WR(ctx, 0x004f4/4, 0x00000111); - INSTANCE_WR(ctx, 0x004f8/4, 0x00080060); - INSTANCE_WR(ctx, 0x00514/4, 0x00000080); - INSTANCE_WR(ctx, 0x00518/4, 0xffff0000); - INSTANCE_WR(ctx, 0x0051c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00530/4, 0x46400000); - INSTANCE_WR(ctx, 0x00540/4, 0xffff0000); - INSTANCE_WR(ctx, 0x00544/4, 0x88888888); - INSTANCE_WR(ctx, 0x00548/4, 0x88888888); - INSTANCE_WR(ctx, 0x0054c/4, 0x88888888); - INSTANCE_WR(ctx, 0x00550/4, 0x88888888); - INSTANCE_WR(ctx, 0x00554/4, 0x88888888); - INSTANCE_WR(ctx, 0x00558/4, 0x88888888); - INSTANCE_WR(ctx, 0x0055c/4, 0x88888888); - INSTANCE_WR(ctx, 0x00560/4, 0x88888888); - INSTANCE_WR(ctx, 0x00564/4, 0x88888888); - INSTANCE_WR(ctx, 0x00568/4, 0x88888888); - INSTANCE_WR(ctx, 0x0056c/4, 0x88888888); - INSTANCE_WR(ctx, 0x00570/4, 0x88888888); - INSTANCE_WR(ctx, 0x00574/4, 0x88888888); - INSTANCE_WR(ctx, 0x00578/4, 0x88888888); - INSTANCE_WR(ctx, 0x0057c/4, 0x88888888); - INSTANCE_WR(ctx, 0x00580/4, 0x88888888); - INSTANCE_WR(ctx, 0x00594/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x00598/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x005a0/4, 0x00011100); - INSTANCE_WR(ctx, 0x005bc/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005c0/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005c4/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005c8/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005cc/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005d0/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005d4/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005d8/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005dc/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005e0/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005e4/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005e8/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005ec/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005f0/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005f4/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x005f8/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x00604/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x0062c/4, 0x30201000); - INSTANCE_WR(ctx, 0x00630/4, 0x70605040); - INSTANCE_WR(ctx, 0x00634/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x00638/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x0064c/4, 0x40100000); - INSTANCE_WR(ctx, 0x00668/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x0069c/4, 0x435185d6); - INSTANCE_WR(ctx, 0x006a0/4, 0x2155b699); - INSTANCE_WR(ctx, 0x006a4/4, 0xfedcba98); - INSTANCE_WR(ctx, 0x006a8/4, 0x00000098); - INSTANCE_WR(ctx, 0x006b8/4, 0xffffffff); - INSTANCE_WR(ctx, 0x006bc/4, 0x00ff7000); - INSTANCE_WR(ctx, 0x006c0/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x006d0/4, 0x00ff0000); - INSTANCE_WR(ctx, 0x0070c/4, 0x00ffff00); - for (i=0x00750; i<=0x0078c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00018488); - for (i=0x00790; i<=0x007cc; i+=4) - INSTANCE_WR(ctx, i/4, 0x00028202); - for (i=0x00810; i<=0x0084c; i+=4) - INSTANCE_WR(ctx, i/4, 0x0000aae4); - for (i=0x00850; i<=0x0088c; i+=4) - INSTANCE_WR(ctx, i/4, 0x01012000); - for (i=0x00890; i<=0x008cc; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - for (i=0x00910; i<=0x0094c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00100008); - for (i=0x009a0; i<=0x009ac; i+=4) - INSTANCE_WR(ctx, i/4, 0x0001bc80); - for (i=0x009b0; i<=0x009bc; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000202); - for (i=0x009d0; i<=0x009dc; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000008); - for (i=0x009f0; i<=0x009fc; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - INSTANCE_WR(ctx, 0x00a10/4, 0x00000002); - INSTANCE_WR(ctx, 0x00a44/4, 0x00000421); - INSTANCE_WR(ctx, 0x00a48/4, 0x030c30c3); - INSTANCE_WR(ctx, 0x00a54/4, 0x3e020200); - INSTANCE_WR(ctx, 0x00a58/4, 0x00ffffff); - INSTANCE_WR(ctx, 0x00a5c/4, 0x20103f00); - INSTANCE_WR(ctx, 0x00a68/4, 0x00040000); - INSTANCE_WR(ctx, 0x00aa0/4, 0x00008100); - INSTANCE_WR(ctx, 0x00b2c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00b70/4, 0x00001001); - INSTANCE_WR(ctx, 0x00b7c/4, 0x00000003); - INSTANCE_WR(ctx, 0x00b80/4, 0x00888001); - INSTANCE_WR(ctx, 0x00bb0/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bb4/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bb8/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bbc/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bc0/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bc4/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bc8/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bcc/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bd0/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bd4/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bd8/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bdc/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00be0/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00be4/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00be8/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bec/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bf0/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bf4/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bf8/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00bfc/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c00/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c04/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c08/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c0c/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c10/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c14/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c18/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c1c/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c20/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c24/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c28/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c2c/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00c54/4, 0x00000005); - INSTANCE_WR(ctx, 0x00c60/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00c7c/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c80/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c84/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c88/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c8c/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c90/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c94/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c98/4, 0x00005555); - INSTANCE_WR(ctx, 0x00c9c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00cd4/4, 0x00000001); - INSTANCE_WR(ctx, 0x00cd8/4, 0x08e00001); - INSTANCE_WR(ctx, 0x00cdc/4, 0x000e3000); - for(i=0x030a0; i<=0x03118; i+=8) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for(i=0x098a0; i<=0x0ba90; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for(i=0x0baa0; i<=0x0be90; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for(i=0x0e2e0; i<=0x0fff0; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for(i=0x10008; i<=0x104d0; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for(i=0x104e0; i<=0x108d0; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for(i=0x12d20; i<=0x14f10; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for(i=0x14f20; i<=0x15310; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for(i=0x17760; i<=0x19950; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for(i=0x19960; i<=0x19d50; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); -} - -static void -nv4c_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); - INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00030/4, 0x00000001); - INSTANCE_WR(ctx, 0x0011c/4, 0x20010001); - INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00); - INSTANCE_WR(ctx, 0x00128/4, 0x02008821); - INSTANCE_WR(ctx, 0x00158/4, 0x00000001); - INSTANCE_WR(ctx, 0x0015c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00160/4, 0x00000001); - INSTANCE_WR(ctx, 0x00164/4, 0x00000001); - INSTANCE_WR(ctx, 0x00168/4, 0x00000001); - INSTANCE_WR(ctx, 0x0016c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00170/4, 0x00000001); - INSTANCE_WR(ctx, 0x00174/4, 0x00000001); - INSTANCE_WR(ctx, 0x00178/4, 0x00000040); - INSTANCE_WR(ctx, 0x0017c/4, 0x00000040); - INSTANCE_WR(ctx, 0x00180/4, 0x00000040); - INSTANCE_WR(ctx, 0x00188/4, 0x00000040); - INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c); - INSTANCE_WR(ctx, 0x00340/4, 0x00040000); - INSTANCE_WR(ctx, 0x00350/4, 0x55555555); - INSTANCE_WR(ctx, 0x00354/4, 0x55555555); - INSTANCE_WR(ctx, 0x00358/4, 0x55555555); - INSTANCE_WR(ctx, 0x0035c/4, 0x55555555); - INSTANCE_WR(ctx, 0x00388/4, 0x00000008); - INSTANCE_WR(ctx, 0x0039c/4, 0x00001010); - INSTANCE_WR(ctx, 0x003d0/4, 0x00000111); - INSTANCE_WR(ctx, 0x003d4/4, 0x00080060); - INSTANCE_WR(ctx, 0x003f0/4, 0x00000080); - INSTANCE_WR(ctx, 0x003f4/4, 0xffff0000); - INSTANCE_WR(ctx, 0x003f8/4, 0x00000001); - INSTANCE_WR(ctx, 0x0040c/4, 0x46400000); - INSTANCE_WR(ctx, 0x0041c/4, 0xffff0000); - INSTANCE_WR(ctx, 0x00428/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x0042c/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x00434/4, 0x00011100); - for (i=0x00450; i<0x0048c; i+=4) - INSTANCE_WR(ctx, i/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x00498/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x004c0/4, 0x30201000); - INSTANCE_WR(ctx, 0x004c4/4, 0x70605040); - INSTANCE_WR(ctx, 0x004c8/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x004cc/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x004e0/4, 0x40100000); - INSTANCE_WR(ctx, 0x004fc/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00530/4, 0x435185d6); - INSTANCE_WR(ctx, 0x00534/4, 0x2155b699); - INSTANCE_WR(ctx, 0x00538/4, 0xfedcba98); - INSTANCE_WR(ctx, 0x0053c/4, 0x00000098); - INSTANCE_WR(ctx, 0x0054c/4, 0xffffffff); - INSTANCE_WR(ctx, 0x00550/4, 0x00ff7000); - INSTANCE_WR(ctx, 0x00554/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00564/4, 0x00ff0000); - INSTANCE_WR(ctx, 0x0059c/4, 0x00ffff00); - for (i=0x005e0; i<=0x0061c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00018488); - for (i=0x00620; i<=0x0065c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00028202); - for (i=0x006a0; i<=0x006dc; i+=4) - INSTANCE_WR(ctx, i/4, 0x0000aae4); - for (i=0x006e0; i<=0x0071c; i+=4) - INSTANCE_WR(ctx, i/4, 0x01012000); - for (i=0x00720; i<=0x0075c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - for (i=0x007a0; i<=0x007dc; i+=4) - INSTANCE_WR(ctx, i/4, 0x00100008); - for (i=0x00830; i<=0x0083c; i+=4) - INSTANCE_WR(ctx, i/4, 0x0001bc80); - for (i=0x00840; i<=0x0084c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000202); - for (i=0x00860; i<=0x0086c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000008); - for (i=0x00880; i<=0x0088c; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - INSTANCE_WR(ctx, 0x008a0/4, 0x00000002); - INSTANCE_WR(ctx, 0x008d4/4, 0x00000020); - INSTANCE_WR(ctx, 0x008d8/4, 0x030c30c3); - INSTANCE_WR(ctx, 0x008dc/4, 0x00011001); - INSTANCE_WR(ctx, 0x008e8/4, 0x3e020200); - INSTANCE_WR(ctx, 0x008ec/4, 0x00ffffff); - INSTANCE_WR(ctx, 0x008f0/4, 0x0c103f00); - INSTANCE_WR(ctx, 0x008fc/4, 0x00040000); - INSTANCE_WR(ctx, 0x00934/4, 0x00008100); - INSTANCE_WR(ctx, 0x009c0/4, 0x00000001); - INSTANCE_WR(ctx, 0x00a04/4, 0x00001001); - INSTANCE_WR(ctx, 0x00a0c/4, 0x00000003); - INSTANCE_WR(ctx, 0x00a10/4, 0x00888001); - INSTANCE_WR(ctx, 0x00a74/4, 0x00000005); - INSTANCE_WR(ctx, 0x00a80/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00a9c/4, 0x00005555); - INSTANCE_WR(ctx, 0x00aa0/4, 0x00000001); - INSTANCE_WR(ctx, 0x00ad8/4, 0x00000001); - for (i=0x016a0; i<0x01718; i+=8) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x03460; i<0x05650; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x05660; i<0x05a50; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); -} - -static void -nv4e_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); - INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00030/4, 0x00000001); - INSTANCE_WR(ctx, 0x0011c/4, 0x20010001); - INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00); - INSTANCE_WR(ctx, 0x00128/4, 0x02008821); - INSTANCE_WR(ctx, 0x00158/4, 0x00000001); - INSTANCE_WR(ctx, 0x0015c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00160/4, 0x00000001); - INSTANCE_WR(ctx, 0x00164/4, 0x00000001); - INSTANCE_WR(ctx, 0x00168/4, 0x00000001); - INSTANCE_WR(ctx, 0x0016c/4, 0x00000001); - INSTANCE_WR(ctx, 0x00170/4, 0x00000001); - INSTANCE_WR(ctx, 0x00174/4, 0x00000001); - INSTANCE_WR(ctx, 0x00178/4, 0x00000040); - INSTANCE_WR(ctx, 0x0017c/4, 0x00000040); - INSTANCE_WR(ctx, 0x00180/4, 0x00000040); - INSTANCE_WR(ctx, 0x00188/4, 0x00000040); - INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c); - INSTANCE_WR(ctx, 0x00340/4, 0x00040000); - INSTANCE_WR(ctx, 0x00350/4, 0x55555555); - INSTANCE_WR(ctx, 0x00354/4, 0x55555555); - INSTANCE_WR(ctx, 0x00358/4, 0x55555555); - INSTANCE_WR(ctx, 0x0035c/4, 0x55555555); - INSTANCE_WR(ctx, 0x00388/4, 0x00000008); - INSTANCE_WR(ctx, 0x0039c/4, 0x00001010); - INSTANCE_WR(ctx, 0x003cc/4, 0x00000111); - INSTANCE_WR(ctx, 0x003d0/4, 0x00080060); - INSTANCE_WR(ctx, 0x003ec/4, 0x00000080); - INSTANCE_WR(ctx, 0x003f0/4, 0xffff0000); - INSTANCE_WR(ctx, 0x003f4/4, 0x00000001); - INSTANCE_WR(ctx, 0x00408/4, 0x46400000); - INSTANCE_WR(ctx, 0x00418/4, 0xffff0000); - INSTANCE_WR(ctx, 0x00424/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x00428/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x00430/4, 0x00011100); - for (i=0x0044c; i<=0x00488; i+=4) - INSTANCE_WR(ctx, i/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x00494/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x004bc/4, 0x30201000); - INSTANCE_WR(ctx, 0x004c0/4, 0x70605040); - INSTANCE_WR(ctx, 0x004c4/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x004c8/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x004dc/4, 0x40100000); - INSTANCE_WR(ctx, 0x004f8/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x0052c/4, 0x435185d6); - INSTANCE_WR(ctx, 0x00530/4, 0x2155b699); - INSTANCE_WR(ctx, 0x00534/4, 0xfedcba98); - INSTANCE_WR(ctx, 0x00538/4, 0x00000098); - INSTANCE_WR(ctx, 0x00548/4, 0xffffffff); - INSTANCE_WR(ctx, 0x0054c/4, 0x00ff7000); - INSTANCE_WR(ctx, 0x00550/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x0055c/4, 0x00ff0000); - INSTANCE_WR(ctx, 0x00594/4, 0x00ffff00); - for (i=0x005d8; i<=0x00614; i+=4) - INSTANCE_WR(ctx, i/4, 0x00018488); - for (i=0x00618; i<=0x00654; i+=4) - INSTANCE_WR(ctx, i/4, 0x00028202); - for (i=0x00698; i<=0x006d4; i+=4) - INSTANCE_WR(ctx, i/4, 0x0000aae4); - for (i=0x006d8; i<=0x00714; i+=4) - INSTANCE_WR(ctx, i/4, 0x01012000); - for (i=0x00718; i<=0x00754; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - for (i=0x00798; i<=0x007d4; i+=4) - INSTANCE_WR(ctx, i/4, 0x00100008); - for (i=0x00828; i<=0x00834; i+=4) - INSTANCE_WR(ctx, i/4, 0x0001bc80); - for (i=0x00838; i<=0x00844; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000202); - for (i=0x00858; i<=0x00864; i+=4) - INSTANCE_WR(ctx, i/4, 0x00000008); - for (i=0x00878; i<=0x00884; i+=4) - INSTANCE_WR(ctx, i/4, 0x00080008); - INSTANCE_WR(ctx, 0x00898/4, 0x00000002); - INSTANCE_WR(ctx, 0x008cc/4, 0x00000020); - INSTANCE_WR(ctx, 0x008d0/4, 0x030c30c3); - INSTANCE_WR(ctx, 0x008d4/4, 0x00011001); - INSTANCE_WR(ctx, 0x008e0/4, 0x3e020200); - INSTANCE_WR(ctx, 0x008e4/4, 0x00ffffff); - INSTANCE_WR(ctx, 0x008e8/4, 0x0c103f00); - INSTANCE_WR(ctx, 0x008f4/4, 0x00040000); - INSTANCE_WR(ctx, 0x0092c/4, 0x00008100); - INSTANCE_WR(ctx, 0x009b8/4, 0x00000001); - INSTANCE_WR(ctx, 0x009fc/4, 0x00001001); - INSTANCE_WR(ctx, 0x00a04/4, 0x00000003); - INSTANCE_WR(ctx, 0x00a08/4, 0x00888001); - INSTANCE_WR(ctx, 0x00a6c/4, 0x00000005); - INSTANCE_WR(ctx, 0x00a78/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x00a94/4, 0x00005555); - INSTANCE_WR(ctx, 0x00a98/4, 0x00000001); - INSTANCE_WR(ctx, 0x00aa4/4, 0x00000001); - for (i=0x01668; i<=0x016e0; i+=8) - INSTANCE_WR(ctx, i/4, 0x3f800000); - for (i=0x03428; i<=0x05618; i+=24) - INSTANCE_WR(ctx, i/4, 0x00000001); - for (i=0x05628; i<=0x05a18; i+=16) - INSTANCE_WR(ctx, i/4, 0x3f800000); -} - -int -nv40_graph_create_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *); - int ret; - - /* These functions populate the graphics context with a whole heap - * of default state. All these functions are very similar, with - * a minimal amount of chipset-specific changes. However, as we're - * currently dependant on the context programs used by the NVIDIA - * binary driver these functions must match the layout expected by - * them. Hopefully at some point this will all change. - */ - switch (dev_priv->chipset) { - case 0x40: - ctx_init = nv40_graph_context_init; - break; - case 0x41: - case 0x42: - ctx_init = nv41_graph_context_init; - break; - case 0x43: - ctx_init = nv43_graph_context_init; - break; - case 0x46: - ctx_init = nv46_graph_context_init; - break; - case 0x47: - ctx_init = nv47_graph_context_init; - break; - case 0x49: - ctx_init = nv49_graph_context_init; - break; - case 0x44: - case 0x4a: - ctx_init = nv4a_graph_context_init; - break; - case 0x4b: - ctx_init = nv4b_graph_context_init; - break; - case 0x4c: - case 0x67: - ctx_init = nv4c_graph_context_init; - break; - case 0x4e: - ctx_init = nv4e_graph_context_init; - break; - default: - ctx_init = nv40_graph_context_init; - break; - } - - /* Allocate a 175KiB block of PRAMIN to store the context. This - * is massive overkill for a lot of chipsets, but it should be safe - * until we're able to implement this properly (will happen at more - * or less the same time we're able to write our own context programs. - */ - if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 175*1024, 16, - NVOBJ_FLAG_ZERO_ALLOC, - &chan->ramin_grctx))) - return ret; - - /* Initialise default context values */ - ctx_init(dev, chan->ramin_grctx->gpuobj); - - return 0; -} - -void -nv40_graph_destroy_context(struct nouveau_channel *chan) -{ - nouveau_gpuobj_ref_del(chan->dev, &chan->ramin_grctx); -} - -static int -nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t old_cp, tv = 1000, tmp; - int i; - - old_cp = NV_READ(NV20_PGRAPH_CHANNEL_CTX_POINTER); - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); - - tmp = NV_READ(NV40_PGRAPH_CTXCTL_0310); - tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE : - NV40_PGRAPH_CTXCTL_0310_XFER_LOAD; - NV_WRITE(NV40_PGRAPH_CTXCTL_0310, tmp); - - tmp = NV_READ(NV40_PGRAPH_CTXCTL_0304); - tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX; - NV_WRITE(NV40_PGRAPH_CTXCTL_0304, tmp); - - nouveau_wait_for_idle(dev); - - for (i = 0; i < tv; i++) { - if (NV_READ(NV40_PGRAPH_CTXCTL_030C) == 0) - break; - } - - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp); - - if (i == tv) { - uint32_t ucstat = NV_READ(NV40_PGRAPH_CTXCTL_UCODE_STAT); - DRM_ERROR("Failed: Instance=0x%08x Save=%d\n", inst, save); - DRM_ERROR("IP: 0x%02x, Opcode: 0x%08x\n", - ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT, - ucstat & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK); - DRM_ERROR("0x40030C = 0x%08x\n", - NV_READ(NV40_PGRAPH_CTXCTL_030C)); - return -EBUSY; - } - - return 0; -} - -/* Save current context (from PGRAPH) into the channel's context */ -int -nv40_graph_save_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - uint32_t inst; - - if (!chan->ramin_grctx) - return -EINVAL; - inst = chan->ramin_grctx->instance >> 4; - - return nv40_graph_transfer_context(dev, inst, 1); -} - -/* Restore the context for a specific channel into PGRAPH */ -int -nv40_graph_load_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t inst; - int ret; - - if (!chan->ramin_grctx) - return -EINVAL; - inst = chan->ramin_grctx->instance >> 4; - - ret = nv40_graph_transfer_context(dev, inst, 0); - if (ret) - return ret; - - /* 0x40032C, no idea of it's exact function. Could simply be a - * record of the currently active PGRAPH context. It's currently - * unknown as to what bit 24 does. The nv ddx has it set, so we will - * set it here too. - */ - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); - NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, - (inst & NV40_PGRAPH_CTXCTL_CUR_INST_MASK) | - NV40_PGRAPH_CTXCTL_CUR_LOADED); - /* 0x32E0 records the instance address of the active FIFO's PGRAPH - * context. If at any time this doesn't match 0x40032C, you will - * recieve PGRAPH_INTR_CONTEXT_SWITCH - */ - NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, inst); - return 0; -} - -/* These blocks of "magic numbers" are actually a microcode that the GPU uses - * to control how graphics contexts get saved and restored between PRAMIN - * and PGRAPH during a context switch. We're currently using values seen - * in mmio-traces of the binary driver. - */ -static uint32_t nv40_ctx_prog[] = { - 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, - 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00408f65, 0x00409406, - 0x0040a268, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080, - 0x004014e6, 0x007000a0, 0x00401a84, 0x00700082, 0x00600001, 0x00500061, - 0x00600002, 0x00401b68, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d, - 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4, - 0x001041c9, 0x0010c1dc, 0x00110205, 0x0011420a, 0x00114210, 0x00110216, - 0x0012421b, 0x00120270, 0x001242c0, 0x00200040, 0x00100280, 0x00128100, - 0x00128120, 0x00128143, 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, - 0x00110400, 0x00104d10, 0x00500060, 0x00403b87, 0x0060000d, 0x004076e6, - 0x002000f0, 0x0060000a, 0x00200045, 0x00100620, 0x00108668, 0x0011466b, - 0x00120682, 0x0011068b, 0x00168691, 0x0010c6ae, 0x001206b4, 0x0020002a, - 0x001006c4, 0x001246f0, 0x002000c0, 0x00100700, 0x0010c3d7, 0x001043e1, - 0x00500060, 0x00405600, 0x00405684, 0x00600003, 0x00500067, 0x00600008, - 0x00500060, 0x00700082, 0x0020026c, 0x0060000a, 0x00104800, 0x00104901, - 0x00120920, 0x00200035, 0x00100940, 0x00148a00, 0x00104a14, 0x00200038, - 0x00100b00, 0x00138d00, 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06, - 0x0020031a, 0x0060000a, 0x00300000, 0x00200680, 0x00406c00, 0x00200684, - 0x00800001, 0x00200b62, 0x0060000a, 0x0020a0b0, 0x0040728a, 0x00201b68, - 0x00800041, 0x00407684, 0x00203e60, 0x00800002, 0x00408700, 0x00600006, - 0x00700003, 0x004080e6, 0x00700080, 0x0020031a, 0x0060000a, 0x00200004, - 0x00800001, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a284, - 0x00700002, 0x00600004, 0x0040a268, 0x00700000, 0x00200000, 0x0060000a, - 0x00106002, 0x00700080, 0x00400a84, 0x00700002, 0x00400a68, 0x00500060, - 0x00600007, 0x00409388, 0x0060000f, 0x00000000, 0x00500060, 0x00200000, - 0x0060000a, 0x00700000, 0x00106001, 0x00700083, 0x00910880, 0x00901ffe, - 0x00940400, 0x00200020, 0x0060000b, 0x00500069, 0x0060000c, 0x00401b68, - 0x0040a406, 0x0040a505, 0x00600009, 0x00700005, 0x00700006, 0x0060000e, - ~0 -}; - -static uint32_t nv41_ctx_prog[] = { - 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, - 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00408f65, 0x00409306, - 0x0040a068, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042, - 0x00200001, 0x0060000a, 0x00700000, 0x001040c5, 0x00401826, 0x00401968, - 0x0060000d, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080, - 0x004020e6, 0x007000a0, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d, - 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4, - 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e, - 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143, - 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10, - 0x001046ec, 0x00500060, 0x00404087, 0x0060000d, 0x004079e6, 0x002000f1, - 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b, - 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6, - 0x00200020, 0x001006cc, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700, - 0x0010c3d7, 0x001043e1, 0x00500060, 0x00200233, 0x0060000a, 0x00104800, - 0x00108901, 0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00148a00, - 0x00108a14, 0x00200020, 0x00100b00, 0x00134b2c, 0x0010cd00, 0x0010cd04, - 0x00114d08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06, - 0x002002d2, 0x0060000a, 0x00300000, 0x00200680, 0x00407200, 0x00200684, - 0x00800001, 0x00200b1a, 0x0060000a, 0x00206380, 0x0040788a, 0x00201480, - 0x00800041, 0x00408900, 0x00600006, 0x004085e6, 0x00700080, 0x0020007a, - 0x0060000a, 0x00104280, 0x002002d2, 0x0060000a, 0x00200004, 0x00800001, - 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a068, 0x00700000, - 0x00200000, 0x0060000a, 0x00106002, 0x00700080, 0x00400a68, 0x00500060, - 0x00600007, 0x00409388, 0x0060000f, 0x00500060, 0x00200000, 0x0060000a, - 0x00700000, 0x00106001, 0x00910880, 0x00901ffe, 0x00940400, 0x00200020, - 0x0060000b, 0x00500069, 0x0060000c, 0x00402168, 0x0040a206, 0x0040a305, - 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0 -}; - -static uint32_t nv43_ctx_prog[] = { - 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, - 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409565, 0x00409a06, - 0x0040a868, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080, - 0x004014e6, 0x007000a0, 0x00401a84, 0x00700082, 0x00600001, 0x00500061, - 0x00600002, 0x00401b68, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d, - 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4, - 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e, - 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143, - 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10, - 0x001046ec, 0x00500060, 0x00403a87, 0x0060000d, 0x00407ce6, 0x002000f1, - 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b, - 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6, - 0x00200020, 0x001006cc, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700, - 0x0010c3d7, 0x001043e1, 0x00500060, 0x00405800, 0x00405884, 0x00600003, - 0x00500067, 0x00600008, 0x00500060, 0x00700082, 0x00200233, 0x0060000a, - 0x00104800, 0x00108901, 0x00124920, 0x0020001f, 0x00100940, 0x00140965, - 0x00148a00, 0x00108a14, 0x00160b00, 0x00134b2c, 0x0010cd00, 0x0010cd04, - 0x0010cd08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06, - 0x002002c8, 0x0060000a, 0x00300000, 0x00200680, 0x00407200, 0x00200684, - 0x00800001, 0x00200b10, 0x0060000a, 0x00203870, 0x0040788a, 0x00201350, - 0x00800041, 0x00407c84, 0x00201560, 0x00800002, 0x00408d00, 0x00600006, - 0x00700003, 0x004086e6, 0x00700080, 0x002002c8, 0x0060000a, 0x00200004, - 0x00800001, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a884, - 0x00700002, 0x00600004, 0x0040a868, 0x00700000, 0x00200000, 0x0060000a, - 0x00106002, 0x00700080, 0x00400a84, 0x00700002, 0x00400a68, 0x00500060, - 0x00600007, 0x00409988, 0x0060000f, 0x00000000, 0x00500060, 0x00200000, - 0x0060000a, 0x00700000, 0x00106001, 0x00700083, 0x00910880, 0x00901ffe, - 0x00940400, 0x00200020, 0x0060000b, 0x00500069, 0x0060000c, 0x00401b68, - 0x0040aa06, 0x0040ab05, 0x00600009, 0x00700005, 0x00700006, 0x0060000e, - ~0 -}; - -static uint32_t nv44_ctx_prog[] = { - 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, - 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409a65, 0x00409f06, - 0x0040ac68, 0x0040248f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042, - 0x001041c6, 0x00104040, 0x00200001, 0x0060000a, 0x00700000, 0x001040c5, - 0x00402320, 0x00402321, 0x00402322, 0x00402324, 0x00402326, 0x0040232b, - 0x001040c5, 0x00402328, 0x001040c5, 0x00402320, 0x00402468, 0x0060000d, - 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080, 0x00402be6, - 0x007000a0, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d, 0x00110158, - 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4, 0x001041c9, - 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e, 0x001242c0, - 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143, 0x0011415f, - 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10, 0x001046ec, - 0x00500060, 0x00404b87, 0x0060000d, 0x004084e6, 0x002000f1, 0x0060000a, - 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b, 0x00168691, - 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6, 0x001646cc, - 0x001186e6, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700, 0x0010c3d7, - 0x001043e1, 0x00500060, 0x00200232, 0x0060000a, 0x00104800, 0x00108901, - 0x00104910, 0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00148a00, - 0x00108a14, 0x00160b00, 0x00134b2c, 0x0010cd00, 0x0010cd04, 0x0010cd08, - 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06, 0x002002c8, - 0x0060000a, 0x00300000, 0x00200080, 0x00407d00, 0x00200084, 0x00800001, - 0x00200510, 0x0060000a, 0x002037e0, 0x0040838a, 0x00201320, 0x00800029, - 0x00409400, 0x00600006, 0x004090e6, 0x00700080, 0x0020007a, 0x0060000a, - 0x00104280, 0x002002c8, 0x0060000a, 0x00200004, 0x00800001, 0x00700000, - 0x00200000, 0x0060000a, 0x00106002, 0x0040ac68, 0x00700000, 0x00200000, - 0x0060000a, 0x00106002, 0x00700080, 0x00400a68, 0x00500060, 0x00600007, - 0x00409e88, 0x0060000f, 0x00000000, 0x00500060, 0x00200000, 0x0060000a, - 0x00700000, 0x00106001, 0x00910880, 0x00901ffe, 0x01940000, 0x00200020, - 0x0060000b, 0x00500069, 0x0060000c, 0x00402c68, 0x0040ae06, 0x0040af05, - 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0 -}; - -static uint32_t nv46_ctx_prog[] = { - 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, - 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00408f65, 0x00409306, - 0x0040a068, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042, - 0x00200001, 0x0060000a, 0x00700000, 0x001040c5, 0x00401826, 0x00401968, - 0x0060000d, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080, - 0x004020e6, 0x007000a0, 0x00500060, 0x00200008, 0x0060000a, 0x0011814d, - 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4, - 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e, - 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143, - 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10, - 0x00500060, 0x00403f87, 0x0060000d, 0x004079e6, 0x002000f7, 0x0060000a, - 0x00200045, 0x00100620, 0x00104668, 0x0017466d, 0x0011068b, 0x00168691, - 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6, 0x00200022, - 0x001006cc, 0x001246f0, 0x002000c0, 0x00100700, 0x0010c3d7, 0x001043e1, - 0x00500060, 0x0020027f, 0x0060000a, 0x00104800, 0x00108901, 0x00104910, - 0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00148a00, 0x00108a14, - 0x00160b00, 0x00134b2c, 0x0010cd00, 0x0010cd04, 0x0010cd08, 0x00104d80, - 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06, 0x00105406, 0x00105709, - 0x00200316, 0x0060000a, 0x00300000, 0x00200080, 0x00407200, 0x00200084, - 0x00800001, 0x0020055e, 0x0060000a, 0x002037e0, 0x0040788a, 0x00201320, - 0x00800029, 0x00408900, 0x00600006, 0x004085e6, 0x00700080, 0x00200081, - 0x0060000a, 0x00104280, 0x00200316, 0x0060000a, 0x00200004, 0x00800001, - 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a068, 0x00700000, - 0x00200000, 0x0060000a, 0x00106002, 0x00700080, 0x00400a68, 0x00500060, - 0x00600007, 0x00409388, 0x0060000f, 0x00500060, 0x00200000, 0x0060000a, - 0x00700000, 0x00106001, 0x00910880, 0x00901ffe, 0x01940000, 0x00200020, - 0x0060000b, 0x00500069, 0x0060000c, 0x00402168, 0x0040a206, 0x0040a305, - 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0 -}; - -static uint32_t nv47_ctx_prog[] = { - 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, - 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409265, 0x00409606, - 0x0040a368, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042, - 0x00200001, 0x0060000a, 0x00700000, 0x001040c5, 0x00401826, 0x00401968, - 0x0060000d, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080, - 0x004020e6, 0x007000a0, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d, - 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4, - 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e, - 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143, - 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d12, - 0x00500060, 0x00403f87, 0x0060000d, 0x00407ce6, 0x002000f0, 0x0060000a, - 0x00200020, 0x00100620, 0x00154650, 0x00104668, 0x0017466d, 0x0011068b, - 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6, - 0x00200022, 0x001006cc, 0x001246f0, 0x002000c0, 0x00100700, 0x0010c3d7, - 0x001043e1, 0x00500060, 0x00200268, 0x0060000a, 0x00104800, 0x00108901, - 0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00144a00, 0x00104a19, - 0x0010ca1c, 0x00110b00, 0x00200028, 0x00100b08, 0x00134c2e, 0x0010cd00, - 0x0010cd04, 0x00120d08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00, - 0x00104f06, 0x00105406, 0x00105709, 0x00200318, 0x0060000a, 0x00300000, - 0x00200680, 0x00407500, 0x00200684, 0x00800001, 0x00200b60, 0x0060000a, - 0x00209540, 0x00407b8a, 0x00201350, 0x00800041, 0x00408c00, 0x00600006, - 0x004088e6, 0x00700080, 0x0020007a, 0x0060000a, 0x00104280, 0x00200318, - 0x0060000a, 0x00200004, 0x00800001, 0x00700000, 0x00200000, 0x0060000a, - 0x00106002, 0x0040a368, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, - 0x00700080, 0x00400a68, 0x00500060, 0x00600007, 0x00409688, 0x0060000f, - 0x00500060, 0x00200000, 0x0060000a, 0x00700000, 0x00106001, 0x0091a880, - 0x00901ffe, 0x10940000, 0x00200020, 0x0060000b, 0x00500069, 0x0060000c, - 0x00402168, 0x0040a506, 0x0040a605, 0x00600009, 0x00700005, 0x00700006, - 0x0060000e, ~0 -}; - -//this is used for nv49 and nv4b -static uint32_t nv49_4b_ctx_prog[] ={ - 0x00400564, 0x00400505, 0x00408165, 0x00408206, 0x00409e68, 0x00200020, - 0x0060000a, 0x00700080, 0x00104042, 0x00200020, 0x0060000a, 0x00700000, - 0x001040c5, 0x00400f26, 0x00401068, 0x0060000d, 0x0070008f, 0x0070000e, - 0x00408d68, 0x004015e6, 0x007000a0, 0x00700080, 0x0040180f, 0x00700000, - 0x00200029, 0x0060000a, 0x0011814d, 0x00110158, 0x00105401, 0x0020003a, - 0x00100051, 0x001040c5, 0x0010c1c4, 0x001041c9, 0x0010c1dc, 0x00150210, - 0x0012c225, 0x00108238, 0x0010823e, 0x001242c0, 0x00200040, 0x00100280, - 0x00128100, 0x00128120, 0x00128143, 0x0011415f, 0x0010815c, 0x0010c140, - 0x00104029, 0x00110400, 0x00104d12, 0x00500060, 0x004071e6, 0x00200118, - 0x0060000a, 0x00200020, 0x00100620, 0x00154650, 0x00104668, 0x0017466d, - 0x0011068b, 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, - 0x001146c6, 0x00200022, 0x001006cc, 0x001246f0, 0x002000c0, 0x00100700, - 0x0010c3d7, 0x001043e1, 0x00500060, 0x00200290, 0x0060000a, 0x00104800, - 0x00108901, 0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00144a00, - 0x00104a19, 0x0010ca1c, 0x00110b00, 0x00200028, 0x00100b08, 0x00134c2e, - 0x0010cd00, 0x0010cd04, 0x00120d08, 0x00104d80, 0x00104e00, 0x0012d600, - 0x00105c00, 0x00104f06, 0x00105406, 0x00105709, 0x00200340, 0x0060000a, - 0x00300000, 0x00200680, 0x00406a0f, 0x00200684, 0x00800001, 0x00200b88, - 0x0060000a, 0x00209540, 0x0040708a, 0x00201350, 0x00800041, 0x00407c0f, - 0x00600006, 0x00407ce6, 0x00700080, 0x002000a2, 0x0060000a, 0x00104280, - 0x00200340, 0x0060000a, 0x00200004, 0x00800001, 0x0070008e, 0x00408d68, - 0x0040020f, 0x00600006, 0x00409e68, 0x00600007, 0x0070000f, 0x0070000e, - 0x00408d68, 0x0091a880, 0x00901ffe, 0x10940000, 0x00200020, 0x0060000b, - 0x00500069, 0x0060000c, 0x00401568, 0x00700000, 0x00200001, 0x0040910e, - 0x00200021, 0x0060000a, 0x00409b0d, 0x00104a40, 0x00104a50, 0x00104a60, - 0x00104a70, 0x00104a80, 0x00104a90, 0x00104aa0, 0x00104ab0, 0x00407e0e, - 0x0040130f, 0x00408568, 0x0040a006, 0x0040a105, 0x00600009, 0x00700005, - 0x00700006, 0x0060000e, ~0 -}; - - -static uint32_t nv4a_ctx_prog[] = { - 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, - 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409965, 0x00409e06, - 0x0040ac68, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080, - 0x004014e6, 0x007000a0, 0x00401a84, 0x00700082, 0x00600001, 0x00500061, - 0x00600002, 0x00401b68, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d, - 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4, - 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e, - 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143, - 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10, - 0x001046ec, 0x00500060, 0x00403a87, 0x0060000d, 0x00407de6, 0x002000f1, - 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b, - 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6, - 0x001646cc, 0x001186e6, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700, - 0x0010c3d7, 0x001043e1, 0x00500060, 0x00405800, 0x00405884, 0x00600003, - 0x00500067, 0x00600008, 0x00500060, 0x00700082, 0x00200232, 0x0060000a, - 0x00104800, 0x00108901, 0x00104910, 0x00124920, 0x0020001f, 0x00100940, - 0x00140965, 0x00148a00, 0x00108a14, 0x00160b00, 0x00134b2c, 0x0010cd00, - 0x0010cd04, 0x0010cd08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00, - 0x00104f06, 0x002002c8, 0x0060000a, 0x00300000, 0x00200080, 0x00407300, - 0x00200084, 0x00800001, 0x00200510, 0x0060000a, 0x002037e0, 0x0040798a, - 0x00201320, 0x00800029, 0x00407d84, 0x00201560, 0x00800002, 0x00409100, - 0x00600006, 0x00700003, 0x00408ae6, 0x00700080, 0x0020007a, 0x0060000a, - 0x00104280, 0x002002c8, 0x0060000a, 0x00200004, 0x00800001, 0x00700000, - 0x00200000, 0x0060000a, 0x00106002, 0x0040ac84, 0x00700002, 0x00600004, - 0x0040ac68, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x00700080, - 0x00400a84, 0x00700002, 0x00400a68, 0x00500060, 0x00600007, 0x00409d88, - 0x0060000f, 0x00000000, 0x00500060, 0x00200000, 0x0060000a, 0x00700000, - 0x00106001, 0x00700083, 0x00910880, 0x00901ffe, 0x01940000, 0x00200020, - 0x0060000b, 0x00500069, 0x0060000c, 0x00401b68, 0x0040ae06, 0x0040af05, - 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0 -}; - -static uint32_t nv4c_ctx_prog[] = { - 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, - 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409065, 0x00409406, - 0x0040a168, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042, - 0x00200001, 0x0060000a, 0x00700000, 0x001040c5, 0x00401826, 0x00401968, - 0x0060000d, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080, - 0x004020e6, 0x007000a0, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d, - 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4, - 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e, - 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143, - 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10, - 0x0010427e, 0x001046ec, 0x00500060, 0x00404187, 0x0060000d, 0x00407ae6, - 0x002000f2, 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, - 0x0011068b, 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, - 0x001146c6, 0x00200020, 0x001006cc, 0x001046ed, 0x001246f0, 0x002000c0, - 0x00100700, 0x0010c3d7, 0x001043e1, 0x00500060, 0x00200234, 0x0060000a, - 0x00104800, 0x00108901, 0x00104910, 0x00124920, 0x0020001f, 0x00100940, - 0x00140965, 0x00148a00, 0x00108a14, 0x00140b00, 0x00134b2c, 0x0010cd00, - 0x0010cd04, 0x00104d08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00, - 0x00104f06, 0x002002c0, 0x0060000a, 0x00300000, 0x00200080, 0x00407300, - 0x00200084, 0x00800001, 0x00200508, 0x0060000a, 0x00201320, 0x0040798a, - 0xfffffaf8, 0x00800029, 0x00408a00, 0x00600006, 0x004086e6, 0x00700080, - 0x0020007a, 0x0060000a, 0x00104280, 0x002002c0, 0x0060000a, 0x00200004, - 0x00800001, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a168, - 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x00700080, 0x00400a68, - 0x00500060, 0x00600007, 0x00409488, 0x0060000f, 0x00500060, 0x00200000, - 0x0060000a, 0x00700000, 0x00106001, 0x00910880, 0x00901ffe, 0x01940000, - 0x00200020, 0x0060000b, 0x00500069, 0x0060000c, 0x00402168, 0x0040a306, - 0x0040a405, 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0 -}; - -static uint32_t nv4e_ctx_prog[] = { - 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, - 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409565, 0x00409a06, - 0x0040a868, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080, - 0x004014e6, 0x007000a0, 0x00401a84, 0x00700082, 0x00600001, 0x00500061, - 0x00600002, 0x00401b68, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d, - 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4, - 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e, - 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143, - 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10, - 0x001046ec, 0x00500060, 0x00403a87, 0x0060000d, 0x00407ce6, 0x002000f1, - 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b, - 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6, - 0x001646cc, 0x001186e6, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700, - 0x0010c3d7, 0x001043e1, 0x00500060, 0x00405800, 0x00405884, 0x00600003, - 0x00500067, 0x00600008, 0x00500060, 0x00700082, 0x00200232, 0x0060000a, - 0x00104800, 0x00108901, 0x00104910, 0x00124920, 0x0020001f, 0x00100940, - 0x00140965, 0x00148a00, 0x00108a14, 0x00140b00, 0x00134b2c, 0x0010cd00, - 0x0010cd04, 0x00104d08, 0x00104d80, 0x00104e00, 0x00105c00, 0x00104f06, - 0x002002b2, 0x0060000a, 0x00300000, 0x00200080, 0x00407200, 0x00200084, - 0x00800001, 0x002004fa, 0x0060000a, 0x00201320, 0x0040788a, 0xfffffb06, - 0x00800029, 0x00407c84, 0x00200b20, 0x00800002, 0x00408d00, 0x00600006, - 0x00700003, 0x004086e6, 0x00700080, 0x002002b2, 0x0060000a, 0x00200004, - 0x00800001, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a884, - 0x00700002, 0x00600004, 0x0040a868, 0x00700000, 0x00200000, 0x0060000a, - 0x00106002, 0x00700080, 0x00400a84, 0x00700002, 0x00400a68, 0x00500060, - 0x00600007, 0x00409988, 0x0060000f, 0x00000000, 0x00500060, 0x00200000, - 0x0060000a, 0x00700000, 0x00106001, 0x00700083, 0x00910880, 0x00901ffe, - 0x01940000, 0x00200020, 0x0060000b, 0x00500069, 0x0060000c, 0x00401b68, - 0x0040aa06, 0x0040ab05, 0x00600009, 0x00700005, 0x00700006, 0x0060000e, - ~0 -}; - -/* - * G70 0x47 - * G71 0x49 - * NV45 0x48 - * G72[M] 0x46 - * G73 0x4b - * C51_G7X 0x4c - * C51 0x4e - */ -int -nv40_graph_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = - (struct drm_nouveau_private *)dev->dev_private; - uint32_t *ctx_prog; - uint32_t vramsz, tmp; - int i, j; - - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & - ~NV_PMC_ENABLE_PGRAPH); - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | - NV_PMC_ENABLE_PGRAPH); - - switch (dev_priv->chipset) { - case 0x40: ctx_prog = nv40_ctx_prog; break; - case 0x41: - case 0x42: ctx_prog = nv41_ctx_prog; break; - case 0x43: ctx_prog = nv43_ctx_prog; break; - case 0x44: ctx_prog = nv44_ctx_prog; break; - case 0x46: ctx_prog = nv46_ctx_prog; break; - case 0x47: ctx_prog = nv47_ctx_prog; break; - case 0x49: ctx_prog = nv49_4b_ctx_prog; break; - case 0x4a: ctx_prog = nv4a_ctx_prog; break; - case 0x4b: ctx_prog = nv49_4b_ctx_prog; break; - case 0x4c: - case 0x67: ctx_prog = nv4c_ctx_prog; break; - case 0x4e: ctx_prog = nv4e_ctx_prog; break; - default: - DRM_ERROR("Context program for 0x%02x unavailable\n", - dev_priv->chipset); - return -EINVAL; - } - - /* Load the context program onto the card */ - DRM_DEBUG("Loading context program\n"); - - i = 0; - NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0); - while (ctx_prog[i] != ~0) { - NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, ctx_prog[i]); - i++; - } - - /* No context present currently */ - NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, 0x00000000); - - NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); - NV_WRITE(NV40_PGRAPH_INTR_EN, 0xFFFFFFFF); - - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); - NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x401287c0); - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xe0de8055); - NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000); - NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f); - - NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100); - NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF); - NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001); - - j = NV_READ(0x1540) & 0xff; - if (j) { - for (i=0; !(j&1); j>>=1, i++); - NV_WRITE(0x405000, i); - } - - if (dev_priv->chipset == 0x40) { - NV_WRITE(0x4009b0, 0x83280fff); - NV_WRITE(0x4009b4, 0x000000a0); - } else { - NV_WRITE(0x400820, 0x83280eff); - NV_WRITE(0x400824, 0x000000a0); - } - - switch (dev_priv->chipset) { - case 0x40: - case 0x45: - NV_WRITE(0x4009b8, 0x0078e366); - NV_WRITE(0x4009bc, 0x0000014c); - break; - case 0x41: - case 0x42: /* pciid also 0x00Cx */ -// case 0x0120: //XXX (pciid) - NV_WRITE(0x400828, 0x007596ff); - NV_WRITE(0x40082c, 0x00000108); - break; - case 0x43: - NV_WRITE(0x400828, 0x0072cb77); - NV_WRITE(0x40082c, 0x00000108); - break; - case 0x44: - case 0x46: /* G72 */ - case 0x4a: - case 0x4c: /* G7x-based C51 */ - case 0x4e: - NV_WRITE(0x400860, 0); - NV_WRITE(0x400864, 0); - break; - case 0x47: /* G70 */ - case 0x49: /* G71 */ - case 0x4b: /* G73 */ - NV_WRITE(0x400828, 0x07830610); - NV_WRITE(0x40082c, 0x0000016A); - break; - default: - break; - } - - NV_WRITE(0x400b38, 0x2ffff800); - NV_WRITE(0x400b3c, 0x00006000); - - /* copy tile info from PFB */ - switch (dev_priv->chipset) { - case 0x40: /* vanilla NV40 */ - for (i=0; ichipset) { - case 0x40: - NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0)); - NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1)); - NV_WRITE(0x4069A4, NV_READ(NV04_PFB_CFG0)); - NV_WRITE(0x4069A8, NV_READ(NV04_PFB_CFG1)); - NV_WRITE(0x400820, 0); - NV_WRITE(0x400824, 0); - NV_WRITE(0x400864, vramsz); - NV_WRITE(0x400868, vramsz); - break; - default: - switch (dev_priv->chipset) { - case 0x46: - case 0x47: - case 0x49: - case 0x4b: - NV_WRITE(0x400DF0, NV_READ(NV04_PFB_CFG0)); - NV_WRITE(0x400DF4, NV_READ(NV04_PFB_CFG1)); - break; - default: - NV_WRITE(0x4009F0, NV_READ(NV04_PFB_CFG0)); - NV_WRITE(0x4009F4, NV_READ(NV04_PFB_CFG1)); - break; - } - NV_WRITE(0x4069F0, NV_READ(NV04_PFB_CFG0)); - NV_WRITE(0x4069F4, NV_READ(NV04_PFB_CFG1)); - NV_WRITE(0x400840, 0); - NV_WRITE(0x400844, 0); - NV_WRITE(0x4008A0, vramsz); - NV_WRITE(0x4008A4, vramsz); - break; - } - - /* per-context state, doesn't belong here */ - NV_WRITE(0x400B20, 0x00000000); - NV_WRITE(0x400B04, 0xFFFFFFFF); - - tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; - NV_WRITE(NV10_PGRAPH_SURFACE, tmp); - tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100; - NV_WRITE(NV10_PGRAPH_SURFACE, tmp); - - NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0); - NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0); - NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); - NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); - - return 0; -} - -void nv40_graph_takedown(struct drm_device *dev) -{ -} diff --git a/shared-core/nv40_mc.c b/shared-core/nv40_mc.c deleted file mode 100644 index cca8bf58..00000000 --- a/shared-core/nv40_mc.c +++ /dev/null @@ -1,38 +0,0 @@ -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" -#include "nouveau_drm.h" - -int -nv40_mc_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t tmp; - - /* Power up everything, resetting each individual unit will - * be done later if needed. - */ - NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF); - - switch (dev_priv->chipset) { - case 0x44: - case 0x46: /* G72 */ - case 0x4e: - case 0x4c: /* C51_G7X */ - tmp = NV_READ(NV10_PFB_CSTATUS); - NV_WRITE(NV40_PMC_1700, tmp); - NV_WRITE(NV40_PMC_1704, 0); - NV_WRITE(NV40_PMC_1708, 0); - NV_WRITE(NV40_PMC_170C, tmp); - break; - default: - break; - } - - return 0; -} - -void -nv40_mc_takedown(struct drm_device *dev) -{ -} diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c deleted file mode 100644 index c6dd0c3d..00000000 --- a/shared-core/nv50_fifo.c +++ /dev/null @@ -1,343 +0,0 @@ -/* - * Copyright (C) 2007 Ben Skeggs. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" - -struct nv50_fifo_priv { - struct nouveau_gpuobj_ref *thingo[2]; - int cur_thingo; -}; - -#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50) - -static void -nv50_fifo_init_thingo(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; - struct nouveau_gpuobj_ref *cur; - int i, nr; - - DRM_DEBUG("\n"); - - cur = priv->thingo[priv->cur_thingo]; - priv->cur_thingo = !priv->cur_thingo; - - /* We never schedule channel 0 or 127 */ - for (i = 1, nr = 0; i < 127; i++) { - if (dev_priv->fifos[i]) { - INSTANCE_WR(cur->gpuobj, nr++, i); - } - } - NV_WRITE(0x32f4, cur->instance >> 12); - NV_WRITE(0x32ec, nr); - NV_WRITE(0x2500, 0x101); -} - -static int -nv50_fifo_channel_enable(struct drm_device *dev, int channel, int nt) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_channel *chan = dev_priv->fifos[channel]; - uint32_t inst; - - DRM_DEBUG("ch%d\n", channel); - - if (!chan->ramfc) - return -EINVAL; - - if (IS_G80) inst = chan->ramfc->instance >> 12; - else inst = chan->ramfc->instance >> 8; - NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), - inst | NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); - - if (!nt) nv50_fifo_init_thingo(dev); - return 0; -} - -static void -nv50_fifo_channel_disable(struct drm_device *dev, int channel, int nt) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t inst; - - DRM_DEBUG("ch%d, nt=%d\n", channel, nt); - - if (IS_G80) inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80; - else inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84; - NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), inst); - - if (!nt) nv50_fifo_init_thingo(dev); -} - -static void -nv50_fifo_init_reset(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t pmc_e = NV_PMC_ENABLE_PFIFO; - - DRM_DEBUG("\n"); - - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~pmc_e); - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | pmc_e); -} - -static void -nv50_fifo_init_intr(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - DRM_DEBUG("\n"); - - NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF); - NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF); -} - -static void -nv50_fifo_init_context_table(struct drm_device *dev) -{ - int i; - - DRM_DEBUG("\n"); - - for (i = 0; i < NV50_PFIFO_CTX_TABLE__SIZE; i++) - nv50_fifo_channel_disable(dev, i, 1); - nv50_fifo_init_thingo(dev); -} - -static void -nv50_fifo_init_regs__nv(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - DRM_DEBUG("\n"); - - NV_WRITE(0x250c, 0x6f3cfc34); -} - -static void -nv50_fifo_init_regs(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - DRM_DEBUG("\n"); - - NV_WRITE(0x2500, 0); - NV_WRITE(0x3250, 0); - NV_WRITE(0x3220, 0); - NV_WRITE(0x3204, 0); - NV_WRITE(0x3210, 0); - NV_WRITE(0x3270, 0); - - /* Enable dummy channels setup by nv50_instmem.c */ - nv50_fifo_channel_enable(dev, 0, 1); - nv50_fifo_channel_enable(dev, 127, 1); -} - -int -nv50_fifo_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nv50_fifo_priv *priv; - int ret; - - DRM_DEBUG("\n"); - - priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER); - if (!priv) - return -ENOMEM; - dev_priv->Engine.fifo.priv = priv; - - nv50_fifo_init_reset(dev); - nv50_fifo_init_intr(dev); - - ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 128*4, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC, &priv->thingo[0]); - if (ret) { - DRM_ERROR("error creating thingo0: %d\n", ret); - return ret; - } - - ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 128*4, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC, &priv->thingo[1]); - if (ret) { - DRM_ERROR("error creating thingo1: %d\n", ret); - return ret; - } - - nv50_fifo_init_context_table(dev); - nv50_fifo_init_regs__nv(dev); - nv50_fifo_init_regs(dev); - - return 0; -} - -void -nv50_fifo_takedown(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; - - DRM_DEBUG("\n"); - - if (!priv) - return; - - nouveau_gpuobj_ref_del(dev, &priv->thingo[0]); - nouveau_gpuobj_ref_del(dev, &priv->thingo[1]); - - dev_priv->Engine.fifo.priv = NULL; - drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER); -} - -int -nv50_fifo_channel_id(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) & - NV50_PFIFO_CACHE1_PUSH1_CHID_MASK); -} - -int -nv50_fifo_create_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_gpuobj *ramfc = NULL; - int ret; - - DRM_DEBUG("ch%d\n", chan->id); - - if (IS_G80) { - uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start; - uint32_t vram_offset = chan->ramin->gpuobj->im_backing->start; - ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, vram_offset, - 0x100, NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ZERO_FREE, &ramfc, - &chan->ramfc); - if (ret) - return ret; - } else { - ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 0x100, 256, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ZERO_FREE, - &chan->ramfc); - if (ret) - return ret; - ramfc = chan->ramfc->gpuobj; - } - - INSTANCE_WR(ramfc, 0x48/4, chan->pushbuf->instance >> 4); - INSTANCE_WR(ramfc, 0x80/4, (0xc << 24) | (chan->ramht->instance >> 4)); - INSTANCE_WR(ramfc, 0x3c/4, 0x000f0078); /* fetch? */ - INSTANCE_WR(ramfc, 0x44/4, 0x2101ffff); - INSTANCE_WR(ramfc, 0x60/4, 0x7fffffff); - INSTANCE_WR(ramfc, 0x10/4, 0x00000000); - INSTANCE_WR(ramfc, 0x08/4, 0x00000000); - INSTANCE_WR(ramfc, 0x40/4, 0x00000000); - INSTANCE_WR(ramfc, 0x50/4, 0x2039b2e0); - INSTANCE_WR(ramfc, 0x54/4, 0x000f0000); - INSTANCE_WR(ramfc, 0x7c/4, 0x30000001); - INSTANCE_WR(ramfc, 0x78/4, 0x00000000); - INSTANCE_WR(ramfc, 0x4c/4, chan->pushbuf_mem->size - 1); - - if (!IS_G80) { - INSTANCE_WR(chan->ramin->gpuobj, 0, chan->id); - INSTANCE_WR(chan->ramin->gpuobj, 1, chan->ramfc->instance >> 8); - - INSTANCE_WR(ramfc, 0x88/4, 0x3d520); /* some vram addy >> 10 */ - INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12); - } - - ret = nv50_fifo_channel_enable(dev, chan->id, 0); - if (ret) { - DRM_ERROR("error enabling ch%d: %d\n", chan->id, ret); - nouveau_gpuobj_ref_del(dev, &chan->ramfc); - return ret; - } - - return 0; -} - -void -nv50_fifo_destroy_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - - DRM_DEBUG("ch%d\n", chan->id); - - nv50_fifo_channel_disable(dev, chan->id, 0); - - /* Dummy channel, also used on ch 127 */ - if (chan->id == 0) - nv50_fifo_channel_disable(dev, 127, 0); - - if ((NV_READ(NV03_PFIFO_CACHE1_PUSH1) & 0xffff) == chan->id) - NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 127); - - nouveau_gpuobj_ref_del(dev, &chan->ramfc); -} - -int -nv50_fifo_load_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_gpuobj *ramfc = chan->ramfc->gpuobj; - - DRM_DEBUG("ch%d\n", chan->id); - - /*XXX: incomplete, only touches the regs that NV does */ - - NV_WRITE(0x3244, 0); - NV_WRITE(0x3240, 0); - - NV_WRITE(0x3224, INSTANCE_RD(ramfc, 0x3c/4)); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, INSTANCE_RD(ramfc, 0x48/4)); - NV_WRITE(0x3234, INSTANCE_RD(ramfc, 0x4c/4)); - NV_WRITE(0x3254, 1); - NV_WRITE(NV03_PFIFO_RAMHT, INSTANCE_RD(ramfc, 0x80/4)); - - if (!IS_G80) { - NV_WRITE(0x340c, INSTANCE_RD(ramfc, 0x88/4)); - NV_WRITE(0x3410, INSTANCE_RD(ramfc, 0x98/4)); - } - - NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16)); - return 0; -} - -int -nv50_fifo_save_context(struct nouveau_channel *chan) -{ - DRM_DEBUG("ch%d\n", chan->id); - DRM_ERROR("stub!\n"); - return 0; -} diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c deleted file mode 100644 index 43f35e06..00000000 --- a/shared-core/nv50_graph.c +++ /dev/null @@ -1,338 +0,0 @@ -/* - * Copyright (C) 2007 Ben Skeggs. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" -#include "nv50_grctx.h" - -#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50) - -static void -nv50_graph_init_reset(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21); - - DRM_DEBUG("\n"); - - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~pmc_e); - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | pmc_e); -} - -static void -nv50_graph_init_intr(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - DRM_DEBUG("\n"); - NV_WRITE(NV03_PGRAPH_INTR, 0xffffffff); - NV_WRITE(0x400138, 0xffffffff); - NV_WRITE(NV40_PGRAPH_INTR_EN, 0xffffffff); -} - -static void -nv50_graph_init_regs__nv(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - DRM_DEBUG("\n"); - - NV_WRITE(0x400804, 0xc0000000); - NV_WRITE(0x406800, 0xc0000000); - NV_WRITE(0x400c04, 0xc0000000); - NV_WRITE(0x401804, 0xc0000000); - NV_WRITE(0x405018, 0xc0000000); - NV_WRITE(0x402000, 0xc0000000); - - NV_WRITE(0x400108, 0xffffffff); - - NV_WRITE(0x400824, 0x00004000); - NV_WRITE(0x400500, 0x00010001); -} - -static void -nv50_graph_init_regs(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - DRM_DEBUG("\n"); - - NV_WRITE(NV04_PGRAPH_DEBUG_3, (1<<2) /* HW_CONTEXT_SWITCH_ENABLED */); - NV_WRITE(0x402ca8, 0x800); -} - -static int -nv50_graph_init_ctxctl(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t *voodoo = NULL; - - DRM_DEBUG("\n"); - - switch (dev_priv->chipset) { - case 0x50: - voodoo = nv50_ctxprog; - break; - case 0x84: - voodoo = nv84_ctxprog; - break; - case 0x86: - voodoo = nv86_ctxprog; - break; - case 0x92: - voodoo = nv92_ctxprog; - break; - case 0x94: - case 0x96: - voodoo = nv94_ctxprog; - break; - case 0x98: - voodoo = nv98_ctxprog; - break; - case 0xa0: - voodoo = nva0_ctxprog; - break; - case 0xaa: - voodoo = nvaa_ctxprog; - break; - default: - DRM_ERROR("no ctxprog for chipset NV%02x\n", dev_priv->chipset); - return -EINVAL; - } - - NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0); - while (*voodoo != ~0) { - NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, *voodoo); - voodoo++; - } - - NV_WRITE(0x400320, 4); - NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, 0); - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, 0); - - return 0; -} - -int -nv50_graph_init(struct drm_device *dev) -{ - int ret; - - DRM_DEBUG("\n"); - - nv50_graph_init_reset(dev); - nv50_graph_init_intr(dev); - nv50_graph_init_regs__nv(dev); - nv50_graph_init_regs(dev); - - ret = nv50_graph_init_ctxctl(dev); - if (ret) - return ret; - - return 0; -} - -void -nv50_graph_takedown(struct drm_device *dev) -{ - DRM_DEBUG("\n"); -} - -int -nv50_graph_create_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_gpuobj *ramin = chan->ramin->gpuobj; - struct nouveau_gpuobj *ctx; - struct nouveau_engine *engine = &dev_priv->Engine; - uint32_t *ctxvals = NULL; - int grctx_size = 0x70000, hdr; - int ret; - - DRM_DEBUG("ch%d\n", chan->id); - - ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, grctx_size, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx); - if (ret) - return ret; - ctx = chan->ramin_grctx->gpuobj; - - hdr = IS_G80 ? 0x200 : 0x20; - INSTANCE_WR(ramin, (hdr + 0x00)/4, 0x00190002); - INSTANCE_WR(ramin, (hdr + 0x04)/4, chan->ramin_grctx->instance + - grctx_size - 1); - INSTANCE_WR(ramin, (hdr + 0x08)/4, chan->ramin_grctx->instance); - INSTANCE_WR(ramin, (hdr + 0x0c)/4, 0); - INSTANCE_WR(ramin, (hdr + 0x10)/4, 0); - INSTANCE_WR(ramin, (hdr + 0x14)/4, 0x00010000); - - switch (dev_priv->chipset) { - case 0x50: - ctxvals = nv50_ctxvals; - break; - case 0x84: - ctxvals = nv84_ctxvals; - break; - case 0x86: - ctxvals = nv86_ctxvals; - break; - case 0x92: - ctxvals = nv92_ctxvals; - break; - case 0x94: - ctxvals = nv94_ctxvals; - break; - case 0x96: - ctxvals = nv96_ctxvals; - break; - case 0x98: - ctxvals = nv98_ctxvals; - break; - case 0xa0: - ctxvals = nva0_ctxvals; - break; - case 0xaa: - ctxvals = nvaa_ctxvals; - break; - default: - break; - } - - if (ctxvals) { - int pos = 0; - - while (*ctxvals) { - int cnt = *ctxvals++; - - while (cnt--) - INSTANCE_WR(ctx, pos++, *ctxvals); - ctxvals++; - } - } else { - /* This is complete crack, it accidently used to make at - * least some G8x cards work partially somehow, though there's - * no good reason why - and it stopped working as the rest - * of the code got off the drugs.. - */ - ret = engine->graph.load_context(chan); - if (ret) { - DRM_ERROR("Error hacking up context: %d\n", ret); - return ret; - } - } - - INSTANCE_WR(ctx, 0x00000/4, chan->ramin->instance >> 12); - if ((dev_priv->chipset & 0xf0) == 0xa0) - INSTANCE_WR(ctx, 0x00004/4, 0x00000002); - else - INSTANCE_WR(ctx, 0x0011c/4, 0x00000002); - - return 0; -} - -void -nv50_graph_destroy_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i, hdr; - - DRM_DEBUG("ch%d\n", chan->id); - - hdr = IS_G80 ? 0x200 : 0x20; - for (i=hdr; iramin->gpuobj, i/4, 0); - - nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); -} - -static int -nv50_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t old_cp, tv = 20000; - int i; - - DRM_DEBUG("inst=0x%08x, save=%d\n", inst, save); - - old_cp = NV_READ(NV20_PGRAPH_CHANNEL_CTX_POINTER); - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); - NV_WRITE(0x400824, NV_READ(0x400824) | - (save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE : - NV40_PGRAPH_CTXCTL_0310_XFER_LOAD)); - NV_WRITE(NV40_PGRAPH_CTXCTL_0304, NV40_PGRAPH_CTXCTL_0304_XFER_CTX); - - for (i = 0; i < tv; i++) { - if (NV_READ(NV40_PGRAPH_CTXCTL_030C) == 0) - break; - } - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp); - - if (i == tv) { - DRM_ERROR("failed: inst=0x%08x save=%d\n", inst, save); - DRM_ERROR("0x40030C = 0x%08x\n", - NV_READ(NV40_PGRAPH_CTXCTL_030C)); - return -EBUSY; - } - - return 0; -} - -int -nv50_graph_load_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t inst = chan->ramin->instance >> 12; - int ret; (void)ret; - - DRM_DEBUG("ch%d\n", chan->id); - -#if 0 - if ((ret = nv50_graph_transfer_context(dev, inst, 0))) - return ret; -#endif - - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); - NV_WRITE(0x400320, 4); - NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, inst | (1<<31)); - - return 0; -} - -int -nv50_graph_save_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - uint32_t inst = chan->ramin->instance >> 12; - - DRM_DEBUG("ch%d\n", chan->id); - - return nv50_graph_transfer_context(dev, inst, 1); -} diff --git a/shared-core/nv50_grctx.h b/shared-core/nv50_grctx.h deleted file mode 100644 index a63796f3..00000000 --- a/shared-core/nv50_grctx.h +++ /dev/null @@ -1,20935 +0,0 @@ -#ifndef __NV50_GRCTX_H__ -#define __NV50_GRCTX_H__ - -static uint32_t nv50_ctxprog[] = { - 0x0070008e, 0x0070009c, 0x00200020, 0x00600008, 0x0050004c, 0x00400e89, - 0x00200000, 0x00600007, 0x00300000, 0x00c000ff, 0x00200000, 0x008000ff, - 0x00700009, 0x0041874d, 0x00401e44, 0x00401e05, 0x00401e0d, 0x00416306, - 0x00600005, 0x004015c5, 0x00600011, 0x00401c0b, 0x0090ffff, 0x0091ffff, - 0x00200020, 0x00600008, 0x0050004c, 0x00600009, 0x00416345, 0x00417e4d, - 0x0070009d, 0x004022cf, 0x0070009f, 0x0050009f, 0x00401fc0, 0x00200080, - 0x00600008, 0x00401f4f, 0x00401fc0, 0x004025cc, 0x00700081, 0x00200000, - 0x00600006, 0x00700000, 0x00111bfc, 0x00700083, 0x00300000, 0x00215900, - 0x00600007, 0x00c00b01, 0x0020001c, 0x00800001, 0x005000cb, 0x00c000ff, - 0x00700080, 0x00700083, 0x00200047, 0x00600006, 0x0011020a, 0x002005c0, - 0x00600007, 0x00300000, 0x00c000ff, 0x00c800ff, 0x00416e07, 0x00202627, - 0x008000ff, 0x0040458c, 0x005000cb, 0x00a0023f, 0x00200040, 0x00600006, - 0x0070000f, 0x00170202, 0x0011020a, 0x00200032, 0x0010020d, 0x001b0242, - 0x00120302, 0x00140402, 0x00180500, 0x00130509, 0x00150550, 0x00110605, - 0x001e0607, 0x00110700, 0x00110900, 0x00110902, 0x00110a00, 0x00160b02, - 0x00110b28, 0x00140b2b, 0x00110c01, 0x00111400, 0x00111405, 0x00111407, - 0x00111409, 0x0011140b, 0x002000ea, 0x00101500, 0x00406d0f, 0x00406d4b, - 0x00213700, 0x00600007, 0x00200440, 0x008800ff, 0x0070008f, 0x00406d8c, - 0x005000cb, 0x00000000, 0x001118f8, 0x0020002b, 0x00101a05, 0x00131c00, - 0x00111c04, 0x00141c20, 0x00111c25, 0x00131c40, 0x00111c44, 0x00141c60, - 0x00111c65, 0x00131c80, 0x00111c84, 0x00141ca0, 0x00111ca5, 0x00131cc0, - 0x00111cc4, 0x00141ce0, 0x00111ce5, 0x00131d00, 0x00111d04, 0x00141d20, - 0x00111d25, 0x00131d40, 0x00111d44, 0x00141d60, 0x00111d65, 0x00131f00, - 0x00191f40, 0x0040a7e0, 0x00200217, 0x00600006, 0x00200044, 0x00102080, - 0x001120c6, 0x001520c9, 0x001920d0, 0x00122100, 0x00122103, 0x00162200, - 0x00409f0f, 0x00409f4b, 0x00213700, 0x00600007, 0x00200440, 0x008800ff, - 0x0070008f, 0x00409f8c, 0x005000cb, 0x00000000, 0x00122207, 0x00112280, - 0x00112300, 0x00112302, 0x00122380, 0x0011238b, 0x00192394, 0x0040b9e1, - 0x00200285, 0x00600006, 0x00200044, 0x00102480, 0x001124c6, 0x001524c9, - 0x001924d0, 0x00122500, 0x00122503, 0x00162600, 0x00122607, 0x00112680, - 0x00112700, 0x00112702, 0x00122780, 0x0011278b, 0x00192794, 0x0040d5e2, - 0x002002f3, 0x00600006, 0x00200044, 0x00102880, 0x001128c6, 0x001528c9, - 0x0040c90f, 0x0040c94b, 0x00213700, 0x00600007, 0x00200440, 0x008800ff, - 0x0070008f, 0x0040c98c, 0x005000cb, 0x00000000, 0x001928d0, 0x00122900, - 0x00122903, 0x00162a00, 0x00122a07, 0x00112a80, 0x00112b00, 0x00112b02, - 0x00122b80, 0x00112b8b, 0x00192b94, 0x0040e7e3, 0x00200361, 0x00600006, - 0x00200044, 0x00102c80, 0x00112cc6, 0x00152cc9, 0x00192cd0, 0x00122d00, - 0x00122d03, 0x00162e00, 0x00122e07, 0x00112e80, 0x00112f00, 0x00112f02, - 0x00122f80, 0x00112f8b, 0x00192f94, 0x004103e4, 0x002003cf, 0x00600006, - 0x00200044, 0x00103080, 0x0040f50f, 0x0040f54b, 0x00213700, 0x00600007, - 0x00200440, 0x008800ff, 0x0070008f, 0x0040f58c, 0x005000cb, 0x00000000, - 0x001130c6, 0x001530c9, 0x001930d0, 0x00123100, 0x00123103, 0x00163200, - 0x00123207, 0x00113280, 0x00113300, 0x00113302, 0x00123380, 0x0011338b, - 0x00193394, 0x004115e5, 0x0020043d, 0x00600006, 0x00200044, 0x00103480, - 0x001134c6, 0x001534c9, 0x001934d0, 0x00123500, 0x00123503, 0x00163600, - 0x00123607, 0x00113680, 0x00113700, 0x00113702, 0x00123780, 0x0011378b, - 0x00193794, 0x004131e6, 0x002004ab, 0x00600006, 0x00200044, 0x00103880, - 0x0041230f, 0x0041234b, 0x00213700, 0x00600007, 0x00200440, 0x008800ff, - 0x0070008f, 0x0041238c, 0x005000cb, 0x00000000, 0x001138c6, 0x001538c9, - 0x001938d0, 0x00123900, 0x00123903, 0x00163a00, 0x00123a07, 0x00113a80, - 0x00113b00, 0x00113b02, 0x00123b80, 0x00113b8b, 0x00193b94, 0x004143e7, - 0x00200519, 0x00600006, 0x00200044, 0x00103c80, 0x00113cc6, 0x00153cc9, - 0x00193cd0, 0x00123d00, 0x00123d03, 0x00163e00, 0x00123e07, 0x00113e80, - 0x00113f00, 0x00113f02, 0x00123f80, 0x00113f8b, 0x00193f94, 0x00000000, - 0x00414a0f, 0x005000cb, 0x00213700, 0x00600007, 0x00200440, 0x008800ff, - 0x005000cb, 0x00414d87, 0x0060000a, 0x00000000, 0x00415c00, 0x007000a0, - 0x00700080, 0x002005c0, 0x00600007, 0x00200004, 0x00c000ff, 0x008000ff, - 0x005000cb, 0x00700000, 0x00200000, 0x00600006, 0x00111bfe, 0x00417e4d, - 0x00700000, 0x00200000, 0x00600006, 0x00111bfe, 0x00700080, 0x0070001d, - 0x0040114d, 0x00700081, 0x00600004, 0x0050004a, 0x00416888, 0x0060000b, - 0x00200000, 0x00600006, 0x00700000, 0x00417e0b, 0x00111bfd, 0x0040374d, - 0x00202627, 0x008000fd, 0x005000cb, 0x00c00002, 0x002005c0, 0x00600007, - 0x0020015f, 0x00800002, 0x005000cb, 0x00c01802, 0x002024c8, 0x00800002, - 0x005000cb, 0x0040434d, 0x0060000b, 0x00417c4d, 0x00700001, 0x00700003, - 0x00418206, 0x00418305, 0x0060000d, 0x00700005, 0x0070000d, 0x00700006, - 0x0070000b, 0x0070000e, 0x0070001c, 0x0060000c, ~0 -}; - -static uint32_t nv50_ctxvals[] = { - 0x0043, 0x00000000, - 0x0001, 0x00000030, - 0x0004, 0x00000000, - 0x0001, 0xff400040, - 0x0001, 0xfff00080, - 0x0001, 0xfff70090, - 0x0001, 0xffe806a8, - 0x0001, 0x00000002, - 0x0028, 0x00000000, - 0x0001, 0x00000003, - 0x0001, 0x00001000, - 0x000e, 0x00000000, - 0x0001, 0x0000fe0c, - 0x0004, 0x00000000, - 0x0001, 0x00001000, - 0x000a, 0x00000000, - 0x0001, 0x0001fd87, - 0x0004, 0x00000000, - 0x0001, 0x00001018, - 0x0001, 0x000000ff, - 0x000d, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x0001005f, - 0x0001, 0x00000000, - 0x0001, 0x00000600, - 0x0001, 0x00000006, - 0x0004, 0x00000000, - 0x0001, 0x000000ff, - 0x0001, 0x00000000, - 0x0001, 0x00000400, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00300080, - 0x0001, 0x00000004, - 0x0006, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0005, 0x00000000, - 0x0001, 0x00000002, - 0x0002, 0x00000001, - 0x0003, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x003fffff, - 0x0001, 0x00001fff, - 0x0001, 0x00000000, - 0x0002, 0x00000001, - 0x0001, 0x00000000, - 0x0003, 0x00000001, - 0x0001, 0x00000004, - 0x0003, 0x00000001, - 0x0001, 0x00000007, - 0x0001, 0x00000001, - 0x0001, 0x00000007, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0002, 0x00000001, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x0000000a, - 0x0003, 0x00000000, - 0x0001, 0x00000040, - 0x0001, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00000100, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0006, 0x00000000, - 0x0001, 0x00000001, - 0x0008, 0x00000000, - 0x0001, 0x00000004, - 0x0005, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000100, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 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0x001c, 0x00000000, - 0x0004, 0x00000002, - 0x0004, 0x00000000, - 0x0004, 0x0fac6881, - 0x004c, 0x00000000, - 0x0004, 0x00000001, - 0x0024, 0x00000000, - 0x0004, 0x00000004, - 0x000c, 0x00000000, - 0x0004, 0x00000001, - 0x0004, 0x00000000, - 0x0004, 0x00000400, - 0x0004, 0x00000000, - 0x0004, 0x00000300, - 0x0004, 0x00000000, - 0x0004, 0x00001001, - 0x001c, 0x00000000, - 0x0004, 0x00000011, - 0x003c, 0x00000000, - 0x0004, 0x0fac6881, - 0x0004, 0x00000000, - 0x0004, 0x0000000f, - 0x00bc, 0x00000000, - 0x0004, 0x00003e60, - 0x001c, 0x00000000, - 0x0004, 0x00000011, - 0x0014, 0x00000000, - 0x0004, 0x00000004, - 0x000c, 0x00000000, - 0x0004, 0x00000001, - 0x0004, 0x00000000, - 0x0004, 0x00000001, - 0x001c, 0x00000000, - 0x0004, 0x00000001, - 0x001c, 0x00000000, - 0x0004, 0x00000001, - 0x000c, 0x00000000, - 0x0004, 0x00000001, - 0x0014, 0x00000000, - 0x0004, 0x2a712488, - 0x000c, 0x00000000, - 0x0004, 0x4085c000, - 0x0004, 0x00000000, - 0x0004, 0x00000040, - 0x0004, 0x00000000, - 0x0004, 0x00000100, - 0x0004, 0x00000000, - 0x0004, 0x00010100, - 0x0004, 0x00000000, - 0x0004, 0x02800000, - 0x007c, 0x00000000, - 0x0004, 0x04e3bfdf, - 0x0004, 0x00000000, - 0x0004, 0x04e3bfdf, - 0x0004, 0x00000000, - 0x0004, 0x00000001, - 0x000c, 0x00000000, - 0x0004, 0x00ffff00, - 0x0004, 0x00000000, - 0x0004, 0x00000001, - 0x0014, 0x00000000, - 0x0004, 0x00ffff00, - 0x0044, 0x00000000, - 0x0004, 0x00000001, - 0x000c, 0x00000000, - 0x0004, 0x00000001, - 0x0004, 0x00000000, - 0x0004, 0x30201000, - 0x0004, 0x00000000, - 0x0004, 0x70605040, - 0x0004, 0x00000000, - 0x0004, 0xb8a89888, - 0x0004, 0x00000000, - 0x0004, 0xf8e8d8c8, - 0x000c, 0x00000000, - 0x0004, 0x0000001a, - 0x4c70, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x08100c12, - 0x000f, 0x00000000, - 0x0001, 0x08100c12, - 0x000f, 0x00000000, - 0x0001, 0x00080c14, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00080c14, - 0x0017, 0x00000000, - 0x0001, 0x08100c12, - 0x0007, 0x00000000, - 0x0001, 0x00000027, - 0x0017, 0x00000000, - 0x0001, 0x00000001, - 0x1e0f, 0x00000000, - 0x0001, 0x00000001, - 0x00b7, 0x00000000, - 0x0001, 0x08100c12, - 0x005f, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x000f, 0x00000000, - 0x0001, 0x00000080, - 0x001f, 0x00000000, - 0x0001, 0x00000080, - 0x000f, 0x00000000, - 0x0001, 0x0000003f, - 0x0057, 0x00000000, - 0x0001, 0x00000002, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0047, 0x00000000, - 0x0001, 0x00000004, - 0x001f, 0x00000000, - 0x0001, 0x00000004, - 0x0087, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00001001, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0107, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x00000010, - 0x000f, 0x00000000, - 0x0001, 0x00000003, - 0x001f, 0x00000000, - 0x0001, 0x08100c12, - 0x0008, 0x00000000, - 0x0008, 0x00000080, - 0x0008, 0x80007004, - 0x0008, 0x04000400, - 0x0008, 0x00001000, - 0x0010, 0x00000000, - 0x0008, 0x00000001, - 0x0010, 0x00000000, - 0x0010, 0x00001000, - 0x0008, 0x00000001, - 0x0008, 0x00000000, - 0x0008, 0x00000004, - 0x0008, 0x00000002, - 0x0058, 0x00000000, - 0x0008, 0x00000080, - 0x0008, 0x80007004, - 0x0008, 0x04000400, - 0x0008, 0x00001000, - 0x0010, 0x00000000, - 0x0008, 0x00000001, - 0x0010, 0x00000000, - 0x0010, 0x00001000, - 0x0008, 0x00000001, - 0x0008, 0x00000000, - 0x0008, 0x00000004, - 0x0008, 0x00000002, - 0x0050, 0x00000000, - 0x0008, 0x08100c12, - 0x0030, 0x00000000, - 0x0020, 0x0000ffff, - 0x0008, 0x00000001, - 0x0010, 0x00010001, - 0x0008, 0x00000001, - 0x0008, 0x00000000, - 0x0008, 0x0001fe21, - 0x0028, 0x00000000, - 0x0008, 0x08100c12, - 0x0008, 0x00000004, - 0x0008, 0x00000000, - 0x0008, 0x00000002, - 0x0008, 0x00000011, - 0x0040, 0x00000000, - 0x0008, 0x0fac6881, - 0x0020, 0x00000000, - 0x0008, 0x00000004, - 0x0048, 0x00000000, - 0x0008, 0x00000002, - 0x0010, 0x00000001, - 0x0008, 0x00000002, - 0x0018, 0x00000001, - 0x0008, 0x00000000, - 0x0008, 0x00000004, - 0x1d00, 0x00000000, - 0x0008, 0x00000011, - 0x0008, 0x00000000, - 0x0008, 0x00000001, - 0x0000 -}; - -static uint32_t nv84_ctxprog[] = { - 0x0070008e, 0x0070009c, 0x00200020, 0x00600008, 0x0050004c, 0x00400e89, - 0x00200000, 0x00600007, 0x00300000, 0x00c000ff, 0x00200000, 0x008000ff, - 0x00700009, 0x0041634d, 0x00402944, 0x00402905, 0x0040290d, 0x00413e06, - 0x00600005, 0x004015c5, 0x00600011, 0x0040270b, 0x004021c5, 0x00700000, - 0x00700081, 0x00600004, 0x0050004a, 0x00216f40, 0x00600007, 0x00c02801, - 0x0020002e, 0x00800001, 0x005000cb, 0x0090ffff, 0x0091ffff, 0x00200020, - 0x00600008, 0x0050004c, 0x00600009, 0x00413e45, 0x0041594d, 0x0070009d, - 0x00402dcf, 0x0070009f, 0x0050009f, 0x00402ac0, 0x00200200, 0x00600008, - 0x00402a4f, 0x00402ac0, 0x004030cc, 0x00700081, 0x00200000, 0x00600006, - 0x00700000, 0x00111bfc, 0x00700083, 0x00300000, 0x00216f40, 0x00600007, - 0x00c00b01, 0x0020001e, 0x00800001, 0x005000cb, 0x00c000ff, 0x00700080, - 0x00700083, 0x00200047, 0x00600006, 0x0011020a, 0x00200480, 0x00600007, - 0x00300000, 0x00c000ff, 0x00c800ff, 0x00414907, 0x00202916, 0x008000ff, - 0x0040508c, 0x005000cb, 0x00a0023f, 0x00200040, 0x00600006, 0x0070000f, - 0x00170202, 0x0011020a, 0x00200032, 0x0010020d, 0x001c0242, 0x00120302, - 0x00140402, 0x00180500, 0x00130509, 0x00150550, 0x00110605, 0x0020000f, - 0x00100607, 0x00110700, 0x00110900, 0x00120902, 0x00110a00, 0x00160b02, - 0x00120b28, 0x00140b2b, 0x00110c01, 0x00111400, 0x00111405, 0x00111407, - 0x00111409, 0x0011140b, 0x002000cb, 0x00101500, 0x0040790f, 0x0040794b, - 0x00214d40, 0x00600007, 0x0020043e, 0x008800ff, 0x0070008f, 0x0040798c, - 0x005000cb, 0x00000000, 0x0020002b, 0x00101a05, 0x00131c00, 0x00121c04, - 0x00141c20, 0x00111c25, 0x00131c40, 0x00121c44, 0x00141c60, 0x00111c65, - 0x00131c80, 0x00121c84, 0x00141ca0, 0x00111ca5, 0x00131cc0, 0x00121cc4, - 0x00141ce0, 0x00111ce5, 0x00131f00, 0x00191f40, 0x0040a1e0, 0x002001ed, - 0x00600006, 0x00200044, 0x00102080, 0x001120c6, 0x001520c9, 0x001920d0, - 0x00122100, 0x00122103, 0x00162200, 0x00122207, 0x00112280, 0x00112300, - 0x00112302, 0x00122380, 0x0011238b, 0x00112394, 0x0011239c, 0x0040bee1, - 0x00200254, 0x00600006, 0x00200044, 0x00102480, 0x0040af0f, 0x0040af4b, - 0x00214d40, 0x00600007, 0x0020043e, 0x008800ff, 0x0070008f, 0x0040af8c, - 0x005000cb, 0x00000000, 0x001124c6, 0x001524c9, 0x001924d0, 0x00122500, - 0x00122503, 0x00162600, 0x00122607, 0x00112680, 0x00112700, 0x00112702, - 0x00122780, 0x0011278b, 0x00112794, 0x0011279c, 0x0040d1e2, 0x002002bb, - 0x00600006, 0x00200044, 0x00102880, 0x001128c6, 0x001528c9, 0x001928d0, - 0x00122900, 0x00122903, 0x00162a00, 0x00122a07, 0x00112a80, 0x00112b00, - 0x00112b02, 0x00122b80, 0x00112b8b, 0x00112b94, 0x00112b9c, 0x0040eee3, - 0x00200322, 0x00600006, 0x00200044, 0x00102c80, 0x0040df0f, 0x0040df4b, - 0x00214d40, 0x00600007, 0x0020043e, 0x008800ff, 0x0070008f, 0x0040df8c, - 0x005000cb, 0x00000000, 0x00112cc6, 0x00152cc9, 0x00192cd0, 0x00122d00, - 0x00122d03, 0x00162e00, 0x00122e07, 0x00112e80, 0x00112f00, 0x00112f02, - 0x00122f80, 0x00112f8b, 0x00112f94, 0x00112f9c, 0x004101e4, 0x00200389, - 0x00600006, 0x00200044, 0x00103080, 0x001130c6, 0x001530c9, 0x001930d0, - 0x00123100, 0x00123103, 0x00163200, 0x00123207, 0x00113280, 0x00113300, - 0x00113302, 0x00123380, 0x0011338b, 0x00113394, 0x0011339c, 0x00411ee5, - 0x002003f0, 0x00600006, 0x00200044, 0x00103480, 0x00410f0f, 0x00410f4b, - 0x00214d40, 0x00600007, 0x0020043e, 0x008800ff, 0x0070008f, 0x00410f8c, - 0x005000cb, 0x00000000, 0x001134c6, 0x001534c9, 0x001934d0, 0x00123500, - 0x00123503, 0x00163600, 0x00123607, 0x00113680, 0x00113700, 0x00113702, - 0x00123780, 0x0011378b, 0x00113794, 0x0011379c, 0x00000000, 0x0041250f, - 0x005000cb, 0x00214d40, 0x00600007, 0x0020043e, 0x008800ff, 0x005000cb, - 0x00412887, 0x0060000a, 0x00000000, 0x00413700, 0x007000a0, 0x00700080, - 0x00200480, 0x00600007, 0x00200004, 0x00c000ff, 0x008000ff, 0x005000cb, - 0x00700000, 0x00200000, 0x00600006, 0x00111bfe, 0x0041594d, 0x00700000, - 0x00200000, 0x00600006, 0x00111bfe, 0x00700080, 0x0070001d, 0x0040114d, - 0x00700081, 0x00600004, 0x0050004a, 0x00414388, 0x0060000b, 0x00200000, - 0x00600006, 0x00700000, 0x0041590b, 0x00111bfd, 0x0040424d, 0x00202916, - 0x008000fd, 0x005000cb, 0x00c00002, 0x00200480, 0x00600007, 0x00200160, - 0x00800002, 0x005000cb, 0x00c01802, 0x002027b6, 0x00800002, 0x005000cb, - 0x00404e4d, 0x0060000b, 0x0041574d, 0x00700001, 0x005000cf, 0x00700003, - 0x00415e06, 0x00415f05, 0x0060000d, 0x00700005, 0x0070000d, 0x00700006, - 0x0070000b, 0x0070000e, 0x0070001c, 0x0060000c, ~0 -}; - -static uint32_t nv84_ctxvals[] = { - 0x0043, 0x00000000, - 0x0001, 0x00000030, - 0x0008, 0x00000000, - 0x0001, 0x00000002, - 0x0028, 0x00000000, - 0x0001, 0x00000003, - 0x0001, 0x00001000, - 0x000f, 0x00000000, - 0x0001, 0x0000fe0c, - 0x0004, 0x00000000, - 0x0001, 0x00001000, - 0x000a, 0x00000000, - 0x0001, 0x00000187, - 0x0004, 0x00000000, - 0x0001, 0x00001018, - 0x0001, 0x000000ff, - 0x000e, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x044d00df, - 0x0001, 0x00000000, - 0x0001, 0x00000600, - 0x0005, 0x00000000, - 0x0001, 0x01000000, - 0x0001, 0x000000ff, - 0x0001, 0x00000000, - 0x0001, 0x00000400, - 0x0005, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x000e0080, - 0x0001, 0x00000004, - 0x0006, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0005, 0x00000000, - 0x0001, 0x00000002, - 0x0002, 0x00000001, - 0x0003, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x003fffff, - 0x0001, 0x00001fff, - 0x0001, 0x00000000, - 0x0002, 0x00000001, - 0x0001, 0x00000000, - 0x0003, 0x00000001, - 0x0001, 0x00000004, - 0x0003, 0x00000001, - 0x0001, 0x00000007, - 0x0001, 0x00000001, - 0x0001, 0x00000007, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000100, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000100, - 0x0004, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x00000070, - 0x0001, 0x00000080, - 0x0004, 0x00000000, - 0x0001, 0x0000000c, - 0x0001, 0x00000000, - 0x0001, 0x00000008, - 0x0001, 0x00000014, - 0x0001, 0x00000000, - 0x0001, 0x00000029, - 0x0001, 0x00000027, - 0x0001, 0x00000026, - 0x0001, 0x00000008, - 0x0001, 0x00000004, - 0x0001, 0x00000027, - 0x0002, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000002, - 0x0001, 0x00000003, - 0x0001, 0x00000004, - 0x0001, 0x00000005, - 0x0001, 0x00000006, - 0x0001, 0x00000007, - 0x0001, 0x00000001, - 0x0010, 0x00000000, - 0x0001, 0x000000cf, - 0x000b, 0x00000000, - 0x0001, 0x00000080, - 0x0002, 0x00000004, - 0x0001, 0x00000003, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000012, - 0x0001, 0x00000010, - 0x0001, 0x0000000c, - 0x0001, 0x00000001, - 0x0003, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x00000002, - 0x0001, 0x00000004, - 0x0002, 0x00000000, - 0x0001, 0x003fffff, - 0x0001, 0x00001fff, - 0x0009, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x00000014, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000002, - 0x0002, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00001000, - 0x0001, 0x00000e00, - 0x0001, 0x00001000, - 0x0001, 0x00001e00, - 0x0001, 0x00000000, - 0x0005, 0x00000001, - 0x0003, 0x00000000, - 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0x0001, 0x00000001, - 0x0027, 0x00000000, - 0x0001, 0x00000004, - 0x000f, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00000400, - 0x0007, 0x00000000, - 0x0001, 0x00000300, - 0x0007, 0x00000000, - 0x0001, 0x00001001, - 0x001f, 0x00000000, - 0x0001, 0x00000011, - 0x003f, 0x00000000, - 0x0001, 0x0fac6881, - 0x0007, 0x00000000, - 0x0001, 0x0000000f, - 0x00bf, 0x00000000, - 0x0001, 0x001ffe67, - 0x001f, 0x00000000, - 0x0001, 0x00000011, - 0x0017, 0x00000000, - 0x0001, 0x00000004, - 0x000f, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x001f, 0x00000000, - 0x0001, 0x00000001, - 0x0027, 0x00000000, - 0x0001, 0x00000001, - 0x000f, 0x00000000, - 0x0001, 0x00000001, - 0x001f, 0x00000000, - 0x0001, 0x2a712488, - 0x000f, 0x00000000, - 0x0001, 0x4085c000, - 0x0007, 0x00000000, - 0x0001, 0x00000040, - 0x0007, 0x00000000, - 0x0001, 0x00000100, - 0x0007, 0x00000000, - 0x0001, 0x00010100, - 0x0007, 0x00000000, - 0x0001, 0x02800000, - 0x0097, 0x00000000, - 0x0001, 0x04e3bfdf, - 0x0007, 0x00000000, - 0x0001, 0x04e3bfdf, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x000f, 0x00000000, - 0x0001, 0x00ffff00, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0017, 0x00000000, - 0x0001, 0x00ffff00, - 0x0047, 0x00000000, - 0x0001, 0x00000001, - 0x000f, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x30201000, - 0x0007, 0x00000000, - 0x0001, 0x70605040, - 0x0007, 0x00000000, - 0x0001, 0xb8a89888, - 0x0007, 0x00000000, - 0x0001, 0xf8e8d8c8, - 0x000f, 0x00000000, - 0x0001, 0x0000001a, - 0x637b, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x08100c12, - 0x0007, 0x00000000, - 0x0001, 0x00000003, - 0x000f, 0x00000000, - 0x0001, 0x08100c12, - 0x000f, 0x00000000, - 0x0001, 0x00080c14, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00080c14, - 0x0017, 0x00000000, - 0x0001, 0x08100c12, - 0x0007, 0x00000000, - 0x0001, 0x00000027, - 0x0017, 0x00000000, - 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0x0010, 0x00000000, - 0x0001, 0x00000001, - 0x0006, 0x00000000, - 0x0001, 0x00000001, - 0x0008, 0x00000000, - 0x0001, 0x00000004, - 0x0006, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x00000002, - 0x0006, 0x00000000, - 0x0001, 0x00000002, - 0x0058, 0x00000000, - 0x0001, 0x00000080, - 0x0006, 0x00000000, - 0x0001, 0x00000080, - 0x0001, 0x80007004, - 0x0006, 0x00000000, - 0x0001, 0x80007004, - 0x0001, 0x04000400, - 0x0006, 0x00000000, - 0x0001, 0x04000400, - 0x0001, 0x00001000, - 0x0006, 0x00000000, - 0x0001, 0x00001000, - 0x0010, 0x00000000, - 0x0001, 0x00000001, - 0x0006, 0x00000000, - 0x0001, 0x00000001, - 0x0010, 0x00000000, - 0x0001, 0x00000001, - 0x0006, 0x00000000, - 0x0001, 0x00000001, - 0x0008, 0x00000000, - 0x0001, 0x00000004, - 0x0006, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x00000002, - 0x0006, 0x00000000, - 0x0001, 0x00000002, - 0x0050, 0x00000000, - 0x0001, 0x08100c12, - 0x0006, 0x00000000, - 0x0001, 0x08100c12, - 0x0030, 0x00000000, - 0x0001, 0x0000ffff, - 0x0006, 0x00000000, - 0x0002, 0x0000ffff, - 0x0006, 0x00000000, - 0x0002, 0x0000ffff, - 0x0006, 0x00000000, - 0x0002, 0x0000ffff, - 0x0006, 0x00000000, - 0x0001, 0x0000ffff, - 0x0001, 0x00000001, - 0x0006, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00010001, - 0x0006, 0x00000000, - 0x0002, 0x00010001, - 0x0006, 0x00000000, - 0x0001, 0x00010001, - 0x0001, 0x00000001, - 0x0006, 0x00000000, - 0x0001, 0x00000001, - 0x0008, 0x00000000, - 0x0001, 0x0001fe21, - 0x0006, 0x00000000, - 0x0001, 0x0001fe21, - 0x0028, 0x00000000, - 0x0001, 0x08100c12, - 0x0006, 0x00000000, - 0x0001, 0x08100c12, - 0x0001, 0x00000004, - 0x0006, 0x00000000, - 0x0001, 0x00000004, - 0x0008, 0x00000000, - 0x0001, 0x00000002, - 0x0006, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00000011, - 0x0006, 0x00000000, - 0x0001, 0x00000011, - 0x0040, 0x00000000, - 0x0001, 0x0fac6881, - 0x0006, 0x00000000, - 0x0001, 0x0fac6881, - 0x0020, 0x00000000, - 0x0001, 0x00000004, - 0x0006, 0x00000000, - 0x0001, 0x00000004, - 0x0048, 0x00000000, - 0x0001, 0x00000002, - 0x0006, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00000001, - 0x0006, 0x00000000, - 0x0002, 0x00000001, - 0x0006, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000002, - 0x0006, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00000001, - 0x0006, 0x00000000, - 0x0002, 0x00000001, - 0x0006, 0x00000000, - 0x0002, 0x00000001, - 0x0006, 0x00000000, - 0x0001, 0x00000001, - 0x0008, 0x00000000, - 0x0001, 0x00000004, - 0x0006, 0x00000000, - 0x0001, 0x00000004, - 0x1d10, 0x00000000, - 0x0001, 0x00000011, - 0x0006, 0x00000000, - 0x0001, 0x00000011, - 0x0008, 0x00000000, - 0x0001, 0x00000001, - 0x0006, 0x00000000, - 0x0001, 0x00000001, - 0x0000 -}; - -static uint32_t nv86_ctxprog[] = { - 0x0070008e, 0x0070009c, 0x00200020, 0x00600008, 0x0050004c, 0x00400e89, - 0x00200000, 0x00600007, 0x00300000, 0x00c000ff, 0x00200000, 0x008000ff, - 0x00700009, 0x0040dd4d, 0x00402944, 0x00402905, 0x0040290d, 0x0040b906, - 0x00600005, 0x004015c5, 0x00600011, 0x0040270b, 0x004021c5, 0x00700000, - 0x00700081, 0x00600004, 0x0050004a, 0x00216d80, 0x00600007, 0x00c02801, - 0x0020002e, 0x00800001, 0x005000cb, 0x0090ffff, 0x0091ffff, 0x00200020, - 0x00600008, 0x0050004c, 0x00600009, 0x0040b945, 0x0040d44d, 0x0070009d, - 0x00402dcf, 0x0070009f, 0x0050009f, 0x00402ac0, 0x00200200, 0x00600008, - 0x00402a4f, 0x00402ac0, 0x004030cc, 0x00700081, 0x00200000, 0x00600006, - 0x00700000, 0x00111bfc, 0x00700083, 0x00300000, 0x00216d80, 0x00600007, - 0x00c00b01, 0x0020001e, 0x00800001, 0x005000cb, 0x00c000ff, 0x00700080, - 0x00700083, 0x00200047, 0x00600006, 0x0011020a, 0x00200280, 0x00600007, - 0x00300000, 0x00c000ff, 0x00c800ff, 0x0040c407, 0x00202916, 0x008000ff, - 0x0040508c, 0x005000cb, 0x00a0023f, 0x00200040, 0x00600006, 0x0070000f, - 0x00170202, 0x0011020a, 0x00200032, 0x0010020d, 0x001c0242, 0x00120302, - 0x00140402, 0x00180500, 0x00130509, 0x00150550, 0x00110605, 0x0020000f, - 0x00100607, 0x00110700, 0x00110900, 0x00120902, 0x00110a00, 0x00160b02, - 0x00120b28, 0x00140b2b, 0x00110c01, 0x00111400, 0x00111405, 0x00111407, - 0x00111409, 0x0011140b, 0x002000cb, 0x00101500, 0x0040790f, 0x0040794b, - 0x00214b40, 0x00600007, 0x00200442, 0x008800ff, 0x0070008f, 0x0040798c, - 0x005000cb, 0x00000000, 0x0020002b, 0x00101a05, 0x00131c00, 0x00121c04, - 0x00141c20, 0x00111c25, 0x00131c40, 0x00121c44, 0x00141c60, 0x00111c65, - 0x00131f00, 0x00191f40, 0x004099e0, 0x002001d9, 0x00600006, 0x00200044, - 0x00102080, 0x001120c6, 0x001520c9, 0x001920d0, 0x00122100, 0x00122103, - 0x00162200, 0x00122207, 0x00112280, 0x00112300, 0x00112302, 0x00122380, - 0x0011238b, 0x00112394, 0x0011239c, 0x00000000, 0x0040a00f, 0x005000cb, - 0x00214b40, 0x00600007, 0x00200442, 0x008800ff, 0x005000cb, 0x0040a387, - 0x0060000a, 0x00000000, 0x0040b200, 0x007000a0, 0x00700080, 0x00200280, - 0x00600007, 0x00200004, 0x00c000ff, 0x008000ff, 0x005000cb, 0x00700000, - 0x00200000, 0x00600006, 0x00111bfe, 0x0040d44d, 0x00700000, 0x00200000, - 0x00600006, 0x00111bfe, 0x00700080, 0x0070001d, 0x0040114d, 0x00700081, - 0x00600004, 0x0050004a, 0x0040be88, 0x0060000b, 0x00200000, 0x00600006, - 0x00700000, 0x0040d40b, 0x00111bfd, 0x0040424d, 0x00202916, 0x008000fd, - 0x005000cb, 0x00c00002, 0x00200280, 0x00600007, 0x00200160, 0x00800002, - 0x005000cb, 0x00c01802, 0x002027b6, 0x00800002, 0x005000cb, 0x00404e4d, - 0x0060000b, 0x0040d24d, 0x00700001, 0x00700003, 0x0040d806, 0x0040d905, - 0x0060000d, 0x00700005, 0x0070000d, 0x00700006, 0x0070000b, 0x0070000e, - 0x0060000c, ~0 -}; - -static uint32_t nv86_ctxvals[] = { - 0x0043, 0x00000000, - 0x0001, 0x00000030, - 0x0031, 0x00000000, - 0x0001, 0x00000003, - 0x0001, 0x00001000, - 0x000f, 0x00000000, - 0x0001, 0x0000fe0c, - 0x0004, 0x00000000, - 0x0001, 0x00001000, - 0x000a, 0x00000000, - 0x0001, 0x00000187, - 0x0004, 0x00000000, - 0x0001, 0x00001018, - 0x0001, 0x000000ff, - 0x000e, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x044d00df, - 0x0001, 0x00000000, - 0x0001, 0x00000600, - 0x0005, 0x00000000, - 0x0001, 0x01000000, - 0x0001, 0x000000ff, - 0x0001, 0x00000000, - 0x0001, 0x00000400, - 0x0005, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000080, - 0x0001, 0x00000004, - 0x0006, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0005, 0x00000000, - 0x0001, 0x00000002, - 0x0002, 0x00000001, - 0x0003, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x003fffff, - 0x0001, 0x00001fff, - 0x0001, 0x00000000, - 0x0002, 0x00000001, - 0x0001, 0x00000000, - 0x0003, 0x00000001, - 0x0001, 0x00000004, - 0x0003, 0x00000001, - 0x0001, 0x00000007, - 0x0001, 0x00000001, - 0x0001, 0x00000007, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000100, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000100, - 0x0004, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x00000070, - 0x0001, 0x00000080, - 0x0004, 0x00000000, - 0x0001, 0x0000000c, - 0x0001, 0x00000000, - 0x0001, 0x00000008, - 0x0001, 0x00000014, - 0x0001, 0x00000000, - 0x0001, 0x00000029, - 0x0001, 0x00000027, - 0x0001, 0x00000026, - 0x0001, 0x00000008, - 0x0001, 0x00000004, - 0x0001, 0x00000027, - 0x0002, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000002, - 0x0001, 0x00000003, - 0x0001, 0x00000004, - 0x0001, 0x00000005, - 0x0001, 0x00000006, - 0x0001, 0x00000007, - 0x0001, 0x00000001, - 0x0010, 0x00000000, - 0x0001, 0x000000cf, - 0x000b, 0x00000000, - 0x0001, 0x00000080, - 0x0002, 0x00000004, - 0x0001, 0x00000003, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000012, - 0x0001, 0x00000010, - 0x0001, 0x0000000c, - 0x0001, 0x00000001, - 0x0003, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x00000002, - 0x0001, 0x00000004, - 0x0002, 0x00000000, - 0x0001, 0x003fffff, - 0x0001, 0x00001fff, - 0x0009, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x00000014, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000002, - 0x0002, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00001000, - 0x0001, 0x00000e00, - 0x0001, 0x00001000, - 0x0001, 0x00001e00, - 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0x0001, 0x00080c14, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x001f, 0x00000000, - 0x0001, 0x2a712488, - 0x000f, 0x00000000, - 0x0001, 0x4085c000, - 0x0007, 0x00000000, - 0x0001, 0x00000040, - 0x0007, 0x00000000, - 0x0001, 0x00000100, - 0x0007, 0x00000000, - 0x0001, 0x00010100, - 0x0007, 0x00000000, - 0x0001, 0x02800000, - 0x0097, 0x00000000, - 0x0001, 0x04e3bfdf, - 0x0007, 0x00000000, - 0x0001, 0x04e3bfdf, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x000f, 0x00000000, - 0x0001, 0x00ffff00, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0017, 0x00000000, - 0x0001, 0x00ffff00, - 0x0047, 0x00000000, - 0x0001, 0x00000001, - 0x000f, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x30201000, - 0x0007, 0x00000000, - 0x0001, 0x70605040, - 0x0007, 0x00000000, - 0x0001, 0xb8a89888, - 0x0007, 0x00000000, - 0x0001, 0xf8e8d8c8, - 0x000f, 0x00000000, - 0x0001, 0x0000001a, - 0x0015, 0x00000000, - 0x0001, 0x00000001, - 0x0017, 0x00000000, - 0x0001, 0x00000010, - 0x01c7, 0x00000000, - 0x0001, 0x00000088, - 0x0007, 0x00000000, - 0x0001, 0x00000088, - 0x0017, 0x00000000, - 0x0001, 0x00000004, - 0x00b7, 0x00000000, - 0x0001, 0x00000026, - 0x0017, 0x00000000, - 0x0001, 0x3f800000, - 0x001f, 0x00000000, - 0x0001, 0x0000001a, - 0x0007, 0x00000000, - 0x0001, 0x00000010, - 0x0147, 0x00000000, - 0x0001, 0x00000052, - 0x000f, 0x00000000, - 0x0001, 0x00000026, - 0x000f, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x000f, 0x00000000, - 0x0001, 0x0000001a, - 0x0017, 0x00000000, - 0x0001, 0x00ffff00, - 0x000f, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x000f, 0x00000000, - 0x0001, 0x00000080, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00080c14, - 0x000f, 0x00000000, - 0x0001, 0x000007ff, - 0x2a17, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x000f, 0x00000000, - 0x0001, 0x00000080, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x000f, 0x00000000, - 0x0001, 0x00000027, - 0x000f, 0x00000000, - 0x0001, 0x00000026, - 0x001f, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0127, 0x00000000, - 0x0001, 0x04e3bfdf, - 0x0007, 0x00000000, - 0x0001, 0x04e3bfdf, - 0x0017, 0x00000000, - 0x0001, 0x0001fe21, - 0x933d, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x08100c12, - 0x0007, 0x00000000, - 0x0001, 0x00000003, - 0x000f, 0x00000000, - 0x0001, 0x08100c12, - 0x000f, 0x00000000, - 0x0001, 0x00080c14, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00080c14, - 0x0017, 0x00000000, - 0x0001, 0x08100c12, - 0x0007, 0x00000000, - 0x0001, 0x00000027, - 0x0017, 0x00000000, - 0x0001, 0x00000001, - 0x1e0f, 0x00000000, - 0x0001, 0x00000001, - 0x00b7, 0x00000000, - 0x0001, 0x08100c12, - 0x0067, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x000f, 0x00000000, - 0x0001, 0x00000080, - 0x001f, 0x00000000, - 0x0001, 0x00000080, - 0x000f, 0x00000000, - 0x0001, 0x0000003f, - 0x0057, 0x00000000, - 0x0001, 0x00000002, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0047, 0x00000000, - 0x0001, 0x00000004, - 0x001f, 0x00000000, - 0x0001, 0x00000004, - 0x008f, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00001001, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0107, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x00000010, - 0x0017, 0x00000000, - 0x0001, 0x00000003, - 0x0000 -}; - -static uint32_t nv92_ctxprog[] = { - 0x0070008E, 0x0070009C, 0x00200020, 0x00600008, 0x0050004C, 0x00400E89, - 0x00200000, 0x00600007, 0x00300000, 0x00C000FF, 0x00200000, 0x008000FF, - 0x00700009, 0x0041924D, 0x00402944, 0x00402905, 0x0040290D, 0x00416E06, - 0x00600005, 0x004015C5, 0x00600011, 0x0040270B, 0x004021C5, 0x00700000, - 0x00700081, 0x00600004, 0x0050004A, 0x00219600, 0x00600007, 0x00C02701, - 0x0020002E, 0x00800001, 0x005000CB, 0x0090FFFF, 0x0091FFFF, 0x00200020, - 0x00600008, 0x0050004C, 0x00600009, 0x00416E45, 0x0041894D, 0x0070009D, - 0x00402DCF, 0x0070009F, 0x0050009F, 0x00402AC0, 0x00200080, 0x00600008, - 0x00402A4F, 0x00402AC0, 0x004030CC, 0x00700081, 0x00200000, 0x00600006, - 0x00700000, 0x00111BFC, 0x00700083, 0x00300000, 0x00219600, 0x00600007, - 0x00C00A01, 0x0020001E, 0x00800001, 0x005000CB, 0x00C000FF, 0x00700080, - 0x00700083, 0x00200047, 0x00600006, 0x0011020A, 0x00200540, 0x00600007, - 0x00300000, 0x00C000FF, 0x00C800FF, 0x00417907, 0x00202DD2, 0x008000FF, - 0x0040508C, 0x005000CB, 0x00A0023F, 0x00200040, 0x00600006, 0x0070000F, - 0x00170202, 0x0011020A, 0x00200032, 0x0010020D, 0x001C0242, 0x00120302, - 0x00140402, 0x00180500, 0x00130509, 0x00150550, 0x00110605, 0x0020000F, - 0x00100607, 0x00110700, 0x00110900, 0x00120902, 0x00110A00, 0x00160B02, - 0x00120B28, 0x00140B2B, 0x00110C01, 0x00111400, 0x00111405, 0x00111407, - 0x00111409, 0x0011140B, 0x002000CB, 0x00101500, 0x0040790F, 0x0040794B, - 0x00217400, 0x00600007, 0x0020043E, 0x008800FF, 0x0070008F, 0x0040798C, - 0x005000CB, 0x00000000, 0x00141A05, 0x00131A0C, 0x00131C00, 0x00121C04, - 0x00141C20, 0x00111C25, 0x00131C40, 0x00121C44, 0x00141C60, 0x00111C65, - 0x00131C80, 0x00121C84, 0x00141CA0, 0x00111CA5, 0x00131CC0, 0x00121CC4, - 0x00141CE0, 0x00111CE5, 0x00131F00, 0x00191F40, 0x0040A1E0, 0x002001C9, - 0x00600006, 0x00200044, 0x00102080, 0x001120C6, 0x001520C9, 0x001920D0, - 0x00122100, 0x00122103, 0x00162200, 0x00122207, 0x00112280, 0x00112300, - 0x00112302, 0x00122380, 0x0011238B, 0x00112394, 0x0011239C, 0x0040BEE1, - 0x00200230, 0x00600006, 0x00200044, 0x00102480, 0x0040AF0F, 0x0040AF4B, - 0x00217400, 0x00600007, 0x0020043E, 0x008800FF, 0x0070008F, 0x0040AF8C, - 0x005000CB, 0x00000000, 0x001124C6, 0x001524C9, 0x001924D0, 0x00122500, - 0x00122503, 0x00162600, 0x00122607, 0x00112680, 0x00112700, 0x00112702, - 0x00122780, 0x0011278B, 0x00112794, 0x0011279C, 0x0040D1E2, 0x00200297, - 0x00600006, 0x00200044, 0x00102880, 0x001128C6, 0x001528C9, 0x001928D0, - 0x00122900, 0x00122903, 0x00162A00, 0x00122A07, 0x00112A80, 0x00112B00, - 0x00112B02, 0x00122B80, 0x00112B8B, 0x00112B94, 0x00112B9C, 0x0040EEE3, - 0x002002FE, 0x00600006, 0x00200044, 0x00102C80, 0x0040DF0F, 0x0040DF4B, - 0x00217400, 0x00600007, 0x0020043E, 0x008800FF, 0x0070008F, 0x0040DF8C, - 0x005000CB, 0x00000000, 0x00112CC6, 0x00152CC9, 0x00192CD0, 0x00122D00, - 0x00122D03, 0x00162E00, 0x00122E07, 0x00112E80, 0x00112F00, 0x00112F02, - 0x00122F80, 0x00112F8B, 0x00112F94, 0x00112F9C, 0x004101E4, 0x00200365, - 0x00600006, 0x00200044, 0x00103080, 0x001130C6, 0x001530C9, 0x001930D0, - 0x00123100, 0x00123103, 0x00163200, 0x00123207, 0x00113280, 0x00113300, - 0x00113302, 0x00123380, 0x0011338B, 0x00113394, 0x0011339C, 0x00411EE5, - 0x002003CC, 0x00600006, 0x00200044, 0x00103480, 0x00410F0F, 0x00410F4B, - 0x00217400, 0x00600007, 0x0020043E, 0x008800FF, 0x0070008F, 0x00410F8C, - 0x005000CB, 0x00000000, 0x001134C6, 0x001534C9, 0x001934D0, 0x00123500, - 0x00123503, 0x00163600, 0x00123607, 0x00113680, 0x00113700, 0x00113702, - 0x00123780, 0x0011378B, 0x00113794, 0x0011379C, 0x004131E6, 0x00200433, - 0x00600006, 0x00200044, 0x00103880, 0x001138C6, 0x001538C9, 0x001938D0, - 0x00123900, 0x00123903, 0x00163A00, 0x00123A07, 0x00113A80, 0x00113B00, - 0x00113B02, 0x00123B80, 0x00113B8B, 0x00113B94, 0x00113B9C, 0x00414EE7, - 0x0020049A, 0x00600006, 0x00200044, 0x00103C80, 0x00413F0F, 0x00413F4B, - 0x00217400, 0x00600007, 0x0020043E, 0x008800FF, 0x0070008F, 0x00413F8C, - 0x005000CB, 0x00000000, 0x00113CC6, 0x00153CC9, 0x00193CD0, 0x00123D00, - 0x00123D03, 0x00163E00, 0x00123E07, 0x00113E80, 0x00113F00, 0x00113F02, - 0x00123F80, 0x00113F8B, 0x00113F94, 0x00113F9C, 0x00000000, 0x0041550F, - 0x005000CB, 0x00217400, 0x00600007, 0x0020043E, 0x008800FF, 0x005000CB, - 0x00415887, 0x0060000A, 0x00000000, 0x00416700, 0x007000A0, 0x00700080, - 0x00200540, 0x00600007, 0x00200004, 0x00C000FF, 0x008000FF, 0x005000CB, - 0x00700000, 0x00200000, 0x00600006, 0x00111BFE, 0x0041894D, 0x00700000, - 0x00200000, 0x00600006, 0x00111BFE, 0x00700080, 0x0070001D, 0x0040114D, - 0x00700081, 0x00600004, 0x0050004A, 0x00417388, 0x0060000B, 0x00200000, - 0x00600006, 0x00700000, 0x0041890B, 0x00111BFD, 0x0040424D, 0x00202DD2, - 0x008000FD, 0x005000CB, 0x00C00002, 0x00200540, 0x00600007, 0x00200160, - 0x00800002, 0x005000CB, 0x00C01802, 0x00202C72, 0x00800002, 0x005000CB, - 0x00404E4D, 0x0060000B, 0x0041874D, 0x00700001, 0x00700003, 0x00418D06, - 0x00418E05, 0x0060000D, 0x00700005, 0x0070000D, 0x00700006, 0x0070000B, - 0x0070000E, 0x0070001C, 0x0060000C, ~0 -}; - -static uint32_t nv92_ctxvals[] = { - 0x0043, 0x00000000, - 0x0001, 0x00000030, - 0x0031, 0x00000000, - 0x0001, 0x00000003, - 0x0001, 0x00001000, - 0x000f, 0x00000000, - 0x0001, 0x0000fe0c, - 0x0004, 0x00000000, - 0x0001, 0x00001000, - 0x000a, 0x00000000, - 0x0001, 0x00000187, - 0x0004, 0x00000000, - 0x0001, 0x00001018, - 0x0001, 0x000000ff, - 0x000e, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x042500df, - 0x0001, 0x00000000, - 0x0001, 0x00000600, - 0x0005, 0x00000000, - 0x0001, 0x01000000, - 0x0001, 0x000000ff, - 0x0001, 0x00000000, - 0x0001, 0x00000400, - 0x0005, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000080, - 0x0001, 0x00000004, - 0x0006, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0005, 0x00000000, - 0x0001, 0x00000002, - 0x0002, 0x00000001, - 0x0003, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x003fffff, - 0x0001, 0x00001fff, - 0x0001, 0x00000000, - 0x0002, 0x00000001, - 0x0001, 0x00000000, - 0x0003, 0x00000001, - 0x0001, 0x00000004, - 0x0003, 0x00000001, - 0x0001, 0x00000007, - 0x0001, 0x00000001, - 0x0001, 0x00000007, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000100, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000100, - 0x0004, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x00000070, - 0x0001, 0x00000080, - 0x0004, 0x00000000, - 0x0001, 0x0000000c, - 0x0001, 0x00000000, - 0x0001, 0x00000008, - 0x0001, 0x00000014, - 0x0001, 0x00000000, - 0x0001, 0x00000029, - 0x0001, 0x00000027, - 0x0001, 0x00000026, - 0x0001, 0x00000008, - 0x0001, 0x00000004, - 0x0001, 0x00000027, - 0x0002, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000002, - 0x0001, 0x00000003, - 0x0001, 0x00000004, - 0x0001, 0x00000005, - 0x0001, 0x00000006, - 0x0001, 0x00000007, - 0x0001, 0x00000001, - 0x0010, 0x00000000, - 0x0001, 0x000000cf, - 0x000b, 0x00000000, - 0x0001, 0x00000080, - 0x0002, 0x00000004, - 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0x0015, 0x00000000, - 0x0001, 0x00080c14, - 0x0017, 0x00000000, - 0x0001, 0x00000804, - 0x000f, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x08100c12, - 0x000f, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x000f, 0x00000000, - 0x0001, 0x00000010, - 0x0027, 0x00000000, - 0x0001, 0x00000804, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x0000001a, - 0x0007, 0x00000000, - 0x0001, 0x0000007f, - 0x0009, 0x00000000, - 0x0001, 0x001ffe67, - 0x0005, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00080c14, - 0x000f, 0x00000000, - 0x0001, 0x08100c12, - 0x0001, 0x00000000, - 0x0001, 0x00000011, - 0x0005, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0009, 0x00000000, - 0x0001, 0x00000004, - 0x0005, 0x00000000, - 0x0001, 0x00000010, - 0x0009, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x000d, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x08100c12, - 0x0009, 0x00000000, - 0x0001, 0x00000001, - 0x0027, 0x00000000, - 0x0001, 0x00000001, - 0x0005, 0x00000000, - 0x0001, 0x000007ff, - 0x0007, 0x00000000, - 0x0001, 0x00080c14, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x001f, 0x00000000, - 0x0001, 0x2a712488, - 0x000f, 0x00000000, - 0x0001, 0x4085c000, - 0x0007, 0x00000000, - 0x0001, 0x00000040, - 0x0007, 0x00000000, - 0x0001, 0x00000100, - 0x0007, 0x00000000, - 0x0001, 0x00010100, - 0x0007, 0x00000000, - 0x0001, 0x02800000, - 0x0097, 0x00000000, - 0x0001, 0x04e3bfdf, - 0x0007, 0x00000000, - 0x0001, 0x04e3bfdf, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x000f, 0x00000000, - 0x0001, 0x00ffff00, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0017, 0x00000000, - 0x0001, 0x00ffff00, - 0x0047, 0x00000000, - 0x0001, 0x00000001, - 0x000f, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x30201000, - 0x0007, 0x00000000, - 0x0001, 0x70605040, - 0x0007, 0x00000000, - 0x0001, 0xb8a89888, - 0x0007, 0x00000000, - 0x0001, 0xf8e8d8c8, - 0x000f, 0x00000000, - 0x0001, 0x0000001a, - 0x0015, 0x00000000, - 0x0001, 0x00000001, - 0x0017, 0x00000000, - 0x0001, 0x00000010, - 0x01c7, 0x00000000, - 0x0001, 0x00000088, - 0x0007, 0x00000000, - 0x0001, 0x00000088, - 0x0017, 0x00000000, - 0x0001, 0x00000004, - 0x00b7, 0x00000000, - 0x0001, 0x00000026, - 0x0017, 0x00000000, - 0x0001, 0x3f800000, - 0x001f, 0x00000000, - 0x0001, 0x0000001a, - 0x0007, 0x00000000, - 0x0001, 0x00000010, - 0x0147, 0x00000000, - 0x0001, 0x00000052, - 0x000f, 0x00000000, - 0x0001, 0x00000026, - 0x000f, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x000f, 0x00000000, - 0x0001, 0x0000001a, - 0x0017, 0x00000000, - 0x0001, 0x00ffff00, - 0x000f, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x000f, 0x00000000, - 0x0001, 0x00000080, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00080c14, - 0x000f, 0x00000000, - 0x0001, 0x000007ff, - 0x2a17, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x000f, 0x00000000, - 0x0001, 0x00000080, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x000f, 0x00000000, - 0x0001, 0x00000027, - 0x000f, 0x00000000, - 0x0001, 0x00000026, - 0x001f, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0127, 0x00000000, - 0x0001, 0x04e3bfdf, - 0x0007, 0x00000000, - 0x0001, 0x04e3bfdf, - 0x0017, 0x00000000, - 0x0001, 0x0001fe21, - 0x931d, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x08100c12, - 0x0007, 0x00000000, - 0x0001, 0x00000003, - 0x000f, 0x00000000, - 0x0001, 0x08100c12, - 0x000f, 0x00000000, - 0x0001, 0x00080c14, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00080c14, - 0x0017, 0x00000000, - 0x0001, 0x08100c12, - 0x0007, 0x00000000, - 0x0001, 0x00000027, - 0x0017, 0x00000000, - 0x0001, 0x00000001, - 0x1e0f, 0x00000000, - 0x0001, 0x00000001, - 0x00b7, 0x00000000, - 0x0001, 0x08100c12, - 0x0067, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x000f, 0x00000000, - 0x0001, 0x00000080, - 0x001f, 0x00000000, - 0x0001, 0x00000080, - 0x000f, 0x00000000, - 0x0001, 0x0000003f, - 0x0057, 0x00000000, - 0x0001, 0x00000002, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0047, 0x00000000, - 0x0001, 0x00000004, - 0x001f, 0x00000000, - 0x0001, 0x00000004, - 0x008f, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00001001, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0107, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x00000010, - 0x0017, 0x00000000, - 0x0001, 0x00000003, - 0x0047, 0x00000000, - 0x0001, 0x08100c12, - 0x000f, 0x00000000, - 0x0001, 0x00000080, - 0x0007, 0x00000000, - 0x0001, 0x80007004, - 0x0007, 0x00000000, - 0x0001, 0x04000400, - 0x0007, 0x00000000, - 0x0001, 0x00001000, - 0x0017, 0x00000000, - 0x0001, 0x00000e00, - 0x0007, 0x00000000, - 0x0001, 0x00001e00, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0017, 0x00000000, - 0x0001, 0x00000001, - 0x000f, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000002, - 0x0057, 0x00000000, - 0x0001, 0x08100c12, - 0x0037, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00010001, - 0x0007, 0x00000000, - 0x0001, 0x00010001, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x000f, 0x00000000, - 0x0001, 0x0001fe21, - 0x002f, 0x00000000, - 0x0001, 0x08100c12, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x000f, 0x00000000, - 0x0001, 0x00000002, - 0x0007, 0x00000000, - 0x0001, 0x00000011, - 0x0047, 0x00000000, - 0x0001, 0x0fac6881, - 0x0027, 0x00000000, - 0x0001, 0x00000004, - 0x004f, 0x00000000, - 0x0001, 0x00000002, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00000002, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x000f, 0x00000000, - 0x0001, 0x00000004, - 0x1cff, 0x00000000, - 0x0001, 0x00000011, - 0x000f, 0x00000000, - 0x0001, 0x00000001, - 0x0000 -}; - -static uint32_t nva0_ctxprog[] = { - 0x0070009c, 0x00300000, 0x00452c09, 0x00402d09, 0x00412051, 0x00400a44, - 0x00400a05, 0x00400a0d, 0x0070008e, 0x0040124d, 0x0070009d, 0x00453b4d, - 0x00700097, 0x00453c21, 0x004446a1, 0x0044914d, 0x00449d4d, 0x0070001d, - 0x00401806, 0x00600005, 0x00444445, 0x0044308b, 0x00401845, 0x0040234d, - 0x00700081, 0x00401ccf, 0x0070009f, 0x0050009f, 0x0045174d, 0x00700017, - 0x0040230b, 0x0044984d, 0x00453d21, 0x004456a1, 0x007000a0, 0x00700001, - 0x00700003, 0x00402706, 0x00402805, 0x0060000d, 0x00700005, 0x0070000d, - 0x00700006, 0x00700002, 0x0070000b, 0x0070000e, 0x0070001c, 0x0060000c, - 0x00000000, 0x0090ffff, 0x0091ffff, 0x00450f4d, 0x00600009, 0x0048004d, - 0x00700096, 0x00403acf, 0x0070009f, 0x0050009f, 0x00412051, 0x004036c0, - 0x00200080, 0x00600008, 0x0040364f, 0x004036c0, 0x00403ecc, 0x00403651, - 0x00700016, 0x0048004d, 0x00600011, 0x0048004d, 0x0044364d, 0x0070008e, - 0x00700081, 0x00448b4d, 0x0044984d, 0x00700083, 0x00300000, 0x00217c80, - 0x00600007, 0x00c00a01, 0x00200022, 0x00800001, 0x005000cb, 0x00c000ff, - 0x00445e4d, 0x0048004d, 0x00450908, 0x00448e4d, 0x0044a64d, 0x00445e4d, - 0x00451d4d, 0x0044914d, 0x00449d4d, 0x0048004d, 0x00700083, 0x00453e4d, - 0x00a0023f, 0x00200040, 0x00600006, 0x0045374d, 0x0044a84d, 0x0020022b, - 0x0044ef60, 0x002002ba, 0x00300001, 0x0044ef61, 0x00200349, 0x00300002, - 0x0044ef62, 0x002003d8, 0x00300003, 0x0044ef63, 0x00200467, 0x00300004, - 0x0044ef64, 0x002004f6, 0x00300005, 0x0044ef65, 0x00200585, 0x00300006, - 0x0044ef66, 0x00200614, 0x00300007, 0x0044ef67, 0x002006a3, 0x00300008, - 0x0044ef68, 0x00200732, 0x00300009, 0x0044ef69, 0x00200800, 0x0038ffff, - 0x0045044d, 0x00300000, 0x005000cb, 0x0045564d, 0x005000cb, 0x00450b07, - 0x0048004d, 0x0044944d, 0x00111bfc, 0x0048004d, 0x0044944d, 0x00111bfd, - 0x0048004d, 0x0044944d, 0x00111bfe, 0x0048004d, 0x00200000, 0x00700000, - 0x00600006, 0x0048004d, 0x00200001, 0x00600006, 0x0045374d, 0x0011020a, - 0x0048004d, 0x00300000, 0x00c3ffff, 0x00200000, 0x00600007, 0x00700000, - 0x00200008, 0x008000ff, 0x005000cb, 0x0048004d, 0x00000000, 0x0048004d, - 0x00000000, 0x00170202, 0x00200032, 0x0010020d, 0x001e0242, 0x001102c0, - 0x00120302, 0x00150402, 0x00180500, 0x00130509, 0x00150550, 0x00110605, - 0x00200013, 0x00100607, 0x00110700, 0x00110900, 0x00120902, 0x00110a00, - 0x00160b02, 0x00120b28, 0x00140b2b, 0x00110c01, 0x00110d01, 0x00111400, - 0x00111405, 0x00111407, 0x00111409, 0x0011140b, 0x002000d4, 0x00101500, - 0x00141a05, 0x00131a0c, 0x00131c00, 0x00131c04, 0x00141c20, 0x00131c25, - 0x00131c40, 0x00131c44, 0x00141c60, 0x00131c65, 0x00131c80, 0x00131c84, - 0x00141ca0, 0x00131ca5, 0x00131cc0, 0x00131cc4, 0x00141ce0, 0x00131ce5, - 0x00131d00, 0x00131d04, 0x00141d20, 0x00131d25, 0x00131d40, 0x00131d44, - 0x00141d60, 0x00131d65, 0x00131d80, 0x00131d84, 0x00141da0, 0x00131da5, - 0x00131dc0, 0x00131dc4, 0x00141de0, 0x00131de5, 0x00131f00, 0x00131f04, - 0x00111f08, 0x00111f0b, 0x00200015, 0x00101f40, 0x0048004d, 0x00600006, - 0x0045564d, 0x00112020, 0x00112022, 0x00200060, 0x00102040, 0x001520c0, - 0x001120c8, 0x001420ca, 0x001b20cf, 0x00122100, 0x00122103, 0x00162140, - 0x00122147, 0x00122153, 0x001121a0, 0x001221c0, 0x001121cb, 0x001121d4, - 0x001521d8, 0x0048004d, 0x00000000, 0x00700000, 0x00600006, 0x0045374d, - 0x0048004d, 0x0060000b, 0x0048004d, 0x0060000a, 0x0048004d, 0x0060000b, - 0x00410d4d, 0x00200020, 0x00600008, 0x0050004c, 0x0048004d, 0x002003e8, - 0x00600008, 0x0050004c, 0x0048004d, 0x00600004, 0x0050004a, 0x0048004d, - 0x00c000ff, 0x00c800ff, 0x0048004d, 0x00c000ff, 0x00c800ff, 0x0048004d, - 0x00700016, 0x0070008e, 0x00700082, 0x00500041, 0x0045134d, 0x00700095, - 0x005000d1, 0x00600016, 0x00500052, 0x00700002, 0x00700015, 0x0040284d, - 0x0070008e, 0x00450f4d, 0x00200000, 0x00600007, 0x00300000, 0x00c000ff, - 0x00200000, 0x008000ff, 0x00700009, 0x0070000e, 0x0048004d, 0x00700080, - 0x00480017, 0x00700000, 0x0048004d, 0x0048004d, 0x0048004d, 0x0048004d, - 0x0070008e, 0x00450f4d, 0x00700083, 0x00451a4d, 0x0045474d, 0x0070000f, - 0x0041468c, 0x005000cb, 0x0048004d, 0x00200800, 0x00600007, 0x00454b87, - 0x0048004d, 0x00000000, 0x0020216c, 0x0045374d, 0x008000ff, 0x0048004d, - 0x00211380, 0x00600007, 0x00200d20, 0x0045374d, 0x008800ff, 0x0048004d, - 0x0048000f, 0x0048004b, 0x0045504d, 0x0070008f, 0x0048008c, 0x005000cb, - 0x0048004d, ~0 -}; - -static unsigned nva0_ctxvals[] = { - 0x0001, 0x00007f30, - 0x0042, 0x00000000, - 0x0001, 0x00000030, - 0x0007, 0x00000000, - 0x0001, 0x00000002, - 0x0028, 0x00000000, - 0x0001, 0x00000003, - 0x0001, 0x00001000, - 0x0012, 0x00000000, - 0x0001, 0x0000fe0c, - 0x0005, 0x00000000, - 0x0001, 0x00001000, - 0x000a, 0x00000000, - 0x0001, 0x00000187, - 0x0004, 0x00000000, - 0x0001, 0x00001018, - 0x0001, 0x000000ff, - 0x0012, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x042500df, - 0x0001, 0x00000000, - 0x0001, 0x00000600, - 0x0005, 0x00000000, - 0x0001, 0x01000000, - 0x0001, 0x000000ff, - 0x0001, 0x00000000, - 0x0001, 0x00000800, - 0x0005, 0x00000000, - 0x0002, 0x00000001, - 0x0001, 0x000e0080, - 0x0001, 0x00000004, - 0x0006, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00000001, - 0x0003, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0005, 0x00000000, - 0x0001, 0x00000002, - 0x0002, 0x00000001, - 0x0003, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x003fffff, - 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0x0003, 0x0001fe21, - 0x0004, 0x00000000, - 0x0001, 0x0001fe21, - 0x0028, 0x00000000, - 0x0003, 0x08100c12, - 0x0004, 0x00000000, - 0x0001, 0x08100c12, - 0x0003, 0x00000004, - 0x0004, 0x00000000, - 0x0001, 0x00000004, - 0x0008, 0x00000000, - 0x0003, 0x00000002, - 0x0004, 0x00000000, - 0x0001, 0x00000002, - 0x0003, 0x00000011, - 0x0004, 0x00000000, - 0x0001, 0x00000011, - 0x0040, 0x00000000, - 0x0003, 0x0fac6881, - 0x0004, 0x00000000, - 0x0001, 0x0fac6881, - 0x0020, 0x00000000, - 0x0003, 0x00000004, - 0x0004, 0x00000000, - 0x0001, 0x00000004, - 0x0048, 0x00000000, - 0x0003, 0x00000002, - 0x0004, 0x00000000, - 0x0001, 0x00000002, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0004, 0x00000001, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0003, 0x00000002, - 0x0004, 0x00000000, - 0x0001, 0x00000002, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0004, 0x00000001, - 0x0004, 0x00000000, - 0x0004, 0x00000001, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0008, 0x00000000, - 0x0003, 0x00000004, - 0x0004, 0x00000000, - 0x0001, 0x00000004, - 0x1d18, 0x00000000, - 0x0003, 0x00000011, - 0x0004, 0x00000000, - 0x0001, 0x00000011, - 0x0008, 0x00000000, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0171, 0x00000000, - 0x0002, 0x00000080, - 0x0006, 0x00000000, - 0x0002, 0x80007004, - 0x0006, 0x00000000, - 0x0002, 0x04000400, - 0x0006, 0x00000000, - 0x0002, 0x000000c0, - 0x0006, 0x00000000, - 0x0002, 0x00001000, - 0x0016, 0x00000000, - 0x0002, 0x00000001, - 0x0016, 0x00000000, - 0x0002, 0x00000001, - 0x000e, 0x00000000, - 0x0002, 0x00000004, - 0x0006, 0x00000000, - 0x0002, 0x00000002, - 0x006e, 0x00000000, - 0x0002, 0x00000080, - 0x0006, 0x00000000, - 0x0002, 0x80007004, - 0x0006, 0x00000000, - 0x0002, 0x04000400, - 0x0006, 0x00000000, - 0x0002, 0x000000c0, - 0x0006, 0x00000000, - 0x0002, 0x00001000, - 0x0016, 0x00000000, - 0x0002, 0x00000001, - 0x0016, 0x00000000, - 0x0002, 0x00000001, - 0x000e, 0x00000000, - 0x0002, 0x00000004, - 0x0006, 0x00000000, - 0x0002, 0x00000002, - 0x006e, 0x00000000, - 0x0002, 0x00000080, - 0x0006, 0x00000000, - 0x0002, 0x80007004, - 0x0006, 0x00000000, - 0x0002, 0x04000400, - 0x0006, 0x00000000, - 0x0002, 0x000000c0, - 0x0006, 0x00000000, - 0x0002, 0x00001000, - 0x0016, 0x00000000, - 0x0002, 0x00000001, - 0x0016, 0x00000000, - 0x0002, 0x00000001, - 0x000e, 0x00000000, - 0x0002, 0x00000004, - 0x0006, 0x00000000, - 0x0002, 0x00000002, - 0x0066, 0x00000000, - 0x0002, 0x08100c12, - 0x000e, 0x00000000, - 0x0002, 0x0001fe21, - 0x002e, 0x00000000, - 0x0002, 0x0000ffff, - 0x0006, 0x00000000, - 0x0002, 0x0000ffff, - 0x0006, 0x00000000, - 0x0002, 0x0000ffff, - 0x0006, 0x00000000, - 0x0002, 0x0000ffff, - 0x0006, 0x00000000, - 0x0002, 0x00000001, - 0x0006, 0x00000000, - 0x0002, 0x00010001, - 0x0006, 0x00000000, - 0x0002, 0x00010001, - 0x0006, 0x00000000, - 0x0002, 0x00000001, - 0x000e, 0x00000000, - 0x0002, 0x0001fe21, - 0x002e, 0x00000000, - 0x0002, 0x08100c12, - 0x0006, 0x00000000, - 0x0002, 0x00000004, - 0x000e, 0x00000000, - 0x0002, 0x00000002, - 0x0006, 0x00000000, - 0x0002, 0x00000011, - 0x0046, 0x00000000, - 0x0002, 0x0fac6881, - 0x0026, 0x00000000, - 0x0002, 0x00000004, - 0x004e, 0x00000000, - 0x0002, 0x00000002, - 0x0006, 0x00000000, - 0x0002, 0x00000001, - 0x0006, 0x00000000, - 0x0002, 0x00000001, - 0x0006, 0x00000000, - 0x0002, 0x00000002, - 0x0006, 0x00000000, - 0x0002, 0x00000001, - 0x0006, 0x00000000, - 0x0002, 0x00000001, - 0x0006, 0x00000000, - 0x0002, 0x00000001, - 0x000e, 0x00000000, - 0x0002, 0x00000004, - 0x1d1e, 0x00000000, - 0x0002, 0x00000011, - 0x000e, 0x00000000, - 0x0002, 0x00000001, - 0x0000 -}; - -static uint32_t nvaa_ctxprog[] = { - 0x0070009c, 0x00300000, 0x0044f109, 0x00402d09, 0x0040e551, 0x00400a44, - 0x00400a05, 0x00400a0d, 0x0070008e, 0x0040124d, 0x0070009d, 0x0045004d, - 0x00700097, 0x00450121, 0x004446a1, 0x0044764d, 0x0044824d, 0x0070001d, - 0x00401806, 0x00600005, 0x00444445, 0x0044308b, 0x00401845, 0x0040234d, - 0x00700081, 0x00401ccf, 0x0070009f, 0x0050009f, 0x0044dc4d, 0x00700017, - 0x0040230b, 0x00447d4d, 0x00450221, 0x004456a1, 0x007000a0, 0x00700001, - 0x00700003, 0x00402706, 0x00402805, 0x0060000d, 0x00700005, 0x0070000d, - 0x00700006, 0x00700002, 0x0070000b, 0x0070000e, 0x0070001c, 0x0060000c, - 0x00000000, 0x0090ffff, 0x0091ffff, 0x0044d44d, 0x00600009, 0x0048004d, - 0x00700096, 0x00403acf, 0x0070009f, 0x0050009f, 0x0040e551, 0x004036c0, - 0x00200080, 0x00600008, 0x0040364f, 0x004036c0, 0x00403ecc, 0x00403651, - 0x00700016, 0x0048004d, 0x00600011, 0x0048004d, 0x0044364d, 0x0070008e, - 0x00700081, 0x0044704d, 0x00447d4d, 0x00700083, 0x00300000, 0x00212740, - 0x00600007, 0x00c00b01, 0x00200022, 0x00800001, 0x005000cb, 0x00c000ff, - 0x00445e4d, 0x0048004d, 0x0044ce08, 0x0044734d, 0x00448b4d, 0x00445e4d, - 0x0044e24d, 0x0044764d, 0x0044824d, 0x0048004d, 0x00700083, 0x0045034d, - 0x00a0023f, 0x00200040, 0x00600006, 0x0044fc4d, 0x00448d4d, 0x002001d0, - 0x0044b860, 0x00200280, 0x0038ffff, 0x0044cc4d, 0x00300000, 0x005000cb, - 0x00451c4d, 0x005000cb, 0x0044d007, 0x0048004d, 0x0044794d, 0x00111bfc, - 0x0048004d, 0x0044794d, 0x00111bfd, 0x0048004d, 0x0044794d, 0x00111bfe, - 0x0048004d, 0x00200000, 0x00700000, 0x00600006, 0x0048004d, 0x00200001, - 0x00600006, 0x0044fc4d, 0x0011020a, 0x0048004d, 0x00300000, 0x00c3ffff, - 0x00200000, 0x00600007, 0x00700000, 0x00200008, 0x008000ff, 0x005000cb, - 0x0048004d, 0x00000000, 0x0048004d, 0x00000000, 0x00170202, 0x00200032, - 0x0010020d, 0x001e0242, 0x001102c0, 0x00120302, 0x00150402, 0x00180500, - 0x00130509, 0x00150550, 0x00110605, 0x00200013, 0x00100607, 0x00110700, - 0x00110900, 0x00120902, 0x00110a00, 0x00160b02, 0x00120b28, 0x00140b2b, - 0x00110c01, 0x00110d01, 0x00111400, 0x00111405, 0x00111407, 0x00111409, - 0x0011140b, 0x002000d4, 0x00101500, 0x00141a05, 0x00131a0c, 0x00131c00, - 0x00131c04, 0x00141c20, 0x00131c25, 0x00131f00, 0x00131f04, 0x00111f08, - 0x00111f0b, 0x00200015, 0x00101f40, 0x0048004d, 0x00600006, 0x00451c4d, - 0x00112020, 0x00112022, 0x00200085, 0x00102040, 0x001120c8, 0x001420ca, - 0x001b20cf, 0x00122100, 0x00122103, 0x00162140, 0x00122147, 0x00122153, - 0x001121a0, 0x001221c0, 0x001121cb, 0x001121d4, 0x001521d8, 0x0048004d, - 0x00000000, 0x0048004d, 0x0060000b, 0x0048004d, 0x0060000a, 0x0048004d, - 0x0060000b, 0x0040d24d, 0x00200020, 0x00600008, 0x0050004c, 0x0048004d, - 0x002003e8, 0x00600008, 0x0050004c, 0x0048004d, 0x00600004, 0x0050004a, - 0x0048004d, 0x00c000ff, 0x00c800ff, 0x0048004d, 0x00c000ff, 0x00c800ff, - 0x0048004d, 0x00700016, 0x0070008e, 0x00700082, 0x00500041, 0x0044d84d, - 0x00700095, 0x005000d1, 0x00600016, 0x00500052, 0x00700002, 0x00700015, - 0x0040284d, 0x0070008e, 0x0044d44d, 0x00200000, 0x00600007, 0x00300000, - 0x00c000ff, 0x00200000, 0x008000ff, 0x00700009, 0x0070000e, 0x0048004d, - 0x00700080, 0x00480017, 0x00700000, 0x0048004d, 0x0048004d, 0x0048004d, - 0x0048004d, 0x0070008e, 0x0044d44d, 0x00700083, 0x0044df4d, 0x00450c4d, - 0x0070000f, 0x00410b8c, 0x005000cb, 0x0048004d, 0x00200280, 0x00600007, - 0x00452307, 0x00451187, 0x0048004d, 0x00000000, 0x00202070, 0x0044fc4d, - 0x008000ff, 0x0048004d, 0x00210600, 0x00600007, 0x00200428, 0x0044fc4d, - 0x008800ff, 0x0048004d, 0x0048000f, 0x0048004b, 0x0045164d, 0x0070008f, - 0x0048008c, 0x005000cb, 0x0048004d, 0x00202070, 0x0044fc4d, 0x008000fd, - 0x005000cb, 0x00c00002, 0x00200280, 0x00600007, 0x00200161, 0x0044fc4d, - 0x00800002, 0x005000cb, 0x00c00002, 0x00201f0e, 0x0044fc4d, 0x00800002, - 0x005000cb, 0x0048004d, ~0 -}; - -static uint32_t nvaa_ctxvals[] = { - 0x0043, 0x00000000, - 0x0001, 0x00000030, - 0x0007, 0x00000000, - 0x0001, 0x00000002, - 0x0028, 0x00000000, - 0x0001, 0x00000003, - 0x0001, 0x00001000, - 0x0012, 0x00000000, - 0x0001, 0x0000fe0c, - 0x0005, 0x00000000, - 0x0001, 0x00001000, - 0x000a, 0x00000000, - 0x0001, 0x00000187, - 0x0004, 0x00000000, - 0x0001, 0x00001018, - 0x0001, 0x000000ff, - 0x0012, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x042500df, - 0x0001, 0x00000000, - 0x0001, 0x00000600, - 0x0005, 0x00000000, - 0x0001, 0x01000000, - 0x0001, 0x000000ff, - 0x0001, 0x00000000, - 0x0001, 0x00000800, - 0x0005, 0x00000000, - 0x0001, 0x00000004, - 0x0009, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00000001, - 0x0003, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0005, 0x00000000, - 0x0001, 0x00000002, - 0x0002, 0x00000001, - 0x0003, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x003fffff, - 0x0001, 0x00001fff, - 0x0001, 0x00000000, - 0x0002, 0x00000001, - 0x0001, 0x00000000, - 0x0001, 0x00000007, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0008, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000100, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000100, - 0x0004, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x00000070, - 0x0001, 0x00000080, - 0x0004, 0x00000000, - 0x0001, 0x0000000c, - 0x0001, 0x00000000, - 0x0001, 0x00000008, - 0x0001, 0x00000014, - 0x0001, 0x00000000, - 0x0001, 0x00000027, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0017, 0x00000000, - 0x0001, 0x000000cf, - 0x000b, 0x00000000, - 0x0001, 0x00000001, - 0x0006, 0x00000000, - 0x0001, 0x00000001, - 0x0006, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x00000002, - 0x0001, 0x00000004, - 0x0003, 0x00000000, - 0x0001, 0x003fffff, - 0x0001, 0x00001fff, - 0x0009, 0x00000000, - 0x0002, 0x00000001, - 0x0001, 0x00000002, - 0x0001, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x00000014, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000002, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000000, - 0x0001, 0x00001e00, - 0x0005, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00000200, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x000000f0, - 0x0001, 0x000000ff, - 0x0002, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x000000f0, - 0x0001, 0x000000ff, - 0x0001, 0x00000000, - 0x0001, 0x00000009, - 0x0002, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x000000cf, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0003, 0x00000000, - 0x0001, 0x000000cf, - 0x0001, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000000, - 0x0002, 0x000000cf, - 0x0001, 0x00000001, - 0x0001, 0x00000000, - 0x0001, 0x00001f80, - 0x0005, 0x00000000, - 0x0001, 0x3b74f821, - 0x0001, 0x89058001, - 0x0001, 0x00000000, - 0x0001, 0x00001000, - 0x0001, 0x000000ff, - 0x0001, 0x00000000, - 0x0001, 0x027c10fa, - 0x0001, 0x400000c0, - 0x0001, 0xb7892080, - 0x0004, 0x00000000, - 0x0001, 0x003d0040, - 0x0001, 0x00000000, - 0x0001, 0x00000022, - 0x0007, 0x00000000, - 0x0001, 0x003d0040, - 0x0001, 0x00000022, - 0x0011, 0x00000000, - 0x0001, 0x0000ff0a, - 0x0001, 0x00000000, - 0x0001, 0x01800000, - 0x0001, 0x00160000, - 0x0001, 0x01800000, - 0x0003, 0x00000000, - 0x0001, 0x0003ffff, - 0x0001, 0x300c0000, - 0x0008, 0x00000000, - 0x0001, 0x00010401, - 0x0001, 0x00000000, - 0x0001, 0x00000078, - 0x0001, 0x00000000, - 0x0001, 0x000000bf, - 0x0001, 0x00000000, - 0x0001, 0x00001210, - 0x0001, 0x08000080, - 0x0002, 0x00000000, - 0x0001, 0x0000003e, - 0x0005, 0x00000000, - 0x0001, 0x01800000, - 0x0001, 0x00160000, - 0x0001, 0x01800000, - 0x0003, 0x00000000, - 0x0001, 0x0003ffff, - 0x0001, 0x300c0000, - 0x0008, 0x00000000, - 0x0001, 0x00010401, - 0x0001, 0x00000000, - 0x0001, 0x00000078, - 0x0001, 0x00000000, - 0x0001, 0x000000bf, - 0x0001, 0x00000000, - 0x0001, 0x00001210, - 0x0001, 0x08000080, - 0x0002, 0x00000000, - 0x0001, 0x0000003e, - 0x0005, 0x00000000, - 0x0001, 0x01800000, - 0x0001, 0x00160000, - 0x0001, 0x01800000, - 0x0003, 0x00000000, - 0x0001, 0x0003ffff, - 0x0001, 0x300c0000, - 0x0008, 0x00000000, - 0x0001, 0x00010401, - 0x0001, 0x00000000, - 0x0001, 0x00000078, - 0x0001, 0x00000000, - 0x0001, 0x000000bf, - 0x0001, 0x00000000, - 0x0001, 0x00001210, - 0x0001, 0x08000080, - 0x0002, 0x00000000, - 0x0001, 0x0000003e, - 0x0005, 0x00000000, - 0x0001, 0x01800000, - 0x0001, 0x00160000, - 0x0001, 0x01800000, - 0x0003, 0x00000000, - 0x0001, 0x0003ffff, - 0x0001, 0x300c0000, - 0x0008, 0x00000000, - 0x0001, 0x00010401, - 0x0001, 0x00000000, - 0x0001, 0x00000078, - 0x0001, 0x00000000, - 0x0001, 0x000000bf, - 0x0001, 0x00000000, - 0x0001, 0x00001210, - 0x0001, 0x08000080, - 0x0002, 0x00000000, - 0x0001, 0x0000003e, - 0x0006, 0x00000000, - 0x0001, 0x01127070, - 0x0003, 0x00000000, - 0x0001, 0x07ffffff, - 0x0006, 0x00000000, - 0x0001, 0x00030201, - 0x0009, 0x00000000, - 0x0001, 0x00008000, - 0x0007, 0x00000000, - 0x0001, 0x02bf7fff, - 0x0010, 0x00000000, - 0x0001, 0x00000004, - 0x0004, 0x00000000, - 0x0001, 0x0000003f, - 0x0002, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000000, - 0x0001, 0x0fac6881, - 0x000b, 0x00000000, - 0x0001, 0x00000080, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00080c14, - 0x0005, 0x00000000, - 0x0001, 0x00080c14, - 0x0003, 0x00000000, - 0x0001, 0x0000000f, - 0x0005, 0x00000000, - 0x0001, 0x000007ff, - 0x000d, 0x00000000, - 0x0001, 0x00000804, - 0x000f, 0x00000000, - 0x0001, 0x00000004, - 0x0003, 0x00000000, - 0x0001, 0x00000020, - 0x0002, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00000004, - 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0x0001, 0x00000102, - 0x000f, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0047, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x000f, 0x00000000, - 0x0001, 0x000007ff, - 0x000f, 0x00000000, - 0x0001, 0x00000102, - 0x004f, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x6ee1, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x08100c12, - 0x0007, 0x00000000, - 0x0001, 0x00000003, - 0x000f, 0x00000000, - 0x0001, 0x08100c12, - 0x000f, 0x00000000, - 0x0001, 0x00080c14, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00080c14, - 0x0017, 0x00000000, - 0x0001, 0x08100c12, - 0x0007, 0x00000000, - 0x0001, 0x00000027, - 0x0017, 0x00000000, - 0x0001, 0x00000001, - 0x1e0f, 0x00000000, - 0x0001, 0x00000001, - 0x00b7, 0x00000000, - 0x0001, 0x08100c12, - 0x000d, 0x00000000, - 0x0001, 0x08100c12, - 0x000f, 0x00000000, - 0x0001, 0x00000080, - 0x0007, 0x00000000, - 0x0001, 0x80007004, - 0x0007, 0x00000000, - 0x0001, 0x04000400, - 0x0007, 0x00000000, - 0x0001, 0x000000c0, - 0x0007, 0x00000000, - 0x0001, 0x00001000, - 0x0017, 0x00000000, - 0x0001, 0x00000e00, - 0x0007, 0x00000000, - 0x0001, 0x00001e00, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0017, 0x00000000, - 0x0001, 0x00000001, - 0x000f, 0x00000000, - 0x0001, 0x00000004, - 0x0007, 0x00000000, - 0x0001, 0x00000002, - 0x005f, 0x00000000, - 0x0001, 0x08100c12, - 0x000f, 0x00000000, - 0x0001, 0x0001fe21, - 0x002f, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00010001, - 0x0007, 0x00000000, - 0x0001, 0x00010001, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x000f, 0x00000000, - 0x0001, 0x0001fe21, - 0x002f, 0x00000000, - 0x0001, 0x08100c12, - 0x0007, 0x00000000, - 0x0001, 0x00000004, - 0x000f, 0x00000000, - 0x0001, 0x00000002, - 0x0007, 0x00000000, - 0x0001, 0x00000011, - 0x0047, 0x00000000, - 0x0001, 0x0fac6881, - 0x0027, 0x00000000, - 0x0001, 0x00000004, - 0x004f, 0x00000000, - 0x0001, 0x00000002, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00000002, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x000f, 0x00000000, - 0x0001, 0x00000004, - 0x1cff, 0x00000000, - 0x0001, 0x00000011, - 0x000f, 0x00000000, - 0x0001, 0x00000001, - 0x0000 -}; - -static uint32_t nv94_ctxprog[] = { - 0x0070008e, 0x0070009c, 0x00200020, 0x00600008, 0x0050004c, 0x00400e89, - 0x00200000, 0x00600007, 0x00300000, 0x00c000ff, 0x00200000, 0x008000ff, - 0x00700009, 0x0041324d, 0x00402944, 0x00402905, 0x0040290d, 0x00410e06, - 0x00600005, 0x004015c5, 0x00600011, 0x0040270b, 0x004021c5, 0x00700000, - 0x00700081, 0x00600004, 0x0050004a, 0x00219440, 0x00600007, 0x00c02701, - 0x0020002e, 0x00800001, 0x005000cb, 0x0090ffff, 0x0091ffff, 0x00200020, - 0x00600008, 0x0050004c, 0x00600009, 0x00410e45, 0x0041294d, 0x0070009d, - 0x00402dcf, 0x0070009f, 0x0050009f, 0x00402ac0, 0x00200080, 0x00600008, - 0x00402a4f, 0x00402ac0, 0x004030cc, 0x00700081, 0x00200000, 0x00600006, - 0x00700000, 0x00111bfc, 0x00700083, 0x00300000, 0x00219440, 0x00600007, - 0x00c00a01, 0x0020001e, 0x00800001, 0x005000cb, 0x00c000ff, 0x00700080, - 0x00700083, 0x00200047, 0x00600006, 0x0011020a, 0x00200380, 0x00600007, - 0x00300000, 0x00c000ff, 0x00c800ff, 0x00411907, 0x00202dd2, 0x008000ff, - 0x0040508c, 0x005000cb, 0x00a0023f, 0x00200040, 0x00600006, 0x0070000f, - 0x00170202, 0x0011020a, 0x00200032, 0x0010020d, 0x001c0242, 0x00120302, - 0x00140402, 0x00180500, 0x00130509, 0x00150550, 0x00110605, 0x0020000f, - 0x00100607, 0x00110700, 0x00110900, 0x00120902, 0x00110a00, 0x00160b02, - 0x00120b28, 0x00140b2b, 0x00110c01, 0x00111400, 0x00111405, 0x00111407, - 0x00111409, 0x0011140b, 0x002000cc, 0x00101500, 0x0040790f, 0x0040794b, - 0x00217240, 0x00600007, 0x0020043f, 0x008800ff, 0x0070008f, 0x0040798c, - 0x005000cb, 0x00000000, 0x00141a05, 0x00131a0c, 0x00131c00, 0x00121c04, - 0x00141c20, 0x00111c25, 0x00131c40, 0x00121c44, 0x00141c60, 0x00111c65, - 0x00131c80, 0x00121c84, 0x00141ca0, 0x00111ca5, 0x00131cc0, 0x00121cc4, - 0x00141ce0, 0x00111ce5, 0x00131f00, 0x00191f40, 0x0040a1e0, 0x002001ca, - 0x00600006, 0x00200044, 0x00102080, 0x001120c6, 0x001520c9, 0x001920d0, - 0x00122100, 0x00122103, 0x00162200, 0x00122207, 0x00112280, 0x00112300, - 0x00112302, 0x00122380, 0x0011238b, 0x00112394, 0x0011239c, 0x0040bee1, - 0x00200231, 0x00600006, 0x00200044, 0x00102480, 0x0040af0f, 0x0040af4b, - 0x00217240, 0x00600007, 0x0020043f, 0x008800ff, 0x0070008f, 0x0040af8c, - 0x005000cb, 0x00000000, 0x001124c6, 0x001524c9, 0x001924d0, 0x00122500, - 0x00122503, 0x00162600, 0x00122607, 0x00112680, 0x00112700, 0x00112702, - 0x00122780, 0x0011278b, 0x00112794, 0x0011279c, 0x0040d1e2, 0x00200298, - 0x00600006, 0x00200044, 0x00102880, 0x001128c6, 0x001528c9, 0x001928d0, - 0x00122900, 0x00122903, 0x00162a00, 0x00122a07, 0x00112a80, 0x00112b00, - 0x00112b02, 0x00122b80, 0x00112b8b, 0x00112b94, 0x00112b9c, 0x0040eee3, - 0x002002ff, 0x00600006, 0x00200044, 0x00102c80, 0x0040df0f, 0x0040df4b, - 0x00217240, 0x00600007, 0x0020043f, 0x008800ff, 0x0070008f, 0x0040df8c, - 0x005000cb, 0x00000000, 0x00112cc6, 0x00152cc9, 0x00192cd0, 0x00122d00, - 0x00122d03, 0x00162e00, 0x00122e07, 0x00112e80, 0x00112f00, 0x00112f02, - 0x00122f80, 0x00112f8b, 0x00112f94, 0x00112f9c, 0x00000000, 0x0040f50f, - 0x005000cb, 0x00217240, 0x00600007, 0x0020043f, 0x008800ff, 0x005000cb, - 0x0040f887, 0x0060000a, 0x00000000, 0x00410700, 0x007000a0, 0x00700080, - 0x00200380, 0x00600007, 0x00200004, 0x00c000ff, 0x008000ff, 0x005000cb, - 0x00700000, 0x00200000, 0x00600006, 0x00111bfe, 0x0041294d, 0x00700000, - 0x00200000, 0x00600006, 0x00111bfe, 0x00700080, 0x0070001d, 0x0040114d, - 0x00700081, 0x00600004, 0x0050004a, 0x00411388, 0x0060000b, 0x00200000, - 0x00600006, 0x00700000, 0x0041290b, 0x00111bfd, 0x0040424d, 0x00202dd2, - 0x008000fd, 0x005000cb, 0x00c00002, 0x00200380, 0x00600007, 0x00200160, - 0x00800002, 0x005000cb, 0x00c01802, 0x00202c72, 0x00800002, 0x005000cb, - 0x00404e4d, 0x0060000b, 0x0041274d, 0x00700001, 0x00700003, 0x00412d06, - 0x00412e05, 0x0060000d, 0x00700005, 0x0070000d, 0x00700006, 0x0070000b, - 0x0070000e, 0x0070001c, 0x0060000c, ~0 -}; - -static unsigned nv94_ctxvals[] = { - 0x0043, 0x00000000, - 0x0001, 0x00000030, - 0x0008, 0x00000000, - 0x0001, 0x00000002, - 0x0028, 0x00000000, - 0x0001, 0x00000003, - 0x0001, 0x00001000, - 0x000f, 0x00000000, - 0x0001, 0x0000fe0c, - 0x0004, 0x00000000, - 0x0001, 0x00001000, - 0x000a, 0x00000000, - 0x0001, 0x00000187, - 0x0004, 0x00000000, - 0x0001, 0x00001018, - 0x0001, 0x000000ff, - 0x000e, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x044d00df, - 0x0001, 0x00000000, - 0x0001, 0x00000600, - 0x0005, 0x00000000, - 0x0001, 0x01000000, - 0x0001, 0x000000ff, - 0x0001, 0x00000000, - 0x0001, 0x00000400, - 0x0005, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000080, - 0x0001, 0x00000004, - 0x0006, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00000001, - 0x0003, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0005, 0x00000000, - 0x0001, 0x00000002, - 0x0002, 0x00000001, - 0x0003, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x003fffff, - 0x0001, 0x00001fff, - 0x0001, 0x00000000, - 0x0002, 0x00000001, - 0x0001, 0x00000000, - 0x0003, 0x00000001, - 0x0001, 0x00000004, - 0x0003, 0x00000001, - 0x0001, 0x00000007, - 0x0001, 0x00000001, - 0x0001, 0x00000007, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000100, - 0x0001, 0x00000001, - 0x0001, 0x00000100, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000100, - 0x0004, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x00000070, - 0x0001, 0x00000080, - 0x0004, 0x00000000, - 0x0001, 0x0000000c, - 0x0001, 0x00000000, - 0x0001, 0x00000008, - 0x0001, 0x00000014, - 0x0001, 0x00000000, - 0x0001, 0x00000029, - 0x0001, 0x00000027, - 0x0001, 0x00000026, - 0x0001, 0x00000008, - 0x0001, 0x00000004, - 0x0001, 0x00000027, - 0x0002, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000002, - 0x0001, 0x00000003, - 0x0001, 0x00000004, - 0x0001, 0x00000005, - 0x0001, 0x00000006, - 0x0001, 0x00000007, - 0x0001, 0x00000001, - 0x0010, 0x00000000, - 0x0001, 0x000000cf, - 0x000b, 0x00000000, - 0x0001, 0x00000080, - 0x0002, 0x00000004, - 0x0001, 0x00000003, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000012, - 0x0001, 0x00000010, - 0x0001, 0x0000000c, - 0x0001, 0x00000001, - 0x0003, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x00000002, - 0x0001, 0x00000004, - 0x0002, 0x00000000, - 0x0001, 0x003fffff, - 0x0001, 0x00001fff, - 0x0009, 0x00000000, - 0x0001, 0x00000004, - 0x0001, 0x00000014, - 0x0001, 0x00000001, - 0x0002, 0x00000000, - 0x0001, 0x00000002, - 0x0002, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00001000, - 0x0001, 0x00000e00, - 0x0001, 0x00001000, - 0x0001, 0x00001e00, - 0x0001, 0x00000000, - 0x0005, 0x00000001, - 0x0003, 0x00000000, - 0x0001, 0x00000200, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000070, - 0x0001, 0x00000080, - 0x0002, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000070, - 0x0001, 0x00000080, - 0x0003, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x000000cf, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0003, 0x00000000, - 0x0001, 0x000000cf, - 0x0001, 0x00000000, - 0x0001, 0x00000002, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000000, - 0x0001, 0x00000001, - 0x0001, 0x00000000, - 0x0002, 0x000000cf, - 0x0001, 0x00000001, - 0x0001, 0x00000000, - 0x0001, 0x00001f80, - 0x0005, 0x00000000, - 0x0001, 0x3b74f821, - 0x0001, 0x89058001, - 0x0001, 0x00000000, - 0x0001, 0x00001000, - 0x0001, 0x0000001f, - 0x0001, 0x027c10fa, - 0x0001, 0x400000c0, - 0x0001, 0xb7892080, - 0x0002, 0x00000000, - 0x0001, 0x3b74f821, - 0x0001, 0x89058001, - 0x0001, 0x00000000, - 0x0001, 0x00001000, - 0x0001, 0x0000001f, - 0x0001, 0x027c10fa, - 0x0001, 0x400000c0, - 0x0001, 0xb7892080, - 0x0002, 0x00000000, - 0x0001, 0x3b74f821, - 0x0001, 0x89058001, - 0x0001, 0x00000000, - 0x0001, 0x00001000, - 0x0001, 0x0000001f, - 0x0001, 0x027c10fa, - 0x0001, 0x400000c0, - 0x0001, 0xb7892080, - 0x0002, 0x00000000, - 0x0001, 0x3b74f821, - 0x0001, 0x89058001, - 0x0001, 0x00000000, - 0x0001, 0x00001000, - 0x0001, 0x0000001f, - 0x0001, 0x027c10fa, - 0x0001, 0x400000c0, - 0x0001, 0xb7892080, - 0x0002, 0x00000000, - 0x0001, 0x00390040, - 0x0001, 0x00000000, - 0x0001, 0x00000022, - 0x0002, 0x00000000, - 0x0001, 0x00390040, - 0x0001, 0x00000022, - 0x0005, 0x00000000, - 0x0001, 0x01800000, - 0x0001, 0x00160000, - 0x0001, 0x01800000, - 0x0003, 0x00000000, - 0x0001, 0x0003ffff, - 0x0001, 0x10880000, - 0x0008, 0x00000000, - 0x0001, 0x00010401, - 0x0001, 0x00000000, - 0x0001, 0x00000078, - 0x0001, 0x00000000, - 0x0001, 0x000000bf, - 0x0001, 0x00000000, - 0x0001, 0x00001210, - 0x0001, 0x08000080, - 0x0008, 0x00000000, - 0x0001, 0x01800000, - 0x0001, 0x00160000, - 0x0001, 0x01800000, - 0x0003, 0x00000000, - 0x0001, 0x0003ffff, - 0x0001, 0x10880000, - 0x0008, 0x00000000, - 0x0001, 0x00010401, - 0x0001, 0x00000000, - 0x0001, 0x00000078, - 0x0001, 0x00000000, - 0x0001, 0x000000bf, - 0x0001, 0x00000000, - 0x0001, 0x00001210, - 0x0001, 0x08000080, - 0x0009, 0x00000000, - 0x0001, 0x00027070, - 0x0002, 0x00000000, - 0x0001, 0x03ffffff, - 0x0005, 0x00000000, - 0x0001, 0x00120407, - 0x0001, 0x05091507, - 0x0001, 0x05010202, - 0x0001, 0x00030201, - 0x0006, 0x00000000, - 0x0001, 0x00000040, - 0x0001, 0x0d0c0b0a, - 0x0001, 0x00141210, - 0x0001, 0x000001f0, - 0x0001, 0x00000001, - 0x0001, 0x00000003, - 0x0002, 0x00000000, - 0x0001, 0x00039e00, - 0x0001, 0x00000100, - 0x0001, 0x00003800, - 0x0001, 0x00404040, - 0x0001, 0x0000ff0a, - 0x0001, 0x00000000, - 0x0001, 0x0077f005, - 0x0001, 0x003f7fff, - 0x0003, 0x00000000, - 0x0001, 0x01800000, - 0x0001, 0x00160000, - 0x0001, 0x01800000, - 0x0003, 0x00000000, - 0x0001, 0x0003ffff, - 0x0001, 0x10880000, - 0x0008, 0x00000000, - 0x0001, 0x00010401, - 0x0001, 0x00000000, - 0x0001, 0x00000078, - 0x0001, 0x00000000, - 0x0001, 0x000000bf, - 0x0001, 0x00000000, - 0x0001, 0x00001210, - 0x0001, 0x08000080, - 0x0008, 0x00000000, - 0x0001, 0x01800000, - 0x0001, 0x00160000, - 0x0001, 0x01800000, - 0x0003, 0x00000000, - 0x0001, 0x0003ffff, - 0x0001, 0x10880000, - 0x0008, 0x00000000, - 0x0001, 0x00010401, - 0x0001, 0x00000000, - 0x0001, 0x00000078, - 0x0001, 0x00000000, - 0x0001, 0x000000bf, - 0x0001, 0x00000000, - 0x0001, 0x00001210, - 0x0001, 0x08000080, - 0x0009, 0x00000000, - 0x0001, 0x00027070, - 0x0002, 0x00000000, - 0x0001, 0x03ffffff, - 0x0005, 0x00000000, - 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0x0007, 0x00000000, - 0x0001, 0x08100c12, - 0x0007, 0x00000000, - 0x0001, 0x00000003, - 0x000f, 0x00000000, - 0x0001, 0x08100c12, - 0x000f, 0x00000000, - 0x0001, 0x00080c14, - 0x0007, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00080c14, - 0x0017, 0x00000000, - 0x0001, 0x08100c12, - 0x0007, 0x00000000, - 0x0001, 0x00000027, - 0x0017, 0x00000000, - 0x0001, 0x00000001, - 0x1e0f, 0x00000000, - 0x0001, 0x00000001, - 0x00b7, 0x00000000, - 0x0001, 0x08100c12, - 0x0067, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x000f, 0x00000000, - 0x0001, 0x00000080, - 0x001f, 0x00000000, - 0x0001, 0x00000080, - 0x000f, 0x00000000, - 0x0001, 0x0000003f, - 0x0057, 0x00000000, - 0x0001, 0x00000002, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0007, 0x00000000, - 0x0001, 0x04000000, - 0x0047, 0x00000000, - 0x0001, 0x00000004, - 0x001f, 0x00000000, - 0x0001, 0x00000004, - 0x008f, 0x00000000, - 0x0001, 0x00000001, - 0x0007, 0x00000000, - 0x0001, 0x00001001, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0007, 0x00000000, - 0x0001, 0x0000ffff, - 0x0107, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x3f800000, - 0x0007, 0x00000000, - 0x0001, 0x00000010, - 0x0017, 0x00000000, - 0x0001, 0x00000003, - 0x0047, 0x00000000, - 0x0001, 0x08100c12, - 0x0008, 0x00000000, - 0x0003, 0x00000080, - 0x0004, 0x00000000, - 0x0001, 0x00000080, - 0x0003, 0x80007004, - 0x0004, 0x00000000, - 0x0001, 0x80007004, - 0x0003, 0x04000400, - 0x0004, 0x00000000, - 0x0001, 0x04000400, - 0x0003, 0x00001000, - 0x0004, 0x00000000, - 0x0001, 0x00001000, - 0x0010, 0x00000000, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0010, 0x00000000, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0008, 0x00000000, - 0x0003, 0x00000004, - 0x0004, 0x00000000, - 0x0001, 0x00000004, - 0x0003, 0x00000002, - 0x0004, 0x00000000, - 0x0001, 0x00000002, - 0x0058, 0x00000000, - 0x0003, 0x00000080, - 0x0004, 0x00000000, - 0x0001, 0x00000080, - 0x0003, 0x80007004, - 0x0004, 0x00000000, - 0x0001, 0x80007004, - 0x0003, 0x04000400, - 0x0004, 0x00000000, - 0x0001, 0x04000400, - 0x0003, 0x00001000, - 0x0004, 0x00000000, - 0x0001, 0x00001000, - 0x0010, 0x00000000, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0010, 0x00000000, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0008, 0x00000000, - 0x0003, 0x00000004, - 0x0004, 0x00000000, - 0x0001, 0x00000004, - 0x0003, 0x00000002, - 0x0004, 0x00000000, - 0x0001, 0x00000002, - 0x0050, 0x00000000, - 0x0003, 0x08100c12, - 0x0004, 0x00000000, - 0x0001, 0x08100c12, - 0x0030, 0x00000000, - 0x0003, 0x0000ffff, - 0x0004, 0x00000000, - 0x0004, 0x0000ffff, - 0x0004, 0x00000000, - 0x0004, 0x0000ffff, - 0x0004, 0x00000000, - 0x0004, 0x0000ffff, - 0x0004, 0x00000000, - 0x0001, 0x0000ffff, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0003, 0x00010001, - 0x0004, 0x00000000, - 0x0004, 0x00010001, - 0x0004, 0x00000000, - 0x0001, 0x00010001, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0008, 0x00000000, - 0x0003, 0x0001fe21, - 0x0004, 0x00000000, - 0x0001, 0x0001fe21, - 0x0028, 0x00000000, - 0x0003, 0x08100c12, - 0x0004, 0x00000000, - 0x0001, 0x08100c12, - 0x0003, 0x00000004, - 0x0004, 0x00000000, - 0x0001, 0x00000004, - 0x0008, 0x00000000, - 0x0003, 0x00000002, - 0x0004, 0x00000000, - 0x0001, 0x00000002, - 0x0003, 0x00000011, - 0x0004, 0x00000000, - 0x0001, 0x00000011, - 0x0040, 0x00000000, - 0x0003, 0x0fac6881, - 0x0004, 0x00000000, - 0x0001, 0x0fac6881, - 0x0020, 0x00000000, - 0x0003, 0x00000004, - 0x0004, 0x00000000, - 0x0001, 0x00000004, - 0x0048, 0x00000000, - 0x0003, 0x00000002, - 0x0004, 0x00000000, - 0x0001, 0x00000002, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0004, 0x00000001, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0003, 0x00000002, - 0x0004, 0x00000000, - 0x0001, 0x00000002, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0004, 0x00000001, - 0x0004, 0x00000000, - 0x0004, 0x00000001, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0008, 0x00000000, - 0x0003, 0x00000004, - 0x0004, 0x00000000, - 0x0001, 0x00000004, - 0x1d18, 0x00000000, - 0x0003, 0x00000011, - 0x0004, 0x00000000, - 0x0001, 0x00000011, - 0x0008, 0x00000000, - 0x0003, 0x00000001, - 0x0004, 0x00000000, - 0x0001, 0x00000001, - 0x0000 -}; - -#endif diff --git a/shared-core/nv50_instmem.c b/shared-core/nv50_instmem.c deleted file mode 100644 index d76ebf38..00000000 --- a/shared-core/nv50_instmem.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright (C) 2007 Ben Skeggs. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" - -typedef struct { - uint32_t save1700[5]; /* 0x1700->0x1710 */ - - struct nouveau_gpuobj_ref *pramin_pt; - struct nouveau_gpuobj_ref *pramin_bar; -} nv50_instmem_priv; - -#define NV50_INSTMEM_PAGE_SHIFT 12 -#define NV50_INSTMEM_PAGE_SIZE (1 << NV50_INSTMEM_PAGE_SHIFT) -#define NV50_INSTMEM_PT_SIZE(a) (((a) >> 12) << 3) - -/*NOTE: - Assumes 0x1700 already covers the correct MiB of PRAMIN - */ -#define BAR0_WI32(g,o,v) do { \ - uint32_t offset; \ - if ((g)->im_backing) { \ - offset = (g)->im_backing->start; \ - } else { \ - offset = chan->ramin->gpuobj->im_backing->start; \ - offset += (g)->im_pramin->start; \ - } \ - offset += (o); \ - NV_WRITE(NV_RAMIN + (offset & 0xfffff), (v)); \ -} while(0) - -int -nv50_instmem_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_channel *chan; - uint32_t c_offset, c_size, c_ramfc, c_vmpd, c_base, pt_size; - nv50_instmem_priv *priv; - int ret, i; - uint32_t v; - - priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER); - if (!priv) - return -ENOMEM; - dev_priv->Engine.instmem.priv = priv; - - /* Save state, will restore at takedown. */ - for (i = 0x1700; i <= 0x1710; i+=4) - priv->save1700[(i-0x1700)/4] = NV_READ(i); - - /* Reserve the last MiB of VRAM, we should probably try to avoid - * setting up the below tables over the top of the VBIOS image at - * some point. - */ - dev_priv->ramin_rsvd_vram = 1 << 20; - c_offset = nouveau_mem_fb_amount(dev) - dev_priv->ramin_rsvd_vram; - c_size = 128 << 10; - c_vmpd = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x1400 : 0x200; - c_ramfc = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x0 : 0x20; - c_base = c_vmpd + 0x4000; - pt_size = NV50_INSTMEM_PT_SIZE(dev_priv->ramin->size); - - DRM_DEBUG(" Rsvd VRAM base: 0x%08x\n", c_offset); - DRM_DEBUG(" VBIOS image: 0x%08x\n", (NV_READ(0x619f04)&~0xff)<<8); - DRM_DEBUG(" Aperture size: %d MiB\n", - (uint32_t)dev_priv->ramin->size >> 20); - DRM_DEBUG(" PT size: %d KiB\n", pt_size >> 10); - - NV_WRITE(NV50_PUNK_BAR0_PRAMIN, (c_offset >> 16)); - - /* Create a fake channel, and use it as our "dummy" channels 0/127. - * The main reason for creating a channel is so we can use the gpuobj - * code. However, it's probably worth noting that NVIDIA also setup - * their channels 0/127 with the same values they configure here. - * So, there may be some other reason for doing this. - * - * Have to create the entire channel manually, as the real channel - * creation code assumes we have PRAMIN access, and we don't until - * we're done here. - */ - chan = drm_calloc(1, sizeof(*chan), DRM_MEM_DRIVER); - if (!chan) - return -ENOMEM; - chan->id = 0; - chan->dev = dev; - chan->file_priv = (struct drm_file *)-2; - dev_priv->fifos[0] = dev_priv->fifos[127] = chan; - - /* Channel's PRAMIN object + heap */ - if ((ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, 128<<10, 0, - NULL, &chan->ramin))) - return ret; - - if (nouveau_mem_init_heap(&chan->ramin_heap, c_base, c_size - c_base)) - return -ENOMEM; - - /* RAMFC + zero channel's PRAMIN up to start of VM pagedir */ - if ((ret = nouveau_gpuobj_new_fake(dev, c_ramfc, c_offset + c_ramfc, - 0x4000, 0, NULL, &chan->ramfc))) - return ret; - - for (i = 0; i < c_vmpd; i += 4) - BAR0_WI32(chan->ramin->gpuobj, i, 0); - - /* VM page directory */ - if ((ret = nouveau_gpuobj_new_fake(dev, c_vmpd, c_offset + c_vmpd, - 0x4000, 0, &chan->vm_pd, NULL))) - return ret; - for (i = 0; i < 0x4000; i += 8) { - BAR0_WI32(chan->vm_pd, i + 0x00, 0x00000000); - BAR0_WI32(chan->vm_pd, i + 0x04, 0x00000000); - } - - /* PRAMIN page table, cheat and map into VM at 0x0000000000. - * We map the entire fake channel into the start of the PRAMIN BAR - */ - if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pt_size, 0x1000, - 0, &priv->pramin_pt))) - return ret; - - for (i = 0, v = c_offset; i < pt_size; i+=8, v+=0x1000) { - if (v < (c_offset + c_size)) - BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v | 1); - else - BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000009); - BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000); - } - - BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63); - BAR0_WI32(chan->vm_pd, 0x04, 0x00000000); - - /* DMA object for PRAMIN BAR */ - if ((ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 6*4, 16, 0, - &priv->pramin_bar))) - return ret; - BAR0_WI32(priv->pramin_bar->gpuobj, 0x00, 0x7fc00000); - BAR0_WI32(priv->pramin_bar->gpuobj, 0x04, dev_priv->ramin->size - 1); - BAR0_WI32(priv->pramin_bar->gpuobj, 0x08, 0x00000000); - BAR0_WI32(priv->pramin_bar->gpuobj, 0x0c, 0x00000000); - BAR0_WI32(priv->pramin_bar->gpuobj, 0x10, 0x00000000); - BAR0_WI32(priv->pramin_bar->gpuobj, 0x14, 0x00000000); - - /* Poke the relevant regs, and pray it works :) */ - NV_WRITE(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12)); - NV_WRITE(NV50_PUNK_UNK1710, 0); - NV_WRITE(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) | - NV50_PUNK_BAR_CFG_BASE_VALID); - NV_WRITE(NV50_PUNK_BAR1_CTXDMA, 0); - NV_WRITE(NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) | - NV50_PUNK_BAR3_CTXDMA_VALID); - - /* Assume that praying isn't enough, check that we can re-read the - * entire fake channel back from the PRAMIN BAR */ - for (i = 0; i < c_size; i+=4) { - if (NV_READ(NV_RAMIN + i) != NV_RI32(i)) { - DRM_ERROR("Error reading back PRAMIN at 0x%08x\n", i); - return -EINVAL; - } - } - - /* Global PRAMIN heap */ - if (nouveau_mem_init_heap(&dev_priv->ramin_heap, - c_size, dev_priv->ramin->size - c_size)) { - dev_priv->ramin_heap = NULL; - DRM_ERROR("Failed to init RAMIN heap\n"); - } - - /*XXX: incorrect, but needed to make hash func "work" */ - dev_priv->ramht_offset = 0x10000; - dev_priv->ramht_bits = 9; - dev_priv->ramht_size = (1 << dev_priv->ramht_bits); - return 0; -} - -void -nv50_instmem_takedown(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv; - struct nouveau_channel *chan = dev_priv->fifos[0]; - int i; - - DRM_DEBUG("\n"); - - if (!priv) - return; - - /* Restore state from before init */ - for (i = 0x1700; i <= 0x1710; i+=4) - NV_WRITE(i, priv->save1700[(i-0x1700)/4]); - - nouveau_gpuobj_ref_del(dev, &priv->pramin_bar); - nouveau_gpuobj_ref_del(dev, &priv->pramin_pt); - - /* Destroy dummy channel */ - if (chan) { - nouveau_gpuobj_del(dev, &chan->vm_pd); - nouveau_gpuobj_ref_del(dev, &chan->ramfc); - nouveau_gpuobj_ref_del(dev, &chan->ramin); - nouveau_mem_takedown(&chan->ramin_heap); - - dev_priv->fifos[0] = dev_priv->fifos[127] = NULL; - drm_free(chan, sizeof(*chan), DRM_MEM_DRIVER); - } - - dev_priv->Engine.instmem.priv = NULL; - drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER); -} - -int -nv50_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz) -{ - if (gpuobj->im_backing) - return -EINVAL; - - *sz = (*sz + (NV50_INSTMEM_PAGE_SIZE-1)) & ~(NV50_INSTMEM_PAGE_SIZE-1); - if (*sz == 0) - return -EINVAL; - - gpuobj->im_backing = nouveau_mem_alloc(dev, NV50_INSTMEM_PAGE_SIZE, - *sz, NOUVEAU_MEM_FB | - NOUVEAU_MEM_NOVM, - (struct drm_file *)-2); - if (!gpuobj->im_backing) { - DRM_ERROR("Couldn't allocate vram to back PRAMIN pages\n"); - return -ENOMEM; - } - - return 0; -} - -void -nv50_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - if (gpuobj && gpuobj->im_backing) { - if (gpuobj->im_bound) - dev_priv->Engine.instmem.unbind(dev, gpuobj); - nouveau_mem_free(dev, gpuobj->im_backing); - gpuobj->im_backing = NULL; - } -} - -int -nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv; - uint32_t pte, pte_end, vram; - - if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound) - return -EINVAL; - - DRM_DEBUG("st=0x%0llx sz=0x%0llx\n", - gpuobj->im_pramin->start, gpuobj->im_pramin->size); - - pte = (gpuobj->im_pramin->start >> 12) << 3; - pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte; - vram = gpuobj->im_backing->start; - - DRM_DEBUG("pramin=0x%llx, pte=%d, pte_end=%d\n", - gpuobj->im_pramin->start, pte, pte_end); - DRM_DEBUG("first vram page: 0x%llx\n", - gpuobj->im_backing->start); - - while (pte < pte_end) { - INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 0)/4, vram | 1); - INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000); - - pte += 8; - vram += NV50_INSTMEM_PAGE_SIZE; - } - - NV_WRITE(0x070000, 0x00000001); - while(NV_READ(0x070000) & 1); - NV_WRITE(0x100c80, 0x00040001); - while(NV_READ(0x100c80) & 1); - NV_WRITE(0x100c80, 0x00060001); - while(NV_READ(0x100c80) & 1); - - gpuobj->im_bound = 1; - return 0; -} - -int -nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv; - uint32_t pte, pte_end; - - if (gpuobj->im_bound == 0) - return -EINVAL; - - pte = (gpuobj->im_pramin->start >> 12) << 3; - pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte; - while (pte < pte_end) { - INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 0)/4, 0x00000009); - INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000); - pte += 8; - } - - gpuobj->im_bound = 0; - return 0; -} diff --git a/shared-core/nv50_mc.c b/shared-core/nv50_mc.c deleted file mode 100644 index b111826b..00000000 --- a/shared-core/nv50_mc.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (C) 2007 Ben Skeggs. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" - -int -nv50_mc_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF); - - return 0; -} - -void nv50_mc_takedown(struct drm_device *dev) -{ -} diff --git a/shared-core/r128_cce.c b/shared-core/r128_cce.c deleted file mode 100644 index 995c6f2e..00000000 --- a/shared-core/r128_cce.c +++ /dev/null @@ -1,933 +0,0 @@ -/* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*- - * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com - */ -/* - * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - */ - -#include "drmP.h" -#include "drm.h" -#include "r128_drm.h" -#include "r128_drv.h" - -#define R128_FIFO_DEBUG 0 - -/* CCE microcode (from ATI) */ -static u32 r128_cce_microcode[] = { - 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0, - 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0, - 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1, - 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11, - 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28, - 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9, - 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656, - 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1, - 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071, - 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2, - 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1, - 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1, - 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1, - 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2, - 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1, - 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82, - 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729, - 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008, - 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0, - 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1, - 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1, - 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0, - 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370, - 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1, - 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793, - 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1, - 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1, - 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1, - 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1, - 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894, - 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14, - 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1, - 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1, - 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1, - 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static int R128_READ_PLL(struct drm_device * dev, int addr) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - - R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f); - return R128_READ(R128_CLOCK_CNTL_DATA); -} - -#if R128_FIFO_DEBUG -static void r128_status(drm_r128_private_t * dev_priv) -{ - printk("GUI_STAT = 0x%08x\n", - (unsigned int)R128_READ(R128_GUI_STAT)); - printk("PM4_STAT = 0x%08x\n", - (unsigned int)R128_READ(R128_PM4_STAT)); - printk("PM4_BUFFER_DL_WPTR = 0x%08x\n", - (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR)); - printk("PM4_BUFFER_DL_RPTR = 0x%08x\n", - (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR)); - printk("PM4_MICRO_CNTL = 0x%08x\n", - (unsigned int)R128_READ(R128_PM4_MICRO_CNTL)); - printk("PM4_BUFFER_CNTL = 0x%08x\n", - (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL)); -} -#endif - -/* ================================================================ - * Engine, FIFO control - */ - -static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv) -{ - u32 tmp; - int i; - - tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL; - R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp); - - for (i = 0; i < dev_priv->usec_timeout; i++) { - if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) { - return 0; - } - DRM_UDELAY(1); - } - -#if R128_FIFO_DEBUG - DRM_ERROR("failed!\n"); -#endif - return -EBUSY; -} - -static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries) -{ - int i; - - for (i = 0; i < dev_priv->usec_timeout; i++) { - int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK; - if (slots >= entries) - return 0; - DRM_UDELAY(1); - } - -#if R128_FIFO_DEBUG - DRM_ERROR("failed!\n"); -#endif - return -EBUSY; -} - -static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv) -{ - int i, ret; - - ret = r128_do_wait_for_fifo(dev_priv, 64); - if (ret) - return ret; - - for (i = 0; i < dev_priv->usec_timeout; i++) { - if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) { - r128_do_pixcache_flush(dev_priv); - return 0; - } - DRM_UDELAY(1); - } - -#if R128_FIFO_DEBUG - DRM_ERROR("failed!\n"); -#endif - return -EBUSY; -} - -/* ================================================================ - * CCE control, initialization - */ - -/* Load the microcode for the CCE */ -static void r128_cce_load_microcode(drm_r128_private_t * dev_priv) -{ - int i; - - DRM_DEBUG("\n"); - - r128_do_wait_for_idle(dev_priv); - - R128_WRITE(R128_PM4_MICROCODE_ADDR, 0); - for (i = 0; i < 256; i++) { - R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]); - R128_WRITE(R128_PM4_MICROCODE_DATAL, - r128_cce_microcode[i * 2 + 1]); - } -} - -/* Flush any pending commands to the CCE. This should only be used just - * prior to a wait for idle, as it informs the engine that the command - * stream is ending. - */ -static void r128_do_cce_flush(drm_r128_private_t * dev_priv) -{ - u32 tmp; - - tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE; - R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp); -} - -/* Wait for the CCE to go idle. - */ -int r128_do_cce_idle(drm_r128_private_t * dev_priv) -{ - int i; - - for (i = 0; i < dev_priv->usec_timeout; i++) { - if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) { - int pm4stat = R128_READ(R128_PM4_STAT); - if (((pm4stat & R128_PM4_FIFOCNT_MASK) >= - dev_priv->cce_fifo_size) && - !(pm4stat & (R128_PM4_BUSY | - R128_PM4_GUI_ACTIVE))) { - return r128_do_pixcache_flush(dev_priv); - } - } - DRM_UDELAY(1); - } - -#if R128_FIFO_DEBUG - DRM_ERROR("failed!\n"); - r128_status(dev_priv); -#endif - return -EBUSY; -} - -/* Start the Concurrent Command Engine. - */ -static void r128_do_cce_start(drm_r128_private_t * dev_priv) -{ - r128_do_wait_for_idle(dev_priv); - - R128_WRITE(R128_PM4_BUFFER_CNTL, - dev_priv->cce_mode | dev_priv->ring.size_l2qw - | R128_PM4_BUFFER_CNTL_NOUPDATE); - R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */ - R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN); - - dev_priv->cce_running = 1; -} - -/* Reset the Concurrent Command Engine. This will not flush any pending - * commands, so you must wait for the CCE command stream to complete - * before calling this routine. - */ -static void r128_do_cce_reset(drm_r128_private_t * dev_priv) -{ - R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0); - R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0); - dev_priv->ring.tail = 0; -} - -/* Stop the Concurrent Command Engine. This will not flush any pending - * commands, so you must flush the command stream and wait for the CCE - * to go idle before calling this routine. - */ -static void r128_do_cce_stop(drm_r128_private_t * dev_priv) -{ - R128_WRITE(R128_PM4_MICRO_CNTL, 0); - R128_WRITE(R128_PM4_BUFFER_CNTL, - R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE); - - dev_priv->cce_running = 0; -} - -/* Reset the engine. This will stop the CCE if it is running. - */ -static int r128_do_engine_reset(struct drm_device * dev) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - u32 clock_cntl_index, mclk_cntl, gen_reset_cntl; - - r128_do_pixcache_flush(dev_priv); - - clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX); - mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL); - - R128_WRITE_PLL(R128_MCLK_CNTL, - mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP); - - gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL); - - /* Taken from the sample code - do not change */ - R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI); - R128_READ(R128_GEN_RESET_CNTL); - R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI); - R128_READ(R128_GEN_RESET_CNTL); - - R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl); - R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index); - R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl); - - /* Reset the CCE ring */ - r128_do_cce_reset(dev_priv); - - /* The CCE is no longer running after an engine reset */ - dev_priv->cce_running = 0; - - /* Reset any pending vertex, indirect buffers */ - r128_freelist_reset(dev); - - return 0; -} - -static void r128_cce_init_ring_buffer(struct drm_device * dev, - drm_r128_private_t * dev_priv) -{ - u32 ring_start; - u32 tmp; - - DRM_DEBUG("\n"); - - /* The manual (p. 2) says this address is in "VM space". This - * means it's an offset from the start of AGP space. - */ -#if __OS_HAS_AGP - if (!dev_priv->is_pci) - ring_start = dev_priv->cce_ring->offset - dev->agp->base; - else -#endif - ring_start = dev_priv->cce_ring->offset - - (unsigned long)dev->sg->virtual; - - R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET); - - R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0); - R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0); - - /* Set watermark control */ - R128_WRITE(R128_PM4_BUFFER_WM_CNTL, - ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT) - | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT) - | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT) - | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT)); - - /* Force read. Why? Because it's in the examples... */ - R128_READ(R128_PM4_BUFFER_ADDR); - - /* Turn on bus mastering */ - tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS; - R128_WRITE(R128_BUS_CNTL, tmp); -} - -static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) -{ - drm_r128_private_t *dev_priv; - - DRM_DEBUG("\n"); - - dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER); - if (dev_priv == NULL) - return -ENOMEM; - - memset(dev_priv, 0, sizeof(drm_r128_private_t)); - - dev_priv->is_pci = init->is_pci; - - if (dev_priv->is_pci && !dev->sg) { - DRM_ERROR("PCI GART memory not allocated!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce(dev); - return -EINVAL; - } - - dev_priv->usec_timeout = init->usec_timeout; - if (dev_priv->usec_timeout < 1 || - dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) { - DRM_DEBUG("TIMEOUT problem!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce(dev); - return -EINVAL; - } - - dev_priv->cce_mode = init->cce_mode; - - /* GH: Simple idle check. - */ - atomic_set(&dev_priv->idle_count, 0); - - /* We don't support anything other than bus-mastering ring mode, - * but the ring can be in either AGP or PCI space for the ring - * read pointer. - */ - if ((init->cce_mode != R128_PM4_192BM) && - (init->cce_mode != R128_PM4_128BM_64INDBM) && - (init->cce_mode != R128_PM4_64BM_128INDBM) && - (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) { - DRM_DEBUG("Bad cce_mode!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce(dev); - return -EINVAL; - } - - switch (init->cce_mode) { - case R128_PM4_NONPM4: - dev_priv->cce_fifo_size = 0; - break; - case R128_PM4_192PIO: - case R128_PM4_192BM: - dev_priv->cce_fifo_size = 192; - break; - case R128_PM4_128PIO_64INDBM: - case R128_PM4_128BM_64INDBM: - dev_priv->cce_fifo_size = 128; - break; - case R128_PM4_64PIO_128INDBM: - case R128_PM4_64BM_128INDBM: - case R128_PM4_64PIO_64VCBM_64INDBM: - case R128_PM4_64BM_64VCBM_64INDBM: - case R128_PM4_64PIO_64VCPIO_64INDPIO: - dev_priv->cce_fifo_size = 64; - break; - } - - switch (init->fb_bpp) { - case 16: - dev_priv->color_fmt = R128_DATATYPE_RGB565; - break; - case 32: - default: - dev_priv->color_fmt = R128_DATATYPE_ARGB8888; - break; - } - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; - - switch (init->depth_bpp) { - case 16: - dev_priv->depth_fmt = R128_DATATYPE_RGB565; - break; - case 24: - case 32: - default: - dev_priv->depth_fmt = R128_DATATYPE_ARGB8888; - break; - } - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; - dev_priv->span_offset = init->span_offset; - - dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) | - (dev_priv->front_offset >> 5)); - dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) | - (dev_priv->back_offset >> 5)); - dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | - (dev_priv->depth_offset >> 5) | - R128_DST_TILE); - dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | - (dev_priv->span_offset >> 5)); - - dev_priv->sarea = drm_getsarea(dev); - if (!dev_priv->sarea) { - DRM_ERROR("could not find sarea!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce(dev); - return -EINVAL; - } - - dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); - if (!dev_priv->mmio) { - DRM_ERROR("could not find mmio region!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce(dev); - return -EINVAL; - } - dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset); - if (!dev_priv->cce_ring) { - DRM_ERROR("could not find cce ring region!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce(dev); - return -EINVAL; - } - dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); - if (!dev_priv->ring_rptr) { - DRM_ERROR("could not find ring read pointer!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce(dev); - return -EINVAL; - } - dev->agp_buffer_token = init->buffers_offset; - dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); - if (!dev->agp_buffer_map) { - DRM_ERROR("could not find dma buffer region!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce(dev); - return -EINVAL; - } - - if (!dev_priv->is_pci) { - dev_priv->agp_textures = - drm_core_findmap(dev, init->agp_textures_offset); - if (!dev_priv->agp_textures) { - DRM_ERROR("could not find agp texture region!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce(dev); - return -EINVAL; - } - } - - dev_priv->sarea_priv = - (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle + - init->sarea_priv_offset); - -#if __OS_HAS_AGP - if (!dev_priv->is_pci) { - drm_core_ioremap(dev_priv->cce_ring, dev); - drm_core_ioremap(dev_priv->ring_rptr, dev); - drm_core_ioremap(dev->agp_buffer_map, dev); - if (!dev_priv->cce_ring->handle || - !dev_priv->ring_rptr->handle || - !dev->agp_buffer_map->handle) { - DRM_ERROR("Could not ioremap agp regions!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce(dev); - return -ENOMEM; - } - } else -#endif - { - dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset; - dev_priv->ring_rptr->handle = - (void *)dev_priv->ring_rptr->offset; - dev->agp_buffer_map->handle = - (void *)dev->agp_buffer_map->offset; - } - -#if __OS_HAS_AGP - if (!dev_priv->is_pci) - dev_priv->cce_buffers_offset = dev->agp->base; - else -#endif - dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual; - - dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle; - dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle - + init->ring_size / sizeof(u32)); - dev_priv->ring.size = init->ring_size; - dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); - - dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; - - dev_priv->ring.high_mark = 128; - - dev_priv->sarea_priv->last_frame = 0; - R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); - - dev_priv->sarea_priv->last_dispatch = 0; - R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch); - -#if __OS_HAS_AGP - if (dev_priv->is_pci) { -#endif - dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); - dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN; - dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE; - dev_priv->gart_info.addr = NULL; - dev_priv->gart_info.bus_addr = 0; - dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; - if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { - DRM_ERROR("failed to init PCI GART!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce(dev); - return -ENOMEM; - } - R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr); -#if __OS_HAS_AGP - } -#endif - - r128_cce_init_ring_buffer(dev, dev_priv); - r128_cce_load_microcode(dev_priv); - - dev->dev_private = (void *)dev_priv; - - r128_do_engine_reset(dev); - - return 0; -} - -int r128_do_cleanup_cce(struct drm_device * dev) -{ - - /* Make sure interrupts are disabled here because the uninstall ioctl - * may not have been called from userspace and after dev_private - * is freed, it's too late. - */ - if (dev->irq_enabled) - drm_irq_uninstall(dev); - - if (dev->dev_private) { - drm_r128_private_t *dev_priv = dev->dev_private; - -#if __OS_HAS_AGP - if (!dev_priv->is_pci) { - if (dev_priv->cce_ring != NULL) - drm_core_ioremapfree(dev_priv->cce_ring, dev); - if (dev_priv->ring_rptr != NULL) - drm_core_ioremapfree(dev_priv->ring_rptr, dev); - if (dev->agp_buffer_map != NULL) { - drm_core_ioremapfree(dev->agp_buffer_map, dev); - dev->agp_buffer_map = NULL; - } - } else -#endif - { - if (dev_priv->gart_info.bus_addr) - if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) - DRM_ERROR("failed to cleanup PCI GART!\n"); - } - - drm_free(dev->dev_private, sizeof(drm_r128_private_t), - DRM_MEM_DRIVER); - dev->dev_private = NULL; - } - - return 0; -} - -int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_r128_init_t *init = data; - - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - switch (init->func) { - case R128_INIT_CCE: - return r128_do_init_cce(dev, init); - case R128_CLEANUP_CCE: - return r128_do_cleanup_cce(dev); - } - - return -EINVAL; -} - -int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) { - DRM_DEBUG("while CCE running\n"); - return 0; - } - - r128_do_cce_start(dev_priv); - - return 0; -} - -/* Stop the CCE. The engine must have been idled before calling this - * routine. - */ -int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_cce_stop_t *stop = data; - int ret; - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - /* Flush any pending CCE commands. This ensures any outstanding - * commands are exectuted by the engine before we turn it off. - */ - if (stop->flush) { - r128_do_cce_flush(dev_priv); - } - - /* If we fail to make the engine go idle, we return an error - * code so that the DRM ioctl wrapper can try again. - */ - if (stop->idle) { - ret = r128_do_cce_idle(dev_priv); - if (ret) - return ret; - } - - /* Finally, we can turn off the CCE. If the engine isn't idle, - * we will get some dropped triangles as they won't be fully - * rendered before the CCE is shut down. - */ - r128_do_cce_stop(dev_priv); - - /* Reset the engine */ - r128_do_engine_reset(dev); - - return 0; -} - -/* Just reset the CCE ring. Called as part of an X Server engine reset. - */ -int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (!dev_priv) { - DRM_DEBUG("called before init done\n"); - return -EINVAL; - } - - r128_do_cce_reset(dev_priv); - - /* The CCE is no longer running after an engine reset */ - dev_priv->cce_running = 0; - - return 0; -} - -int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (dev_priv->cce_running) { - r128_do_cce_flush(dev_priv); - } - - return r128_do_cce_idle(dev_priv); -} - -int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - return r128_do_engine_reset(dev); -} - -int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - return -EINVAL; -} - -/* ================================================================ - * Freelist management - */ -#define R128_BUFFER_USED 0xffffffff -#define R128_BUFFER_FREE 0 - -#if 0 -static int r128_freelist_init(struct drm_device * dev) -{ - struct drm_device_dma *dma = dev->dma; - drm_r128_private_t *dev_priv = dev->dev_private; - struct drm_buf *buf; - drm_r128_buf_priv_t *buf_priv; - drm_r128_freelist_t *entry; - int i; - - dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER); - if (dev_priv->head == NULL) - return -ENOMEM; - - memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t)); - dev_priv->head->age = R128_BUFFER_USED; - - for (i = 0; i < dma->buf_count; i++) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - - entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER); - if (!entry) - return -ENOMEM; - - entry->age = R128_BUFFER_FREE; - entry->buf = buf; - entry->prev = dev_priv->head; - entry->next = dev_priv->head->next; - if (!entry->next) - dev_priv->tail = entry; - - buf_priv->discard = 0; - buf_priv->dispatched = 0; - buf_priv->list_entry = entry; - - dev_priv->head->next = entry; - - if (dev_priv->head->next) - dev_priv->head->next->prev = entry; - } - - return 0; - -} -#endif - -static struct drm_buf *r128_freelist_get(struct drm_device * dev) -{ - struct drm_device_dma *dma = dev->dma; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_buf_priv_t *buf_priv; - struct drm_buf *buf; - int i, t; - - /* FIXME: Optimize -- use freelist code */ - - for (i = 0; i < dma->buf_count; i++) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - if (buf->file_priv == 0) - return buf; - } - - for (t = 0; t < dev_priv->usec_timeout; t++) { - u32 done_age = R128_READ(R128_LAST_DISPATCH_REG); - - for (i = 0; i < dma->buf_count; i++) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - if (buf->pending && buf_priv->age <= done_age) { - /* The buffer has been processed, so it - * can now be used. - */ - buf->pending = 0; - return buf; - } - } - DRM_UDELAY(1); - } - - DRM_DEBUG("returning NULL!\n"); - return NULL; -} - -void r128_freelist_reset(struct drm_device * dev) -{ - struct drm_device_dma *dma = dev->dma; - int i; - - for (i = 0; i < dma->buf_count; i++) { - struct drm_buf *buf = dma->buflist[i]; - drm_r128_buf_priv_t *buf_priv = buf->dev_private; - buf_priv->age = 0; - } -} - -/* ================================================================ - * CCE command submission - */ - -int r128_wait_ring(drm_r128_private_t * dev_priv, int n) -{ - drm_r128_ring_buffer_t *ring = &dev_priv->ring; - int i; - - for (i = 0; i < dev_priv->usec_timeout; i++) { - r128_update_ring_snapshot(dev_priv); - if (ring->space >= n) - return 0; - DRM_UDELAY(1); - } - - /* FIXME: This is being ignored... */ - DRM_ERROR("failed!\n"); - return -EBUSY; -} - -static int r128_cce_get_buffers(struct drm_device * dev, - struct drm_file *file_priv, - struct drm_dma * d) -{ - int i; - struct drm_buf *buf; - - for (i = d->granted_count; i < d->request_count; i++) { - buf = r128_freelist_get(dev); - if (!buf) - return -EAGAIN; - - buf->file_priv = file_priv; - - if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, - sizeof(buf->idx))) - return -EFAULT; - if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, - sizeof(buf->total))) - return -EFAULT; - - d->granted_count++; - } - return 0; -} - -int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - struct drm_device_dma *dma = dev->dma; - int ret = 0; - struct drm_dma *d = data; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - /* Please don't send us buffers. - */ - if (d->send_count != 0) { - DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d->send_count); - return -EINVAL; - } - - /* We'll send you buffers. - */ - if (d->request_count < 0 || d->request_count > dma->buf_count) { - DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d->request_count, dma->buf_count); - return -EINVAL; - } - - d->granted_count = 0; - - if (d->request_count) { - ret = r128_cce_get_buffers(dev, file_priv, d); - } - - return ret; -} diff --git a/shared-core/r128_drm.h b/shared-core/r128_drm.h deleted file mode 100644 index 8d8878b5..00000000 --- a/shared-core/r128_drm.h +++ /dev/null @@ -1,326 +0,0 @@ -/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*- - * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com - */ -/* - * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Kevin E. Martin - */ - -#ifndef __R128_DRM_H__ -#define __R128_DRM_H__ - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the X server file (r128_sarea.h) - */ -#ifndef __R128_SAREA_DEFINES__ -#define __R128_SAREA_DEFINES__ - -/* What needs to be changed for the current vertex buffer? - */ -#define R128_UPLOAD_CONTEXT 0x001 -#define R128_UPLOAD_SETUP 0x002 -#define R128_UPLOAD_TEX0 0x004 -#define R128_UPLOAD_TEX1 0x008 -#define R128_UPLOAD_TEX0IMAGES 0x010 -#define R128_UPLOAD_TEX1IMAGES 0x020 -#define R128_UPLOAD_CORE 0x040 -#define R128_UPLOAD_MASKS 0x080 -#define R128_UPLOAD_WINDOW 0x100 -#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */ -#define R128_REQUIRE_QUIESCENCE 0x400 -#define R128_UPLOAD_ALL 0x7ff - -#define R128_FRONT 0x1 -#define R128_BACK 0x2 -#define R128_DEPTH 0x4 - -/* Primitive types - */ -#define R128_POINTS 0x1 -#define R128_LINES 0x2 -#define R128_LINE_STRIP 0x3 -#define R128_TRIANGLES 0x4 -#define R128_TRIANGLE_FAN 0x5 -#define R128_TRIANGLE_STRIP 0x6 - -/* Vertex/indirect buffer size - */ -#define R128_BUFFER_SIZE 16384 - -/* Byte offsets for indirect buffer data - */ -#define R128_INDEX_PRIM_OFFSET 20 -#define R128_HOSTDATA_BLIT_OFFSET 32 - -/* Keep these small for testing. - */ -#define R128_NR_SAREA_CLIPRECTS 12 - -/* There are 2 heaps (local/AGP). Each region within a heap is a - * minimum of 64k, and there are at most 64 of them per heap. - */ -#define R128_LOCAL_TEX_HEAP 0 -#define R128_AGP_TEX_HEAP 1 -#define R128_NR_TEX_HEAPS 2 -#define R128_NR_TEX_REGIONS 64 -#define R128_LOG_TEX_GRANULARITY 16 - -#define R128_NR_CONTEXT_REGS 12 - -#define R128_MAX_TEXTURE_LEVELS 11 -#define R128_MAX_TEXTURE_UNITS 2 - -#endif /* __R128_SAREA_DEFINES__ */ - -typedef struct { - /* Context state - can be written in one large chunk */ - unsigned int dst_pitch_offset_c; - unsigned int dp_gui_master_cntl_c; - unsigned int sc_top_left_c; - unsigned int sc_bottom_right_c; - unsigned int z_offset_c; - unsigned int z_pitch_c; - unsigned int z_sten_cntl_c; - unsigned int tex_cntl_c; - unsigned int misc_3d_state_cntl_reg; - unsigned int texture_clr_cmp_clr_c; - unsigned int texture_clr_cmp_msk_c; - unsigned int fog_color_c; - - /* Texture state */ - unsigned int tex_size_pitch_c; - unsigned int constant_color_c; - - /* Setup state */ - unsigned int pm4_vc_fpu_setup; - unsigned int setup_cntl; - - /* Mask state */ - unsigned int dp_write_mask; - unsigned int sten_ref_mask_c; - unsigned int plane_3d_mask_c; - - /* Window state */ - unsigned int window_xy_offset; - - /* Core state */ - unsigned int scale_3d_cntl; -} drm_r128_context_regs_t; - -/* Setup registers for each texture unit - */ -typedef struct { - unsigned int tex_cntl; - unsigned int tex_combine_cntl; - unsigned int tex_size_pitch; - unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS]; - unsigned int tex_border_color; -} drm_r128_texture_regs_t; - -typedef struct drm_r128_sarea { - /* The channel for communication of state information to the kernel - * on firing a vertex buffer. - */ - drm_r128_context_regs_t context_state; - drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS]; - unsigned int dirty; - unsigned int vertsize; - unsigned int vc_format; - - /* The current cliprects, or a subset thereof. - */ - struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS]; - unsigned int nbox; - - /* Counters for client-side throttling of rendering clients. - */ - unsigned int last_frame; - unsigned int last_dispatch; - - struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1]; - unsigned int tex_age[R128_NR_TEX_HEAPS]; - int ctx_owner; - int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ - int pfCurrentPage; /* which buffer is being displayed? */ -} drm_r128_sarea_t; - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (xf86drmR128.h) - */ - -/* Rage 128 specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ -#define DRM_R128_INIT 0x00 -#define DRM_R128_CCE_START 0x01 -#define DRM_R128_CCE_STOP 0x02 -#define DRM_R128_CCE_RESET 0x03 -#define DRM_R128_CCE_IDLE 0x04 -/* 0x05 not used */ -#define DRM_R128_RESET 0x06 -#define DRM_R128_SWAP 0x07 -#define DRM_R128_CLEAR 0x08 -#define DRM_R128_VERTEX 0x09 -#define DRM_R128_INDICES 0x0a -#define DRM_R128_BLIT 0x0b -#define DRM_R128_DEPTH 0x0c -#define DRM_R128_STIPPLE 0x0d -/* 0x0e not used */ -#define DRM_R128_INDIRECT 0x0f -#define DRM_R128_FULLSCREEN 0x10 -#define DRM_R128_CLEAR2 0x11 -#define DRM_R128_GETPARAM 0x12 -#define DRM_R128_FLIP 0x13 - -#define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t) -#define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START) -#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t) -#define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET) -#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE) -/* 0x05 not used */ -#define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET) -#define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP) -#define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t) -#define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t) -#define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t) -#define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t) -#define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t) -#define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t) -/* 0x0e not used */ -#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t) -#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t) -#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t) -#define DRM_IOCTL_R128_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t) -#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP) - -typedef struct drm_r128_init { - enum { - R128_INIT_CCE = 0x01, - R128_CLEANUP_CCE = 0x02 - } func; - unsigned long sarea_priv_offset; - int is_pci; - int cce_mode; - int cce_secure; - int ring_size; - int usec_timeout; - - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - unsigned int span_offset; - - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long ring_offset; - unsigned long ring_rptr_offset; - unsigned long buffers_offset; - unsigned long agp_textures_offset; -} drm_r128_init_t; - -typedef struct drm_r128_cce_stop { - int flush; - int idle; -} drm_r128_cce_stop_t; - -typedef struct drm_r128_clear { - unsigned int flags; - unsigned int clear_color; - unsigned int clear_depth; - unsigned int color_mask; - unsigned int depth_mask; -} drm_r128_clear_t; - -typedef struct drm_r128_vertex { - int prim; - int idx; /* Index of vertex buffer */ - int count; /* Number of vertices in buffer */ - int discard; /* Client finished with buffer? */ -} drm_r128_vertex_t; - -typedef struct drm_r128_indices { - int prim; - int idx; - int start; - int end; - int discard; /* Client finished with buffer? */ -} drm_r128_indices_t; - -typedef struct drm_r128_blit { - int idx; - int pitch; - int offset; - int format; - unsigned short x, y; - unsigned short width, height; -} drm_r128_blit_t; - -typedef struct drm_r128_depth { - enum { - R128_WRITE_SPAN = 0x01, - R128_WRITE_PIXELS = 0x02, - R128_READ_SPAN = 0x03, - R128_READ_PIXELS = 0x04 - } func; - int n; - int __user *x; - int __user *y; - unsigned int __user *buffer; - unsigned char __user *mask; -} drm_r128_depth_t; - -typedef struct drm_r128_stipple { - unsigned int __user *mask; -} drm_r128_stipple_t; - -typedef struct drm_r128_indirect { - int idx; - int start; - int end; - int discard; -} drm_r128_indirect_t; - -typedef struct drm_r128_fullscreen { - enum { - R128_INIT_FULLSCREEN = 0x01, - R128_CLEANUP_FULLSCREEN = 0x02 - } func; -} drm_r128_fullscreen_t; - -/* 2.3: An ioctl to get parameters that aren't available to the 3d - * client any other way. - */ -#define R128_PARAM_IRQ_NR 1 - -typedef struct drm_r128_getparam { - int param; - void __user *value; -} drm_r128_getparam_t; - -#endif diff --git a/shared-core/r128_drv.h b/shared-core/r128_drv.h deleted file mode 100644 index 9e7a6467..00000000 --- a/shared-core/r128_drv.h +++ /dev/null @@ -1,526 +0,0 @@ -/* r128_drv.h -- Private header for r128 driver -*- linux-c -*- - * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com - */ -/* - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Rickard E. (Rik) Faith - * Kevin E. Martin - * Gareth Hughes - * Michel D�zer - */ - -#ifndef __R128_DRV_H__ -#define __R128_DRV_H__ - -/* General customization: - */ -#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." - -#define DRIVER_NAME "r128" -#define DRIVER_DESC "ATI Rage 128" -#define DRIVER_DATE "20030725" - -/* Interface history: - * - * ?? - ?? - * 2.4 - Add support for ycbcr textures (no new ioctls) - * 2.5 - Add FLIP ioctl, disable FULLSCREEN. - */ -#define DRIVER_MAJOR 2 -#define DRIVER_MINOR 5 -#define DRIVER_PATCHLEVEL 0 - -#define GET_RING_HEAD(dev_priv) R128_READ( R128_PM4_BUFFER_DL_RPTR ) - -typedef struct drm_r128_freelist { - unsigned int age; - struct drm_buf *buf; - struct drm_r128_freelist *next; - struct drm_r128_freelist *prev; -} drm_r128_freelist_t; - -typedef struct drm_r128_ring_buffer { - u32 *start; - u32 *end; - int size; - int size_l2qw; - - u32 tail; - u32 tail_mask; - int space; - - int high_mark; -} drm_r128_ring_buffer_t; - -typedef struct drm_r128_private { - drm_r128_ring_buffer_t ring; - drm_r128_sarea_t *sarea_priv; - - int cce_mode; - int cce_fifo_size; - int cce_running; - - drm_r128_freelist_t *head; - drm_r128_freelist_t *tail; - - int usec_timeout; - int is_pci; - unsigned long cce_buffers_offset; - - atomic_t idle_count; - - int page_flipping; - int current_page; - u32 crtc_offset; - u32 crtc_offset_cntl; - - atomic_t vbl_received; - - u32 color_fmt; - unsigned int front_offset; - unsigned int front_pitch; - unsigned int back_offset; - unsigned int back_pitch; - - u32 depth_fmt; - unsigned int depth_offset; - unsigned int depth_pitch; - unsigned int span_offset; - - u32 front_pitch_offset_c; - u32 back_pitch_offset_c; - u32 depth_pitch_offset_c; - u32 span_pitch_offset_c; - - drm_local_map_t *sarea; - drm_local_map_t *mmio; - drm_local_map_t *cce_ring; - drm_local_map_t *ring_rptr; - drm_local_map_t *agp_textures; - struct drm_ati_pcigart_info gart_info; -} drm_r128_private_t; - -typedef struct drm_r128_buf_priv { - u32 age; - int prim; - int discard; - int dispatched; - drm_r128_freelist_t *list_entry; -} drm_r128_buf_priv_t; - -extern struct drm_ioctl_desc r128_ioctls[]; -extern int r128_max_ioctl; - - /* r128_cce.c */ -extern int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); - -extern void r128_freelist_reset(struct drm_device * dev); - -extern int r128_wait_ring(drm_r128_private_t * dev_priv, int n); - -extern int r128_do_cce_idle(drm_r128_private_t * dev_priv); -extern int r128_do_cleanup_cce(struct drm_device * dev); - -extern int r128_enable_vblank(struct drm_device *dev, int crtc); -extern void r128_disable_vblank(struct drm_device *dev, int crtc); -extern u32 r128_get_vblank_counter(struct drm_device *dev, int crtc); -extern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS); -extern void r128_driver_irq_preinstall(struct drm_device * dev); -extern int r128_driver_irq_postinstall(struct drm_device * dev); -extern void r128_driver_irq_uninstall(struct drm_device * dev); -extern void r128_driver_lastclose(struct drm_device * dev); -extern int r128_driver_load(struct drm_device * dev, unsigned long flags); -extern void r128_driver_preclose(struct drm_device * dev, - struct drm_file *file_priv); - -extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, - unsigned long arg); - -/* Register definitions, register access macros and drmAddMap constants - * for Rage 128 kernel driver. - */ - -#define R128_AUX_SC_CNTL 0x1660 -# define R128_AUX1_SC_EN (1 << 0) -# define R128_AUX1_SC_MODE_OR (0 << 1) -# define R128_AUX1_SC_MODE_NAND (1 << 1) -# define R128_AUX2_SC_EN (1 << 2) -# define R128_AUX2_SC_MODE_OR (0 << 3) -# define R128_AUX2_SC_MODE_NAND (1 << 3) -# define R128_AUX3_SC_EN (1 << 4) -# define R128_AUX3_SC_MODE_OR (0 << 5) -# define R128_AUX3_SC_MODE_NAND (1 << 5) -#define R128_AUX1_SC_LEFT 0x1664 -#define R128_AUX1_SC_RIGHT 0x1668 -#define R128_AUX1_SC_TOP 0x166c -#define R128_AUX1_SC_BOTTOM 0x1670 -#define R128_AUX2_SC_LEFT 0x1674 -#define R128_AUX2_SC_RIGHT 0x1678 -#define R128_AUX2_SC_TOP 0x167c -#define R128_AUX2_SC_BOTTOM 0x1680 -#define R128_AUX3_SC_LEFT 0x1684 -#define R128_AUX3_SC_RIGHT 0x1688 -#define R128_AUX3_SC_TOP 0x168c -#define R128_AUX3_SC_BOTTOM 0x1690 - -#define R128_BRUSH_DATA0 0x1480 -#define R128_BUS_CNTL 0x0030 -# define R128_BUS_MASTER_DIS (1 << 6) - -#define R128_CLOCK_CNTL_INDEX 0x0008 -#define R128_CLOCK_CNTL_DATA 0x000c -# define R128_PLL_WR_EN (1 << 7) -#define R128_CONSTANT_COLOR_C 0x1d34 -#define R128_CRTC_OFFSET 0x0224 -#define R128_CRTC_OFFSET_CNTL 0x0228 -# define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16) - -#define R128_DP_GUI_MASTER_CNTL 0x146c -# define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) -# define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) -# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) -# define R128_GMC_BRUSH_NONE (15 << 4) -# define R128_GMC_DST_16BPP (4 << 8) -# define R128_GMC_DST_24BPP (5 << 8) -# define R128_GMC_DST_32BPP (6 << 8) -# define R128_GMC_DST_DATATYPE_SHIFT 8 -# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) -# define R128_DP_SRC_SOURCE_MEMORY (2 << 24) -# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24) -# define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) -# define R128_GMC_AUX_CLIP_DIS (1 << 29) -# define R128_GMC_WR_MSK_DIS (1 << 30) -# define R128_ROP3_S 0x00cc0000 -# define R128_ROP3_P 0x00f00000 -#define R128_DP_WRITE_MASK 0x16cc -#define R128_DST_PITCH_OFFSET_C 0x1c80 -# define R128_DST_TILE (1 << 31) - -#define R128_GEN_INT_CNTL 0x0040 -# define R128_CRTC_VBLANK_INT_EN (1 << 0) -#define R128_GEN_INT_STATUS 0x0044 -# define R128_CRTC_VBLANK_INT (1 << 0) -# define R128_CRTC_VBLANK_INT_AK (1 << 0) -#define R128_GEN_RESET_CNTL 0x00f0 -# define R128_SOFT_RESET_GUI (1 << 0) - -#define R128_GUI_SCRATCH_REG0 0x15e0 -#define R128_GUI_SCRATCH_REG1 0x15e4 -#define R128_GUI_SCRATCH_REG2 0x15e8 -#define R128_GUI_SCRATCH_REG3 0x15ec -#define R128_GUI_SCRATCH_REG4 0x15f0 -#define R128_GUI_SCRATCH_REG5 0x15f4 - -#define R128_GUI_STAT 0x1740 -# define R128_GUI_FIFOCNT_MASK 0x0fff -# define R128_GUI_ACTIVE (1 << 31) - -#define R128_MCLK_CNTL 0x000f -# define R128_FORCE_GCP (1 << 16) -# define R128_FORCE_PIPE3D_CP (1 << 17) -# define R128_FORCE_RCP (1 << 18) - -#define R128_PC_GUI_CTLSTAT 0x1748 -#define R128_PC_NGUI_CTLSTAT 0x0184 -# define R128_PC_FLUSH_GUI (3 << 0) -# define R128_PC_RI_GUI (1 << 2) -# define R128_PC_FLUSH_ALL 0x00ff -# define R128_PC_BUSY (1 << 31) - -#define R128_PCI_GART_PAGE 0x017c -#define R128_PRIM_TEX_CNTL_C 0x1cb0 - -#define R128_SCALE_3D_CNTL 0x1a00 -#define R128_SEC_TEX_CNTL_C 0x1d00 -#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c -#define R128_SETUP_CNTL 0x1bc4 -#define R128_STEN_REF_MASK_C 0x1d40 - -#define R128_TEX_CNTL_C 0x1c9c -# define R128_TEX_CACHE_FLUSH (1 << 23) - -#define R128_WAIT_UNTIL 0x1720 -# define R128_EVENT_CRTC_OFFSET (1 << 0) -#define R128_WINDOW_XY_OFFSET 0x1bcc - -/* CCE registers - */ -#define R128_PM4_BUFFER_OFFSET 0x0700 -#define R128_PM4_BUFFER_CNTL 0x0704 -# define R128_PM4_MASK (15 << 28) -# define R128_PM4_NONPM4 (0 << 28) -# define R128_PM4_192PIO (1 << 28) -# define R128_PM4_192BM (2 << 28) -# define R128_PM4_128PIO_64INDBM (3 << 28) -# define R128_PM4_128BM_64INDBM (4 << 28) -# define R128_PM4_64PIO_128INDBM (5 << 28) -# define R128_PM4_64BM_128INDBM (6 << 28) -# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28) -# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28) -# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28) -# define R128_PM4_BUFFER_CNTL_NOUPDATE (1 << 27) - -#define R128_PM4_BUFFER_WM_CNTL 0x0708 -# define R128_WMA_SHIFT 0 -# define R128_WMB_SHIFT 8 -# define R128_WMC_SHIFT 16 -# define R128_WB_WM_SHIFT 24 - -#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c -#define R128_PM4_BUFFER_DL_RPTR 0x0710 -#define R128_PM4_BUFFER_DL_WPTR 0x0714 -# define R128_PM4_BUFFER_DL_DONE (1 << 31) - -#define R128_PM4_VC_FPU_SETUP 0x071c - -#define R128_PM4_IW_INDOFF 0x0738 -#define R128_PM4_IW_INDSIZE 0x073c - -#define R128_PM4_STAT 0x07b8 -# define R128_PM4_FIFOCNT_MASK 0x0fff -# define R128_PM4_BUSY (1 << 16) -# define R128_PM4_GUI_ACTIVE (1 << 31) - -#define R128_PM4_MICROCODE_ADDR 0x07d4 -#define R128_PM4_MICROCODE_RADDR 0x07d8 -#define R128_PM4_MICROCODE_DATAH 0x07dc -#define R128_PM4_MICROCODE_DATAL 0x07e0 - -#define R128_PM4_BUFFER_ADDR 0x07f0 -#define R128_PM4_MICRO_CNTL 0x07fc -# define R128_PM4_MICRO_FREERUN (1 << 30) - -#define R128_PM4_FIFO_DATA_EVEN 0x1000 -#define R128_PM4_FIFO_DATA_ODD 0x1004 - -/* CCE command packets - */ -#define R128_CCE_PACKET0 0x00000000 -#define R128_CCE_PACKET1 0x40000000 -#define R128_CCE_PACKET2 0x80000000 -#define R128_CCE_PACKET3 0xC0000000 -# define R128_CNTL_HOSTDATA_BLT 0x00009400 -# define R128_CNTL_PAINT_MULTI 0x00009A00 -# define R128_CNTL_BITBLT_MULTI 0x00009B00 -# define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300 - -#define R128_CCE_PACKET_MASK 0xC0000000 -#define R128_CCE_PACKET_COUNT_MASK 0x3fff0000 -#define R128_CCE_PACKET0_REG_MASK 0x000007ff -#define R128_CCE_PACKET1_REG0_MASK 0x000007ff -#define R128_CCE_PACKET1_REG1_MASK 0x003ff800 - -#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000 -#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001 -#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002 -#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 -#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 -#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 -#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 -#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 -#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010 -#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020 -#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030 -#define R128_CCE_VC_CNTL_NUM_SHIFT 16 - -#define R128_DATATYPE_VQ 0 -#define R128_DATATYPE_CI4 1 -#define R128_DATATYPE_CI8 2 -#define R128_DATATYPE_ARGB1555 3 -#define R128_DATATYPE_RGB565 4 -#define R128_DATATYPE_RGB888 5 -#define R128_DATATYPE_ARGB8888 6 -#define R128_DATATYPE_RGB332 7 -#define R128_DATATYPE_Y8 8 -#define R128_DATATYPE_RGB8 9 -#define R128_DATATYPE_CI16 10 -#define R128_DATATYPE_YVYU422 11 -#define R128_DATATYPE_VYUY422 12 -#define R128_DATATYPE_AYUV444 14 -#define R128_DATATYPE_ARGB4444 15 - -/* Constants */ -#define R128_AGP_OFFSET 0x02000000 - -#define R128_WATERMARK_L 16 -#define R128_WATERMARK_M 8 -#define R128_WATERMARK_N 8 -#define R128_WATERMARK_K 128 - -#define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */ - -#define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0 -#define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1 -#define R128_MAX_VB_AGE 0x7fffffff -#define R128_MAX_VB_VERTS (0xffff) - -#define R128_RING_HIGH_MARK 128 - -#define R128_PERFORMANCE_BOXES 0 - -#define R128_PCIGART_TABLE_SIZE 32768 - -#define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) -#define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) -#define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) -#define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) - -#define R128_WRITE_PLL(addr,val) \ -do { \ - R128_WRITE8(R128_CLOCK_CNTL_INDEX, \ - ((addr) & 0x1f) | R128_PLL_WR_EN); \ - R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ -} while (0) - -#define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \ - ((n) << 16) | ((reg) >> 2)) -#define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \ - (((reg1) >> 2) << 11) | ((reg0) >> 2)) -#define CCE_PACKET2() (R128_CCE_PACKET2) -#define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \ - (pkt) | ((n) << 16)) - -static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv) -{ - drm_r128_ring_buffer_t *ring = &dev_priv->ring; - ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32); - if (ring->space <= 0) - ring->space += ring->size; -} - -/* ================================================================ - * Misc helper macros - */ - -#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ -do { \ - drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \ - if ( ring->space < ring->high_mark ) { \ - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \ - r128_update_ring_snapshot( dev_priv ); \ - if ( ring->space >= ring->high_mark ) \ - goto __ring_space_done; \ - DRM_UDELAY(1); \ - } \ - DRM_ERROR( "ring space check failed!\n" ); \ - return -EBUSY; \ - } \ - __ring_space_done: \ - ; \ -} while (0) - -#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ -do { \ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \ - if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \ - int __ret = r128_do_cce_idle( dev_priv ); \ - if ( __ret ) return __ret; \ - sarea_priv->last_dispatch = 0; \ - r128_freelist_reset( dev ); \ - } \ -} while (0) - -#define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \ - OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \ - OUT_RING( R128_EVENT_CRTC_OFFSET ); \ -} while (0) - -/* ================================================================ - * Ring control - */ - -#define R128_VERBOSE 0 - -#define RING_LOCALS \ - int write, _nr; unsigned int tail_mask; volatile u32 *ring; - -#define BEGIN_RING( n ) do { \ - if ( R128_VERBOSE ) { \ - DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ - } \ - if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ - COMMIT_RING(); \ - r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \ - } \ - _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ - ring = dev_priv->ring.start; \ - write = dev_priv->ring.tail; \ - tail_mask = dev_priv->ring.tail_mask; \ -} while (0) - -/* You can set this to zero if you want. If the card locks up, you'll - * need to keep this set. It works around a bug in early revs of the - * Rage 128 chipset, where the CCE would read 32 dwords past the end of - * the ring buffer before wrapping around. - */ -#define R128_BROKEN_CCE 1 - -#define ADVANCE_RING() do { \ - if ( R128_VERBOSE ) { \ - DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ - write, dev_priv->ring.tail ); \ - } \ - if ( R128_BROKEN_CCE && write < 32 ) { \ - memcpy( dev_priv->ring.end, \ - dev_priv->ring.start, \ - write * sizeof(u32) ); \ - } \ - if (((dev_priv->ring.tail + _nr) & tail_mask) != write) { \ - DRM_ERROR( \ - "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ - ((dev_priv->ring.tail + _nr) & tail_mask), \ - write, __LINE__); \ - } else \ - dev_priv->ring.tail = write; \ -} while (0) - -#define COMMIT_RING() do { \ - if ( R128_VERBOSE ) { \ - DRM_INFO( "COMMIT_RING() tail=0x%06x\n", \ - dev_priv->ring.tail ); \ - } \ - DRM_MEMORYBARRIER(); \ - R128_WRITE( R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail ); \ - R128_READ( R128_PM4_BUFFER_DL_WPTR ); \ -} while (0) - -#define OUT_RING( x ) do { \ - if ( R128_VERBOSE ) { \ - DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ - (unsigned int)(x), write ); \ - } \ - ring[write++] = cpu_to_le32( x ); \ - write &= tail_mask; \ -} while (0) - -#endif /* __R128_DRV_H__ */ diff --git a/shared-core/r128_irq.c b/shared-core/r128_irq.c deleted file mode 100644 index 86e5daa9..00000000 --- a/shared-core/r128_irq.c +++ /dev/null @@ -1,116 +0,0 @@ -/* r128_irq.c -- IRQ handling for radeon -*- linux-c -*- */ -/* - * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * - * The Weather Channel (TM) funded Tungsten Graphics to develop the - * initial release of the Radeon 8500 driver under the XFree86 license. - * This notice must be preserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Keith Whitwell - * Eric Anholt - */ - -#include "drmP.h" -#include "drm.h" -#include "r128_drm.h" -#include "r128_drv.h" - -u32 r128_get_vblank_counter(struct drm_device *dev, int crtc) -{ - const drm_r128_private_t *dev_priv = dev->dev_private; - - if (crtc != 0) - return 0; - - return atomic_read(&dev_priv->vbl_received); -} - -irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS) -{ - struct drm_device *dev = (struct drm_device *) arg; - drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; - int status; - - status = R128_READ(R128_GEN_INT_STATUS); - - /* VBLANK interrupt */ - if (status & R128_CRTC_VBLANK_INT) { - R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK); - atomic_inc(&dev_priv->vbl_received); - drm_handle_vblank(dev, 0); - return IRQ_HANDLED; - } - return IRQ_NONE; -} - -int r128_enable_vblank(struct drm_device *dev, int crtc) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - - if (crtc != 0) { - DRM_ERROR("%s: bad crtc %d\n", __FUNCTION__, crtc); - return -EINVAL; - } - - R128_WRITE(R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN); - return 0; -} - -void r128_disable_vblank(struct drm_device *dev, int crtc) -{ - if (crtc != 0) - DRM_ERROR("%s: bad crtc %d\n", __FUNCTION__, crtc); - - /* - * FIXME: implement proper interrupt disable by using the vblank - * counter register (if available) - * - * R128_WRITE(R128_GEN_INT_CNTL, - * R128_READ(R128_GEN_INT_CNTL) & ~R128_CRTC_VBLANK_INT_EN); - */ -} - -void r128_driver_irq_preinstall(struct drm_device * dev) -{ - drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; - - /* Disable *all* interrupts */ - R128_WRITE(R128_GEN_INT_CNTL, 0); - /* Clear vblank bit if it's already high */ - R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK); -} - -int r128_driver_irq_postinstall(struct drm_device * dev) -{ - return 0; -} - -void r128_driver_irq_uninstall(struct drm_device * dev) -{ - drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; - if (!dev_priv) - return; - - /* Disable *all* interrupts */ - R128_WRITE(R128_GEN_INT_CNTL, 0); -} diff --git a/shared-core/r128_state.c b/shared-core/r128_state.c deleted file mode 100644 index 51a9afce..00000000 --- a/shared-core/r128_state.c +++ /dev/null @@ -1,1681 +0,0 @@ -/* r128_state.c -- State support for r128 -*- linux-c -*- - * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com - */ -/* - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - */ - -#include "drmP.h" -#include "drm.h" -#include "r128_drm.h" -#include "r128_drv.h" - -/* ================================================================ - * CCE hardware state programming functions - */ - -static void r128_emit_clip_rects(drm_r128_private_t * dev_priv, - struct drm_clip_rect * boxes, int count) -{ - u32 aux_sc_cntl = 0x00000000; - RING_LOCALS; - DRM_DEBUG("\n"); - - BEGIN_RING((count < 3 ? count : 3) * 5 + 2); - - if (count >= 1) { - OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3)); - OUT_RING(boxes[0].x1); - OUT_RING(boxes[0].x2 - 1); - OUT_RING(boxes[0].y1); - OUT_RING(boxes[0].y2 - 1); - - aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR); - } - if (count >= 2) { - OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3)); - OUT_RING(boxes[1].x1); - OUT_RING(boxes[1].x2 - 1); - OUT_RING(boxes[1].y1); - OUT_RING(boxes[1].y2 - 1); - - aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR); - } - if (count >= 3) { - OUT_RING(CCE_PACKET0(R128_AUX3_SC_LEFT, 3)); - OUT_RING(boxes[2].x1); - OUT_RING(boxes[2].x2 - 1); - OUT_RING(boxes[2].y1); - OUT_RING(boxes[2].y2 - 1); - - aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR); - } - - OUT_RING(CCE_PACKET0(R128_AUX_SC_CNTL, 0)); - OUT_RING(aux_sc_cntl); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_core(drm_r128_private_t * dev_priv) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - RING_LOCALS; - DRM_DEBUG("\n"); - - BEGIN_RING(2); - - OUT_RING(CCE_PACKET0(R128_SCALE_3D_CNTL, 0)); - OUT_RING(ctx->scale_3d_cntl); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_context(drm_r128_private_t * dev_priv) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - RING_LOCALS; - DRM_DEBUG("\n"); - - BEGIN_RING(13); - - OUT_RING(CCE_PACKET0(R128_DST_PITCH_OFFSET_C, 11)); - OUT_RING(ctx->dst_pitch_offset_c); - OUT_RING(ctx->dp_gui_master_cntl_c); - OUT_RING(ctx->sc_top_left_c); - OUT_RING(ctx->sc_bottom_right_c); - OUT_RING(ctx->z_offset_c); - OUT_RING(ctx->z_pitch_c); - OUT_RING(ctx->z_sten_cntl_c); - OUT_RING(ctx->tex_cntl_c); - OUT_RING(ctx->misc_3d_state_cntl_reg); - OUT_RING(ctx->texture_clr_cmp_clr_c); - OUT_RING(ctx->texture_clr_cmp_msk_c); - OUT_RING(ctx->fog_color_c); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_setup(drm_r128_private_t * dev_priv) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - RING_LOCALS; - DRM_DEBUG("\n"); - - BEGIN_RING(3); - - OUT_RING(CCE_PACKET1(R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP)); - OUT_RING(ctx->setup_cntl); - OUT_RING(ctx->pm4_vc_fpu_setup); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_masks(drm_r128_private_t * dev_priv) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - RING_LOCALS; - DRM_DEBUG("\n"); - - BEGIN_RING(5); - - OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0)); - OUT_RING(ctx->dp_write_mask); - - OUT_RING(CCE_PACKET0(R128_STEN_REF_MASK_C, 1)); - OUT_RING(ctx->sten_ref_mask_c); - OUT_RING(ctx->plane_3d_mask_c); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_window(drm_r128_private_t * dev_priv) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - RING_LOCALS; - DRM_DEBUG("\n"); - - BEGIN_RING(2); - - OUT_RING(CCE_PACKET0(R128_WINDOW_XY_OFFSET, 0)); - OUT_RING(ctx->window_xy_offset); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_tex0(drm_r128_private_t * dev_priv) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0]; - int i; - RING_LOCALS; - DRM_DEBUG("\n"); - - BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS); - - OUT_RING(CCE_PACKET0(R128_PRIM_TEX_CNTL_C, - 2 + R128_MAX_TEXTURE_LEVELS)); - OUT_RING(tex->tex_cntl); - OUT_RING(tex->tex_combine_cntl); - OUT_RING(ctx->tex_size_pitch_c); - for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) { - OUT_RING(tex->tex_offset[i]); - } - - OUT_RING(CCE_PACKET0(R128_CONSTANT_COLOR_C, 1)); - OUT_RING(ctx->constant_color_c); - OUT_RING(tex->tex_border_color); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_tex1(drm_r128_private_t * dev_priv) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1]; - int i; - RING_LOCALS; - DRM_DEBUG("\n"); - - BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS); - - OUT_RING(CCE_PACKET0(R128_SEC_TEX_CNTL_C, 1 + R128_MAX_TEXTURE_LEVELS)); - OUT_RING(tex->tex_cntl); - OUT_RING(tex->tex_combine_cntl); - for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) { - OUT_RING(tex->tex_offset[i]); - } - - OUT_RING(CCE_PACKET0(R128_SEC_TEXTURE_BORDER_COLOR_C, 0)); - OUT_RING(tex->tex_border_color); - - ADVANCE_RING(); -} - -static void r128_emit_state(drm_r128_private_t * dev_priv) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int dirty = sarea_priv->dirty; - - DRM_DEBUG("dirty=0x%08x\n", dirty); - - if (dirty & R128_UPLOAD_CORE) { - r128_emit_core(dev_priv); - sarea_priv->dirty &= ~R128_UPLOAD_CORE; - } - - if (dirty & R128_UPLOAD_CONTEXT) { - r128_emit_context(dev_priv); - sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT; - } - - if (dirty & R128_UPLOAD_SETUP) { - r128_emit_setup(dev_priv); - sarea_priv->dirty &= ~R128_UPLOAD_SETUP; - } - - if (dirty & R128_UPLOAD_MASKS) { - r128_emit_masks(dev_priv); - sarea_priv->dirty &= ~R128_UPLOAD_MASKS; - } - - if (dirty & R128_UPLOAD_WINDOW) { - r128_emit_window(dev_priv); - sarea_priv->dirty &= ~R128_UPLOAD_WINDOW; - } - - if (dirty & R128_UPLOAD_TEX0) { - r128_emit_tex0(dev_priv); - sarea_priv->dirty &= ~R128_UPLOAD_TEX0; - } - - if (dirty & R128_UPLOAD_TEX1) { - r128_emit_tex1(dev_priv); - sarea_priv->dirty &= ~R128_UPLOAD_TEX1; - } - - /* Turn off the texture cache flushing */ - sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH; - - sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE; -} - -#if R128_PERFORMANCE_BOXES -/* ================================================================ - * Performance monitoring functions - */ - -static void r128_clear_box(drm_r128_private_t * dev_priv, - int x, int y, int w, int h, int r, int g, int b) -{ - u32 pitch, offset; - u32 fb_bpp, color; - RING_LOCALS; - - switch (dev_priv->fb_bpp) { - case 16: - fb_bpp = R128_GMC_DST_16BPP; - color = (((r & 0xf8) << 8) | - ((g & 0xfc) << 3) | ((b & 0xf8) >> 3)); - break; - case 24: - fb_bpp = R128_GMC_DST_24BPP; - color = ((r << 16) | (g << 8) | b); - break; - case 32: - fb_bpp = R128_GMC_DST_32BPP; - color = (((0xff) << 24) | (r << 16) | (g << 8) | b); - break; - default: - return; - } - - offset = dev_priv->back_offset; - pitch = dev_priv->back_pitch >> 3; - - BEGIN_RING(6); - - OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); - OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - fb_bpp | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS); - - OUT_RING((pitch << 21) | (offset >> 5)); - OUT_RING(color); - - OUT_RING((x << 16) | y); - OUT_RING((w << 16) | h); - - ADVANCE_RING(); -} - -static void r128_cce_performance_boxes(drm_r128_private_t * dev_priv) -{ - if (atomic_read(&dev_priv->idle_count) == 0) { - r128_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0); - } else { - atomic_set(&dev_priv->idle_count, 0); - } -} - -#endif - -/* ================================================================ - * CCE command dispatch functions - */ - -static void r128_print_dirty(const char *msg, unsigned int flags) -{ - DRM_INFO("%s: (0x%x) %s%s%s%s%s%s%s%s%s\n", - msg, - flags, - (flags & R128_UPLOAD_CORE) ? "core, " : "", - (flags & R128_UPLOAD_CONTEXT) ? "context, " : "", - (flags & R128_UPLOAD_SETUP) ? "setup, " : "", - (flags & R128_UPLOAD_TEX0) ? "tex0, " : "", - (flags & R128_UPLOAD_TEX1) ? "tex1, " : "", - (flags & R128_UPLOAD_MASKS) ? "masks, " : "", - (flags & R128_UPLOAD_WINDOW) ? "window, " : "", - (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "", - (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : ""); -} - -static void r128_cce_dispatch_clear(struct drm_device * dev, - drm_r128_clear_t * clear) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - int nbox = sarea_priv->nbox; - struct drm_clip_rect *pbox = sarea_priv->boxes; - unsigned int flags = clear->flags; - int i; - RING_LOCALS; - DRM_DEBUG("\n"); - - if (dev_priv->page_flipping && dev_priv->current_page == 1) { - unsigned int tmp = flags; - - flags &= ~(R128_FRONT | R128_BACK); - if (tmp & R128_FRONT) - flags |= R128_BACK; - if (tmp & R128_BACK) - flags |= R128_FRONT; - } - - for (i = 0; i < nbox; i++) { - int x = pbox[i].x1; - int y = pbox[i].y1; - int w = pbox[i].x2 - x; - int h = pbox[i].y2 - y; - - DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n", - pbox[i].x1, pbox[i].y1, pbox[i].x2, - pbox[i].y2, flags); - - if (flags & (R128_FRONT | R128_BACK)) { - BEGIN_RING(2); - - OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0)); - OUT_RING(clear->color_mask); - - ADVANCE_RING(); - } - - if (flags & R128_FRONT) { - BEGIN_RING(6); - - OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); - OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS); - - OUT_RING(dev_priv->front_pitch_offset_c); - OUT_RING(clear->clear_color); - - OUT_RING((x << 16) | y); - OUT_RING((w << 16) | h); - - ADVANCE_RING(); - } - - if (flags & R128_BACK) { - BEGIN_RING(6); - - OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); - OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS); - - OUT_RING(dev_priv->back_pitch_offset_c); - OUT_RING(clear->clear_color); - - OUT_RING((x << 16) | y); - OUT_RING((w << 16) | h); - - ADVANCE_RING(); - } - - if (flags & R128_DEPTH) { - BEGIN_RING(6); - - OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); - OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS); - - OUT_RING(dev_priv->depth_pitch_offset_c); - OUT_RING(clear->clear_depth); - - OUT_RING((x << 16) | y); - OUT_RING((w << 16) | h); - - ADVANCE_RING(); - } - } -} - -static void r128_cce_dispatch_swap(struct drm_device * dev) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - int nbox = sarea_priv->nbox; - struct drm_clip_rect *pbox = sarea_priv->boxes; - int i; - RING_LOCALS; - DRM_DEBUG("\n"); - -#if R128_PERFORMANCE_BOXES - /* Do some trivial performance monitoring... - */ - r128_cce_performance_boxes(dev_priv); -#endif - - for (i = 0; i < nbox; i++) { - int x = pbox[i].x1; - int y = pbox[i].y1; - int w = pbox[i].x2 - x; - int h = pbox[i].y2 - y; - - BEGIN_RING(7); - - OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); - OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | - R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (dev_priv->color_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_MEMORY | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS); - - /* Make this work even if front & back are flipped: - */ - if (dev_priv->current_page == 0) { - OUT_RING(dev_priv->back_pitch_offset_c); - OUT_RING(dev_priv->front_pitch_offset_c); - } else { - OUT_RING(dev_priv->front_pitch_offset_c); - OUT_RING(dev_priv->back_pitch_offset_c); - } - - OUT_RING((x << 16) | y); - OUT_RING((x << 16) | y); - OUT_RING((w << 16) | h); - - ADVANCE_RING(); - } - - /* Increment the frame counter. The client-side 3D driver must - * throttle the framerate by waiting for this value before - * performing the swapbuffer ioctl. - */ - dev_priv->sarea_priv->last_frame++; - - BEGIN_RING(2); - - OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0)); - OUT_RING(dev_priv->sarea_priv->last_frame); - - ADVANCE_RING(); -} - -static void r128_cce_dispatch_flip(struct drm_device * dev) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - RING_LOCALS; - DRM_DEBUG("page=%d pfCurrentPage=%d\n", - dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage); - -#if R128_PERFORMANCE_BOXES - /* Do some trivial performance monitoring... - */ - r128_cce_performance_boxes(dev_priv); -#endif - - BEGIN_RING(4); - - R128_WAIT_UNTIL_PAGE_FLIPPED(); - OUT_RING(CCE_PACKET0(R128_CRTC_OFFSET, 0)); - - if (dev_priv->current_page == 0) { - OUT_RING(dev_priv->back_offset); - } else { - OUT_RING(dev_priv->front_offset); - } - - ADVANCE_RING(); - - /* Increment the frame counter. The client-side 3D driver must - * throttle the framerate by waiting for this value before - * performing the swapbuffer ioctl. - */ - dev_priv->sarea_priv->last_frame++; - dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = - 1 - dev_priv->current_page; - - BEGIN_RING(2); - - OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0)); - OUT_RING(dev_priv->sarea_priv->last_frame); - - ADVANCE_RING(); -} - -static void r128_cce_dispatch_vertex(struct drm_device * dev, struct drm_buf * buf) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_buf_priv_t *buf_priv = buf->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - int format = sarea_priv->vc_format; - int offset = buf->bus_address; - int size = buf->used; - int prim = buf_priv->prim; - int i = 0; - RING_LOCALS; - DRM_DEBUG("buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox); - - if (0) - r128_print_dirty("dispatch_vertex", sarea_priv->dirty); - - if (buf->used) { - buf_priv->dispatched = 1; - - if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) { - r128_emit_state(dev_priv); - } - - do { - /* Emit the next set of up to three cliprects */ - if (i < sarea_priv->nbox) { - r128_emit_clip_rects(dev_priv, - &sarea_priv->boxes[i], - sarea_priv->nbox - i); - } - - /* Emit the vertex buffer rendering commands */ - BEGIN_RING(5); - - OUT_RING(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 3)); - OUT_RING(offset); - OUT_RING(size); - OUT_RING(format); - OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | - (size << R128_CCE_VC_CNTL_NUM_SHIFT)); - - ADVANCE_RING(); - - i += 3; - } while (i < sarea_priv->nbox); - } - - if (buf_priv->discard) { - buf_priv->age = dev_priv->sarea_priv->last_dispatch; - - /* Emit the vertex buffer age */ - BEGIN_RING(2); - - OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); - OUT_RING(buf_priv->age); - - ADVANCE_RING(); - - buf->pending = 1; - buf->used = 0; - /* FIXME: Check dispatched field */ - buf_priv->dispatched = 0; - } - - dev_priv->sarea_priv->last_dispatch++; - - sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; - sarea_priv->nbox = 0; -} - -static void r128_cce_dispatch_indirect(struct drm_device * dev, - struct drm_buf * buf, int start, int end) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_buf_priv_t *buf_priv = buf->dev_private; - RING_LOCALS; - DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end); - - if (start != end) { - int offset = buf->bus_address + start; - int dwords = (end - start + 3) / sizeof(u32); - - /* Indirect buffer data must be an even number of - * dwords, so if we've been given an odd number we must - * pad the data with a Type-2 CCE packet. - */ - if (dwords & 1) { - u32 *data = (u32 *) - ((char *)dev->agp_buffer_map->handle - + buf->offset + start); - data[dwords++] = cpu_to_le32(R128_CCE_PACKET2); - } - - buf_priv->dispatched = 1; - - /* Fire off the indirect buffer */ - BEGIN_RING(3); - - OUT_RING(CCE_PACKET0(R128_PM4_IW_INDOFF, 1)); - OUT_RING(offset); - OUT_RING(dwords); - - ADVANCE_RING(); - } - - if (buf_priv->discard) { - buf_priv->age = dev_priv->sarea_priv->last_dispatch; - - /* Emit the indirect buffer age */ - BEGIN_RING(2); - - OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); - OUT_RING(buf_priv->age); - - ADVANCE_RING(); - - buf->pending = 1; - buf->used = 0; - /* FIXME: Check dispatched field */ - buf_priv->dispatched = 0; - } - - dev_priv->sarea_priv->last_dispatch++; -} - -static void r128_cce_dispatch_indices(struct drm_device * dev, - struct drm_buf * buf, - int start, int end, int count) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_buf_priv_t *buf_priv = buf->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - int format = sarea_priv->vc_format; - int offset = dev->agp_buffer_map->offset - dev_priv->cce_buffers_offset; - int prim = buf_priv->prim; - u32 *data; - int dwords; - int i = 0; - RING_LOCALS; - DRM_DEBUG("indices: s=%d e=%d c=%d\n", start, end, count); - - if (0) - r128_print_dirty("dispatch_indices", sarea_priv->dirty); - - if (start != end) { - buf_priv->dispatched = 1; - - if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) { - r128_emit_state(dev_priv); - } - - dwords = (end - start + 3) / sizeof(u32); - - data = (u32 *) ((char *)dev->agp_buffer_map->handle - + buf->offset + start); - - data[0] = cpu_to_le32(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, - dwords - 2)); - - data[1] = cpu_to_le32(offset); - data[2] = cpu_to_le32(R128_MAX_VB_VERTS); - data[3] = cpu_to_le32(format); - data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | - (count << 16))); - - if (count & 0x1) { -#ifdef __LITTLE_ENDIAN - data[dwords - 1] &= 0x0000ffff; -#else - data[dwords - 1] &= 0xffff0000; -#endif - } - - do { - /* Emit the next set of up to three cliprects */ - if (i < sarea_priv->nbox) { - r128_emit_clip_rects(dev_priv, - &sarea_priv->boxes[i], - sarea_priv->nbox - i); - } - - r128_cce_dispatch_indirect(dev, buf, start, end); - - i += 3; - } while (i < sarea_priv->nbox); - } - - if (buf_priv->discard) { - buf_priv->age = dev_priv->sarea_priv->last_dispatch; - - /* Emit the vertex buffer age */ - BEGIN_RING(2); - - OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); - OUT_RING(buf_priv->age); - - ADVANCE_RING(); - - buf->pending = 1; - /* FIXME: Check dispatched field */ - buf_priv->dispatched = 0; - } - - dev_priv->sarea_priv->last_dispatch++; - - sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; - sarea_priv->nbox = 0; -} - -static int r128_cce_dispatch_blit(struct drm_device * dev, - struct drm_file *file_priv, - drm_r128_blit_t * blit) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - struct drm_device_dma *dma = dev->dma; - struct drm_buf *buf; - drm_r128_buf_priv_t *buf_priv; - u32 *data; - int dword_shift, dwords; - RING_LOCALS; - DRM_DEBUG("\n"); - - /* The compiler won't optimize away a division by a variable, - * even if the only legal values are powers of two. Thus, we'll - * use a shift instead. - */ - switch (blit->format) { - case R128_DATATYPE_ARGB8888: - dword_shift = 0; - break; - case R128_DATATYPE_ARGB1555: - case R128_DATATYPE_RGB565: - case R128_DATATYPE_ARGB4444: - case R128_DATATYPE_YVYU422: - case R128_DATATYPE_VYUY422: - dword_shift = 1; - break; - case R128_DATATYPE_CI8: - case R128_DATATYPE_RGB8: - dword_shift = 2; - break; - default: - DRM_ERROR("invalid blit format %d\n", blit->format); - return -EINVAL; - } - - /* Flush the pixel cache, and mark the contents as Read Invalid. - * This ensures no pixel data gets mixed up with the texture - * data from the host data blit, otherwise part of the texture - * image may be corrupted. - */ - BEGIN_RING(2); - - OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0)); - OUT_RING(R128_PC_RI_GUI | R128_PC_FLUSH_GUI); - - ADVANCE_RING(); - - /* Dispatch the indirect buffer. - */ - buf = dma->buflist[blit->idx]; - buf_priv = buf->dev_private; - - if (buf->file_priv != file_priv) { - DRM_ERROR("process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->file_priv); - return -EINVAL; - } - if (buf->pending) { - DRM_ERROR("sending pending buffer %d\n", blit->idx); - return -EINVAL; - } - - buf_priv->discard = 1; - - dwords = (blit->width * blit->height) >> dword_shift; - - data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); - - data[0] = cpu_to_le32(CCE_PACKET3(R128_CNTL_HOSTDATA_BLT, dwords + 6)); - data[1] = cpu_to_le32((R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (blit->format << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_HOST_DATA | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS)); - - data[2] = cpu_to_le32((blit->pitch << 21) | (blit->offset >> 5)); - data[3] = cpu_to_le32(0xffffffff); - data[4] = cpu_to_le32(0xffffffff); - data[5] = cpu_to_le32((blit->y << 16) | blit->x); - data[6] = cpu_to_le32((blit->height << 16) | blit->width); - data[7] = cpu_to_le32(dwords); - - buf->used = (dwords + 8) * sizeof(u32); - - r128_cce_dispatch_indirect(dev, buf, 0, buf->used); - - /* Flush the pixel cache after the blit completes. This ensures - * the texture data is written out to memory before rendering - * continues. - */ - BEGIN_RING(2); - - OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0)); - OUT_RING(R128_PC_FLUSH_GUI); - - ADVANCE_RING(); - - return 0; -} - -/* ================================================================ - * Tiled depth buffer management - * - * FIXME: These should all set the destination write mask for when we - * have hardware stencil support. - */ - -static int r128_cce_dispatch_write_span(struct drm_device * dev, - drm_r128_depth_t * depth) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - int count, x, y; - u32 *buffer; - u8 *mask; - int i, buffer_size, mask_size; - RING_LOCALS; - DRM_DEBUG("\n"); - - count = depth->n; - if (count > 4096 || count <= 0) - return -EMSGSIZE; - - if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) { - return -EFAULT; - } - if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) { - return -EFAULT; - } - - buffer_size = depth->n * sizeof(u32); - buffer = drm_alloc(buffer_size, DRM_MEM_BUFS); - if (buffer == NULL) - return -ENOMEM; - if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) { - drm_free(buffer, buffer_size, DRM_MEM_BUFS); - return -EFAULT; - } - - mask_size = depth->n * sizeof(u8); - if (depth->mask) { - mask = drm_alloc(mask_size, DRM_MEM_BUFS); - if (mask == NULL) { - drm_free(buffer, buffer_size, DRM_MEM_BUFS); - return -ENOMEM; - } - if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) { - drm_free(buffer, buffer_size, DRM_MEM_BUFS); - drm_free(mask, mask_size, DRM_MEM_BUFS); - return -EFAULT; - } - - for (i = 0; i < count; i++, x++) { - if (mask[i]) { - BEGIN_RING(6); - - OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); - OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS); - - OUT_RING(dev_priv->depth_pitch_offset_c); - OUT_RING(buffer[i]); - - OUT_RING((x << 16) | y); - OUT_RING((1 << 16) | 1); - - ADVANCE_RING(); - } - } - - drm_free(mask, mask_size, DRM_MEM_BUFS); - } else { - for (i = 0; i < count; i++, x++) { - BEGIN_RING(6); - - OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); - OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS); - - OUT_RING(dev_priv->depth_pitch_offset_c); - OUT_RING(buffer[i]); - - OUT_RING((x << 16) | y); - OUT_RING((1 << 16) | 1); - - ADVANCE_RING(); - } - } - - drm_free(buffer, buffer_size, DRM_MEM_BUFS); - - return 0; -} - -static int r128_cce_dispatch_write_pixels(struct drm_device * dev, - drm_r128_depth_t * depth) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - int count, *x, *y; - u32 *buffer; - u8 *mask; - int i, xbuf_size, ybuf_size, buffer_size, mask_size; - RING_LOCALS; - DRM_DEBUG("\n"); - - count = depth->n; - if (count > 4096 || count <= 0) - return -EMSGSIZE; - - xbuf_size = count * sizeof(*x); - ybuf_size = count * sizeof(*y); - x = drm_alloc(xbuf_size, DRM_MEM_BUFS); - if (x == NULL) { - return -ENOMEM; - } - y = drm_alloc(ybuf_size, DRM_MEM_BUFS); - if (y == NULL) { - drm_free(x, xbuf_size, DRM_MEM_BUFS); - return -ENOMEM; - } - if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) { - drm_free(x, xbuf_size, DRM_MEM_BUFS); - drm_free(y, ybuf_size, DRM_MEM_BUFS); - return -EFAULT; - } - if (DRM_COPY_FROM_USER(y, depth->y, xbuf_size)) { - drm_free(x, xbuf_size, DRM_MEM_BUFS); - drm_free(y, ybuf_size, DRM_MEM_BUFS); - return -EFAULT; - } - - buffer_size = depth->n * sizeof(u32); - buffer = drm_alloc(buffer_size, DRM_MEM_BUFS); - if (buffer == NULL) { - drm_free(x, xbuf_size, DRM_MEM_BUFS); - drm_free(y, ybuf_size, DRM_MEM_BUFS); - return -ENOMEM; - } - if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) { - drm_free(x, xbuf_size, DRM_MEM_BUFS); - drm_free(y, ybuf_size, DRM_MEM_BUFS); - drm_free(buffer, buffer_size, DRM_MEM_BUFS); - return -EFAULT; - } - - if (depth->mask) { - mask_size = depth->n * sizeof(u8); - mask = drm_alloc(mask_size, DRM_MEM_BUFS); - if (mask == NULL) { - drm_free(x, xbuf_size, DRM_MEM_BUFS); - drm_free(y, ybuf_size, DRM_MEM_BUFS); - drm_free(buffer, buffer_size, DRM_MEM_BUFS); - return -ENOMEM; - } - if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) { - drm_free(x, xbuf_size, DRM_MEM_BUFS); - drm_free(y, ybuf_size, DRM_MEM_BUFS); - drm_free(buffer, buffer_size, DRM_MEM_BUFS); - drm_free(mask, mask_size, DRM_MEM_BUFS); - return -EFAULT; - } - - for (i = 0; i < count; i++) { - if (mask[i]) { - BEGIN_RING(6); - - OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); - OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS); - - OUT_RING(dev_priv->depth_pitch_offset_c); - OUT_RING(buffer[i]); - - OUT_RING((x[i] << 16) | y[i]); - OUT_RING((1 << 16) | 1); - - ADVANCE_RING(); - } - } - - drm_free(mask, mask_size, DRM_MEM_BUFS); - } else { - for (i = 0; i < count; i++) { - BEGIN_RING(6); - - OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); - OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS); - - OUT_RING(dev_priv->depth_pitch_offset_c); - OUT_RING(buffer[i]); - - OUT_RING((x[i] << 16) | y[i]); - OUT_RING((1 << 16) | 1); - - ADVANCE_RING(); - } - } - - drm_free(x, xbuf_size, DRM_MEM_BUFS); - drm_free(y, ybuf_size, DRM_MEM_BUFS); - drm_free(buffer, buffer_size, DRM_MEM_BUFS); - - return 0; -} - -static int r128_cce_dispatch_read_span(struct drm_device * dev, - drm_r128_depth_t * depth) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - int count, x, y; - RING_LOCALS; - DRM_DEBUG("\n"); - - count = depth->n; - if (count > 4096 || count <= 0) - return -EMSGSIZE; - - if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) { - return -EFAULT; - } - if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) { - return -EFAULT; - } - - BEGIN_RING(7); - - OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); - OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | - R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_MEMORY | - R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS); - - OUT_RING(dev_priv->depth_pitch_offset_c); - OUT_RING(dev_priv->span_pitch_offset_c); - - OUT_RING((x << 16) | y); - OUT_RING((0 << 16) | 0); - OUT_RING((count << 16) | 1); - - ADVANCE_RING(); - - return 0; -} - -static int r128_cce_dispatch_read_pixels(struct drm_device * dev, - drm_r128_depth_t * depth) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - int count, *x, *y; - int i, xbuf_size, ybuf_size; - RING_LOCALS; - DRM_DEBUG("\n"); - - count = depth->n; - if (count > 4096 || count <= 0) - return -EMSGSIZE; - - if (count > dev_priv->depth_pitch) { - count = dev_priv->depth_pitch; - } - - xbuf_size = count * sizeof(*x); - ybuf_size = count * sizeof(*y); - x = drm_alloc(xbuf_size, DRM_MEM_BUFS); - if (x == NULL) { - return -ENOMEM; - } - y = drm_alloc(ybuf_size, DRM_MEM_BUFS); - if (y == NULL) { - drm_free(x, xbuf_size, DRM_MEM_BUFS); - return -ENOMEM; - } - if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) { - drm_free(x, xbuf_size, DRM_MEM_BUFS); - drm_free(y, ybuf_size, DRM_MEM_BUFS); - return -EFAULT; - } - if (DRM_COPY_FROM_USER(y, depth->y, ybuf_size)) { - drm_free(x, xbuf_size, DRM_MEM_BUFS); - drm_free(y, ybuf_size, DRM_MEM_BUFS); - return -EFAULT; - } - - for (i = 0; i < count; i++) { - BEGIN_RING(7); - - OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); - OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | - R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_MEMORY | - R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS); - - OUT_RING(dev_priv->depth_pitch_offset_c); - OUT_RING(dev_priv->span_pitch_offset_c); - - OUT_RING((x[i] << 16) | y[i]); - OUT_RING((i << 16) | 0); - OUT_RING((1 << 16) | 1); - - ADVANCE_RING(); - } - - drm_free(x, xbuf_size, DRM_MEM_BUFS); - drm_free(y, ybuf_size, DRM_MEM_BUFS); - - return 0; -} - -/* ================================================================ - * Polygon stipple - */ - -static void r128_cce_dispatch_stipple(struct drm_device * dev, u32 * stipple) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - int i; - RING_LOCALS; - DRM_DEBUG("\n"); - - BEGIN_RING(33); - - OUT_RING(CCE_PACKET0(R128_BRUSH_DATA0, 31)); - for (i = 0; i < 32; i++) { - OUT_RING(stipple[i]); - } - - ADVANCE_RING(); -} - -/* ================================================================ - * IOCTL functions - */ - -static int r128_cce_clear(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_clear_t *clear = data; - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - - if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) - sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; - - r128_cce_dispatch_clear(dev, clear); - COMMIT_RING(); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS; - - return 0; -} - -static int r128_do_init_pageflip(struct drm_device * dev) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG("\n"); - - dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET); - dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL); - - R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset); - R128_WRITE(R128_CRTC_OFFSET_CNTL, - dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL); - - dev_priv->page_flipping = 1; - dev_priv->current_page = 0; - dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page; - - return 0; -} - -static int r128_do_cleanup_pageflip(struct drm_device * dev) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG("\n"); - - R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset); - R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl); - - if (dev_priv->current_page != 0) { - r128_cce_dispatch_flip(dev); - COMMIT_RING(); - } - - dev_priv->page_flipping = 0; - return 0; -} - -/* Swapping and flipping are different operations, need different ioctls. - * They can & should be intermixed to support multiple 3d windows. - */ - -static int r128_cce_flip(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - - if (!dev_priv->page_flipping) - r128_do_init_pageflip(dev); - - r128_cce_dispatch_flip(dev); - - COMMIT_RING(); - return 0; -} - -static int r128_cce_swap(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - - if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) - sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; - - r128_cce_dispatch_swap(dev); - dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT | - R128_UPLOAD_MASKS); - - COMMIT_RING(); - return 0; -} - -static int r128_cce_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - struct drm_device_dma *dma = dev->dma; - struct drm_buf *buf; - drm_r128_buf_priv_t *buf_priv; - drm_r128_vertex_t *vertex = data; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", - DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard); - - if (vertex->idx < 0 || vertex->idx >= dma->buf_count) { - DRM_ERROR("buffer index %d (of %d max)\n", - vertex->idx, dma->buf_count - 1); - return -EINVAL; - } - if (vertex->prim < 0 || - vertex->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { - DRM_ERROR("buffer prim %d\n", vertex->prim); - return -EINVAL; - } - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - VB_AGE_TEST_WITH_RETURN(dev_priv); - - buf = dma->buflist[vertex->idx]; - buf_priv = buf->dev_private; - - if (buf->file_priv != file_priv) { - DRM_ERROR("process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->file_priv); - return -EINVAL; - } - if (buf->pending) { - DRM_ERROR("sending pending buffer %d\n", vertex->idx); - return -EINVAL; - } - - buf->used = vertex->count; - buf_priv->prim = vertex->prim; - buf_priv->discard = vertex->discard; - - r128_cce_dispatch_vertex(dev, buf); - - COMMIT_RING(); - return 0; -} - -static int r128_cce_indices(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - struct drm_device_dma *dma = dev->dma; - struct drm_buf *buf; - drm_r128_buf_priv_t *buf_priv; - drm_r128_indices_t *elts = data; - int count; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, - elts->idx, elts->start, elts->end, elts->discard); - - if (elts->idx < 0 || elts->idx >= dma->buf_count) { - DRM_ERROR("buffer index %d (of %d max)\n", - elts->idx, dma->buf_count - 1); - return -EINVAL; - } - if (elts->prim < 0 || - elts->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { - DRM_ERROR("buffer prim %d\n", elts->prim); - return -EINVAL; - } - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - VB_AGE_TEST_WITH_RETURN(dev_priv); - - buf = dma->buflist[elts->idx]; - buf_priv = buf->dev_private; - - if (buf->file_priv != file_priv) { - DRM_ERROR("process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->file_priv); - return -EINVAL; - } - if (buf->pending) { - DRM_ERROR("sending pending buffer %d\n", elts->idx); - return -EINVAL; - } - - count = (elts->end - elts->start) / sizeof(u16); - elts->start -= R128_INDEX_PRIM_OFFSET; - - if (elts->start & 0x7) { - DRM_ERROR("misaligned buffer 0x%x\n", elts->start); - return -EINVAL; - } - if (elts->start < buf->used) { - DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used); - return -EINVAL; - } - - buf->used = elts->end; - buf_priv->prim = elts->prim; - buf_priv->discard = elts->discard; - - r128_cce_dispatch_indices(dev, buf, elts->start, elts->end, count); - - COMMIT_RING(); - return 0; -} - -static int r128_cce_blit(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - struct drm_device_dma *dma = dev->dma; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_blit_t *blit = data; - int ret; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit->idx); - - if (blit->idx < 0 || blit->idx >= dma->buf_count) { - DRM_ERROR("buffer index %d (of %d max)\n", - blit->idx, dma->buf_count - 1); - return -EINVAL; - } - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - VB_AGE_TEST_WITH_RETURN(dev_priv); - - ret = r128_cce_dispatch_blit(dev, file_priv, blit); - - COMMIT_RING(); - return ret; -} - -static int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_depth_t *depth = data; - int ret; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - - ret = -EINVAL; - switch (depth->func) { - case R128_WRITE_SPAN: - ret = r128_cce_dispatch_write_span(dev, depth); - break; - case R128_WRITE_PIXELS: - ret = r128_cce_dispatch_write_pixels(dev, depth); - break; - case R128_READ_SPAN: - ret = r128_cce_dispatch_read_span(dev, depth); - break; - case R128_READ_PIXELS: - ret = r128_cce_dispatch_read_pixels(dev, depth); - break; - } - - COMMIT_RING(); - return ret; -} - -static int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_stipple_t *stipple = data; - u32 mask[32]; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32))) - return -EFAULT; - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - - r128_cce_dispatch_stipple(dev, mask); - - COMMIT_RING(); - return 0; -} - -static int r128_cce_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - struct drm_device_dma *dma = dev->dma; - struct drm_buf *buf; - drm_r128_buf_priv_t *buf_priv; - drm_r128_indirect_t *indirect = data; -#if 0 - RING_LOCALS; -#endif - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - DRM_DEBUG("idx=%d s=%d e=%d d=%d\n", - indirect->idx, indirect->start, indirect->end, - indirect->discard); - - if (indirect->idx < 0 || indirect->idx >= dma->buf_count) { - DRM_ERROR("buffer index %d (of %d max)\n", - indirect->idx, dma->buf_count - 1); - return -EINVAL; - } - - buf = dma->buflist[indirect->idx]; - buf_priv = buf->dev_private; - - if (buf->file_priv != file_priv) { - DRM_ERROR("process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->file_priv); - return -EINVAL; - } - if (buf->pending) { - DRM_ERROR("sending pending buffer %d\n", indirect->idx); - return -EINVAL; - } - - if (indirect->start < buf->used) { - DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", - indirect->start, buf->used); - return -EINVAL; - } - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - VB_AGE_TEST_WITH_RETURN(dev_priv); - - buf->used = indirect->end; - buf_priv->discard = indirect->discard; - -#if 0 - /* Wait for the 3D stream to idle before the indirect buffer - * containing 2D acceleration commands is processed. - */ - BEGIN_RING(2); - RADEON_WAIT_UNTIL_3D_IDLE(); - ADVANCE_RING(); -#endif - - /* Dispatch the indirect buffer full of commands from the - * X server. This is insecure and is thus only available to - * privileged clients. - */ - r128_cce_dispatch_indirect(dev, buf, indirect->start, indirect->end); - - COMMIT_RING(); - return 0; -} - -static int r128_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_getparam_t *param = data; - int value; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - - switch (param->param) { - case R128_PARAM_IRQ_NR: - value = dev->irq; - break; - default: - return -EINVAL; - } - - if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { - DRM_ERROR("copy_to_user\n"); - return -EFAULT; - } - - return 0; -} - -void r128_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) -{ - if (dev->dev_private) { - drm_r128_private_t *dev_priv = dev->dev_private; - if (dev_priv->page_flipping) { - r128_do_cleanup_pageflip(dev); - } - } -} - -void r128_driver_lastclose(struct drm_device * dev) -{ - r128_do_cleanup_cce(dev); -} - -struct drm_ioctl_desc r128_ioctls[] = { - DRM_IOCTL_DEF(DRM_R128_INIT, r128_cce_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_R128_CCE_START, r128_cce_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_R128_CCE_STOP, r128_cce_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_R128_CCE_RESET, r128_cce_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_R128_CCE_IDLE, r128_cce_idle, DRM_AUTH), - DRM_IOCTL_DEF(DRM_R128_RESET, r128_engine_reset, DRM_AUTH), - DRM_IOCTL_DEF(DRM_R128_FULLSCREEN, r128_fullscreen, DRM_AUTH), - DRM_IOCTL_DEF(DRM_R128_SWAP, r128_cce_swap, DRM_AUTH), - DRM_IOCTL_DEF(DRM_R128_FLIP, r128_cce_flip, DRM_AUTH), - DRM_IOCTL_DEF(DRM_R128_CLEAR, r128_cce_clear, DRM_AUTH), - DRM_IOCTL_DEF(DRM_R128_VERTEX, r128_cce_vertex, DRM_AUTH), - DRM_IOCTL_DEF(DRM_R128_INDICES, r128_cce_indices, DRM_AUTH), - DRM_IOCTL_DEF(DRM_R128_BLIT, r128_cce_blit, DRM_AUTH), - DRM_IOCTL_DEF(DRM_R128_DEPTH, r128_cce_depth, DRM_AUTH), - DRM_IOCTL_DEF(DRM_R128_STIPPLE, r128_cce_stipple, DRM_AUTH), - DRM_IOCTL_DEF(DRM_R128_INDIRECT, r128_cce_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_R128_GETPARAM, r128_getparam, DRM_AUTH), -}; - -int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls); diff --git a/shared-core/r300_cmdbuf.c b/shared-core/r300_cmdbuf.c deleted file mode 100644 index 7546e839..00000000 --- a/shared-core/r300_cmdbuf.c +++ /dev/null @@ -1,1198 +0,0 @@ -/* r300_cmdbuf.c -- Command buffer emission for R300 -*- linux-c -*- - * - * Copyright (C) The Weather Channel, Inc. 2002. - * Copyright (C) 2004 Nicolai Haehnle. - * All Rights Reserved. - * - * The Weather Channel (TM) funded Tungsten Graphics to develop the - * initial release of the Radeon 8500 driver under the XFree86 license. - * This notice must be preserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Nicolai Haehnle - */ - -#include "drmP.h" -#include "drm.h" -#include "radeon_drm.h" -#include "radeon_drv.h" -#include "r300_reg.h" - -#define R300_SIMULTANEOUS_CLIPRECTS 4 - -/* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects - */ -static const int r300_cliprect_cntl[4] = { - 0xAAAA, - 0xEEEE, - 0xFEFE, - 0xFFFE -}; - -/** - * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command - * buffer, starting with index n. - */ -static int r300_emit_cliprects(drm_radeon_private_t *dev_priv, - drm_radeon_kcmd_buffer_t *cmdbuf, int n) -{ - struct drm_clip_rect box; - int nr; - int i; - RING_LOCALS; - - nr = cmdbuf->nbox - n; - if (nr > R300_SIMULTANEOUS_CLIPRECTS) - nr = R300_SIMULTANEOUS_CLIPRECTS; - - DRM_DEBUG("%i cliprects\n", nr); - - if (nr) { - BEGIN_RING(6 + nr * 2); - OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); - - for (i = 0; i < nr; ++i) { - if (DRM_COPY_FROM_USER_UNCHECKED - (&box, &cmdbuf->boxes[n + i], sizeof(box))) { - DRM_ERROR("copy cliprect faulted\n"); - return -EFAULT; - } - - box.x2--; /* Hardware expects inclusive bottom-right corner */ - box.y2--; - - if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { - box.x1 = (box.x1) & - R300_CLIPRECT_MASK; - box.y1 = (box.y1) & - R300_CLIPRECT_MASK; - box.x2 = (box.x2) & - R300_CLIPRECT_MASK; - box.y2 = (box.y2) & - R300_CLIPRECT_MASK; - } else { - box.x1 = (box.x1 + R300_CLIPRECT_OFFSET) & - R300_CLIPRECT_MASK; - box.y1 = (box.y1 + R300_CLIPRECT_OFFSET) & - R300_CLIPRECT_MASK; - box.x2 = (box.x2 + R300_CLIPRECT_OFFSET) & - R300_CLIPRECT_MASK; - box.y2 = (box.y2 + R300_CLIPRECT_OFFSET) & - R300_CLIPRECT_MASK; - } - - OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) | - (box.y1 << R300_CLIPRECT_Y_SHIFT)); - OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) | - (box.y2 << R300_CLIPRECT_Y_SHIFT)); - - } - - OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]); - - /* TODO/SECURITY: Force scissors to a safe value, otherwise the - * client might be able to trample over memory. - * The impact should be very limited, but I'd rather be safe than - * sorry. - */ - OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1)); - OUT_RING(0); - OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK); - ADVANCE_RING(); - } else { - /* Why we allow zero cliprect rendering: - * There are some commands in a command buffer that must be submitted - * even when there are no cliprects, e.g. DMA buffer discard - * or state setting (though state setting could be avoided by - * simulating a loss of context). - * - * Now since the cmdbuf interface is so chaotic right now (and is - * bound to remain that way for a bit until things settle down), - * it is basically impossible to filter out the commands that are - * necessary and those that aren't. - * - * So I choose the safe way and don't do any filtering at all; - * instead, I simply set up the engine so that all rendering - * can't produce any fragments. - */ - BEGIN_RING(2); - OUT_RING_REG(R300_RE_CLIPRECT_CNTL, 0); - ADVANCE_RING(); - } - - /* flus cache and wait idle clean after cliprect change */ - BEGIN_RING(2); - OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); - OUT_RING(R300_RB3D_DC_FLUSH); - ADVANCE_RING(); - BEGIN_RING(2); - OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); - OUT_RING(RADEON_WAIT_3D_IDLECLEAN); - ADVANCE_RING(); - /* set flush flag */ - dev_priv->track_flush |= RADEON_FLUSH_EMITED; - - return 0; -} - -static u8 r300_reg_flags[0x10000 >> 2]; - -void r300_init_reg_flags(struct drm_device *dev) -{ - int i; - drm_radeon_private_t *dev_priv = dev->dev_private; - - memset(r300_reg_flags, 0, 0x10000 >> 2); -#define ADD_RANGE_MARK(reg, count,mark) \ - for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\ - r300_reg_flags[i]|=(mark); - -#define MARK_SAFE 1 -#define MARK_CHECK_OFFSET 2 - -#define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE) - - /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */ - ADD_RANGE(R300_SE_VPORT_XSCALE, 6); - ADD_RANGE(R300_VAP_CNTL, 1); - ADD_RANGE(R300_SE_VTE_CNTL, 2); - ADD_RANGE(0x2134, 2); - ADD_RANGE(R300_VAP_CNTL_STATUS, 1); - ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2); - ADD_RANGE(0x21DC, 1); - ADD_RANGE(R300_VAP_UNKNOWN_221C, 1); - ADD_RANGE(R300_VAP_CLIP_X_0, 4); - ADD_RANGE(R300_VAP_PVS_STATE_FLUSH_REG, 1); - ADD_RANGE(R300_VAP_UNKNOWN_2288, 1); - ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2); - ADD_RANGE(R300_VAP_PVS_CNTL_1, 3); - ADD_RANGE(R300_GB_ENABLE, 1); - ADD_RANGE(R300_GB_MSPOS0, 5); - ADD_RANGE(R300_TX_INVALTAGS, 1); - ADD_RANGE(R300_TX_ENABLE, 1); - ADD_RANGE(0x4200, 4); - ADD_RANGE(0x4214, 1); - ADD_RANGE(R300_RE_POINTSIZE, 1); - ADD_RANGE(0x4230, 3); - ADD_RANGE(R300_RE_LINE_CNT, 1); - ADD_RANGE(R300_RE_UNK4238, 1); - ADD_RANGE(0x4260, 3); - ADD_RANGE(R300_RE_SHADE, 4); - ADD_RANGE(R300_RE_POLYGON_MODE, 5); - ADD_RANGE(R300_RE_ZBIAS_CNTL, 1); - ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4); - ADD_RANGE(R300_RE_OCCLUSION_CNTL, 1); - ADD_RANGE(R300_RE_CULL_CNTL, 1); - ADD_RANGE(0x42C0, 2); - ADD_RANGE(R300_RS_CNTL_0, 2); - - ADD_RANGE(R300_SC_HYPERZ, 2); - ADD_RANGE(0x43E8, 1); - - ADD_RANGE(0x46A4, 5); - - ADD_RANGE(R300_RE_FOG_STATE, 1); - ADD_RANGE(R300_FOG_COLOR_R, 3); - ADD_RANGE(R300_PP_ALPHA_TEST, 2); - ADD_RANGE(0x4BD8, 1); - ADD_RANGE(R300_PFS_PARAM_0_X, 64); - ADD_RANGE(0x4E00, 1); - ADD_RANGE(R300_RB3D_CBLEND, 2); - ADD_RANGE(R300_RB3D_COLORMASK, 1); - ADD_RANGE(R300_RB3D_BLEND_COLOR, 3); - ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */ - ADD_RANGE(R300_RB3D_COLORPITCH0, 1); - ADD_RANGE(0x4E50, 9); - ADD_RANGE(0x4E88, 1); - ADD_RANGE(0x4EA0, 2); - ADD_RANGE(R300_ZB_CNTL, 3); - ADD_RANGE(R300_ZB_FORMAT, 4); - ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ - ADD_RANGE(R300_ZB_DEPTHPITCH, 1); - ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1); - ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13); - - ADD_RANGE(R300_TX_FILTER_0, 16); - ADD_RANGE(R300_TX_FILTER1_0, 16); - ADD_RANGE(R300_TX_SIZE_0, 16); - ADD_RANGE(R300_TX_FORMAT_0, 16); - ADD_RANGE(R300_TX_PITCH_0, 16); - /* Texture offset is dangerous and needs more checking */ - ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET); - ADD_RANGE(R300_TX_CHROMA_KEY_0, 16); - ADD_RANGE(R300_TX_BORDER_COLOR_0, 16); - - /* Sporadic registers used as primitives are emitted */ - ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1); - ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1); - ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8); - ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8); - - if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { - ADD_RANGE(R500_VAP_INDEX_OFFSET, 1); - ADD_RANGE(R500_US_CONFIG, 2); - ADD_RANGE(R500_US_CODE_ADDR, 3); - ADD_RANGE(R500_US_FC_CTRL, 1); - ADD_RANGE(R500_RS_IP_0, 16); - ADD_RANGE(R500_RS_INST_0, 16); - ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2); - ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2); - ADD_RANGE(R500_ZB_FIFO_SIZE, 2); - } else { - ADD_RANGE(R300_PFS_CNTL_0, 3); - ADD_RANGE(R300_PFS_NODE_0, 4); - ADD_RANGE(R300_PFS_TEXI_0, 64); - ADD_RANGE(R300_PFS_INSTR0_0, 64); - ADD_RANGE(R300_PFS_INSTR1_0, 64); - ADD_RANGE(R300_PFS_INSTR2_0, 64); - ADD_RANGE(R300_PFS_INSTR3_0, 64); - ADD_RANGE(R300_RS_INTERP_0, 8); - ADD_RANGE(R300_RS_ROUTE_0, 8); - - } -} - -static __inline__ int r300_check_range(unsigned reg, int count) -{ - int i; - if (reg & ~0xffff) - return -1; - for (i = (reg >> 2); i < (reg >> 2) + count; i++) - if (r300_reg_flags[i] != MARK_SAFE) - return 1; - return 0; -} - -static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t * - dev_priv, - drm_radeon_kcmd_buffer_t - * cmdbuf, - drm_r300_cmd_header_t - header) -{ - int reg; - int sz; - int i; - int values[64]; - RING_LOCALS; - - sz = header.packet0.count; - reg = (header.packet0.reghi << 8) | header.packet0.reglo; - - if ((sz > 64) || (sz < 0)) { - DRM_ERROR - ("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n", - reg, sz); - return -EINVAL; - } - for (i = 0; i < sz; i++) { - values[i] = ((int *)cmdbuf->buf)[i]; - switch (r300_reg_flags[(reg >> 2) + i]) { - case MARK_SAFE: - break; - case MARK_CHECK_OFFSET: - if (!radeon_check_offset(dev_priv, (u32) values[i])) { - DRM_ERROR - ("Offset failed range check (reg=%04x sz=%d)\n", - reg, sz); - return -EINVAL; - } - break; - default: - DRM_ERROR("Register %04x failed check as flag=%02x\n", - reg + i * 4, r300_reg_flags[(reg >> 2) + i]); - return -EINVAL; - } - } - - BEGIN_RING(1 + sz); - OUT_RING(CP_PACKET0(reg, sz - 1)); - OUT_RING_TABLE(values, sz); - ADVANCE_RING(); - - cmdbuf->buf += sz * 4; - cmdbuf->bufsz -= sz * 4; - - return 0; -} - -/** - * Emits a packet0 setting arbitrary registers. - * Called by r300_do_cp_cmdbuf. - * - * Note that checks are performed on contents and addresses of the registers - */ -static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv, - drm_radeon_kcmd_buffer_t *cmdbuf, - drm_r300_cmd_header_t header) -{ - int reg; - int sz; - RING_LOCALS; - - sz = header.packet0.count; - reg = (header.packet0.reghi << 8) | header.packet0.reglo; - - DRM_DEBUG("R300_CMD_PACKET0: reg %04x, sz %d\n", reg, sz); - if (!sz) - return 0; - - if (sz * 4 > cmdbuf->bufsz) - return -EINVAL; - - if (reg + sz * 4 >= 0x10000) { - DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg, - sz); - return -EINVAL; - } - - if (r300_check_range(reg, sz)) { - /* go and check everything */ - return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf, - header); - } - /* the rest of the data is safe to emit, whatever the values the user passed */ - - BEGIN_RING(1 + sz); - OUT_RING(CP_PACKET0(reg, sz - 1)); - OUT_RING_TABLE((int *)cmdbuf->buf, sz); - ADVANCE_RING(); - - cmdbuf->buf += sz * 4; - cmdbuf->bufsz -= sz * 4; - - return 0; -} - -/** - * Uploads user-supplied vertex program instructions or parameters onto - * the graphics card. - * Called by r300_do_cp_cmdbuf. - */ -static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv, - drm_radeon_kcmd_buffer_t *cmdbuf, - drm_r300_cmd_header_t header) -{ - int sz; - int addr; - RING_LOCALS; - - sz = header.vpu.count; - addr = (header.vpu.adrhi << 8) | header.vpu.adrlo; - - if (!sz) - return 0; - if (sz * 16 > cmdbuf->bufsz) - return -EINVAL; - - /* VAP is very sensitive so we purge cache before we program it - * and we also flush its state before & after */ - BEGIN_RING(6); - OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); - OUT_RING(R300_RB3D_DC_FLUSH); - OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); - OUT_RING(RADEON_WAIT_3D_IDLECLEAN); - OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0)); - OUT_RING(0); - ADVANCE_RING(); - /* set flush flag */ - dev_priv->track_flush |= RADEON_FLUSH_EMITED; - - BEGIN_RING(3 + sz * 4); - OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr); - OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1)); - OUT_RING_TABLE((int *)cmdbuf->buf, sz * 4); - ADVANCE_RING(); - - BEGIN_RING(2); - OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0)); - OUT_RING(0); - ADVANCE_RING(); - - cmdbuf->buf += sz * 16; - cmdbuf->bufsz -= sz * 16; - - return 0; -} - -/** - * Emit a clear packet from userspace. - * Called by r300_emit_packet3. - */ -static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv, - drm_radeon_kcmd_buffer_t *cmdbuf) -{ - RING_LOCALS; - - if (8 * 4 > cmdbuf->bufsz) - return -EINVAL; - - BEGIN_RING(10); - OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); - OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | - (1 << R300_PRIM_NUM_VERTICES_SHIFT)); - OUT_RING_TABLE((int *)cmdbuf->buf, 8); - ADVANCE_RING(); - - BEGIN_RING(4); - OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); - OUT_RING(R300_RB3D_DC_FLUSH); - OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); - OUT_RING(RADEON_WAIT_3D_IDLECLEAN); - ADVANCE_RING(); - /* set flush flag */ - dev_priv->track_flush |= RADEON_FLUSH_EMITED; - - cmdbuf->buf += 8 * 4; - cmdbuf->bufsz -= 8 * 4; - - return 0; -} - -static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv, - drm_radeon_kcmd_buffer_t *cmdbuf, - u32 header) -{ - int count, i, k; -#define MAX_ARRAY_PACKET 64 - u32 payload[MAX_ARRAY_PACKET]; - u32 narrays; - RING_LOCALS; - - count = (header >> 16) & 0x3fff; - - if ((count + 1) > MAX_ARRAY_PACKET) { - DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", - count); - return -EINVAL; - } - memset(payload, 0, MAX_ARRAY_PACKET * 4); - memcpy(payload, cmdbuf->buf + 4, (count + 1) * 4); - - /* carefully check packet contents */ - - narrays = payload[0]; - k = 0; - i = 1; - while ((k < narrays) && (i < (count + 1))) { - i++; /* skip attribute field */ - if (!radeon_check_offset(dev_priv, payload[i])) { - DRM_ERROR - ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", - k, i); - return -EINVAL; - } - k++; - i++; - if (k == narrays) - break; - /* have one more to process, they come in pairs */ - if (!radeon_check_offset(dev_priv, payload[i])) { - DRM_ERROR - ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", - k, i); - return -EINVAL; - } - k++; - i++; - } - /* do the counts match what we expect ? */ - if ((k != narrays) || (i != (count + 1))) { - DRM_ERROR - ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n", - k, i, narrays, count + 1); - return -EINVAL; - } - - /* all clear, output packet */ - - BEGIN_RING(count + 2); - OUT_RING(header); - OUT_RING_TABLE(payload, count + 1); - ADVANCE_RING(); - - cmdbuf->buf += (count + 2) * 4; - cmdbuf->bufsz -= (count + 2) * 4; - - return 0; -} - -static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv, - drm_radeon_kcmd_buffer_t *cmdbuf) -{ - u32 *cmd = (u32 *) cmdbuf->buf; - int count, ret; - RING_LOCALS; - - count=(cmd[0]>>16) & 0x3fff; - - if (cmd[0] & 0x8000) { - u32 offset; - - if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL - | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { - offset = cmd[2] << 10; - ret = !radeon_check_offset(dev_priv, offset); - if (ret) { - DRM_ERROR("Invalid bitblt first offset is %08X\n", offset); - return -EINVAL; - } - } - - if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) && - (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { - offset = cmd[3] << 10; - ret = !radeon_check_offset(dev_priv, offset); - if (ret) { - DRM_ERROR("Invalid bitblt second offset is %08X\n", offset); - return -EINVAL; - } - - } - } - - BEGIN_RING(count+2); - OUT_RING(cmd[0]); - OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1); - ADVANCE_RING(); - - cmdbuf->buf += (count+2)*4; - cmdbuf->bufsz -= (count+2)*4; - - return 0; -} - -static __inline__ int r300_emit_draw_indx_2(drm_radeon_private_t *dev_priv, - drm_radeon_kcmd_buffer_t *cmdbuf) -{ - u32 *cmd; - int count; - int expected_count; - RING_LOCALS; - - cmd = (u32 *) cmdbuf->buf; - count = (cmd[0]>>16) & 0x3fff; - expected_count = cmd[1] >> 16; - if (!(cmd[1] & R300_VAP_VF_CNTL__INDEX_SIZE_32bit)) - expected_count = (expected_count+1)/2; - - if (count && count != expected_count) { - DRM_ERROR("3D_DRAW_INDX_2: packet size %i, expected %i\n", - count, expected_count); - return -EINVAL; - } - - BEGIN_RING(count+2); - OUT_RING(cmd[0]); - OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1); - ADVANCE_RING(); - - cmdbuf->buf += (count+2)*4; - cmdbuf->bufsz -= (count+2)*4; - - if (!count) { - drm_r300_cmd_header_t header; - - if (cmdbuf->bufsz < 4*4 + sizeof(header)) { - DRM_ERROR("3D_DRAW_INDX_2: expect subsequent INDX_BUFFER, but stream is too short.\n"); - return -EINVAL; - } - - header.u = *(unsigned int *)cmdbuf->buf; - - cmdbuf->buf += sizeof(header); - cmdbuf->bufsz -= sizeof(header); - cmd = (u32 *) cmdbuf->buf; - - if (header.header.cmd_type != R300_CMD_PACKET3 || - header.packet3.packet != R300_CMD_PACKET3_RAW || - cmd[0] != CP_PACKET3(RADEON_CP_INDX_BUFFER, 2)) { - DRM_ERROR("3D_DRAW_INDX_2: expect subsequent INDX_BUFFER.\n"); - return -EINVAL; - } - - if ((cmd[1] & 0x8000ffff) != 0x80000810) { - DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]); - return -EINVAL; - } - if (!radeon_check_offset(dev_priv, cmd[2])) { - DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]); - return -EINVAL; - } - if (cmd[3] != expected_count) { - DRM_ERROR("INDX_BUFFER: buffer size %i, expected %i\n", - cmd[3], expected_count); - return -EINVAL; - } - - BEGIN_RING(4); - OUT_RING(cmd[0]); - OUT_RING_TABLE((int *)(cmdbuf->buf + 4), 3); - ADVANCE_RING(); - - cmdbuf->buf += 4*4; - cmdbuf->bufsz -= 4*4; - } - - return 0; -} - -static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv, - drm_radeon_kcmd_buffer_t *cmdbuf) -{ - u32 header; - int count; - RING_LOCALS; - - if (4 > cmdbuf->bufsz) - return -EINVAL; - - /* Fixme !! This simply emits a packet without much checking. - We need to be smarter. */ - - /* obtain first word - actual packet3 header */ - header = *(u32 *) cmdbuf->buf; - - /* Is it packet 3 ? */ - if ((header >> 30) != 0x3) { - DRM_ERROR("Not a packet3 header (0x%08x)\n", header); - return -EINVAL; - } - - count = (header >> 16) & 0x3fff; - - /* Check again now that we know how much data to expect */ - if ((count + 2) * 4 > cmdbuf->bufsz) { - DRM_ERROR - ("Expected packet3 of length %d but have only %d bytes left\n", - (count + 2) * 4, cmdbuf->bufsz); - return -EINVAL; - } - - /* Is it a packet type we know about ? */ - switch (header & 0xff00) { - case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */ - return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header); - - case RADEON_CNTL_BITBLT_MULTI: - return r300_emit_bitblt_multi(dev_priv, cmdbuf); - - case RADEON_CP_INDX_BUFFER: - DRM_ERROR("packet3 INDX_BUFFER without preceding 3D_DRAW_INDX_2 is illegal.\n"); - return -EINVAL; - case RADEON_CP_3D_DRAW_IMMD_2: - /* triggers drawing using in-packet vertex data */ - case RADEON_CP_3D_DRAW_VBUF_2: - /* triggers drawing of vertex buffers setup elsewhere */ - dev_priv->track_flush &= ~(RADEON_FLUSH_EMITED | - RADEON_PURGE_EMITED); - break; - case RADEON_CP_3D_DRAW_INDX_2: - /* triggers drawing using indices to vertex buffer */ - /* whenever we send vertex we clear flush & purge */ - dev_priv->track_flush &= ~(RADEON_FLUSH_EMITED | - RADEON_PURGE_EMITED); - return r300_emit_draw_indx_2(dev_priv, cmdbuf); - case RADEON_WAIT_FOR_IDLE: - case RADEON_CP_NOP: - /* these packets are safe */ - break; - default: - DRM_ERROR("Unknown packet3 header (0x%08x)\n", header); - return -EINVAL; - } - - BEGIN_RING(count + 2); - OUT_RING(header); - OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1); - ADVANCE_RING(); - - cmdbuf->buf += (count + 2) * 4; - cmdbuf->bufsz -= (count + 2) * 4; - - return 0; -} - -/** - * Emit a rendering packet3 from userspace. - * Called by r300_do_cp_cmdbuf. - */ -static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv, - drm_radeon_kcmd_buffer_t *cmdbuf, - drm_r300_cmd_header_t header) -{ - int n; - int ret; - char *orig_buf = cmdbuf->buf; - int orig_bufsz = cmdbuf->bufsz; - - /* This is a do-while-loop so that we run the interior at least once, - * even if cmdbuf->nbox is 0. Compare r300_emit_cliprects for rationale. - */ - n = 0; - do { - if (cmdbuf->nbox > R300_SIMULTANEOUS_CLIPRECTS) { - ret = r300_emit_cliprects(dev_priv, cmdbuf, n); - if (ret) - return ret; - - cmdbuf->buf = orig_buf; - cmdbuf->bufsz = orig_bufsz; - } - - switch (header.packet3.packet) { - case R300_CMD_PACKET3_CLEAR: - DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n"); - ret = r300_emit_clear(dev_priv, cmdbuf); - if (ret) { - DRM_ERROR("r300_emit_clear failed\n"); - return ret; - } - break; - - case R300_CMD_PACKET3_RAW: - DRM_DEBUG("R300_CMD_PACKET3_RAW\n"); - ret = r300_emit_raw_packet3(dev_priv, cmdbuf); - if (ret) { - DRM_ERROR("r300_emit_raw_packet3 failed\n"); - return ret; - } - break; - - default: - DRM_ERROR("bad packet3 type %i at %p\n", - header.packet3.packet, - cmdbuf->buf - sizeof(header)); - return -EINVAL; - } - - n += R300_SIMULTANEOUS_CLIPRECTS; - } while (n < cmdbuf->nbox); - - return 0; -} - -/* Some of the R300 chips seem to be extremely touchy about the two registers - * that are configured in r300_pacify. - * Among the worst offenders seems to be the R300 ND (0x4E44): When userspace - * sends a command buffer that contains only state setting commands and a - * vertex program/parameter upload sequence, this will eventually lead to a - * lockup, unless the sequence is bracketed by calls to r300_pacify. - * So we should take great care to *always* call r300_pacify before - * *anything* 3D related, and again afterwards. This is what the - * call bracket in r300_do_cp_cmdbuf is for. - */ - -/** - * Emit the sequence to pacify R300. - */ -static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv) -{ - uint32_t cache_z, cache_3d, cache_2d; - RING_LOCALS; - - cache_z = R300_ZC_FLUSH; - cache_2d = R300_RB2D_DC_FLUSH; - cache_3d = R300_RB3D_DC_FLUSH; - if (!(dev_priv->track_flush & RADEON_PURGE_EMITED)) { - /* we can purge, primitive where draw since last purge */ - cache_z |= R300_ZC_FREE; - cache_2d |= R300_RB2D_DC_FREE; - cache_3d |= R300_RB3D_DC_FREE; - } - - /* flush & purge zbuffer */ - BEGIN_RING(2); - OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); - OUT_RING(cache_z); - ADVANCE_RING(); - /* flush & purge 3d */ - BEGIN_RING(2); - OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); - OUT_RING(cache_3d); - ADVANCE_RING(); - /* flush & purge texture */ - BEGIN_RING(2); - OUT_RING(CP_PACKET0(R300_TX_INVALTAGS, 0)); - OUT_RING(0); - ADVANCE_RING(); - /* FIXME: is this one really needed ? */ - BEGIN_RING(2); - OUT_RING(CP_PACKET0(R300_RB3D_AARESOLVE_CTL, 0)); - OUT_RING(0); - ADVANCE_RING(); - BEGIN_RING(2); - OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); - OUT_RING(RADEON_WAIT_3D_IDLECLEAN); - ADVANCE_RING(); - /* flush & purge 2d through E2 as RB2D will trigger lockup */ - BEGIN_RING(4); - OUT_RING(CP_PACKET0(R300_DSTCACHE_CTLSTAT, 0)); - OUT_RING(cache_2d); - OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); - OUT_RING(RADEON_WAIT_2D_IDLECLEAN | - RADEON_WAIT_HOST_IDLECLEAN); - ADVANCE_RING(); - /* set flush & purge flags */ - dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED; -} - -/** - * Called by r300_do_cp_cmdbuf to update the internal buffer age and state. - * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must - * be careful about how this function is called. - */ -static void r300_discard_buffer(struct drm_device * dev, struct drm_buf * buf) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_buf_priv_t *buf_priv = buf->dev_private; - - buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; - buf->pending = 1; - buf->used = 0; -} - -static void r300_cmd_wait(drm_radeon_private_t * dev_priv, - drm_r300_cmd_header_t header) -{ - u32 wait_until; - RING_LOCALS; - - if (!header.wait.flags) - return; - - wait_until = 0; - - switch(header.wait.flags) { - case R300_WAIT_2D: - wait_until = RADEON_WAIT_2D_IDLE; - break; - case R300_WAIT_3D: - wait_until = RADEON_WAIT_3D_IDLE; - break; - case R300_NEW_WAIT_2D_3D: - wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_3D_IDLE; - break; - case R300_NEW_WAIT_2D_2D_CLEAN: - wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_2D_IDLECLEAN; - break; - case R300_NEW_WAIT_3D_3D_CLEAN: - wait_until = RADEON_WAIT_3D_IDLE|RADEON_WAIT_3D_IDLECLEAN; - break; - case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN: - wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_2D_IDLECLEAN; - wait_until |= RADEON_WAIT_3D_IDLE|RADEON_WAIT_3D_IDLECLEAN; - break; - default: - return; - } - - BEGIN_RING(2); - OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); - OUT_RING(wait_until); - ADVANCE_RING(); -} - -static int r300_scratch(drm_radeon_private_t *dev_priv, - drm_radeon_kcmd_buffer_t *cmdbuf, - drm_r300_cmd_header_t header) -{ - u32 *ref_age_base; - u32 i, buf_idx, h_pending; - RING_LOCALS; - - if (cmdbuf->bufsz < sizeof(uint64_t) + header.scratch.n_bufs * sizeof(buf_idx) ) { - return -EINVAL; - } - - if (header.scratch.reg >= 5) { - return -EINVAL; - } - - dev_priv->scratch_ages[header.scratch.reg] ++; - - ref_age_base = (u32 *)(unsigned long)*((uint64_t *)cmdbuf->buf); - - cmdbuf->buf += sizeof(uint64_t); - cmdbuf->bufsz -= sizeof(uint64_t); - - for (i=0; i < header.scratch.n_bufs; i++) { - buf_idx = *(u32 *)cmdbuf->buf; - buf_idx *= 2; /* 8 bytes per buf */ - - if (DRM_COPY_TO_USER(ref_age_base + buf_idx, &dev_priv->scratch_ages[header.scratch.reg], sizeof(u32))) { - return -EINVAL; - } - - if (DRM_COPY_FROM_USER(&h_pending, ref_age_base + buf_idx + 1, sizeof(u32))) { - return -EINVAL; - } - - if (h_pending == 0) { - return -EINVAL; - } - - h_pending--; - - if (DRM_COPY_TO_USER(ref_age_base + buf_idx + 1, &h_pending, sizeof(u32))) { - return -EINVAL; - } - - cmdbuf->buf += sizeof(buf_idx); - cmdbuf->bufsz -= sizeof(buf_idx); - } - - BEGIN_RING(2); - OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0 ) ); - OUT_RING( dev_priv->scratch_ages[header.scratch.reg] ); - ADVANCE_RING(); - - return 0; -} - -/** - * Uploads user-supplied vertex program instructions or parameters onto - * the graphics card. - * Called by r300_do_cp_cmdbuf. - */ -static __inline__ int r300_emit_r500fp(drm_radeon_private_t *dev_priv, - drm_radeon_kcmd_buffer_t *cmdbuf, - drm_r300_cmd_header_t header) -{ - int sz; - int addr; - int type; - int clamp; - int stride; - RING_LOCALS; - - sz = header.r500fp.count; - /* address is 9 bits 0 - 8, bit 1 of flags is part of address */ - addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo; - - type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE); - clamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP); - - addr |= (type << 16); - addr |= (clamp << 17); - - stride = type ? 4 : 6; - - DRM_DEBUG("r500fp %d %d type: %d\n", sz, addr, type); - if (!sz) - return 0; - if (sz * stride * 4 > cmdbuf->bufsz) - return -EINVAL; - - BEGIN_RING(3 + sz * stride); - OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr); - OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1)); - OUT_RING_TABLE((int *)cmdbuf->buf, sz * stride); - - ADVANCE_RING(); - - cmdbuf->buf += sz * stride * 4; - cmdbuf->bufsz -= sz * stride * 4; - - return 0; -} - - -/** - * Parses and validates a user-supplied command buffer and emits appropriate - * commands on the DMA ring buffer. - * Called by the ioctl handler function radeon_cp_cmdbuf. - */ -int r300_do_cp_cmdbuf(struct drm_device *dev, - struct drm_file *file_priv, - drm_radeon_kcmd_buffer_t *cmdbuf) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - struct drm_device_dma *dma = dev->dma; - struct drm_buf *buf = NULL; - int emit_dispatch_age = 0; - int ret = 0; - - DRM_DEBUG("\n"); - - /* pacify */ - r300_pacify(dev_priv); - - if (cmdbuf->nbox <= R300_SIMULTANEOUS_CLIPRECTS) { - ret = r300_emit_cliprects(dev_priv, cmdbuf, 0); - if (ret) - goto cleanup; - } - - while (cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) { - int idx; - drm_r300_cmd_header_t header; - - header.u = *(unsigned int *)cmdbuf->buf; - - cmdbuf->buf += sizeof(header); - cmdbuf->bufsz -= sizeof(header); - - switch (header.header.cmd_type) { - case R300_CMD_PACKET0: - ret = r300_emit_packet0(dev_priv, cmdbuf, header); - if (ret) { - DRM_ERROR("r300_emit_packet0 failed\n"); - goto cleanup; - } - break; - - case R300_CMD_VPU: - DRM_DEBUG("R300_CMD_VPU\n"); - ret = r300_emit_vpu(dev_priv, cmdbuf, header); - if (ret) { - DRM_ERROR("r300_emit_vpu failed\n"); - goto cleanup; - } - break; - - case R300_CMD_PACKET3: - DRM_DEBUG("R300_CMD_PACKET3\n"); - ret = r300_emit_packet3(dev_priv, cmdbuf, header); - if (ret) { - DRM_ERROR("r300_emit_packet3 failed\n"); - goto cleanup; - } - break; - - case R300_CMD_END3D: - DRM_DEBUG("R300_CMD_END3D\n"); - /* TODO: - Ideally userspace driver should not need to issue this call, - i.e. the drm driver should issue it automatically and prevent - lockups. - - In practice, we do not understand why this call is needed and what - it does (except for some vague guesses that it has to do with cache - coherence) and so the user space driver does it. - - Once we are sure which uses prevent lockups the code could be moved - into the kernel and the userspace driver will not - need to use this command. - - Note that issuing this command does not hurt anything - except, possibly, performance */ - r300_pacify(dev_priv); - break; - - case R300_CMD_CP_DELAY: - /* simple enough, we can do it here */ - DRM_DEBUG("R300_CMD_CP_DELAY\n"); - { - int i; - RING_LOCALS; - - BEGIN_RING(header.delay.count); - for (i = 0; i < header.delay.count; i++) - OUT_RING(RADEON_CP_PACKET2); - ADVANCE_RING(); - } - break; - - case R300_CMD_DMA_DISCARD: - DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); - idx = header.dma.buf_idx; - if (idx < 0 || idx >= dma->buf_count) { - DRM_ERROR("buffer index %d (of %d max)\n", - idx, dma->buf_count - 1); - ret = -EINVAL; - goto cleanup; - } - - buf = dma->buflist[idx]; - if (buf->file_priv != file_priv || buf->pending) { - DRM_ERROR("bad buffer %p %p %d\n", - buf->file_priv, file_priv, - buf->pending); - ret = -EINVAL; - goto cleanup; - } - - emit_dispatch_age = 1; - r300_discard_buffer(dev, buf); - break; - - case R300_CMD_WAIT: - DRM_DEBUG("R300_CMD_WAIT\n"); - r300_cmd_wait(dev_priv, header); - break; - - case R300_CMD_SCRATCH: - DRM_DEBUG("R300_CMD_SCRATCH\n"); - ret = r300_scratch(dev_priv, cmdbuf, header); - if (ret) { - DRM_ERROR("r300_scratch failed\n"); - goto cleanup; - } - break; - - case R300_CMD_R500FP: - if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) { - DRM_ERROR("Calling r500 command on r300 card\n"); - ret = -EINVAL; - goto cleanup; - } - DRM_DEBUG("R300_CMD_R500FP\n"); - ret = r300_emit_r500fp(dev_priv, cmdbuf, header); - if (ret) { - DRM_ERROR("r300_emit_r500fp failed\n"); - goto cleanup; - } - break; - default: - DRM_ERROR("bad cmd_type %i at %p\n", - header.header.cmd_type, - cmdbuf->buf - sizeof(header)); - ret = -EINVAL; - goto cleanup; - } - } - - DRM_DEBUG("END\n"); - - cleanup: - r300_pacify(dev_priv); - - /* We emit the vertex buffer age here, outside the pacifier "brackets" - * for two reasons: - * (1) This may coalesce multiple age emissions into a single one and - * (2) more importantly, some chips lock up hard when scratch registers - * are written inside the pacifier bracket. - */ - if (emit_dispatch_age) { - RING_LOCALS; - - /* Emit the vertex buffer age */ - BEGIN_RING(2); - RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch); - ADVANCE_RING(); - } - - COMMIT_RING(); - - return ret; -} diff --git a/shared-core/r300_reg.h b/shared-core/r300_reg.h deleted file mode 100644 index d35dd39d..00000000 --- a/shared-core/r300_reg.h +++ /dev/null @@ -1,1778 +0,0 @@ -/************************************************************************** - -Copyright (C) 2004-2005 Nicolai Haehnle et al. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* *INDENT-OFF* */ - -#ifndef _R300_REG_H -#define _R300_REG_H - -#define R300_MC_INIT_MISC_LAT_TIMER 0x180 -# define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0 -# define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4 -# define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8 -# define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12 -# define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16 -# define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20 -# define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24 -# define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28 - - -#define R300_MC_INIT_GFX_LAT_TIMER 0x154 -# define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0 -# define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4 -# define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8 -# define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12 -# define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16 -# define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20 -# define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24 -# define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28 - -/* - * This file contains registers and constants for the R300. They have been - * found mostly by examining command buffers captured using glxtest, as well - * as by extrapolating some known registers and constants from the R200. - * I am fairly certain that they are correct unless stated otherwise - * in comments. - */ - -#define R300_SE_VPORT_XSCALE 0x1D98 -#define R300_SE_VPORT_XOFFSET 0x1D9C -#define R300_SE_VPORT_YSCALE 0x1DA0 -#define R300_SE_VPORT_YOFFSET 0x1DA4 -#define R300_SE_VPORT_ZSCALE 0x1DA8 -#define R300_SE_VPORT_ZOFFSET 0x1DAC - - -/* - * Vertex Array Processing (VAP) Control - * Stolen from r200 code from Christoph Brill (It's a guess!) - */ -#define R300_VAP_CNTL 0x2080 - -/* This register is written directly and also starts data section - * in many 3d CP_PACKET3's - */ -#define R300_VAP_VF_CNTL 0x2084 -# define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0 -# define R300_VAP_VF_CNTL__PRIM_NONE (0<<0) -# define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0) -# define R300_VAP_VF_CNTL__PRIM_LINES (2<<0) -# define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0) -# define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0) -# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0) -# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0) -# define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0) -# define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0) -# define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0) -# define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0) - -# define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4 - /* State based - direct writes to registers trigger vertex - generation */ -# define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4) -# define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4) -# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4) -# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4) - - /* I don't think I saw these three used.. */ -# define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6 -# define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9 -# define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10 - - /* index size - when not set the indices are assumed to be 16 bit */ -# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11) - /* number of vertices */ -# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16 - -/* BEGIN: Wild guesses */ -#define R300_VAP_OUTPUT_VTX_FMT_0 0x2090 -# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0) -# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1) -# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */ -# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */ -# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */ -# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */ - -#define R300_VAP_OUTPUT_VTX_FMT_1 0x2094 - /* each of the following is 3 bits wide, specifies number - of components */ -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 -/* END: Wild guesses */ - -#define R300_SE_VTE_CNTL 0x20b0 -# define R300_VPORT_X_SCALE_ENA 0x00000001 -# define R300_VPORT_X_OFFSET_ENA 0x00000002 -# define R300_VPORT_Y_SCALE_ENA 0x00000004 -# define R300_VPORT_Y_OFFSET_ENA 0x00000008 -# define R300_VPORT_Z_SCALE_ENA 0x00000010 -# define R300_VPORT_Z_OFFSET_ENA 0x00000020 -# define R300_VTX_XY_FMT 0x00000100 -# define R300_VTX_Z_FMT 0x00000200 -# define R300_VTX_W0_FMT 0x00000400 -# define R300_VTX_W0_NORMALIZE 0x00000800 -# define R300_VTX_ST_DENORMALIZED 0x00001000 - -/* BEGIN: Vertex data assembly - lots of uncertainties */ - -/* gap */ - -#define R300_VAP_CNTL_STATUS 0x2140 -# define R300_VC_NO_SWAP (0 << 0) -# define R300_VC_16BIT_SWAP (1 << 0) -# define R300_VC_32BIT_SWAP (2 << 0) -# define R300_VAP_TCL_BYPASS (1 << 8) - -/* gap */ - -/* Where do we get our vertex data? - * - * Vertex data either comes either from immediate mode registers or from - * vertex arrays. - * There appears to be no mixed mode (though we can force the pitch of - * vertex arrays to 0, effectively reusing the same element over and over - * again). - * - * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure - * if these registers influence vertex array processing. - * - * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3. - * - * In both cases, vertex attributes are then passed through INPUT_ROUTE. - * - * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data - * into the vertex processor's input registers. - * The first word routes the first input, the second word the second, etc. - * The corresponding input is routed into the register with the given index. - * The list is ended by a word with INPUT_ROUTE_END set. - * - * Always set COMPONENTS_4 in immediate mode. - */ - -#define R300_VAP_INPUT_ROUTE_0_0 0x2150 -# define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0) -# define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0) -# define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0) -# define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0) -# define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */ -# define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8 -# define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */ -# define R300_VAP_INPUT_ROUTE_END (1 << 13) -# define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */ -# define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */ -# define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */ -# define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */ -#define R300_VAP_INPUT_ROUTE_0_1 0x2154 -#define R300_VAP_INPUT_ROUTE_0_2 0x2158 -#define R300_VAP_INPUT_ROUTE_0_3 0x215C -#define R300_VAP_INPUT_ROUTE_0_4 0x2160 -#define R300_VAP_INPUT_ROUTE_0_5 0x2164 -#define R300_VAP_INPUT_ROUTE_0_6 0x2168 -#define R300_VAP_INPUT_ROUTE_0_7 0x216C - -/* gap */ - -/* Notes: - * - always set up to produce at least two attributes: - * if vertex program uses only position, fglrx will set normal, too - * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal. - */ -#define R300_VAP_INPUT_CNTL_0 0x2180 -# define R300_INPUT_CNTL_0_COLOR 0x00000001 -#define R300_VAP_INPUT_CNTL_1 0x2184 -# define R300_INPUT_CNTL_POS 0x00000001 -# define R300_INPUT_CNTL_NORMAL 0x00000002 -# define R300_INPUT_CNTL_COLOR 0x00000004 -# define R300_INPUT_CNTL_TC0 0x00000400 -# define R300_INPUT_CNTL_TC1 0x00000800 -# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */ -# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */ -# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */ -# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */ -# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */ -# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */ - -/* gap */ - -/* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0 - * are set to a swizzling bit pattern, other words are 0. - * - * In immediate mode, the pattern is always set to xyzw. In vertex array - * mode, the swizzling pattern is e.g. used to set zw components in texture - * coordinates with only tweo components. - */ -#define R300_VAP_INPUT_ROUTE_1_0 0x21E0 -# define R300_INPUT_ROUTE_SELECT_X 0 -# define R300_INPUT_ROUTE_SELECT_Y 1 -# define R300_INPUT_ROUTE_SELECT_Z 2 -# define R300_INPUT_ROUTE_SELECT_W 3 -# define R300_INPUT_ROUTE_SELECT_ZERO 4 -# define R300_INPUT_ROUTE_SELECT_ONE 5 -# define R300_INPUT_ROUTE_SELECT_MASK 7 -# define R300_INPUT_ROUTE_X_SHIFT 0 -# define R300_INPUT_ROUTE_Y_SHIFT 3 -# define R300_INPUT_ROUTE_Z_SHIFT 6 -# define R300_INPUT_ROUTE_W_SHIFT 9 -# define R300_INPUT_ROUTE_ENABLE (15 << 12) -#define R300_VAP_INPUT_ROUTE_1_1 0x21E4 -#define R300_VAP_INPUT_ROUTE_1_2 0x21E8 -#define R300_VAP_INPUT_ROUTE_1_3 0x21EC -#define R300_VAP_INPUT_ROUTE_1_4 0x21F0 -#define R300_VAP_INPUT_ROUTE_1_5 0x21F4 -#define R300_VAP_INPUT_ROUTE_1_6 0x21F8 -#define R300_VAP_INPUT_ROUTE_1_7 0x21FC - -/* END: Vertex data assembly */ - -/* gap */ - -/* BEGIN: Upload vertex program and data */ - -/* - * The programmable vertex shader unit has a memory bank of unknown size - * that can be written to in 16 byte units by writing the address into - * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs). - * - * Pointers into the memory bank are always in multiples of 16 bytes. - * - * The memory bank is divided into areas with fixed meaning. - * - * Starting at address UPLOAD_PROGRAM: Vertex program instructions. - * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB), - * whereas the difference between known addresses suggests size 512. - * - * Starting at address UPLOAD_PARAMETERS: Vertex program parameters. - * Native reported limits and the VPI layout suggest size 256, whereas - * difference between known addresses suggests size 512. - * - * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the - * floating point pointsize. The exact purpose of this state is uncertain, - * as there is also the R300_RE_POINTSIZE register. - * - * Multiple vertex programs and parameter sets can be loaded at once, - * which could explain the size discrepancy. - */ -#define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200 -# define R300_PVS_UPLOAD_PROGRAM 0x00000000 -# define R300_PVS_UPLOAD_PARAMETERS 0x00000200 -# define R300_PVS_UPLOAD_POINTSIZE 0x00000406 - -/* gap */ - -#define R300_VAP_PVS_UPLOAD_DATA 0x2208 - -/* END: Upload vertex program and data */ - -/* gap */ - -/* I do not know the purpose of this register. However, I do know that - * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL - * for normal rendering. - */ -#define R300_VAP_UNKNOWN_221C 0x221C -# define R300_221C_NORMAL 0x00000000 -# define R300_221C_CLEAR 0x0001C000 - -/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first - * plane is per-pixel and the second plane is per-vertex. - * - * This was determined by experimentation alone but I believe it is correct. - * - * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest. - */ -#define R300_VAP_CLIP_X_0 0x2220 -#define R300_VAP_CLIP_X_1 0x2224 -#define R300_VAP_CLIP_Y_0 0x2228 -#define R300_VAP_CLIP_Y_1 0x2230 - -/* gap */ - -/* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between - * rendering commands and overwriting vertex program parameters. - * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and - * avoids bugs caused by still running shaders reading bad data from memory. - */ -#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 - -/* Absolutely no clue what this register is about. */ -#define R300_VAP_UNKNOWN_2288 0x2288 -# define R300_2288_R300 0x00750000 /* -- nh */ -# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */ - -/* gap */ - -/* Addresses are relative to the vertex program instruction area of the - * memory bank. PROGRAM_END points to the last instruction of the active - * program - * - * The meaning of the two UNKNOWN fields is obviously not known. However, - * experiments so far have shown that both *must* point to an instruction - * inside the vertex program, otherwise the GPU locks up. - * - * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and - * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to - * position takes place. - * - * Most likely this is used to ignore rest of the program in cases - * where group of verts arent visible. For some reason this "section" - * is sometimes accepted other instruction that have no relationship with - * position calculations. - */ -#define R300_VAP_PVS_CNTL_1 0x22D0 -# define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0 -# define R300_PVS_CNTL_1_POS_END_SHIFT 10 -# define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20 -/* Addresses are relative the the vertex program parameters area. */ -#define R300_VAP_PVS_CNTL_2 0x22D4 -# define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0 -# define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16 -#define R300_VAP_PVS_CNTL_3 0x22D8 -# define R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT 10 -# define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT 0 - -/* The entire range from 0x2300 to 0x2AC inclusive seems to be used for - * immediate vertices - */ -#define R300_VAP_VTX_COLOR_R 0x2464 -#define R300_VAP_VTX_COLOR_G 0x2468 -#define R300_VAP_VTX_COLOR_B 0x246C -#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */ -#define R300_VAP_VTX_POS_0_Y_1 0x2494 -#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */ -#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */ -#define R300_VAP_VTX_POS_0_Y_2 0x24A4 -#define R300_VAP_VTX_POS_0_Z_2 0x24A8 -/* write 0 to indicate end of packet? */ -#define R300_VAP_VTX_END_OF_PKT 0x24AC - -/* gap */ - -/* These are values from r300_reg/r300_reg.h - they are known to be correct - * and are here so we can use one register file instead of several - * - Vladimir - */ -#define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000 -# define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0) -# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1) -# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2) -# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3) -# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4) -# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5) -# define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16) - -#define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004 - /* each of the following is 3 bits wide, specifies number - of components */ -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 - -/* UNK30 seems to enables point to quad transformation on textures - * (or something closely related to that). - * This bit is rather fatal at the time being due to lackings at pixel - * shader side - */ -#define R300_GB_ENABLE 0x4008 -# define R300_GB_POINT_STUFF_ENABLE (1<<0) -# define R300_GB_LINE_STUFF_ENABLE (1<<1) -# define R300_GB_TRIANGLE_STUFF_ENABLE (1<<2) -# define R300_GB_STENCIL_AUTO_ENABLE (1<<4) -# define R300_GB_UNK31 (1<<31) - /* each of the following is 2 bits wide */ -#define R300_GB_TEX_REPLICATE 0 -#define R300_GB_TEX_ST 1 -#define R300_GB_TEX_STR 2 -# define R300_GB_TEX0_SOURCE_SHIFT 16 -# define R300_GB_TEX1_SOURCE_SHIFT 18 -# define R300_GB_TEX2_SOURCE_SHIFT 20 -# define R300_GB_TEX3_SOURCE_SHIFT 22 -# define R300_GB_TEX4_SOURCE_SHIFT 24 -# define R300_GB_TEX5_SOURCE_SHIFT 26 -# define R300_GB_TEX6_SOURCE_SHIFT 28 -# define R300_GB_TEX7_SOURCE_SHIFT 30 - -/* MSPOS - positions for multisample antialiasing (?) */ -#define R300_GB_MSPOS0 0x4010 - /* shifts - each of the fields is 4 bits */ -# define R300_GB_MSPOS0__MS_X0_SHIFT 0 -# define R300_GB_MSPOS0__MS_Y0_SHIFT 4 -# define R300_GB_MSPOS0__MS_X1_SHIFT 8 -# define R300_GB_MSPOS0__MS_Y1_SHIFT 12 -# define R300_GB_MSPOS0__MS_X2_SHIFT 16 -# define R300_GB_MSPOS0__MS_Y2_SHIFT 20 -# define R300_GB_MSPOS0__MSBD0_Y 24 -# define R300_GB_MSPOS0__MSBD0_X 28 - -#define R300_GB_MSPOS1 0x4014 -# define R300_GB_MSPOS1__MS_X3_SHIFT 0 -# define R300_GB_MSPOS1__MS_Y3_SHIFT 4 -# define R300_GB_MSPOS1__MS_X4_SHIFT 8 -# define R300_GB_MSPOS1__MS_Y4_SHIFT 12 -# define R300_GB_MSPOS1__MS_X5_SHIFT 16 -# define R300_GB_MSPOS1__MS_Y5_SHIFT 20 -# define R300_GB_MSPOS1__MSBD1 24 - - -#define R300_GB_TILE_CONFIG 0x4018 -# define R300_GB_TILE_ENABLE (1<<0) -# define R300_GB_TILE_PIPE_COUNT_RV300 0 -# define R300_GB_TILE_PIPE_COUNT_R300 (3<<1) -# define R300_GB_TILE_PIPE_COUNT_R420 (7<<1) -# define R300_GB_TILE_PIPE_COUNT_RV410 (3<<1) -# define R300_GB_TILE_SIZE_8 0 -# define R300_GB_TILE_SIZE_16 (1<<4) -# define R300_GB_TILE_SIZE_32 (2<<4) -# define R300_GB_SUPER_SIZE_1 (0<<6) -# define R300_GB_SUPER_SIZE_2 (1<<6) -# define R300_GB_SUPER_SIZE_4 (2<<6) -# define R300_GB_SUPER_SIZE_8 (3<<6) -# define R300_GB_SUPER_SIZE_16 (4<<6) -# define R300_GB_SUPER_SIZE_32 (5<<6) -# define R300_GB_SUPER_SIZE_64 (6<<6) -# define R300_GB_SUPER_SIZE_128 (7<<6) -# define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */ -# define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */ -# define R300_GB_SUPER_TILE_A 0 -# define R300_GB_SUPER_TILE_B (1<<15) -# define R300_GB_SUBPIXEL_1_12 0 -# define R300_GB_SUBPIXEL_1_16 (1<<16) - -#define R300_GB_FIFO_SIZE 0x4024 - /* each of the following is 2 bits wide */ -#define R300_GB_FIFO_SIZE_32 0 -#define R300_GB_FIFO_SIZE_64 1 -#define R300_GB_FIFO_SIZE_128 2 -#define R300_GB_FIFO_SIZE_256 3 -# define R300_SC_IFIFO_SIZE_SHIFT 0 -# define R300_SC_TZFIFO_SIZE_SHIFT 2 -# define R300_SC_BFIFO_SIZE_SHIFT 4 - -# define R300_US_OFIFO_SIZE_SHIFT 12 -# define R300_US_WFIFO_SIZE_SHIFT 14 - /* the following use the same constants as above, but meaning is - is times 2 (i.e. instead of 32 words it means 64 */ -# define R300_RS_TFIFO_SIZE_SHIFT 6 -# define R300_RS_CFIFO_SIZE_SHIFT 8 -# define R300_US_RAM_SIZE_SHIFT 10 - /* watermarks, 3 bits wide */ -# define R300_RS_HIGHWATER_COL_SHIFT 16 -# define R300_RS_HIGHWATER_TEX_SHIFT 19 -# define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */ -# define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24 - -#define R300_GB_SELECT 0x401C -# define R300_GB_FOG_SELECT_C0A 0 -# define R300_GB_FOG_SELECT_C1A 1 -# define R300_GB_FOG_SELECT_C2A 2 -# define R300_GB_FOG_SELECT_C3A 3 -# define R300_GB_FOG_SELECT_1_1_W 4 -# define R300_GB_FOG_SELECT_Z 5 -# define R300_GB_DEPTH_SELECT_Z 0 -# define R300_GB_DEPTH_SELECT_1_1_W (1<<3) -# define R300_GB_W_SELECT_1_W 0 -# define R300_GB_W_SELECT_1 (1<<4) - -#define R300_GB_AA_CONFIG 0x4020 -# define R300_AA_DISABLE 0x00 -# define R300_AA_ENABLE 0x01 -# define R300_AA_SUBSAMPLES_2 0 -# define R300_AA_SUBSAMPLES_3 (1<<1) -# define R300_AA_SUBSAMPLES_4 (2<<1) -# define R300_AA_SUBSAMPLES_6 (3<<1) - -/* gap */ - -/* Zero to flush caches. */ -#define R300_TX_INVALTAGS 0x4100 -#define R300_TX_FLUSH 0x0 - -/* The upper enable bits are guessed, based on fglrx reported limits. */ -#define R300_TX_ENABLE 0x4104 -# define R300_TX_ENABLE_0 (1 << 0) -# define R300_TX_ENABLE_1 (1 << 1) -# define R300_TX_ENABLE_2 (1 << 2) -# define R300_TX_ENABLE_3 (1 << 3) -# define R300_TX_ENABLE_4 (1 << 4) -# define R300_TX_ENABLE_5 (1 << 5) -# define R300_TX_ENABLE_6 (1 << 6) -# define R300_TX_ENABLE_7 (1 << 7) -# define R300_TX_ENABLE_8 (1 << 8) -# define R300_TX_ENABLE_9 (1 << 9) -# define R300_TX_ENABLE_10 (1 << 10) -# define R300_TX_ENABLE_11 (1 << 11) -# define R300_TX_ENABLE_12 (1 << 12) -# define R300_TX_ENABLE_13 (1 << 13) -# define R300_TX_ENABLE_14 (1 << 14) -# define R300_TX_ENABLE_15 (1 << 15) - -/* The pointsize is given in multiples of 6. The pointsize can be - * enormous: Clear() renders a single point that fills the entire - * framebuffer. - */ -#define R300_RE_POINTSIZE 0x421C -# define R300_POINTSIZE_Y_SHIFT 0 -# define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */ -# define R300_POINTSIZE_X_SHIFT 16 -# define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */ -# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6) - -/* The line width is given in multiples of 6. - * In default mode lines are classified as vertical lines. - * HO: horizontal - * VE: vertical or horizontal - * HO & VE: no classification - */ -#define R300_RE_LINE_CNT 0x4234 -# define R300_LINESIZE_SHIFT 0 -# define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */ -# define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6) -# define R300_LINE_CNT_HO (1 << 16) -# define R300_LINE_CNT_VE (1 << 17) - -/* Some sort of scale or clamp value for texcoordless textures. */ -#define R300_RE_UNK4238 0x4238 - -/* Something shade related */ -#define R300_RE_SHADE 0x4274 - -#define R300_RE_SHADE_MODEL 0x4278 -# define R300_RE_SHADE_MODEL_SMOOTH 0x3aaaa -# define R300_RE_SHADE_MODEL_FLAT 0x39595 - -/* Dangerous */ -#define R300_RE_POLYGON_MODE 0x4288 -# define R300_PM_ENABLED (1 << 0) -# define R300_PM_FRONT_POINT (0 << 0) -# define R300_PM_BACK_POINT (0 << 0) -# define R300_PM_FRONT_LINE (1 << 4) -# define R300_PM_FRONT_FILL (1 << 5) -# define R300_PM_BACK_LINE (1 << 7) -# define R300_PM_BACK_FILL (1 << 8) - -/* Fog parameters */ -#define R300_RE_FOG_SCALE 0x4294 -#define R300_RE_FOG_START 0x4298 - -/* Not sure why there are duplicate of factor and constant values. - * My best guess so far is that there are seperate zbiases for test and write. - * Ordering might be wrong. - * Some of the tests indicate that fgl has a fallback implementation of zbias - * via pixel shaders. - */ -#define R300_RE_ZBIAS_CNTL 0x42A0 /* GUESS */ -#define R300_RE_ZBIAS_T_FACTOR 0x42A4 -#define R300_RE_ZBIAS_T_CONSTANT 0x42A8 -#define R300_RE_ZBIAS_W_FACTOR 0x42AC -#define R300_RE_ZBIAS_W_CONSTANT 0x42B0 - -/* This register needs to be set to (1<<1) for RV350 to correctly - * perform depth test (see --vb-triangles in r300_demo) - * Don't know about other chips. - Vladimir - * This is set to 3 when GL_POLYGON_OFFSET_FILL is on. - * My guess is that there are two bits for each zbias primitive - * (FILL, LINE, POINT). - * One to enable depth test and one for depth write. - * Yet this doesnt explain why depth writes work ... - */ -#define R300_RE_OCCLUSION_CNTL 0x42B4 -# define R300_OCCLUSION_ON (1<<1) - -#define R300_RE_CULL_CNTL 0x42B8 -# define R300_CULL_FRONT (1 << 0) -# define R300_CULL_BACK (1 << 1) -# define R300_FRONT_FACE_CCW (0 << 2) -# define R300_FRONT_FACE_CW (1 << 2) - - -/* BEGIN: Rasterization / Interpolators - many guesses */ - -/* 0_UNKNOWN_18 has always been set except for clear operations. - * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends - * on the vertex program, *not* the fragment program) - */ -#define R300_RS_CNTL_0 0x4300 -# define R300_RS_CNTL_TC_CNT_SHIFT 2 -# define R300_RS_CNTL_TC_CNT_MASK (7 << 2) - /* number of color interpolators used */ -# define R300_RS_CNTL_CI_CNT_SHIFT 7 -# define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18) - /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n - register. */ -#define R300_RS_CNTL_1 0x4304 - -/* gap */ - -/* Only used for texture coordinates. - * Use the source field to route texture coordinate input from the - * vertex program to the desired interpolator. Note that the source - * field is relative to the outputs the vertex program *actually* - * writes. If a vertex program only writes texcoord[1], this will - * be source index 0. - * Set INTERP_USED on all interpolators that produce data used by - * the fragment program. INTERP_USED looks like a swizzling mask, - * but I haven't seen it used that way. - * - * Note: The _UNKNOWN constants are always set in their respective - * register. I don't know if this is necessary. - */ -#define R300_RS_INTERP_0 0x4310 -#define R300_RS_INTERP_1 0x4314 -# define R300_RS_INTERP_1_UNKNOWN 0x40 -#define R300_RS_INTERP_2 0x4318 -# define R300_RS_INTERP_2_UNKNOWN 0x80 -#define R300_RS_INTERP_3 0x431C -# define R300_RS_INTERP_3_UNKNOWN 0xC0 -#define R300_RS_INTERP_4 0x4320 -#define R300_RS_INTERP_5 0x4324 -#define R300_RS_INTERP_6 0x4328 -#define R300_RS_INTERP_7 0x432C -# define R300_RS_INTERP_SRC_SHIFT 2 -# define R300_RS_INTERP_SRC_MASK (7 << 2) -# define R300_RS_INTERP_USED 0x00D10000 - -/* These DWORDs control how vertex data is routed into fragment program - * registers, after interpolators. - */ -#define R300_RS_ROUTE_0 0x4330 -#define R300_RS_ROUTE_1 0x4334 -#define R300_RS_ROUTE_2 0x4338 -#define R300_RS_ROUTE_3 0x433C /* GUESS */ -#define R300_RS_ROUTE_4 0x4340 /* GUESS */ -#define R300_RS_ROUTE_5 0x4344 /* GUESS */ -#define R300_RS_ROUTE_6 0x4348 /* GUESS */ -#define R300_RS_ROUTE_7 0x434C /* GUESS */ -# define R300_RS_ROUTE_SOURCE_INTERP_0 0 -# define R300_RS_ROUTE_SOURCE_INTERP_1 1 -# define R300_RS_ROUTE_SOURCE_INTERP_2 2 -# define R300_RS_ROUTE_SOURCE_INTERP_3 3 -# define R300_RS_ROUTE_SOURCE_INTERP_4 4 -# define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */ -# define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */ -# define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */ -# define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */ -# define R300_RS_ROUTE_DEST_SHIFT 6 -# define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */ - -/* Special handling for color: When the fragment program uses color, - * the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the - * color register index. - * - * Apperently you may set the R300_RS_ROUTE_0_COLOR bit, but not provide any - * R300_RS_ROUTE_0_COLOR_DEST value; this setup is used for clearing the state. - * See r300_ioctl.c:r300EmitClearState. I'm not sure if this setup is strictly - * correct or not. - Oliver. - */ -# define R300_RS_ROUTE_0_COLOR (1 << 14) -# define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17 -# define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */ -/* As above, but for secondary color */ -# define R300_RS_ROUTE_1_COLOR1 (1 << 14) -# define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17 -# define R300_RS_ROUTE_1_COLOR1_DEST_MASK (31 << 17) -# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) -/* END: Rasterization / Interpolators - many guesses */ - -/* Hierarchical Z Enable */ -#define R300_SC_HYPERZ 0x43a4 -# define R300_SC_HYPERZ_DISABLE (0 << 0) -# define R300_SC_HYPERZ_ENABLE (1 << 0) -# define R300_SC_HYPERZ_MIN (0 << 1) -# define R300_SC_HYPERZ_MAX (1 << 1) -# define R300_SC_HYPERZ_ADJ_256 (0 << 2) -# define R300_SC_HYPERZ_ADJ_128 (1 << 2) -# define R300_SC_HYPERZ_ADJ_64 (2 << 2) -# define R300_SC_HYPERZ_ADJ_32 (3 << 2) -# define R300_SC_HYPERZ_ADJ_16 (4 << 2) -# define R300_SC_HYPERZ_ADJ_8 (5 << 2) -# define R300_SC_HYPERZ_ADJ_4 (6 << 2) -# define R300_SC_HYPERZ_ADJ_2 (7 << 2) -# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5) -# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5) -# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6) -# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6) - -#define R300_SC_EDGERULE 0x43a8 - -/* BEGIN: Scissors and cliprects */ - -/* There are four clipping rectangles. Their corner coordinates are inclusive. - * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending - * on whether the pixel is inside cliprects 0-3, respectively. For example, - * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned - * the number 3 (binary 0011). - * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set, - * the pixel is rasterized. - * - * In addition to this, there is a scissors rectangle. Only pixels inside the - * scissors rectangle are drawn. (coordinates are inclusive) - * - * For some reason, the top-left corner of the framebuffer is at (1440, 1440) - * for the purpose of clipping and scissors. - */ -#define R300_RE_CLIPRECT_TL_0 0x43B0 -#define R300_RE_CLIPRECT_BR_0 0x43B4 -#define R300_RE_CLIPRECT_TL_1 0x43B8 -#define R300_RE_CLIPRECT_BR_1 0x43BC -#define R300_RE_CLIPRECT_TL_2 0x43C0 -#define R300_RE_CLIPRECT_BR_2 0x43C4 -#define R300_RE_CLIPRECT_TL_3 0x43C8 -#define R300_RE_CLIPRECT_BR_3 0x43CC -# define R300_CLIPRECT_OFFSET 1440 -# define R300_CLIPRECT_MASK 0x1FFF -# define R300_CLIPRECT_X_SHIFT 0 -# define R300_CLIPRECT_X_MASK (0x1FFF << 0) -# define R300_CLIPRECT_Y_SHIFT 13 -# define R300_CLIPRECT_Y_MASK (0x1FFF << 13) -#define R300_RE_CLIPRECT_CNTL 0x43D0 -# define R300_CLIP_OUT (1 << 0) -# define R300_CLIP_0 (1 << 1) -# define R300_CLIP_1 (1 << 2) -# define R300_CLIP_10 (1 << 3) -# define R300_CLIP_2 (1 << 4) -# define R300_CLIP_20 (1 << 5) -# define R300_CLIP_21 (1 << 6) -# define R300_CLIP_210 (1 << 7) -# define R300_CLIP_3 (1 << 8) -# define R300_CLIP_30 (1 << 9) -# define R300_CLIP_31 (1 << 10) -# define R300_CLIP_310 (1 << 11) -# define R300_CLIP_32 (1 << 12) -# define R300_CLIP_320 (1 << 13) -# define R300_CLIP_321 (1 << 14) -# define R300_CLIP_3210 (1 << 15) - -/* gap */ - -#define R300_RE_SCISSORS_TL 0x43E0 -#define R300_RE_SCISSORS_BR 0x43E4 -# define R300_SCISSORS_OFFSET 1440 -# define R300_SCISSORS_X_SHIFT 0 -# define R300_SCISSORS_X_MASK (0x1FFF << 0) -# define R300_SCISSORS_Y_SHIFT 13 -# define R300_SCISSORS_Y_MASK (0x1FFF << 13) -/* END: Scissors and cliprects */ - -/* BEGIN: Texture specification */ - -/* - * The texture specification dwords are grouped by meaning and not by texture - * unit. This means that e.g. the offset for texture image unit N is found in - * register TX_OFFSET_0 + (4*N) - */ -#define R300_TX_FILTER_0 0x4400 -# define R300_TX_REPEAT 0 -# define R300_TX_MIRRORED 1 -# define R300_TX_CLAMP 4 -# define R300_TX_CLAMP_TO_EDGE 2 -# define R300_TX_CLAMP_TO_BORDER 6 -# define R300_TX_WRAP_S_SHIFT 0 -# define R300_TX_WRAP_S_MASK (7 << 0) -# define R300_TX_WRAP_T_SHIFT 3 -# define R300_TX_WRAP_T_MASK (7 << 3) -# define R300_TX_WRAP_Q_SHIFT 6 -# define R300_TX_WRAP_Q_MASK (7 << 6) -# define R300_TX_MAG_FILTER_NEAREST (1 << 9) -# define R300_TX_MAG_FILTER_LINEAR (2 << 9) -# define R300_TX_MAG_FILTER_MASK (3 << 9) -# define R300_TX_MIN_FILTER_NEAREST (1 << 11) -# define R300_TX_MIN_FILTER_LINEAR (2 << 11) -# define R300_TX_MIN_FILTER_NEAREST_MIP_NEAREST (5 << 11) -# define R300_TX_MIN_FILTER_NEAREST_MIP_LINEAR (9 << 11) -# define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 11) -# define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11) - -/* NOTE: NEAREST doesnt seem to exist. - * Im not seting MAG_FILTER_MASK and (3 << 11) on for all - * anisotropy modes because that would void selected mag filter - */ -# define R300_TX_MIN_FILTER_ANISO_NEAREST (0 << 13) -# define R300_TX_MIN_FILTER_ANISO_LINEAR (0 << 13) -# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (1 << 13) -# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (2 << 13) -# define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) ) -# define R300_TX_MAX_ANISO_1_TO_1 (0 << 21) -# define R300_TX_MAX_ANISO_2_TO_1 (2 << 21) -# define R300_TX_MAX_ANISO_4_TO_1 (4 << 21) -# define R300_TX_MAX_ANISO_8_TO_1 (6 << 21) -# define R300_TX_MAX_ANISO_16_TO_1 (8 << 21) -# define R300_TX_MAX_ANISO_MASK (14 << 21) - -#define R300_TX_FILTER1_0 0x4440 -# define R300_CHROMA_KEY_MODE_DISABLE 0 -# define R300_CHROMA_KEY_FORCE 1 -# define R300_CHROMA_KEY_BLEND 2 -# define R300_MC_ROUND_NORMAL (0<<2) -# define R300_MC_ROUND_MPEG4 (1<<2) -# define R300_LOD_BIAS_MASK 0x1fff -# define R300_EDGE_ANISO_EDGE_DIAG (0<<13) -# define R300_EDGE_ANISO_EDGE_ONLY (1<<13) -# define R300_MC_COORD_TRUNCATE_DISABLE (0<<14) -# define R300_MC_COORD_TRUNCATE_MPEG (1<<14) -# define R300_TX_TRI_PERF_0_8 (0<<15) -# define R300_TX_TRI_PERF_1_8 (1<<15) -# define R300_TX_TRI_PERF_1_4 (2<<15) -# define R300_TX_TRI_PERF_3_8 (3<<15) -# define R300_ANISO_THRESHOLD_MASK (7<<17) - -#define R300_TX_SIZE_0 0x4480 -# define R300_TX_WIDTHMASK_SHIFT 0 -# define R300_TX_WIDTHMASK_MASK (2047 << 0) -# define R300_TX_HEIGHTMASK_SHIFT 11 -# define R300_TX_HEIGHTMASK_MASK (2047 << 11) -# define R300_TX_UNK23 (1 << 23) -# define R300_TX_MAX_MIP_LEVEL_SHIFT 26 -# define R300_TX_MAX_MIP_LEVEL_MASK (0xf << 26) -# define R300_TX_SIZE_PROJECTED (1<<30) -# define R300_TX_SIZE_TXPITCH_EN (1<<31) -#define R300_TX_FORMAT_0 0x44C0 - /* The interpretation of the format word by Wladimir van der Laan */ - /* The X, Y, Z and W refer to the layout of the components. - They are given meanings as R, G, B and Alpha by the swizzle - specification */ -# define R300_TX_FORMAT_X8 0x0 -# define R300_TX_FORMAT_X16 0x1 -# define R300_TX_FORMAT_Y4X4 0x2 -# define R300_TX_FORMAT_Y8X8 0x3 -# define R300_TX_FORMAT_Y16X16 0x4 -# define R300_TX_FORMAT_Z3Y3X2 0x5 -# define R300_TX_FORMAT_Z5Y6X5 0x6 -# define R300_TX_FORMAT_Z6Y5X5 0x7 -# define R300_TX_FORMAT_Z11Y11X10 0x8 -# define R300_TX_FORMAT_Z10Y11X11 0x9 -# define R300_TX_FORMAT_W4Z4Y4X4 0xA -# define R300_TX_FORMAT_W1Z5Y5X5 0xB -# define R300_TX_FORMAT_W8Z8Y8X8 0xC -# define R300_TX_FORMAT_W2Z10Y10X10 0xD -# define R300_TX_FORMAT_W16Z16Y16X16 0xE -# define R300_TX_FORMAT_DXT1 0xF -# define R300_TX_FORMAT_DXT3 0x10 -# define R300_TX_FORMAT_DXT5 0x11 -# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ -# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ -# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ -# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ - /* 0x16 - some 16 bit green format.. ?? */ -# define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */ -# define R300_TX_FORMAT_CUBIC_MAP (1 << 26) - - /* gap */ - /* Floating point formats */ - /* Note - hardware supports both 16 and 32 bit floating point */ -# define R300_TX_FORMAT_FL_I16 0x18 -# define R300_TX_FORMAT_FL_I16A16 0x19 -# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A -# define R300_TX_FORMAT_FL_I32 0x1B -# define R300_TX_FORMAT_FL_I32A32 0x1C -# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D - /* alpha modes, convenience mostly */ - /* if you have alpha, pick constant appropriate to the - number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ -# define R300_TX_FORMAT_ALPHA_1CH 0x000 -# define R300_TX_FORMAT_ALPHA_2CH 0x200 -# define R300_TX_FORMAT_ALPHA_4CH 0x600 -# define R300_TX_FORMAT_ALPHA_NONE 0xA00 - /* Swizzling */ - /* constants */ -# define R300_TX_FORMAT_X 0 -# define R300_TX_FORMAT_Y 1 -# define R300_TX_FORMAT_Z 2 -# define R300_TX_FORMAT_W 3 -# define R300_TX_FORMAT_ZERO 4 -# define R300_TX_FORMAT_ONE 5 - /* 2.0*Z, everything above 1.0 is set to 0.0 */ -# define R300_TX_FORMAT_CUT_Z 6 - /* 2.0*W, everything above 1.0 is set to 0.0 */ -# define R300_TX_FORMAT_CUT_W 7 - -# define R300_TX_FORMAT_B_SHIFT 18 -# define R300_TX_FORMAT_G_SHIFT 15 -# define R300_TX_FORMAT_R_SHIFT 12 -# define R300_TX_FORMAT_A_SHIFT 9 - /* Convenience macro to take care of layout and swizzling */ -# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \ - ((R300_TX_FORMAT_##B)< 0.5, return ARG0, else return ARG1 - * - CMP: If ARG2 < 0, return ARG1, else return ARG0 - * - FLR: use FRC+MAD - * - XPD: use MAD+MAD - * - SGE, SLT: use MAD+CMP - * - RSQ: use ABS modifier for argument - * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation - * (e.g. RCP) into color register - * - apparently, there's no quick DST operation - * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2" - * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0" - * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1" - * - * Operand selection - * First stage selects three sources from the available registers and - * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha). - * fglrx sorts the three source fields: Registers before constants, - * lower indices before higher indices; I do not know whether this is - * necessary. - * - * fglrx fills unused sources with "read constant 0" - * According to specs, you cannot select more than two different constants. - * - * Second stage selects the operands from the sources. This is defined in - * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants - * zero and one. - * Swizzling and negation happens in this stage, as well. - * - * Important: Color and alpha seem to be mostly separate, i.e. their sources - * selection appears to be fully independent (the register storage is probably - * physically split into a color and an alpha section). - * However (because of the apparent physical split), there is some interaction - * WRT swizzling. If, for example, you want to load an R component into an - * Alpha operand, this R component is taken from a *color* source, not from - * an alpha source. The corresponding register doesn't even have to appear in - * the alpha sources list. (I hope this all makes sense to you) - * - * Destination selection - * The destination register index is in FPI1 (color) and FPI3 (alpha) - * together with enable bits. - * There are separate enable bits for writing into temporary registers - * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_* - * /DSTA_OUTPUT). You can write to both at once, or not write at all (the - * same index must be used for both). - * - * Note: There is a special form for LRP - * - Argument order is the same as in ARB_fragment_program. - * - Operation is MAD - * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP - * - Set FPI0/FPI2_SPECIAL_LRP - * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD - */ -#define R300_PFS_INSTR1_0 0x46C0 -# define R300_FPI1_SRC0C_SHIFT 0 -# define R300_FPI1_SRC0C_MASK (31 << 0) -# define R300_FPI1_SRC0C_CONST (1 << 5) -# define R300_FPI1_SRC1C_SHIFT 6 -# define R300_FPI1_SRC1C_MASK (31 << 6) -# define R300_FPI1_SRC1C_CONST (1 << 11) -# define R300_FPI1_SRC2C_SHIFT 12 -# define R300_FPI1_SRC2C_MASK (31 << 12) -# define R300_FPI1_SRC2C_CONST (1 << 17) -# define R300_FPI1_SRC_MASK 0x0003ffff -# define R300_FPI1_DSTC_SHIFT 18 -# define R300_FPI1_DSTC_MASK (31 << 18) -# define R300_FPI1_DSTC_REG_MASK_SHIFT 23 -# define R300_FPI1_DSTC_REG_X (1 << 23) -# define R300_FPI1_DSTC_REG_Y (1 << 24) -# define R300_FPI1_DSTC_REG_Z (1 << 25) -# define R300_FPI1_DSTC_OUTPUT_MASK_SHIFT 26 -# define R300_FPI1_DSTC_OUTPUT_X (1 << 26) -# define R300_FPI1_DSTC_OUTPUT_Y (1 << 27) -# define R300_FPI1_DSTC_OUTPUT_Z (1 << 28) - -#define R300_PFS_INSTR3_0 0x47C0 -# define R300_FPI3_SRC0A_SHIFT 0 -# define R300_FPI3_SRC0A_MASK (31 << 0) -# define R300_FPI3_SRC0A_CONST (1 << 5) -# define R300_FPI3_SRC1A_SHIFT 6 -# define R300_FPI3_SRC1A_MASK (31 << 6) -# define R300_FPI3_SRC1A_CONST (1 << 11) -# define R300_FPI3_SRC2A_SHIFT 12 -# define R300_FPI3_SRC2A_MASK (31 << 12) -# define R300_FPI3_SRC2A_CONST (1 << 17) -# define R300_FPI3_SRC_MASK 0x0003ffff -# define R300_FPI3_DSTA_SHIFT 18 -# define R300_FPI3_DSTA_MASK (31 << 18) -# define R300_FPI3_DSTA_REG (1 << 23) -# define R300_FPI3_DSTA_OUTPUT (1 << 24) -# define R300_FPI3_DSTA_DEPTH (1 << 27) - -#define R300_PFS_INSTR0_0 0x48C0 -# define R300_FPI0_ARGC_SRC0C_XYZ 0 -# define R300_FPI0_ARGC_SRC0C_XXX 1 -# define R300_FPI0_ARGC_SRC0C_YYY 2 -# define R300_FPI0_ARGC_SRC0C_ZZZ 3 -# define R300_FPI0_ARGC_SRC1C_XYZ 4 -# define R300_FPI0_ARGC_SRC1C_XXX 5 -# define R300_FPI0_ARGC_SRC1C_YYY 6 -# define R300_FPI0_ARGC_SRC1C_ZZZ 7 -# define R300_FPI0_ARGC_SRC2C_XYZ 8 -# define R300_FPI0_ARGC_SRC2C_XXX 9 -# define R300_FPI0_ARGC_SRC2C_YYY 10 -# define R300_FPI0_ARGC_SRC2C_ZZZ 11 -# define R300_FPI0_ARGC_SRC0A 12 -# define R300_FPI0_ARGC_SRC1A 13 -# define R300_FPI0_ARGC_SRC2A 14 -# define R300_FPI0_ARGC_SRC1C_LRP 15 -# define R300_FPI0_ARGC_ZERO 20 -# define R300_FPI0_ARGC_ONE 21 - /* GUESS */ -# define R300_FPI0_ARGC_HALF 22 -# define R300_FPI0_ARGC_SRC0C_YZX 23 -# define R300_FPI0_ARGC_SRC1C_YZX 24 -# define R300_FPI0_ARGC_SRC2C_YZX 25 -# define R300_FPI0_ARGC_SRC0C_ZXY 26 -# define R300_FPI0_ARGC_SRC1C_ZXY 27 -# define R300_FPI0_ARGC_SRC2C_ZXY 28 -# define R300_FPI0_ARGC_SRC0CA_WZY 29 -# define R300_FPI0_ARGC_SRC1CA_WZY 30 -# define R300_FPI0_ARGC_SRC2CA_WZY 31 - -# define R300_FPI0_ARG0C_SHIFT 0 -# define R300_FPI0_ARG0C_MASK (31 << 0) -# define R300_FPI0_ARG0C_NEG (1 << 5) -# define R300_FPI0_ARG0C_ABS (1 << 6) -# define R300_FPI0_ARG1C_SHIFT 7 -# define R300_FPI0_ARG1C_MASK (31 << 7) -# define R300_FPI0_ARG1C_NEG (1 << 12) -# define R300_FPI0_ARG1C_ABS (1 << 13) -# define R300_FPI0_ARG2C_SHIFT 14 -# define R300_FPI0_ARG2C_MASK (31 << 14) -# define R300_FPI0_ARG2C_NEG (1 << 19) -# define R300_FPI0_ARG2C_ABS (1 << 20) -# define R300_FPI0_SPECIAL_LRP (1 << 21) -# define R300_FPI0_OUTC_MAD (0 << 23) -# define R300_FPI0_OUTC_DP3 (1 << 23) -# define R300_FPI0_OUTC_DP4 (2 << 23) -# define R300_FPI0_OUTC_MIN (4 << 23) -# define R300_FPI0_OUTC_MAX (5 << 23) -# define R300_FPI0_OUTC_CMPH (7 << 23) -# define R300_FPI0_OUTC_CMP (8 << 23) -# define R300_FPI0_OUTC_FRC (9 << 23) -# define R300_FPI0_OUTC_REPL_ALPHA (10 << 23) -# define R300_FPI0_OUTC_SAT (1 << 30) -# define R300_FPI0_INSERT_NOP (1 << 31) - -#define R300_PFS_INSTR2_0 0x49C0 -# define R300_FPI2_ARGA_SRC0C_X 0 -# define R300_FPI2_ARGA_SRC0C_Y 1 -# define R300_FPI2_ARGA_SRC0C_Z 2 -# define R300_FPI2_ARGA_SRC1C_X 3 -# define R300_FPI2_ARGA_SRC1C_Y 4 -# define R300_FPI2_ARGA_SRC1C_Z 5 -# define R300_FPI2_ARGA_SRC2C_X 6 -# define R300_FPI2_ARGA_SRC2C_Y 7 -# define R300_FPI2_ARGA_SRC2C_Z 8 -# define R300_FPI2_ARGA_SRC0A 9 -# define R300_FPI2_ARGA_SRC1A 10 -# define R300_FPI2_ARGA_SRC2A 11 -# define R300_FPI2_ARGA_SRC1A_LRP 15 -# define R300_FPI2_ARGA_ZERO 16 -# define R300_FPI2_ARGA_ONE 17 - /* GUESS */ -# define R300_FPI2_ARGA_HALF 18 -# define R300_FPI2_ARG0A_SHIFT 0 -# define R300_FPI2_ARG0A_MASK (31 << 0) -# define R300_FPI2_ARG0A_NEG (1 << 5) - /* GUESS */ -# define R300_FPI2_ARG0A_ABS (1 << 6) -# define R300_FPI2_ARG1A_SHIFT 7 -# define R300_FPI2_ARG1A_MASK (31 << 7) -# define R300_FPI2_ARG1A_NEG (1 << 12) - /* GUESS */ -# define R300_FPI2_ARG1A_ABS (1 << 13) -# define R300_FPI2_ARG2A_SHIFT 14 -# define R300_FPI2_ARG2A_MASK (31 << 14) -# define R300_FPI2_ARG2A_NEG (1 << 19) - /* GUESS */ -# define R300_FPI2_ARG2A_ABS (1 << 20) -# define R300_FPI2_SPECIAL_LRP (1 << 21) -# define R300_FPI2_OUTA_MAD (0 << 23) -# define R300_FPI2_OUTA_DP4 (1 << 23) -# define R300_FPI2_OUTA_MIN (2 << 23) -# define R300_FPI2_OUTA_MAX (3 << 23) -# define R300_FPI2_OUTA_CMP (6 << 23) -# define R300_FPI2_OUTA_FRC (7 << 23) -# define R300_FPI2_OUTA_EX2 (8 << 23) -# define R300_FPI2_OUTA_LG2 (9 << 23) -# define R300_FPI2_OUTA_RCP (10 << 23) -# define R300_FPI2_OUTA_RSQ (11 << 23) -# define R300_FPI2_OUTA_SAT (1 << 30) -# define R300_FPI2_UNKNOWN_31 (1 << 31) -/* END: Fragment program instruction set */ - -/* Fog state and color */ -#define R300_RE_FOG_STATE 0x4BC0 -# define R300_FOG_ENABLE (1 << 0) -# define R300_FOG_MODE_LINEAR (0 << 1) -# define R300_FOG_MODE_EXP (1 << 1) -# define R300_FOG_MODE_EXP2 (2 << 1) -# define R300_FOG_MODE_MASK (3 << 1) -#define R300_FOG_COLOR_R 0x4BC8 -#define R300_FOG_COLOR_G 0x4BCC -#define R300_FOG_COLOR_B 0x4BD0 - -#define R300_PP_ALPHA_TEST 0x4BD4 -# define R300_REF_ALPHA_MASK 0x000000ff -# define R300_ALPHA_TEST_FAIL (0 << 8) -# define R300_ALPHA_TEST_LESS (1 << 8) -# define R300_ALPHA_TEST_LEQUAL (3 << 8) -# define R300_ALPHA_TEST_EQUAL (2 << 8) -# define R300_ALPHA_TEST_GEQUAL (6 << 8) -# define R300_ALPHA_TEST_GREATER (4 << 8) -# define R300_ALPHA_TEST_NEQUAL (5 << 8) -# define R300_ALPHA_TEST_PASS (7 << 8) -# define R300_ALPHA_TEST_OP_MASK (7 << 8) -# define R300_ALPHA_TEST_ENABLE (1 << 11) - -/* gap */ - -/* Fragment program parameters in 7.16 floating point */ -#define R300_PFS_PARAM_0_X 0x4C00 -#define R300_PFS_PARAM_0_Y 0x4C04 -#define R300_PFS_PARAM_0_Z 0x4C08 -#define R300_PFS_PARAM_0_W 0x4C0C -/* GUESS: PARAM_31 is last, based on native limits reported by fglrx */ -#define R300_PFS_PARAM_31_X 0x4DF0 -#define R300_PFS_PARAM_31_Y 0x4DF4 -#define R300_PFS_PARAM_31_Z 0x4DF8 -#define R300_PFS_PARAM_31_W 0x4DFC - -/* Notes: - * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in - * the application - * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND - * are set to the same - * function (both registers are always set up completely in any case) - * - Most blend flags are simply copied from R200 and not tested yet - */ -#define R300_RB3D_CBLEND 0x4E04 -#define R300_RB3D_ABLEND 0x4E08 -/* the following only appear in CBLEND */ -# define R300_BLEND_ENABLE (1 << 0) -# define R300_BLEND_UNKNOWN (3 << 1) -# define R300_BLEND_NO_SEPARATE (1 << 3) -/* the following are shared between CBLEND and ABLEND */ -# define R300_FCN_MASK (3 << 12) -# define R300_COMB_FCN_ADD_CLAMP (0 << 12) -# define R300_COMB_FCN_ADD_NOCLAMP (1 << 12) -# define R300_COMB_FCN_SUB_CLAMP (2 << 12) -# define R300_COMB_FCN_SUB_NOCLAMP (3 << 12) -# define R300_COMB_FCN_MIN (4 << 12) -# define R300_COMB_FCN_MAX (5 << 12) -# define R300_COMB_FCN_RSUB_CLAMP (6 << 12) -# define R300_COMB_FCN_RSUB_NOCLAMP (7 << 12) -# define R300_BLEND_GL_ZERO (32) -# define R300_BLEND_GL_ONE (33) -# define R300_BLEND_GL_SRC_COLOR (34) -# define R300_BLEND_GL_ONE_MINUS_SRC_COLOR (35) -# define R300_BLEND_GL_DST_COLOR (36) -# define R300_BLEND_GL_ONE_MINUS_DST_COLOR (37) -# define R300_BLEND_GL_SRC_ALPHA (38) -# define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA (39) -# define R300_BLEND_GL_DST_ALPHA (40) -# define R300_BLEND_GL_ONE_MINUS_DST_ALPHA (41) -# define R300_BLEND_GL_SRC_ALPHA_SATURATE (42) -# define R300_BLEND_GL_CONST_COLOR (43) -# define R300_BLEND_GL_ONE_MINUS_CONST_COLOR (44) -# define R300_BLEND_GL_CONST_ALPHA (45) -# define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA (46) -# define R300_BLEND_MASK (63) -# define R300_SRC_BLEND_SHIFT (16) -# define R300_DST_BLEND_SHIFT (24) -#define R300_RB3D_BLEND_COLOR 0x4E10 -#define R300_RB3D_COLORMASK 0x4E0C -# define R300_COLORMASK0_B (1<<0) -# define R300_COLORMASK0_G (1<<1) -# define R300_COLORMASK0_R (1<<2) -# define R300_COLORMASK0_A (1<<3) - -/* gap */ - -#define R300_RB3D_COLOROFFSET0 0x4E28 -# define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */ -#define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */ -#define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */ -#define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */ - -/* gap */ - -/* Bit 16: Larger tiles - * Bit 17: 4x2 tiles - * Bit 18: Extremely weird tile like, but some pixels duplicated? - */ -#define R300_RB3D_COLORPITCH0 0x4E38 -# define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */ -# define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */ -# define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */ -# define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ -# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ -# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ -# define R300_COLOR_FORMAT_RGB565 (2 << 22) -# define R300_COLOR_FORMAT_ARGB8888 (3 << 22) -#define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */ -#define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ -#define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ - -#define R300_RB3D_AARESOLVE_CTL 0x4E88 -/* gap */ - -/* Guess by Vladimir. - * Set to 0A before 3D operations, set to 02 afterwards. - */ -/*#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C*/ -# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002 -# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A - -/* gap */ -/* There seems to be no "write only" setting, so use Z-test = ALWAYS - * for this. - * Bit (1<<8) is the "test" bit. so plain write is 6 - vd - */ -#define R300_ZB_CNTL 0x4F00 -# define R300_STENCIL_ENABLE (1 << 0) -# define R300_Z_ENABLE (1 << 1) -# define R300_Z_WRITE_ENABLE (1 << 2) -# define R300_Z_SIGNED_COMPARE (1 << 3) -# define R300_STENCIL_FRONT_BACK (1 << 4) - -#define R300_ZB_ZSTENCILCNTL 0x4f04 - /* functions */ -# define R300_ZS_NEVER 0 -# define R300_ZS_LESS 1 -# define R300_ZS_LEQUAL 2 -# define R300_ZS_EQUAL 3 -# define R300_ZS_GEQUAL 4 -# define R300_ZS_GREATER 5 -# define R300_ZS_NOTEQUAL 6 -# define R300_ZS_ALWAYS 7 -# define R300_ZS_MASK 7 - /* operations */ -# define R300_ZS_KEEP 0 -# define R300_ZS_ZERO 1 -# define R300_ZS_REPLACE 2 -# define R300_ZS_INCR 3 -# define R300_ZS_DECR 4 -# define R300_ZS_INVERT 5 -# define R300_ZS_INCR_WRAP 6 -# define R300_ZS_DECR_WRAP 7 -# define R300_Z_FUNC_SHIFT 0 - /* front and back refer to operations done for front - and back faces, i.e. separate stencil function support */ -# define R300_S_FRONT_FUNC_SHIFT 3 -# define R300_S_FRONT_SFAIL_OP_SHIFT 6 -# define R300_S_FRONT_ZPASS_OP_SHIFT 9 -# define R300_S_FRONT_ZFAIL_OP_SHIFT 12 -# define R300_S_BACK_FUNC_SHIFT 15 -# define R300_S_BACK_SFAIL_OP_SHIFT 18 -# define R300_S_BACK_ZPASS_OP_SHIFT 21 -# define R300_S_BACK_ZFAIL_OP_SHIFT 24 - -#define R300_ZB_STENCILREFMASK 0x4f08 -# define R300_STENCILREF_SHIFT 0 -# define R300_STENCILREF_MASK 0x000000ff -# define R300_STENCILMASK_SHIFT 8 -# define R300_STENCILMASK_MASK 0x0000ff00 -# define R300_STENCILWRITEMASK_SHIFT 16 -# define R300_STENCILWRITEMASK_MASK 0x00ff0000 - -/* gap */ - -#define R300_ZB_FORMAT 0x4f10 -# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0) -# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0) -# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0) -/* reserved up to (15 << 0) */ -# define R300_INVERT_13E3_LEADING_ONES (0 << 4) -# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4) - -#define R300_ZB_ZTOP 0x4F14 -# define R300_ZTOP_DISABLE (0 << 0) -# define R300_ZTOP_ENABLE (1 << 0) - -/* gap */ - -#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 -# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0) -# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0) -# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1) -# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1) -# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31) -# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31) - -#define R300_ZB_BW_CNTL 0x4f1c -# define R300_HIZ_DISABLE (0 << 0) -# define R300_HIZ_ENABLE (1 << 0) -# define R300_HIZ_MIN (0 << 1) -# define R300_HIZ_MAX (1 << 1) -# define R300_FAST_FILL_DISABLE (0 << 2) -# define R300_FAST_FILL_ENABLE (1 << 2) -# define R300_RD_COMP_DISABLE (0 << 3) -# define R300_RD_COMP_ENABLE (1 << 3) -# define R300_WR_COMP_DISABLE (0 << 4) -# define R300_WR_COMP_ENABLE (1 << 4) -# define R300_ZB_CB_CLEAR_RMW (0 << 5) -# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5) -# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6) -# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6) - -# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7) -# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7) -# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8) -# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8) - -# define R500_BMASK_ENABLE (0 << 10) -# define R500_BMASK_DISABLE (1 << 10) -# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11) -# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11) -# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12) -# define R500_HIZ_FP_EXP_BITS_1 (1 << 12) -# define R500_HIZ_FP_EXP_BITS_2 (2 << 12) -# define R500_HIZ_FP_EXP_BITS_3 (3 << 12) -# define R500_HIZ_FP_EXP_BITS_4 (4 << 12) -# define R500_HIZ_FP_EXP_BITS_5 (5 << 12) -# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15) -# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15) -# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16) -# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16) -# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17) -# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17) -# define R500_PEQ_PACKING_DISABLE (0 << 18) -# define R500_PEQ_PACKING_ENABLE (1 << 18) -# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18) -# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18) - - -/* gap */ - -/* Z Buffer Address Offset. - * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles. - */ -#define R300_ZB_DEPTHOFFSET 0x4f20 - -/* Z Buffer Pitch and Endian Control */ -#define R300_ZB_DEPTHPITCH 0x4f24 -# define R300_DEPTHPITCH_MASK 0x00003FFC -# define R300_DEPTHMACROTILE_DISABLE (0 << 16) -# define R300_DEPTHMACROTILE_ENABLE (1 << 16) -# define R300_DEPTHMICROTILE_LINEAR (0 << 17) -# define R300_DEPTHMICROTILE_TILED (1 << 17) -# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17) -# define R300_DEPTHENDIAN_NO_SWAP (0 << 18) -# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18) -# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18) -# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18) - -/* Z Buffer Clear Value */ -#define R300_ZB_DEPTHCLEARVALUE 0x4f28 - -#define R300_ZB_ZMASK_OFFSET 0x4f30 -#define R300_ZB_ZMASK_PITCH 0x4f34 -#define R300_ZB_ZMASK_WRINDEX 0x4f38 -#define R300_ZB_ZMASK_DWORD 0x4f3c -#define R300_ZB_ZMASK_RDINDEX 0x4f40 - -/* Hierarchical Z Memory Offset */ -#define R300_ZB_HIZ_OFFSET 0x4f44 - -/* Hierarchical Z Write Index */ -#define R300_ZB_HIZ_WRINDEX 0x4f48 - -/* Hierarchical Z Data */ -#define R300_ZB_HIZ_DWORD 0x4f4c - -/* Hierarchical Z Read Index */ -#define R300_ZB_HIZ_RDINDEX 0x4f50 - -/* Hierarchical Z Pitch */ -#define R300_ZB_HIZ_PITCH 0x4f54 - -/* Z Buffer Z Pass Counter Data */ -#define R300_ZB_ZPASS_DATA 0x4f58 - -/* Z Buffer Z Pass Counter Address */ -#define R300_ZB_ZPASS_ADDR 0x4f5c - -/* Depth buffer X and Y coordinate offset */ -#define R300_ZB_DEPTHXY_OFFSET 0x4f60 -# define R300_DEPTHX_OFFSET_SHIFT 1 -# define R300_DEPTHX_OFFSET_MASK 0x000007FE -# define R300_DEPTHY_OFFSET_SHIFT 17 -# define R300_DEPTHY_OFFSET_MASK 0x07FE0000 - -/* Sets the fifo sizes */ -#define R500_ZB_FIFO_SIZE 0x4fd0 -# define R500_OP_FIFO_SIZE_FULL (0 << 0) -# define R500_OP_FIFO_SIZE_HALF (1 << 0) -# define R500_OP_FIFO_SIZE_QUATER (2 << 0) -# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0) - -/* Stencil Reference Value and Mask for backfacing quads */ -/* R300_ZB_STENCILREFMASK handles front face */ -#define R500_ZB_STENCILREFMASK_BF 0x4fd4 -# define R500_STENCILREF_SHIFT 0 -# define R500_STENCILREF_MASK 0x000000ff -# define R500_STENCILMASK_SHIFT 8 -# define R500_STENCILMASK_MASK 0x0000ff00 -# define R500_STENCILWRITEMASK_SHIFT 16 -# define R500_STENCILWRITEMASK_MASK 0x00ff0000 - -/* BEGIN: Vertex program instruction set */ - -/* Every instruction is four dwords long: - * DWORD 0: output and opcode - * DWORD 1: first argument - * DWORD 2: second argument - * DWORD 3: third argument - * - * Notes: - * - ABS r, a is implemented as MAX r, a, -a - * - MOV is implemented as ADD to zero - * - XPD is implemented as MUL + MAD - * - FLR is implemented as FRC + ADD - * - apparently, fglrx tries to schedule instructions so that there is at - * least one instruction between the write to a temporary and the first - * read from said temporary; however, violations of this scheduling are - * allowed - * - register indices seem to be unrelated with OpenGL aliasing to - * conventional state - * - only one attribute and one parameter can be loaded at a time; however, - * the same attribute/parameter can be used for more than one argument - * - the second software argument for POW is the third hardware argument - * (no idea why) - * - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2 - * - * There is some magic surrounding LIT: - * The single argument is replicated across all three inputs, but swizzled: - * First argument: xyzy - * Second argument: xyzx - * Third argument: xyzw - * Whenever the result is used later in the fragment program, fglrx forces - * x and w to be 1.0 in the input selection; I don't know whether this is - * strictly necessary - */ -#define R300_VPI_OUT_OP_DOT (1 << 0) -#define R300_VPI_OUT_OP_MUL (2 << 0) -#define R300_VPI_OUT_OP_ADD (3 << 0) -#define R300_VPI_OUT_OP_MAD (4 << 0) -#define R300_VPI_OUT_OP_DST (5 << 0) -#define R300_VPI_OUT_OP_FRC (6 << 0) -#define R300_VPI_OUT_OP_MAX (7 << 0) -#define R300_VPI_OUT_OP_MIN (8 << 0) -#define R300_VPI_OUT_OP_SGE (9 << 0) -#define R300_VPI_OUT_OP_SLT (10 << 0) - /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */ -#define R300_VPI_OUT_OP_UNK12 (12 << 0) -#define R300_VPI_OUT_OP_ARL (13 << 0) -#define R300_VPI_OUT_OP_EXP (65 << 0) -#define R300_VPI_OUT_OP_LOG (66 << 0) - /* Used in fog computations, scalar(scalar) */ -#define R300_VPI_OUT_OP_UNK67 (67 << 0) -#define R300_VPI_OUT_OP_LIT (68 << 0) -#define R300_VPI_OUT_OP_POW (69 << 0) -#define R300_VPI_OUT_OP_RCP (70 << 0) -#define R300_VPI_OUT_OP_RSQ (72 << 0) - /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */ -#define R300_VPI_OUT_OP_UNK73 (73 << 0) -#define R300_VPI_OUT_OP_EX2 (75 << 0) -#define R300_VPI_OUT_OP_LG2 (76 << 0) -#define R300_VPI_OUT_OP_MAD_2 (128 << 0) - /* all temps, vector(scalar, vector, vector) */ -#define R300_VPI_OUT_OP_UNK129 (129 << 0) - -#define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8) -#define R300_VPI_OUT_REG_CLASS_ADDR (1 << 8) -#define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8) -#define R300_VPI_OUT_REG_CLASS_MASK (31 << 8) - -#define R300_VPI_OUT_REG_INDEX_SHIFT 13 - /* GUESS based on fglrx native limits */ -#define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) - -#define R300_VPI_OUT_WRITE_X (1 << 20) -#define R300_VPI_OUT_WRITE_Y (1 << 21) -#define R300_VPI_OUT_WRITE_Z (1 << 22) -#define R300_VPI_OUT_WRITE_W (1 << 23) - -#define R300_VPI_IN_REG_CLASS_TEMPORARY (0 << 0) -#define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0) -#define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0) -#define R300_VPI_IN_REG_CLASS_NONE (9 << 0) -#define R300_VPI_IN_REG_CLASS_MASK (31 << 0) - -#define R300_VPI_IN_REG_INDEX_SHIFT 5 - /* GUESS based on fglrx native limits */ -#define R300_VPI_IN_REG_INDEX_MASK (255 << 5) - -/* The R300 can select components from the input register arbitrarily. - * Use the following constants, shifted by the component shift you - * want to select - */ -#define R300_VPI_IN_SELECT_X 0 -#define R300_VPI_IN_SELECT_Y 1 -#define R300_VPI_IN_SELECT_Z 2 -#define R300_VPI_IN_SELECT_W 3 -#define R300_VPI_IN_SELECT_ZERO 4 -#define R300_VPI_IN_SELECT_ONE 5 -#define R300_VPI_IN_SELECT_MASK 7 - -#define R300_VPI_IN_X_SHIFT 13 -#define R300_VPI_IN_Y_SHIFT 16 -#define R300_VPI_IN_Z_SHIFT 19 -#define R300_VPI_IN_W_SHIFT 22 - -#define R300_VPI_IN_NEG_X (1 << 25) -#define R300_VPI_IN_NEG_Y (1 << 26) -#define R300_VPI_IN_NEG_Z (1 << 27) -#define R300_VPI_IN_NEG_W (1 << 28) -/* END: Vertex program instruction set */ - -/* BEGIN: Packet 3 commands */ - -/* A primitive emission dword. */ -#define R300_PRIM_TYPE_NONE (0 << 0) -#define R300_PRIM_TYPE_POINT (1 << 0) -#define R300_PRIM_TYPE_LINE (2 << 0) -#define R300_PRIM_TYPE_LINE_STRIP (3 << 0) -#define R300_PRIM_TYPE_TRI_LIST (4 << 0) -#define R300_PRIM_TYPE_TRI_FAN (5 << 0) -#define R300_PRIM_TYPE_TRI_STRIP (6 << 0) -#define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0) -#define R300_PRIM_TYPE_RECT_LIST (8 << 0) -#define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) -#define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) - /* GUESS (based on r200) */ -#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) -#define R300_PRIM_TYPE_LINE_LOOP (12 << 0) -#define R300_PRIM_TYPE_QUADS (13 << 0) -#define R300_PRIM_TYPE_QUAD_STRIP (14 << 0) -#define R300_PRIM_TYPE_POLYGON (15 << 0) -#define R300_PRIM_TYPE_MASK 0xF -#define R300_PRIM_WALK_IND (1 << 4) -#define R300_PRIM_WALK_LIST (2 << 4) -#define R300_PRIM_WALK_RING (3 << 4) -#define R300_PRIM_WALK_MASK (3 << 4) - /* GUESS (based on r200) */ -#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) -#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) -#define R300_PRIM_NUM_VERTICES_SHIFT 16 -#define R300_PRIM_NUM_VERTICES_MASK 0xffff - -/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR. - * Two parameter dwords: - * 0. The first parameter appears to be always 0 - * 1. The second parameter is a standard primitive emission dword. - */ -#define R300_PACKET3_3D_DRAW_VBUF 0x00002800 - -/* Specify the full set of vertex arrays as (address, stride). - * The first parameter is the number of vertex arrays specified. - * The rest of the command is a variable length list of blocks, where - * each block is three dwords long and specifies two arrays. - * The first dword of a block is split into two words, the lower significant - * word refers to the first array, the more significant word to the second - * array in the block. - * The low byte of each word contains the size of an array entry in dwords, - * the high byte contains the stride of the array. - * The second dword of a block contains the pointer to the first array, - * the third dword of a block contains the pointer to the second array. - * Note that if the total number of arrays is odd, the third dword of - * the last block is omitted. - */ -#define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00 - -#define R300_PACKET3_INDX_BUFFER 0x00003300 -# define R300_EB_UNK1_SHIFT 24 -# define R300_EB_UNK1 (0x80<<24) -# define R300_EB_UNK2 0x0810 -#define R300_PACKET3_3D_DRAW_VBUF_2 0x00003400 -#define R300_PACKET3_3D_DRAW_INDX_2 0x00003600 - -/* END: Packet 3 commands */ - - -/* Color formats for 2d packets - */ -#define R300_CP_COLOR_FORMAT_CI8 2 -#define R300_CP_COLOR_FORMAT_ARGB1555 3 -#define R300_CP_COLOR_FORMAT_RGB565 4 -#define R300_CP_COLOR_FORMAT_ARGB8888 6 -#define R300_CP_COLOR_FORMAT_RGB332 7 -#define R300_CP_COLOR_FORMAT_RGB8 9 -#define R300_CP_COLOR_FORMAT_ARGB4444 15 - -/* - * CP type-3 packets - */ -#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00 - -#define R500_VAP_INDEX_OFFSET 0x208c - -#define R500_GA_US_VECTOR_INDEX 0x4250 -#define R500_GA_US_VECTOR_DATA 0x4254 - -#define R500_RS_IP_0 0x4074 -#define R500_RS_INST_0 0x4320 - -#define R500_US_CONFIG 0x4600 - -#define R500_US_FC_CTRL 0x4624 -#define R500_US_CODE_ADDR 0x4630 - -#define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c0 -#define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8 - -#endif /* _R300_REG_H */ - -/* *INDENT-ON* */ diff --git a/shared-core/r600_microcode.h b/shared-core/r600_microcode.h deleted file mode 100644 index 58a3f838..00000000 --- a/shared-core/r600_microcode.h +++ /dev/null @@ -1,14275 +0,0 @@ -/* - * Copyright 2007 Advanced Micro Devices, Inc. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/* this file is not used we just have it as a placeholder for future R600 - work */ -#if 0 -static const int ME_JUMP_TABLE_START = 1764; -static const int ME_JUMP_TABLE_END = 1792; - -static const u32 R600_cp_microcode[][3]={ - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x614 }, - { 0x00000000, 0x00600000, 0x5b2 }, - { 0x00000000, 0x00600000, 0x5c5 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000020, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000021, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x0000001d, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x0000001d, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000030, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x00000010, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000030, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000032, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x0000002d, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x080 }, - { 0x0000002e, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x081 }, - { 0x00000000, 0x00400000, 0x087 }, - { 0x0000002d, 0x00203623, 0x000 }, - { 0x0000002e, 0x00203624, 0x000 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x087 }, - { 0x00000000, 0x00600000, 0x5ed }, - { 0x00000000, 0x00600000, 0x5e1 }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08a }, - { 0x00000018, 0xc0403620, 0x090 }, - { 0x00000000, 0x2ee00000, 0x08e }, - { 0x00000000, 0x2ce00000, 0x08d }, - { 0x00000002, 0x00400e2d, 0x08f }, - { 0x00000003, 0x00400e2d, 0x08f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000018, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x095 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x09d }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09b }, - { 0x00000000, 0x2ce00000, 0x09a }, - { 0x00000002, 0x00400e2d, 0x09c }, - { 0x00000003, 0x00400e2d, 0x09c }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a4 }, - { 0x0000001c, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x0000001b, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0db }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x28c }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x128 }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0c5 }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0d6 }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0d4 }, - { 0x00000013, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0cf }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0ce }, - { 0x00003f00, 0x00400c11, 0x0d0 }, - { 0x00001f00, 0x00400c11, 0x0d0 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0d6 }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00284a22, 0x000 }, - { 0x00000030, 0x00200e2d, 0x000 }, - { 0x0000002e, 0x0020122d, 0x000 }, - { 0x00000000, 0x002f0083, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e3 }, - { 0x00000000, 0x00600000, 0x5e7 }, - { 0x00000000, 0x00400000, 0x0e4 }, - { 0x00000000, 0x00600000, 0x5ea }, - { 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0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x57d }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x614 }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x57b }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x58d }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x614 }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x58b }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x614 }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x599 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x59f }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5a4 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x5b7 }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x00000034, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x5bb }, - { 0x00000000, 0x00600000, 0x5a4 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x5bb }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x0000217a, 0xc0204411, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x5e1 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000016, 0x00604811, 0x35e }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x614 }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x5dc }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x0000001d, 0x00803627, 0x000 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x0000001d, 0x00803627, 0x000 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x0000001d, 0x00803627, 0x000 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x0000001d, 0x00803627, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000016, 0x00604811, 0x35e }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0x00ffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x614 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x613 }, - { 0x00000010, 0x00404c11, 0x5f9 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x00000025, 0x00200a2d, 0x000 }, - { 0x00000026, 0x00200e2d, 0x000 }, - { 0x00000027, 0x0020122d, 0x000 }, - { 0x00000028, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x612 }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x00000027, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x614 }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x617 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x2fe }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x19f }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000029, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x0000002c, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000002a, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000002b, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x013304ef, 0x059b0239, 0x000 }, - { 0x01b00159, 0x0425059b, 0x000 }, - { 0x021201f6, 0x02390142, 0x000 }, - { 0x0210022e, 0x0289022a, 0x000 }, - { 0x03c2059b, 0x059b059b, 0x000 }, - { 0x05cd05ce, 0x0308059b, 0x000 }, - { 0x059b05a0, 0x03090329, 0x000 }, - { 0x0313026b, 0x032b031d, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b052c, 0x059b059b, 0x000 }, - { 0x03a5059b, 0x04a2032d, 0x000 }, - { 0x04810433, 0x0423059b, 0x000 }, - { 0x04bb04ed, 0x042704c8, 0x000 }, - { 0x043304f4, 0x033a0365, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b059b, 0x05b905a2, 0x000 }, - { 0x059b059b, 0x0007059b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x03e303d8, 0x03f303f1, 0x000 }, - { 0x03f903f5, 0x03f703fb, 0x000 }, - { 0x04070403, 0x040f040b, 0x000 }, - { 0x04170413, 0x041f041b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x00020600, 0x06190006, 0x000 }, -}; - -static const u32 R600_pfp_microcode[]={ -0xd40071, -0xd40072, -0xca0400, -0xa00000, -0x7e828b, -0x800003, -0xca0400, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d4, -0xd5c01e, -0xca0800, -0x80001b, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000d, -0xc41838, -0xe4013e, -0xd4001e, -0x80000d, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800054, -0xd40073, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800002, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800002, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b9, -0xd4c01e, -0xc6083e, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800002, -0x062001, -0xc6083e, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x80007a, -0xd42013, -0xc6083e, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008e, -0x000000, -0xc41432, -0xc6183e, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800002, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xd40073, -0xe4015e, -0xd4001e, -0x8001b9, -0x062001, -0x0a2001, -0xd60074, -0xc40836, -0xc61040, -0x988007, -0xcc3835, -0x95010f, -0xd4001f, -0xd46062, -0x800002, -0xd42062, -0xcc1433, -0x8401bc, -0xd40070, -0xd5401e, -0x800002, -0xee001e, -0xca0c00, -0xca1000, -0xd4c01a, -0x8401bc, -0xd5001a, -0xcc0443, -0x35101f, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b9, -0xd4006d, -0x344401, -0xcc0c44, -0x98403a, -0xcc2c46, -0x958004, -0xcc0445, -0x8001b9, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f3, -0xcc1003, -0x98801b, -0x04380c, -0x8400f3, -0xcc1003, -0x988017, -0x043808, -0x8400f3, -0xcc1003, -0x988013, -0x043804, -0x8400f3, -0xcc1003, -0x988014, -0xcc1047, -0x9a8009, -0xcc1448, -0x9840da, -0xd4006d, -0xcc1844, -0xd5001a, -0xd5401a, -0x8000cc, -0xd5801a, -0x96c0d3, -0xd4006d, -0x8001b9, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800002, -0xec007f, -0x9ac0ca, -0xd4006d, -0x8001b9, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b9, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809c, -0xd4006d, -0x98409a, -0xd4006e, -0xcc0847, -0xcc0c48, -0xcc1044, -0xd4801a, -0xd4c01a, -0x800104, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d8, -0xca0c00, -0xd4401e, -0x800002, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800002, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bc, -0x000000, -0x8401bc, -0xd7806f, -0x800002, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902af, -0x7c738b, -0x8401bc, -0xd7806f, -0x800002, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984296, -0x000000, -0x800164, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800002, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc1049, -0x990004, -0xd40071, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800002, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x95001f, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x7d8380, -0xd5806f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0x8001b9, -0xd60074, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800002, -0xee001e, -0x800002, -0xee001f, -0xd4001f, -0x800002, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010174, -0x02017b, -0x030090, -0x040080, -0x050005, -0x060040, -0x070033, -0x08012f, -0x090047, -0x0a0037, -0x1001b7, -0x1700a4, -0x22013d, -0x23014c, -0x2000b5, -0x240128, -0x27004e, -0x28006b, -0x2a0061, -0x2b0053, -0x2f0066, -0x320088, -0x340182, -0x3c0159, -0x3f0073, -0x41018f, -0x440131, -0x550176, -0x56017d, -0x60000c, -0x610035, -0x620039, -0x630039, -0x640039, -0x650039, -0x660039, -0x670039, -0x68003b, -0x690042, -0x6a0049, -0x6b0049, -0x6c0049, -0x6d0049, -0x6e0049, -0x6f0049, -0x7301b7, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -}; - -static const u32 RV610_cp_microcode[][3]={ - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x668 }, - { 0x00000000, 0x00600000, 0x65c }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 0x00400c11, 0x0d6 }, - { 0x00001f00, 0x00400c11, 0x0d6 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0dc }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00280e22, 0x000 }, - { 0x00000080, 0x00294a23, 0x000 }, - { 0x00000027, 0x00200e2d, 0x000 }, - { 0x00000026, 0x0020122d, 0x000 }, - { 0x00000000, 0x002f0083, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0ea }, - { 0x00000000, 0x00600000, 0x662 }, - { 0x00000000, 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0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x57a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x692 }, - { 0x00000000, 0x00401c10, 0x57c }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x57e }, - { 0x00000000, 0x00600000, 0x5c9 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x58f }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x58d }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5a0 }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x59e }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5b1 }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5af }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5be }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5c4 }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5c9 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000002c, 0x00203621, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0230, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5d0 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000030, 0x00403621, 0x5e3 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5e3 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a092, 0x00604411, 0x68d }, - { 0x00000031, 0x00203630, 0x000 }, - { 0x0004a093, 0x00604411, 0x68d }, - { 0x00000032, 0x00203630, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68d }, - { 0x00000033, 0x00203630, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68d }, - { 0x00000034, 0x00203630, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68d }, - { 0x00000035, 0x00203630, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68d }, - { 0x00000036, 0x00203630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000001, 0x002f0230, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62c }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62c }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x605 }, - { 0x0000a092, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x0000a093, 0x00204411, 0x000 }, - { 0x00000032, 0x00204a2d, 0x000 }, - { 0x0000a2b6, 0x00204411, 0x000 }, - { 0x00000033, 0x00204a2d, 0x000 }, - { 0x0000a2ba, 0x00204411, 0x000 }, - { 0x00000034, 0x00204a2d, 0x000 }, - { 0x0000a2be, 0x00204411, 0x000 }, - { 0x00000035, 0x00204a2d, 0x000 }, - { 0x0000a2c2, 0x00204411, 0x000 }, - { 0x00000036, 0x00204a2d, 0x000 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x000001ff, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62b }, - { 0x00000000, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x60e }, - { 0x0004a003, 0x00604411, 0x68d }, - { 0x0000a003, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x14c00000, 0x613 }, - { 0x0004a010, 0x00604411, 0x68d }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62b }, - { 0x0004a011, 0x00604411, 0x68d }, - { 0x0000a011, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a012, 0x00604411, 0x68d }, - { 0x0000a012, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a013, 0x00604411, 0x68d }, - { 0x0000a013, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a014, 0x00604411, 0x68d }, - { 0x0000a014, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a015, 0x00604411, 0x68d }, - { 0x0000a015, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a016, 0x00604411, 0x68d }, - { 0x0000a016, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a017, 0x00604411, 0x68d }, - { 0x0000a017, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000002c, 0x0080062d, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x63d }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000002, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x63b }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x641 }, - { 0x00000000, 0x00600000, 0x5c9 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x641 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x62d }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x62d }, - { 0x00000000, 0x00600000, 0x65c }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x656 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x68c }, - { 0x00000010, 0x00404c11, 0x672 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x68b }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68d }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x690 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x692 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x695 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x01420502, 0x05c00250, 0x000 }, - { 0x01c30168, 0x043f05c0, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03d705c0, 0x05c005c0, 0x000 }, - { 0x0649064a, 0x031f05c0, 0x000 }, - { 0x05c005c5, 0x03200340, 0x000 }, - { 0x032a0282, 0x03420334, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c00551, 0x05c005c0, 0x000 }, - { 0x03ba05c0, 0x04bb0344, 0x000 }, - { 0x049a0450, 0x043d05c0, 0x000 }, - { 0x04d005c0, 0x044104dd, 0x000 }, - { 0x04500507, 0x03510375, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x063f05c7, 0x000 }, - { 0x05c005c0, 0x000705c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x03f803ed, 0x04080406, 0x000 }, - { 0x040e040a, 0x040c0410, 0x000 }, - { 0x041c0418, 0x04240420, 0x000 }, - { 0x042c0428, 0x04340430, 0x000 }, - { 0x05c005c0, 0x043805c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x00020679, 0x06970006, 0x000 }, -}; - -static const u32 RV610_pfp_microcode[]={ -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001b8, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800053, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b8, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x800079, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008d, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401bb, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401bb, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b8, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001b8, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f0, -0xcc1003, -0x98801b, -0x04380c, -0x8400f0, -0xcc1003, -0x988017, -0x043808, -0x8400f0, -0xcc1003, -0x988013, -0x043804, -0x8400f0, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000c9, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001b8, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001b8, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b8, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800101, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d9, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bd, -0x000000, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902b0, -0x7c738b, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984297, -0x000000, -0x800161, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001b8, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010171, -0x020178, -0x03008f, -0x04007f, -0x050003, -0x06003f, -0x070032, -0x08012c, -0x090046, -0x0a0036, -0x1001b6, -0x1700a2, -0x22013a, -0x230149, -0x2000b4, -0x240125, -0x27004d, -0x28006a, -0x2a0060, -0x2b0052, -0x2f0065, -0x320087, -0x34017f, -0x3c0156, -0x3f0072, -0x41018c, -0x44012e, -0x550173, -0x56017a, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; - -static const u32 RV620_cp_microcode[][3]={ - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x668 }, - { 0x00000000, 0x00600000, 0x65c }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 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0x00694622, 0x68d }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00020000, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56e }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x57c }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68d }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x57c }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x572 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x57c }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x57a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x692 }, - { 0x00000000, 0x00401c10, 0x57c }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x57e }, - { 0x00000000, 0x00600000, 0x5c9 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x58f }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x58d }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5a0 }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x59e }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5b1 }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5af }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5be }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5c4 }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5c9 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000002c, 0x00203621, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0230, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5d0 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000030, 0x00403621, 0x5e3 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5e3 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a092, 0x00604411, 0x68d }, - { 0x00000031, 0x00203630, 0x000 }, - { 0x0004a093, 0x00604411, 0x68d }, - { 0x00000032, 0x00203630, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68d }, - { 0x00000033, 0x00203630, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68d }, - { 0x00000034, 0x00203630, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68d }, - { 0x00000035, 0x00203630, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68d }, - { 0x00000036, 0x00203630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000001, 0x002f0230, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62c }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62c }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x605 }, - { 0x0000a092, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x0000a093, 0x00204411, 0x000 }, - { 0x00000032, 0x00204a2d, 0x000 }, - { 0x0000a2b6, 0x00204411, 0x000 }, - { 0x00000033, 0x00204a2d, 0x000 }, - { 0x0000a2ba, 0x00204411, 0x000 }, - { 0x00000034, 0x00204a2d, 0x000 }, - { 0x0000a2be, 0x00204411, 0x000 }, - { 0x00000035, 0x00204a2d, 0x000 }, - { 0x0000a2c2, 0x00204411, 0x000 }, - { 0x00000036, 0x00204a2d, 0x000 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x000001ff, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62b }, - { 0x00000000, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x60e }, - { 0x0004a003, 0x00604411, 0x68d }, - { 0x0000a003, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x14c00000, 0x613 }, - { 0x0004a010, 0x00604411, 0x68d }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62b }, - { 0x0004a011, 0x00604411, 0x68d }, - { 0x0000a011, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a012, 0x00604411, 0x68d }, - { 0x0000a012, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a013, 0x00604411, 0x68d }, - { 0x0000a013, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a014, 0x00604411, 0x68d }, - { 0x0000a014, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a015, 0x00604411, 0x68d }, - { 0x0000a015, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a016, 0x00604411, 0x68d }, - { 0x0000a016, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a017, 0x00604411, 0x68d }, - { 0x0000a017, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000002c, 0x0080062d, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x63d }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000002, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x63b }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x641 }, - { 0x00000000, 0x00600000, 0x5c9 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x641 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x62d }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x62d }, - { 0x00000000, 0x00600000, 0x65c }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x656 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x68c }, - { 0x00000010, 0x00404c11, 0x672 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x68b }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68d }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x690 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x692 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x695 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x01420502, 0x05c00250, 0x000 }, - { 0x01c30168, 0x043f05c0, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03d705c0, 0x05c005c0, 0x000 }, - { 0x0649064a, 0x031f05c0, 0x000 }, - { 0x05c005c5, 0x03200340, 0x000 }, - { 0x032a0282, 0x03420334, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c00551, 0x05c005c0, 0x000 }, - { 0x03ba05c0, 0x04bb0344, 0x000 }, - { 0x049a0450, 0x043d05c0, 0x000 }, - { 0x04d005c0, 0x044104dd, 0x000 }, - { 0x04500507, 0x03510375, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x063f05c7, 0x000 }, - { 0x05c005c0, 0x000705c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x03f803ed, 0x04080406, 0x000 }, - { 0x040e040a, 0x040c0410, 0x000 }, - { 0x041c0418, 0x04240420, 0x000 }, - { 0x042c0428, 0x04340430, 0x000 }, - { 0x05c005c0, 0x043805c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x00020679, 0x06970006, 0x000 }, -}; - -static const u32 RV620_pfp_microcode[]={ -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001b8, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800053, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b8, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x800079, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008d, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401bb, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401bb, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b8, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001b8, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f0, -0xcc1003, -0x98801b, -0x04380c, -0x8400f0, -0xcc1003, -0x988017, -0x043808, -0x8400f0, -0xcc1003, -0x988013, -0x043804, -0x8400f0, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000c9, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001b8, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001b8, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b8, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800101, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d9, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bd, -0x000000, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902b0, -0x7c738b, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984297, -0x000000, -0x800161, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001b8, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010171, -0x020178, -0x03008f, -0x04007f, -0x050003, -0x06003f, -0x070032, -0x08012c, -0x090046, -0x0a0036, -0x1001b6, -0x1700a2, -0x22013a, -0x230149, -0x2000b4, -0x240125, -0x27004d, -0x28006a, -0x2a0060, -0x2b0052, -0x2f0065, -0x320087, -0x34017f, -0x3c0156, -0x3f0072, -0x41018c, -0x44012e, -0x550173, -0x56017a, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; - -static const u32 RV630_cp_microcode[][3]={ - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x665 }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 0x00400c11, 0x0d6 }, - { 0x00001f00, 0x00400c11, 0x0d6 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 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0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56b }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68a }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56f }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x577 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x68f }, - { 0x00000000, 0x00401c10, 0x579 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x57b }, - { 0x00000000, 0x00600000, 0x5c6 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x58c }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x58a }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x59d }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x59b }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5ae }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5ac }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5bb }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5c1 }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5c6 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000002c, 0x00203621, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0230, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5cd }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000030, 0x00403621, 0x5e0 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5e0 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a092, 0x00604411, 0x68a }, - { 0x00000031, 0x00203630, 0x000 }, - { 0x0004a093, 0x00604411, 0x68a }, - { 0x00000032, 0x00203630, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68a }, - { 0x00000033, 0x00203630, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68a }, - { 0x00000034, 0x00203630, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68a }, - { 0x00000035, 0x00203630, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68a }, - { 0x00000036, 0x00203630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000001, 0x002f0230, 0x000 }, - { 0x00000000, 0x0ce00000, 0x629 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x629 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x602 }, - { 0x0000a092, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x0000a093, 0x00204411, 0x000 }, - { 0x00000032, 0x00204a2d, 0x000 }, - { 0x0000a2b6, 0x00204411, 0x000 }, - { 0x00000033, 0x00204a2d, 0x000 }, - { 0x0000a2ba, 0x00204411, 0x000 }, - { 0x00000034, 0x00204a2d, 0x000 }, - { 0x0000a2be, 0x00204411, 0x000 }, - { 0x00000035, 0x00204a2d, 0x000 }, - { 0x0000a2c2, 0x00204411, 0x000 }, - { 0x00000036, 0x00204a2d, 0x000 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x000001ff, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x628 }, - { 0x00000000, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x60b }, - { 0x0004a003, 0x00604411, 0x68a }, - { 0x0000a003, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x14c00000, 0x610 }, - { 0x0004a010, 0x00604411, 0x68a }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x628 }, - { 0x0004a011, 0x00604411, 0x68a }, - { 0x0000a011, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a012, 0x00604411, 0x68a }, - { 0x0000a012, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a013, 0x00604411, 0x68a }, - { 0x0000a013, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a014, 0x00604411, 0x68a }, - { 0x0000a014, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a015, 0x00604411, 0x68a }, - { 0x0000a015, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a016, 0x00604411, 0x68a }, - { 0x0000a016, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a017, 0x00604411, 0x68a }, - { 0x0000a017, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000002c, 0x0080062d, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x63a }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000002, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x638 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x63e }, - { 0x00000000, 0x00600000, 0x5c6 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x63e }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x62a }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x62a }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x653 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x689 }, - { 0x00000010, 0x00404c11, 0x66f }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x688 }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68a }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x68d }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68f }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x692 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x014204ff, 0x05bd0250, 0x000 }, - { 0x01c30168, 0x043f05bd, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03d705bd, 0x05bd05bd, 0x000 }, - { 0x06460647, 0x031f05bd, 0x000 }, - { 0x05bd05c2, 0x03200340, 0x000 }, - { 0x032a0282, 0x03420334, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd054e, 0x05bd05bd, 0x000 }, - { 0x03ba05bd, 0x04b80344, 0x000 }, - { 0x0497044d, 0x043d05bd, 0x000 }, - { 0x04cd05bd, 0x044104da, 0x000 }, - { 0x044d0504, 0x03510375, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x063c05c4, 0x000 }, - { 0x05bd05bd, 0x000705bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x03f803ed, 0x04080406, 0x000 }, - { 0x040e040a, 0x040c0410, 0x000 }, - { 0x041c0418, 0x04240420, 0x000 }, - { 0x042c0428, 0x04340430, 0x000 }, - { 0x05bd05bd, 0x043805bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x00020676, 0x06940006, 0x000 }, -}; - -static const u32 RV630_pfp_microcode[]={ -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001b8, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800053, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b8, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x800079, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008d, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401bb, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401bb, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b8, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001b8, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f0, -0xcc1003, -0x98801b, -0x04380c, -0x8400f0, -0xcc1003, -0x988017, -0x043808, -0x8400f0, -0xcc1003, -0x988013, -0x043804, -0x8400f0, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000c9, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001b8, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001b8, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b8, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800101, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d9, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bd, -0x000000, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902b0, -0x7c738b, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984297, -0x000000, -0x800161, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001b8, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010171, -0x020178, -0x03008f, -0x04007f, -0x050003, -0x06003f, -0x070032, -0x08012c, -0x090046, -0x0a0036, -0x1001b6, -0x1700a2, -0x22013a, -0x230149, -0x2000b4, -0x240125, -0x27004d, -0x28006a, -0x2a0060, -0x2b0052, -0x2f0065, -0x320087, -0x34017f, -0x3c0156, -0x3f0072, -0x41018c, -0x44012e, -0x550173, -0x56017a, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; - -static const u32 RV635_cp_microcode[][3]={ - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x665 }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 0x00400c11, 0x0d6 }, - { 0x00001f00, 0x00400c11, 0x0d6 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0dc }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 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0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68a }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56f }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x577 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x68f }, - { 0x00000000, 0x00401c10, 0x579 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x57b }, - { 0x00000000, 0x00600000, 0x5c6 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x58c }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x58a }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x59d }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x59b }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5ae }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5ac }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5bb }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5c1 }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5c6 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000002c, 0x00203621, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0230, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5cd }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000030, 0x00403621, 0x5e0 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5e0 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a092, 0x00604411, 0x68a }, - { 0x00000031, 0x00203630, 0x000 }, - { 0x0004a093, 0x00604411, 0x68a }, - { 0x00000032, 0x00203630, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68a }, - { 0x00000033, 0x00203630, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68a }, - { 0x00000034, 0x00203630, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68a }, - { 0x00000035, 0x00203630, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68a }, - { 0x00000036, 0x00203630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000001, 0x002f0230, 0x000 }, - { 0x00000000, 0x0ce00000, 0x629 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x629 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x602 }, - { 0x0000a092, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x0000a093, 0x00204411, 0x000 }, - { 0x00000032, 0x00204a2d, 0x000 }, - { 0x0000a2b6, 0x00204411, 0x000 }, - { 0x00000033, 0x00204a2d, 0x000 }, - { 0x0000a2ba, 0x00204411, 0x000 }, - { 0x00000034, 0x00204a2d, 0x000 }, - { 0x0000a2be, 0x00204411, 0x000 }, - { 0x00000035, 0x00204a2d, 0x000 }, - { 0x0000a2c2, 0x00204411, 0x000 }, - { 0x00000036, 0x00204a2d, 0x000 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x000001ff, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x628 }, - { 0x00000000, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x60b }, - { 0x0004a003, 0x00604411, 0x68a }, - { 0x0000a003, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x14c00000, 0x610 }, - { 0x0004a010, 0x00604411, 0x68a }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x628 }, - { 0x0004a011, 0x00604411, 0x68a }, - { 0x0000a011, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a012, 0x00604411, 0x68a }, - { 0x0000a012, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a013, 0x00604411, 0x68a }, - { 0x0000a013, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a014, 0x00604411, 0x68a }, - { 0x0000a014, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a015, 0x00604411, 0x68a }, - { 0x0000a015, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a016, 0x00604411, 0x68a }, - { 0x0000a016, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a017, 0x00604411, 0x68a }, - { 0x0000a017, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000002c, 0x0080062d, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x63a }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000002, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x638 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x63e }, - { 0x00000000, 0x00600000, 0x5c6 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x63e }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x62a }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x62a }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x653 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x689 }, - { 0x00000010, 0x00404c11, 0x66f }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x688 }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68a }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x68d }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68f }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x692 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x014204ff, 0x05bd0250, 0x000 }, - { 0x01c30168, 0x043f05bd, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03d705bd, 0x05bd05bd, 0x000 }, - { 0x06460647, 0x031f05bd, 0x000 }, - { 0x05bd05c2, 0x03200340, 0x000 }, - { 0x032a0282, 0x03420334, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd054e, 0x05bd05bd, 0x000 }, - { 0x03ba05bd, 0x04b80344, 0x000 }, - { 0x0497044d, 0x043d05bd, 0x000 }, - { 0x04cd05bd, 0x044104da, 0x000 }, - { 0x044d0504, 0x03510375, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x063c05c4, 0x000 }, - { 0x05bd05bd, 0x000705bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x03f803ed, 0x04080406, 0x000 }, - { 0x040e040a, 0x040c0410, 0x000 }, - { 0x041c0418, 0x04240420, 0x000 }, - { 0x042c0428, 0x04340430, 0x000 }, - { 0x05bd05bd, 0x043805bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x00020676, 0x06940006, 0x000 }, -}; - -static const u32 RV635_pfp_microcode[]={ -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001b8, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800053, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b8, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x800079, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008d, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401bb, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401bb, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b8, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001b8, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f0, -0xcc1003, -0x98801b, -0x04380c, -0x8400f0, -0xcc1003, -0x988017, -0x043808, -0x8400f0, -0xcc1003, -0x988013, -0x043804, -0x8400f0, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000c9, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001b8, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001b8, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b8, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800101, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d9, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bd, -0x000000, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902b0, -0x7c738b, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984297, -0x000000, -0x800161, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001b8, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010171, -0x020178, -0x03008f, -0x04007f, -0x050003, -0x06003f, -0x070032, -0x08012c, -0x090046, -0x0a0036, -0x1001b6, -0x1700a2, -0x22013a, -0x230149, -0x2000b4, -0x240125, -0x27004d, -0x28006a, -0x2a0060, -0x2b0052, -0x2f0065, -0x320087, -0x34017f, -0x3c0156, -0x3f0072, -0x41018c, -0x44012e, -0x550173, -0x56017a, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; - -static const u32 RV670_cp_microcode[][3]={ - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x00000000, 0x00600000, 0x624 }, - { 0x00000000, 0x00600000, 0x638 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00000000, 0x00600000, 0x64d }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 0x00400c11, 0x0d6 }, - { 0x00001f00, 0x00400c11, 0x0d6 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0dc }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00280e22, 0x000 }, - { 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0x00000000, 0x00401c10, 0x56f }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x571 }, - { 0x00000000, 0x00600000, 0x5bc }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x582 }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x67c }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x580 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x593 }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x67c }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x591 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5a4 }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x67c }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5a2 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x67c }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5b1 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5b7 }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5bc }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000002c, 0x00203621, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0230, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5c3 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000030, 0x00403621, 0x5d6 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5d6 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a092, 0x00604411, 0x67c }, - { 0x00000031, 0x00203630, 0x000 }, - { 0x0004a093, 0x00604411, 0x67c }, - { 0x00000032, 0x00203630, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x67c }, - { 0x00000033, 0x00203630, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x67c }, - { 0x00000034, 0x00203630, 0x000 }, - { 0x0004a2be, 0x00604411, 0x67c }, - { 0x00000035, 0x00203630, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x67c }, - { 0x00000036, 0x00203630, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000001, 0x002f0230, 0x000 }, - { 0x00000000, 0x0ce00000, 0x61f }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x61f }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5f8 }, - { 0x0000a092, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x0000a093, 0x00204411, 0x000 }, - { 0x00000032, 0x00204a2d, 0x000 }, - { 0x0000a2b6, 0x00204411, 0x000 }, - { 0x00000033, 0x00204a2d, 0x000 }, - { 0x0000a2ba, 0x00204411, 0x000 }, - { 0x00000034, 0x00204a2d, 0x000 }, - { 0x0000a2be, 0x00204411, 0x000 }, - { 0x00000035, 0x00204a2d, 0x000 }, - { 0x0000a2c2, 0x00204411, 0x000 }, - { 0x00000036, 0x00204a2d, 0x000 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x000001ff, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x61e }, - { 0x00000000, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x601 }, - { 0x0004a003, 0x00604411, 0x67c }, - { 0x0000a003, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x14c00000, 0x606 }, - { 0x0004a010, 0x00604411, 0x67c }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x61e }, - { 0x0004a011, 0x00604411, 0x67c }, - { 0x0000a011, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a012, 0x00604411, 0x67c }, - { 0x0000a012, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a013, 0x00604411, 0x67c }, - { 0x0000a013, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a014, 0x00604411, 0x67c }, - { 0x0000a014, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a015, 0x00604411, 0x67c }, - { 0x0000a015, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a016, 0x00604411, 0x67c }, - { 0x0000a016, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a017, 0x00604411, 0x67c }, - { 0x0000a017, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0000002c, 0x0080062d, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x630 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000002, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x634 }, - { 0x00000000, 0x00600000, 0x5bc }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x634 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x620 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x620 }, - { 0x00000000, 0x00600000, 0x64d }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36a }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x67c }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x647 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36a }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x67c }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x67b }, - { 0x00000010, 0x00404c11, 0x661 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x67a }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x67c }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x67f }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x681 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x684 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x014204f5, 0x05b30250, 0x000 }, - { 0x01c30168, 0x043505b3, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03cd05b3, 0x05b305b3, 0x000 }, - { 0x063c063d, 0x031f05b3, 0x000 }, - { 0x05b305b8, 0x03200340, 0x000 }, - { 0x032a0282, 0x03420334, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x05b30544, 0x05b305b3, 0x000 }, - { 0x03b205b3, 0x04ae0344, 0x000 }, - { 0x048d0443, 0x043305b3, 0x000 }, - { 0x04c305b3, 0x043704d0, 0x000 }, - { 0x044304fa, 0x03510371, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x05b305b3, 0x063205ba, 0x000 }, - { 0x05b305b3, 0x000705b3, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x03ee03e3, 0x03fe03fc, 0x000 }, - { 0x04040400, 0x04020406, 0x000 }, - { 0x0412040e, 0x041a0416, 0x000 }, - { 0x0422041e, 0x042a0426, 0x000 }, - { 0x05b305b3, 0x042e05b3, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x00020668, 0x06860006, 0x000 }, -}; - -static const u32 RV670_pfp_microcode[]={ -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001b8, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800053, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b8, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x800079, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008d, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401bb, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401bb, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b8, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001b8, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f0, -0xcc1003, -0x98801b, -0x04380c, -0x8400f0, -0xcc1003, -0x988017, -0x043808, -0x8400f0, -0xcc1003, -0x988013, -0x043804, -0x8400f0, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000c9, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001b8, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001b8, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b8, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800101, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d9, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bd, -0x000000, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902b0, -0x7c738b, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984297, -0x000000, -0x800161, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001b8, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010171, -0x020178, -0x03008f, -0x04007f, -0x050003, -0x06003f, -0x070032, -0x08012c, -0x090046, -0x0a0036, -0x1001b6, -0x1700a2, -0x22013a, -0x230149, -0x2000b4, -0x240125, -0x27004d, -0x28006a, -0x2a0060, -0x2b0052, -0x2f0065, -0x320087, -0x34017f, -0x3c0156, -0x3f0072, -0x41018c, -0x44012e, -0x550173, -0x56017a, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; -#endif diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c deleted file mode 100644 index 6771d4f5..00000000 --- a/shared-core/radeon_cp.c +++ /dev/null @@ -1,1793 +0,0 @@ -/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */ -/* - * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Fremont, California. - * Copyright 2007 Advanced Micro Devices, Inc. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Kevin E. Martin - * Gareth Hughes - */ - -#include "drmP.h" -#include "drm.h" -#include "radeon_drm.h" -#include "radeon_drv.h" -#include "r300_reg.h" - -#include "radeon_microcode.h" -#define RADEON_FIFO_DEBUG 0 - -static int radeon_do_cleanup_cp(struct drm_device * dev); -static void radeon_do_cp_start(drm_radeon_private_t * dev_priv); - -static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) -{ - u32 ret; - RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); - ret = RADEON_READ(R520_MC_IND_DATA); - RADEON_WRITE(R520_MC_IND_INDEX, 0); - return ret; -} - -static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) -{ - u32 ret; - RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff); - ret = RADEON_READ(RS480_NB_MC_DATA); - RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); - return ret; -} - -static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) -{ - u32 ret; - RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); - ret = RADEON_READ(RS690_MC_DATA); - RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK); - return ret; -} - -static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) -{ - if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) - return RS690_READ_MCIND(dev_priv, addr); - else - return RS480_READ_MCIND(dev_priv, addr); -} - -u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) -{ - - if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) - return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); - else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) - return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); - else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) - return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); - else - return RADEON_READ(RADEON_MC_FB_LOCATION); -} - -static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) -{ - if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) - R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); - else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) - RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); - else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) - R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); - else - RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); -} - -static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) -{ - if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) - R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); - else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) - RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); - else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) - R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); - else - RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); -} - -static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) -{ - u32 agp_base_hi = upper_32_bits(agp_base); - u32 agp_base_lo = agp_base & 0xffffffff; - - if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) { - R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo); - R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi); - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { - RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo); - RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi); - } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { - R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); - R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { - RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); - RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi); - } else { - RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); - if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) - RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi); - } -} - -static int RADEON_READ_PLL(struct drm_device * dev, int addr) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - - RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); - return RADEON_READ(RADEON_CLOCK_CNTL_DATA); -} - -static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) -{ - RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); - return RADEON_READ(RADEON_PCIE_DATA); -} - -#if RADEON_FIFO_DEBUG -static void radeon_status(drm_radeon_private_t * dev_priv) -{ - printk("%s:\n", __FUNCTION__); - printk("RBBM_STATUS = 0x%08x\n", - (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); - printk("CP_RB_RTPR = 0x%08x\n", - (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); - printk("CP_RB_WTPR = 0x%08x\n", - (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); - printk("AIC_CNTL = 0x%08x\n", - (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); - printk("AIC_STAT = 0x%08x\n", - (unsigned int)RADEON_READ(RADEON_AIC_STAT)); - printk("AIC_PT_BASE = 0x%08x\n", - (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); - printk("TLB_ADDR = 0x%08x\n", - (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); - printk("TLB_DATA = 0x%08x\n", - (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); -} -#endif - -/* ================================================================ - * Engine, FIFO control - */ - -static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) -{ - u32 tmp; - int i; - - dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - - if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { - tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); - tmp |= RADEON_RB3D_DC_FLUSH_ALL; - RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); - - for (i = 0; i < dev_priv->usec_timeout; i++) { - if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) - & RADEON_RB3D_DC_BUSY)) { - return 0; - } - DRM_UDELAY(1); - } - } else { - /* don't flush or purge cache here or lockup */ - return 0; - } - -#if RADEON_FIFO_DEBUG - DRM_ERROR("failed!\n"); - radeon_status(dev_priv); -#endif - return -EBUSY; -} - -static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) -{ - int i; - - dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - - for (i = 0; i < dev_priv->usec_timeout; i++) { - int slots = (RADEON_READ(RADEON_RBBM_STATUS) - & RADEON_RBBM_FIFOCNT_MASK); - if (slots >= entries) - return 0; - DRM_UDELAY(1); - } - DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n", - RADEON_READ(RADEON_RBBM_STATUS), - RADEON_READ(R300_VAP_CNTL_STATUS)); - -#if RADEON_FIFO_DEBUG - DRM_ERROR("failed!\n"); - radeon_status(dev_priv); -#endif - return -EBUSY; -} - -static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) -{ - int i, ret; - - dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - - ret = radeon_do_wait_for_fifo(dev_priv, 64); - if (ret) - return ret; - - for (i = 0; i < dev_priv->usec_timeout; i++) { - if (!(RADEON_READ(RADEON_RBBM_STATUS) - & RADEON_RBBM_ACTIVE)) { - radeon_do_pixcache_flush(dev_priv); - return 0; - } - DRM_UDELAY(1); - } - DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n", - RADEON_READ(RADEON_RBBM_STATUS), - RADEON_READ(R300_VAP_CNTL_STATUS)); - -#if RADEON_FIFO_DEBUG - DRM_ERROR("failed!\n"); - radeon_status(dev_priv); -#endif - return -EBUSY; -} - -static void radeon_init_pipes(drm_radeon_private_t * dev_priv) -{ - uint32_t gb_tile_config, gb_pipe_sel = 0; - - /* RS4xx/RS6xx/R4xx/R5xx */ - if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { - gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); - dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; - } else { - /* R3xx */ - if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) { - dev_priv->num_gb_pipes = 2; - } else { - /* R3Vxx */ - dev_priv->num_gb_pipes = 1; - } - } - DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes); - - gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/); - - switch(dev_priv->num_gb_pipes) { - case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; - case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; - case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; - default: - case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; - } - - if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { - RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); - RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); - } - RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config); - radeon_do_wait_for_idle(dev_priv); - RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); - RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) | - R300_DC_AUTOFLUSH_ENABLE | - R300_DC_DC_DISABLE_IGNORE_PE)); - - -} - -/* ================================================================ - * CP control, initialization - */ - -/* Load the microcode for the CP */ -static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) -{ - int i; - DRM_DEBUG("\n"); - - radeon_do_wait_for_idle(dev_priv); - - RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); - - if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) { - DRM_INFO("Loading R100 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - R100_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - R100_cp_microcode[i][0]); - } - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) { - DRM_INFO("Loading R200 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - R200_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - R200_cp_microcode[i][0]); - } - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { - DRM_INFO("Loading R300 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - R300_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - R300_cp_microcode[i][0]); - } - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { - DRM_INFO("Loading R400 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - R420_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - R420_cp_microcode[i][0]); - } - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { - DRM_INFO("Loading RS690/RS740 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - RS690_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - RS690_cp_microcode[i][0]); - } - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) { - DRM_INFO("Loading R500 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - R520_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - R520_cp_microcode[i][0]); - } - } -} - -/* Flush any pending commands to the CP. This should only be used just - * prior to a wait for idle, as it informs the engine that the command - * stream is ending. - */ -static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) -{ - DRM_DEBUG("\n"); -#if 0 - u32 tmp; - - tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); - RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); -#endif -} - -/* Wait for the CP to go idle. - */ -int radeon_do_cp_idle(drm_radeon_private_t * dev_priv) -{ - RING_LOCALS; - DRM_DEBUG("\n"); - - BEGIN_RING(6); - - RADEON_PURGE_CACHE(); - RADEON_PURGE_ZCACHE(); - RADEON_WAIT_UNTIL_IDLE(); - - ADVANCE_RING(); - COMMIT_RING(); - - return radeon_do_wait_for_idle(dev_priv); -} - -/* Start the Command Processor. - */ -static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) -{ - RING_LOCALS; - DRM_DEBUG("\n"); - - radeon_do_wait_for_idle(dev_priv); - - RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); - - dev_priv->cp_running = 1; - - BEGIN_RING(8); - /* isync can only be written through cp on r5xx write it here */ - OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); - OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | - RADEON_ISYNC_ANY3D_IDLE2D | - RADEON_ISYNC_WAIT_IDLEGUI | - RADEON_ISYNC_CPSCRATCH_IDLEGUI); - RADEON_PURGE_CACHE(); - RADEON_PURGE_ZCACHE(); - RADEON_WAIT_UNTIL_IDLE(); - ADVANCE_RING(); - COMMIT_RING(); - - dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED; -} - -/* Reset the Command Processor. This will not flush any pending - * commands, so you must wait for the CP command stream to complete - * before calling this routine. - */ -static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) -{ - u32 cur_read_ptr; - DRM_DEBUG("\n"); - - cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); - RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); - SET_RING_HEAD(dev_priv, cur_read_ptr); - dev_priv->ring.tail = cur_read_ptr; -} - -/* Stop the Command Processor. This will not flush any pending - * commands, so you must flush the command stream and wait for the CP - * to go idle before calling this routine. - */ -static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) -{ - DRM_DEBUG("\n"); - - RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); - - dev_priv->cp_running = 0; -} - -/* Reset the engine. This will stop the CP if it is running. - */ -static int radeon_do_engine_reset(struct drm_device * dev) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset; - DRM_DEBUG("\n"); - - radeon_do_pixcache_flush(dev_priv); - - if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { - /* may need something similar for newer chips */ - clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); - mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); - - RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | - RADEON_FORCEON_MCLKA | - RADEON_FORCEON_MCLKB | - RADEON_FORCEON_YCLKA | - RADEON_FORCEON_YCLKB | - RADEON_FORCEON_MC | - RADEON_FORCEON_AIC)); - } - - rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); - - RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | - RADEON_SOFT_RESET_CP | - RADEON_SOFT_RESET_HI | - RADEON_SOFT_RESET_SE | - RADEON_SOFT_RESET_RE | - RADEON_SOFT_RESET_PP | - RADEON_SOFT_RESET_E2 | - RADEON_SOFT_RESET_RB)); - RADEON_READ(RADEON_RBBM_SOFT_RESET); - RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & - ~(RADEON_SOFT_RESET_CP | - RADEON_SOFT_RESET_HI | - RADEON_SOFT_RESET_SE | - RADEON_SOFT_RESET_RE | - RADEON_SOFT_RESET_PP | - RADEON_SOFT_RESET_E2 | - RADEON_SOFT_RESET_RB))); - RADEON_READ(RADEON_RBBM_SOFT_RESET); - - if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { - RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); - RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); - RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); - } - - /* setup the raster pipes */ - if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300) - radeon_init_pipes(dev_priv); - - /* Reset the CP ring */ - radeon_do_cp_reset(dev_priv); - - /* The CP is no longer running after an engine reset */ - dev_priv->cp_running = 0; - - /* Reset any pending vertex, indirect buffers */ - radeon_freelist_reset(dev); - - return 0; -} - -static void radeon_cp_init_ring_buffer(struct drm_device * dev, - drm_radeon_private_t * dev_priv) -{ - u32 ring_start, cur_read_ptr; - u32 tmp; - - /* Initialize the memory controller. With new memory map, the fb location - * is not changed, it should have been properly initialized already. Part - * of the problem is that the code below is bogus, assuming the GART is - * always appended to the fb which is not necessarily the case - */ - if (!dev_priv->new_memmap) - radeon_write_fb_location(dev_priv, - ((dev_priv->gart_vm_start - 1) & 0xffff0000) - | (dev_priv->fb_location >> 16)); - -#if __OS_HAS_AGP - if (dev_priv->flags & RADEON_IS_AGP) { - radeon_write_agp_base(dev_priv, dev->agp->base); - - radeon_write_agp_location(dev_priv, - (((dev_priv->gart_vm_start - 1 + - dev_priv->gart_size) & 0xffff0000) | - (dev_priv->gart_vm_start >> 16))); - - ring_start = (dev_priv->cp_ring->offset - - dev->agp->base - + dev_priv->gart_vm_start); - } else -#endif - ring_start = (dev_priv->cp_ring->offset - - (unsigned long)dev->sg->virtual - + dev_priv->gart_vm_start); - - RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); - - /* Set the write pointer delay */ - RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); - - /* Initialize the ring buffer's read and write pointers */ - cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); - RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); - SET_RING_HEAD(dev_priv, cur_read_ptr); - dev_priv->ring.tail = cur_read_ptr; - -#if __OS_HAS_AGP - if (dev_priv->flags & RADEON_IS_AGP) { - RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, - dev_priv->ring_rptr->offset - - dev->agp->base + dev_priv->gart_vm_start); - } else -#endif - { - struct drm_sg_mem *entry = dev->sg; - unsigned long tmp_ofs, page_ofs; - - tmp_ofs = dev_priv->ring_rptr->offset - - (unsigned long)dev->sg->virtual; - page_ofs = tmp_ofs >> PAGE_SHIFT; - - RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]); - DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n", - (unsigned long)entry->busaddr[page_ofs], - entry->handle + tmp_ofs); - } - - /* Set ring buffer size */ -#ifdef __BIG_ENDIAN - RADEON_WRITE(RADEON_CP_RB_CNTL, - RADEON_BUF_SWAP_32BIT | - (dev_priv->ring.fetch_size_l2ow << 18) | - (dev_priv->ring.rptr_update_l2qw << 8) | - dev_priv->ring.size_l2qw); -#else - RADEON_WRITE(RADEON_CP_RB_CNTL, - (dev_priv->ring.fetch_size_l2ow << 18) | - (dev_priv->ring.rptr_update_l2qw << 8) | - dev_priv->ring.size_l2qw); -#endif - - /* Initialize the scratch register pointer. This will cause - * the scratch register values to be written out to memory - * whenever they are updated. - * - * We simply put this behind the ring read pointer, this works - * with PCI GART as well as (whatever kind of) AGP GART - */ - RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) - + RADEON_SCRATCH_REG_OFFSET); - - dev_priv->scratch = ((__volatile__ u32 *) - dev_priv->ring_rptr->handle + - (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); - - RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); - - /* Turn on bus mastering */ - if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { - /* rs600/rs690/rs740 */ - tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; - RADEON_WRITE(RADEON_BUS_CNTL, tmp); - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { - /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ - tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; - RADEON_WRITE(RADEON_BUS_CNTL, tmp); - } /* PCIE cards appears to not need this */ - - dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; - RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); - - dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; - RADEON_WRITE(RADEON_LAST_DISPATCH_REG, - dev_priv->sarea_priv->last_dispatch); - - dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; - RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear); - - radeon_do_wait_for_idle(dev_priv); - - /* Sync everything up */ - RADEON_WRITE(RADEON_ISYNC_CNTL, - (RADEON_ISYNC_ANY2D_IDLE3D | - RADEON_ISYNC_ANY3D_IDLE2D | - RADEON_ISYNC_WAIT_IDLEGUI | - RADEON_ISYNC_CPSCRATCH_IDLEGUI)); - -} - -static void radeon_test_writeback(drm_radeon_private_t * dev_priv) -{ - u32 tmp; - - /* Writeback doesn't seem to work everywhere, test it here and possibly - * enable it if it appears to work - */ - DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0); - RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); - - for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { - if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) == - 0xdeadbeef) - break; - DRM_UDELAY(1); - } - - if (tmp < dev_priv->usec_timeout) { - dev_priv->writeback_works = 1; - DRM_INFO("writeback test succeeded in %d usecs\n", tmp); - } else { - dev_priv->writeback_works = 0; - DRM_INFO("writeback test failed\n"); - } - if (radeon_no_wb == 1) { - dev_priv->writeback_works = 0; - DRM_INFO("writeback forced off\n"); - } - - if (!dev_priv->writeback_works) { - /* Disable writeback to avoid unnecessary bus master transfers */ - RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE); - RADEON_WRITE(RADEON_SCRATCH_UMSK, 0); - } -} - -/* Enable or disable IGP GART on the chip */ -static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) -{ - u32 temp; - - if (on) { - DRM_DEBUG("programming igp gart %08X %08lX %08X\n", - dev_priv->gart_vm_start, - (long)dev_priv->gart_info.bus_addr, - dev_priv->gart_size); - - temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); - - if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) - IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN | - RS690_BLOCK_GFX_D3_EN)); - else - IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); - - IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | - RS480_VA_SIZE_32MB)); - - temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID); - IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN | - RS480_TLB_ENABLE | - RS480_GTW_LAC_EN | - RS480_1LEVEL_GART)); - - temp = dev_priv->gart_info.bus_addr & 0xfffff000; - temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; - IGP_WRITE_MCIND(RS480_GART_BASE, temp); - - temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL); - IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) | - RS480_REQ_TYPE_SNOOP_DIS)); - - radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start); - - dev_priv->gart_size = 32*1024*1024; - temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & - 0xffff0000) | (dev_priv->gart_vm_start >> 16)); - - radeon_write_agp_location(dev_priv, temp); - - temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE); - IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | - RS480_VA_SIZE_32MB)); - - do { - temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); - if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) - break; - DRM_UDELAY(1); - } while(1); - - IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, - RS480_GART_CACHE_INVALIDATE); - - do { - temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); - if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) - break; - DRM_UDELAY(1); - } while(1); - - IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0); - } else { - IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0); - } -} - -static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) -{ - u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); - if (on) { - - DRM_DEBUG("programming pcie %08X %08lX %08X\n", - dev_priv->gart_vm_start, - (long)dev_priv->gart_info.bus_addr, - dev_priv->gart_size); - RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, - dev_priv->gart_vm_start); - RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, - dev_priv->gart_info.bus_addr); - RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, - dev_priv->gart_vm_start); - RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, - dev_priv->gart_vm_start + - dev_priv->gart_size - 1); - - radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ - - RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, - RADEON_PCIE_TX_GART_EN); - } else { - RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, - tmp & ~RADEON_PCIE_TX_GART_EN); - } -} - -/* Enable or disable PCI GART on the chip */ -static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) -{ - u32 tmp; - - if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) || - (dev_priv->flags & RADEON_IS_IGPGART)) { - radeon_set_igpgart(dev_priv, on); - return; - } - - if (dev_priv->flags & RADEON_IS_PCIE) { - radeon_set_pciegart(dev_priv, on); - return; - } - - tmp = RADEON_READ(RADEON_AIC_CNTL); - - if (on) { - RADEON_WRITE(RADEON_AIC_CNTL, - tmp | RADEON_PCIGART_TRANSLATE_EN); - - /* set PCI GART page-table base address - */ - RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); - - /* set address range for PCI address translate - */ - RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); - RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start - + dev_priv->gart_size - 1); - - /* Turn off AGP aperture -- is this required for PCI GART? - */ - radeon_write_agp_location(dev_priv, 0xffffffc0); - RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ - } else { - RADEON_WRITE(RADEON_AIC_CNTL, - tmp & ~RADEON_PCIGART_TRANSLATE_EN); - } -} - -static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - - DRM_DEBUG("\n"); - - /* if we require new memory map but we don't have it fail */ - if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { - DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); - radeon_do_cleanup_cp(dev); - return -EINVAL; - } - - if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) - { - DRM_DEBUG("Forcing AGP card to PCI mode\n"); - dev_priv->flags &= ~RADEON_IS_AGP; - } - else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) - && !init->is_pci) - { - DRM_DEBUG("Restoring AGP flag\n"); - dev_priv->flags |= RADEON_IS_AGP; - } - - if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) { - DRM_ERROR("PCI GART memory not allocated!\n"); - radeon_do_cleanup_cp(dev); - return -EINVAL; - } - - dev_priv->usec_timeout = init->usec_timeout; - if (dev_priv->usec_timeout < 1 || - dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { - DRM_DEBUG("TIMEOUT problem!\n"); - radeon_do_cleanup_cp(dev); - return -EINVAL; - } - - /* Enable vblank on CRTC1 for older X servers - */ - dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; - - dev_priv->do_boxes = 0; - dev_priv->cp_mode = init->cp_mode; - - /* We don't support anything other than bus-mastering ring mode, - * but the ring can be in either AGP or PCI space for the ring - * read pointer. - */ - if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && - (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { - DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); - radeon_do_cleanup_cp(dev); - return -EINVAL; - } - - switch (init->fb_bpp) { - case 16: - dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; - break; - case 32: - default: - dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; - break; - } - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; - - switch (init->depth_bpp) { - case 16: - dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; - break; - case 32: - default: - dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; - break; - } - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; - - /* Hardware state for depth clears. Remove this if/when we no - * longer clear the depth buffer with a 3D rectangle. Hard-code - * all values to prevent unwanted 3D state from slipping through - * and screwing with the clear operation. - */ - dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | - (dev_priv->color_fmt << 10) | - (dev_priv->chip_family < CHIP_R200 ? RADEON_ZBLOCK16 : 0)); - - dev_priv->depth_clear.rb3d_zstencilcntl = - (dev_priv->depth_fmt | - RADEON_Z_TEST_ALWAYS | - RADEON_STENCIL_TEST_ALWAYS | - RADEON_STENCIL_S_FAIL_REPLACE | - RADEON_STENCIL_ZPASS_REPLACE | - RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); - - dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | - RADEON_BFACE_SOLID | - RADEON_FFACE_SOLID | - RADEON_FLAT_SHADE_VTX_LAST | - RADEON_DIFFUSE_SHADE_FLAT | - RADEON_ALPHA_SHADE_FLAT | - RADEON_SPECULAR_SHADE_FLAT | - RADEON_FOG_SHADE_FLAT | - RADEON_VTX_PIX_CENTER_OGL | - RADEON_ROUND_MODE_TRUNC | - RADEON_ROUND_PREC_8TH_PIX); - - - dev_priv->ring_offset = init->ring_offset; - dev_priv->ring_rptr_offset = init->ring_rptr_offset; - dev_priv->buffers_offset = init->buffers_offset; - dev_priv->gart_textures_offset = init->gart_textures_offset; - - dev_priv->sarea = drm_getsarea(dev); - if (!dev_priv->sarea) { - DRM_ERROR("could not find sarea!\n"); - radeon_do_cleanup_cp(dev); - return -EINVAL; - } - - dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); - if (!dev_priv->cp_ring) { - DRM_ERROR("could not find cp ring region!\n"); - radeon_do_cleanup_cp(dev); - return -EINVAL; - } - dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); - if (!dev_priv->ring_rptr) { - DRM_ERROR("could not find ring read pointer!\n"); - radeon_do_cleanup_cp(dev); - return -EINVAL; - } - dev->agp_buffer_token = init->buffers_offset; - dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); - if (!dev->agp_buffer_map) { - DRM_ERROR("could not find dma buffer region!\n"); - radeon_do_cleanup_cp(dev); - return -EINVAL; - } - - if (init->gart_textures_offset) { - dev_priv->gart_textures = - drm_core_findmap(dev, init->gart_textures_offset); - if (!dev_priv->gart_textures) { - DRM_ERROR("could not find GART texture region!\n"); - radeon_do_cleanup_cp(dev); - return -EINVAL; - } - } - - dev_priv->sarea_priv = - (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle + - init->sarea_priv_offset); - -#if __OS_HAS_AGP - if (dev_priv->flags & RADEON_IS_AGP) { - drm_core_ioremap(dev_priv->cp_ring, dev); - drm_core_ioremap(dev_priv->ring_rptr, dev); - drm_core_ioremap(dev->agp_buffer_map, dev); - if (!dev_priv->cp_ring->handle || - !dev_priv->ring_rptr->handle || - !dev->agp_buffer_map->handle) { - DRM_ERROR("could not find ioremap agp regions!\n"); - radeon_do_cleanup_cp(dev); - return -EINVAL; - } - } else -#endif - { - dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; - dev_priv->ring_rptr->handle = - (void *)dev_priv->ring_rptr->offset; - dev->agp_buffer_map->handle = - (void *)dev->agp_buffer_map->offset; - - DRM_DEBUG("dev_priv->cp_ring->handle %p\n", - dev_priv->cp_ring->handle); - DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", - dev_priv->ring_rptr->handle); - DRM_DEBUG("dev->agp_buffer_map->handle %p\n", - dev->agp_buffer_map->handle); - } - - dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16; - dev_priv->fb_size = - ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000) - - dev_priv->fb_location; - - dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | - ((dev_priv->front_offset - + dev_priv->fb_location) >> 10)); - - dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | - ((dev_priv->back_offset - + dev_priv->fb_location) >> 10)); - - dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | - ((dev_priv->depth_offset - + dev_priv->fb_location) >> 10)); - - dev_priv->gart_size = init->gart_size; - - /* New let's set the memory map ... */ - if (dev_priv->new_memmap) { - u32 base = 0; - - DRM_INFO("Setting GART location based on new memory map\n"); - - /* If using AGP, try to locate the AGP aperture at the same - * location in the card and on the bus, though we have to - * align it down. - */ -#if __OS_HAS_AGP - if (dev_priv->flags & RADEON_IS_AGP) { - base = dev->agp->base; - /* Check if valid */ - if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && - base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { - DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", - dev->agp->base); - base = 0; - } - } -#endif - /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ - if (base == 0) { - base = dev_priv->fb_location + dev_priv->fb_size; - if (base < dev_priv->fb_location || - ((base + dev_priv->gart_size) & 0xfffffffful) < base) - base = dev_priv->fb_location - - dev_priv->gart_size; - } - dev_priv->gart_vm_start = base & 0xffc00000u; - if (dev_priv->gart_vm_start != base) - DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", - base, dev_priv->gart_vm_start); - } else { - DRM_INFO("Setting GART location based on old memory map\n"); - dev_priv->gart_vm_start = dev_priv->fb_location + - RADEON_READ(RADEON_CONFIG_APER_SIZE); - } - -#if __OS_HAS_AGP - if (dev_priv->flags & RADEON_IS_AGP) - dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset - - dev->agp->base - + dev_priv->gart_vm_start); - else -#endif - dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset - - (unsigned long)dev->sg->virtual - + dev_priv->gart_vm_start); - - DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); - DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); - DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", - dev_priv->gart_buffers_offset); - - dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; - dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle - + init->ring_size / sizeof(u32)); - dev_priv->ring.size = init->ring_size; - dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); - - dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; - dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8); - - dev_priv->ring.fetch_size = /* init->fetch_size */ 32; - dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16); - - dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; - - dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; - -#if __OS_HAS_AGP - if (dev_priv->flags & RADEON_IS_AGP) { - /* Turn off PCI GART */ - radeon_set_pcigart(dev_priv, 0); - } else -#endif - { - dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); - /* if we have an offset set from userspace */ - if (dev_priv->pcigart_offset_set) { - dev_priv->gart_info.bus_addr = - dev_priv->pcigart_offset + dev_priv->fb_location; - dev_priv->gart_info.mapping.offset = - dev_priv->pcigart_offset + dev_priv->fb_aper_offset; - dev_priv->gart_info.mapping.size = - dev_priv->gart_info.table_size; - - drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); - dev_priv->gart_info.addr = - dev_priv->gart_info.mapping.handle; - - if (dev_priv->flags & RADEON_IS_PCIE) - dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE; - else - dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; - dev_priv->gart_info.gart_table_location = - DRM_ATI_GART_FB; - - DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", - dev_priv->gart_info.addr, - dev_priv->pcigart_offset); - } else { - if (dev_priv->flags & RADEON_IS_IGPGART) - dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP; - else - dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; - dev_priv->gart_info.gart_table_location = - DRM_ATI_GART_MAIN; - dev_priv->gart_info.addr = NULL; - dev_priv->gart_info.bus_addr = 0; - if (dev_priv->flags & RADEON_IS_PCIE) { - DRM_ERROR - ("Cannot use PCI Express without GART in FB memory\n"); - radeon_do_cleanup_cp(dev); - return -EINVAL; - } - } - - if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { - DRM_ERROR("failed to init PCI GART!\n"); - radeon_do_cleanup_cp(dev); - return -ENOMEM; - } - - /* Turn on PCI GART */ - radeon_set_pcigart(dev_priv, 1); - } - - /* Start with assuming that writeback doesn't work */ - dev_priv->writeback_works = 0; - - radeon_cp_load_microcode(dev_priv); - radeon_cp_init_ring_buffer(dev, dev_priv); - - dev_priv->last_buf = 0; - - radeon_do_engine_reset(dev); - radeon_test_writeback(dev_priv); - - return 0; -} - -static int radeon_do_cleanup_cp(struct drm_device * dev) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG("\n"); - - /* Make sure interrupts are disabled here because the uninstall ioctl - * may not have been called from userspace and after dev_private - * is freed, it's too late. - */ - if (dev->irq_enabled) - drm_irq_uninstall(dev); - -#if __OS_HAS_AGP - if (dev_priv->flags & RADEON_IS_AGP) { - if (dev_priv->cp_ring != NULL) { - drm_core_ioremapfree(dev_priv->cp_ring, dev); - dev_priv->cp_ring = NULL; - } - if (dev_priv->ring_rptr != NULL) { - drm_core_ioremapfree(dev_priv->ring_rptr, dev); - dev_priv->ring_rptr = NULL; - } - if (dev->agp_buffer_map != NULL) { - drm_core_ioremapfree(dev->agp_buffer_map, dev); - dev->agp_buffer_map = NULL; - } - } else -#endif - { - - if (dev_priv->gart_info.bus_addr) { - /* Turn off PCI GART */ - radeon_set_pcigart(dev_priv, 0); - if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) - DRM_ERROR("failed to cleanup PCI GART!\n"); - } - - if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) - { - drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); - dev_priv->gart_info.addr = 0; - } - } - /* only clear to the start of flags */ - memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); - - return 0; -} - -/* This code will reinit the Radeon CP hardware after a resume from disc. - * AFAIK, it would be very difficult to pickle the state at suspend time, so - * here we make sure that all Radeon hardware initialisation is re-done without - * affecting running applications. - * - * Charl P. Botha - */ -static int radeon_do_resume_cp(struct drm_device * dev) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - - if (!dev_priv) { - DRM_ERROR("Called with no initialization\n"); - return -EINVAL; - } - - DRM_DEBUG("Starting radeon_do_resume_cp()\n"); - -#if __OS_HAS_AGP - if (dev_priv->flags & RADEON_IS_AGP) { - /* Turn off PCI GART */ - radeon_set_pcigart(dev_priv, 0); - } else -#endif - { - /* Turn on PCI GART */ - radeon_set_pcigart(dev_priv, 1); - } - - radeon_cp_load_microcode(dev_priv); - radeon_cp_init_ring_buffer(dev, dev_priv); - - radeon_do_engine_reset(dev); - radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); - - DRM_DEBUG("radeon_do_resume_cp() complete\n"); - - return 0; -} - -int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_init_t *init = data; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (init->func == RADEON_INIT_R300_CP) - r300_init_reg_flags(dev); - - switch (init->func) { - case RADEON_INIT_CP: - case RADEON_INIT_R200_CP: - case RADEON_INIT_R300_CP: - return radeon_do_init_cp(dev, init); - case RADEON_CLEANUP_CP: - return radeon_do_cleanup_cp(dev); - } - - return -EINVAL; -} - -int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (dev_priv->cp_running) { - DRM_DEBUG("while CP running\n"); - return 0; - } - if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { - DRM_DEBUG("called with bogus CP mode (%d)\n", - dev_priv->cp_mode); - return 0; - } - - radeon_do_cp_start(dev_priv); - - return 0; -} - -/* Stop the CP. The engine must have been idled before calling this - * routine. - */ -int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_cp_stop_t *stop = data; - int ret; - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (!dev_priv->cp_running) - return 0; - - /* Flush any pending CP commands. This ensures any outstanding - * commands are exectuted by the engine before we turn it off. - */ - if (stop->flush) { - radeon_do_cp_flush(dev_priv); - } - - /* If we fail to make the engine go idle, we return an error - * code so that the DRM ioctl wrapper can try again. - */ - if (stop->idle) { - ret = radeon_do_cp_idle(dev_priv); - if (ret) - return ret; - } - - /* Finally, we can turn off the CP. If the engine isn't idle, - * we will get some dropped triangles as they won't be fully - * rendered before the CP is shut down. - */ - radeon_do_cp_stop(dev_priv); - - /* Reset the engine */ - radeon_do_engine_reset(dev); - - return 0; -} - -void radeon_do_release(struct drm_device * dev) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - int i, ret; - - if (dev_priv) { - if (dev_priv->cp_running) { - /* Stop the cp */ - while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { - DRM_DEBUG("radeon_do_cp_idle %d\n", ret); -#ifdef __linux__ - schedule(); -#else - mtx_sleep(&ret, &dev->dev_lock, 0, "rdnrel", 1); -#endif - } - radeon_do_cp_stop(dev_priv); - radeon_do_engine_reset(dev); - } - - /* Disable *all* interrupts */ - if (dev_priv->mmio) /* remove this after permanent addmaps */ - RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); - - if (dev_priv->mmio) { /* remove all surfaces */ - for (i = 0; i < RADEON_MAX_SURFACES; i++) { - RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0); - RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + - 16 * i, 0); - RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + - 16 * i, 0); - } - } - - /* Free memory heap structures */ - radeon_mem_takedown(&(dev_priv->gart_heap)); - radeon_mem_takedown(&(dev_priv->fb_heap)); - - /* deallocate kernel resources */ - radeon_do_cleanup_cp(dev); - } -} - -/* Just reset the CP ring. Called as part of an X Server engine reset. - */ -int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (!dev_priv) { - DRM_DEBUG("called before init done\n"); - return -EINVAL; - } - - radeon_do_cp_reset(dev_priv); - - /* The CP is no longer running after an engine reset */ - dev_priv->cp_running = 0; - - return 0; -} - -int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - return radeon_do_cp_idle(dev_priv); -} - -/* Added by Charl P. Botha to call radeon_do_resume_cp(). - */ -int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - - return radeon_do_resume_cp(dev); -} - -int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - return radeon_do_engine_reset(dev); -} - -/* ================================================================ - * Fullscreen mode - */ - -/* KW: Deprecated to say the least: - */ -int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - return 0; -} - -/* ================================================================ - * Freelist management - */ - -/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through - * bufs until freelist code is used. Note this hides a problem with - * the scratch register * (used to keep track of last buffer - * completed) being written to before * the last buffer has actually - * completed rendering. - * - * KW: It's also a good way to find free buffers quickly. - * - * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't - * sleep. However, bugs in older versions of radeon_accel.c mean that - * we essentially have to do this, else old clients will break. - * - * However, it does leave open a potential deadlock where all the - * buffers are held by other clients, which can't release them because - * they can't get the lock. - */ - -struct drm_buf *radeon_freelist_get(struct drm_device * dev) -{ - struct drm_device_dma *dma = dev->dma; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_buf_priv_t *buf_priv; - struct drm_buf *buf; - int i, t; - int start; - - if (++dev_priv->last_buf >= dma->buf_count) - dev_priv->last_buf = 0; - - start = dev_priv->last_buf; - - for (t = 0; t < dev_priv->usec_timeout; t++) { - u32 done_age = GET_SCRATCH(1); - DRM_DEBUG("done_age = %d\n", done_age); - for (i = start; i < dma->buf_count; i++) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - if (buf->file_priv == NULL || (buf->pending && - buf_priv->age <= - done_age)) { - dev_priv->stats.requested_bufs++; - buf->pending = 0; - return buf; - } - start = 0; - } - - if (t) { - DRM_UDELAY(1); - dev_priv->stats.freelist_loops++; - } - } - - DRM_DEBUG("returning NULL!\n"); - return NULL; -} - -#if 0 -struct drm_buf *radeon_freelist_get(struct drm_device * dev) -{ - struct drm_device_dma *dma = dev->dma; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_buf_priv_t *buf_priv; - struct drm_buf *buf; - int i, t; - int start; - u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); - - if (++dev_priv->last_buf >= dma->buf_count) - dev_priv->last_buf = 0; - - start = dev_priv->last_buf; - dev_priv->stats.freelist_loops++; - - for (t = 0; t < 2; t++) { - for (i = start; i < dma->buf_count; i++) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - if (buf->file_priv == 0 || (buf->pending && - buf_priv->age <= - done_age)) { - dev_priv->stats.requested_bufs++; - buf->pending = 0; - return buf; - } - } - start = 0; - } - - return NULL; -} -#endif - -void radeon_freelist_reset(struct drm_device * dev) -{ - struct drm_device_dma *dma = dev->dma; - drm_radeon_private_t *dev_priv = dev->dev_private; - int i; - - dev_priv->last_buf = 0; - for (i = 0; i < dma->buf_count; i++) { - struct drm_buf *buf = dma->buflist[i]; - drm_radeon_buf_priv_t *buf_priv = buf->dev_private; - buf_priv->age = 0; - } -} - -/* ================================================================ - * CP command submission - */ - -int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) -{ - drm_radeon_ring_buffer_t *ring = &dev_priv->ring; - int i; - u32 last_head = GET_RING_HEAD(dev_priv); - - for (i = 0; i < dev_priv->usec_timeout; i++) { - u32 head = GET_RING_HEAD(dev_priv); - - ring->space = (head - ring->tail) * sizeof(u32); - if (ring->space <= 0) - ring->space += ring->size; - if (ring->space > n) - return 0; - - dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - - if (head != last_head) - i = 0; - last_head = head; - - DRM_UDELAY(1); - } - - /* FIXME: This return value is ignored in the BEGIN_RING macro! */ -#if RADEON_FIFO_DEBUG - radeon_status(dev_priv); - DRM_ERROR("failed!\n"); -#endif - return -EBUSY; -} - -static int radeon_cp_get_buffers(struct drm_device *dev, - struct drm_file *file_priv, - struct drm_dma * d) -{ - int i; - struct drm_buf *buf; - - for (i = d->granted_count; i < d->request_count; i++) { - buf = radeon_freelist_get(dev); - if (!buf) - return -EBUSY; /* NOTE: broken client */ - - buf->file_priv = file_priv; - - if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, - sizeof(buf->idx))) - return -EFAULT; - if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, - sizeof(buf->total))) - return -EFAULT; - - d->granted_count++; - } - return 0; -} - -int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - struct drm_device_dma *dma = dev->dma; - int ret = 0; - struct drm_dma *d = data; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - /* Please don't send us buffers. - */ - if (d->send_count != 0) { - DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d->send_count); - return -EINVAL; - } - - /* We'll send you buffers. - */ - if (d->request_count < 0 || d->request_count > dma->buf_count) { - DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d->request_count, dma->buf_count); - return -EINVAL; - } - - d->granted_count = 0; - - if (d->request_count) { - ret = radeon_cp_get_buffers(dev, file_priv, d); - } - - return ret; -} - -int radeon_driver_load(struct drm_device *dev, unsigned long flags) -{ - drm_radeon_private_t *dev_priv; - int ret = 0; - - dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); - if (dev_priv == NULL) - return -ENOMEM; - - memset(dev_priv, 0, sizeof(drm_radeon_private_t)); - dev->dev_private = (void *)dev_priv; - dev_priv->flags = flags; - - switch (flags & RADEON_FAMILY_MASK) { - case CHIP_R100: - case CHIP_RV200: - case CHIP_R200: - case CHIP_R300: - case CHIP_R350: - case CHIP_R420: - case CHIP_R423: - case CHIP_RV410: - case CHIP_RV515: - case CHIP_R520: - case CHIP_RV570: - case CHIP_R580: - dev_priv->flags |= RADEON_HAS_HIERZ; - break; - default: - /* all other chips have no hierarchical z buffer */ - break; - } - - dev_priv->chip_family = flags & RADEON_FAMILY_MASK; - if (drm_device_is_agp(dev)) - dev_priv->flags |= RADEON_IS_AGP; - else if (drm_device_is_pcie(dev)) - dev_priv->flags |= RADEON_IS_PCIE; - else - dev_priv->flags |= RADEON_IS_PCI; - - ret = drm_vblank_init(dev, 2); - if (ret) { - radeon_driver_unload(dev); - return ret; - } - - DRM_DEBUG("%s card detected\n", - ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); - return ret; -} - -/* Create mappings for registers and framebuffer so userland doesn't necessarily - * have to find them. - */ -int radeon_driver_firstopen(struct drm_device *dev) -{ - int ret; - drm_local_map_t *map; - drm_radeon_private_t *dev_priv = dev->dev_private; - - dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; - - ret = drm_addmap(dev, drm_get_resource_start(dev, 2), - drm_get_resource_len(dev, 2), _DRM_REGISTERS, - _DRM_READ_ONLY, &dev_priv->mmio); - if (ret != 0) - return ret; - - dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0); - ret = drm_addmap(dev, dev_priv->fb_aper_offset, - drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, - _DRM_WRITE_COMBINING, &map); - if (ret != 0) - return ret; - - return 0; -} - -int radeon_driver_unload(struct drm_device *dev) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - - DRM_DEBUG("\n"); - drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); - - dev->dev_private = NULL; - return 0; -} diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h deleted file mode 100644 index f53057ab..00000000 --- a/shared-core/radeon_drm.h +++ /dev/null @@ -1,907 +0,0 @@ -/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- - * - * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Fremont, California. - * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Kevin E. Martin - * Gareth Hughes - * Keith Whitwell - */ - -#ifndef __RADEON_DRM_H__ -#define __RADEON_DRM_H__ - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the X server file (radeon_sarea.h) - */ -#ifndef __RADEON_SAREA_DEFINES__ -#define __RADEON_SAREA_DEFINES__ - -/* Old style state flags, required for sarea interface (1.1 and 1.2 - * clears) and 1.2 drm_vertex2 ioctl. - */ -#define RADEON_UPLOAD_CONTEXT 0x00000001 -#define RADEON_UPLOAD_VERTFMT 0x00000002 -#define RADEON_UPLOAD_LINE 0x00000004 -#define RADEON_UPLOAD_BUMPMAP 0x00000008 -#define RADEON_UPLOAD_MASKS 0x00000010 -#define RADEON_UPLOAD_VIEWPORT 0x00000020 -#define RADEON_UPLOAD_SETUP 0x00000040 -#define RADEON_UPLOAD_TCL 0x00000080 -#define RADEON_UPLOAD_MISC 0x00000100 -#define RADEON_UPLOAD_TEX0 0x00000200 -#define RADEON_UPLOAD_TEX1 0x00000400 -#define RADEON_UPLOAD_TEX2 0x00000800 -#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 -#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 -#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 -#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ -#define RADEON_REQUIRE_QUIESCENCE 0x00010000 -#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ -#define RADEON_UPLOAD_ALL 0x003effff -#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff - -/* New style per-packet identifiers for use in cmd_buffer ioctl with - * the RADEON_EMIT_PACKET command. Comments relate new packets to old - * state bits and the packet size: - */ -#define RADEON_EMIT_PP_MISC 0 /* context/7 */ -#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ -#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ -#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ -#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ -#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ -#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ -#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ -#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ -#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ -#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ -#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ -#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ -#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ -#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ -#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ -#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ -#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ -#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ -#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ -#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ -#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ -#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ -#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ -#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ -#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ -#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ -#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ -#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ -#define R200_EMIT_VAP_CTL 32 /* vap/1 */ -#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ -#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ -#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ -#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ -#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ -#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ -#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ -#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ -#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ -#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ -#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ -#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ -#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ -#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ -#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ -#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ -#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ -#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ -#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ -#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ -#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ -#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ -#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ -#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ -#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ -#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ -#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ -#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ -#define R200_EMIT_PP_CUBIC_FACES_0 61 -#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 -#define R200_EMIT_PP_CUBIC_FACES_1 63 -#define R200_EMIT_PP_CUBIC_OFFSETS_1 64 -#define R200_EMIT_PP_CUBIC_FACES_2 65 -#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 -#define R200_EMIT_PP_CUBIC_FACES_3 67 -#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 -#define R200_EMIT_PP_CUBIC_FACES_4 69 -#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 -#define R200_EMIT_PP_CUBIC_FACES_5 71 -#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 -#define RADEON_EMIT_PP_TEX_SIZE_0 73 -#define RADEON_EMIT_PP_TEX_SIZE_1 74 -#define RADEON_EMIT_PP_TEX_SIZE_2 75 -#define R200_EMIT_RB3D_BLENDCOLOR 76 -#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 -#define RADEON_EMIT_PP_CUBIC_FACES_0 78 -#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 -#define RADEON_EMIT_PP_CUBIC_FACES_1 80 -#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 -#define RADEON_EMIT_PP_CUBIC_FACES_2 82 -#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 -#define R200_EMIT_PP_TRI_PERF_CNTL 84 -#define R200_EMIT_PP_AFS_0 85 -#define R200_EMIT_PP_AFS_1 86 -#define R200_EMIT_ATF_TFACTOR 87 -#define R200_EMIT_PP_TXCTLALL_0 88 -#define R200_EMIT_PP_TXCTLALL_1 89 -#define R200_EMIT_PP_TXCTLALL_2 90 -#define R200_EMIT_PP_TXCTLALL_3 91 -#define R200_EMIT_PP_TXCTLALL_4 92 -#define R200_EMIT_PP_TXCTLALL_5 93 -#define R200_EMIT_VAP_PVS_CNTL 94 -#define RADEON_MAX_STATE_PACKETS 95 - -/* Commands understood by cmd_buffer ioctl. More can be added but - * obviously these can't be removed or changed: - */ -#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ -#define RADEON_CMD_SCALARS 2 /* emit scalar data */ -#define RADEON_CMD_VECTORS 3 /* emit vector data */ -#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ -#define RADEON_CMD_PACKET3 5 /* emit hw packet */ -#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ -#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ -#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: - * doesn't make the cpu wait, just - * the graphics hardware */ -#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ - -typedef union { - int i; - struct { - unsigned char cmd_type, pad0, pad1, pad2; - } header; - struct { - unsigned char cmd_type, packet_id, pad0, pad1; - } packet; - struct { - unsigned char cmd_type, offset, stride, count; - } scalars; - struct { - unsigned char cmd_type, offset, stride, count; - } vectors; - struct { - unsigned char cmd_type, addr_lo, addr_hi, count; - } veclinear; - struct { - unsigned char cmd_type, buf_idx, pad0, pad1; - } dma; - struct { - unsigned char cmd_type, flags, pad0, pad1; - } wait; -} drm_radeon_cmd_header_t; - -#define RADEON_WAIT_2D 0x1 -#define RADEON_WAIT_3D 0x2 - -/* Allowed parameters for R300_CMD_PACKET3 - */ -#define R300_CMD_PACKET3_CLEAR 0 -#define R300_CMD_PACKET3_RAW 1 - -/* Commands understood by cmd_buffer ioctl for R300. - * The interface has not been stabilized, so some of these may be removed - * and eventually reordered before stabilization. - */ -#define R300_CMD_PACKET0 1 -#define R300_CMD_VPU 2 /* emit vertex program upload */ -#define R300_CMD_PACKET3 3 /* emit a packet3 */ -#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ -#define R300_CMD_CP_DELAY 5 -#define R300_CMD_DMA_DISCARD 6 -#define R300_CMD_WAIT 7 -# define R300_WAIT_2D 0x1 -# define R300_WAIT_3D 0x2 -/* these two defines are DOING IT WRONG - however - * we have userspace which relies on using these. - * The wait interface is backwards compat new - * code should use the NEW_WAIT defines below - * THESE ARE NOT BIT FIELDS - */ -# define R300_WAIT_2D_CLEAN 0x3 -# define R300_WAIT_3D_CLEAN 0x4 - -# define R300_NEW_WAIT_2D_3D 0x3 -# define R300_NEW_WAIT_2D_2D_CLEAN 0x4 -# define R300_NEW_WAIT_3D_3D_CLEAN 0x6 -# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 - -#define R300_CMD_SCRATCH 8 -#define R300_CMD_R500FP 9 - -typedef union { - unsigned int u; - struct { - unsigned char cmd_type, pad0, pad1, pad2; - } header; - struct { - unsigned char cmd_type, count, reglo, reghi; - } packet0; - struct { - unsigned char cmd_type, count, adrlo, adrhi; - } vpu; - struct { - unsigned char cmd_type, packet, pad0, pad1; - } packet3; - struct { - unsigned char cmd_type, packet; - unsigned short count; /* amount of packet2 to emit */ - } delay; - struct { - unsigned char cmd_type, buf_idx, pad0, pad1; - } dma; - struct { - unsigned char cmd_type, flags, pad0, pad1; - } wait; - struct { - unsigned char cmd_type, reg, n_bufs, flags; - } scratch; - struct { - unsigned char cmd_type, count, adrlo, adrhi_flags; - } r500fp; -} drm_r300_cmd_header_t; - -#define RADEON_FRONT 0x1 -#define RADEON_BACK 0x2 -#define RADEON_DEPTH 0x4 -#define RADEON_STENCIL 0x8 -#define RADEON_CLEAR_FASTZ 0x80000000 -#define RADEON_USE_HIERZ 0x40000000 -#define RADEON_USE_COMP_ZBUF 0x20000000 - -#define R500FP_CONSTANT_TYPE (1 << 1) -#define R500FP_CONSTANT_CLAMP (1 << 2) - -/* Primitive types - */ -#define RADEON_POINTS 0x1 -#define RADEON_LINES 0x2 -#define RADEON_LINE_STRIP 0x3 -#define RADEON_TRIANGLES 0x4 -#define RADEON_TRIANGLE_FAN 0x5 -#define RADEON_TRIANGLE_STRIP 0x6 - -/* Vertex/indirect buffer size - */ -#define RADEON_BUFFER_SIZE 65536 - -/* Byte offsets for indirect buffer data - */ -#define RADEON_INDEX_PRIM_OFFSET 20 - -#define RADEON_SCRATCH_REG_OFFSET 32 -#define R600_SCRATCH_REG_OFFSET 256 - -#define RADEON_NR_SAREA_CLIPRECTS 12 - -/* There are 2 heaps (local/GART). Each region within a heap is a - * minimum of 64k, and there are at most 64 of them per heap. - */ -#define RADEON_LOCAL_TEX_HEAP 0 -#define RADEON_GART_TEX_HEAP 1 -#define RADEON_NR_TEX_HEAPS 2 -#define RADEON_NR_TEX_REGIONS 64 -#define RADEON_LOG_TEX_GRANULARITY 16 - -#define RADEON_MAX_TEXTURE_LEVELS 12 -#define RADEON_MAX_TEXTURE_UNITS 3 - -#define RADEON_MAX_SURFACES 8 - -/* Blits have strict offset rules. All blit offset must be aligned on - * a 1K-byte boundary. - */ -#define RADEON_OFFSET_SHIFT 10 -#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) -#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) - -#endif /* __RADEON_SAREA_DEFINES__ */ - -typedef struct { - unsigned int red; - unsigned int green; - unsigned int blue; - unsigned int alpha; -} radeon_color_regs_t; - -typedef struct { - /* Context state */ - unsigned int pp_misc; /* 0x1c14 */ - unsigned int pp_fog_color; - unsigned int re_solid_color; - unsigned int rb3d_blendcntl; - unsigned int rb3d_depthoffset; - unsigned int rb3d_depthpitch; - unsigned int rb3d_zstencilcntl; - - unsigned int pp_cntl; /* 0x1c38 */ - unsigned int rb3d_cntl; - unsigned int rb3d_coloroffset; - unsigned int re_width_height; - unsigned int rb3d_colorpitch; - unsigned int se_cntl; - - /* Vertex format state */ - unsigned int se_coord_fmt; /* 0x1c50 */ - - /* Line state */ - unsigned int re_line_pattern; /* 0x1cd0 */ - unsigned int re_line_state; - - unsigned int se_line_width; /* 0x1db8 */ - - /* Bumpmap state */ - unsigned int pp_lum_matrix; /* 0x1d00 */ - - unsigned int pp_rot_matrix_0; /* 0x1d58 */ - unsigned int pp_rot_matrix_1; - - /* Mask state */ - unsigned int rb3d_stencilrefmask; /* 0x1d7c */ - unsigned int rb3d_ropcntl; - unsigned int rb3d_planemask; - - /* Viewport state */ - unsigned int se_vport_xscale; /* 0x1d98 */ - unsigned int se_vport_xoffset; - unsigned int se_vport_yscale; - unsigned int se_vport_yoffset; - unsigned int se_vport_zscale; - unsigned int se_vport_zoffset; - - /* Setup state */ - unsigned int se_cntl_status; /* 0x2140 */ - - /* Misc state */ - unsigned int re_top_left; /* 0x26c0 */ - unsigned int re_misc; -} drm_radeon_context_regs_t; - -typedef struct { - /* Zbias state */ - unsigned int se_zbias_factor; /* 0x1dac */ - unsigned int se_zbias_constant; -} drm_radeon_context2_regs_t; - -/* Setup registers for each texture unit - */ -typedef struct { - unsigned int pp_txfilter; - unsigned int pp_txformat; - unsigned int pp_txoffset; - unsigned int pp_txcblend; - unsigned int pp_txablend; - unsigned int pp_tfactor; - unsigned int pp_border_color; -} drm_radeon_texture_regs_t; - -typedef struct { - unsigned int start; - unsigned int finish; - unsigned int prim:8; - unsigned int stateidx:8; - unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ - unsigned int vc_format; /* vertex format */ -} drm_radeon_prim_t; - -typedef struct { - drm_radeon_context_regs_t context; - drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; - drm_radeon_context2_regs_t context2; - unsigned int dirty; -} drm_radeon_state_t; - -typedef struct { - /* The channel for communication of state information to the - * kernel on firing a vertex buffer with either of the - * obsoleted vertex/index ioctls. - */ - drm_radeon_context_regs_t context_state; - drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; - unsigned int dirty; - unsigned int vertsize; - unsigned int vc_format; - - /* The current cliprects, or a subset thereof. - */ - struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; - unsigned int nbox; - - /* Counters for client-side throttling of rendering clients. - */ - unsigned int last_frame; - unsigned int last_dispatch; - unsigned int last_clear; - - struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + - 1]; - unsigned int tex_age[RADEON_NR_TEX_HEAPS]; - int ctx_owner; - int pfState; /* number of 3d windows (0,1,2ormore) */ - int pfCurrentPage; /* which buffer is being displayed? */ - int crtc2_base; /* CRTC2 frame offset */ - int tiling_enabled; /* set by drm, read by 2d + 3d clients */ -} drm_radeon_sarea_t; - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (xf86drmRadeon.h) - * - * KW: actually it's illegal to change any of this (backwards compatibility). - */ - -/* Radeon specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ -#define DRM_RADEON_CP_INIT 0x00 -#define DRM_RADEON_CP_START 0x01 -#define DRM_RADEON_CP_STOP 0x02 -#define DRM_RADEON_CP_RESET 0x03 -#define DRM_RADEON_CP_IDLE 0x04 -#define DRM_RADEON_RESET 0x05 -#define DRM_RADEON_FULLSCREEN 0x06 -#define DRM_RADEON_SWAP 0x07 -#define DRM_RADEON_CLEAR 0x08 -#define DRM_RADEON_VERTEX 0x09 -#define DRM_RADEON_INDICES 0x0A -#define DRM_RADEON_NOT_USED -#define DRM_RADEON_STIPPLE 0x0C -#define DRM_RADEON_INDIRECT 0x0D -#define DRM_RADEON_TEXTURE 0x0E -#define DRM_RADEON_VERTEX2 0x0F -#define DRM_RADEON_CMDBUF 0x10 -#define DRM_RADEON_GETPARAM 0x11 -#define DRM_RADEON_FLIP 0x12 -#define DRM_RADEON_ALLOC 0x13 -#define DRM_RADEON_FREE 0x14 -#define DRM_RADEON_INIT_HEAP 0x15 -#define DRM_RADEON_IRQ_EMIT 0x16 -#define DRM_RADEON_IRQ_WAIT 0x17 -#define DRM_RADEON_CP_RESUME 0x18 -#define DRM_RADEON_SETPARAM 0x19 -#define DRM_RADEON_SURF_ALLOC 0x1a -#define DRM_RADEON_SURF_FREE 0x1b -/* KMS ioctl */ -#define DRM_RADEON_GEM_INFO 0x1c -#define DRM_RADEON_GEM_CREATE 0x1d -#define DRM_RADEON_GEM_MMAP 0x1e -#define DRM_RADEON_GEM_PREAD 0x21 -#define DRM_RADEON_GEM_PWRITE 0x22 -#define DRM_RADEON_GEM_SET_DOMAIN 0x23 -#define DRM_RADEON_GEM_WAIT_IDLE 0x24 -#define DRM_RADEON_CS 0x26 -#define DRM_RADEON_INFO 0x27 -#define DRM_RADEON_GEM_SET_TILING 0x28 -#define DRM_RADEON_GEM_GET_TILING 0x29 -#define DRM_RADEON_GEM_BUSY 0x2a - -#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) -#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) -#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) -#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) -#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) -#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) -#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) -#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) -#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) -#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) -#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) -#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) -#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) -#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) -#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) -#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) -#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) -#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) -#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) -#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) -#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) -#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) -#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) -#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) -#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) -#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) -#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) -/* KMS */ -#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) -#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) -#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) -#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) -#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) -#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) -#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) -#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) -#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) -#define DRM_IOCTL_RADEON_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) -#define DRM_IOCTL_RADEON_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) -#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) - -typedef struct drm_radeon_init { - enum { - RADEON_INIT_CP = 0x01, - RADEON_CLEANUP_CP = 0x02, - RADEON_INIT_R200_CP = 0x03, - RADEON_INIT_R300_CP = 0x04, - RADEON_INIT_R600_CP = 0x05 - } func; - unsigned long sarea_priv_offset; - int is_pci; /* for overriding only */ - int cp_mode; - int gart_size; - int ring_size; - int usec_timeout; - - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - - unsigned long fb_offset DEPRECATED; /* deprecated, driver asks hardware */ - unsigned long mmio_offset DEPRECATED; /* deprecated, driver asks hardware */ - unsigned long ring_offset; - unsigned long ring_rptr_offset; - unsigned long buffers_offset; - unsigned long gart_textures_offset; -} drm_radeon_init_t; - -typedef struct drm_radeon_cp_stop { - int flush; - int idle; -} drm_radeon_cp_stop_t; - -typedef struct drm_radeon_fullscreen { - enum { - RADEON_INIT_FULLSCREEN = 0x01, - RADEON_CLEANUP_FULLSCREEN = 0x02 - } func; -} drm_radeon_fullscreen_t; - -#define CLEAR_X1 0 -#define CLEAR_Y1 1 -#define CLEAR_X2 2 -#define CLEAR_Y2 3 -#define CLEAR_DEPTH 4 - -typedef union drm_radeon_clear_rect { - float f[5]; - unsigned int ui[5]; -} drm_radeon_clear_rect_t; - -typedef struct drm_radeon_clear { - unsigned int flags; - unsigned int clear_color; - unsigned int clear_depth; - unsigned int color_mask; - unsigned int depth_mask; /* misnamed field: should be stencil */ - drm_radeon_clear_rect_t __user *depth_boxes; -} drm_radeon_clear_t; - -typedef struct drm_radeon_vertex { - int prim; - int idx; /* Index of vertex buffer */ - int count; /* Number of vertices in buffer */ - int discard; /* Client finished with buffer? */ -} drm_radeon_vertex_t; - -typedef struct drm_radeon_indices { - int prim; - int idx; - int start; - int end; - int discard; /* Client finished with buffer? */ -} drm_radeon_indices_t; - -/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices - * - allows multiple primitives and state changes in a single ioctl - * - supports driver change to emit native primitives - */ -typedef struct drm_radeon_vertex2 { - int idx; /* Index of vertex buffer */ - int discard; /* Client finished with buffer? */ - int nr_states; - drm_radeon_state_t __user *state; - int nr_prims; - drm_radeon_prim_t __user *prim; -} drm_radeon_vertex2_t; - -/* v1.3 - obsoletes drm_radeon_vertex2 - * - allows arbitarily large cliprect list - * - allows updating of tcl packet, vector and scalar state - * - allows memory-efficient description of state updates - * - allows state to be emitted without a primitive - * (for clears, ctx switches) - * - allows more than one dma buffer to be referenced per ioctl - * - supports tcl driver - * - may be extended in future versions with new cmd types, packets - */ -typedef struct drm_radeon_cmd_buffer { - int bufsz; - char __user *buf; - int nbox; - struct drm_clip_rect __user *boxes; -} drm_radeon_cmd_buffer_t; - -typedef struct drm_radeon_tex_image { - unsigned int x, y; /* Blit coordinates */ - unsigned int width, height; - const void __user *data; -} drm_radeon_tex_image_t; - -typedef struct drm_radeon_texture { - unsigned int offset; - int pitch; - int format; - int width; /* Texture image coordinates */ - int height; - drm_radeon_tex_image_t __user *image; -} drm_radeon_texture_t; - -typedef struct drm_radeon_stipple { - unsigned int __user *mask; -} drm_radeon_stipple_t; - -typedef struct drm_radeon_indirect { - int idx; - int start; - int end; - int discard; -} drm_radeon_indirect_t; - -/* enum for card type parameters */ -#define RADEON_CARD_PCI 0 -#define RADEON_CARD_AGP 1 -#define RADEON_CARD_PCIE 2 - -/* 1.3: An ioctl to get parameters that aren't available to the 3d - * client any other way. - */ -#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ -#define RADEON_PARAM_LAST_FRAME 2 -#define RADEON_PARAM_LAST_DISPATCH 3 -#define RADEON_PARAM_LAST_CLEAR 4 -/* Added with DRM version 1.6. */ -#define RADEON_PARAM_IRQ_NR 5 -#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ -/* Added with DRM version 1.8. */ -#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ -#define RADEON_PARAM_STATUS_HANDLE 8 -#define RADEON_PARAM_SAREA_HANDLE 9 -#define RADEON_PARAM_GART_TEX_HANDLE 10 -#define RADEON_PARAM_SCRATCH_OFFSET 11 -#define RADEON_PARAM_CARD_TYPE 12 -#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ -#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ -#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ -#define RADEON_PARAM_DEVICE_ID 16 -#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */ - -typedef struct drm_radeon_getparam { - int param; - void __user *value; -} drm_radeon_getparam_t; - -/* 1.6: Set up a memory manager for regions of shared memory: - */ -#define RADEON_MEM_REGION_GART 1 -#define RADEON_MEM_REGION_FB 2 - -typedef struct drm_radeon_mem_alloc { - int region; - int alignment; - int size; - int __user *region_offset; /* offset from start of fb or GART */ -} drm_radeon_mem_alloc_t; - -typedef struct drm_radeon_mem_free { - int region; - int region_offset; -} drm_radeon_mem_free_t; - -typedef struct drm_radeon_mem_init_heap { - int region; - int size; - int start; -} drm_radeon_mem_init_heap_t; - -/* 1.6: Userspace can request & wait on irq's: - */ -typedef struct drm_radeon_irq_emit { - int __user *irq_seq; -} drm_radeon_irq_emit_t; - -typedef struct drm_radeon_irq_wait { - int irq_seq; -} drm_radeon_irq_wait_t; - -/* 1.10: Clients tell the DRM where they think the framebuffer is located in - * the card's address space, via a new generic ioctl to set parameters - */ - -typedef struct drm_radeon_setparam { - unsigned int param; - int64_t value; -} drm_radeon_setparam_t; - -#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ -#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ -#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ -#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ -#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ -#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ -/* 1.14: Clients can allocate/free a surface - */ -typedef struct drm_radeon_surface_alloc { - unsigned int address; - unsigned int size; - unsigned int flags; -} drm_radeon_surface_alloc_t; - -typedef struct drm_radeon_surface_free { - unsigned int address; -} drm_radeon_surface_free_t; - -#define DRM_RADEON_VBLANK_CRTC1 1 -#define DRM_RADEON_VBLANK_CRTC2 2 - -/* - * Kernel modesetting world below. - */ -#define RADEON_GEM_DOMAIN_CPU 0x1 -#define RADEON_GEM_DOMAIN_GTT 0x2 -#define RADEON_GEM_DOMAIN_VRAM 0x4 - -struct drm_radeon_gem_info { - uint64_t gart_size; - uint64_t vram_size; - uint64_t vram_visible; -}; - -#define RADEON_GEM_NO_BACKING_STORE 1 - -struct drm_radeon_gem_create { - uint64_t size; - uint64_t alignment; - uint32_t handle; - uint32_t initial_domain; - uint32_t flags; -}; - -#define RADEON_TILING_MACRO 0x1 -#define RADEON_TILING_MICRO 0x2 -#define RADEON_TILING_SWAP_16BIT 0x4 -#define RADEON_TILING_SWAP_32BIT 0x8 -#define RADEON_TILING_SURFACE 0x10 /* this object requires a surface - * when mapped - i.e. front buffer */ - -struct drm_radeon_gem_set_tiling { - uint32_t handle; - uint32_t tiling_flags; - uint32_t pitch; -}; - -struct drm_radeon_gem_get_tiling { - uint32_t handle; - uint32_t tiling_flags; - uint32_t pitch; -}; - -struct drm_radeon_gem_mmap { - uint32_t handle; - uint32_t pad; - uint64_t offset; - uint64_t size; - uint64_t addr_ptr; -}; - -struct drm_radeon_gem_set_domain { - uint32_t handle; - uint32_t read_domains; - uint32_t write_domain; -}; - -struct drm_radeon_gem_wait_idle { - uint32_t handle; - uint32_t pad; -}; - -struct drm_radeon_gem_busy { - uint32_t handle; - uint32_t domain; -}; - -struct drm_radeon_gem_pread { - /** Handle for the object being read. */ - uint32_t handle; - uint32_t pad; - /** Offset into the object to read from */ - uint64_t offset; - /** Length of data to read */ - uint64_t size; - /** Pointer to write the data into. */ - /* void *, but pointers are not 32/64 compatible */ - uint64_t data_ptr; -}; - -struct drm_radeon_gem_pwrite { - /** Handle for the object being written to. */ - uint32_t handle; - uint32_t pad; - /** Offset into the object to write to */ - uint64_t offset; - /** Length of data to write */ - uint64_t size; - /** Pointer to read the data from. */ - /* void *, but pointers are not 32/64 compatible */ - uint64_t data_ptr; -}; - -#define RADEON_CHUNK_ID_RELOCS 0x01 -#define RADEON_CHUNK_ID_IB 0x02 - -struct drm_radeon_cs_chunk { - uint32_t chunk_id; - uint32_t length_dw; - uint64_t chunk_data; -}; - -struct drm_radeon_cs_reloc { - uint32_t handle; - uint32_t read_domains; - uint32_t write_domain; - uint32_t flags; -}; - -struct drm_radeon_cs { - uint32_t num_chunks; - uint32_t cs_id; - /* this points to uint64_t * which point to cs chunks */ - uint64_t chunks; - /* updates to the limits after this CS ioctl */ - uint64_t gart_limit; - uint64_t vram_limit; -}; - -#define RADEON_INFO_DEVICE_ID 0x00 -#define RADEON_INFO_NUM_GB_PIPES 0x01 -#define RADEON_INFO_NUM_Z_PIPES 0x02 - -struct drm_radeon_info { - uint32_t request; - uint32_t pad; - uint64_t value; -}; - -#endif diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h deleted file mode 100644 index dd2b71ae..00000000 --- a/shared-core/radeon_drv.h +++ /dev/null @@ -1,1470 +0,0 @@ -/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Fremont, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Kevin E. Martin - * Gareth Hughes - */ - -#ifndef __RADEON_DRV_H__ -#define __RADEON_DRV_H__ - -/* General customization: - */ - -#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." - -#define DRIVER_NAME "radeon" -#define DRIVER_DESC "ATI Radeon" -#define DRIVER_DATE "20080613" - -/* Interface history: - * - * 1.1 - ?? - * 1.2 - Add vertex2 ioctl (keith) - * - Add stencil capability to clear ioctl (gareth, keith) - * - Increase MAX_TEXTURE_LEVELS (brian) - * 1.3 - Add cmdbuf ioctl (keith) - * - Add support for new radeon packets (keith) - * - Add getparam ioctl (keith) - * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). - * 1.4 - Add scratch registers to get_param ioctl. - * 1.5 - Add r200 packets to cmdbuf ioctl - * - Add r200 function to init ioctl - * - Add 'scalar2' instruction to cmdbuf - * 1.6 - Add static GART memory manager - * Add irq handler (won't be turned on unless X server knows to) - * Add irq ioctls and irq_active getparam. - * Add wait command for cmdbuf ioctl - * Add GART offset query for getparam - * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] - * and R200_PP_CUBIC_OFFSET_F1_[0..5]. - * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and - * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) - * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) - * Add 'GET' queries for starting additional clients on different VT's. - * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. - * Add texture rectangle support for r100. - * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which - * clients use to tell the DRM where they think the framebuffer is - * located in the card's address space - * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color - * and GL_EXT_blend_[func|equation]_separate on r200 - * 1.12- Add R300 CP microcode support - this just loads the CP on r300 - * (No 3D support yet - just microcode loading). - * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters - * - Add hyperz support, add hyperz flags to clear ioctl. - * 1.14- Add support for color tiling - * - Add R100/R200 surface allocation/free support - * 1.15- Add support for texture micro tiling - * - Add support for r100 cube maps - * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear - * texture filtering on r200 - * 1.17- Add initial support for R300 (3D). - * 1.18- Add support for GL_ATI_fragment_shader, new packets - * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces - * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR - * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) - * 1.19- Add support for gart table in FB memory and PCIE r300 - * 1.20- Add support for r300 texrect - * 1.21- Add support for card type getparam - * 1.22- Add support for texture cache flushes (R300_TX_CNTL) - * 1.23- Add new radeon memory map work from benh - * 1.24- Add general-purpose packet for manipulating scratch registers (r300) - * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, - * new packet type) - * 1.26- Add support for variable size PCI(E) gart aperture - * 1.27- Add support for IGP GART - * 1.28- Add support for VBL on CRTC2 - * 1.29- R500 3D cmd buffer support - */ - -#define DRIVER_MAJOR 1 -#define DRIVER_MINOR 29 -#define DRIVER_PATCHLEVEL 0 - -/* - * Radeon chip families - */ -enum radeon_family { - CHIP_R100, - CHIP_RV100, - CHIP_RS100, - CHIP_RV200, - CHIP_RS200, - CHIP_R200, - CHIP_RV250, - CHIP_RS300, - CHIP_RV280, - CHIP_R300, - CHIP_R350, - CHIP_RV350, - CHIP_RV380, - CHIP_R420, - CHIP_R423, - CHIP_RV410, - CHIP_RS400, - CHIP_RS480, - CHIP_RS690, - CHIP_RS740, - CHIP_RV515, - CHIP_R520, - CHIP_RV530, - CHIP_RV560, - CHIP_RV570, - CHIP_R580, - CHIP_LAST, -}; - -/* - * Chip flags - */ -enum radeon_chip_flags { - RADEON_FAMILY_MASK = 0x0000ffffUL, - RADEON_FLAGS_MASK = 0xffff0000UL, - RADEON_IS_MOBILITY = 0x00010000UL, - RADEON_IS_IGP = 0x00020000UL, - RADEON_SINGLE_CRTC = 0x00040000UL, - RADEON_IS_AGP = 0x00080000UL, - RADEON_HAS_HIERZ = 0x00100000UL, - RADEON_IS_PCIE = 0x00200000UL, - RADEON_NEW_MEMMAP = 0x00400000UL, - RADEON_IS_PCI = 0x00800000UL, - RADEON_IS_IGPGART = 0x01000000UL, -}; - -#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ - DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR)) -#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) - -typedef struct drm_radeon_freelist { - unsigned int age; - struct drm_buf *buf; - struct drm_radeon_freelist *next; - struct drm_radeon_freelist *prev; -} drm_radeon_freelist_t; - -typedef struct drm_radeon_ring_buffer { - u32 *start; - u32 *end; - int size; /* Double Words */ - int size_l2qw; /* log2 Quad Words */ - - int rptr_update; /* Double Words */ - int rptr_update_l2qw; /* log2 Quad Words */ - - int fetch_size; /* Double Words */ - int fetch_size_l2ow; /* log2 Oct Words */ - - u32 tail; - u32 tail_mask; - int space; - - int high_mark; -} drm_radeon_ring_buffer_t; - -typedef struct drm_radeon_depth_clear_t { - u32 rb3d_cntl; - u32 rb3d_zstencilcntl; - u32 se_cntl; -} drm_radeon_depth_clear_t; - -struct drm_radeon_driver_file_fields { - int64_t radeon_fb_delta; -}; - -struct mem_block { - struct mem_block *next; - struct mem_block *prev; - int start; - int size; - struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ -}; - -struct radeon_surface { - int refcount; - u32 lower; - u32 upper; - u32 flags; -}; - -struct radeon_virt_surface { - int surface_index; - u32 lower; - u32 upper; - u32 flags; - struct drm_file *file_priv; -}; - -#define RADEON_FLUSH_EMITED (1 < 0) -#define RADEON_PURGE_EMITED (1 < 1) - -typedef struct drm_radeon_private { - - drm_radeon_ring_buffer_t ring; - drm_radeon_sarea_t *sarea_priv; - - u32 fb_location; - u32 fb_size; - int new_memmap; - - int gart_size; - u32 gart_vm_start; - unsigned long gart_buffers_offset; - - int cp_mode; - int cp_running; - - drm_radeon_freelist_t *head; - drm_radeon_freelist_t *tail; - int last_buf; - volatile u32 *scratch; - int writeback_works; - - int usec_timeout; - - struct { - u32 boxes; - int freelist_timeouts; - int freelist_loops; - int requested_bufs; - int last_frame_reads; - int last_clear_reads; - int clears; - int texture_uploads; - } stats; - - int do_boxes; - int page_flipping; - - u32 color_fmt; - unsigned int front_offset; - unsigned int front_pitch; - unsigned int back_offset; - unsigned int back_pitch; - - u32 depth_fmt; - unsigned int depth_offset; - unsigned int depth_pitch; - - u32 front_pitch_offset; - u32 back_pitch_offset; - u32 depth_pitch_offset; - - drm_radeon_depth_clear_t depth_clear; - - unsigned long ring_offset; - unsigned long ring_rptr_offset; - unsigned long buffers_offset; - unsigned long gart_textures_offset; - - drm_local_map_t *sarea; - drm_local_map_t *mmio; - drm_local_map_t *cp_ring; - drm_local_map_t *ring_rptr; - drm_local_map_t *gart_textures; - - struct mem_block *gart_heap; - struct mem_block *fb_heap; - - /* SW interrupt */ - wait_queue_head_t swi_queue; - atomic_t swi_emitted; - int vblank_crtc; - uint32_t irq_enable_reg; - int irq_enabled; - uint32_t r500_disp_irq_reg; - - struct radeon_surface surfaces[RADEON_MAX_SURFACES]; - struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; - - unsigned long pcigart_offset; - unsigned int pcigart_offset_set; - struct drm_ati_pcigart_info gart_info; - - u32 scratch_ages[5]; - - unsigned int crtc_last_cnt; - unsigned int crtc2_last_cnt; - - /* starting from here on, data is preserved accross an open */ - uint32_t flags; /* see radeon_chip_flags */ - unsigned long fb_aper_offset; - - int num_gb_pipes; - int track_flush; - uint32_t chip_family; /* extract from flags */ -} drm_radeon_private_t; - -typedef struct drm_radeon_buf_priv { - u32 age; -} drm_radeon_buf_priv_t; - -typedef struct drm_radeon_kcmd_buffer { - int bufsz; - char *buf; - int nbox; - struct drm_clip_rect __user *boxes; -} drm_radeon_kcmd_buffer_t; - -extern int radeon_no_wb; -extern struct drm_ioctl_desc radeon_ioctls[]; -extern int radeon_max_ioctl; - -/* Check whether the given hardware address is inside the framebuffer or the - * GART area. - */ -static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, - u64 off) -{ - u32 fb_start = dev_priv->fb_location; - u32 fb_end = fb_start + dev_priv->fb_size - 1; - u32 gart_start = dev_priv->gart_vm_start; - u32 gart_end = gart_start + dev_priv->gart_size - 1; - - return ((off >= fb_start && off <= fb_end) || - (off >= gart_start && off <= gart_end)); -} - - /* radeon_cp.c */ -extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); - -extern void radeon_freelist_reset(struct drm_device * dev); -extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); - -extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); - -extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); - -extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern void radeon_mem_takedown(struct mem_block **heap); -extern void radeon_mem_release(struct drm_file *file_priv, - struct mem_block *heap); - - /* radeon_irq.c */ -extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); -extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); - -extern void radeon_do_release(struct drm_device * dev); -extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); -extern int radeon_enable_vblank(struct drm_device *dev, int crtc); -extern void radeon_disable_vblank(struct drm_device *dev, int crtc); -extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); -extern void radeon_driver_irq_preinstall(struct drm_device * dev); -extern int radeon_driver_irq_postinstall(struct drm_device * dev); -extern void radeon_driver_irq_uninstall(struct drm_device * dev); -extern int radeon_vblank_crtc_get(struct drm_device *dev); -extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); - -extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); -extern int radeon_driver_unload(struct drm_device *dev); -extern int radeon_driver_firstopen(struct drm_device *dev); -extern void radeon_driver_preclose(struct drm_device * dev, - struct drm_file *file_priv); -extern void radeon_driver_postclose(struct drm_device * dev, - struct drm_file *file_priv); -extern void radeon_driver_lastclose(struct drm_device * dev); -extern int radeon_driver_open(struct drm_device * dev, - struct drm_file * file_priv); -extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, - unsigned long arg); - -/* r300_cmdbuf.c */ -extern void r300_init_reg_flags(struct drm_device *dev); - -extern int r300_do_cp_cmdbuf(struct drm_device *dev, - struct drm_file *file_priv, - drm_radeon_kcmd_buffer_t *cmdbuf); - -/* Flags for stats.boxes - */ -#define RADEON_BOX_DMA_IDLE 0x1 -#define RADEON_BOX_RING_FULL 0x2 -#define RADEON_BOX_FLIP 0x4 -#define RADEON_BOX_WAIT_IDLE 0x8 -#define RADEON_BOX_TEXTURE_LOAD 0x10 - -/* Register definitions, register access macros and drmAddMap constants - * for Radeon kernel driver. - */ -#define RADEON_AGP_COMMAND 0x0f60 -#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ -# define RADEON_AGP_ENABLE (1<<8) -#define RADEON_AUX_SCISSOR_CNTL 0x26f0 -# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) -# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) -# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) -# define RADEON_SCISSOR_0_ENABLE (1 << 28) -# define RADEON_SCISSOR_1_ENABLE (1 << 29) -# define RADEON_SCISSOR_2_ENABLE (1 << 30) - -/* - * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx) - * don't have an explicit bus mastering disable bit. It's handled - * by the PCI D-states. PMI_BM_DIS disables D-state bus master - * handling, not bus mastering itself. - */ -#define RADEON_BUS_CNTL 0x0030 -/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ -# define RADEON_BUS_MASTER_DIS (1 << 6) -/* rs600/rs690/rs740 */ -# define RS600_BUS_MASTER_DIS (1 << 14) -# define RS600_MSI_REARM (1 << 20) -/* see RS480_MSI_REARM in AIC_CNTL for rs480 */ - -#define RADEON_BUS_CNTL1 0x0034 -# define RADEON_PMI_BM_DIS (1 << 2) -# define RADEON_PMI_INT_DIS (1 << 3) - -#define RV370_BUS_CNTL 0x004c -# define RV370_PMI_BM_DIS (1 << 5) -# define RV370_PMI_INT_DIS (1 << 6) - -#define RADEON_MSI_REARM_EN 0x0160 -/* rv370/rv380, rv410, r423/r430/r480, r5xx */ -# define RV370_MSI_REARM_EN (1 << 0) - -#define RADEON_CLOCK_CNTL_DATA 0x000c -# define RADEON_PLL_WR_EN (1 << 7) -#define RADEON_CLOCK_CNTL_INDEX 0x0008 -#define RADEON_CONFIG_APER_SIZE 0x0108 -#define RADEON_CONFIG_MEMSIZE 0x00f8 -#define RADEON_CRTC_OFFSET 0x0224 -#define RADEON_CRTC_OFFSET_CNTL 0x0228 -# define RADEON_CRTC_TILE_EN (1 << 15) -# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) -#define RADEON_CRTC2_OFFSET 0x0324 -#define RADEON_CRTC2_OFFSET_CNTL 0x0328 - -#define RADEON_PCIE_INDEX 0x0030 -#define RADEON_PCIE_DATA 0x0034 -#define RADEON_PCIE_TX_GART_CNTL 0x10 -# define RADEON_PCIE_TX_GART_EN (1 << 0) -# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) -# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) -# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) -# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) -# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) -# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) -# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) -#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 -#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 -#define RADEON_PCIE_TX_GART_BASE 0x13 -#define RADEON_PCIE_TX_GART_START_LO 0x14 -#define RADEON_PCIE_TX_GART_START_HI 0x15 -#define RADEON_PCIE_TX_GART_END_LO 0x16 -#define RADEON_PCIE_TX_GART_END_HI 0x17 - -#define RS480_NB_MC_INDEX 0x168 -# define RS480_NB_MC_IND_WR_EN (1 << 8) -#define RS480_NB_MC_DATA 0x16c - -#define RS690_MC_INDEX 0x78 -# define RS690_MC_INDEX_MASK 0x1ff -# define RS690_MC_INDEX_WR_EN (1 << 9) -# define RS690_MC_INDEX_WR_ACK 0x7f -#define RS690_MC_DATA 0x7c - -/* MC indirect registers */ -#define RS480_MC_MISC_CNTL 0x18 -# define RS480_DISABLE_GTW (1 << 1) -/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ -# define RS480_GART_INDEX_REG_EN (1 << 12) -# define RS690_BLOCK_GFX_D3_EN (1 << 14) -#define RS480_K8_FB_LOCATION 0x1e -#define RS480_GART_FEATURE_ID 0x2b -# define RS480_HANG_EN (1 << 11) -# define RS480_TLB_ENABLE (1 << 18) -# define RS480_P2P_ENABLE (1 << 19) -# define RS480_GTW_LAC_EN (1 << 25) -# define RS480_2LEVEL_GART (0 << 30) -# define RS480_1LEVEL_GART (1 << 30) -# define RS480_PDC_EN (1 << 31) -#define RS480_GART_BASE 0x2c -#define RS480_GART_CACHE_CNTRL 0x2e -# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ -#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 -# define RS480_GART_EN (1 << 0) -# define RS480_VA_SIZE_32MB (0 << 1) -# define RS480_VA_SIZE_64MB (1 << 1) -# define RS480_VA_SIZE_128MB (2 << 1) -# define RS480_VA_SIZE_256MB (3 << 1) -# define RS480_VA_SIZE_512MB (4 << 1) -# define RS480_VA_SIZE_1GB (5 << 1) -# define RS480_VA_SIZE_2GB (6 << 1) -#define RS480_AGP_MODE_CNTL 0x39 -# define RS480_POST_GART_Q_SIZE (1 << 18) -# define RS480_NONGART_SNOOP (1 << 19) -# define RS480_AGP_RD_BUF_SIZE (1 << 20) -# define RS480_REQ_TYPE_SNOOP_SHIFT 22 -# define RS480_REQ_TYPE_SNOOP_MASK 0x3 -# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) -#define RS480_MC_MISC_UMA_CNTL 0x5f -#define RS480_MC_MCLK_CNTL 0x7a -#define RS480_MC_UMA_DUALCH_CNTL 0x86 - -#define RS690_MC_FB_LOCATION 0x100 -#define RS690_MC_AGP_LOCATION 0x101 -#define RS690_MC_AGP_BASE 0x102 -#define RS690_MC_AGP_BASE_2 0x103 - -#define R520_MC_IND_INDEX 0x70 -#define R520_MC_IND_WR_EN (1 << 24) -#define R520_MC_IND_DATA 0x74 - -#define RV515_MC_FB_LOCATION 0x01 -#define RV515_MC_AGP_LOCATION 0x02 -#define RV515_MC_AGP_BASE 0x03 -#define RV515_MC_AGP_BASE_2 0x04 - -#define R520_MC_FB_LOCATION 0x04 -#define R520_MC_AGP_LOCATION 0x05 -#define R520_MC_AGP_BASE 0x06 -#define R520_MC_AGP_BASE_2 0x07 - -#define RADEON_MPP_TB_CONFIG 0x01c0 -#define RADEON_MEM_CNTL 0x0140 -#define RADEON_MEM_SDRAM_MODE_REG 0x0158 -#define RADEON_AGP_BASE_2 0x015c /* r200+ only */ -#define RS480_AGP_BASE_2 0x0164 -#define RADEON_AGP_BASE 0x0170 - -/* pipe config regs */ -#define R400_GB_PIPE_SELECT 0x402c -#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ -#define R500_SU_REG_DEST 0x42c8 -#define R300_GB_TILE_CONFIG 0x4018 -# define R300_ENABLE_TILING (1 << 0) -# define R300_PIPE_COUNT_RV350 (0 << 1) -# define R300_PIPE_COUNT_R300 (3 << 1) -# define R300_PIPE_COUNT_R420_3P (6 << 1) -# define R300_PIPE_COUNT_R420 (7 << 1) -# define R300_TILE_SIZE_8 (0 << 4) -# define R300_TILE_SIZE_16 (1 << 4) -# define R300_TILE_SIZE_32 (2 << 4) -# define R300_SUBPIXEL_1_12 (0 << 16) -# define R300_SUBPIXEL_1_16 (1 << 16) -#define R300_DST_PIPE_CONFIG 0x170c -# define R300_PIPE_AUTO_CONFIG (1 << 31) -#define R300_RB2D_DSTCACHE_MODE 0x3428 -# define R300_DC_AUTOFLUSH_ENABLE (1 << 8) -# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) - -#define RADEON_RB3D_COLOROFFSET 0x1c40 -#define RADEON_RB3D_COLORPITCH 0x1c48 - -#define RADEON_SRC_X_Y 0x1590 - -#define RADEON_DP_GUI_MASTER_CNTL 0x146c -# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) -# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) -# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) -# define RADEON_GMC_BRUSH_NONE (15 << 4) -# define RADEON_GMC_DST_16BPP (4 << 8) -# define RADEON_GMC_DST_24BPP (5 << 8) -# define RADEON_GMC_DST_32BPP (6 << 8) -# define RADEON_GMC_DST_DATATYPE_SHIFT 8 -# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) -# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) -# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) -# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) -# define RADEON_GMC_WR_MSK_DIS (1 << 30) -# define RADEON_ROP3_S 0x00cc0000 -# define RADEON_ROP3_P 0x00f00000 -#define RADEON_DP_WRITE_MASK 0x16cc -#define RADEON_SRC_PITCH_OFFSET 0x1428 -#define RADEON_DST_PITCH_OFFSET 0x142c -#define RADEON_DST_PITCH_OFFSET_C 0x1c80 -# define RADEON_DST_TILE_LINEAR (0 << 30) -# define RADEON_DST_TILE_MACRO (1 << 30) -# define RADEON_DST_TILE_MICRO (2 << 30) -# define RADEON_DST_TILE_BOTH (3 << 30) - -#define RADEON_SCRATCH_REG0 0x15e0 -#define RADEON_SCRATCH_REG1 0x15e4 -#define RADEON_SCRATCH_REG2 0x15e8 -#define RADEON_SCRATCH_REG3 0x15ec -#define RADEON_SCRATCH_REG4 0x15f0 -#define RADEON_SCRATCH_REG5 0x15f4 -#define RADEON_SCRATCH_UMSK 0x0770 -#define RADEON_SCRATCH_ADDR 0x0774 - -#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) - -#define GET_SCRATCH( x ) (dev_priv->writeback_works \ - ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ - : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) - -#define RADEON_CRTC_CRNT_FRAME 0x0214 -#define RADEON_CRTC2_CRNT_FRAME 0x0314 - -#define RADEON_CRTC_STATUS 0x005c -#define RADEON_CRTC2_STATUS 0x03fc - -#define RADEON_GEN_INT_CNTL 0x0040 -# define RADEON_CRTC_VBLANK_MASK (1 << 0) -# define RADEON_CRTC2_VBLANK_MASK (1 << 9) -# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) -# define RADEON_SW_INT_ENABLE (1 << 25) - -#define RADEON_GEN_INT_STATUS 0x0044 -# define RADEON_CRTC_VBLANK_STAT (1 << 0) -# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) -# define RADEON_CRTC2_VBLANK_STAT (1 << 9) -# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) -# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) -# define RADEON_SW_INT_TEST (1 << 25) -# define RADEON_SW_INT_TEST_ACK (1 << 25) -# define RADEON_SW_INT_FIRE (1 << 26) -# define R500_DISPLAY_INT_STATUS (1 << 0) - - -#define RADEON_HOST_PATH_CNTL 0x0130 -# define RADEON_HDP_SOFT_RESET (1 << 26) -# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) -# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) - -#define RADEON_ISYNC_CNTL 0x1724 -# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) -# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) -# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) -# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) -# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) -# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) - -#define RADEON_RBBM_GUICNTL 0x172c -# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) -# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) -# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) -# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) - -#define RADEON_MC_AGP_LOCATION 0x014c -#define RADEON_MC_FB_LOCATION 0x0148 -#define RADEON_MCLK_CNTL 0x0012 -# define RADEON_FORCEON_MCLKA (1 << 16) -# define RADEON_FORCEON_MCLKB (1 << 17) -# define RADEON_FORCEON_YCLKA (1 << 18) -# define RADEON_FORCEON_YCLKB (1 << 19) -# define RADEON_FORCEON_MC (1 << 20) -# define RADEON_FORCEON_AIC (1 << 21) - -#define RADEON_PP_BORDER_COLOR_0 0x1d40 -#define RADEON_PP_BORDER_COLOR_1 0x1d44 -#define RADEON_PP_BORDER_COLOR_2 0x1d48 -#define RADEON_PP_CNTL 0x1c38 -# define RADEON_SCISSOR_ENABLE (1 << 1) -#define RADEON_PP_LUM_MATRIX 0x1d00 -#define RADEON_PP_MISC 0x1c14 -#define RADEON_PP_ROT_MATRIX_0 0x1d58 -#define RADEON_PP_TXFILTER_0 0x1c54 -#define RADEON_PP_TXOFFSET_0 0x1c5c -#define RADEON_PP_TXFILTER_1 0x1c6c -#define RADEON_PP_TXFILTER_2 0x1c84 - -#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ -#define R300_DSTCACHE_CTLSTAT 0x1714 -# define R300_RB2D_DC_FLUSH (3 << 0) -# define R300_RB2D_DC_FREE (3 << 2) -# define R300_RB2D_DC_FLUSH_ALL 0xf -# define R300_RB2D_DC_BUSY (1 << 31) -#define RADEON_RB3D_CNTL 0x1c3c -# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) -# define RADEON_PLANE_MASK_ENABLE (1 << 1) -# define RADEON_DITHER_ENABLE (1 << 2) -# define RADEON_ROUND_ENABLE (1 << 3) -# define RADEON_SCALE_DITHER_ENABLE (1 << 4) -# define RADEON_DITHER_INIT (1 << 5) -# define RADEON_ROP_ENABLE (1 << 6) -# define RADEON_STENCIL_ENABLE (1 << 7) -# define RADEON_Z_ENABLE (1 << 8) -# define RADEON_ZBLOCK16 (1 << 15) -#define RADEON_RB3D_DEPTHOFFSET 0x1c24 -#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 -#define RADEON_RB3D_DEPTHPITCH 0x1c28 -#define RADEON_RB3D_PLANEMASK 0x1d84 -#define RADEON_RB3D_STENCILREFMASK 0x1d7c -#define RADEON_RB3D_ZCACHE_MODE 0x3250 -#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 -# define RADEON_RB3D_ZC_FLUSH (1 << 0) -# define RADEON_RB3D_ZC_FREE (1 << 2) -# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 -# define RADEON_RB3D_ZC_BUSY (1 << 31) -#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 -# define R300_ZC_FLUSH (1 << 0) -# define R300_ZC_FREE (1 << 1) -# define R300_ZC_BUSY (1 << 31) -#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c -# define RADEON_RB3D_DC_FLUSH (3 << 0) -# define RADEON_RB3D_DC_FREE (3 << 2) -# define RADEON_RB3D_DC_FLUSH_ALL 0xf -# define RADEON_RB3D_DC_BUSY (1 << 31) -#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c -# define R300_RB3D_DC_FLUSH (2 << 0) -# define R300_RB3D_DC_FREE (2 << 2) -# define R300_RB3D_DC_FINISH (1 << 4) -#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c -# define RADEON_Z_TEST_MASK (7 << 4) -# define RADEON_Z_TEST_ALWAYS (7 << 4) -# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) -# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) -# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) -# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) -# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) -# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) -# define RADEON_FORCE_Z_DIRTY (1 << 29) -# define RADEON_Z_WRITE_ENABLE (1 << 30) -# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) -#define RADEON_RBBM_SOFT_RESET 0x00f0 -# define RADEON_SOFT_RESET_CP (1 << 0) -# define RADEON_SOFT_RESET_HI (1 << 1) -# define RADEON_SOFT_RESET_SE (1 << 2) -# define RADEON_SOFT_RESET_RE (1 << 3) -# define RADEON_SOFT_RESET_PP (1 << 4) -# define RADEON_SOFT_RESET_E2 (1 << 5) -# define RADEON_SOFT_RESET_RB (1 << 6) -# define RADEON_SOFT_RESET_HDP (1 << 7) -/* - * 6:0 Available slots in the FIFO - * 8 Host Interface active - * 9 CP request active - * 10 FIFO request active - * 11 Host Interface retry active - * 12 CP retry active - * 13 FIFO retry active - * 14 FIFO pipeline busy - * 15 Event engine busy - * 16 CP command stream busy - * 17 2D engine busy - * 18 2D portion of render backend busy - * 20 3D setup engine busy - * 26 GA engine busy - * 27 CBA 2D engine busy - * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or - * command stream queue not empty or Ring Buffer not empty - */ -#define RADEON_RBBM_STATUS 0x0e40 -/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */ -/* #define RADEON_RBBM_STATUS 0x1740 */ -/* bits 6:0 are dword slots available in the cmd fifo */ -# define RADEON_RBBM_FIFOCNT_MASK 0x007f -# define RADEON_HIRQ_ON_RBB (1 << 8) -# define RADEON_CPRQ_ON_RBB (1 << 9) -# define RADEON_CFRQ_ON_RBB (1 << 10) -# define RADEON_HIRQ_IN_RTBUF (1 << 11) -# define RADEON_CPRQ_IN_RTBUF (1 << 12) -# define RADEON_CFRQ_IN_RTBUF (1 << 13) -# define RADEON_PIPE_BUSY (1 << 14) -# define RADEON_ENG_EV_BUSY (1 << 15) -# define RADEON_CP_CMDSTRM_BUSY (1 << 16) -# define RADEON_E2_BUSY (1 << 17) -# define RADEON_RB2D_BUSY (1 << 18) -# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */ -# define RADEON_VAP_BUSY (1 << 20) -# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */ -# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */ -# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */ -# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */ -# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ -# define RADEON_GA_BUSY (1 << 26) -# define RADEON_CBA2D_BUSY (1 << 27) -# define RADEON_RBBM_ACTIVE (1 << 31) -#define RADEON_RE_LINE_PATTERN 0x1cd0 -#define RADEON_RE_MISC 0x26c4 -#define RADEON_RE_TOP_LEFT 0x26c0 -#define RADEON_RE_WIDTH_HEIGHT 0x1c44 -#define RADEON_RE_STIPPLE_ADDR 0x1cc8 -#define RADEON_RE_STIPPLE_DATA 0x1ccc - -#define RADEON_SCISSOR_TL_0 0x1cd8 -#define RADEON_SCISSOR_BR_0 0x1cdc -#define RADEON_SCISSOR_TL_1 0x1ce0 -#define RADEON_SCISSOR_BR_1 0x1ce4 -#define RADEON_SCISSOR_TL_2 0x1ce8 -#define RADEON_SCISSOR_BR_2 0x1cec -#define RADEON_SE_COORD_FMT 0x1c50 -#define RADEON_SE_CNTL 0x1c4c -# define RADEON_FFACE_CULL_CW (0 << 0) -# define RADEON_BFACE_SOLID (3 << 1) -# define RADEON_FFACE_SOLID (3 << 3) -# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) -# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) -# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) -# define RADEON_ALPHA_SHADE_FLAT (1 << 10) -# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) -# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) -# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) -# define RADEON_FOG_SHADE_FLAT (1 << 14) -# define RADEON_FOG_SHADE_GOURAUD (2 << 14) -# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) -# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) -# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) -# define RADEON_ROUND_MODE_TRUNC (0 << 28) -# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) -#define RADEON_SE_CNTL_STATUS 0x2140 -#define RADEON_SE_LINE_WIDTH 0x1db8 -#define RADEON_SE_VPORT_XSCALE 0x1d98 -#define RADEON_SE_ZBIAS_FACTOR 0x1db0 -#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 -#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 -#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 -# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 -# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 -#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 -#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 -# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 -#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C -#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 -#define RADEON_SURFACE_ACCESS_CLR 0x0bfc -#define RADEON_SURFACE_CNTL 0x0b00 -# define RADEON_SURF_TRANSLATION_DIS (1 << 8) -# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) -# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) -# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) -# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) -# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) -# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) -# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) -# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) -#define RADEON_SURFACE0_INFO 0x0b0c -# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) -# define RADEON_SURF_TILE_MODE_MASK (3 << 16) -# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) -# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) -# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) -# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) -#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 -#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 -# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) -#define RADEON_SURFACE1_INFO 0x0b1c -#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 -#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 -#define RADEON_SURFACE2_INFO 0x0b2c -#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 -#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 -#define RADEON_SURFACE3_INFO 0x0b3c -#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 -#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 -#define RADEON_SURFACE4_INFO 0x0b4c -#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 -#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 -#define RADEON_SURFACE5_INFO 0x0b5c -#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 -#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 -#define RADEON_SURFACE6_INFO 0x0b6c -#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 -#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 -#define RADEON_SURFACE7_INFO 0x0b7c -#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 -#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 -#define RADEON_SW_SEMAPHORE 0x013c - -#define RADEON_WAIT_UNTIL 0x1720 -# define RADEON_WAIT_CRTC_PFLIP (1 << 0) -# define RADEON_WAIT_2D_IDLE (1 << 14) -# define RADEON_WAIT_3D_IDLE (1 << 15) -# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) -# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) -# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) - -#define RADEON_RB3D_ZMASKOFFSET 0x3234 -#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c -# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) -# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) - -/* CP registers */ -#define RADEON_CP_ME_RAM_ADDR 0x07d4 -#define RADEON_CP_ME_RAM_RADDR 0x07d8 -#define RADEON_CP_ME_RAM_DATAH 0x07dc -#define RADEON_CP_ME_RAM_DATAL 0x07e0 - -#define RADEON_CP_RB_BASE 0x0700 -#define RADEON_CP_RB_CNTL 0x0704 -# define RADEON_BUF_SWAP_32BIT (2 << 16) -# define RADEON_RB_NO_UPDATE (1 << 27) -#define RADEON_CP_RB_RPTR_ADDR 0x070c -#define RADEON_CP_RB_RPTR 0x0710 -#define RADEON_CP_RB_WPTR 0x0714 - -#define RADEON_CP_RB_WPTR_DELAY 0x0718 -# define RADEON_PRE_WRITE_TIMER_SHIFT 0 -# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 - -#define RADEON_CP_IB_BASE 0x0738 - -#define RADEON_CP_CSQ_CNTL 0x0740 -# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) -# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) -# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) -# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) -# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) -# define RADEON_CSQ_PRIBM_INDBM (4 << 28) -# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) - -#define RADEON_AIC_CNTL 0x01d0 -# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) -# define RS400_MSI_REARM (1 << 3) -#define RADEON_AIC_STAT 0x01d4 -#define RADEON_AIC_PT_BASE 0x01d8 -#define RADEON_AIC_LO_ADDR 0x01dc -#define RADEON_AIC_HI_ADDR 0x01e0 -#define RADEON_AIC_TLB_ADDR 0x01e4 -#define RADEON_AIC_TLB_DATA 0x01e8 - -/* CP command packets */ -#define RADEON_CP_PACKET0 0x00000000 -# define RADEON_ONE_REG_WR (1 << 15) -#define RADEON_CP_PACKET1 0x40000000 -#define RADEON_CP_PACKET2 0x80000000 -#define RADEON_CP_PACKET3 0xC0000000 -# define RADEON_CP_NOP 0x00001000 -# define RADEON_CP_NEXT_CHAR 0x00001900 -# define RADEON_CP_PLY_NEXTSCAN 0x00001D00 -# define RADEON_CP_SET_SCISSORS 0x00001E00 - /* GEN_INDX_PRIM is unsupported starting with R300 */ -# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 -# define RADEON_WAIT_FOR_IDLE 0x00002600 -# define RADEON_3D_DRAW_VBUF 0x00002800 -# define RADEON_3D_DRAW_IMMD 0x00002900 -# define RADEON_3D_DRAW_INDX 0x00002A00 -# define RADEON_CP_LOAD_PALETTE 0x00002C00 -# define RADEON_3D_LOAD_VBPNTR 0x00002F00 -# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 -# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 -# define RADEON_3D_CLEAR_ZMASK 0x00003200 -# define RADEON_CP_INDX_BUFFER 0x00003300 -# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 -# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 -# define RADEON_CP_3D_DRAW_INDX_2 0x00003600 -# define RADEON_3D_CLEAR_HIZ 0x00003700 -# define RADEON_CP_3D_CLEAR_CMASK 0x00003802 -# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 -# define RADEON_CNTL_PAINT_MULTI 0x00009A00 -# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 -# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 - -#define RADEON_CP_PACKET_MASK 0xC0000000 -#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 -#define RADEON_CP_PACKET0_REG_MASK 0x000007ff -#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff -#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 - -#define RADEON_VTX_Z_PRESENT (1 << 31) -#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) - -#define RADEON_PRIM_TYPE_NONE (0 << 0) -#define RADEON_PRIM_TYPE_POINT (1 << 0) -#define RADEON_PRIM_TYPE_LINE (2 << 0) -#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) -#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) -#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) -#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) -#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) -#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) -#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) -#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) -#define RADEON_PRIM_TYPE_MASK 0xf -#define RADEON_PRIM_WALK_IND (1 << 4) -#define RADEON_PRIM_WALK_LIST (2 << 4) -#define RADEON_PRIM_WALK_RING (3 << 4) -#define RADEON_COLOR_ORDER_BGRA (0 << 6) -#define RADEON_COLOR_ORDER_RGBA (1 << 6) -#define RADEON_MAOS_ENABLE (1 << 7) -#define RADEON_VTX_FMT_R128_MODE (0 << 8) -#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) -#define RADEON_NUM_VERTICES_SHIFT 16 - -#define RADEON_COLOR_FORMAT_CI8 2 -#define RADEON_COLOR_FORMAT_ARGB1555 3 -#define RADEON_COLOR_FORMAT_RGB565 4 -#define RADEON_COLOR_FORMAT_ARGB8888 6 -#define RADEON_COLOR_FORMAT_RGB332 7 -#define RADEON_COLOR_FORMAT_RGB8 9 -#define RADEON_COLOR_FORMAT_ARGB4444 15 - -#define RADEON_TXFORMAT_I8 0 -#define RADEON_TXFORMAT_AI88 1 -#define RADEON_TXFORMAT_RGB332 2 -#define RADEON_TXFORMAT_ARGB1555 3 -#define RADEON_TXFORMAT_RGB565 4 -#define RADEON_TXFORMAT_ARGB4444 5 -#define RADEON_TXFORMAT_ARGB8888 6 -#define RADEON_TXFORMAT_RGBA8888 7 -#define RADEON_TXFORMAT_Y8 8 -#define RADEON_TXFORMAT_VYUY422 10 -#define RADEON_TXFORMAT_YVYU422 11 -#define RADEON_TXFORMAT_DXT1 12 -#define RADEON_TXFORMAT_DXT23 14 -#define RADEON_TXFORMAT_DXT45 15 - -#define R200_PP_TXCBLEND_0 0x2f00 -#define R200_PP_TXCBLEND_1 0x2f10 -#define R200_PP_TXCBLEND_2 0x2f20 -#define R200_PP_TXCBLEND_3 0x2f30 -#define R200_PP_TXCBLEND_4 0x2f40 -#define R200_PP_TXCBLEND_5 0x2f50 -#define R200_PP_TXCBLEND_6 0x2f60 -#define R200_PP_TXCBLEND_7 0x2f70 -#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 -#define R200_PP_TFACTOR_0 0x2ee0 -#define R200_SE_VTX_FMT_0 0x2088 -#define R200_SE_VAP_CNTL 0x2080 -#define R200_SE_TCL_MATRIX_SEL_0 0x2230 -#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 -#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 -#define R200_PP_TXFILTER_5 0x2ca0 -#define R200_PP_TXFILTER_4 0x2c80 -#define R200_PP_TXFILTER_3 0x2c60 -#define R200_PP_TXFILTER_2 0x2c40 -#define R200_PP_TXFILTER_1 0x2c20 -#define R200_PP_TXFILTER_0 0x2c00 -#define R200_PP_TXOFFSET_5 0x2d78 -#define R200_PP_TXOFFSET_4 0x2d60 -#define R200_PP_TXOFFSET_3 0x2d48 -#define R200_PP_TXOFFSET_2 0x2d30 -#define R200_PP_TXOFFSET_1 0x2d18 -#define R200_PP_TXOFFSET_0 0x2d00 - -#define R200_PP_CUBIC_FACES_0 0x2c18 -#define R200_PP_CUBIC_FACES_1 0x2c38 -#define R200_PP_CUBIC_FACES_2 0x2c58 -#define R200_PP_CUBIC_FACES_3 0x2c78 -#define R200_PP_CUBIC_FACES_4 0x2c98 -#define R200_PP_CUBIC_FACES_5 0x2cb8 -#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 -#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 -#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c -#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 -#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 -#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c -#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 -#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 -#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 -#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c -#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 -#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 -#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c -#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 -#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 -#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c -#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 -#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 -#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 -#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c -#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 -#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 -#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c -#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 -#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 -#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c -#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 -#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 -#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 -#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c - -#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 -#define R200_SE_VTE_CNTL 0x20b0 -#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 -#define R200_PP_TAM_DEBUG3 0x2d9c -#define R200_PP_CNTL_X 0x2cc4 -#define R200_SE_VAP_CNTL_STATUS 0x2140 -#define R200_RE_SCISSOR_TL_0 0x1cd8 -#define R200_RE_SCISSOR_TL_1 0x1ce0 -#define R200_RE_SCISSOR_TL_2 0x1ce8 -#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 -#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 -#define R200_SE_VTX_STATE_CNTL 0x2180 -#define R200_RE_POINTSIZE 0x2648 -#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 - -#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ -#define RADEON_PP_TEX_SIZE_1 0x1d0c -#define RADEON_PP_TEX_SIZE_2 0x1d14 - -#define RADEON_PP_CUBIC_FACES_0 0x1d24 -#define RADEON_PP_CUBIC_FACES_1 0x1d28 -#define RADEON_PP_CUBIC_FACES_2 0x1d2c -#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ -#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 -#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 - -#define RADEON_SE_TCL_STATE_FLUSH 0x2284 - -#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 -#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 -#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 -#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 -#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 -#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 -#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 -#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b -#define R200_3D_DRAW_IMMD_2 0xC0003500 -#define R200_SE_VTX_FMT_1 0x208c -#define R200_RE_CNTL 0x1c50 - -#define R200_RB3D_BLENDCOLOR 0x3218 - -#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 - -#define R200_PP_TRI_PERF 0x2cf8 - -#define R200_PP_AFS_0 0x2f80 -#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ - -#define R200_VAP_PVS_CNTL_1 0x22D0 - -/* MPEG settings from VHA code */ -#define RADEON_VHA_SETTO16_1 0x2694 -#define RADEON_VHA_SETTO16_2 0x2680 -#define RADEON_VHA_SETTO0_1 0x1840 -#define RADEON_VHA_FB_OFFSET 0x19e4 -#define RADEON_VHA_SETTO1AND70S 0x19d8 -#define RADEON_VHA_DST_PITCH 0x1408 - -// set as reference header -#define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840 -#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844 -#define RADEON_VHA_BACKFRAME0_OFF_U 0x1848 -#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c -#define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850 -#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854 -#define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858 -#define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c -#define RADEON_VHA_FORWFRAME0_OFF_U 0x1860 -#define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864 -#define RADEON_VHA_FORWFRAME0_OFF_V 0x1868 -#define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880 -#define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884 -#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888 -#define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c -#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890 -#define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894 -#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898 - -#define R500_D1CRTC_STATUS 0x609c -#define R500_D2CRTC_STATUS 0x689c -#define R500_CRTC_V_BLANK (1<<0) - -#define R500_D1CRTC_FRAME_COUNT 0x60a4 -#define R500_D2CRTC_FRAME_COUNT 0x68a4 - -#define R500_D1MODE_V_COUNTER 0x6530 -#define R500_D2MODE_V_COUNTER 0x6d30 - -#define R500_D1MODE_VBLANK_STATUS 0x6534 -#define R500_D2MODE_VBLANK_STATUS 0x6d34 -#define R500_VBLANK_OCCURED (1<<0) -#define R500_VBLANK_ACK (1<<4) -#define R500_VBLANK_STAT (1<<12) -#define R500_VBLANK_INT (1<<16) - -#define R500_DxMODE_INT_MASK 0x6540 -#define R500_D1MODE_INT_MASK (1<<0) -#define R500_D2MODE_INT_MASK (1<<8) - -#define R500_DISP_INTERRUPT_STATUS 0x7edc -#define R500_D1_VBLANK_INTERRUPT (1 << 4) -#define R500_D2_VBLANK_INTERRUPT (1 << 5) - -/* Constants */ -#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ - -#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 -#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 -#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 -#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 -#define RADEON_LAST_DISPATCH 1 - -#define RADEON_MAX_VB_AGE 0x7fffffff -#define RADEON_MAX_VB_VERTS (0xffff) - -#define RADEON_RING_HIGH_MARK 128 - -#define RADEON_PCIGART_TABLE_SIZE (32*1024) - -#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) -#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) -#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) -#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) - -#define RADEON_WRITE_PLL( addr, val ) \ -do { \ - RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ - ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ - RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ -} while (0) - -#define RADEON_WRITE_PCIE( addr, val ) \ -do { \ - RADEON_WRITE8( RADEON_PCIE_INDEX, \ - ((addr) & 0xff)); \ - RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ -} while (0) - -#define R500_WRITE_MCIND( addr, val ) \ -do { \ - RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ - RADEON_WRITE(R520_MC_IND_DATA, (val)); \ - RADEON_WRITE(R520_MC_IND_INDEX, 0); \ -} while (0) - -#define RS480_WRITE_MCIND( addr, val ) \ -do { \ - RADEON_WRITE( RS480_NB_MC_INDEX, \ - ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ - RADEON_WRITE( RS480_NB_MC_DATA, (val) ); \ - RADEON_WRITE( RS480_NB_MC_INDEX, 0xff ); \ -} while (0) - -#define RS690_WRITE_MCIND( addr, val ) \ -do { \ - RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ - RADEON_WRITE(RS690_MC_DATA, val); \ - RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ -} while (0) - -#define IGP_WRITE_MCIND( addr, val ) \ -do { \ - if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \ - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \ - RS690_WRITE_MCIND( addr, val ); \ - else \ - RS480_WRITE_MCIND( addr, val ); \ -} while (0) - -#define CP_PACKET0( reg, n ) \ - (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) -#define CP_PACKET0_TABLE( reg, n ) \ - (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) -#define CP_PACKET1( reg0, reg1 ) \ - (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) -#define CP_PACKET2() \ - (RADEON_CP_PACKET2) -#define CP_PACKET3( pkt, n ) \ - (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) - -/* ================================================================ - * Engine control helper macros - */ - -#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ - OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ - OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ - RADEON_WAIT_HOST_IDLECLEAN) ); \ -} while (0) - -#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ - OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ - OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ - RADEON_WAIT_HOST_IDLECLEAN) ); \ -} while (0) - -#define RADEON_WAIT_UNTIL_IDLE() do { \ - OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ - OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ - RADEON_WAIT_3D_IDLECLEAN | \ - RADEON_WAIT_HOST_IDLECLEAN) ); \ -} while (0) - -#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ - OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ - OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ -} while (0) - -#define RADEON_FLUSH_CACHE() do { \ - if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ - OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ - OUT_RING(RADEON_RB3D_DC_FLUSH); \ - } else { \ - OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ - OUT_RING(R300_RB3D_DC_FLUSH); \ - } \ -} while (0) - -#define RADEON_PURGE_CACHE() do { \ - if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ - OUT_RING(CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ - OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ - } else { \ - OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ - OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE ); \ - } \ -} while (0) - -#define RADEON_FLUSH_ZCACHE() do { \ - if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ - OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ - OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ - } else { \ - OUT_RING( CP_PACKET0( R300_ZB_ZCACHE_CTLSTAT, 0 ) ); \ - OUT_RING( R300_ZC_FLUSH ); \ - } \ -} while (0) - -#define RADEON_PURGE_ZCACHE() do { \ - if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ - OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ - OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ - } else { \ - OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ - OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ - } \ -} while (0) - -/* ================================================================ - * Misc helper macros - */ - -/* Perfbox functionality only. - */ -#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ -do { \ - if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ - u32 head = GET_RING_HEAD( dev_priv ); \ - if (head == dev_priv->ring.tail) \ - dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ - } \ -} while (0) - -#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ -do { \ - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ - if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ - int __ret = radeon_do_cp_idle( dev_priv ); \ - if ( __ret ) return __ret; \ - sarea_priv->last_dispatch = 0; \ - radeon_freelist_reset( dev ); \ - } \ -} while (0) - -#define RADEON_DISPATCH_AGE( age ) do { \ - OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ - OUT_RING( age ); \ -} while (0) - -#define RADEON_FRAME_AGE( age ) do { \ - OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ - OUT_RING( age ); \ -} while (0) - -#define RADEON_CLEAR_AGE( age ) do { \ - OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ - OUT_RING( age ); \ -} while (0) - -/* ================================================================ - * Ring control - */ - -#define RADEON_VERBOSE 0 - -#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; - -#define BEGIN_RING( n ) do { \ - if ( RADEON_VERBOSE ) { \ - DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ - } \ - if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ - COMMIT_RING(); \ - radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ - } \ - _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ - ring = dev_priv->ring.start; \ - write = dev_priv->ring.tail; \ - mask = dev_priv->ring.tail_mask; \ -} while (0) - -#define ADVANCE_RING() do { \ - if ( RADEON_VERBOSE ) { \ - DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ - write, dev_priv->ring.tail ); \ - } \ - if (((dev_priv->ring.tail + _nr) & mask) != write) { \ - DRM_ERROR( \ - "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ - ((dev_priv->ring.tail + _nr) & mask), \ - write, __LINE__); \ - } else \ - dev_priv->ring.tail = write; \ -} while (0) - -#define COMMIT_RING() do { \ - /* Flush writes to ring */ \ - DRM_MEMORYBARRIER(); \ - GET_RING_HEAD( dev_priv ); \ - RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ - /* read from PCI bus to ensure correct posting */ \ - RADEON_READ( RADEON_CP_RB_RPTR ); \ -} while (0) - -#define OUT_RING( x ) do { \ - if ( RADEON_VERBOSE ) { \ - DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ - (unsigned int)(x), write ); \ - } \ - ring[write++] = (x); \ - write &= mask; \ -} while (0) - -#define OUT_RING_REG( reg, val ) do { \ - OUT_RING( CP_PACKET0( reg, 0 ) ); \ - OUT_RING( val ); \ -} while (0) - -#define OUT_RING_TABLE( tab, sz ) do { \ - int _size = (sz); \ - int *_tab = (int *)(tab); \ - \ - if (write + _size > mask) { \ - int _i = (mask+1) - write; \ - _size -= _i; \ - while (_i > 0) { \ - *(int *)(ring + write) = *_tab++; \ - write++; \ - _i--; \ - } \ - write = 0; \ - _tab += _i; \ - } \ - while (_size > 0) { \ - *(ring + write) = *_tab++; \ - write++; \ - _size--; \ - } \ - write &= mask; \ -} while (0) - -#endif /* __RADEON_DRV_H__ */ diff --git a/shared-core/radeon_irq.c b/shared-core/radeon_irq.c deleted file mode 100644 index 60654b2c..00000000 --- a/shared-core/radeon_irq.c +++ /dev/null @@ -1,415 +0,0 @@ -/* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */ -/* - * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * - * The Weather Channel (TM) funded Tungsten Graphics to develop the - * initial release of the Radeon 8500 driver under the XFree86 license. - * This notice must be preserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Keith Whitwell - * Michel D�zer - */ - -#include "drmP.h" -#include "drm.h" -#include "radeon_drm.h" -#include "radeon_drv.h" - -void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - - if (state) - dev_priv->irq_enable_reg |= mask; - else - dev_priv->irq_enable_reg &= ~mask; - - if (dev->irq_enabled) - RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); -} - -static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - - if (state) - dev_priv->r500_disp_irq_reg |= mask; - else - dev_priv->r500_disp_irq_reg &= ~mask; - - if (dev->irq_enabled) - RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); -} - -int radeon_enable_vblank(struct drm_device *dev, int crtc) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - - if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) { - switch (crtc) { - case 0: - r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1); - break; - case 1: - r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1); - break; - default: - DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", - crtc); - return EINVAL; - } - } else { - switch (crtc) { - case 0: - radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1); - break; - case 1: - radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1); - break; - default: - DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", - crtc); - return EINVAL; - } - } - - return 0; -} - -void radeon_disable_vblank(struct drm_device *dev, int crtc) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - - if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) { - switch (crtc) { - case 0: - r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0); - break; - case 1: - r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0); - break; - default: - DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", - crtc); - break; - } - } else { - switch (crtc) { - case 0: - radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0); - break; - case 1: - radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0); - break; - default: - DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", - crtc); - break; - } - } -} - -static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, u32 *r500_disp_int) -{ - u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS); - u32 irq_mask = RADEON_SW_INT_TEST; - - *r500_disp_int = 0; - if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) { - /* vbl interrupts in a different place */ - - if (irqs & R500_DISPLAY_INT_STATUS) { - /* if a display interrupt */ - u32 disp_irq; - - disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS); - - *r500_disp_int = disp_irq; - if (disp_irq & R500_D1_VBLANK_INTERRUPT) { - RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK); - } - if (disp_irq & R500_D2_VBLANK_INTERRUPT) { - RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK); - } - } - irq_mask |= R500_DISPLAY_INT_STATUS; - } else - irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT; - - irqs &= irq_mask; - - if (irqs) - RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs); - - return irqs; -} - -/* Interrupts - Used for device synchronization and flushing in the - * following circumstances: - * - * - Exclusive FB access with hw idle: - * - Wait for GUI Idle (?) interrupt, then do normal flush. - * - * - Frame throttling, NV_fence: - * - Drop marker irq's into command stream ahead of time. - * - Wait on irq's with lock *not held* - * - Check each for termination condition - * - * - Internally in cp_getbuffer, etc: - * - as above, but wait with lock held??? - * - * NOTE: These functions are misleadingly named -- the irq's aren't - * tied to dma at all, this is just a hangover from dri prehistory. - */ - -irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS) -{ - struct drm_device *dev = (struct drm_device *) arg; - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *) dev->dev_private; - u32 stat; - u32 r500_disp_int; - u32 tmp; - - /* Only consider the bits we're interested in - others could be used - * outside the DRM - */ - stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int); - if (!stat) - return IRQ_NONE; - - stat &= dev_priv->irq_enable_reg; - - /* SW interrupt */ - if (stat & RADEON_SW_INT_TEST) - DRM_WAKEUP(&dev_priv->swi_queue); - - /* VBLANK interrupt */ - if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) { - if (r500_disp_int & R500_D1_VBLANK_INTERRUPT) - drm_handle_vblank(dev, 0); - if (r500_disp_int & R500_D2_VBLANK_INTERRUPT) - drm_handle_vblank(dev, 1); - } else { - if (stat & RADEON_CRTC_VBLANK_STAT) - drm_handle_vblank(dev, 0); - if (stat & RADEON_CRTC2_VBLANK_STAT) - drm_handle_vblank(dev, 1); - } - if (dev->msi_enabled) { - switch(dev_priv->flags & RADEON_FAMILY_MASK) { - case CHIP_RS400: - case CHIP_RS480: - tmp = RADEON_READ(RADEON_AIC_CNTL) & - ~RS400_MSI_REARM; - RADEON_WRITE(RADEON_AIC_CNTL, tmp); - RADEON_WRITE(RADEON_AIC_CNTL, - tmp | RS400_MSI_REARM); - break; - case CHIP_RS690: - case CHIP_RS740: - tmp = RADEON_READ(RADEON_BUS_CNTL) & - ~RS600_MSI_REARM; - RADEON_WRITE(RADEON_BUS_CNTL, tmp); - RADEON_WRITE(RADEON_BUS_CNTL, tmp | - RS600_MSI_REARM); - break; - default: - tmp = RADEON_READ(RADEON_MSI_REARM_EN) & - ~RV370_MSI_REARM_EN; - RADEON_WRITE(RADEON_MSI_REARM_EN, tmp); - RADEON_WRITE(RADEON_MSI_REARM_EN, - tmp | RV370_MSI_REARM_EN); - break; - } - } - return IRQ_HANDLED; -} - -static int radeon_emit_irq(struct drm_device * dev) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - unsigned int ret; - RING_LOCALS; - - atomic_inc(&dev_priv->swi_emitted); - ret = atomic_read(&dev_priv->swi_emitted); - - BEGIN_RING(4); - OUT_RING_REG(RADEON_LAST_SWI_REG, ret); - OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE); - ADVANCE_RING(); - COMMIT_RING(); - - return ret; -} - -static int radeon_wait_irq(struct drm_device * dev, int swi_nr) -{ - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *) dev->dev_private; - int ret = 0; - - if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr) - return 0; - - dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - - DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ, - RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr); - - return ret; -} - -u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - if (crtc < 0 || crtc > 1) { - DRM_ERROR("Invalid crtc %d\n", crtc); - return -EINVAL; - } - - if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) { - if (crtc == 0) - return RADEON_READ(R500_D1CRTC_FRAME_COUNT); - else - return RADEON_READ(R500_D2CRTC_FRAME_COUNT); - } else { - if (crtc == 0) - return RADEON_READ(RADEON_CRTC_CRNT_FRAME); - else - return RADEON_READ(RADEON_CRTC2_CRNT_FRAME); - } -} - -/* Needs the lock as it touches the ring. - */ -int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_irq_emit_t *emit = data; - int result; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - result = radeon_emit_irq(dev); - - if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { - DRM_ERROR("copy_to_user\n"); - return -EFAULT; - } - - return 0; -} - -/* Doesn't need the hardware lock. - */ -int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_irq_wait_t *irqwait = data; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - return radeon_wait_irq(dev, irqwait->irq_seq); -} - -/* drm_dma.h hooks -*/ -void radeon_driver_irq_preinstall(struct drm_device * dev) -{ - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *) dev->dev_private; - u32 dummy; - - /* Disable *all* interrupts */ - if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) - RADEON_WRITE(R500_DxMODE_INT_MASK, 0); - RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); - - /* Clear bits if they're already high */ - radeon_acknowledge_irqs(dev_priv, &dummy); -} - -int radeon_driver_irq_postinstall(struct drm_device * dev) -{ - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *) dev->dev_private; - - atomic_set(&dev_priv->swi_emitted, 0); - DRM_INIT_WAITQUEUE(&dev_priv->swi_queue); - - dev->max_vblank_count = 0x001fffff; - - radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); - - return 0; -} - -void radeon_driver_irq_uninstall(struct drm_device * dev) -{ - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *) dev->dev_private; - if (!dev_priv) - return; - - dev_priv->irq_enabled = 0; - - if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) - RADEON_WRITE(R500_DxMODE_INT_MASK, 0); - /* Disable *all* interrupts */ - RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); -} - - -int radeon_vblank_crtc_get(struct drm_device *dev) -{ - drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; - - return dev_priv->vblank_crtc; -} - -int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value) -{ - drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; - if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) { - DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value); - return -EINVAL; - } - dev_priv->vblank_crtc = (unsigned int)value; - return 0; -} diff --git a/shared-core/radeon_mem.c b/shared-core/radeon_mem.c deleted file mode 100644 index dbd73c50..00000000 --- a/shared-core/radeon_mem.c +++ /dev/null @@ -1,302 +0,0 @@ -/* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*- */ -/* - * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * - * The Weather Channel (TM) funded Tungsten Graphics to develop the - * initial release of the Radeon 8500 driver under the XFree86 license. - * This notice must be preserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Keith Whitwell - */ - -#include "drmP.h" -#include "drm.h" -#include "radeon_drm.h" -#include "radeon_drv.h" - -/* Very simple allocator for GART memory, working on a static range - * already mapped into each client's address space. - */ - -static struct mem_block *split_block(struct mem_block *p, int start, int size, - struct drm_file *file_priv) -{ - /* Maybe cut off the start of an existing block */ - if (start > p->start) { - struct mem_block *newblock = - drm_alloc(sizeof(*newblock), DRM_MEM_BUFS); - if (!newblock) - goto out; - newblock->start = start; - newblock->size = p->size - (start - p->start); - newblock->file_priv = NULL; - newblock->next = p->next; - newblock->prev = p; - p->next->prev = newblock; - p->next = newblock; - p->size -= newblock->size; - p = newblock; - } - - /* Maybe cut off the end of an existing block */ - if (size < p->size) { - struct mem_block *newblock = - drm_alloc(sizeof(*newblock), DRM_MEM_BUFS); - if (!newblock) - goto out; - newblock->start = start + size; - newblock->size = p->size - size; - newblock->file_priv = NULL; - newblock->next = p->next; - newblock->prev = p; - p->next->prev = newblock; - p->next = newblock; - p->size = size; - } - - out: - /* Our block is in the middle */ - p->file_priv = file_priv; - return p; -} - -static struct mem_block *alloc_block(struct mem_block *heap, int size, - int align2, struct drm_file *file_priv) -{ - struct mem_block *p; - int mask = (1 << align2) - 1; - - list_for_each(p, heap) { - int start = (p->start + mask) & ~mask; - if (p->file_priv == NULL && start + size <= p->start + p->size) - return split_block(p, start, size, file_priv); - } - - return NULL; -} - -static struct mem_block *find_block(struct mem_block *heap, int start) -{ - struct mem_block *p; - - list_for_each(p, heap) - if (p->start == start) - return p; - - return NULL; -} - -static void free_block(struct mem_block *p) -{ - p->file_priv = NULL; - - /* Assumes a single contiguous range. Needs a special file_priv in - * 'heap' to stop it being subsumed. - */ - if (p->next->file_priv == NULL) { - struct mem_block *q = p->next; - p->size += q->size; - p->next = q->next; - p->next->prev = p; - drm_free(q, sizeof(*q), DRM_MEM_BUFS); - } - - if (p->prev->file_priv == NULL) { - struct mem_block *q = p->prev; - q->size += p->size; - q->next = p->next; - q->next->prev = q; - drm_free(p, sizeof(*q), DRM_MEM_BUFS); - } -} - -/* Initialize. How to check for an uninitialized heap? - */ -static int init_heap(struct mem_block **heap, int start, int size) -{ - struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFS); - - if (!blocks) - return -ENOMEM; - - *heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFS); - if (!*heap) { - drm_free(blocks, sizeof(*blocks), DRM_MEM_BUFS); - return -ENOMEM; - } - - blocks->start = start; - blocks->size = size; - blocks->file_priv = NULL; - blocks->next = blocks->prev = *heap; - - memset(*heap, 0, sizeof(**heap)); - (*heap)->file_priv = (struct drm_file *) - 1; - (*heap)->next = (*heap)->prev = blocks; - return 0; -} - -/* Free all blocks associated with the releasing file. - */ -void radeon_mem_release(struct drm_file *file_priv, struct mem_block *heap) -{ - struct mem_block *p; - - if (!heap || !heap->next) - return; - - list_for_each(p, heap) { - if (p->file_priv == file_priv) - p->file_priv = NULL; - } - - /* Assumes a single contiguous range. Needs a special file_priv in - * 'heap' to stop it being subsumed. - */ - list_for_each(p, heap) { - while (p->file_priv == NULL && p->next->file_priv == NULL) { - struct mem_block *q = p->next; - p->size += q->size; - p->next = q->next; - p->next->prev = p; - drm_free(q, sizeof(*q), DRM_MEM_DRIVER); - } - } -} - -/* Shutdown. - */ -void radeon_mem_takedown(struct mem_block **heap) -{ - struct mem_block *p; - - if (!*heap) - return; - - for (p = (*heap)->next; p != *heap;) { - struct mem_block *q = p; - p = p->next; - drm_free(q, sizeof(*q), DRM_MEM_DRIVER); - } - - drm_free(*heap, sizeof(**heap), DRM_MEM_DRIVER); - *heap = NULL; -} - -/* IOCTL HANDLERS */ - -static struct mem_block **get_heap(drm_radeon_private_t * dev_priv, int region) -{ - switch (region) { - case RADEON_MEM_REGION_GART: - return &dev_priv->gart_heap; - case RADEON_MEM_REGION_FB: - return &dev_priv->fb_heap; - default: - return NULL; - } -} - -int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_mem_alloc_t *alloc = data; - struct mem_block *block, **heap; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - heap = get_heap(dev_priv, alloc->region); - if (!heap || !*heap) - return -EFAULT; - - /* Make things easier on ourselves: all allocations at least - * 4k aligned. - */ - if (alloc->alignment < 12) - alloc->alignment = 12; - - block = alloc_block(*heap, alloc->size, alloc->alignment, file_priv); - - if (!block) - return -ENOMEM; - - if (DRM_COPY_TO_USER(alloc->region_offset, &block->start, - sizeof(int))) { - DRM_ERROR("copy_to_user\n"); - return -EFAULT; - } - - return 0; -} - -int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_mem_free_t *memfree = data; - struct mem_block *block, **heap; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - heap = get_heap(dev_priv, memfree->region); - if (!heap || !*heap) - return -EFAULT; - - block = find_block(*heap, memfree->region_offset); - if (!block) - return -EFAULT; - - if (block->file_priv != file_priv) - return -EPERM; - - free_block(block); - return 0; -} - -int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_mem_init_heap_t *initheap = data; - struct mem_block **heap; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - heap = get_heap(dev_priv, initheap->region); - if (!heap) - return -EFAULT; - - if (*heap) { - DRM_ERROR("heap already initialized?"); - return -EFAULT; - } - - return init_heap(heap, initheap->start, initheap->size); -} diff --git a/shared-core/radeon_microcode.h b/shared-core/radeon_microcode.h deleted file mode 100644 index a50b58ea..00000000 --- a/shared-core/radeon_microcode.h +++ /dev/null @@ -1,1844 +0,0 @@ -/* - * Copyright 2007 Advanced Micro Devices, Inc. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef RADEON_MICROCODE_H -#define RADEON_MICROCODE_H - -/* production radeon ucode r1xx-r6xx */ -static const u32 R100_cp_microcode[][2]={ - { 0x21007000, 0000000000 }, - { 0x20007000, 0000000000 }, - { 0x000000b4, 0x00000004 }, - { 0x000000b8, 0x00000004 }, - { 0x6f5b4d4c, 0000000000 }, - { 0x4c4c427f, 0000000000 }, - { 0x5b568a92, 0000000000 }, - { 0x4ca09c6d, 0000000000 }, - { 0xad4c4c4c, 0000000000 }, - { 0x4ce1af3d, 0000000000 }, - { 0xd8afafaf, 0000000000 }, - { 0xd64c4cdc, 0000000000 }, - { 0x4cd10d10, 0000000000 }, - { 0x000f0000, 0x00000016 }, - { 0x362f242d, 0000000000 }, - { 0x00000012, 0x00000004 }, - { 0x000f0000, 0x00000016 }, - { 0x362f282d, 0000000000 }, - { 0x000380e7, 0x00000002 }, - { 0x04002c97, 0x00000002 }, - { 0x000f0001, 0x00000016 }, - { 0x333a3730, 0000000000 }, - { 0x000077ef, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000021, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000021, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000021, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00000017, 0x00000004 }, - { 0x0003802b, 0x00000002 }, - { 0x040067e0, 0x00000002 }, - { 0x00000017, 0x00000004 }, - { 0x000077e0, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x000037e1, 0x00000002 }, - { 0x040067e1, 0x00000006 }, - { 0x000077e0, 0x00000002 }, - { 0x000077e1, 0x00000002 }, - { 0x000077e1, 0x00000006 }, - { 0xffffffff, 0000000000 }, - { 0x10000000, 0000000000 }, - { 0x0003802b, 0x00000002 }, - { 0x040067e0, 0x00000006 }, - { 0x00007675, 0x00000002 }, - { 0x00007676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0003802c, 0x00000002 }, - { 0x04002676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0000002f, 0x00000018 }, - { 0x0000002f, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x00000030, 0x00000018 }, - { 0x00000030, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x01605000, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00098000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x64c0603e, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00080000, 0x00000016 }, - { 0000000000, 0000000000 }, - { 0x0400251d, 0x00000002 }, - { 0x00007580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x04002580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x00000049, 0x00000004 }, - { 0x00005000, 0000000000 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x00019000, 0x00000002 }, - { 0x00011055, 0x00000014 }, - { 0x00000055, 0x00000012 }, - { 0x0400250f, 0x00000002 }, - { 0x0000504f, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00007565, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x00000058, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x01e655b4, 0x00000002 }, - { 0x4401b0e4, 0x00000002 }, - { 0x01c110e4, 0x00000002 }, - { 0x26667066, 0x00000018 }, - { 0x040c2565, 0x00000002 }, - { 0x00000066, 0x00000018 }, - { 0x04002564, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x0000005d, 0x00000004 }, - { 0x00401069, 0x00000008 }, - { 0x00101000, 0x00000002 }, - { 0x000d80ff, 0x00000002 }, - { 0x0080006c, 0x00000008 }, - { 0x000f9000, 0x00000002 }, - { 0x000e00ff, 0x00000002 }, - { 0000000000, 0x00000006 }, - { 0x0000008f, 0x00000018 }, - { 0x0000005b, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00007576, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00009000, 0x00000002 }, - { 0x00041000, 0x00000002 }, - { 0x0c00350e, 0x00000002 }, - { 0x00049000, 0x00000002 }, - { 0x00051000, 0x00000002 }, - { 0x01e785f8, 0x00000002 }, - { 0x00200000, 0x00000002 }, - { 0x0060007e, 0x0000000c }, - { 0x00007563, 0x00000002 }, - { 0x006075f0, 0x00000021 }, - { 0x20007073, 0x00000004 }, - { 0x00005073, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00007576, 0x00000002 }, - { 0x00007577, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x0000750f, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00600083, 0x0000000c }, - { 0x006075f0, 0x00000021 }, - { 0x000075f8, 0x00000002 }, - { 0x00000083, 0x00000004 }, - { 0x000a750e, 0x00000002 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x0020750f, 0x00000002 }, - { 0x00600086, 0x00000004 }, - { 0x00007570, 0x00000002 }, - { 0x00007571, 0x00000002 }, - { 0x00007572, 0x00000006 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00005000, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00007568, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000095, 0x0000000c }, - { 0x00058000, 0x00000002 }, - { 0x0c607562, 0x00000002 }, - { 0x00000097, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00600096, 0x00000004 }, - { 0x400070e5, 0000000000 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x000380e5, 0x00000002 }, - { 0x000000a8, 0x0000001c }, - { 0x000650aa, 0x00000018 }, - { 0x040025bb, 0x00000002 }, - { 0x000610ab, 0x00000018 }, - { 0x040075bc, 0000000000 }, - { 0x000075bb, 0x00000002 }, - { 0x000075bc, 0000000000 }, - { 0x00090000, 0x00000006 }, - { 0x00090000, 0x00000002 }, - { 0x000d8002, 0x00000006 }, - { 0x00007832, 0x00000002 }, - { 0x00005000, 0x00000002 }, - { 0x000380e7, 0x00000002 }, - { 0x04002c97, 0x00000002 }, - { 0x00007820, 0x00000002 }, - { 0x00007821, 0x00000002 }, - { 0x00007800, 0000000000 }, - { 0x01200000, 0x00000002 }, - { 0x20077000, 0x00000002 }, - { 0x01200000, 0x00000002 }, - { 0x20007000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x0120751b, 0x00000002 }, - { 0x8040750a, 0x00000002 }, - { 0x8040750b, 0x00000002 }, - { 0x00110000, 0x00000002 }, - { 0x000380e5, 0x00000002 }, - { 0x000000c6, 0x0000001c }, - { 0x000610ab, 0x00000018 }, - { 0x844075bd, 0x00000002 }, - { 0x000610aa, 0x00000018 }, - { 0x840075bb, 0x00000002 }, - { 0x000610ab, 0x00000018 }, - { 0x844075bc, 0x00000002 }, - { 0x000000c9, 0x00000004 }, - { 0x804075bd, 0x00000002 }, - { 0x800075bb, 0x00000002 }, - { 0x804075bc, 0x00000002 }, - { 0x00108000, 0x00000002 }, - { 0x01400000, 0x00000002 }, - { 0x006000cd, 0x0000000c }, - { 0x20c07000, 0x00000020 }, - { 0x000000cf, 0x00000012 }, - { 0x00800000, 0x00000006 }, - { 0x0080751d, 0x00000006 }, - { 0000000000, 0000000000 }, - { 0x0000775c, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00661000, 0x00000002 }, - { 0x0460275d, 0x00000020 }, - { 0x00004000, 0000000000 }, - { 0x01e00830, 0x00000002 }, - { 0x21007000, 0000000000 }, - { 0x6464614d, 0000000000 }, - { 0x69687420, 0000000000 }, - { 0x00000073, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x00005000, 0x00000002 }, - { 0x000380d0, 0x00000002 }, - { 0x040025e0, 0x00000002 }, - { 0x000075e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000380e0, 0x00000002 }, - { 0x04002394, 0x00000002 }, - { 0x00005000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x00000008, 0000000000 }, - { 0x00000004, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 R200_cp_microcode[][2]={ - { 0x21007000, 0000000000 }, - { 0x20007000, 0000000000 }, - { 0x000000bf, 0x00000004 }, - { 0x000000c3, 0x00000004 }, - { 0x7a685e5d, 0000000000 }, - { 0x5d5d5588, 0000000000 }, - { 0x68659197, 0000000000 }, - { 0x5da19f78, 0000000000 }, - { 0x5d5d5d5d, 0000000000 }, - { 0x5dee5d50, 0000000000 }, - { 0xf2acacac, 0000000000 }, - { 0xe75df9e9, 0000000000 }, - { 0xb1dd0e11, 0000000000 }, - { 0xe2afafaf, 0000000000 }, - { 0x000f0000, 0x00000016 }, - { 0x452f232d, 0000000000 }, - { 0x00000013, 0x00000004 }, - { 0x000f0000, 0x00000016 }, - { 0x452f272d, 0000000000 }, - { 0x000f0001, 0x00000016 }, - { 0x3e4d4a37, 0000000000 }, - { 0x000077ef, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00000016, 0x00000004 }, - { 0x0003802a, 0x00000002 }, - { 0x040067e0, 0x00000002 }, - { 0x00000016, 0x00000004 }, - { 0x000077e0, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x000037e1, 0x00000002 }, - { 0x040067e1, 0x00000006 }, - { 0x000077e0, 0x00000002 }, - { 0x000077e1, 0x00000002 }, - { 0x000077e1, 0x00000006 }, - { 0xffffffff, 0000000000 }, - { 0x10000000, 0000000000 }, - { 0x07f007f0, 0000000000 }, - { 0x0003802a, 0x00000002 }, - { 0x040067e0, 0x00000006 }, - { 0x0003802c, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002743, 0x00000002 }, - { 0x00007675, 0x00000002 }, - { 0x00007676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0003802c, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002743, 0x00000002 }, - { 0x00007676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0003802b, 0x00000002 }, - { 0x04002676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x0003802c, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002743, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0003802c, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002743, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0000002f, 0x00000018 }, - { 0x0000002f, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x00000037, 0x00000018 }, - { 0x00000037, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x01605000, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00098000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x64c06051, 0x00000004 }, - { 0x00080000, 0x00000016 }, - { 0000000000, 0000000000 }, - { 0x0400251d, 0x00000002 }, - { 0x00007580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x04002580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x0000005a, 0x00000004 }, - { 0x00005000, 0000000000 }, - { 0x00061000, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x00019000, 0x00000002 }, - { 0x00011064, 0x00000014 }, - { 0x00000064, 0x00000012 }, - { 0x0400250f, 0x00000002 }, - { 0x0000505e, 0x00000004 }, - { 0x00007565, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x00000065, 0x00000004 }, - { 0x01e655b4, 0x00000002 }, - { 0x4401b0f0, 0x00000002 }, - { 0x01c110f0, 0x00000002 }, - { 0x26667071, 0x00000018 }, - { 0x040c2565, 0x00000002 }, - { 0x00000071, 0x00000018 }, - { 0x04002564, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x00000068, 0x00000004 }, - { 0x00401074, 0x00000008 }, - { 0x00101000, 0x00000002 }, - { 0x000d80ff, 0x00000002 }, - { 0x00800077, 0x00000008 }, - { 0x000f9000, 0x00000002 }, - { 0x000e00ff, 0x00000002 }, - { 0000000000, 0x00000006 }, - { 0x00000094, 0x00000018 }, - { 0x00000068, 0x00000004 }, - { 0x00007576, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00009000, 0x00000002 }, - { 0x00041000, 0x00000002 }, - { 0x0c00350e, 0x00000002 }, - { 0x00049000, 0x00000002 }, - { 0x00051000, 0x00000002 }, - { 0x01e785f8, 0x00000002 }, - { 0x00200000, 0x00000002 }, - { 0x00600087, 0x0000000c }, - { 0x00007563, 0x00000002 }, - { 0x006075f0, 0x00000021 }, - { 0x2000707c, 0x00000004 }, - { 0x0000507c, 0x00000004 }, - { 0x00007576, 0x00000002 }, - { 0x00007577, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x0000750f, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x0060008a, 0x0000000c }, - { 0x006075f0, 0x00000021 }, - { 0x000075f8, 0x00000002 }, - { 0x0000008a, 0x00000004 }, - { 0x000a750e, 0x00000002 }, - { 0x0020750f, 0x00000002 }, - { 0x0060008d, 0x00000004 }, - { 0x00007570, 0x00000002 }, - { 0x00007571, 0x00000002 }, - { 0x00007572, 0x00000006 }, - { 0x00005000, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00007568, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000098, 0x0000000c }, - { 0x00058000, 0x00000002 }, - { 0x0c607562, 0x00000002 }, - { 0x0000009a, 0x00000004 }, - { 0x00600099, 0x00000004 }, - { 0x400070f1, 0000000000 }, - { 0x000380f1, 0x00000002 }, - { 0x000000a7, 0x0000001c }, - { 0x000650a9, 0x00000018 }, - { 0x040025bb, 0x00000002 }, - { 0x000610aa, 0x00000018 }, - { 0x040075bc, 0000000000 }, - { 0x000075bb, 0x00000002 }, - { 0x000075bc, 0000000000 }, - { 0x00090000, 0x00000006 }, - { 0x00090000, 0x00000002 }, - { 0x000d8002, 0x00000006 }, - { 0x00005000, 0x00000002 }, - { 0x00007821, 0x00000002 }, - { 0x00007800, 0000000000 }, - { 0x00007821, 0x00000002 }, - { 0x00007800, 0000000000 }, - { 0x01665000, 0x00000002 }, - { 0x000a0000, 0x00000002 }, - { 0x000671cc, 0x00000002 }, - { 0x0286f1cd, 0x00000002 }, - { 0x000000b7, 0x00000010 }, - { 0x21007000, 0000000000 }, - { 0x000000be, 0x0000001c }, - { 0x00065000, 0x00000002 }, - { 0x000a0000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x000b0000, 0x00000002 }, - { 0x38067000, 0x00000002 }, - { 0x000a00ba, 0x00000004 }, - { 0x20007000, 0000000000 }, - { 0x01200000, 0x00000002 }, - { 0x20077000, 0x00000002 }, - { 0x01200000, 0x00000002 }, - { 0x20007000, 0000000000 }, - { 0x00061000, 0x00000002 }, - { 0x0120751b, 0x00000002 }, - { 0x8040750a, 0x00000002 }, - { 0x8040750b, 0x00000002 }, - { 0x00110000, 0x00000002 }, - { 0x000380f1, 0x00000002 }, - { 0x000000d1, 0x0000001c }, - { 0x000610aa, 0x00000018 }, - { 0x844075bd, 0x00000002 }, - { 0x000610a9, 0x00000018 }, - { 0x840075bb, 0x00000002 }, - { 0x000610aa, 0x00000018 }, - { 0x844075bc, 0x00000002 }, - { 0x000000d4, 0x00000004 }, - { 0x804075bd, 0x00000002 }, - { 0x800075bb, 0x00000002 }, - { 0x804075bc, 0x00000002 }, - { 0x00108000, 0x00000002 }, - { 0x01400000, 0x00000002 }, - { 0x006000d8, 0x0000000c }, - { 0x20c07000, 0x00000020 }, - { 0x000000da, 0x00000012 }, - { 0x00800000, 0x00000006 }, - { 0x0080751d, 0x00000006 }, - { 0x000025bb, 0x00000002 }, - { 0x000040d4, 0x00000004 }, - { 0x0000775c, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00661000, 0x00000002 }, - { 0x0460275d, 0x00000020 }, - { 0x00004000, 0000000000 }, - { 0x00007999, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00661000, 0x00000002 }, - { 0x0460299b, 0x00000020 }, - { 0x00004000, 0000000000 }, - { 0x01e00830, 0x00000002 }, - { 0x21007000, 0000000000 }, - { 0x00005000, 0x00000002 }, - { 0x00038056, 0x00000002 }, - { 0x040025e0, 0x00000002 }, - { 0x000075e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000380ed, 0x00000002 }, - { 0x04007394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000078c4, 0x00000002 }, - { 0x000078c5, 0x00000002 }, - { 0x000078c6, 0x00000002 }, - { 0x00007924, 0x00000002 }, - { 0x00007925, 0x00000002 }, - { 0x00007926, 0x00000002 }, - { 0x000000f2, 0x00000004 }, - { 0x00007924, 0x00000002 }, - { 0x00007925, 0x00000002 }, - { 0x00007926, 0x00000002 }, - { 0x000000f9, 0x00000004 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 R300_cp_microcode[][2]={ - { 0x4200e000, 0000000000 }, - { 0x4000e000, 0000000000 }, - { 0x000000ae, 0x00000008 }, - { 0x000000b2, 0x00000008 }, - { 0x67554b4a, 0000000000 }, - { 0x4a4a4475, 0000000000 }, - { 0x55527d83, 0000000000 }, - { 0x4a8c8b65, 0000000000 }, - { 0x4aef4af6, 0000000000 }, - { 0x4ae14a4a, 0000000000 }, - { 0xe4979797, 0000000000 }, - { 0xdb4aebdd, 0000000000 }, - { 0x9ccc4a4a, 0000000000 }, - { 0xd1989898, 0000000000 }, - { 0x4a0f9ad6, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 0x0000e857, 0x00000004 }, - { 0x000d001e, 0x00000038 }, - { 0x0000e824, 0x00000004 }, - { 0x000d0020, 0x00000038 }, - { 0x0000e825, 0x00000004 }, - { 0x000d0022, 0x00000038 }, - { 0x0000e830, 0x00000004 }, - { 0x000d0024, 0x00000038 }, - { 0x0000f0c0, 0x00000004 }, - { 0x000d0026, 0x00000038 }, - { 0x0000f0c1, 0x00000004 }, - { 0x000d0028, 0x00000038 }, - { 0x0000f041, 0x00000004 }, - { 0x000d002a, 0x00000038 }, - { 0x0000f184, 0x00000004 }, - { 0x000d002c, 0x00000038 }, - { 0x0000f185, 0x00000004 }, - { 0x000d002e, 0x00000038 }, - { 0x0000f186, 0x00000004 }, - { 0x000d0030, 0x00000038 }, - { 0x0000f187, 0x00000004 }, - { 0x000d0032, 0x00000038 }, - { 0x0000f180, 0x00000004 }, - { 0x000d0034, 0x00000038 }, - { 0x0000f393, 0x00000004 }, - { 0x000d0036, 0x00000038 }, - { 0x0000f38a, 0x00000004 }, - { 0x000d0038, 0x00000038 }, - { 0x0000f38e, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000043, 0x00000018 }, - { 0x00cce800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x0000003a, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x2000451d, 0x00000004 }, - { 0x0000e580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x08004580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x00000047, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x00032000, 0x00000004 }, - { 0x00022051, 0x00000028 }, - { 0x00000051, 0x00000024 }, - { 0x0800450f, 0x00000004 }, - { 0x0000a04b, 0x00000008 }, - { 0x0000e565, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000052, 0x00000008 }, - { 0x03cca5b4, 0x00000004 }, - { 0x05432000, 0x00000004 }, - { 0x00022000, 0x00000004 }, - { 0x4ccce05e, 0x00000030 }, - { 0x08274565, 0x00000004 }, - { 0x0000005e, 0x00000030 }, - { 0x08004564, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000055, 0x00000008 }, - { 0x00802061, 0x00000010 }, - { 0x00202000, 0x00000004 }, - { 0x001b00ff, 0x00000004 }, - { 0x01000064, 0x00000010 }, - { 0x001f2000, 0x00000004 }, - { 0x001c00ff, 0x00000004 }, - { 0000000000, 0x0000000c }, - { 0x00000080, 0x00000030 }, - { 0x00000055, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x00012000, 0x00000004 }, - { 0x00082000, 0x00000004 }, - { 0x1800650e, 0x00000004 }, - { 0x00092000, 0x00000004 }, - { 0x000a2000, 0x00000004 }, - { 0x000f0000, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x00000074, 0x00000018 }, - { 0x0000e563, 0x00000004 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000069, 0x00000008 }, - { 0x0000a069, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x0000e577, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x0000e50f, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000077, 0x00000018 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000077, 0x00000008 }, - { 0x0014e50e, 0x00000004 }, - { 0x0040e50f, 0x00000004 }, - { 0x00c0007a, 0x00000008 }, - { 0x0000e570, 0x00000004 }, - { 0x0000e571, 0x00000004 }, - { 0x0000e572, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000e568, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00000084, 0x00000018 }, - { 0x000b0000, 0x00000004 }, - { 0x18c0e562, 0x00000004 }, - { 0x00000086, 0x00000008 }, - { 0x00c00085, 0x00000008 }, - { 0x000700e3, 0x00000004 }, - { 0x00000092, 0x00000038 }, - { 0x000ca094, 0x00000030 }, - { 0x080045bb, 0x00000004 }, - { 0x000c2095, 0x00000030 }, - { 0x0800e5bc, 0000000000 }, - { 0x0000e5bb, 0x00000004 }, - { 0x0000e5bc, 0000000000 }, - { 0x00120000, 0x0000000c }, - { 0x00120000, 0x00000004 }, - { 0x001b0002, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e800, 0000000000 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e82e, 0000000000 }, - { 0x02cca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000ce1cc, 0x00000004 }, - { 0x050de1cd, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x000000a4, 0x00000018 }, - { 0x00c0a000, 0x00000004 }, - { 0x000000a1, 0x00000008 }, - { 0x000000a6, 0x00000020 }, - { 0x4200e000, 0000000000 }, - { 0x000000ad, 0x00000038 }, - { 0x000ca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00160000, 0x00000004 }, - { 0x700ce000, 0x00000004 }, - { 0x001400a9, 0x00000008 }, - { 0x4000e000, 0000000000 }, - { 0x02400000, 0x00000004 }, - { 0x400ee000, 0x00000004 }, - { 0x02400000, 0x00000004 }, - { 0x4000e000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0240e51b, 0x00000004 }, - { 0x0080e50a, 0x00000005 }, - { 0x0080e50b, 0x00000005 }, - { 0x00220000, 0x00000004 }, - { 0x000700e3, 0x00000004 }, - { 0x000000c0, 0x00000038 }, - { 0x000c2095, 0x00000030 }, - { 0x0880e5bd, 0x00000005 }, - { 0x000c2094, 0x00000030 }, - { 0x0800e5bb, 0x00000005 }, - { 0x000c2095, 0x00000030 }, - { 0x0880e5bc, 0x00000005 }, - { 0x000000c3, 0x00000008 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000c7, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000c9, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080c3, 0x00000008 }, - { 0x0000f3ce, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053cf, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f3d2, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053d3, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f39d, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c0539e, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700e0, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x0000e8c4, 0x00000004 }, - { 0x0000e8c5, 0x00000004 }, - { 0x0000e8c6, 0x00000004 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000e4, 0x00000008 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000eb, 0x00000008 }, - { 0x02c02000, 0x00000004 }, - { 0x00060000, 0x00000004 }, - { 0x000000f3, 0x00000034 }, - { 0x000000f0, 0x00000008 }, - { 0x00008000, 0x00000004 }, - { 0xc000e000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x001d0018, 0x00000004 }, - { 0x001a0001, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0x0500a04a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 R420_cp_microcode[][2]={ - { 0x4200e000, 0000000000 }, - { 0x4000e000, 0000000000 }, - { 0x00000099, 0x00000008 }, - { 0x0000009d, 0x00000008 }, - { 0x4a554b4a, 0000000000 }, - { 0x4a4a4467, 0000000000 }, - { 0x55526f75, 0000000000 }, - { 0x4a7e7d65, 0000000000 }, - { 0xd9d3dff6, 0000000000 }, - { 0x4ac54a4a, 0000000000 }, - { 0xc8828282, 0000000000 }, - { 0xbf4acfc1, 0000000000 }, - { 0x87b04a4a, 0000000000 }, - { 0xb5838383, 0000000000 }, - { 0x4a0f85ba, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 0x0000e857, 0x00000004 }, - { 0x000d001e, 0x00000038 }, - { 0x0000e824, 0x00000004 }, - { 0x000d0020, 0x00000038 }, - { 0x0000e825, 0x00000004 }, - { 0x000d0022, 0x00000038 }, - { 0x0000e830, 0x00000004 }, - { 0x000d0024, 0x00000038 }, - { 0x0000f0c0, 0x00000004 }, - { 0x000d0026, 0x00000038 }, - { 0x0000f0c1, 0x00000004 }, - { 0x000d0028, 0x00000038 }, - { 0x0000f041, 0x00000004 }, - { 0x000d002a, 0x00000038 }, - { 0x0000f184, 0x00000004 }, - { 0x000d002c, 0x00000038 }, - { 0x0000f185, 0x00000004 }, - { 0x000d002e, 0x00000038 }, - { 0x0000f186, 0x00000004 }, - { 0x000d0030, 0x00000038 }, - { 0x0000f187, 0x00000004 }, - { 0x000d0032, 0x00000038 }, - { 0x0000f180, 0x00000004 }, - { 0x000d0034, 0x00000038 }, - { 0x0000f393, 0x00000004 }, - { 0x000d0036, 0x00000038 }, - { 0x0000f38a, 0x00000004 }, - { 0x000d0038, 0x00000038 }, - { 0x0000f38e, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000043, 0x00000018 }, - { 0x00cce800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x0000003a, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x2000451d, 0x00000004 }, - { 0x0000e580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x08004580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x00000047, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x00032000, 0x00000004 }, - { 0x00022051, 0x00000028 }, - { 0x00000051, 0x00000024 }, - { 0x0800450f, 0x00000004 }, - { 0x0000a04b, 0x00000008 }, - { 0x0000e565, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000052, 0x00000008 }, - { 0x03cca5b4, 0x00000004 }, - { 0x05432000, 0x00000004 }, - { 0x00022000, 0x00000004 }, - { 0x4ccce05e, 0x00000030 }, - { 0x08274565, 0x00000004 }, - { 0x0000005e, 0x00000030 }, - { 0x08004564, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000055, 0x00000008 }, - { 0x00802061, 0x00000010 }, - { 0x00202000, 0x00000004 }, - { 0x001b00ff, 0x00000004 }, - { 0x01000064, 0x00000010 }, - { 0x001f2000, 0x00000004 }, - { 0x001c00ff, 0x00000004 }, - { 0000000000, 0x0000000c }, - { 0x00000072, 0x00000030 }, - { 0x00000055, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x0000e577, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x0000e50f, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000069, 0x00000018 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000069, 0x00000008 }, - { 0x0014e50e, 0x00000004 }, - { 0x0040e50f, 0x00000004 }, - { 0x00c0006c, 0x00000008 }, - { 0x0000e570, 0x00000004 }, - { 0x0000e571, 0x00000004 }, - { 0x0000e572, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000e568, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00000076, 0x00000018 }, - { 0x000b0000, 0x00000004 }, - { 0x18c0e562, 0x00000004 }, - { 0x00000078, 0x00000008 }, - { 0x00c00077, 0x00000008 }, - { 0x000700c7, 0x00000004 }, - { 0x00000080, 0x00000038 }, - { 0x0000e5bb, 0x00000004 }, - { 0x0000e5bc, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e800, 0000000000 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e82e, 0000000000 }, - { 0x02cca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000ce1cc, 0x00000004 }, - { 0x050de1cd, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x0000008f, 0x00000018 }, - { 0x00c0a000, 0x00000004 }, - { 0x0000008c, 0x00000008 }, - { 0x00000091, 0x00000020 }, - { 0x4200e000, 0000000000 }, - { 0x00000098, 0x00000038 }, - { 0x000ca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00160000, 0x00000004 }, - { 0x700ce000, 0x00000004 }, - { 0x00140094, 0x00000008 }, - { 0x4000e000, 0000000000 }, - { 0x02400000, 0x00000004 }, - { 0x400ee000, 0x00000004 }, - { 0x02400000, 0x00000004 }, - { 0x4000e000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0240e51b, 0x00000004 }, - { 0x0080e50a, 0x00000005 }, - { 0x0080e50b, 0x00000005 }, - { 0x00220000, 0x00000004 }, - { 0x000700c7, 0x00000004 }, - { 0x000000a4, 0x00000038 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000ab, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000ad, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080a7, 0x00000008 }, - { 0x0000f3ce, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053cf, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f3d2, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053d3, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f39d, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c0539e, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700c4, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x0000e8c4, 0x00000004 }, - { 0x0000e8c5, 0x00000004 }, - { 0x0000e8c6, 0x00000004 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000c8, 0x00000008 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000cf, 0x00000008 }, - { 0x02c02000, 0x00000004 }, - { 0x00060000, 0x00000004 }, - { 0x000000d7, 0x00000034 }, - { 0x000000d4, 0x00000008 }, - { 0x00008000, 0x00000004 }, - { 0xc000e000, 0000000000 }, - { 0x0000e1cc, 0x00000004 }, - { 0x0500e1cd, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x000000de, 0x00000034 }, - { 0x000000da, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x0019e1cc, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x0500a000, 0x00000004 }, - { 0x080041cd, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x001d0018, 0x00000004 }, - { 0x001a0001, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0x0500a04a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 RS600_cp_microcode[][2]={ - { 0x4200e000, 0000000000 }, - { 0x4000e000, 0000000000 }, - { 0x000000a0, 0x00000008 }, - { 0x000000a4, 0x00000008 }, - { 0x4a554b4a, 0000000000 }, - { 0x4a4a4467, 0000000000 }, - { 0x55526f75, 0000000000 }, - { 0x4a7e7d65, 0000000000 }, - { 0x4ae74af6, 0000000000 }, - { 0x4ad34a4a, 0000000000 }, - { 0xd6898989, 0000000000 }, - { 0xcd4addcf, 0000000000 }, - { 0x8ebe4ae2, 0000000000 }, - { 0xc38a8a8a, 0000000000 }, - { 0x4a0f8cc8, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 0x0000e857, 0x00000004 }, - { 0x000d001e, 0x00000038 }, - { 0x0000e824, 0x00000004 }, - { 0x000d0020, 0x00000038 }, - { 0x0000e825, 0x00000004 }, - { 0x000d0022, 0x00000038 }, - { 0x0000e830, 0x00000004 }, - { 0x000d0024, 0x00000038 }, - { 0x0000f0c0, 0x00000004 }, - { 0x000d0026, 0x00000038 }, - { 0x0000f0c1, 0x00000004 }, - { 0x000d0028, 0x00000038 }, - { 0x0000f041, 0x00000004 }, - { 0x000d002a, 0x00000038 }, - { 0x0000f184, 0x00000004 }, - { 0x000d002c, 0x00000038 }, - { 0x0000f185, 0x00000004 }, - { 0x000d002e, 0x00000038 }, - { 0x0000f186, 0x00000004 }, - { 0x000d0030, 0x00000038 }, - { 0x0000f187, 0x00000004 }, - { 0x000d0032, 0x00000038 }, - { 0x0000f180, 0x00000004 }, - { 0x000d0034, 0x00000038 }, - { 0x0000f393, 0x00000004 }, - { 0x000d0036, 0x00000038 }, - { 0x0000f38a, 0x00000004 }, - { 0x000d0038, 0x00000038 }, - { 0x0000f38e, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000043, 0x00000018 }, - { 0x00cce800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x0000003a, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x2000451d, 0x00000004 }, - { 0x0000e580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x08004580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x00000047, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x00032000, 0x00000004 }, - { 0x00022051, 0x00000028 }, - { 0x00000051, 0x00000024 }, - { 0x0800450f, 0x00000004 }, - { 0x0000a04b, 0x00000008 }, - { 0x0000e565, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000052, 0x00000008 }, - { 0x03cca5b4, 0x00000004 }, - { 0x05432000, 0x00000004 }, - { 0x00022000, 0x00000004 }, - { 0x4ccce05e, 0x00000030 }, - { 0x08274565, 0x00000004 }, - { 0x0000005e, 0x00000030 }, - { 0x08004564, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000055, 0x00000008 }, - { 0x00802061, 0x00000010 }, - { 0x00202000, 0x00000004 }, - { 0x001b00ff, 0x00000004 }, - { 0x01000064, 0x00000010 }, - { 0x001f2000, 0x00000004 }, - { 0x001c00ff, 0x00000004 }, - { 0000000000, 0x0000000c }, - { 0x00000072, 0x00000030 }, - { 0x00000055, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x0000e577, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x0000e50f, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000069, 0x00000018 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000069, 0x00000008 }, - { 0x0014e50e, 0x00000004 }, - { 0x0040e50f, 0x00000004 }, - { 0x00c0006c, 0x00000008 }, - { 0x0000e570, 0x00000004 }, - { 0x0000e571, 0x00000004 }, - { 0x0000e572, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000e568, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00000076, 0x00000018 }, - { 0x000b0000, 0x00000004 }, - { 0x18c0e562, 0x00000004 }, - { 0x00000078, 0x00000008 }, - { 0x00c00077, 0x00000008 }, - { 0x000700d5, 0x00000004 }, - { 0x00000084, 0x00000038 }, - { 0x000ca086, 0x00000030 }, - { 0x080045bb, 0x00000004 }, - { 0x000c2087, 0x00000030 }, - { 0x0800e5bc, 0000000000 }, - { 0x0000e5bb, 0x00000004 }, - { 0x0000e5bc, 0000000000 }, - { 0x00120000, 0x0000000c }, - { 0x00120000, 0x00000004 }, - { 0x001b0002, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e800, 0000000000 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e82e, 0000000000 }, - { 0x02cca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000ce1cc, 0x00000004 }, - { 0x050de1cd, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x00000096, 0x00000018 }, - { 0x00c0a000, 0x00000004 }, - { 0x00000093, 0x00000008 }, - { 0x00000098, 0x00000020 }, - { 0x4200e000, 0000000000 }, - { 0x0000009f, 0x00000038 }, - { 0x000ca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00160000, 0x00000004 }, - { 0x700ce000, 0x00000004 }, - { 0x0014009b, 0x00000008 }, - { 0x4000e000, 0000000000 }, - { 0x02400000, 0x00000004 }, - { 0x400ee000, 0x00000004 }, - { 0x02400000, 0x00000004 }, - { 0x4000e000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0240e51b, 0x00000004 }, - { 0x0080e50a, 0x00000005 }, - { 0x0080e50b, 0x00000005 }, - { 0x00220000, 0x00000004 }, - { 0x000700d5, 0x00000004 }, - { 0x000000b2, 0x00000038 }, - { 0x000c2087, 0x00000030 }, - { 0x0880e5bd, 0x00000005 }, - { 0x000c2086, 0x00000030 }, - { 0x0800e5bb, 0x00000005 }, - { 0x000c2087, 0x00000030 }, - { 0x0880e5bc, 0x00000005 }, - { 0x000000b5, 0x00000008 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000b9, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000bb, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080b5, 0x00000008 }, - { 0x0000f3ce, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053cf, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f3d2, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053d3, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f39d, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c0539e, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700d2, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x0000e8c4, 0x00000004 }, - { 0x0000e8c5, 0x00000004 }, - { 0x0000e8c6, 0x00000004 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000d6, 0x00000008 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000dd, 0x00000008 }, - { 0x00e00116, 0000000000 }, - { 0x000700e1, 0x00000004 }, - { 0x0800401c, 0x00000004 }, - { 0x200050e7, 0x00000004 }, - { 0x0000e01d, 0x00000004 }, - { 0x000000e4, 0x00000008 }, - { 0x02c02000, 0x00000004 }, - { 0x00060000, 0x00000004 }, - { 0x000000eb, 0x00000034 }, - { 0x000000e8, 0x00000008 }, - { 0x00008000, 0x00000004 }, - { 0xc000e000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x001d0018, 0x00000004 }, - { 0x001a0001, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0x0500a04a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 RS690_cp_microcode[][2]={ - { 0x000000dd, 0x00000008 }, - { 0x000000df, 0x00000008 }, - { 0x000000a0, 0x00000008 }, - { 0x000000a4, 0x00000008 }, - { 0x4a554b4a, 0000000000 }, - { 0x4a4a4467, 0000000000 }, - { 0x55526f75, 0000000000 }, - { 0x4a7e7d65, 0000000000 }, - { 0x4ad74af6, 0000000000 }, - { 0x4ac94a4a, 0000000000 }, - { 0xcc898989, 0000000000 }, - { 0xc34ad3c5, 0000000000 }, - { 0x8e4a4a4a, 0000000000 }, - { 0x4a8a8a8a, 0000000000 }, - { 0x4a0f8c4a, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 0x0000e857, 0x00000004 }, - { 0x000d001e, 0x00000038 }, - { 0x0000e824, 0x00000004 }, - { 0x000d0020, 0x00000038 }, - { 0x0000e825, 0x00000004 }, - { 0x000d0022, 0x00000038 }, - { 0x0000e830, 0x00000004 }, - { 0x000d0024, 0x00000038 }, - { 0x0000f0c0, 0x00000004 }, - { 0x000d0026, 0x00000038 }, - { 0x0000f0c1, 0x00000004 }, - { 0x000d0028, 0x00000038 }, - { 0x0000f041, 0x00000004 }, - { 0x000d002a, 0x00000038 }, - { 0x0000f184, 0x00000004 }, - { 0x000d002c, 0x00000038 }, - { 0x0000f185, 0x00000004 }, - { 0x000d002e, 0x00000038 }, - { 0x0000f186, 0x00000004 }, - { 0x000d0030, 0x00000038 }, - { 0x0000f187, 0x00000004 }, - { 0x000d0032, 0x00000038 }, - { 0x0000f180, 0x00000004 }, - { 0x000d0034, 0x00000038 }, - { 0x0000f393, 0x00000004 }, - { 0x000d0036, 0x00000038 }, - { 0x0000f38a, 0x00000004 }, - { 0x000d0038, 0x00000038 }, - { 0x0000f38e, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000043, 0x00000018 }, - { 0x00cce800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x0000003a, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x2000451d, 0x00000004 }, - { 0x0000e580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x08004580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x00000047, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x00032000, 0x00000004 }, - { 0x00022051, 0x00000028 }, - { 0x00000051, 0x00000024 }, - { 0x0800450f, 0x00000004 }, - { 0x0000a04b, 0x00000008 }, - { 0x0000e565, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000052, 0x00000008 }, - { 0x03cca5b4, 0x00000004 }, - { 0x05432000, 0x00000004 }, - { 0x00022000, 0x00000004 }, - { 0x4ccce05e, 0x00000030 }, - { 0x08274565, 0x00000004 }, - { 0x0000005e, 0x00000030 }, - { 0x08004564, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000055, 0x00000008 }, - { 0x00802061, 0x00000010 }, - { 0x00202000, 0x00000004 }, - { 0x001b00ff, 0x00000004 }, - { 0x01000064, 0x00000010 }, - { 0x001f2000, 0x00000004 }, - { 0x001c00ff, 0x00000004 }, - { 0000000000, 0x0000000c }, - { 0x00000072, 0x00000030 }, - { 0x00000055, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x0000e577, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x0000e50f, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000069, 0x00000018 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000069, 0x00000008 }, - { 0x0014e50e, 0x00000004 }, - { 0x0040e50f, 0x00000004 }, - { 0x00c0006c, 0x00000008 }, - { 0x0000e570, 0x00000004 }, - { 0x0000e571, 0x00000004 }, - { 0x0000e572, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000e568, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00000076, 0x00000018 }, - { 0x000b0000, 0x00000004 }, - { 0x18c0e562, 0x00000004 }, - { 0x00000078, 0x00000008 }, - { 0x00c00077, 0x00000008 }, - { 0x000700cb, 0x00000004 }, - { 0x00000084, 0x00000038 }, - { 0x000ca086, 0x00000030 }, - { 0x080045bb, 0x00000004 }, - { 0x000c2087, 0x00000030 }, - { 0x0800e5bc, 0000000000 }, - { 0x0000e5bb, 0x00000004 }, - { 0x0000e5bc, 0000000000 }, - { 0x00120000, 0x0000000c }, - { 0x00120000, 0x00000004 }, - { 0x001b0002, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e800, 0000000000 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e82e, 0000000000 }, - { 0x02cca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000ce1cc, 0x00000004 }, - { 0x050de1cd, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x00000096, 0x00000018 }, - { 0x00c0a000, 0x00000004 }, - { 0x00000093, 0x00000008 }, - { 0x00000098, 0x00000020 }, - { 0x4200e000, 0000000000 }, - { 0x0000009f, 0x00000038 }, - { 0x000ca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00160000, 0x00000004 }, - { 0x700ce000, 0x00000004 }, - { 0x0014009b, 0x00000008 }, - { 0x4000e000, 0000000000 }, - { 0x02400000, 0x00000004 }, - { 0x400ee000, 0x00000004 }, - { 0x02400000, 0x00000004 }, - { 0x4000e000, 0000000000 }, - { 0x00100000, 0x0000002c }, - { 0x00004000, 0000000000 }, - { 0x080045c8, 0x00000004 }, - { 0x00240005, 0x00000004 }, - { 0x08004d0b, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x0240e51b, 0x00000004 }, - { 0x0080e50a, 0x00000005 }, - { 0x0080e50b, 0x00000005 }, - { 0x00220000, 0x00000004 }, - { 0x000700cb, 0x00000004 }, - { 0x000000b7, 0x00000038 }, - { 0x000c2087, 0x00000030 }, - { 0x0880e5bd, 0x00000005 }, - { 0x000c2086, 0x00000030 }, - { 0x0800e5bb, 0x00000005 }, - { 0x000c2087, 0x00000030 }, - { 0x0880e5bc, 0x00000005 }, - { 0x000000ba, 0x00000008 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000be, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000c0, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080ba, 0x00000008 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700c8, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x0000e8c4, 0x00000004 }, - { 0x0000e8c5, 0x00000004 }, - { 0x0000e8c6, 0x00000004 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000cc, 0x00000008 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000d3, 0x00000008 }, - { 0x02c02000, 0x00000004 }, - { 0x00060000, 0x00000004 }, - { 0x000000db, 0x00000034 }, - { 0x000000d8, 0x00000008 }, - { 0x00008000, 0x00000004 }, - { 0xc000e000, 0000000000 }, - { 0x000000e1, 0x00000030 }, - { 0x4200e000, 0000000000 }, - { 0x000000e1, 0x00000030 }, - { 0x4000e000, 0000000000 }, - { 0x0025001b, 0x00000004 }, - { 0x00230000, 0x00000004 }, - { 0x00250005, 0x00000004 }, - { 0x000000e6, 0x00000034 }, - { 0000000000, 0x0000000c }, - { 0x00244000, 0x00000004 }, - { 0x080045c8, 0x00000004 }, - { 0x00240005, 0x00000004 }, - { 0x08004d0b, 0x0000000c }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x001d0018, 0x00000004 }, - { 0x001a0001, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0x0500a04a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 R520_cp_microcode[][2]={ - { 0x4200e000, 0000000000 }, - { 0x4000e000, 0000000000 }, - { 0x00000099, 0x00000008 }, - { 0x0000009d, 0x00000008 }, - { 0x4a554b4a, 0000000000 }, - { 0x4a4a4467, 0000000000 }, - { 0x55526f75, 0000000000 }, - { 0x4a7e7d65, 0000000000 }, - { 0xe0dae6f6, 0000000000 }, - { 0x4ac54a4a, 0000000000 }, - { 0xc8828282, 0000000000 }, - { 0xbf4acfc1, 0000000000 }, - { 0x87b04ad5, 0000000000 }, - { 0xb5838383, 0000000000 }, - { 0x4a0f85ba, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 0x0000e857, 0x00000004 }, - { 0x000d001e, 0x00000038 }, - { 0x0000e824, 0x00000004 }, - { 0x000d0020, 0x00000038 }, - { 0x0000e825, 0x00000004 }, - { 0x000d0022, 0x00000038 }, - { 0x0000e830, 0x00000004 }, - { 0x000d0024, 0x00000038 }, - { 0x0000f0c0, 0x00000004 }, - { 0x000d0026, 0x00000038 }, - { 0x0000f0c1, 0x00000004 }, - { 0x000d0028, 0x00000038 }, - { 0x0000e000, 0x00000004 }, - { 0x000d002a, 0x00000038 }, - { 0x0000e000, 0x00000004 }, - { 0x000d002c, 0x00000038 }, - { 0x0000e000, 0x00000004 }, - { 0x000d002e, 0x00000038 }, - { 0x0000e000, 0x00000004 }, - { 0x000d0030, 0x00000038 }, - { 0x0000e000, 0x00000004 }, - { 0x000d0032, 0x00000038 }, - { 0x0000f180, 0x00000004 }, - { 0x000d0034, 0x00000038 }, - { 0x0000f393, 0x00000004 }, - { 0x000d0036, 0x00000038 }, - { 0x0000f38a, 0x00000004 }, - { 0x000d0038, 0x00000038 }, - { 0x0000f38e, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000043, 0x00000018 }, - { 0x00cce800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x0000003a, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x2000451d, 0x00000004 }, - { 0x0000e580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x08004580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x00000047, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x00032000, 0x00000004 }, - { 0x00022051, 0x00000028 }, - { 0x00000051, 0x00000024 }, - { 0x0800450f, 0x00000004 }, - { 0x0000a04b, 0x00000008 }, - { 0x0000e565, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000052, 0x00000008 }, - { 0x03cca5b4, 0x00000004 }, - { 0x05432000, 0x00000004 }, - { 0x00022000, 0x00000004 }, - { 0x4ccce05e, 0x00000030 }, - { 0x08274565, 0x00000004 }, - { 0x0000005e, 0x00000030 }, - { 0x08004564, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000055, 0x00000008 }, - { 0x00802061, 0x00000010 }, - { 0x00202000, 0x00000004 }, - { 0x001b00ff, 0x00000004 }, - { 0x01000064, 0x00000010 }, - { 0x001f2000, 0x00000004 }, - { 0x001c00ff, 0x00000004 }, - { 0000000000, 0x0000000c }, - { 0x00000072, 0x00000030 }, - { 0x00000055, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x0000e577, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x0000e50f, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000069, 0x00000018 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000069, 0x00000008 }, - { 0x0014e50e, 0x00000004 }, - { 0x0040e50f, 0x00000004 }, - { 0x00c0006c, 0x00000008 }, - { 0x0000e570, 0x00000004 }, - { 0x0000e571, 0x00000004 }, - { 0x0000e572, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000e568, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00000076, 0x00000018 }, - { 0x000b0000, 0x00000004 }, - { 0x18c0e562, 0x00000004 }, - { 0x00000078, 0x00000008 }, - { 0x00c00077, 0x00000008 }, - { 0x000700c7, 0x00000004 }, - { 0x00000080, 0x00000038 }, - { 0x0000e5bb, 0x00000004 }, - { 0x0000e5bc, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e800, 0000000000 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e82e, 0000000000 }, - { 0x02cca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000ce1cc, 0x00000004 }, - { 0x050de1cd, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x0000008f, 0x00000018 }, - { 0x00c0a000, 0x00000004 }, - { 0x0000008c, 0x00000008 }, - { 0x00000091, 0x00000020 }, - { 0x4200e000, 0000000000 }, - { 0x00000098, 0x00000038 }, - { 0x000ca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00160000, 0x00000004 }, - { 0x700ce000, 0x00000004 }, - { 0x00140094, 0x00000008 }, - { 0x4000e000, 0000000000 }, - { 0x02400000, 0x00000004 }, - { 0x400ee000, 0x00000004 }, - { 0x02400000, 0x00000004 }, - { 0x4000e000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0240e51b, 0x00000004 }, - { 0x0080e50a, 0x00000005 }, - { 0x0080e50b, 0x00000005 }, - { 0x00220000, 0x00000004 }, - { 0x000700c7, 0x00000004 }, - { 0x000000a4, 0x00000038 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000ab, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000ad, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080a7, 0x00000008 }, - { 0x0000f3ce, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053cf, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f3d2, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053d3, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f39d, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c0539e, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700c4, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x0000e8c4, 0x00000004 }, - { 0x0000e8c5, 0x00000004 }, - { 0x0000e8c6, 0x00000004 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000c8, 0x00000008 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000cf, 0x00000008 }, - { 0xdeadbeef, 0000000000 }, - { 0x00000116, 0000000000 }, - { 0x000700d3, 0x00000004 }, - { 0x080050e7, 0x00000004 }, - { 0x000700d4, 0x00000004 }, - { 0x0800401c, 0x00000004 }, - { 0x0000e01d, 0000000000 }, - { 0x02c02000, 0x00000004 }, - { 0x00060000, 0x00000004 }, - { 0x000000de, 0x00000034 }, - { 0x000000db, 0x00000008 }, - { 0x00008000, 0x00000004 }, - { 0xc000e000, 0000000000 }, - { 0x0000e1cc, 0x00000004 }, - { 0x0500e1cd, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x000000e5, 0x00000034 }, - { 0x000000e1, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x0019e1cc, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x0500a000, 0x00000004 }, - { 0x080041cd, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x001d0018, 0x00000004 }, - { 0x001a0001, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0x0500a04a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - - -#endif diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c deleted file mode 100644 index 57e3a3bb..00000000 --- a/shared-core/radeon_state.c +++ /dev/null @@ -1,3263 +0,0 @@ -/* radeon_state.c -- State support for Radeon -*- linux-c -*- */ -/* - * Copyright 2000 VA Linux Systems, Inc., Fremont, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Kevin E. Martin - */ - -#include "drmP.h" -#include "drm.h" -#include "drm_sarea.h" -#include "radeon_drm.h" -#include "radeon_drv.h" - -/* ================================================================ - * Helper functions for client state checking and fixup - */ - -static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t * - dev_priv, - struct drm_file *file_priv, - u32 * offset) -{ - u64 off = *offset; - u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1; - struct drm_radeon_driver_file_fields *radeon_priv; - - /* Hrm ... the story of the offset ... So this function converts - * the various ideas of what userland clients might have for an - * offset in the card address space into an offset into the card - * address space :) So with a sane client, it should just keep - * the value intact and just do some boundary checking. However, - * not all clients are sane. Some older clients pass us 0 based - * offsets relative to the start of the framebuffer and some may - * assume the AGP aperture it appended to the framebuffer, so we - * try to detect those cases and fix them up. - * - * Note: It might be a good idea here to make sure the offset lands - * in some "allowed" area to protect things like the PCIE GART... - */ - - /* First, the best case, the offset already lands in either the - * framebuffer or the GART mapped space - */ - if (radeon_check_offset(dev_priv, off)) - return 0; - - /* Ok, that didn't happen... now check if we have a zero based - * offset that fits in the framebuffer + gart space, apply the - * magic offset we get from SETPARAM or calculated from fb_location - */ - if (off < (dev_priv->fb_size + dev_priv->gart_size)) { - radeon_priv = file_priv->driver_priv; - off += radeon_priv->radeon_fb_delta; - } - - /* Finally, assume we aimed at a GART offset if beyond the fb */ - if (off > fb_end) - off = off - fb_end - 1 + dev_priv->gart_vm_start; - - /* Now recheck and fail if out of bounds */ - if (radeon_check_offset(dev_priv, off)) { - DRM_DEBUG("offset fixed up to 0x%x\n", (unsigned int)off); - *offset = off; - return 0; - } - return -EINVAL; -} - -static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * - dev_priv, - struct drm_file *file_priv, - int id, u32 *data) -{ - switch (id) { - - case RADEON_EMIT_PP_MISC: - if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) { - DRM_ERROR("Invalid depth buffer offset\n"); - return -EINVAL; - } - break; - - case RADEON_EMIT_PP_CNTL: - if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) { - DRM_ERROR("Invalid colour buffer offset\n"); - return -EINVAL; - } - break; - - case R200_EMIT_PP_TXOFFSET_0: - case R200_EMIT_PP_TXOFFSET_1: - case R200_EMIT_PP_TXOFFSET_2: - case R200_EMIT_PP_TXOFFSET_3: - case R200_EMIT_PP_TXOFFSET_4: - case R200_EMIT_PP_TXOFFSET_5: - if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &data[0])) { - DRM_ERROR("Invalid R200 texture offset\n"); - return -EINVAL; - } - break; - - case RADEON_EMIT_PP_TXFILTER_0: - case RADEON_EMIT_PP_TXFILTER_1: - case RADEON_EMIT_PP_TXFILTER_2: - if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) { - DRM_ERROR("Invalid R100 texture offset\n"); - return -EINVAL; - } - break; - - case R200_EMIT_PP_CUBIC_OFFSETS_0: - case R200_EMIT_PP_CUBIC_OFFSETS_1: - case R200_EMIT_PP_CUBIC_OFFSETS_2: - case R200_EMIT_PP_CUBIC_OFFSETS_3: - case R200_EMIT_PP_CUBIC_OFFSETS_4: - case R200_EMIT_PP_CUBIC_OFFSETS_5:{ - int i; - for (i = 0; i < 5; i++) { - if (radeon_check_and_fixup_offset(dev_priv, - file_priv, - &data[i])) { - DRM_ERROR - ("Invalid R200 cubic texture offset\n"); - return -EINVAL; - } - } - break; - } - - case RADEON_EMIT_PP_CUBIC_OFFSETS_T0: - case RADEON_EMIT_PP_CUBIC_OFFSETS_T1: - case RADEON_EMIT_PP_CUBIC_OFFSETS_T2:{ - int i; - for (i = 0; i < 5; i++) { - if (radeon_check_and_fixup_offset(dev_priv, - file_priv, - &data[i])) { - DRM_ERROR - ("Invalid R100 cubic texture offset\n"); - return -EINVAL; - } - } - } - break; - - case R200_EMIT_VAP_CTL: { - RING_LOCALS; - BEGIN_RING(2); - OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0); - ADVANCE_RING(); - } - break; - - case RADEON_EMIT_RB3D_COLORPITCH: - case RADEON_EMIT_RE_LINE_PATTERN: - case RADEON_EMIT_SE_LINE_WIDTH: - case RADEON_EMIT_PP_LUM_MATRIX: - case RADEON_EMIT_PP_ROT_MATRIX_0: - case RADEON_EMIT_RB3D_STENCILREFMASK: - case RADEON_EMIT_SE_VPORT_XSCALE: - case RADEON_EMIT_SE_CNTL: - case RADEON_EMIT_SE_CNTL_STATUS: - case RADEON_EMIT_RE_MISC: - case RADEON_EMIT_PP_BORDER_COLOR_0: - case RADEON_EMIT_PP_BORDER_COLOR_1: - case RADEON_EMIT_PP_BORDER_COLOR_2: - case RADEON_EMIT_SE_ZBIAS_FACTOR: - case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT: - case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED: - case R200_EMIT_PP_TXCBLEND_0: - case R200_EMIT_PP_TXCBLEND_1: - case R200_EMIT_PP_TXCBLEND_2: - case R200_EMIT_PP_TXCBLEND_3: - case R200_EMIT_PP_TXCBLEND_4: - case R200_EMIT_PP_TXCBLEND_5: - case R200_EMIT_PP_TXCBLEND_6: - case R200_EMIT_PP_TXCBLEND_7: - case R200_EMIT_TCL_LIGHT_MODEL_CTL_0: - case R200_EMIT_TFACTOR_0: - case R200_EMIT_VTX_FMT_0: - case R200_EMIT_MATRIX_SELECT_0: - case R200_EMIT_TEX_PROC_CTL_2: - case R200_EMIT_TCL_UCP_VERT_BLEND_CTL: - case R200_EMIT_PP_TXFILTER_0: - case R200_EMIT_PP_TXFILTER_1: - case R200_EMIT_PP_TXFILTER_2: - case R200_EMIT_PP_TXFILTER_3: - case R200_EMIT_PP_TXFILTER_4: - case R200_EMIT_PP_TXFILTER_5: - case R200_EMIT_VTE_CNTL: - case R200_EMIT_OUTPUT_VTX_COMP_SEL: - case R200_EMIT_PP_TAM_DEBUG3: - case R200_EMIT_PP_CNTL_X: - case R200_EMIT_RB3D_DEPTHXY_OFFSET: - case R200_EMIT_RE_AUX_SCISSOR_CNTL: - case R200_EMIT_RE_SCISSOR_TL_0: - case R200_EMIT_RE_SCISSOR_TL_1: - case R200_EMIT_RE_SCISSOR_TL_2: - case R200_EMIT_SE_VAP_CNTL_STATUS: - case R200_EMIT_SE_VTX_STATE_CNTL: - case R200_EMIT_RE_POINTSIZE: - case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0: - case R200_EMIT_PP_CUBIC_FACES_0: - case R200_EMIT_PP_CUBIC_FACES_1: - case R200_EMIT_PP_CUBIC_FACES_2: - case R200_EMIT_PP_CUBIC_FACES_3: - case R200_EMIT_PP_CUBIC_FACES_4: - case R200_EMIT_PP_CUBIC_FACES_5: - case RADEON_EMIT_PP_TEX_SIZE_0: - case RADEON_EMIT_PP_TEX_SIZE_1: - case RADEON_EMIT_PP_TEX_SIZE_2: - case R200_EMIT_RB3D_BLENDCOLOR: - case R200_EMIT_TCL_POINT_SPRITE_CNTL: - case RADEON_EMIT_PP_CUBIC_FACES_0: - case RADEON_EMIT_PP_CUBIC_FACES_1: - case RADEON_EMIT_PP_CUBIC_FACES_2: - case R200_EMIT_PP_TRI_PERF_CNTL: - case R200_EMIT_PP_AFS_0: - case R200_EMIT_PP_AFS_1: - case R200_EMIT_ATF_TFACTOR: - case R200_EMIT_PP_TXCTLALL_0: - case R200_EMIT_PP_TXCTLALL_1: - case R200_EMIT_PP_TXCTLALL_2: - case R200_EMIT_PP_TXCTLALL_3: - case R200_EMIT_PP_TXCTLALL_4: - case R200_EMIT_PP_TXCTLALL_5: - case R200_EMIT_VAP_PVS_CNTL: - /* These packets don't contain memory offsets */ - break; - - default: - DRM_ERROR("Unknown state packet ID %d\n", id); - return -EINVAL; - } - - return 0; -} - -static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * - dev_priv, - struct drm_file *file_priv, - drm_radeon_kcmd_buffer_t * - cmdbuf, - unsigned int *cmdsz) -{ - u32 *cmd = (u32 *) cmdbuf->buf; - u32 offset, narrays; - int count, i, k; - - *cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16); - - if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) { - DRM_ERROR("Not a type 3 packet\n"); - return -EINVAL; - } - - if (4 * *cmdsz > cmdbuf->bufsz) { - DRM_ERROR("Packet size larger than size of data provided\n"); - return -EINVAL; - } - - switch(cmd[0] & 0xff00) { - /* XXX Are there old drivers needing other packets? */ - - case RADEON_3D_DRAW_IMMD: - case RADEON_3D_DRAW_VBUF: - case RADEON_3D_DRAW_INDX: - case RADEON_WAIT_FOR_IDLE: - case RADEON_CP_NOP: - case RADEON_3D_CLEAR_ZMASK: -/* case RADEON_CP_NEXT_CHAR: - case RADEON_CP_PLY_NEXTSCAN: - case RADEON_CP_SET_SCISSORS: */ /* probably safe but will never need them? */ - /* these packets are safe */ - break; - - case RADEON_CP_3D_DRAW_IMMD_2: - case RADEON_CP_3D_DRAW_VBUF_2: - case RADEON_CP_3D_DRAW_INDX_2: - case RADEON_3D_CLEAR_HIZ: - /* safe but r200 only */ - if ((dev_priv->chip_family < CHIP_R200) || - (dev_priv->chip_family > CHIP_RV280)) { - DRM_ERROR("Invalid 3d packet for non r200-class chip\n"); - return -EINVAL; - } - break; - - case RADEON_3D_LOAD_VBPNTR: - count = (cmd[0] >> 16) & 0x3fff; - - if (count > 18) { /* 12 arrays max */ - DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", - count); - return -EINVAL; - } - - /* carefully check packet contents */ - narrays = cmd[1] & ~0xc000; - k = 0; - i = 2; - while ((k < narrays) && (i < (count + 2))) { - i++; /* skip attribute field */ - if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &cmd[i])) { - DRM_ERROR - ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n", - k, i); - return -EINVAL; - } - k++; - i++; - if (k == narrays) - break; - /* have one more to process, they come in pairs */ - if (radeon_check_and_fixup_offset(dev_priv, - file_priv, &cmd[i])) - { - DRM_ERROR - ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n", - k, i); - return -EINVAL; - } - k++; - i++; - } - /* do the counts match what we expect ? */ - if ((k != narrays) || (i != (count + 2))) { - DRM_ERROR - ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n", - k, i, narrays, count + 1); - return -EINVAL; - } - break; - - case RADEON_3D_RNDR_GEN_INDX_PRIM: - if (dev_priv->chip_family > CHIP_RS200) { - DRM_ERROR("Invalid 3d packet for non-r100-class chip\n"); - return -EINVAL; - } - if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[1])) { - DRM_ERROR("Invalid rndr_gen_indx offset\n"); - return -EINVAL; - } - break; - - case RADEON_CP_INDX_BUFFER: - /* safe but r200 only */ - if ((dev_priv->chip_family < CHIP_R200) || - (dev_priv->chip_family > CHIP_RV280)) { - DRM_ERROR("Invalid 3d packet for non-r200-class chip\n"); - return -EINVAL; - } - if ((cmd[1] & 0x8000ffff) != 0x80000810) { - DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]); - return -EINVAL; - } - if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[2])) { - DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]); - return -EINVAL; - } - break; - - case RADEON_CNTL_HOSTDATA_BLT: - case RADEON_CNTL_PAINT_MULTI: - case RADEON_CNTL_BITBLT_MULTI: - /* MSB of opcode: next DWORD GUI_CNTL */ - if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL - | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { - offset = cmd[2] << 10; - if (radeon_check_and_fixup_offset - (dev_priv, file_priv, &offset)) { - DRM_ERROR("Invalid first packet offset\n"); - return -EINVAL; - } - cmd[2] = (cmd[2] & 0xffc00000) | offset >> 10; - } - - if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) && - (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { - offset = cmd[3] << 10; - if (radeon_check_and_fixup_offset - (dev_priv, file_priv, &offset)) { - DRM_ERROR("Invalid second packet offset\n"); - return -EINVAL; - } - cmd[3] = (cmd[3] & 0xffc00000) | offset >> 10; - } - break; - - default: - DRM_ERROR("Invalid packet type %x\n", cmd[0] & 0xff00); - return -EINVAL; - } - - return 0; -} - -/* ================================================================ - * CP hardware state programming functions - */ - -static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv, - struct drm_clip_rect * box) -{ - RING_LOCALS; - - DRM_DEBUG(" box: x1=%d y1=%d x2=%d y2=%d\n", - box->x1, box->y1, box->x2, box->y2); - - BEGIN_RING(4); - OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); - OUT_RING((box->y1 << 16) | box->x1); - OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); - OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1)); - ADVANCE_RING(); -} - -/* Emit 1.1 state - */ -static int radeon_emit_state(drm_radeon_private_t * dev_priv, - struct drm_file *file_priv, - drm_radeon_context_regs_t * ctx, - drm_radeon_texture_regs_t * tex, - unsigned int dirty) -{ - RING_LOCALS; - DRM_DEBUG("dirty=0x%08x\n", dirty); - - if (dirty & RADEON_UPLOAD_CONTEXT) { - if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &ctx->rb3d_depthoffset)) { - DRM_ERROR("Invalid depth buffer offset\n"); - return -EINVAL; - } - - if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &ctx->rb3d_coloroffset)) { - DRM_ERROR("Invalid depth buffer offset\n"); - return -EINVAL; - } - - BEGIN_RING(14); - OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6)); - OUT_RING(ctx->pp_misc); - OUT_RING(ctx->pp_fog_color); - OUT_RING(ctx->re_solid_color); - OUT_RING(ctx->rb3d_blendcntl); - OUT_RING(ctx->rb3d_depthoffset); - OUT_RING(ctx->rb3d_depthpitch); - OUT_RING(ctx->rb3d_zstencilcntl); - OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2)); - OUT_RING(ctx->pp_cntl); - OUT_RING(ctx->rb3d_cntl); - OUT_RING(ctx->rb3d_coloroffset); - OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); - OUT_RING(ctx->rb3d_colorpitch); - ADVANCE_RING(); - } - - if (dirty & RADEON_UPLOAD_VERTFMT) { - BEGIN_RING(2); - OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0)); - OUT_RING(ctx->se_coord_fmt); - ADVANCE_RING(); - } - - if (dirty & RADEON_UPLOAD_LINE) { - BEGIN_RING(5); - OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1)); - OUT_RING(ctx->re_line_pattern); - OUT_RING(ctx->re_line_state); - OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0)); - OUT_RING(ctx->se_line_width); - ADVANCE_RING(); - } - - if (dirty & RADEON_UPLOAD_BUMPMAP) { - BEGIN_RING(5); - OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0)); - OUT_RING(ctx->pp_lum_matrix); - OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1)); - OUT_RING(ctx->pp_rot_matrix_0); - OUT_RING(ctx->pp_rot_matrix_1); - ADVANCE_RING(); - } - - if (dirty & RADEON_UPLOAD_MASKS) { - BEGIN_RING(4); - OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2)); - OUT_RING(ctx->rb3d_stencilrefmask); - OUT_RING(ctx->rb3d_ropcntl); - OUT_RING(ctx->rb3d_planemask); - ADVANCE_RING(); - } - - if (dirty & RADEON_UPLOAD_VIEWPORT) { - BEGIN_RING(7); - OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5)); - OUT_RING(ctx->se_vport_xscale); - OUT_RING(ctx->se_vport_xoffset); - OUT_RING(ctx->se_vport_yscale); - OUT_RING(ctx->se_vport_yoffset); - OUT_RING(ctx->se_vport_zscale); - OUT_RING(ctx->se_vport_zoffset); - ADVANCE_RING(); - } - - if (dirty & RADEON_UPLOAD_SETUP) { - BEGIN_RING(4); - OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0)); - OUT_RING(ctx->se_cntl); - OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0)); - OUT_RING(ctx->se_cntl_status); - ADVANCE_RING(); - } - - if (dirty & RADEON_UPLOAD_MISC) { - BEGIN_RING(2); - OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0)); - OUT_RING(ctx->re_misc); - ADVANCE_RING(); - } - - if (dirty & RADEON_UPLOAD_TEX0) { - if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &tex[0].pp_txoffset)) { - DRM_ERROR("Invalid texture offset for unit 0\n"); - return -EINVAL; - } - - BEGIN_RING(9); - OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5)); - OUT_RING(tex[0].pp_txfilter); - OUT_RING(tex[0].pp_txformat); - OUT_RING(tex[0].pp_txoffset); - OUT_RING(tex[0].pp_txcblend); - OUT_RING(tex[0].pp_txablend); - OUT_RING(tex[0].pp_tfactor); - OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0)); - OUT_RING(tex[0].pp_border_color); - ADVANCE_RING(); - } - - if (dirty & RADEON_UPLOAD_TEX1) { - if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &tex[1].pp_txoffset)) { - DRM_ERROR("Invalid texture offset for unit 1\n"); - return -EINVAL; - } - - BEGIN_RING(9); - OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5)); - OUT_RING(tex[1].pp_txfilter); - OUT_RING(tex[1].pp_txformat); - OUT_RING(tex[1].pp_txoffset); - OUT_RING(tex[1].pp_txcblend); - OUT_RING(tex[1].pp_txablend); - OUT_RING(tex[1].pp_tfactor); - OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0)); - OUT_RING(tex[1].pp_border_color); - ADVANCE_RING(); - } - - if (dirty & RADEON_UPLOAD_TEX2) { - if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &tex[2].pp_txoffset)) { - DRM_ERROR("Invalid texture offset for unit 2\n"); - return -EINVAL; - } - - BEGIN_RING(9); - OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5)); - OUT_RING(tex[2].pp_txfilter); - OUT_RING(tex[2].pp_txformat); - OUT_RING(tex[2].pp_txoffset); - OUT_RING(tex[2].pp_txcblend); - OUT_RING(tex[2].pp_txablend); - OUT_RING(tex[2].pp_tfactor); - OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0)); - OUT_RING(tex[2].pp_border_color); - ADVANCE_RING(); - } - - return 0; -} - -/* Emit 1.2 state - */ -static int radeon_emit_state2(drm_radeon_private_t * dev_priv, - struct drm_file *file_priv, - drm_radeon_state_t * state) -{ - RING_LOCALS; - - if (state->dirty & RADEON_UPLOAD_ZBIAS) { - BEGIN_RING(3); - OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1)); - OUT_RING(state->context2.se_zbias_factor); - OUT_RING(state->context2.se_zbias_constant); - ADVANCE_RING(); - } - - return radeon_emit_state(dev_priv, file_priv, &state->context, - state->tex, state->dirty); -} - -/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in - * 1.3 cmdbuffers allow all previous state to be updated as well as - * the tcl scalar and vector areas. - */ -static struct { - int start; - int len; - const char *name; -} packet[RADEON_MAX_STATE_PACKETS] = { - {RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, - {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, - {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, - {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, - {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, - {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, - {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, - {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, - {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, - {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, - {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, - {RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, - {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, - {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, - {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, - {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, - {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, - {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, - {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, - {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, - {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17, - "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, - {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, - {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, - {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, - {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, - {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, - {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, - {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, - {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, - {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"}, - {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, - {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, - {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, - {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, - {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, - {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"}, - {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, - {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, - {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, - {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, - {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, - {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, - {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, - {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, - {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, - {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, - {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, - {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, - {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, - {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, - "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"}, - {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, - {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, - {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, - {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, - {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, - {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, - {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, - {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, - {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, - {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, - {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, - "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, - {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */ - {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */ - {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, - {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, - {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, - {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, - {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, - {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, - {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, - {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, - {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, - {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, - {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, - {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, - {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, - {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, - {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"}, - {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, - {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, - {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, - {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, - {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, - {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, - {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, - {R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */ - {R200_PP_AFS_1, 32, "R200_PP_AFS_1"}, - {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, - {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, - {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, - {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, - {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, - {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, - {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, - {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, -}; - -/* ================================================================ - * Performance monitoring functions - */ - -static void radeon_clear_box(drm_radeon_private_t * dev_priv, - int x, int y, int w, int h, int r, int g, int b) -{ - u32 color; - RING_LOCALS; - - x += dev_priv->sarea_priv->boxes[0].x1; - y += dev_priv->sarea_priv->boxes[0].y1; - - switch (dev_priv->color_fmt) { - case RADEON_COLOR_FORMAT_RGB565: - color = (((r & 0xf8) << 8) | - ((g & 0xfc) << 3) | ((b & 0xf8) >> 3)); - break; - case RADEON_COLOR_FORMAT_ARGB8888: - default: - color = (((0xff) << 24) | (r << 16) | (g << 8) | b); - break; - } - - BEGIN_RING(4); - RADEON_WAIT_UNTIL_3D_IDLE(); - OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); - OUT_RING(0xffffffff); - ADVANCE_RING(); - - BEGIN_RING(6); - - OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); - OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS); - - if (dev_priv->sarea_priv->pfCurrentPage == 1) { - OUT_RING(dev_priv->front_pitch_offset); - } else { - OUT_RING(dev_priv->back_pitch_offset); - } - - OUT_RING(color); - - OUT_RING((x << 16) | y); - OUT_RING((w << 16) | h); - - ADVANCE_RING(); -} - -static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv) -{ - /* Collapse various things into a wait flag -- trying to - * guess if userspase slept -- better just to have them tell us. - */ - if (dev_priv->stats.last_frame_reads > 1 || - dev_priv->stats.last_clear_reads > dev_priv->stats.clears) { - dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - } - - if (dev_priv->stats.freelist_loops) { - dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - } - - /* Purple box for page flipping - */ - if (dev_priv->stats.boxes & RADEON_BOX_FLIP) - radeon_clear_box(dev_priv, 4, 4, 8, 8, 255, 0, 255); - - /* Red box if we have to wait for idle at any point - */ - if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE) - radeon_clear_box(dev_priv, 16, 4, 8, 8, 255, 0, 0); - - /* Blue box: lost context? - */ - - /* Yellow box for texture swaps - */ - if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD) - radeon_clear_box(dev_priv, 40, 4, 8, 8, 255, 255, 0); - - /* Green box if hardware never idles (as far as we can tell) - */ - if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) - radeon_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0); - - /* Draw bars indicating number of buffers allocated - * (not a great measure, easily confused) - */ - if (dev_priv->stats.requested_bufs) { - if (dev_priv->stats.requested_bufs > 100) - dev_priv->stats.requested_bufs = 100; - - radeon_clear_box(dev_priv, 4, 16, - dev_priv->stats.requested_bufs, 4, - 196, 128, 128); - } - - memset(&dev_priv->stats, 0, sizeof(dev_priv->stats)); - -} - -/* ================================================================ - * CP command dispatch functions - */ - -static void radeon_cp_dispatch_clear(struct drm_device * dev, - drm_radeon_clear_t * clear, - drm_radeon_clear_rect_t * depth_boxes) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear; - int nbox = sarea_priv->nbox; - struct drm_clip_rect *pbox = sarea_priv->boxes; - unsigned int flags = clear->flags; - u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0; - int i; - RING_LOCALS; - DRM_DEBUG("flags = 0x%x\n", flags); - - dev_priv->stats.clears++; - - if (dev_priv->sarea_priv->pfCurrentPage == 1) { - unsigned int tmp = flags; - - flags &= ~(RADEON_FRONT | RADEON_BACK); - if (tmp & RADEON_FRONT) - flags |= RADEON_BACK; - if (tmp & RADEON_BACK) - flags |= RADEON_FRONT; - } - - if (flags & (RADEON_FRONT | RADEON_BACK)) { - - BEGIN_RING(4); - - /* Ensure the 3D stream is idle before doing a - * 2D fill to clear the front or back buffer. - */ - RADEON_WAIT_UNTIL_3D_IDLE(); - - OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); - OUT_RING(clear->color_mask); - - ADVANCE_RING(); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->ctx_owner = 0; - - for (i = 0; i < nbox; i++) { - int x = pbox[i].x1; - int y = pbox[i].y1; - int w = pbox[i].x2 - x; - int h = pbox[i].y2 - y; - - DRM_DEBUG("%d,%d-%d,%d flags 0x%x\n", - x, y, w, h, flags); - - if (flags & RADEON_FRONT) { - BEGIN_RING(6); - - OUT_RING(CP_PACKET3 - (RADEON_CNTL_PAINT_MULTI, 4)); - OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_SOLID_COLOR | - (dev_priv-> - color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_P | - RADEON_GMC_CLR_CMP_CNTL_DIS); - - OUT_RING(dev_priv->front_pitch_offset); - OUT_RING(clear->clear_color); - - OUT_RING((x << 16) | y); - OUT_RING((w << 16) | h); - - ADVANCE_RING(); - } - - if (flags & RADEON_BACK) { - BEGIN_RING(6); - - OUT_RING(CP_PACKET3 - (RADEON_CNTL_PAINT_MULTI, 4)); - OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_SOLID_COLOR | - (dev_priv-> - color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_P | - RADEON_GMC_CLR_CMP_CNTL_DIS); - - OUT_RING(dev_priv->back_pitch_offset); - OUT_RING(clear->clear_color); - - OUT_RING((x << 16) | y); - OUT_RING((w << 16) | h); - - ADVANCE_RING(); - } - } - } - - /* hyper z clear */ - /* no docs available, based on reverse engeneering by Stephane Marchesin */ - if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) - && (flags & RADEON_CLEAR_FASTZ)) { - - int i; - int depthpixperline = - dev_priv->depth_fmt == - RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch / - 2) : (dev_priv-> - depth_pitch / 4); - - u32 clearmask; - - u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth | - ((clear->depth_mask & 0xff) << 24); - - /* Make sure we restore the 3D state next time. - * we haven't touched any "normal" state - still need this? - */ - dev_priv->sarea_priv->ctx_owner = 0; - - if ((dev_priv->flags & RADEON_HAS_HIERZ) - && (flags & RADEON_USE_HIERZ)) { - /* FIXME : reverse engineer that for Rx00 cards */ - /* FIXME : the mask supposedly contains low-res z values. So can't set - just to the max (0xff? or actually 0x3fff?), need to take z clear - value into account? */ - /* pattern seems to work for r100, though get slight - rendering errors with glxgears. If hierz is not enabled for r100, - only 4 bits which indicate clear (15,16,31,32, all zero) matter, the - other ones are ignored, and the same clear mask can be used. That's - very different behaviour than R200 which needs different clear mask - and different number of tiles to clear if hierz is enabled or not !?! - */ - clearmask = (0xff << 22) | (0xff << 6) | 0x003f003f; - } else { - /* clear mask : chooses the clearing pattern. - rv250: could be used to clear only parts of macrotiles - (but that would get really complicated...)? - bit 0 and 1 (either or both of them ?!?!) are used to - not clear tile (or maybe one of the bits indicates if the tile is - compressed or not), bit 2 and 3 to not clear tile 1,...,. - Pattern is as follows: - | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29| - bits ------------------------------------------------- - | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31| - rv100: clearmask covers 2x8 4x1 tiles, but one clear still - covers 256 pixels ?!? - */ - clearmask = 0x0; - } - - BEGIN_RING(8); - RADEON_WAIT_UNTIL_2D_IDLE(); - OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE, - tempRB3D_DEPTHCLEARVALUE); - /* what offset is this exactly ? */ - OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0); - /* need ctlstat, otherwise get some strange black flickering */ - OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT, - RADEON_RB3D_ZC_FLUSH_ALL); - ADVANCE_RING(); - - for (i = 0; i < nbox; i++) { - int tileoffset, nrtilesx, nrtilesy, j; - /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */ - if ((dev_priv->flags & RADEON_HAS_HIERZ) - && (dev_priv->chip_family < CHIP_R200)) { - /* FIXME : figure this out for r200 (when hierz is enabled). Or - maybe r200 actually doesn't need to put the low-res z value into - the tile cache like r100, but just needs to clear the hi-level z-buffer? - Works for R100, both with hierz and without. - R100 seems to operate on 2x1 8x8 tiles, but... - odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially - problematic with resolutions which are not 64 pix aligned? */ - tileoffset = - ((pbox[i].y1 >> 3) * depthpixperline + - pbox[i].x1) >> 6; - nrtilesx = - ((pbox[i].x2 & ~63) - - (pbox[i].x1 & ~63)) >> 4; - nrtilesy = - (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); - for (j = 0; j <= nrtilesy; j++) { - BEGIN_RING(4); - OUT_RING(CP_PACKET3 - (RADEON_3D_CLEAR_ZMASK, 2)); - /* first tile */ - OUT_RING(tileoffset * 8); - /* the number of tiles to clear */ - OUT_RING(nrtilesx + 4); - /* clear mask : chooses the clearing pattern. */ - OUT_RING(clearmask); - ADVANCE_RING(); - tileoffset += depthpixperline >> 6; - } - } else if ((dev_priv->chip_family >= CHIP_R200) && - (dev_priv->chip_family <= CHIP_RV280)) { - /* works for rv250. */ - /* find first macro tile (8x2 4x4 z-pixels on rv250) */ - tileoffset = - ((pbox[i].y1 >> 3) * depthpixperline + - pbox[i].x1) >> 5; - nrtilesx = - (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5); - nrtilesy = - (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); - for (j = 0; j <= nrtilesy; j++) { - BEGIN_RING(4); - OUT_RING(CP_PACKET3 - (RADEON_3D_CLEAR_ZMASK, 2)); - /* first tile */ - /* judging by the first tile offset needed, could possibly - directly address/clear 4x4 tiles instead of 8x2 * 4x4 - macro tiles, though would still need clear mask for - right/bottom if truely 4x4 granularity is desired ? */ - OUT_RING(tileoffset * 16); - /* the number of tiles to clear */ - OUT_RING(nrtilesx + 1); - /* clear mask : chooses the clearing pattern. */ - OUT_RING(clearmask); - ADVANCE_RING(); - tileoffset += depthpixperline >> 5; - } - } else { /* rv 100 */ - /* rv100 might not need 64 pix alignment, who knows */ - /* offsets are, hmm, weird */ - tileoffset = - ((pbox[i].y1 >> 4) * depthpixperline + - pbox[i].x1) >> 6; - nrtilesx = - ((pbox[i].x2 & ~63) - - (pbox[i].x1 & ~63)) >> 4; - nrtilesy = - (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4); - for (j = 0; j <= nrtilesy; j++) { - BEGIN_RING(4); - OUT_RING(CP_PACKET3 - (RADEON_3D_CLEAR_ZMASK, 2)); - OUT_RING(tileoffset * 128); - /* the number of tiles to clear */ - OUT_RING(nrtilesx + 4); - /* clear mask : chooses the clearing pattern. */ - OUT_RING(clearmask); - ADVANCE_RING(); - tileoffset += depthpixperline >> 6; - } - } - } - - /* TODO don't always clear all hi-level z tiles */ - if ((dev_priv->flags & RADEON_HAS_HIERZ) - && ((dev_priv->chip_family >= CHIP_R200) && - (dev_priv->chip_family <= CHIP_RV280)) - && (flags & RADEON_USE_HIERZ)) - /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */ - /* FIXME : the mask supposedly contains low-res z values. So can't set - just to the max (0xff? or actually 0x3fff?), need to take z clear - value into account? */ - { - BEGIN_RING(4); - OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2)); - OUT_RING(0x0); /* First tile */ - OUT_RING(0x3cc0); - OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f); - ADVANCE_RING(); - } - } - - /* We have to clear the depth and/or stencil buffers by - * rendering a quad into just those buffers. Thus, we have to - * make sure the 3D engine is configured correctly. - */ - else if ((dev_priv->chip_family >= CHIP_R200) && - (dev_priv->chip_family <= CHIP_RV280) && - (flags & (RADEON_DEPTH | RADEON_STENCIL))) { - - int tempPP_CNTL; - int tempRE_CNTL; - int tempRB3D_CNTL; - int tempRB3D_ZSTENCILCNTL; - int tempRB3D_STENCILREFMASK; - int tempRB3D_PLANEMASK; - int tempSE_CNTL; - int tempSE_VTE_CNTL; - int tempSE_VTX_FMT_0; - int tempSE_VTX_FMT_1; - int tempSE_VAP_CNTL; - int tempRE_AUX_SCISSOR_CNTL; - - tempPP_CNTL = 0; - tempRE_CNTL = 0; - - tempRB3D_CNTL = depth_clear->rb3d_cntl; - - tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; - tempRB3D_STENCILREFMASK = 0x0; - - tempSE_CNTL = depth_clear->se_cntl; - - /* Disable TCL */ - - tempSE_VAP_CNTL = ( /* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */ - (0x9 << - SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT)); - - tempRB3D_PLANEMASK = 0x0; - - tempRE_AUX_SCISSOR_CNTL = 0x0; - - tempSE_VTE_CNTL = - SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK; - - /* Vertex format (X, Y, Z, W) */ - tempSE_VTX_FMT_0 = - SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK | - SE_VTX_FMT_0__VTX_W0_PRESENT_MASK; - tempSE_VTX_FMT_1 = 0x0; - - /* - * Depth buffer specific enables - */ - if (flags & RADEON_DEPTH) { - /* Enable depth buffer */ - tempRB3D_CNTL |= RADEON_Z_ENABLE; - } else { - /* Disable depth buffer */ - tempRB3D_CNTL &= ~RADEON_Z_ENABLE; - } - - /* - * Stencil buffer specific enables - */ - if (flags & RADEON_STENCIL) { - tempRB3D_CNTL |= RADEON_STENCIL_ENABLE; - tempRB3D_STENCILREFMASK = clear->depth_mask; - } else { - tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE; - tempRB3D_STENCILREFMASK = 0x00000000; - } - - if (flags & RADEON_USE_COMP_ZBUF) { - tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | - RADEON_Z_DECOMPRESSION_ENABLE; - } - if (flags & RADEON_USE_HIERZ) { - tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; - } - - BEGIN_RING(26); - RADEON_WAIT_UNTIL_2D_IDLE(); - - OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL); - OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL); - OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL); - OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL); - OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, - tempRB3D_STENCILREFMASK); - OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK); - OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL); - OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL); - OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0); - OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1); - OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL); - OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL); - ADVANCE_RING(); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->ctx_owner = 0; - - for (i = 0; i < nbox; i++) { - - /* Funny that this should be required -- - * sets top-left? - */ - radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); - - BEGIN_RING(14); - OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12)); - OUT_RING((RADEON_PRIM_TYPE_RECT_LIST | - RADEON_PRIM_WALK_RING | - (3 << RADEON_NUM_VERTICES_SHIFT))); - OUT_RING(depth_boxes[i].ui[CLEAR_X1]); - OUT_RING(depth_boxes[i].ui[CLEAR_Y1]); - OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); - OUT_RING(0x3f800000); - OUT_RING(depth_boxes[i].ui[CLEAR_X1]); - OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); - OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); - OUT_RING(0x3f800000); - OUT_RING(depth_boxes[i].ui[CLEAR_X2]); - OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); - OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); - OUT_RING(0x3f800000); - ADVANCE_RING(); - } - } else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) { - - int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; - - rb3d_cntl = depth_clear->rb3d_cntl; - - if (flags & RADEON_DEPTH) { - rb3d_cntl |= RADEON_Z_ENABLE; - } else { - rb3d_cntl &= ~RADEON_Z_ENABLE; - } - - if (flags & RADEON_STENCIL) { - rb3d_cntl |= RADEON_STENCIL_ENABLE; - rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */ - } else { - rb3d_cntl &= ~RADEON_STENCIL_ENABLE; - rb3d_stencilrefmask = 0x00000000; - } - - if (flags & RADEON_USE_COMP_ZBUF) { - tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | - RADEON_Z_DECOMPRESSION_ENABLE; - } - if (flags & RADEON_USE_HIERZ) { - tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; - } - - BEGIN_RING(13); - RADEON_WAIT_UNTIL_2D_IDLE(); - - OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1)); - OUT_RING(0x00000000); - OUT_RING(rb3d_cntl); - - OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL); - OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask); - OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000); - OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl); - ADVANCE_RING(); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->ctx_owner = 0; - - for (i = 0; i < nbox; i++) { - - /* Funny that this should be required -- - * sets top-left? - */ - radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); - - BEGIN_RING(15); - - OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13)); - OUT_RING(RADEON_VTX_Z_PRESENT | - RADEON_VTX_PKCOLOR_PRESENT); - OUT_RING((RADEON_PRIM_TYPE_RECT_LIST | - RADEON_PRIM_WALK_RING | - RADEON_MAOS_ENABLE | - RADEON_VTX_FMT_RADEON_MODE | - (3 << RADEON_NUM_VERTICES_SHIFT))); - - OUT_RING(depth_boxes[i].ui[CLEAR_X1]); - OUT_RING(depth_boxes[i].ui[CLEAR_Y1]); - OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); - OUT_RING(0x0); - - OUT_RING(depth_boxes[i].ui[CLEAR_X1]); - OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); - OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); - OUT_RING(0x0); - - OUT_RING(depth_boxes[i].ui[CLEAR_X2]); - OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); - OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); - OUT_RING(0x0); - - ADVANCE_RING(); - } - } - - /* Increment the clear counter. The client-side 3D driver must - * wait on this value before performing the clear ioctl. We - * need this because the card's so damned fast... - */ - dev_priv->sarea_priv->last_clear++; - - BEGIN_RING(4); - - RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear); - RADEON_WAIT_UNTIL_IDLE(); - - ADVANCE_RING(); -} - -static void radeon_cp_dispatch_swap(struct drm_device * dev) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - int nbox = sarea_priv->nbox; - struct drm_clip_rect *pbox = sarea_priv->boxes; - int i; - RING_LOCALS; - DRM_DEBUG("\n"); - - /* Do some trivial performance monitoring... - */ - if (dev_priv->do_boxes) - radeon_cp_performance_boxes(dev_priv); - - /* Wait for the 3D stream to idle before dispatching the bitblt. - * This will prevent data corruption between the two streams. - */ - BEGIN_RING(2); - - RADEON_WAIT_UNTIL_3D_IDLE(); - - ADVANCE_RING(); - - for (i = 0; i < nbox; i++) { - int x = pbox[i].x1; - int y = pbox[i].y1; - int w = pbox[i].x2 - x; - int h = pbox[i].y2 - y; - - DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h); - - BEGIN_RING(9); - - OUT_RING(CP_PACKET0(RADEON_DP_GUI_MASTER_CNTL, 0)); - OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | - RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_NONE | - (dev_priv->color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_S | - RADEON_DP_SRC_SOURCE_MEMORY | - RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); - - /* Make this work even if front & back are flipped: - */ - OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1)); - if (dev_priv->sarea_priv->pfCurrentPage == 0) { - OUT_RING(dev_priv->back_pitch_offset); - OUT_RING(dev_priv->front_pitch_offset); - } else { - OUT_RING(dev_priv->front_pitch_offset); - OUT_RING(dev_priv->back_pitch_offset); - } - - OUT_RING(CP_PACKET0(RADEON_SRC_X_Y, 2)); - OUT_RING((x << 16) | y); - OUT_RING((x << 16) | y); - OUT_RING((w << 16) | h); - - ADVANCE_RING(); - } - - /* Increment the frame counter. The client-side 3D driver must - * throttle the framerate by waiting for this value before - * performing the swapbuffer ioctl. - */ - dev_priv->sarea_priv->last_frame++; - - BEGIN_RING(4); - - RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame); - RADEON_WAIT_UNTIL_2D_IDLE(); - - ADVANCE_RING(); -} - -static void radeon_cp_dispatch_flip(struct drm_device * dev) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - struct drm_sarea *sarea = (struct drm_sarea *) dev_priv->sarea->handle; - int offset = (dev_priv->sarea_priv->pfCurrentPage == 1) - ? dev_priv->front_offset : dev_priv->back_offset; - RING_LOCALS; - DRM_DEBUG("pfCurrentPage=%d\n", - dev_priv->sarea_priv->pfCurrentPage); - - /* Do some trivial performance monitoring... - */ - if (dev_priv->do_boxes) { - dev_priv->stats.boxes |= RADEON_BOX_FLIP; - radeon_cp_performance_boxes(dev_priv); - } - - /* Update the frame offsets for both CRTCs - */ - BEGIN_RING(6); - - RADEON_WAIT_UNTIL_3D_IDLE(); - OUT_RING_REG(RADEON_CRTC_OFFSET, - ((sarea->frame.y * dev_priv->front_pitch + - sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7) - + offset); - OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base - + offset); - - ADVANCE_RING(); - - /* Increment the frame counter. The client-side 3D driver must - * throttle the framerate by waiting for this value before - * performing the swapbuffer ioctl. - */ - dev_priv->sarea_priv->last_frame++; - dev_priv->sarea_priv->pfCurrentPage = - 1 - dev_priv->sarea_priv->pfCurrentPage; - - BEGIN_RING(2); - - RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame); - - ADVANCE_RING(); -} - -static int bad_prim_vertex_nr(int primitive, int nr) -{ - switch (primitive & RADEON_PRIM_TYPE_MASK) { - case RADEON_PRIM_TYPE_NONE: - case RADEON_PRIM_TYPE_POINT: - return nr < 1; - case RADEON_PRIM_TYPE_LINE: - return (nr & 1) || nr == 0; - case RADEON_PRIM_TYPE_LINE_STRIP: - return nr < 2; - case RADEON_PRIM_TYPE_TRI_LIST: - case RADEON_PRIM_TYPE_3VRT_POINT_LIST: - case RADEON_PRIM_TYPE_3VRT_LINE_LIST: - case RADEON_PRIM_TYPE_RECT_LIST: - return nr % 3 || nr == 0; - case RADEON_PRIM_TYPE_TRI_FAN: - case RADEON_PRIM_TYPE_TRI_STRIP: - return nr < 3; - default: - return 1; - } -} - -typedef struct { - unsigned int start; - unsigned int finish; - unsigned int prim; - unsigned int numverts; - unsigned int offset; - unsigned int vc_format; -} drm_radeon_tcl_prim_t; - -static void radeon_cp_dispatch_vertex(struct drm_device * dev, - struct drm_buf * buf, - drm_radeon_tcl_prim_t * prim) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start; - int numverts = (int)prim->numverts; - int nbox = sarea_priv->nbox; - int i = 0; - RING_LOCALS; - - DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n", - prim->prim, - prim->vc_format, prim->start, prim->finish, prim->numverts); - - if (bad_prim_vertex_nr(prim->prim, prim->numverts)) { - DRM_ERROR("bad prim %x numverts %d\n", - prim->prim, prim->numverts); - return; - } - - do { - /* Emit the next cliprect */ - if (i < nbox) { - radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); - } - - /* Emit the vertex buffer rendering commands */ - BEGIN_RING(5); - - OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3)); - OUT_RING(offset); - OUT_RING(numverts); - OUT_RING(prim->vc_format); - OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST | - RADEON_COLOR_ORDER_RGBA | - RADEON_VTX_FMT_RADEON_MODE | - (numverts << RADEON_NUM_VERTICES_SHIFT)); - - ADVANCE_RING(); - - i++; - } while (i < nbox); -} - -static void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_buf_priv_t *buf_priv = buf->dev_private; - RING_LOCALS; - - buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; - - /* Emit the vertex buffer age */ - BEGIN_RING(2); - RADEON_DISPATCH_AGE(buf_priv->age); - ADVANCE_RING(); - - buf->pending = 1; - buf->used = 0; -} - -static void radeon_cp_dispatch_indirect(struct drm_device * dev, - struct drm_buf * buf, int start, int end) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - RING_LOCALS; - DRM_DEBUG("buf=%d s=0x%x e=0x%x\n", buf->idx, start, end); - - if (start != end) { - int offset = (dev_priv->gart_buffers_offset - + buf->offset + start); - int dwords = (end - start + 3) / sizeof(u32); - - /* Indirect buffer data must be an even number of - * dwords, so if we've been given an odd number we must - * pad the data with a Type-2 CP packet. - */ - if (dwords & 1) { - u32 *data = (u32 *) - ((char *)dev->agp_buffer_map->handle - + buf->offset + start); - data[dwords++] = RADEON_CP_PACKET2; - } - - /* Fire off the indirect buffer */ - BEGIN_RING(3); - - OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1)); - OUT_RING(offset); - OUT_RING(dwords); - - ADVANCE_RING(); - } -} - -static void radeon_cp_dispatch_indices(struct drm_device * dev, - struct drm_buf * elt_buf, - drm_radeon_tcl_prim_t * prim) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - int offset = dev_priv->gart_buffers_offset + prim->offset; - u32 *data; - int dwords; - int i = 0; - int start = prim->start + RADEON_INDEX_PRIM_OFFSET; - int count = (prim->finish - start) / sizeof(u16); - int nbox = sarea_priv->nbox; - - DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n", - prim->prim, - prim->vc_format, - prim->start, prim->finish, prim->offset, prim->numverts); - - if (bad_prim_vertex_nr(prim->prim, count)) { - DRM_ERROR("bad prim %x count %d\n", prim->prim, count); - return; - } - - if (start >= prim->finish || (prim->start & 0x7)) { - DRM_ERROR("buffer prim %d\n", prim->prim); - return; - } - - dwords = (prim->finish - prim->start + 3) / sizeof(u32); - - data = (u32 *) ((char *)dev->agp_buffer_map->handle + - elt_buf->offset + prim->start); - - data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2); - data[1] = offset; - data[2] = prim->numverts; - data[3] = prim->vc_format; - data[4] = (prim->prim | - RADEON_PRIM_WALK_IND | - RADEON_COLOR_ORDER_RGBA | - RADEON_VTX_FMT_RADEON_MODE | - (count << RADEON_NUM_VERTICES_SHIFT)); - - do { - if (i < nbox) - radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); - - radeon_cp_dispatch_indirect(dev, elt_buf, - prim->start, prim->finish); - - i++; - } while (i < nbox); - -} - -#define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE - -static int radeon_cp_dispatch_texture(struct drm_device * dev, - struct drm_file *file_priv, - drm_radeon_texture_t * tex, - drm_radeon_tex_image_t * image) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - struct drm_buf *buf; - u32 format; - u32 *buffer; - const u8 __user *data; - int size, dwords, tex_width, blit_width, spitch; - u32 height; - int i; - u32 texpitch, microtile; - u32 offset, byte_offset; - RING_LOCALS; - - if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) { - DRM_ERROR("Invalid destination offset\n"); - return -EINVAL; - } - - dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD; - - /* Flush the pixel cache. This ensures no pixel data gets mixed - * up with the texture data from the host data blit, otherwise - * part of the texture image may be corrupted. - */ - BEGIN_RING(4); - RADEON_FLUSH_CACHE(); - RADEON_WAIT_UNTIL_IDLE(); - ADVANCE_RING(); - - /* The compiler won't optimize away a division by a variable, - * even if the only legal values are powers of two. Thus, we'll - * use a shift instead. - */ - switch (tex->format) { - case RADEON_TXFORMAT_ARGB8888: - case RADEON_TXFORMAT_RGBA8888: - format = RADEON_COLOR_FORMAT_ARGB8888; - tex_width = tex->width * 4; - blit_width = image->width * 4; - break; - case RADEON_TXFORMAT_AI88: - case RADEON_TXFORMAT_ARGB1555: - case RADEON_TXFORMAT_RGB565: - case RADEON_TXFORMAT_ARGB4444: - case RADEON_TXFORMAT_VYUY422: - case RADEON_TXFORMAT_YVYU422: - format = RADEON_COLOR_FORMAT_RGB565; - tex_width = tex->width * 2; - blit_width = image->width * 2; - break; - case RADEON_TXFORMAT_I8: - case RADEON_TXFORMAT_RGB332: - format = RADEON_COLOR_FORMAT_CI8; - tex_width = tex->width * 1; - blit_width = image->width * 1; - break; - default: - DRM_ERROR("invalid texture format %d\n", tex->format); - return -EINVAL; - } - spitch = blit_width >> 6; - if (spitch == 0 && image->height > 1) - return -EINVAL; - - texpitch = tex->pitch; - if ((texpitch << 22) & RADEON_DST_TILE_MICRO) { - microtile = 1; - if (tex_width < 64) { - texpitch &= ~(RADEON_DST_TILE_MICRO >> 22); - /* we got tiled coordinates, untile them */ - image->x *= 2; - } - } else - microtile = 0; - - /* this might fail for zero-sized uploads - are those illegal? */ - if (!radeon_check_offset(dev_priv, tex->offset + image->height * - blit_width - 1)) { - DRM_ERROR("Invalid final destination offset\n"); - return -EINVAL; - } - - DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width); - - do { - DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n", - tex->offset >> 10, tex->pitch, tex->format, - image->x, image->y, image->width, image->height); - - /* Make a copy of some parameters in case we have to - * update them for a multi-pass texture blit. - */ - height = image->height; - data = (const u8 __user *)image->data; - - size = height * blit_width; - - if (size > RADEON_MAX_TEXTURE_SIZE) { - height = RADEON_MAX_TEXTURE_SIZE / blit_width; - size = height * blit_width; - } else if (size < 4 && size > 0) { - size = 4; - } else if (size == 0) { - return 0; - } - - buf = radeon_freelist_get(dev); - if (0 && !buf) { - radeon_do_cp_idle(dev_priv); - buf = radeon_freelist_get(dev); - } - if (!buf) { - DRM_DEBUG("EAGAIN\n"); - if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) - return -EFAULT; - return -EAGAIN; - } - - /* Dispatch the indirect buffer. - */ - buffer = - (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); - dwords = size / 4; - -#define RADEON_COPY_MT(_buf, _data, _width) \ - do { \ - if (DRM_COPY_FROM_USER(_buf, _data, (_width))) {\ - DRM_ERROR("EFAULT on pad, %d bytes\n", (_width)); \ - return -EFAULT; \ - } \ - } while(0) - - if (microtile) { - /* texture micro tiling in use, minimum texture width is thus 16 bytes. - however, we cannot use blitter directly for texture width < 64 bytes, - since minimum tex pitch is 64 bytes and we need this to match - the texture width, otherwise the blitter will tile it wrong. - Thus, tiling manually in this case. Additionally, need to special - case tex height = 1, since our actual image will have height 2 - and we need to ensure we don't read beyond the texture size - from user space. */ - if (tex->height == 1) { - if (tex_width >= 64 || tex_width <= 16) { - RADEON_COPY_MT(buffer, data, - (int)(tex_width * sizeof(u32))); - } else if (tex_width == 32) { - RADEON_COPY_MT(buffer, data, 16); - RADEON_COPY_MT(buffer + 8, - data + 16, 16); - } - } else if (tex_width >= 64 || tex_width == 16) { - RADEON_COPY_MT(buffer, data, - (int)(dwords * sizeof(u32))); - } else if (tex_width < 16) { - for (i = 0; i < tex->height; i++) { - RADEON_COPY_MT(buffer, data, tex_width); - buffer += 4; - data += tex_width; - } - } else if (tex_width == 32) { - /* TODO: make sure this works when not fitting in one buffer - (i.e. 32bytes x 2048...) */ - for (i = 0; i < tex->height; i += 2) { - RADEON_COPY_MT(buffer, data, 16); - data += 16; - RADEON_COPY_MT(buffer + 8, data, 16); - data += 16; - RADEON_COPY_MT(buffer + 4, data, 16); - data += 16; - RADEON_COPY_MT(buffer + 12, data, 16); - data += 16; - buffer += 16; - } - } - } else { - if (tex_width >= 32) { - /* Texture image width is larger than the minimum, so we - * can upload it directly. - */ - RADEON_COPY_MT(buffer, data, - (int)(dwords * sizeof(u32))); - } else { - /* Texture image width is less than the minimum, so we - * need to pad out each image scanline to the minimum - * width. - */ - for (i = 0; i < tex->height; i++) { - RADEON_COPY_MT(buffer, data, tex_width); - buffer += 8; - data += tex_width; - } - } - } - -#undef RADEON_COPY_MT - byte_offset = (image->y & ~2047) * blit_width; - buf->file_priv = file_priv; - buf->used = size; - offset = dev_priv->gart_buffers_offset + buf->offset; - BEGIN_RING(9); - OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5)); - OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | - RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_NONE | - (format << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_S | - RADEON_DP_SRC_SOURCE_MEMORY | - RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); - OUT_RING((spitch << 22) | (offset >> 10)); - OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10))); - OUT_RING(0); - OUT_RING((image->x << 16) | (image->y % 2048)); - OUT_RING((image->width << 16) | height); - RADEON_WAIT_UNTIL_2D_IDLE(); - ADVANCE_RING(); - COMMIT_RING(); - - radeon_cp_discard_buffer(dev, buf); - - /* Update the input parameters for next time */ - image->y += height; - image->height -= height; - image->data = (const u8 __user *)image->data + size; - } while (image->height > 0); - - /* Flush the pixel cache after the blit completes. This ensures - * the texture data is written out to memory before rendering - * continues. - */ - BEGIN_RING(4); - RADEON_FLUSH_CACHE(); - RADEON_WAIT_UNTIL_2D_IDLE(); - ADVANCE_RING(); - COMMIT_RING(); - - return 0; -} - -static void radeon_cp_dispatch_stipple(struct drm_device * dev, u32 * stipple) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - int i; - RING_LOCALS; - DRM_DEBUG("\n"); - - BEGIN_RING(35); - - OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0)); - OUT_RING(0x00000000); - - OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31)); - for (i = 0; i < 32; i++) { - OUT_RING(stipple[i]); - } - - ADVANCE_RING(); -} - -static void radeon_apply_surface_regs(int surf_index, - drm_radeon_private_t *dev_priv) -{ - if (!dev_priv->mmio) - return; - - radeon_do_cp_idle(dev_priv); - - RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index, - dev_priv->surfaces[surf_index].flags); - RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index, - dev_priv->surfaces[surf_index].lower); - RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index, - dev_priv->surfaces[surf_index].upper); -} - -/* Allocates a virtual surface - * doesn't always allocate a real surface, will stretch an existing - * surface when possible. - * - * Note that refcount can be at most 2, since during a free refcount=3 - * might mean we have to allocate a new surface which might not always - * be available. - * For example : we allocate three contigous surfaces ABC. If B is - * freed, we suddenly need two surfaces to store A and C, which might - * not always be available. - */ -static int alloc_surface(drm_radeon_surface_alloc_t *new, - drm_radeon_private_t *dev_priv, - struct drm_file *file_priv) -{ - struct radeon_virt_surface *s; - int i; - int virt_surface_index; - uint32_t new_upper, new_lower; - - new_lower = new->address; - new_upper = new_lower + new->size - 1; - - /* sanity check */ - if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) || - ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) != - RADEON_SURF_ADDRESS_FIXED_MASK) - || ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0)) - return -1; - - /* make sure there is no overlap with existing surfaces */ - for (i = 0; i < RADEON_MAX_SURFACES; i++) { - if ((dev_priv->surfaces[i].refcount != 0) && - (((new_lower >= dev_priv->surfaces[i].lower) && - (new_lower < dev_priv->surfaces[i].upper)) || - ((new_lower < dev_priv->surfaces[i].lower) && - (new_upper > dev_priv->surfaces[i].lower)))) { - return -1; - } - } - - /* find a virtual surface */ - for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) - if (dev_priv->virt_surfaces[i].file_priv == 0) - break; - if (i == 2 * RADEON_MAX_SURFACES) { - return -1; - } - virt_surface_index = i; - - /* try to reuse an existing surface */ - for (i = 0; i < RADEON_MAX_SURFACES; i++) { - /* extend before */ - if ((dev_priv->surfaces[i].refcount == 1) && - (new->flags == dev_priv->surfaces[i].flags) && - (new_upper + 1 == dev_priv->surfaces[i].lower)) { - s = &(dev_priv->virt_surfaces[virt_surface_index]); - s->surface_index = i; - s->lower = new_lower; - s->upper = new_upper; - s->flags = new->flags; - s->file_priv = file_priv; - dev_priv->surfaces[i].refcount++; - dev_priv->surfaces[i].lower = s->lower; - radeon_apply_surface_regs(s->surface_index, dev_priv); - return virt_surface_index; - } - - /* extend after */ - if ((dev_priv->surfaces[i].refcount == 1) && - (new->flags == dev_priv->surfaces[i].flags) && - (new_lower == dev_priv->surfaces[i].upper + 1)) { - s = &(dev_priv->virt_surfaces[virt_surface_index]); - s->surface_index = i; - s->lower = new_lower; - s->upper = new_upper; - s->flags = new->flags; - s->file_priv = file_priv; - dev_priv->surfaces[i].refcount++; - dev_priv->surfaces[i].upper = s->upper; - radeon_apply_surface_regs(s->surface_index, dev_priv); - return virt_surface_index; - } - } - - /* okay, we need a new one */ - for (i = 0; i < RADEON_MAX_SURFACES; i++) { - if (dev_priv->surfaces[i].refcount == 0) { - s = &(dev_priv->virt_surfaces[virt_surface_index]); - s->surface_index = i; - s->lower = new_lower; - s->upper = new_upper; - s->flags = new->flags; - s->file_priv = file_priv; - dev_priv->surfaces[i].refcount = 1; - dev_priv->surfaces[i].lower = s->lower; - dev_priv->surfaces[i].upper = s->upper; - dev_priv->surfaces[i].flags = s->flags; - radeon_apply_surface_regs(s->surface_index, dev_priv); - return virt_surface_index; - } - } - - /* we didn't find anything */ - return -1; -} - -static int free_surface(struct drm_file *file_priv, - drm_radeon_private_t * dev_priv, - int lower) -{ - struct radeon_virt_surface *s; - int i; - /* find the virtual surface */ - for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) { - s = &(dev_priv->virt_surfaces[i]); - if (s->file_priv) { - if ((lower == s->lower) && (file_priv == s->file_priv)) - { - if (dev_priv->surfaces[s->surface_index]. - lower == s->lower) - dev_priv->surfaces[s->surface_index]. - lower = s->upper; - - if (dev_priv->surfaces[s->surface_index]. - upper == s->upper) - dev_priv->surfaces[s->surface_index]. - upper = s->lower; - - dev_priv->surfaces[s->surface_index].refcount--; - if (dev_priv->surfaces[s->surface_index]. - refcount == 0) - dev_priv->surfaces[s->surface_index]. - flags = 0; - s->file_priv = NULL; - radeon_apply_surface_regs(s->surface_index, - dev_priv); - return 0; - } - } - } - return 1; -} - -static void radeon_surfaces_release(struct drm_file *file_priv, - drm_radeon_private_t * dev_priv) -{ - int i; - for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) { - if (dev_priv->virt_surfaces[i].file_priv == file_priv) - free_surface(file_priv, dev_priv, - dev_priv->virt_surfaces[i].lower); - } -} - -/* ================================================================ - * IOCTL functions - */ -static int radeon_surface_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_surface_alloc_t *alloc = data; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - if (alloc_surface(alloc, dev_priv, file_priv) == -1) - return -EINVAL; - else - return 0; -} - -static int radeon_surface_free(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_surface_free_t *memfree = data; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - if (free_surface(file_priv, dev_priv, memfree->address)) - return -EINVAL; - else - return 0; -} - -static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_radeon_clear_t *clear = data; - drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - - if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) - sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; - - if (DRM_COPY_FROM_USER(&depth_boxes, clear->depth_boxes, - sarea_priv->nbox * sizeof(depth_boxes[0]))) - return -EFAULT; - - radeon_cp_dispatch_clear(dev, clear, depth_boxes); - - COMMIT_RING(); - return 0; -} - -/* Not sure why this isn't set all the time: - */ -static int radeon_do_init_pageflip(struct drm_device * dev) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - RING_LOCALS; - - DRM_DEBUG("\n"); - - BEGIN_RING(6); - RADEON_WAIT_UNTIL_3D_IDLE(); - OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0)); - OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) | - RADEON_CRTC_OFFSET_FLIP_CNTL); - OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0)); - OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) | - RADEON_CRTC_OFFSET_FLIP_CNTL); - ADVANCE_RING(); - - dev_priv->page_flipping = 1; - - if (dev_priv->sarea_priv->pfCurrentPage != 1) - dev_priv->sarea_priv->pfCurrentPage = 0; - - return 0; -} - -/* Swapping and flipping are different operations, need different ioctls. - * They can & should be intermixed to support multiple 3d windows. - */ -static int radeon_cp_flip(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - - if (!dev_priv->page_flipping) - radeon_do_init_pageflip(dev); - - radeon_cp_dispatch_flip(dev); - - COMMIT_RING(); - return 0; -} - -static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - - if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) - sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; - - radeon_cp_dispatch_swap(dev); - dev_priv->sarea_priv->ctx_owner = 0; - - COMMIT_RING(); - return 0; -} - -static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_sarea_t *sarea_priv; - struct drm_device_dma *dma = dev->dma; - struct drm_buf *buf; - drm_radeon_vertex_t *vertex = data; - drm_radeon_tcl_prim_t prim; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - sarea_priv = dev_priv->sarea_priv; - - DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", - DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard); - - if (vertex->idx < 0 || vertex->idx >= dma->buf_count) { - DRM_ERROR("buffer index %d (of %d max)\n", - vertex->idx, dma->buf_count - 1); - return -EINVAL; - } - if (vertex->prim < 0 || vertex->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { - DRM_ERROR("buffer prim %d\n", vertex->prim); - return -EINVAL; - } - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - VB_AGE_TEST_WITH_RETURN(dev_priv); - - buf = dma->buflist[vertex->idx]; - - if (buf->file_priv != file_priv) { - DRM_ERROR("process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->file_priv); - return -EINVAL; - } - if (buf->pending) { - DRM_ERROR("sending pending buffer %d\n", vertex->idx); - return -EINVAL; - } - - /* Build up a prim_t record: - */ - if (vertex->count) { - buf->used = vertex->count; /* not used? */ - - if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { - if (radeon_emit_state(dev_priv, file_priv, - &sarea_priv->context_state, - sarea_priv->tex_state, - sarea_priv->dirty)) { - DRM_ERROR("radeon_emit_state failed\n"); - return -EINVAL; - } - - sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | - RADEON_UPLOAD_TEX1IMAGES | - RADEON_UPLOAD_TEX2IMAGES | - RADEON_REQUIRE_QUIESCENCE); - } - - prim.start = 0; - prim.finish = vertex->count; /* unused */ - prim.prim = vertex->prim; - prim.numverts = vertex->count; - prim.vc_format = dev_priv->sarea_priv->vc_format; - - radeon_cp_dispatch_vertex(dev, buf, &prim); - } - - if (vertex->discard) { - radeon_cp_discard_buffer(dev, buf); - } - - COMMIT_RING(); - return 0; -} - -static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_sarea_t *sarea_priv; - struct drm_device_dma *dma = dev->dma; - struct drm_buf *buf; - drm_radeon_indices_t *elts = data; - drm_radeon_tcl_prim_t prim; - int count; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - sarea_priv = dev_priv->sarea_priv; - - DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n", - DRM_CURRENTPID, elts->idx, elts->start, elts->end, - elts->discard); - - if (elts->idx < 0 || elts->idx >= dma->buf_count) { - DRM_ERROR("buffer index %d (of %d max)\n", - elts->idx, dma->buf_count - 1); - return -EINVAL; - } - if (elts->prim < 0 || elts->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { - DRM_ERROR("buffer prim %d\n", elts->prim); - return -EINVAL; - } - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - VB_AGE_TEST_WITH_RETURN(dev_priv); - - buf = dma->buflist[elts->idx]; - - if (buf->file_priv != file_priv) { - DRM_ERROR("process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->file_priv); - return -EINVAL; - } - if (buf->pending) { - DRM_ERROR("sending pending buffer %d\n", elts->idx); - return -EINVAL; - } - - count = (elts->end - elts->start) / sizeof(u16); - elts->start -= RADEON_INDEX_PRIM_OFFSET; - - if (elts->start & 0x7) { - DRM_ERROR("misaligned buffer 0x%x\n", elts->start); - return -EINVAL; - } - if (elts->start < buf->used) { - DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used); - return -EINVAL; - } - - buf->used = elts->end; - - if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { - if (radeon_emit_state(dev_priv, file_priv, - &sarea_priv->context_state, - sarea_priv->tex_state, - sarea_priv->dirty)) { - DRM_ERROR("radeon_emit_state failed\n"); - return -EINVAL; - } - - sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | - RADEON_UPLOAD_TEX1IMAGES | - RADEON_UPLOAD_TEX2IMAGES | - RADEON_REQUIRE_QUIESCENCE); - } - - /* Build up a prim_t record: - */ - prim.start = elts->start; - prim.finish = elts->end; - prim.prim = elts->prim; - prim.offset = 0; /* offset from start of dma buffers */ - prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ - prim.vc_format = dev_priv->sarea_priv->vc_format; - - radeon_cp_dispatch_indices(dev, buf, &prim); - if (elts->discard) { - radeon_cp_discard_buffer(dev, buf); - } - - COMMIT_RING(); - return 0; -} - -static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_texture_t *tex = data; - drm_radeon_tex_image_t image; - int ret; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (tex->image == NULL) { - DRM_ERROR("null texture image!\n"); - return -EINVAL; - } - - if (DRM_COPY_FROM_USER(&image, - (drm_radeon_tex_image_t __user *) tex->image, - sizeof(image))) - return -EFAULT; - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - VB_AGE_TEST_WITH_RETURN(dev_priv); - - ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image); - - return ret; -} - -static int radeon_cp_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_stipple_t *stipple = data; - u32 mask[32]; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32))) - return -EFAULT; - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - - radeon_cp_dispatch_stipple(dev, mask); - - COMMIT_RING(); - return 0; -} - -static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - struct drm_device_dma *dma = dev->dma; - struct drm_buf *buf; - drm_radeon_indirect_t *indirect = data; - RING_LOCALS; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - DRM_DEBUG("idx=%d s=%d e=%d d=%d\n", - indirect->idx, indirect->start, indirect->end, - indirect->discard); - - if (indirect->idx < 0 || indirect->idx >= dma->buf_count) { - DRM_ERROR("buffer index %d (of %d max)\n", - indirect->idx, dma->buf_count - 1); - return -EINVAL; - } - - buf = dma->buflist[indirect->idx]; - - if (buf->file_priv != file_priv) { - DRM_ERROR("process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->file_priv); - return -EINVAL; - } - if (buf->pending) { - DRM_ERROR("sending pending buffer %d\n", indirect->idx); - return -EINVAL; - } - - if (indirect->start < buf->used) { - DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", - indirect->start, buf->used); - return -EINVAL; - } - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - VB_AGE_TEST_WITH_RETURN(dev_priv); - - buf->used = indirect->end; - - /* Wait for the 3D stream to idle before the indirect buffer - * containing 2D acceleration commands is processed. - */ - BEGIN_RING(2); - - RADEON_WAIT_UNTIL_3D_IDLE(); - - ADVANCE_RING(); - - /* Dispatch the indirect buffer full of commands from the - * X server. This is insecure and is thus only available to - * privileged clients. - */ - radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end); - if (indirect->discard) { - radeon_cp_discard_buffer(dev, buf); - } - - COMMIT_RING(); - return 0; -} - -static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_sarea_t *sarea_priv; - struct drm_device_dma *dma = dev->dma; - struct drm_buf *buf; - drm_radeon_vertex2_t *vertex = data; - int i; - unsigned char laststate; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - sarea_priv = dev_priv->sarea_priv; - - DRM_DEBUG("pid=%d index=%d discard=%d\n", - DRM_CURRENTPID, vertex->idx, vertex->discard); - - if (vertex->idx < 0 || vertex->idx >= dma->buf_count) { - DRM_ERROR("buffer index %d (of %d max)\n", - vertex->idx, dma->buf_count - 1); - return -EINVAL; - } - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - VB_AGE_TEST_WITH_RETURN(dev_priv); - - buf = dma->buflist[vertex->idx]; - - if (buf->file_priv != file_priv) { - DRM_ERROR("process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->file_priv); - return -EINVAL; - } - - if (buf->pending) { - DRM_ERROR("sending pending buffer %d\n", vertex->idx); - return -EINVAL; - } - - if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) - return -EINVAL; - - for (laststate = 0xff, i = 0; i < vertex->nr_prims; i++) { - drm_radeon_prim_t prim; - drm_radeon_tcl_prim_t tclprim; - - if (DRM_COPY_FROM_USER(&prim, &vertex->prim[i], sizeof(prim))) - return -EFAULT; - - if (prim.stateidx != laststate) { - drm_radeon_state_t state; - - if (DRM_COPY_FROM_USER(&state, - &vertex->state[prim.stateidx], - sizeof(state))) - return -EFAULT; - - if (radeon_emit_state2(dev_priv, file_priv, &state)) { - DRM_ERROR("radeon_emit_state2 failed\n"); - return -EINVAL; - } - - laststate = prim.stateidx; - } - - tclprim.start = prim.start; - tclprim.finish = prim.finish; - tclprim.prim = prim.prim; - tclprim.vc_format = prim.vc_format; - - if (prim.prim & RADEON_PRIM_WALK_IND) { - tclprim.offset = prim.numverts * 64; - tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */ - - radeon_cp_dispatch_indices(dev, buf, &tclprim); - } else { - tclprim.numverts = prim.numverts; - tclprim.offset = 0; /* not used */ - - radeon_cp_dispatch_vertex(dev, buf, &tclprim); - } - - if (sarea_priv->nbox == 1) - sarea_priv->nbox = 0; - } - - if (vertex->discard) { - radeon_cp_discard_buffer(dev, buf); - } - - COMMIT_RING(); - return 0; -} - -static int radeon_emit_packets(drm_radeon_private_t * dev_priv, - struct drm_file *file_priv, - drm_radeon_cmd_header_t header, - drm_radeon_kcmd_buffer_t *cmdbuf) -{ - int id = (int)header.packet.packet_id; - int sz, reg; - int *data = (int *)cmdbuf->buf; - RING_LOCALS; - - if (id >= RADEON_MAX_STATE_PACKETS) - return -EINVAL; - - sz = packet[id].len; - reg = packet[id].start; - - if (sz * sizeof(int) > cmdbuf->bufsz) { - DRM_ERROR("Packet size provided larger than data provided\n"); - return -EINVAL; - } - - if (radeon_check_and_fixup_packets(dev_priv, file_priv, id, data)) { - DRM_ERROR("Packet verification failed\n"); - return -EINVAL; - } - - BEGIN_RING(sz + 1); - OUT_RING(CP_PACKET0(reg, (sz - 1))); - OUT_RING_TABLE(data, sz); - ADVANCE_RING(); - - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); - return 0; -} - -static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv, - drm_radeon_cmd_header_t header, - drm_radeon_kcmd_buffer_t *cmdbuf) -{ - int sz = header.scalars.count; - int start = header.scalars.offset; - int stride = header.scalars.stride; - RING_LOCALS; - - BEGIN_RING(3 + sz); - OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); - OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); - OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); - OUT_RING_TABLE(cmdbuf->buf, sz); - ADVANCE_RING(); - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); - return 0; -} - -/* God this is ugly - */ -static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv, - drm_radeon_cmd_header_t header, - drm_radeon_kcmd_buffer_t *cmdbuf) -{ - int sz = header.scalars.count; - int start = ((unsigned int)header.scalars.offset) + 0x100; - int stride = header.scalars.stride; - RING_LOCALS; - - BEGIN_RING(3 + sz); - OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); - OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); - OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); - OUT_RING_TABLE(cmdbuf->buf, sz); - ADVANCE_RING(); - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); - return 0; -} - -static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv, - drm_radeon_cmd_header_t header, - drm_radeon_kcmd_buffer_t *cmdbuf) -{ - int sz = header.vectors.count; - int start = header.vectors.offset; - int stride = header.vectors.stride; - RING_LOCALS; - - BEGIN_RING(5 + sz); - OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0); - OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); - OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); - OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); - OUT_RING_TABLE(cmdbuf->buf, sz); - ADVANCE_RING(); - - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); - return 0; -} - -static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv, - drm_radeon_cmd_header_t header, - drm_radeon_kcmd_buffer_t *cmdbuf) -{ - int sz = header.veclinear.count * 4; - int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8); - RING_LOCALS; - - if (!sz) - return 0; - if (sz * 4 > cmdbuf->bufsz) - return -EINVAL; - - BEGIN_RING(5 + sz); - OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0); - OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); - OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); - OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); - OUT_RING_TABLE(cmdbuf->buf, sz); - ADVANCE_RING(); - - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); - return 0; -} - -static int radeon_emit_packet3(struct drm_device * dev, - struct drm_file *file_priv, - drm_radeon_kcmd_buffer_t *cmdbuf) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - unsigned int cmdsz; - int ret; - RING_LOCALS; - - DRM_DEBUG("\n"); - - if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv, - cmdbuf, &cmdsz))) { - DRM_ERROR("Packet verification failed\n"); - return ret; - } - - BEGIN_RING(cmdsz); - OUT_RING_TABLE(cmdbuf->buf, cmdsz); - ADVANCE_RING(); - - cmdbuf->buf += cmdsz * 4; - cmdbuf->bufsz -= cmdsz * 4; - return 0; -} - -static int radeon_emit_packet3_cliprect(struct drm_device *dev, - struct drm_file *file_priv, - drm_radeon_kcmd_buffer_t *cmdbuf, - int orig_nbox) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - struct drm_clip_rect box; - unsigned int cmdsz; - int ret; - struct drm_clip_rect __user *boxes = cmdbuf->boxes; - int i = 0; - RING_LOCALS; - - DRM_DEBUG("\n"); - - if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv, - cmdbuf, &cmdsz))) { - DRM_ERROR("Packet verification failed\n"); - return ret; - } - - if (!orig_nbox) - goto out; - - do { - if (i < cmdbuf->nbox) { - if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box))) - return -EFAULT; - /* FIXME The second and subsequent times round - * this loop, send a WAIT_UNTIL_3D_IDLE before - * calling emit_clip_rect(). This fixes a - * lockup on fast machines when sending - * several cliprects with a cmdbuf, as when - * waving a 2D window over a 3D - * window. Something in the commands from user - * space seems to hang the card when they're - * sent several times in a row. That would be - * the correct place to fix it but this works - * around it until I can figure that out - Tim - * Smith */ - if (i) { - BEGIN_RING(2); - RADEON_WAIT_UNTIL_3D_IDLE(); - ADVANCE_RING(); - } - radeon_emit_clip_rect(dev_priv, &box); - } - - BEGIN_RING(cmdsz); - OUT_RING_TABLE(cmdbuf->buf, cmdsz); - ADVANCE_RING(); - - } while (++i < cmdbuf->nbox); - if (cmdbuf->nbox == 1) - cmdbuf->nbox = 0; - - out: - cmdbuf->buf += cmdsz * 4; - cmdbuf->bufsz -= cmdsz * 4; - return 0; -} - -static int radeon_emit_wait(struct drm_device * dev, int flags) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - RING_LOCALS; - - DRM_DEBUG("%x\n", flags); - switch (flags) { - case RADEON_WAIT_2D: - BEGIN_RING(2); - RADEON_WAIT_UNTIL_2D_IDLE(); - ADVANCE_RING(); - break; - case RADEON_WAIT_3D: - BEGIN_RING(2); - RADEON_WAIT_UNTIL_3D_IDLE(); - ADVANCE_RING(); - break; - case RADEON_WAIT_2D | RADEON_WAIT_3D: - BEGIN_RING(2); - RADEON_WAIT_UNTIL_IDLE(); - ADVANCE_RING(); - break; - default: - return -EINVAL; - } - - return 0; -} - -static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - struct drm_device_dma *dma = dev->dma; - struct drm_buf *buf = NULL; - int idx; - drm_radeon_kcmd_buffer_t *cmdbuf = data; - drm_radeon_cmd_header_t header; - int orig_nbox, orig_bufsz; - char *kbuf = NULL; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - RING_SPACE_TEST_WITH_RETURN(dev_priv); - VB_AGE_TEST_WITH_RETURN(dev_priv); - - if (cmdbuf->bufsz > 64 * 1024 || cmdbuf->bufsz < 0) { - return -EINVAL; - } - - /* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid - * races between checking values and using those values in other code, - * and simply to avoid a lot of function calls to copy in data. - */ - orig_bufsz = cmdbuf->bufsz; - if (orig_bufsz != 0) { - kbuf = drm_alloc(cmdbuf->bufsz, DRM_MEM_DRIVER); - if (kbuf == NULL) - return -ENOMEM; - if (DRM_COPY_FROM_USER(kbuf, (void __user *)cmdbuf->buf, - cmdbuf->bufsz)) { - drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); - return -EFAULT; - } - cmdbuf->buf = kbuf; - } - - orig_nbox = cmdbuf->nbox; - - if (dev_priv->chip_family >= CHIP_R300) { - int temp; - temp = r300_do_cp_cmdbuf(dev, file_priv, cmdbuf); - - if (orig_bufsz != 0) - drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); - - return temp; - } - - /* microcode_version != r300 */ - while (cmdbuf->bufsz >= sizeof(header)) { - - header.i = *(int *)cmdbuf->buf; - cmdbuf->buf += sizeof(header); - cmdbuf->bufsz -= sizeof(header); - - switch (header.header.cmd_type) { - case RADEON_CMD_PACKET: - DRM_DEBUG("RADEON_CMD_PACKET\n"); - if (radeon_emit_packets - (dev_priv, file_priv, header, cmdbuf)) { - DRM_ERROR("radeon_emit_packets failed\n"); - goto err; - } - break; - - case RADEON_CMD_SCALARS: - DRM_DEBUG("RADEON_CMD_SCALARS\n"); - if (radeon_emit_scalars(dev_priv, header, cmdbuf)) { - DRM_ERROR("radeon_emit_scalars failed\n"); - goto err; - } - break; - - case RADEON_CMD_VECTORS: - DRM_DEBUG("RADEON_CMD_VECTORS\n"); - if (radeon_emit_vectors(dev_priv, header, cmdbuf)) { - DRM_ERROR("radeon_emit_vectors failed\n"); - goto err; - } - break; - - case RADEON_CMD_DMA_DISCARD: - DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); - idx = header.dma.buf_idx; - if (idx < 0 || idx >= dma->buf_count) { - DRM_ERROR("buffer index %d (of %d max)\n", - idx, dma->buf_count - 1); - goto err; - } - - buf = dma->buflist[idx]; - if (buf->file_priv != file_priv || buf->pending) { - DRM_ERROR("bad buffer %p %p %d\n", - buf->file_priv, file_priv, - buf->pending); - goto err; - } - - radeon_cp_discard_buffer(dev, buf); - break; - - case RADEON_CMD_PACKET3: - DRM_DEBUG("RADEON_CMD_PACKET3\n"); - if (radeon_emit_packet3(dev, file_priv, cmdbuf)) { - DRM_ERROR("radeon_emit_packet3 failed\n"); - goto err; - } - break; - - case RADEON_CMD_PACKET3_CLIP: - DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n"); - if (radeon_emit_packet3_cliprect - (dev, file_priv, cmdbuf, orig_nbox)) { - DRM_ERROR("radeon_emit_packet3_clip failed\n"); - goto err; - } - break; - - case RADEON_CMD_SCALARS2: - DRM_DEBUG("RADEON_CMD_SCALARS2\n"); - if (radeon_emit_scalars2(dev_priv, header, cmdbuf)) { - DRM_ERROR("radeon_emit_scalars2 failed\n"); - goto err; - } - break; - - case RADEON_CMD_WAIT: - DRM_DEBUG("RADEON_CMD_WAIT\n"); - if (radeon_emit_wait(dev, header.wait.flags)) { - DRM_ERROR("radeon_emit_wait failed\n"); - goto err; - } - break; - case RADEON_CMD_VECLINEAR: - DRM_DEBUG("RADEON_CMD_VECLINEAR\n"); - if (radeon_emit_veclinear(dev_priv, header, cmdbuf)) { - DRM_ERROR("radeon_emit_veclinear failed\n"); - goto err; - } - break; - - default: - DRM_ERROR("bad cmd_type %d at %p\n", - header.header.cmd_type, - cmdbuf->buf - sizeof(header)); - goto err; - } - } - - if (orig_bufsz != 0) - drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); - - DRM_DEBUG("DONE\n"); - COMMIT_RING(); - return 0; - - err: - if (orig_bufsz != 0) - drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); - return -EINVAL; -} - -static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_getparam_t *param = data; - int value; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - - switch (param->param) { - case RADEON_PARAM_GART_BUFFER_OFFSET: - value = dev_priv->gart_buffers_offset; - break; - case RADEON_PARAM_LAST_FRAME: - dev_priv->stats.last_frame_reads++; - value = GET_SCRATCH(0); - break; - case RADEON_PARAM_LAST_DISPATCH: - value = GET_SCRATCH(1); - break; - case RADEON_PARAM_LAST_CLEAR: - dev_priv->stats.last_clear_reads++; - value = GET_SCRATCH(2); - break; - case RADEON_PARAM_IRQ_NR: - value = dev->irq; - break; - case RADEON_PARAM_GART_BASE: - value = dev_priv->gart_vm_start; - break; - case RADEON_PARAM_REGISTER_HANDLE: - value = dev_priv->mmio->offset; - break; - case RADEON_PARAM_STATUS_HANDLE: - value = dev_priv->ring_rptr_offset; - break; -#ifndef __LP64__ - /* - * This ioctl() doesn't work on 64-bit platforms because hw_lock is a - * pointer which can't fit into an int-sized variable. According to - * Michel Dänzer, the ioctl() is only used on embedded platforms, so - * not supporting it shouldn't be a problem. If the same functionality - * is needed on 64-bit platforms, a new ioctl() would have to be added, - * so backwards-compatibility for the embedded platforms can be - * maintained. --davidm 4-Feb-2004. - */ - case RADEON_PARAM_SAREA_HANDLE: - /* The lock is the first dword in the sarea. */ - value = (long)dev->lock.hw_lock; - break; -#endif - case RADEON_PARAM_GART_TEX_HANDLE: - value = dev_priv->gart_textures_offset; - break; - case RADEON_PARAM_SCRATCH_OFFSET: - if (!dev_priv->writeback_works) - return -EINVAL; - value = RADEON_SCRATCH_REG_OFFSET; - break; - - case RADEON_PARAM_CARD_TYPE: - if (dev_priv->flags & RADEON_IS_PCIE) - value = RADEON_CARD_PCIE; - else if (dev_priv->flags & RADEON_IS_AGP) - value = RADEON_CARD_AGP; - else - value = RADEON_CARD_PCI; - break; - case RADEON_PARAM_VBLANK_CRTC: - value = radeon_vblank_crtc_get(dev); - break; - case RADEON_PARAM_FB_LOCATION: - value = radeon_read_fb_location(dev_priv); - break; - case RADEON_PARAM_NUM_GB_PIPES: - value = dev_priv->num_gb_pipes; - break; - default: - DRM_DEBUG( "Invalid parameter %d\n", param->param ); - return -EINVAL; - } - - if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { - DRM_ERROR("copy_to_user\n"); - return -EFAULT; - } - - return 0; -} - -static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_setparam_t *sp = data; - struct drm_radeon_driver_file_fields *radeon_priv; - - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } - - switch (sp->param) { - case RADEON_SETPARAM_FB_LOCATION: - radeon_priv = file_priv->driver_priv; - radeon_priv->radeon_fb_delta = dev_priv->fb_location - - sp->value; - break; - case RADEON_SETPARAM_SWITCH_TILING: - if (sp->value == 0) { - DRM_DEBUG("color tiling disabled\n"); - dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO; - dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO; - if (dev_priv->sarea_priv) - dev_priv->sarea_priv->tiling_enabled = 0; - } else if (sp->value == 1) { - DRM_DEBUG("color tiling enabled\n"); - dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO; - dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO; - if (dev_priv->sarea_priv) - dev_priv->sarea_priv->tiling_enabled = 1; - } - break; - case RADEON_SETPARAM_PCIGART_LOCATION: - dev_priv->pcigart_offset = sp->value; - dev_priv->pcigart_offset_set = 1; - break; - case RADEON_SETPARAM_NEW_MEMMAP: - dev_priv->new_memmap = sp->value; - break; - case RADEON_SETPARAM_PCIGART_TABLE_SIZE: - dev_priv->gart_info.table_size = sp->value; - if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE) - dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; - break; - case RADEON_SETPARAM_VBLANK_CRTC: - return radeon_vblank_crtc_set(dev, sp->value); - break; - default: - DRM_DEBUG("Invalid parameter %d\n", sp->param); - return -EINVAL; - } - - return 0; -} - -/* When a client dies: - * - Check for and clean up flipped page state - * - Free any alloced GART memory. - * - Free any alloced radeon surfaces. - * - * DRM infrastructure takes care of reclaiming dma buffers. - */ -void radeon_driver_preclose(struct drm_device *dev, - struct drm_file *file_priv) -{ - if (dev->dev_private) { - drm_radeon_private_t *dev_priv = dev->dev_private; - dev_priv->page_flipping = 0; - radeon_mem_release(file_priv, dev_priv->gart_heap); - radeon_mem_release(file_priv, dev_priv->fb_heap); - radeon_surfaces_release(file_priv, dev_priv); - } -} - -void radeon_driver_lastclose(struct drm_device *dev) -{ - if (dev->dev_private) { - drm_radeon_private_t *dev_priv = dev->dev_private; - - if (dev_priv->sarea_priv && - dev_priv->sarea_priv->pfCurrentPage != 0) - radeon_cp_dispatch_flip(dev); - } - - radeon_do_release(dev); -} - -int radeon_driver_open(struct drm_device *dev, struct drm_file *file_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - struct drm_radeon_driver_file_fields *radeon_priv; - - DRM_DEBUG("\n"); - radeon_priv = - (struct drm_radeon_driver_file_fields *) - drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES); - - if (!radeon_priv) - return -ENOMEM; - - file_priv->driver_priv = radeon_priv; - - if (dev_priv) - radeon_priv->radeon_fb_delta = dev_priv->fb_location; - else - radeon_priv->radeon_fb_delta = 0; - return 0; -} - -void radeon_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) -{ - struct drm_radeon_driver_file_fields *radeon_priv = - file_priv->driver_priv; - - drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); -} - -struct drm_ioctl_desc radeon_ioctls[] = { - DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH) -}; - -int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); diff --git a/shared-core/savage_bci.c b/shared-core/savage_bci.c deleted file mode 100644 index 4b8a89fe..00000000 --- a/shared-core/savage_bci.c +++ /dev/null @@ -1,1092 +0,0 @@ -/* savage_bci.c -- BCI support for Savage - * - * Copyright 2004 Felix Kuehling - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF - * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#include "drmP.h" -#include "savage_drm.h" -#include "savage_drv.h" - -/* Need a long timeout for shadow status updates can take a while - * and so can waiting for events when the queue is full. */ -#define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */ -#define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */ -#define SAVAGE_FREELIST_DEBUG 0 - -static int savage_do_cleanup_bci(struct drm_device *dev); - -static int -savage_bci_wait_fifo_shadow(drm_savage_private_t *dev_priv, unsigned int n) -{ - uint32_t mask = dev_priv->status_used_mask; - uint32_t threshold = dev_priv->bci_threshold_hi; - uint32_t status; - int i; - -#if SAVAGE_BCI_DEBUG - if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold) - DRM_ERROR("Trying to emit %d words " - "(more than guaranteed space in COB)\n", n); -#endif - - for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { - DRM_MEMORYBARRIER(); - status = dev_priv->status_ptr[0]; - if ((status & mask) < threshold) - return 0; - DRM_UDELAY(1); - } - -#if SAVAGE_BCI_DEBUG - DRM_ERROR("failed!\n"); - DRM_INFO(" status=0x%08x, threshold=0x%08x\n", status, threshold); -#endif - return -EBUSY; -} - -static int -savage_bci_wait_fifo_s3d(drm_savage_private_t *dev_priv, unsigned int n) -{ - uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; - uint32_t status; - int i; - - for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { - status = SAVAGE_READ(SAVAGE_STATUS_WORD0); - if ((status & SAVAGE_FIFO_USED_MASK_S3D) <= maxUsed) - return 0; - DRM_UDELAY(1); - } - -#if SAVAGE_BCI_DEBUG - DRM_ERROR("failed!\n"); - DRM_INFO(" status=0x%08x\n", status); -#endif - return -EBUSY; -} - -static int -savage_bci_wait_fifo_s4(drm_savage_private_t *dev_priv, unsigned int n) -{ - uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; - uint32_t status; - int i; - - for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { - status = SAVAGE_READ(SAVAGE_ALT_STATUS_WORD0); - if ((status & SAVAGE_FIFO_USED_MASK_S4) <= maxUsed) - return 0; - DRM_UDELAY(1); - } - -#if SAVAGE_BCI_DEBUG - DRM_ERROR("failed!\n"); - DRM_INFO(" status=0x%08x\n", status); -#endif - return -EBUSY; -} - -/* - * Waiting for events. - * - * The BIOSresets the event tag to 0 on mode changes. Therefore we - * never emit 0 to the event tag. If we find a 0 event tag we know the - * BIOS stomped on it and return success assuming that the BIOS waited - * for engine idle. - * - * Note: if the Xserver uses the event tag it has to follow the same - * rule. Otherwise there may be glitches every 2^16 events. - */ -static int -savage_bci_wait_event_shadow(drm_savage_private_t *dev_priv, uint16_t e) -{ - uint32_t status; - int i; - - for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) { - DRM_MEMORYBARRIER(); - status = dev_priv->status_ptr[1]; - if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff || - (status & 0xffff) == 0) - return 0; - DRM_UDELAY(1); - } - -#if SAVAGE_BCI_DEBUG - DRM_ERROR("failed!\n"); - DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e); -#endif - - return -EBUSY; -} - -static int -savage_bci_wait_event_reg(drm_savage_private_t *dev_priv, uint16_t e) -{ - uint32_t status; - int i; - - for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) { - status = SAVAGE_READ(SAVAGE_STATUS_WORD1); - if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff || - (status & 0xffff) == 0) - return 0; - DRM_UDELAY(1); - } - -#if SAVAGE_BCI_DEBUG - DRM_ERROR("failed!\n"); - DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e); -#endif - - return -EBUSY; -} - -uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, - unsigned int flags) -{ - uint16_t count; - BCI_LOCALS; - - if (dev_priv->status_ptr) { - /* coordinate with Xserver */ - count = dev_priv->status_ptr[1023]; - if (count < dev_priv->event_counter) - dev_priv->event_wrap++; - } else { - count = dev_priv->event_counter; - } - count = (count + 1) & 0xffff; - if (count == 0) { - count++; /* See the comment above savage_wait_event_*. */ - dev_priv->event_wrap++; - } - dev_priv->event_counter = count; - if (dev_priv->status_ptr) - dev_priv->status_ptr[1023] = (uint32_t)count; - - if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) { - unsigned int wait_cmd = BCI_CMD_WAIT; - if ((flags & SAVAGE_WAIT_2D)) - wait_cmd |= BCI_CMD_WAIT_2D; - if ((flags & SAVAGE_WAIT_3D)) - wait_cmd |= BCI_CMD_WAIT_3D; - BEGIN_BCI(2); - BCI_WRITE(wait_cmd); - } else { - BEGIN_BCI(1); - } - BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t)count); - - return count; -} - -/* - * Freelist management - */ -static int savage_freelist_init(struct drm_device *dev) -{ - drm_savage_private_t *dev_priv = dev->dev_private; - struct drm_device_dma *dma = dev->dma; - struct drm_buf *buf; - drm_savage_buf_priv_t *entry; - int i; - DRM_DEBUG("count=%d\n", dma->buf_count); - - dev_priv->head.next = &dev_priv->tail; - dev_priv->head.prev = NULL; - dev_priv->head.buf = NULL; - - dev_priv->tail.next = NULL; - dev_priv->tail.prev = &dev_priv->head; - dev_priv->tail.buf = NULL; - - for (i = 0; i < dma->buf_count; i++) { - buf = dma->buflist[i]; - entry = buf->dev_private; - - SET_AGE(&entry->age, 0, 0); - entry->buf = buf; - - entry->next = dev_priv->head.next; - entry->prev = &dev_priv->head; - dev_priv->head.next->prev = entry; - dev_priv->head.next = entry; - } - - return 0; -} - -static struct drm_buf *savage_freelist_get(struct drm_device *dev) -{ - drm_savage_private_t *dev_priv = dev->dev_private; - drm_savage_buf_priv_t *tail = dev_priv->tail.prev; - uint16_t event; - unsigned int wrap; - DRM_DEBUG("\n"); - - UPDATE_EVENT_COUNTER(); - if (dev_priv->status_ptr) - event = dev_priv->status_ptr[1] & 0xffff; - else - event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; - wrap = dev_priv->event_wrap; - if (event > dev_priv->event_counter) - wrap--; /* hardware hasn't passed the last wrap yet */ - - DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap); - DRM_DEBUG(" head=0x%04x %d\n", event, wrap); - - if (tail->buf && (TEST_AGE(&tail->age, event, wrap) || event == 0)) { - drm_savage_buf_priv_t *next = tail->next; - drm_savage_buf_priv_t *prev = tail->prev; - prev->next = next; - next->prev = prev; - tail->next = tail->prev = NULL; - return tail->buf; - } - - DRM_DEBUG("returning NULL, tail->buf=%p!\n", tail->buf); - return NULL; -} - -void savage_freelist_put(struct drm_device *dev, struct drm_buf *buf) -{ - drm_savage_private_t *dev_priv = dev->dev_private; - drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next; - - DRM_DEBUG("age=0x%04x wrap=%d\n", entry->age.event, entry->age.wrap); - - if (entry->next != NULL || entry->prev != NULL) { - DRM_ERROR("entry already on freelist.\n"); - return; - } - - prev = &dev_priv->head; - next = prev->next; - prev->next = entry; - next->prev = entry; - entry->prev = prev; - entry->next = next; -} - -/* - * Command DMA - */ -static int savage_dma_init(drm_savage_private_t *dev_priv) -{ - unsigned int i; - - dev_priv->nr_dma_pages = dev_priv->cmd_dma->size / - (SAVAGE_DMA_PAGE_SIZE*4); - dev_priv->dma_pages = drm_alloc(sizeof(drm_savage_dma_page_t) * - dev_priv->nr_dma_pages, DRM_MEM_DRIVER); - if (dev_priv->dma_pages == NULL) - return -ENOMEM; - - for (i = 0; i < dev_priv->nr_dma_pages; ++i) { - SET_AGE(&dev_priv->dma_pages[i].age, 0, 0); - dev_priv->dma_pages[i].used = 0; - dev_priv->dma_pages[i].flushed = 0; - } - SET_AGE(&dev_priv->last_dma_age, 0, 0); - - dev_priv->first_dma_page = 0; - dev_priv->current_dma_page = 0; - - return 0; -} - -void savage_dma_reset(drm_savage_private_t *dev_priv) -{ - uint16_t event; - unsigned int wrap, i; - event = savage_bci_emit_event(dev_priv, 0); - wrap = dev_priv->event_wrap; - for (i = 0; i < dev_priv->nr_dma_pages; ++i) { - SET_AGE(&dev_priv->dma_pages[i].age, event, wrap); - dev_priv->dma_pages[i].used = 0; - dev_priv->dma_pages[i].flushed = 0; - } - SET_AGE(&dev_priv->last_dma_age, event, wrap); - dev_priv->first_dma_page = dev_priv->current_dma_page = 0; -} - -void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page) -{ - uint16_t event; - unsigned int wrap; - - /* Faked DMA buffer pages don't age. */ - if (dev_priv->cmd_dma == &dev_priv->fake_dma) - return; - - UPDATE_EVENT_COUNTER(); - if (dev_priv->status_ptr) - event = dev_priv->status_ptr[1] & 0xffff; - else - event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; - wrap = dev_priv->event_wrap; - if (event > dev_priv->event_counter) - wrap--; /* hardware hasn't passed the last wrap yet */ - - if (dev_priv->dma_pages[page].age.wrap > wrap || - (dev_priv->dma_pages[page].age.wrap == wrap && - dev_priv->dma_pages[page].age.event > event)) { - if (dev_priv->wait_evnt(dev_priv, - dev_priv->dma_pages[page].age.event) - < 0) - DRM_ERROR("wait_evnt failed!\n"); - } -} - -uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, unsigned int n) -{ - unsigned int cur = dev_priv->current_dma_page; - unsigned int rest = SAVAGE_DMA_PAGE_SIZE - - dev_priv->dma_pages[cur].used; - unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE - 1) / - SAVAGE_DMA_PAGE_SIZE; - uint32_t *dma_ptr; - unsigned int i; - - DRM_DEBUG("cur=%u, cur->used=%u, n=%u, rest=%u, nr_pages=%u\n", - cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages); - - if (cur + nr_pages < dev_priv->nr_dma_pages) { - dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + - cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used; - if (n < rest) - rest = n; - dev_priv->dma_pages[cur].used += rest; - n -= rest; - cur++; - } else { - dev_priv->dma_flush(dev_priv); - nr_pages = - (n + SAVAGE_DMA_PAGE_SIZE - 1) / SAVAGE_DMA_PAGE_SIZE; - for (i = cur; i < dev_priv->nr_dma_pages; ++i) { - dev_priv->dma_pages[i].age = dev_priv->last_dma_age; - dev_priv->dma_pages[i].used = 0; - dev_priv->dma_pages[i].flushed = 0; - } - dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle; - dev_priv->first_dma_page = cur = 0; - } - for (i = cur; nr_pages > 0; ++i, --nr_pages) { -#if SAVAGE_DMA_DEBUG - if (dev_priv->dma_pages[i].used) { - DRM_ERROR("unflushed page %u: used=%u\n", - i, dev_priv->dma_pages[i].used); - } -#endif - if (n > SAVAGE_DMA_PAGE_SIZE) - dev_priv->dma_pages[i].used = SAVAGE_DMA_PAGE_SIZE; - else - dev_priv->dma_pages[i].used = n; - n -= SAVAGE_DMA_PAGE_SIZE; - } - dev_priv->current_dma_page = --i; - - DRM_DEBUG("cur=%u, cur->used=%u, n=%u\n", - i, dev_priv->dma_pages[i].used, n); - - savage_dma_wait(dev_priv, dev_priv->current_dma_page); - - return dma_ptr; -} - -static void savage_dma_flush(drm_savage_private_t *dev_priv) -{ - unsigned int first = dev_priv->first_dma_page; - unsigned int cur = dev_priv->current_dma_page; - uint16_t event; - unsigned int wrap, pad, align, len, i; - unsigned long phys_addr; - BCI_LOCALS; - - if (first == cur && - dev_priv->dma_pages[cur].used == dev_priv->dma_pages[cur].flushed) - return; - - /* pad length to multiples of 2 entries - * align start of next DMA block to multiles of 8 entries */ - pad = -dev_priv->dma_pages[cur].used & 1; - align = -(dev_priv->dma_pages[cur].used + pad) & 7; - - DRM_DEBUG("first=%u, cur=%u, first->flushed=%u, cur->used=%u, " - "pad=%u, align=%u\n", - first, cur, dev_priv->dma_pages[first].flushed, - dev_priv->dma_pages[cur].used, pad, align); - - /* pad with noops */ - if (pad) { - uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + - cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used; - dev_priv->dma_pages[cur].used += pad; - while (pad != 0) { - *dma_ptr++ = BCI_CMD_WAIT; - pad--; - } - } - - DRM_MEMORYBARRIER(); - - /* do flush ... */ - phys_addr = dev_priv->cmd_dma->offset + - (first * SAVAGE_DMA_PAGE_SIZE + - dev_priv->dma_pages[first].flushed) * 4; - len = (cur - first) * SAVAGE_DMA_PAGE_SIZE + - dev_priv->dma_pages[cur].used - dev_priv->dma_pages[first].flushed; - - DRM_DEBUG("phys_addr=%lx, len=%u\n", - phys_addr | dev_priv->dma_type, len); - - BEGIN_BCI(3); - BCI_SET_REGISTERS(SAVAGE_DMABUFADDR, 1); - BCI_WRITE(phys_addr | dev_priv->dma_type); - BCI_DMA(len); - - /* fix alignment of the start of the next block */ - dev_priv->dma_pages[cur].used += align; - - /* age DMA pages */ - event = savage_bci_emit_event(dev_priv, 0); - wrap = dev_priv->event_wrap; - for (i = first; i < cur; ++i) { - SET_AGE(&dev_priv->dma_pages[i].age, event, wrap); - dev_priv->dma_pages[i].used = 0; - dev_priv->dma_pages[i].flushed = 0; - } - /* age the current page only when it's full */ - if (dev_priv->dma_pages[cur].used == SAVAGE_DMA_PAGE_SIZE) { - SET_AGE(&dev_priv->dma_pages[cur].age, event, wrap); - dev_priv->dma_pages[cur].used = 0; - dev_priv->dma_pages[cur].flushed = 0; - /* advance to next page */ - cur++; - if (cur == dev_priv->nr_dma_pages) - cur = 0; - dev_priv->first_dma_page = dev_priv->current_dma_page = cur; - } else { - dev_priv->first_dma_page = cur; - dev_priv->dma_pages[cur].flushed = dev_priv->dma_pages[i].used; - } - SET_AGE(&dev_priv->last_dma_age, event, wrap); - - DRM_DEBUG("first=cur=%u, cur->used=%u, cur->flushed=%u\n", cur, - dev_priv->dma_pages[cur].used, - dev_priv->dma_pages[cur].flushed); -} - -static void savage_fake_dma_flush(drm_savage_private_t *dev_priv) -{ - unsigned int i, j; - BCI_LOCALS; - - if (dev_priv->first_dma_page == dev_priv->current_dma_page && - dev_priv->dma_pages[dev_priv->current_dma_page].used == 0) - return; - - DRM_DEBUG("first=%u, cur=%u, cur->used=%u\n", - dev_priv->first_dma_page, dev_priv->current_dma_page, - dev_priv->dma_pages[dev_priv->current_dma_page].used); - - for (i = dev_priv->first_dma_page; - i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used; - ++i) { - uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + - i * SAVAGE_DMA_PAGE_SIZE; -#if SAVAGE_DMA_DEBUG - /* Sanity check: all pages except the last one must be full. */ - if (i < dev_priv->current_dma_page && - dev_priv->dma_pages[i].used != SAVAGE_DMA_PAGE_SIZE) { - DRM_ERROR("partial DMA page %u: used=%u", - i, dev_priv->dma_pages[i].used); - } -#endif - BEGIN_BCI(dev_priv->dma_pages[i].used); - for (j = 0; j < dev_priv->dma_pages[i].used; ++j) { - BCI_WRITE(dma_ptr[j]); - } - dev_priv->dma_pages[i].used = 0; - } - - /* reset to first page */ - dev_priv->first_dma_page = dev_priv->current_dma_page = 0; -} - -int savage_driver_load(struct drm_device *dev, unsigned long chipset) -{ - drm_savage_private_t *dev_priv; - - dev_priv = drm_alloc(sizeof(drm_savage_private_t), DRM_MEM_DRIVER); - if (dev_priv == NULL) - return -ENOMEM; - - memset(dev_priv, 0, sizeof(drm_savage_private_t)); - dev->dev_private = (void *)dev_priv; - - dev_priv->chipset = (enum savage_family)chipset; - - return 0; -} - -/* - * Initalize mappings. On Savage4 and SavageIX the alignment - * and size of the aperture is not suitable for automatic MTRR setup - * in drm_addmap. Therefore we add them manually before the maps are - * initialized, and tear them down on last close. - */ -int savage_driver_firstopen(struct drm_device *dev) -{ - drm_savage_private_t *dev_priv = dev->dev_private; - unsigned long mmio_base, fb_base, fb_size, aperture_base; - /* fb_rsrc and aper_rsrc aren't really used currently, but still exist - * in case we decide we need information on the BAR for BSD in the - * future. - */ - unsigned int fb_rsrc, aper_rsrc; - int ret = 0; - - dev_priv->mtrr[0].handle = -1; - dev_priv->mtrr[1].handle = -1; - dev_priv->mtrr[2].handle = -1; - if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { - fb_rsrc = 0; - fb_base = drm_get_resource_start(dev, 0); - fb_size = SAVAGE_FB_SIZE_S3; - mmio_base = fb_base + SAVAGE_FB_SIZE_S3; - aper_rsrc = 0; - aperture_base = fb_base + SAVAGE_APERTURE_OFFSET; - /* this should always be true */ - if (drm_get_resource_len(dev, 0) == 0x08000000) { - /* Don't make MMIO write-cobining! We need 3 - * MTRRs. */ - dev_priv->mtrr[0].base = fb_base; - dev_priv->mtrr[0].size = 0x01000000; - dev_priv->mtrr[0].handle = - drm_mtrr_add(dev_priv->mtrr[0].base, - dev_priv->mtrr[0].size, DRM_MTRR_WC); - dev_priv->mtrr[1].base = fb_base + 0x02000000; - dev_priv->mtrr[1].size = 0x02000000; - dev_priv->mtrr[1].handle = - drm_mtrr_add(dev_priv->mtrr[1].base, - dev_priv->mtrr[1].size, DRM_MTRR_WC); - dev_priv->mtrr[2].base = fb_base + 0x04000000; - dev_priv->mtrr[2].size = 0x04000000; - dev_priv->mtrr[2].handle = - drm_mtrr_add(dev_priv->mtrr[2].base, - dev_priv->mtrr[2].size, DRM_MTRR_WC); - } else { - DRM_ERROR("strange pci_resource_len %08lx\n", - drm_get_resource_len(dev, 0)); - } - } else if (dev_priv->chipset != S3_SUPERSAVAGE && - dev_priv->chipset != S3_SAVAGE2000) { - mmio_base = drm_get_resource_start(dev, 0); - fb_rsrc = 1; - fb_base = drm_get_resource_start(dev, 1); - fb_size = SAVAGE_FB_SIZE_S4; - aper_rsrc = 1; - aperture_base = fb_base + SAVAGE_APERTURE_OFFSET; - /* this should always be true */ - if (drm_get_resource_len(dev, 1) == 0x08000000) { - /* Can use one MTRR to cover both fb and - * aperture. */ - dev_priv->mtrr[0].base = fb_base; - dev_priv->mtrr[0].size = 0x08000000; - dev_priv->mtrr[0].handle = - drm_mtrr_add(dev_priv->mtrr[0].base, - dev_priv->mtrr[0].size, DRM_MTRR_WC); - } else { - DRM_ERROR("strange pci_resource_len %08lx\n", - drm_get_resource_len(dev, 1)); - } - } else { - mmio_base = drm_get_resource_start(dev, 0); - fb_rsrc = 1; - fb_base = drm_get_resource_start(dev, 1); - fb_size = drm_get_resource_len(dev, 1); - aper_rsrc = 2; - aperture_base = drm_get_resource_start(dev, 2); - /* Automatic MTRR setup will do the right thing. */ - } - - ret = drm_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, _DRM_REGISTERS, - _DRM_READ_ONLY, &dev_priv->mmio); - if (ret) - return ret; - - ret = drm_addmap(dev, fb_base, fb_size, _DRM_FRAME_BUFFER, - _DRM_WRITE_COMBINING, &dev_priv->fb); - if (ret) - return ret; - - ret = drm_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE, - _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING, - &dev_priv->aperture); - if (ret) - return ret; - - return ret; -} - -/* - * Delete MTRRs and free device-private data. - */ -void savage_driver_lastclose(struct drm_device *dev) -{ - drm_savage_private_t *dev_priv = dev->dev_private; - int i; - - for (i = 0; i < 3; ++i) - if (dev_priv->mtrr[i].handle >= 0) - drm_mtrr_del(dev_priv->mtrr[i].handle, - dev_priv->mtrr[i].base, - dev_priv->mtrr[i].size, DRM_MTRR_WC); -} - -int savage_driver_unload(struct drm_device *dev) -{ - drm_savage_private_t *dev_priv = dev->dev_private; - - drm_free(dev_priv, sizeof(drm_savage_private_t), DRM_MEM_DRIVER); - - return 0; -} - -static int savage_do_init_bci(struct drm_device *dev, drm_savage_init_t *init) -{ - drm_savage_private_t *dev_priv = dev->dev_private; - - if (init->fb_bpp != 16 && init->fb_bpp != 32) { - DRM_ERROR("invalid frame buffer bpp %d!\n", init->fb_bpp); - return -EINVAL; - } - if (init->depth_bpp != 16 && init->depth_bpp != 32) { - DRM_ERROR("invalid depth buffer bpp %d!\n", init->fb_bpp); - return -EINVAL; - } - if (init->dma_type != SAVAGE_DMA_AGP && - init->dma_type != SAVAGE_DMA_PCI) { - DRM_ERROR("invalid dma memory type %d!\n", init->dma_type); - return -EINVAL; - } - - dev_priv->cob_size = init->cob_size; - dev_priv->bci_threshold_lo = init->bci_threshold_lo; - dev_priv->bci_threshold_hi = init->bci_threshold_hi; - dev_priv->dma_type = init->dma_type; - - dev_priv->fb_bpp = init->fb_bpp; - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; - dev_priv->depth_bpp = init->depth_bpp; - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; - - dev_priv->texture_offset = init->texture_offset; - dev_priv->texture_size = init->texture_size; - - dev_priv->sarea = drm_getsarea(dev); - if (!dev_priv->sarea) { - DRM_ERROR("could not find sarea!\n"); - savage_do_cleanup_bci(dev); - return -EINVAL; - } - if (init->status_offset != 0) { - dev_priv->status = drm_core_findmap(dev, init->status_offset); - if (!dev_priv->status) { - DRM_ERROR("could not find shadow status region!\n"); - savage_do_cleanup_bci(dev); - return -EINVAL; - } - } else { - dev_priv->status = NULL; - } - if (dev_priv->dma_type == SAVAGE_DMA_AGP && init->buffers_offset) { - dev->agp_buffer_token = init->buffers_offset; - dev->agp_buffer_map = drm_core_findmap(dev, - init->buffers_offset); - if (!dev->agp_buffer_map) { - DRM_ERROR("could not find DMA buffer region!\n"); - savage_do_cleanup_bci(dev); - return -EINVAL; - } - drm_core_ioremap(dev->agp_buffer_map, dev); - if (!dev->agp_buffer_map) { - DRM_ERROR("failed to ioremap DMA buffer region!\n"); - savage_do_cleanup_bci(dev); - return -ENOMEM; - } - } - if (init->agp_textures_offset) { - dev_priv->agp_textures = - drm_core_findmap(dev, init->agp_textures_offset); - if (!dev_priv->agp_textures) { - DRM_ERROR("could not find agp texture region!\n"); - savage_do_cleanup_bci(dev); - return -EINVAL; - } - } else { - dev_priv->agp_textures = NULL; - } - - if (init->cmd_dma_offset) { - if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { - DRM_ERROR("command DMA not supported on " - "Savage3D/MX/IX.\n"); - savage_do_cleanup_bci(dev); - return -EINVAL; - } - if (dev->dma && dev->dma->buflist) { - DRM_ERROR("command and vertex DMA not supported " - "at the same time.\n"); - savage_do_cleanup_bci(dev); - return -EINVAL; - } - dev_priv->cmd_dma = drm_core_findmap(dev, init->cmd_dma_offset); - if (!dev_priv->cmd_dma) { - DRM_ERROR("could not find command DMA region!\n"); - savage_do_cleanup_bci(dev); - return -EINVAL; - } - if (dev_priv->dma_type == SAVAGE_DMA_AGP) { - if (dev_priv->cmd_dma->type != _DRM_AGP) { - DRM_ERROR("AGP command DMA region is not a " - "_DRM_AGP map!\n"); - savage_do_cleanup_bci(dev); - return -EINVAL; - } - drm_core_ioremap(dev_priv->cmd_dma, dev); - if (!dev_priv->cmd_dma->handle) { - DRM_ERROR("failed to ioremap command " - "DMA region!\n"); - savage_do_cleanup_bci(dev); - return -ENOMEM; - } - } else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) { - DRM_ERROR("PCI command DMA region is not a " - "_DRM_CONSISTENT map!\n"); - savage_do_cleanup_bci(dev); - return -EINVAL; - } - } else { - dev_priv->cmd_dma = NULL; - } - - dev_priv->dma_flush = savage_dma_flush; - if (!dev_priv->cmd_dma) { - DRM_DEBUG("falling back to faked command DMA.\n"); - dev_priv->fake_dma.offset = 0; - dev_priv->fake_dma.size = SAVAGE_FAKE_DMA_SIZE; - dev_priv->fake_dma.type = _DRM_SHM; - dev_priv->fake_dma.handle = drm_alloc(SAVAGE_FAKE_DMA_SIZE, - DRM_MEM_DRIVER); - if (!dev_priv->fake_dma.handle) { - DRM_ERROR("could not allocate faked DMA buffer!\n"); - savage_do_cleanup_bci(dev); - return -ENOMEM; - } - dev_priv->cmd_dma = &dev_priv->fake_dma; - dev_priv->dma_flush = savage_fake_dma_flush; - } - - dev_priv->sarea_priv = - (drm_savage_sarea_t *)((uint8_t *)dev_priv->sarea->handle + - init->sarea_priv_offset); - - /* setup bitmap descriptors */ - { - unsigned int color_tile_format; - unsigned int depth_tile_format; - unsigned int front_stride, back_stride, depth_stride; - if (dev_priv->chipset <= S3_SAVAGE4) { - color_tile_format = dev_priv->fb_bpp == 16 ? - SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; - depth_tile_format = dev_priv->depth_bpp == 16 ? - SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; - } else { - color_tile_format = SAVAGE_BD_TILE_DEST; - depth_tile_format = SAVAGE_BD_TILE_DEST; - } - front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8); - back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8); - depth_stride = - dev_priv->depth_pitch / (dev_priv->depth_bpp / 8); - - dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE | - (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | - (color_tile_format << SAVAGE_BD_TILE_SHIFT); - - dev_priv-> back_bd = back_stride | SAVAGE_BD_BW_DISABLE | - (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | - (color_tile_format << SAVAGE_BD_TILE_SHIFT); - - dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE | - (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) | - (depth_tile_format << SAVAGE_BD_TILE_SHIFT); - } - - /* setup status and bci ptr */ - dev_priv->event_counter = 0; - dev_priv->event_wrap = 0; - dev_priv->bci_ptr = (volatile uint32_t *) - ((uint8_t *)dev_priv->mmio->handle + SAVAGE_BCI_OFFSET); - if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { - dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D; - } else { - dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S4; - } - if (dev_priv->status != NULL) { - dev_priv->status_ptr = - (volatile uint32_t *)dev_priv->status->handle; - dev_priv->wait_fifo = savage_bci_wait_fifo_shadow; - dev_priv->wait_evnt = savage_bci_wait_event_shadow; - dev_priv->status_ptr[1023] = dev_priv->event_counter; - } else { - dev_priv->status_ptr = NULL; - if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { - dev_priv->wait_fifo = savage_bci_wait_fifo_s3d; - } else { - dev_priv->wait_fifo = savage_bci_wait_fifo_s4; - } - dev_priv->wait_evnt = savage_bci_wait_event_reg; - } - - /* cliprect functions */ - if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) - dev_priv->emit_clip_rect = savage_emit_clip_rect_s3d; - else - dev_priv->emit_clip_rect = savage_emit_clip_rect_s4; - - if (savage_freelist_init(dev) < 0) { - DRM_ERROR("could not initialize freelist\n"); - savage_do_cleanup_bci(dev); - return -ENOMEM; - } - - if (savage_dma_init(dev_priv) < 0) { - DRM_ERROR("could not initialize command DMA\n"); - savage_do_cleanup_bci(dev); - return -ENOMEM; - } - - return 0; -} - -static int savage_do_cleanup_bci(struct drm_device *dev) -{ - drm_savage_private_t *dev_priv = dev->dev_private; - - if (dev_priv->cmd_dma == &dev_priv->fake_dma) { - if (dev_priv->fake_dma.handle) - drm_free(dev_priv->fake_dma.handle, - SAVAGE_FAKE_DMA_SIZE, DRM_MEM_DRIVER); - } else if (dev_priv->cmd_dma && dev_priv->cmd_dma->handle && - dev_priv->cmd_dma->type == _DRM_AGP && - dev_priv->dma_type == SAVAGE_DMA_AGP) - drm_core_ioremapfree(dev_priv->cmd_dma, dev); - - if (dev_priv->dma_type == SAVAGE_DMA_AGP && - dev->agp_buffer_map && dev->agp_buffer_map->handle) { - drm_core_ioremapfree(dev->agp_buffer_map, dev); - /* make sure the next instance (which may be running - * in PCI mode) doesn't try to use an old - * agp_buffer_map. */ - dev->agp_buffer_map = NULL; - } - - if (dev_priv->dma_pages) - drm_free(dev_priv->dma_pages, - sizeof(drm_savage_dma_page_t)*dev_priv->nr_dma_pages, - DRM_MEM_DRIVER); - - return 0; -} - -static int savage_bci_init(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_savage_init_t *init = data; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - switch (init->func) { - case SAVAGE_INIT_BCI: - return savage_do_init_bci(dev, init); - case SAVAGE_CLEANUP_BCI: - return savage_do_cleanup_bci(dev); - } - - return -EINVAL; -} - -static int savage_bci_event_emit(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_savage_private_t *dev_priv = dev->dev_private; - drm_savage_event_emit_t *event = data; - - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - event->count = savage_bci_emit_event(dev_priv, event->flags); - event->count |= dev_priv->event_wrap << 16; - - return 0; -} - -static int savage_bci_event_wait(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_savage_private_t *dev_priv = dev->dev_private; - drm_savage_event_wait_t *event = data; - unsigned int event_e, hw_e; - unsigned int event_w, hw_w; - - DRM_DEBUG("\n"); - - UPDATE_EVENT_COUNTER(); - if (dev_priv->status_ptr) - hw_e = dev_priv->status_ptr[1] & 0xffff; - else - hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; - hw_w = dev_priv->event_wrap; - if (hw_e > dev_priv->event_counter) - hw_w--; /* hardware hasn't passed the last wrap yet */ - - event_e = event->count & 0xffff; - event_w = event->count >> 16; - - /* Don't need to wait if - * - event counter wrapped since the event was emitted or - * - the hardware has advanced up to or over the event to wait for. - */ - if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e)) - return 0; - else - return dev_priv->wait_evnt(dev_priv, event_e); -} - -/* - * DMA buffer management - */ - -static int savage_bci_get_buffers(struct drm_device *dev, - struct drm_file *file_priv, - struct drm_dma *d) -{ - struct drm_buf *buf; - int i; - - for (i = d->granted_count; i < d->request_count; i++) { - buf = savage_freelist_get(dev); - if (!buf) - return -EAGAIN; - - buf->file_priv = file_priv; - - if (DRM_COPY_TO_USER(&d->request_indices[i], - &buf->idx, sizeof(buf->idx))) - return -EFAULT; - if (DRM_COPY_TO_USER(&d->request_sizes[i], - &buf->total, sizeof(buf->total))) - return -EFAULT; - - d->granted_count++; - } - return 0; -} - -int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - struct drm_device_dma *dma = dev->dma; - struct drm_dma *d = data; - int ret = 0; - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - /* Please don't send us buffers. - */ - if (d->send_count != 0) { - DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d->send_count); - return -EINVAL; - } - - /* We'll send you buffers. - */ - if (d->request_count < 0 || d->request_count > dma->buf_count) { - DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d->request_count, dma->buf_count); - return -EINVAL; - } - - d->granted_count = 0; - - if (d->request_count) { - ret = savage_bci_get_buffers(dev, file_priv, d); - } - - return ret; -} - -void savage_reclaim_buffers(struct drm_device *dev, struct drm_file *file_priv) -{ - struct drm_device_dma *dma = dev->dma; - drm_savage_private_t *dev_priv = dev->dev_private; - int i; - - if (!dma) - return; - if (!dev_priv) - return; - if (!dma->buflist) - return; - - for (i = 0; i < dma->buf_count; i++) { - struct drm_buf *buf = dma->buflist[i]; - drm_savage_buf_priv_t *buf_priv = buf->dev_private; - - if (buf->file_priv == file_priv && buf_priv && - buf_priv->next == NULL && buf_priv->prev == NULL) { - uint16_t event; - DRM_DEBUG("reclaimed from client\n"); - event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D); - SET_AGE(&buf_priv->age, event, dev_priv->event_wrap); - savage_freelist_put(dev, buf); - } - } - - drm_core_reclaim_buffers(dev, file_priv); -} - -struct drm_ioctl_desc savage_ioctls[] = { - DRM_IOCTL_DEF(DRM_SAVAGE_BCI_INIT, savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_SAVAGE_BCI_CMDBUF, savage_bci_cmdbuf, DRM_AUTH), - DRM_IOCTL_DEF(DRM_SAVAGE_BCI_EVENT_EMIT, savage_bci_event_emit, DRM_AUTH), - DRM_IOCTL_DEF(DRM_SAVAGE_BCI_EVENT_WAIT, savage_bci_event_wait, DRM_AUTH), -}; - -int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls); diff --git a/shared-core/savage_drm.h b/shared-core/savage_drm.h deleted file mode 100644 index b960d557..00000000 --- a/shared-core/savage_drm.h +++ /dev/null @@ -1,209 +0,0 @@ -/* savage_drm.h -- Public header for the savage driver - * - * Copyright 2004 Felix Kuehling - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF - * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __SAVAGE_DRM_H__ -#define __SAVAGE_DRM_H__ - -#ifndef __SAVAGE_SAREA_DEFINES__ -#define __SAVAGE_SAREA_DEFINES__ - -/* 2 heaps (1 for card, 1 for agp), each divided into upto 128 - * regions, subject to a minimum region size of (1<<16) == 64k. - * - * Clients may subdivide regions internally, but when sharing between - * clients, the region size is the minimum granularity. - */ - -#define SAVAGE_CARD_HEAP 0 -#define SAVAGE_AGP_HEAP 1 -#define SAVAGE_NR_TEX_HEAPS 2 -#define SAVAGE_NR_TEX_REGIONS 16 -#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16 - -#endif /* __SAVAGE_SAREA_DEFINES__ */ - -typedef struct _drm_savage_sarea { - /* LRU lists for texture memory in agp space and on the card. - */ - struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS+1]; - unsigned int texAge[SAVAGE_NR_TEX_HEAPS]; - - /* Mechanism to validate card state. - */ - int ctxOwner; -} drm_savage_sarea_t, *drm_savage_sarea_ptr; - -/* Savage-specific ioctls - */ -#define DRM_SAVAGE_BCI_INIT 0x00 -#define DRM_SAVAGE_BCI_CMDBUF 0x01 -#define DRM_SAVAGE_BCI_EVENT_EMIT 0x02 -#define DRM_SAVAGE_BCI_EVENT_WAIT 0x03 - -#define DRM_IOCTL_SAVAGE_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t) -#define DRM_IOCTL_SAVAGE_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t) -#define DRM_IOCTL_SAVAGE_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t) -#define DRM_IOCTL_SAVAGE_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t) - -#define SAVAGE_DMA_PCI 1 -#define SAVAGE_DMA_AGP 3 -typedef struct drm_savage_init { - enum { - SAVAGE_INIT_BCI = 1, - SAVAGE_CLEANUP_BCI = 2 - } func; - unsigned int sarea_priv_offset; - - /* some parameters */ - unsigned int cob_size; - unsigned int bci_threshold_lo, bci_threshold_hi; - unsigned int dma_type; - - /* frame buffer layout */ - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - - /* local textures */ - unsigned int texture_offset; - unsigned int texture_size; - - /* physical locations of non-permanent maps */ - unsigned long status_offset; - unsigned long buffers_offset; - unsigned long agp_textures_offset; - unsigned long cmd_dma_offset; -} drm_savage_init_t; - -typedef union drm_savage_cmd_header drm_savage_cmd_header_t; -typedef struct drm_savage_cmdbuf { - /* command buffer in client's address space */ - drm_savage_cmd_header_t __user *cmd_addr; - unsigned int size; /* size of the command buffer in 64bit units */ - - unsigned int dma_idx; /* DMA buffer index to use */ - int discard; /* discard DMA buffer when done */ - /* vertex buffer in client's address space */ - unsigned int __user *vb_addr; - unsigned int vb_size; /* size of client vertex buffer in bytes */ - unsigned int vb_stride; /* stride of vertices in 32bit words */ - /* boxes in client's address space */ - struct drm_clip_rect __user *box_addr; - unsigned int nbox; /* number of clipping boxes */ -} drm_savage_cmdbuf_t; - -#define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */ -#define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */ -#define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */ -typedef struct drm_savage_event { - unsigned int count; - unsigned int flags; -} drm_savage_event_emit_t, drm_savage_event_wait_t; - -/* Commands for the cmdbuf ioctl - */ -#define SAVAGE_CMD_STATE 0 /* a range of state registers */ -#define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */ -#define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */ -#define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */ -#define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */ -#define SAVAGE_CMD_CLEAR 5 /* clear buffers */ -#define SAVAGE_CMD_SWAP 6 /* swap buffers */ - -/* Primitive types -*/ -#define SAVAGE_PRIM_TRILIST 0 /* triangle list */ -#define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */ -#define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */ -#define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat - * shading on s3d */ - -/* Skip flags (vertex format) - */ -#define SAVAGE_SKIP_Z 0x01 -#define SAVAGE_SKIP_W 0x02 -#define SAVAGE_SKIP_C0 0x04 -#define SAVAGE_SKIP_C1 0x08 -#define SAVAGE_SKIP_S0 0x10 -#define SAVAGE_SKIP_T0 0x20 -#define SAVAGE_SKIP_ST0 0x30 -#define SAVAGE_SKIP_S1 0x40 -#define SAVAGE_SKIP_T1 0x80 -#define SAVAGE_SKIP_ST1 0xc0 -#define SAVAGE_SKIP_ALL_S3D 0x3f -#define SAVAGE_SKIP_ALL_S4 0xff - -/* Buffer names for clear command - */ -#define SAVAGE_FRONT 0x1 -#define SAVAGE_BACK 0x2 -#define SAVAGE_DEPTH 0x4 - -/* 64-bit command header - */ -union drm_savage_cmd_header { - struct { - unsigned char cmd; /* command */ - unsigned char pad0; - unsigned short pad1; - unsigned short pad2; - unsigned short pad3; - } cmd; /* generic */ - struct { - unsigned char cmd; - unsigned char global; /* need idle engine? */ - unsigned short count; /* number of consecutive registers */ - unsigned short start; /* first register */ - unsigned short pad3; - } state; /* SAVAGE_CMD_STATE */ - struct { - unsigned char cmd; - unsigned char prim; /* primitive type */ - unsigned short skip; /* vertex format (skip flags) */ - unsigned short count; /* number of vertices */ - unsigned short start; /* first vertex in DMA/vertex buffer */ - } prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */ - struct { - unsigned char cmd; - unsigned char prim; - unsigned short skip; - unsigned short count; /* number of indices that follow */ - unsigned short pad3; - } idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */ - struct { - unsigned char cmd; - unsigned char pad0; - unsigned short pad1; - unsigned int flags; - } clear0; /* SAVAGE_CMD_CLEAR */ - struct { - unsigned int mask; - unsigned int value; - } clear1; /* SAVAGE_CMD_CLEAR data */ -}; - -#endif diff --git a/shared-core/savage_drv.h b/shared-core/savage_drv.h deleted file mode 100644 index b9124b1a..00000000 --- a/shared-core/savage_drv.h +++ /dev/null @@ -1,575 +0,0 @@ -/* savage_drv.h -- Private header for the savage driver */ -/* - * Copyright 2004 Felix Kuehling - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF - * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __SAVAGE_DRV_H__ -#define __SAVAGE_DRV_H__ - -#define DRIVER_AUTHOR "Felix Kuehling" - -#define DRIVER_NAME "savage" -#define DRIVER_DESC "Savage3D/MX/IX, Savage4, SuperSavage, Twister, ProSavage[DDR]" -#define DRIVER_DATE "20050313" - -#define DRIVER_MAJOR 2 -#define DRIVER_MINOR 4 -#define DRIVER_PATCHLEVEL 1 -/* Interface history: - * - * 1.x The DRM driver from the VIA/S3 code drop, basically a dummy - * 2.0 The first real DRM - * 2.1 Scissors registers managed by the DRM, 3D operations clipped by - * cliprects of the cmdbuf ioctl - * 2.2 Implemented SAVAGE_CMD_DMA_IDX and SAVAGE_CMD_VB_IDX - * 2.3 Event counters used by BCI_EVENT_EMIT/WAIT ioctls are now 32 bits - * wide and thus very long lived (unlikely to ever wrap). The size - * in the struct was 32 bits before, but only 16 bits were used - * 2.4 Implemented command DMA. Now drm_savage_init_t.cmd_dma_offset is - * actually used - */ - -typedef struct drm_savage_age { - uint16_t event; - unsigned int wrap; -} drm_savage_age_t; - -typedef struct drm_savage_buf_priv { - struct drm_savage_buf_priv *next; - struct drm_savage_buf_priv *prev; - drm_savage_age_t age; - struct drm_buf *buf; -} drm_savage_buf_priv_t; - -typedef struct drm_savage_dma_page { - drm_savage_age_t age; - unsigned int used, flushed; -} drm_savage_dma_page_t; -#define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */ -/* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command - * size of 16kbytes or 4k entries. Minimum requirement would be - * 10kbytes for 255 40-byte vertices in one drawing command. */ -#define SAVAGE_FAKE_DMA_SIZE (SAVAGE_DMA_PAGE_SIZE*4*4) - -/* interesting bits of hardware state that are saved in dev_priv */ -typedef union { - struct drm_savage_common_state { - uint32_t vbaddr; - } common; - struct { - unsigned char pad[sizeof(struct drm_savage_common_state)]; - uint32_t texctrl, texaddr; - uint32_t scstart, new_scstart; - uint32_t scend, new_scend; - } s3d; - struct { - unsigned char pad[sizeof(struct drm_savage_common_state)]; - uint32_t texdescr, texaddr0, texaddr1; - uint32_t drawctrl0, new_drawctrl0; - uint32_t drawctrl1, new_drawctrl1; - } s4; -} drm_savage_state_t; - -/* these chip tags should match the ones in the 2D driver in savage_regs.h. */ -enum savage_family { - S3_UNKNOWN = 0, - S3_SAVAGE3D, - S3_SAVAGE_MX, - S3_SAVAGE4, - S3_PROSAVAGE, - S3_TWISTER, - S3_PROSAVAGEDDR, - S3_SUPERSAVAGE, - S3_SAVAGE2000, - S3_LAST -}; - -extern struct drm_ioctl_desc savage_ioctls[]; -extern int savage_max_ioctl; - -#define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) - -#define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \ - || (chip==S3_PROSAVAGE) \ - || (chip==S3_TWISTER) \ - || (chip==S3_PROSAVAGEDDR)) - -#define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) - -#define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) - -#define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) \ - ||(chip==S3_PROSAVAGEDDR)) - -/* flags */ -#define SAVAGE_IS_AGP 1 - -typedef struct drm_savage_private { - drm_savage_sarea_t *sarea_priv; - - drm_savage_buf_priv_t head, tail; - - /* who am I? */ - enum savage_family chipset; - - unsigned int cob_size; - unsigned int bci_threshold_lo, bci_threshold_hi; - unsigned int dma_type; - - /* frame buffer layout */ - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - - /* bitmap descriptors for swap and clear */ - unsigned int front_bd, back_bd, depth_bd; - - /* local textures */ - unsigned int texture_offset; - unsigned int texture_size; - - /* memory regions in physical memory */ - drm_local_map_t *sarea; - drm_local_map_t *mmio; - drm_local_map_t *fb; - drm_local_map_t *aperture; - drm_local_map_t *status; - drm_local_map_t *agp_textures; - drm_local_map_t *cmd_dma; - drm_local_map_t fake_dma; - - struct { - int handle; - unsigned long base, size; - } mtrr[3]; - - /* BCI and status-related stuff */ - volatile uint32_t *status_ptr, *bci_ptr; - uint32_t status_used_mask; - uint16_t event_counter; - unsigned int event_wrap; - - /* Savage4 command DMA */ - drm_savage_dma_page_t *dma_pages; - unsigned int nr_dma_pages, first_dma_page, current_dma_page; - drm_savage_age_t last_dma_age; - - /* saved hw state for global/local check on S3D */ - uint32_t hw_draw_ctrl, hw_zbuf_ctrl; - /* and for scissors (global, so don't emit if not changed) */ - uint32_t hw_scissors_start, hw_scissors_end; - - drm_savage_state_t state; - - /* after emitting a wait cmd Savage3D needs 63 nops before next DMA */ - unsigned int waiting; - - /* config/hardware-dependent function pointers */ - int (*wait_fifo)(struct drm_savage_private *dev_priv, unsigned int n); - int (*wait_evnt)(struct drm_savage_private *dev_priv, uint16_t e); - /* Err, there is a macro wait_event in include/linux/wait.h. - * Avoid unwanted macro expansion. */ - void (*emit_clip_rect)(struct drm_savage_private *dev_priv, - const struct drm_clip_rect *pbox); - void (*dma_flush)(struct drm_savage_private *dev_priv); -} drm_savage_private_t; - -/* ioctls */ -extern int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); - -/* BCI functions */ -extern uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, - unsigned int flags); -extern void savage_freelist_put(struct drm_device *dev, struct drm_buf *buf); -extern void savage_dma_reset(drm_savage_private_t *dev_priv); -extern void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page); -extern uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, - unsigned int n); -extern int savage_driver_load(struct drm_device *dev, unsigned long chipset); -extern int savage_driver_firstopen(struct drm_device *dev); -extern void savage_driver_lastclose(struct drm_device *dev); -extern int savage_driver_unload(struct drm_device *dev); -extern void savage_reclaim_buffers(struct drm_device *dev, - struct drm_file *file_priv); - -/* state functions */ -extern void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv, - const struct drm_clip_rect *pbox); -extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv, - const struct drm_clip_rect *pbox); - -#define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */ -#define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */ -#define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */ -#define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */ -#define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */ - -#define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region - * inside the MMIO region */ -#define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip - * BCI FIFO */ - -/* - * MMIO registers - */ -#define SAVAGE_STATUS_WORD0 0x48C00 -#define SAVAGE_STATUS_WORD1 0x48C04 -#define SAVAGE_ALT_STATUS_WORD0 0x48C60 - -#define SAVAGE_FIFO_USED_MASK_S3D 0x0001ffff -#define SAVAGE_FIFO_USED_MASK_S4 0x001fffff - -/* Copied from savage_bci.h in the 2D driver with some renaming. */ - -/* Bitmap descriptors */ -#define SAVAGE_BD_STRIDE_SHIFT 0 -#define SAVAGE_BD_BPP_SHIFT 16 -#define SAVAGE_BD_TILE_SHIFT 24 -#define SAVAGE_BD_BW_DISABLE (1<<28) -/* common: */ -#define SAVAGE_BD_TILE_LINEAR 0 -/* savage4, MX, IX, 3D */ -#define SAVAGE_BD_TILE_16BPP 2 -#define SAVAGE_BD_TILE_32BPP 3 -/* twister, prosavage, DDR, supersavage, 2000 */ -#define SAVAGE_BD_TILE_DEST 1 -#define SAVAGE_BD_TILE_TEXTURE 2 -/* GBD - BCI enable */ -/* savage4, MX, IX, 3D */ -#define SAVAGE_GBD_BCI_ENABLE 8 -/* twister, prosavage, DDR, supersavage, 2000 */ -#define SAVAGE_GBD_BCI_ENABLE_TWISTER 0 - -#define SAVAGE_GBD_BIG_ENDIAN 4 -#define SAVAGE_GBD_LITTLE_ENDIAN 0 -#define SAVAGE_GBD_64 1 - -/* Global Bitmap Descriptor */ -#define SAVAGE_BCI_GLB_BD_LOW 0x8168 -#define SAVAGE_BCI_GLB_BD_HIGH 0x816C - -/* - * BCI registers - */ -/* Savage4/Twister/ProSavage 3D registers */ -#define SAVAGE_DRAWLOCALCTRL_S4 0x1e -#define SAVAGE_TEXPALADDR_S4 0x1f -#define SAVAGE_TEXCTRL0_S4 0x20 -#define SAVAGE_TEXCTRL1_S4 0x21 -#define SAVAGE_TEXADDR0_S4 0x22 -#define SAVAGE_TEXADDR1_S4 0x23 -#define SAVAGE_TEXBLEND0_S4 0x24 -#define SAVAGE_TEXBLEND1_S4 0x25 -#define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */ -#define SAVAGE_TEXDESCR_S4 0x27 -#define SAVAGE_FOGTABLE_S4 0x28 -#define SAVAGE_FOGCTRL_S4 0x30 -#define SAVAGE_STENCILCTRL_S4 0x31 -#define SAVAGE_ZBUFCTRL_S4 0x32 -#define SAVAGE_ZBUFOFF_S4 0x33 -#define SAVAGE_DESTCTRL_S4 0x34 -#define SAVAGE_DRAWCTRL0_S4 0x35 -#define SAVAGE_DRAWCTRL1_S4 0x36 -#define SAVAGE_ZWATERMARK_S4 0x37 -#define SAVAGE_DESTTEXRWWATERMARK_S4 0x38 -#define SAVAGE_TEXBLENDCOLOR_S4 0x39 -/* Savage3D/MX/IX 3D registers */ -#define SAVAGE_TEXPALADDR_S3D 0x18 -#define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */ -#define SAVAGE_TEXADDR_S3D 0x1A -#define SAVAGE_TEXDESCR_S3D 0x1B -#define SAVAGE_TEXCTRL_S3D 0x1C -#define SAVAGE_FOGTABLE_S3D 0x20 -#define SAVAGE_FOGCTRL_S3D 0x30 -#define SAVAGE_DRAWCTRL_S3D 0x31 -#define SAVAGE_ZBUFCTRL_S3D 0x32 -#define SAVAGE_ZBUFOFF_S3D 0x33 -#define SAVAGE_DESTCTRL_S3D 0x34 -#define SAVAGE_SCSTART_S3D 0x35 -#define SAVAGE_SCEND_S3D 0x36 -#define SAVAGE_ZWATERMARK_S3D 0x37 -#define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38 -/* common stuff */ -#define SAVAGE_VERTBUFADDR 0x3e -#define SAVAGE_BITPLANEWTMASK 0xd7 -#define SAVAGE_DMABUFADDR 0x51 - -/* texture enable bits (needed for tex addr checking) */ -#define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */ -#define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */ -#define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */ - -/* Global fields in Savage4/Twister/ProSavage 3D registers: - * - * All texture registers and DrawLocalCtrl are local. All other - * registers are global. */ - -/* Global fields in Savage3D/MX/IX 3D registers: - * - * All texture registers are local. DrawCtrl and ZBufCtrl are - * partially local. All other registers are global. - * - * DrawCtrl global fields: cullMode, alphaTestCmpFunc, alphaTestEn, alphaRefVal - * ZBufCtrl global fields: zCmpFunc, zBufEn - */ -#define SAVAGE_DRAWCTRL_S3D_GLOBAL 0x03f3c00c -#define SAVAGE_ZBUFCTRL_S3D_GLOBAL 0x00000027 - -/* Masks for scissor bits (drawCtrl[01] on s4, scissorStart/End on s3d) - */ -#define SAVAGE_SCISSOR_MASK_S4 0x00fff7ff -#define SAVAGE_SCISSOR_MASK_S3D 0x07ff07ff - -/* - * BCI commands - */ -#define BCI_CMD_NOP 0x40000000 -#define BCI_CMD_RECT 0x48000000 -#define BCI_CMD_RECT_XP 0x01000000 -#define BCI_CMD_RECT_YP 0x02000000 -#define BCI_CMD_SCANLINE 0x50000000 -#define BCI_CMD_LINE 0x5C000000 -#define BCI_CMD_LINE_LAST_PIXEL 0x58000000 -#define BCI_CMD_BYTE_TEXT 0x63000000 -#define BCI_CMD_NT_BYTE_TEXT 0x67000000 -#define BCI_CMD_BIT_TEXT 0x6C000000 -#define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF) -#define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16)) -#define BCI_CMD_SEND_COLOR 0x00008000 - -#define BCI_CMD_CLIP_NONE 0x00000000 -#define BCI_CMD_CLIP_CURRENT 0x00002000 -#define BCI_CMD_CLIP_LR 0x00004000 -#define BCI_CMD_CLIP_NEW 0x00006000 - -#define BCI_CMD_DEST_GBD 0x00000000 -#define BCI_CMD_DEST_PBD 0x00000800 -#define BCI_CMD_DEST_PBD_NEW 0x00000C00 -#define BCI_CMD_DEST_SBD 0x00001000 -#define BCI_CMD_DEST_SBD_NEW 0x00001400 - -#define BCI_CMD_SRC_TRANSPARENT 0x00000200 -#define BCI_CMD_SRC_SOLID 0x00000000 -#define BCI_CMD_SRC_GBD 0x00000020 -#define BCI_CMD_SRC_COLOR 0x00000040 -#define BCI_CMD_SRC_MONO 0x00000060 -#define BCI_CMD_SRC_PBD_COLOR 0x00000080 -#define BCI_CMD_SRC_PBD_MONO 0x000000A0 -#define BCI_CMD_SRC_PBD_COLOR_NEW 0x000000C0 -#define BCI_CMD_SRC_PBD_MONO_NEW 0x000000E0 -#define BCI_CMD_SRC_SBD_COLOR 0x00000100 -#define BCI_CMD_SRC_SBD_MONO 0x00000120 -#define BCI_CMD_SRC_SBD_COLOR_NEW 0x00000140 -#define BCI_CMD_SRC_SBD_MONO_NEW 0x00000160 - -#define BCI_CMD_PAT_TRANSPARENT 0x00000010 -#define BCI_CMD_PAT_NONE 0x00000000 -#define BCI_CMD_PAT_COLOR 0x00000002 -#define BCI_CMD_PAT_MONO 0x00000003 -#define BCI_CMD_PAT_PBD_COLOR 0x00000004 -#define BCI_CMD_PAT_PBD_MONO 0x00000005 -#define BCI_CMD_PAT_PBD_COLOR_NEW 0x00000006 -#define BCI_CMD_PAT_PBD_MONO_NEW 0x00000007 -#define BCI_CMD_PAT_SBD_COLOR 0x00000008 -#define BCI_CMD_PAT_SBD_MONO 0x00000009 -#define BCI_CMD_PAT_SBD_COLOR_NEW 0x0000000A -#define BCI_CMD_PAT_SBD_MONO_NEW 0x0000000B - -#define BCI_BD_BW_DISABLE 0x10000000 -#define BCI_BD_TILE_MASK 0x03000000 -#define BCI_BD_TILE_NONE 0x00000000 -#define BCI_BD_TILE_16 0x02000000 -#define BCI_BD_TILE_32 0x03000000 -#define BCI_BD_GET_BPP(bd) (((bd) >> 16) & 0xFF) -#define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16)) -#define BCI_BD_GET_STRIDE(bd) ((bd) & 0xFFFF) -#define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF)) - -#define BCI_CMD_SET_REGISTER 0x96000000 - -#define BCI_CMD_WAIT 0xC0000000 -#define BCI_CMD_WAIT_3D 0x00010000 -#define BCI_CMD_WAIT_2D 0x00020000 - -#define BCI_CMD_UPDATE_EVENT_TAG 0x98000000 - -#define BCI_CMD_DRAW_PRIM 0x80000000 -#define BCI_CMD_DRAW_INDEXED_PRIM 0x88000000 -#define BCI_CMD_DRAW_CONT 0x01000000 -#define BCI_CMD_DRAW_TRILIST 0x00000000 -#define BCI_CMD_DRAW_TRISTRIP 0x02000000 -#define BCI_CMD_DRAW_TRIFAN 0x04000000 -#define BCI_CMD_DRAW_SKIPFLAGS 0x000000ff -#define BCI_CMD_DRAW_NO_Z 0x00000001 -#define BCI_CMD_DRAW_NO_W 0x00000002 -#define BCI_CMD_DRAW_NO_CD 0x00000004 -#define BCI_CMD_DRAW_NO_CS 0x00000008 -#define BCI_CMD_DRAW_NO_U0 0x00000010 -#define BCI_CMD_DRAW_NO_V0 0x00000020 -#define BCI_CMD_DRAW_NO_UV0 0x00000030 -#define BCI_CMD_DRAW_NO_U1 0x00000040 -#define BCI_CMD_DRAW_NO_V1 0x00000080 -#define BCI_CMD_DRAW_NO_UV1 0x000000c0 - -#define BCI_CMD_DMA 0xa8000000 - -#define BCI_W_H(w, h) ((((h) << 16) | (w)) & 0x0FFF0FFF) -#define BCI_X_Y(x, y) ((((y) << 16) | (x)) & 0x0FFF0FFF) -#define BCI_X_W(x, y) ((((w) << 16) | (x)) & 0x0FFF0FFF) -#define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF) -#define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF) -#define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF) - -#define BCI_LINE_X_Y(x, y) (((y) << 16) | ((x) & 0xFFFF)) -#define BCI_LINE_STEPS(diag, axi) (((axi) << 16) | ((diag) & 0xFFFF)) -#define BCI_LINE_MISC(maj, ym, xp, yp, err) \ - (((maj) & 0x1FFF) | \ - ((ym) ? 1<<13 : 0) | \ - ((xp) ? 1<<14 : 0) | \ - ((yp) ? 1<<15 : 0) | \ - ((err) << 16)) - -/* - * common commands - */ -#define BCI_SET_REGISTERS( first, n ) \ - BCI_WRITE(BCI_CMD_SET_REGISTER | \ - ((uint32_t)(n) & 0xff) << 16 | \ - ((uint32_t)(first) & 0xffff)) -#define DMA_SET_REGISTERS( first, n ) \ - DMA_WRITE(BCI_CMD_SET_REGISTER | \ - ((uint32_t)(n) & 0xff) << 16 | \ - ((uint32_t)(first) & 0xffff)) - -#define BCI_DRAW_PRIMITIVE(n, type, skip) \ - BCI_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \ - ((n) << 16)) -#define DMA_DRAW_PRIMITIVE(n, type, skip) \ - DMA_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \ - ((n) << 16)) - -#define BCI_DRAW_INDICES_S3D(n, type, i0) \ - BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \ - ((n) << 16) | (i0)) - -#define BCI_DRAW_INDICES_S4(n, type, skip) \ - BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \ - (skip) | ((n) << 16)) - -#define BCI_DMA(n) \ - BCI_WRITE(BCI_CMD_DMA | (((n) >> 1) - 1)) - -/* - * access to MMIO - */ -#define SAVAGE_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) -#define SAVAGE_WRITE(reg) DRM_WRITE32( dev_priv->mmio, (reg) ) - -/* - * access to the burst command interface (BCI) - */ -#define SAVAGE_BCI_DEBUG 1 - -#define BCI_LOCALS volatile uint32_t *bci_ptr; - -#define BEGIN_BCI( n ) do { \ - dev_priv->wait_fifo(dev_priv, (n)); \ - bci_ptr = dev_priv->bci_ptr; \ -} while(0) - -#define BCI_WRITE( val ) *bci_ptr++ = (uint32_t)(val) - -/* - * command DMA support - */ -#define SAVAGE_DMA_DEBUG 1 - -#define DMA_LOCALS uint32_t *dma_ptr; - -#define BEGIN_DMA( n ) do { \ - unsigned int cur = dev_priv->current_dma_page; \ - unsigned int rest = SAVAGE_DMA_PAGE_SIZE - \ - dev_priv->dma_pages[cur].used; \ - if ((n) > rest) { \ - dma_ptr = savage_dma_alloc(dev_priv, (n)); \ - } else { /* fast path for small allocations */ \ - dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + \ - cur * SAVAGE_DMA_PAGE_SIZE + \ - dev_priv->dma_pages[cur].used; \ - if (dev_priv->dma_pages[cur].used == 0) \ - savage_dma_wait(dev_priv, cur); \ - dev_priv->dma_pages[cur].used += (n); \ - } \ -} while(0) - -#define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val) - -#define DMA_COPY(src, n) do { \ - memcpy(dma_ptr, (src), (n)*4); \ - dma_ptr += n; \ -} while(0) - -#if SAVAGE_DMA_DEBUG -#define DMA_COMMIT() do { \ - unsigned int cur = dev_priv->current_dma_page; \ - uint32_t *expected = (uint32_t *)dev_priv->cmd_dma->handle + \ - cur * SAVAGE_DMA_PAGE_SIZE + \ - dev_priv->dma_pages[cur].used; \ - if (dma_ptr != expected) { \ - DRM_ERROR("DMA allocation and use don't match: " \ - "%p != %p\n", expected, dma_ptr); \ - savage_dma_reset(dev_priv); \ - } \ -} while(0) -#else -#define DMA_COMMIT() do {/* nothing */} while(0) -#endif - -#define DMA_FLUSH() dev_priv->dma_flush(dev_priv) - -/* Buffer aging via event tag - */ - -#define UPDATE_EVENT_COUNTER( ) do { \ - if (dev_priv->status_ptr) { \ - uint16_t count; \ - /* coordinate with Xserver */ \ - count = dev_priv->status_ptr[1023]; \ - if (count < dev_priv->event_counter) \ - dev_priv->event_wrap++; \ - dev_priv->event_counter = count; \ - } \ -} while(0) - -#define SET_AGE( age, e, w ) do { \ - (age)->event = e; \ - (age)->wrap = w; \ -} while(0) - -#define TEST_AGE( age, e, w ) \ - ( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) ) - -#endif /* __SAVAGE_DRV_H__ */ diff --git a/shared-core/savage_state.c b/shared-core/savage_state.c deleted file mode 100644 index 1c5a0e2e..00000000 --- a/shared-core/savage_state.c +++ /dev/null @@ -1,1165 +0,0 @@ -/* savage_state.c -- State and drawing support for Savage - * - * Copyright 2004 Felix Kuehling - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF - * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#include "drmP.h" -#include "savage_drm.h" -#include "savage_drv.h" - -void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv, - const struct drm_clip_rect *pbox) -{ - uint32_t scstart = dev_priv->state.s3d.new_scstart; - uint32_t scend = dev_priv->state.s3d.new_scend; - scstart = (scstart & ~SAVAGE_SCISSOR_MASK_S3D) | - ((uint32_t)pbox->x1 & 0x000007ff) | - (((uint32_t)pbox->y1 << 16) & 0x07ff0000); - scend = (scend & ~SAVAGE_SCISSOR_MASK_S3D) | - (((uint32_t)pbox->x2 - 1) & 0x000007ff) | - ((((uint32_t)pbox->y2 - 1) << 16) & 0x07ff0000); - if (scstart != dev_priv->state.s3d.scstart || - scend != dev_priv->state.s3d.scend) { - DMA_LOCALS; - BEGIN_DMA(4); - DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D); - DMA_SET_REGISTERS(SAVAGE_SCSTART_S3D, 2); - DMA_WRITE(scstart); - DMA_WRITE(scend); - dev_priv->state.s3d.scstart = scstart; - dev_priv->state.s3d.scend = scend; - dev_priv->waiting = 1; - DMA_COMMIT(); - } -} - -void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv, - const struct drm_clip_rect *pbox) -{ - uint32_t drawctrl0 = dev_priv->state.s4.new_drawctrl0; - uint32_t drawctrl1 = dev_priv->state.s4.new_drawctrl1; - drawctrl0 = (drawctrl0 & ~SAVAGE_SCISSOR_MASK_S4) | - ((uint32_t)pbox->x1 & 0x000007ff) | - (((uint32_t)pbox->y1 << 12) & 0x00fff000); - drawctrl1 = (drawctrl1 & ~SAVAGE_SCISSOR_MASK_S4) | - (((uint32_t)pbox->x2 - 1) & 0x000007ff) | - ((((uint32_t)pbox->y2 - 1) << 12) & 0x00fff000); - if (drawctrl0 != dev_priv->state.s4.drawctrl0 || - drawctrl1 != dev_priv->state.s4.drawctrl1) { - DMA_LOCALS; - BEGIN_DMA(4); - DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D); - DMA_SET_REGISTERS(SAVAGE_DRAWCTRL0_S4, 2); - DMA_WRITE(drawctrl0); - DMA_WRITE(drawctrl1); - dev_priv->state.s4.drawctrl0 = drawctrl0; - dev_priv->state.s4.drawctrl1 = drawctrl1; - dev_priv->waiting = 1; - DMA_COMMIT(); - } -} - -static int savage_verify_texaddr(drm_savage_private_t *dev_priv, int unit, - uint32_t addr) -{ - if ((addr & 6) != 2) { /* reserved bits */ - DRM_ERROR("bad texAddr%d %08x (reserved bits)\n", unit, addr); - return -EINVAL; - } - if (!(addr & 1)) { /* local */ - addr &= ~7; - if (addr < dev_priv->texture_offset || - addr >= dev_priv->texture_offset + dev_priv->texture_size) { - DRM_ERROR - ("bad texAddr%d %08x (local addr out of range)\n", - unit, addr); - return -EINVAL; - } - } else { /* AGP */ - if (!dev_priv->agp_textures) { - DRM_ERROR("bad texAddr%d %08x (AGP not available)\n", - unit, addr); - return -EINVAL; - } - addr &= ~7; - if (addr < dev_priv->agp_textures->offset || - addr >= (dev_priv->agp_textures->offset + - dev_priv->agp_textures->size)) { - DRM_ERROR - ("bad texAddr%d %08x (AGP addr out of range)\n", - unit, addr); - return -EINVAL; - } - } - return 0; -} - -#define SAVE_STATE(reg,where) \ - if(start <= reg && start + count > reg) \ - dev_priv->state.where = regs[reg - start] -#define SAVE_STATE_MASK(reg,where,mask) do { \ - if(start <= reg && start + count > reg) { \ - uint32_t tmp; \ - tmp = regs[reg - start]; \ - dev_priv->state.where = (tmp & (mask)) | \ - (dev_priv->state.where & ~(mask)); \ - } \ -} while (0) -static int savage_verify_state_s3d(drm_savage_private_t *dev_priv, - unsigned int start, unsigned int count, - const uint32_t *regs) -{ - if (start < SAVAGE_TEXPALADDR_S3D || - start + count - 1 > SAVAGE_DESTTEXRWWATERMARK_S3D) { - DRM_ERROR("invalid register range (0x%04x-0x%04x)\n", - start, start + count - 1); - return -EINVAL; - } - - SAVE_STATE_MASK(SAVAGE_SCSTART_S3D, s3d.new_scstart, - ~SAVAGE_SCISSOR_MASK_S3D); - SAVE_STATE_MASK(SAVAGE_SCEND_S3D, s3d.new_scend, - ~SAVAGE_SCISSOR_MASK_S3D); - - /* if any texture regs were changed ... */ - if (start <= SAVAGE_TEXCTRL_S3D && - start + count > SAVAGE_TEXPALADDR_S3D) { - /* ... check texture state */ - SAVE_STATE(SAVAGE_TEXCTRL_S3D, s3d.texctrl); - SAVE_STATE(SAVAGE_TEXADDR_S3D, s3d.texaddr); - if (dev_priv->state.s3d.texctrl & SAVAGE_TEXCTRL_TEXEN_MASK) - return savage_verify_texaddr(dev_priv, 0, - dev_priv->state.s3d.texaddr); - } - - return 0; -} - -static int savage_verify_state_s4(drm_savage_private_t *dev_priv, - unsigned int start, unsigned int count, - const uint32_t *regs) -{ - int ret = 0; - - if (start < SAVAGE_DRAWLOCALCTRL_S4 || - start + count - 1 > SAVAGE_TEXBLENDCOLOR_S4) { - DRM_ERROR("invalid register range (0x%04x-0x%04x)\n", - start, start + count - 1); - return -EINVAL; - } - - SAVE_STATE_MASK(SAVAGE_DRAWCTRL0_S4, s4.new_drawctrl0, - ~SAVAGE_SCISSOR_MASK_S4); - SAVE_STATE_MASK(SAVAGE_DRAWCTRL1_S4, s4.new_drawctrl1, - ~SAVAGE_SCISSOR_MASK_S4); - - /* if any texture regs were changed ... */ - if (start <= SAVAGE_TEXDESCR_S4 && - start + count > SAVAGE_TEXPALADDR_S4) { - /* ... check texture state */ - SAVE_STATE(SAVAGE_TEXDESCR_S4, s4.texdescr); - SAVE_STATE(SAVAGE_TEXADDR0_S4, s4.texaddr0); - SAVE_STATE(SAVAGE_TEXADDR1_S4, s4.texaddr1); - if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX0EN_MASK) - ret |= savage_verify_texaddr(dev_priv, 0, - dev_priv->state.s4.texaddr0); - if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX1EN_MASK) - ret |= savage_verify_texaddr(dev_priv, 1, - dev_priv->state.s4.texaddr1); - } - - return ret; -} -#undef SAVE_STATE -#undef SAVE_STATE_MASK - -static int savage_dispatch_state(drm_savage_private_t *dev_priv, - const drm_savage_cmd_header_t *cmd_header, - const uint32_t *regs) -{ - unsigned int count = cmd_header->state.count; - unsigned int start = cmd_header->state.start; - unsigned int count2 = 0; - unsigned int bci_size; - int ret; - DMA_LOCALS; - - if (!count) - return 0; - - if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { - ret = savage_verify_state_s3d(dev_priv, start, count, regs); - if (ret != 0) - return ret; - /* scissor regs are emitted in savage_dispatch_draw */ - if (start < SAVAGE_SCSTART_S3D) { - if (start + count > SAVAGE_SCEND_S3D + 1) - count2 = count - (SAVAGE_SCEND_S3D + 1 - start); - if (start + count > SAVAGE_SCSTART_S3D) - count = SAVAGE_SCSTART_S3D - start; - } else if (start <= SAVAGE_SCEND_S3D) { - if (start + count > SAVAGE_SCEND_S3D + 1) { - count -= SAVAGE_SCEND_S3D + 1 - start; - start = SAVAGE_SCEND_S3D + 1; - } else - return 0; - } - } else { - ret = savage_verify_state_s4(dev_priv, start, count, regs); - if (ret != 0) - return ret; - /* scissor regs are emitted in savage_dispatch_draw */ - if (start < SAVAGE_DRAWCTRL0_S4) { - if (start + count > SAVAGE_DRAWCTRL1_S4 + 1) - count2 = count - - (SAVAGE_DRAWCTRL1_S4 + 1 - start); - if (start + count > SAVAGE_DRAWCTRL0_S4) - count = SAVAGE_DRAWCTRL0_S4 - start; - } else if (start <= SAVAGE_DRAWCTRL1_S4) { - if (start + count > SAVAGE_DRAWCTRL1_S4 + 1) { - count -= SAVAGE_DRAWCTRL1_S4 + 1 - start; - start = SAVAGE_DRAWCTRL1_S4 + 1; - } else - return 0; - } - } - - bci_size = count + (count + 254) / 255 + count2 + (count2 + 254) / 255; - - if (cmd_header->state.global) { - BEGIN_DMA(bci_size + 1); - DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D); - dev_priv->waiting = 1; - } else { - BEGIN_DMA(bci_size); - } - - do { - while (count > 0) { - unsigned int n = count < 255 ? count : 255; - DMA_SET_REGISTERS(start, n); - DMA_COPY(regs, n); - count -= n; - start += n; - regs += n; - } - start += 2; - regs += 2; - count = count2; - count2 = 0; - } while (count); - - DMA_COMMIT(); - - return 0; -} - -static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv, - const drm_savage_cmd_header_t *cmd_header, - const struct drm_buf *dmabuf) -{ - unsigned char reorder = 0; - unsigned int prim = cmd_header->prim.prim; - unsigned int skip = cmd_header->prim.skip; - unsigned int n = cmd_header->prim.count; - unsigned int start = cmd_header->prim.start; - unsigned int i; - BCI_LOCALS; - - if (!dmabuf) { - DRM_ERROR("called without dma buffers!\n"); - return -EINVAL; - } - - if (!n) - return 0; - - switch (prim) { - case SAVAGE_PRIM_TRILIST_201: - reorder = 1; - prim = SAVAGE_PRIM_TRILIST; - case SAVAGE_PRIM_TRILIST: - if (n % 3 != 0) { - DRM_ERROR("wrong number of vertices %u in TRILIST\n", - n); - return -EINVAL; - } - break; - case SAVAGE_PRIM_TRISTRIP: - case SAVAGE_PRIM_TRIFAN: - if (n < 3) { - DRM_ERROR - ("wrong number of vertices %u in TRIFAN/STRIP\n", - n); - return -EINVAL; - } - break; - default: - DRM_ERROR("invalid primitive type %u\n", prim); - return -EINVAL; - } - - if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { - if (skip != 0) { - DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip); - return -EINVAL; - } - } else { - unsigned int size = 10 - (skip & 1) - (skip >> 1 & 1) - - (skip >> 2 & 1) - (skip >> 3 & 1) - (skip >> 4 & 1) - - (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1); - if (skip > SAVAGE_SKIP_ALL_S4 || size != 8) { - DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip); - return -EINVAL; - } - if (reorder) { - DRM_ERROR("TRILIST_201 used on Savage4 hardware\n"); - return -EINVAL; - } - } - - if (start + n > dmabuf->total / 32) { - DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n", - start, start + n - 1, dmabuf->total / 32); - return -EINVAL; - } - - /* Vertex DMA doesn't work with command DMA at the same time, - * so we use BCI_... to submit commands here. Flush buffered - * faked DMA first. */ - DMA_FLUSH(); - - if (dmabuf->bus_address != dev_priv->state.common.vbaddr) { - BEGIN_BCI(2); - BCI_SET_REGISTERS(SAVAGE_VERTBUFADDR, 1); - BCI_WRITE(dmabuf->bus_address | dev_priv->dma_type); - dev_priv->state.common.vbaddr = dmabuf->bus_address; - } - if (S3_SAVAGE3D_SERIES(dev_priv->chipset) && dev_priv->waiting) { - /* Workaround for what looks like a hardware bug. If a - * WAIT_3D_IDLE was emitted some time before the - * indexed drawing command then the engine will lock - * up. There are two known workarounds: - * WAIT_IDLE_EMPTY or emit at least 63 NOPs. */ - BEGIN_BCI(63); - for (i = 0; i < 63; ++i) - BCI_WRITE(BCI_CMD_WAIT); - dev_priv->waiting = 0; - } - - prim <<= 25; - while (n != 0) { - /* Can emit up to 255 indices (85 triangles) at once. */ - unsigned int count = n > 255 ? 255 : n; - if (reorder) { - /* Need to reorder indices for correct flat - * shading while preserving the clock sense - * for correct culling. Only on Savage3D. */ - int reorder[3] = { -1, -1, -1 }; - reorder[start % 3] = 2; - - BEGIN_BCI((count + 1 + 1) / 2); - BCI_DRAW_INDICES_S3D(count, prim, start + 2); - - for (i = start + 1; i + 1 < start + count; i += 2) - BCI_WRITE((i + reorder[i % 3]) | - ((i + 1 + - reorder[(i + 1) % 3]) << 16)); - if (i < start + count) - BCI_WRITE(i + reorder[i % 3]); - } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { - BEGIN_BCI((count + 1 + 1) / 2); - BCI_DRAW_INDICES_S3D(count, prim, start); - - for (i = start + 1; i + 1 < start + count; i += 2) - BCI_WRITE(i | ((i + 1) << 16)); - if (i < start + count) - BCI_WRITE(i); - } else { - BEGIN_BCI((count + 2 + 1) / 2); - BCI_DRAW_INDICES_S4(count, prim, skip); - - for (i = start; i + 1 < start + count; i += 2) - BCI_WRITE(i | ((i + 1) << 16)); - if (i < start + count) - BCI_WRITE(i); - } - - start += count; - n -= count; - - prim |= BCI_CMD_DRAW_CONT; - } - - return 0; -} - -static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv, - const drm_savage_cmd_header_t *cmd_header, - const uint32_t *vtxbuf, unsigned int vb_size, - unsigned int vb_stride) -{ - unsigned char reorder = 0; - unsigned int prim = cmd_header->prim.prim; - unsigned int skip = cmd_header->prim.skip; - unsigned int n = cmd_header->prim.count; - unsigned int start = cmd_header->prim.start; - unsigned int vtx_size; - unsigned int i; - DMA_LOCALS; - - if (!n) - return 0; - - switch (prim) { - case SAVAGE_PRIM_TRILIST_201: - reorder = 1; - prim = SAVAGE_PRIM_TRILIST; - case SAVAGE_PRIM_TRILIST: - if (n % 3 != 0) { - DRM_ERROR("wrong number of vertices %u in TRILIST\n", - n); - return -EINVAL; - } - break; - case SAVAGE_PRIM_TRISTRIP: - case SAVAGE_PRIM_TRIFAN: - if (n < 3) { - DRM_ERROR - ("wrong number of vertices %u in TRIFAN/STRIP\n", - n); - return -EINVAL; - } - break; - default: - DRM_ERROR("invalid primitive type %u\n", prim); - return -EINVAL; - } - - if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { - if (skip > SAVAGE_SKIP_ALL_S3D) { - DRM_ERROR("invalid skip flags 0x%04x\n", skip); - return -EINVAL; - } - vtx_size = 8; /* full vertex */ - } else { - if (skip > SAVAGE_SKIP_ALL_S4) { - DRM_ERROR("invalid skip flags 0x%04x\n", skip); - return -EINVAL; - } - vtx_size = 10; /* full vertex */ - } - - vtx_size -= (skip & 1) + (skip >> 1 & 1) + - (skip >> 2 & 1) + (skip >> 3 & 1) + (skip >> 4 & 1) + - (skip >> 5 & 1) + (skip >> 6 & 1) + (skip >> 7 & 1); - - if (vtx_size > vb_stride) { - DRM_ERROR("vertex size greater than vb stride (%u > %u)\n", - vtx_size, vb_stride); - return -EINVAL; - } - - if (start + n > vb_size / (vb_stride * 4)) { - DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n", - start, start + n - 1, vb_size / (vb_stride * 4)); - return -EINVAL; - } - - prim <<= 25; - while (n != 0) { - /* Can emit up to 255 vertices (85 triangles) at once. */ - unsigned int count = n > 255 ? 255 : n; - if (reorder) { - /* Need to reorder vertices for correct flat - * shading while preserving the clock sense - * for correct culling. Only on Savage3D. */ - int reorder[3] = { -1, -1, -1 }; - reorder[start % 3] = 2; - - BEGIN_DMA(count * vtx_size + 1); - DMA_DRAW_PRIMITIVE(count, prim, skip); - - for (i = start; i < start + count; ++i) { - unsigned int j = i + reorder[i % 3]; - DMA_COPY(&vtxbuf[vb_stride * j], vtx_size); - } - - DMA_COMMIT(); - } else { - BEGIN_DMA(count * vtx_size + 1); - DMA_DRAW_PRIMITIVE(count, prim, skip); - - if (vb_stride == vtx_size) { - DMA_COPY(&vtxbuf[vb_stride * start], - vtx_size * count); - } else { - for (i = start; i < start + count; ++i) { - DMA_COPY(&vtxbuf[vb_stride * i], - vtx_size); - } - } - - DMA_COMMIT(); - } - - start += count; - n -= count; - - prim |= BCI_CMD_DRAW_CONT; - } - - return 0; -} - -static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv, - const drm_savage_cmd_header_t *cmd_header, - const uint16_t *idx, - const struct drm_buf *dmabuf) -{ - unsigned char reorder = 0; - unsigned int prim = cmd_header->idx.prim; - unsigned int skip = cmd_header->idx.skip; - unsigned int n = cmd_header->idx.count; - unsigned int i; - BCI_LOCALS; - - if (!dmabuf) { - DRM_ERROR("called without dma buffers!\n"); - return -EINVAL; - } - - if (!n) - return 0; - - switch (prim) { - case SAVAGE_PRIM_TRILIST_201: - reorder = 1; - prim = SAVAGE_PRIM_TRILIST; - case SAVAGE_PRIM_TRILIST: - if (n % 3 != 0) { - DRM_ERROR("wrong number of indices %u in TRILIST\n", n); - return -EINVAL; - } - break; - case SAVAGE_PRIM_TRISTRIP: - case SAVAGE_PRIM_TRIFAN: - if (n < 3) { - DRM_ERROR - ("wrong number of indices %u in TRIFAN/STRIP\n", n); - return -EINVAL; - } - break; - default: - DRM_ERROR("invalid primitive type %u\n", prim); - return -EINVAL; - } - - if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { - if (skip != 0) { - DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip); - return -EINVAL; - } - } else { - unsigned int size = 10 - (skip & 1) - (skip >> 1 & 1) - - (skip >> 2 & 1) - (skip >> 3 & 1) - (skip >> 4 & 1) - - (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1); - if (skip > SAVAGE_SKIP_ALL_S4 || size != 8) { - DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip); - return -EINVAL; - } - if (reorder) { - DRM_ERROR("TRILIST_201 used on Savage4 hardware\n"); - return -EINVAL; - } - } - - /* Vertex DMA doesn't work with command DMA at the same time, - * so we use BCI_... to submit commands here. Flush buffered - * faked DMA first. */ - DMA_FLUSH(); - - if (dmabuf->bus_address != dev_priv->state.common.vbaddr) { - BEGIN_BCI(2); - BCI_SET_REGISTERS(SAVAGE_VERTBUFADDR, 1); - BCI_WRITE(dmabuf->bus_address | dev_priv->dma_type); - dev_priv->state.common.vbaddr = dmabuf->bus_address; - } - if (S3_SAVAGE3D_SERIES(dev_priv->chipset) && dev_priv->waiting) { - /* Workaround for what looks like a hardware bug. If a - * WAIT_3D_IDLE was emitted some time before the - * indexed drawing command then the engine will lock - * up. There are two known workarounds: - * WAIT_IDLE_EMPTY or emit at least 63 NOPs. */ - BEGIN_BCI(63); - for (i = 0; i < 63; ++i) - BCI_WRITE(BCI_CMD_WAIT); - dev_priv->waiting = 0; - } - - prim <<= 25; - while (n != 0) { - /* Can emit up to 255 indices (85 triangles) at once. */ - unsigned int count = n > 255 ? 255 : n; - - /* check indices */ - for (i = 0; i < count; ++i) { - if (idx[i] > dmabuf->total / 32) { - DRM_ERROR("idx[%u]=%u out of range (0-%u)\n", - i, idx[i], dmabuf->total / 32); - return -EINVAL; - } - } - - if (reorder) { - /* Need to reorder indices for correct flat - * shading while preserving the clock sense - * for correct culling. Only on Savage3D. */ - int reorder[3] = { 2, -1, -1 }; - - BEGIN_BCI((count + 1 + 1) / 2); - BCI_DRAW_INDICES_S3D(count, prim, idx[2]); - - for (i = 1; i + 1 < count; i += 2) - BCI_WRITE(idx[i + reorder[i % 3]] | - (idx[i + 1 + - reorder[(i + 1) % 3]] << 16)); - if (i < count) - BCI_WRITE(idx[i + reorder[i % 3]]); - } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { - BEGIN_BCI((count + 1 + 1) / 2); - BCI_DRAW_INDICES_S3D(count, prim, idx[0]); - - for (i = 1; i + 1 < count; i += 2) - BCI_WRITE(idx[i] | (idx[i + 1] << 16)); - if (i < count) - BCI_WRITE(idx[i]); - } else { - BEGIN_BCI((count + 2 + 1) / 2); - BCI_DRAW_INDICES_S4(count, prim, skip); - - for (i = 0; i + 1 < count; i += 2) - BCI_WRITE(idx[i] | (idx[i + 1] << 16)); - if (i < count) - BCI_WRITE(idx[i]); - } - - idx += count; - n -= count; - - prim |= BCI_CMD_DRAW_CONT; - } - - return 0; -} - -static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv, - const drm_savage_cmd_header_t *cmd_header, - const uint16_t *idx, - const uint32_t *vtxbuf, - unsigned int vb_size, unsigned int vb_stride) -{ - unsigned char reorder = 0; - unsigned int prim = cmd_header->idx.prim; - unsigned int skip = cmd_header->idx.skip; - unsigned int n = cmd_header->idx.count; - unsigned int vtx_size; - unsigned int i; - DMA_LOCALS; - - if (!n) - return 0; - - switch (prim) { - case SAVAGE_PRIM_TRILIST_201: - reorder = 1; - prim = SAVAGE_PRIM_TRILIST; - case SAVAGE_PRIM_TRILIST: - if (n % 3 != 0) { - DRM_ERROR("wrong number of indices %u in TRILIST\n", n); - return -EINVAL; - } - break; - case SAVAGE_PRIM_TRISTRIP: - case SAVAGE_PRIM_TRIFAN: - if (n < 3) { - DRM_ERROR - ("wrong number of indices %u in TRIFAN/STRIP\n", n); - return -EINVAL; - } - break; - default: - DRM_ERROR("invalid primitive type %u\n", prim); - return -EINVAL; - } - - if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { - if (skip > SAVAGE_SKIP_ALL_S3D) { - DRM_ERROR("invalid skip flags 0x%04x\n", skip); - return -EINVAL; - } - vtx_size = 8; /* full vertex */ - } else { - if (skip > SAVAGE_SKIP_ALL_S4) { - DRM_ERROR("invalid skip flags 0x%04x\n", skip); - return -EINVAL; - } - vtx_size = 10; /* full vertex */ - } - - vtx_size -= (skip & 1) + (skip >> 1 & 1) + - (skip >> 2 & 1) + (skip >> 3 & 1) + (skip >> 4 & 1) + - (skip >> 5 & 1) + (skip >> 6 & 1) + (skip >> 7 & 1); - - if (vtx_size > vb_stride) { - DRM_ERROR("vertex size greater than vb stride (%u > %u)\n", - vtx_size, vb_stride); - return -EINVAL; - } - - prim <<= 25; - while (n != 0) { - /* Can emit up to 255 vertices (85 triangles) at once. */ - unsigned int count = n > 255 ? 255 : n; - - /* Check indices */ - for (i = 0; i < count; ++i) { - if (idx[i] > vb_size / (vb_stride * 4)) { - DRM_ERROR("idx[%u]=%u out of range (0-%u)\n", - i, idx[i], vb_size / (vb_stride * 4)); - return -EINVAL; - } - } - - if (reorder) { - /* Need to reorder vertices for correct flat - * shading while preserving the clock sense - * for correct culling. Only on Savage3D. */ - int reorder[3] = { 2, -1, -1 }; - - BEGIN_DMA(count * vtx_size + 1); - DMA_DRAW_PRIMITIVE(count, prim, skip); - - for (i = 0; i < count; ++i) { - unsigned int j = idx[i + reorder[i % 3]]; - DMA_COPY(&vtxbuf[vb_stride * j], vtx_size); - } - - DMA_COMMIT(); - } else { - BEGIN_DMA(count * vtx_size + 1); - DMA_DRAW_PRIMITIVE(count, prim, skip); - - for (i = 0; i < count; ++i) { - unsigned int j = idx[i]; - DMA_COPY(&vtxbuf[vb_stride * j], vtx_size); - } - - DMA_COMMIT(); - } - - idx += count; - n -= count; - - prim |= BCI_CMD_DRAW_CONT; - } - - return 0; -} - -static int savage_dispatch_clear(drm_savage_private_t *dev_priv, - const drm_savage_cmd_header_t *cmd_header, - const drm_savage_cmd_header_t *data, - unsigned int nbox, - const struct drm_clip_rect *boxes) -{ - unsigned int flags = cmd_header->clear0.flags; - unsigned int clear_cmd; - unsigned int i, nbufs; - DMA_LOCALS; - - if (nbox == 0) - return 0; - - clear_cmd = BCI_CMD_RECT | BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | - BCI_CMD_SEND_COLOR | BCI_CMD_DEST_PBD_NEW; - BCI_CMD_SET_ROP(clear_cmd,0xCC); - - nbufs = ((flags & SAVAGE_FRONT) ? 1 : 0) + - ((flags & SAVAGE_BACK) ? 1 : 0) + ((flags & SAVAGE_DEPTH) ? 1 : 0); - if (nbufs == 0) - return 0; - - if (data->clear1.mask != 0xffffffff) { - /* set mask */ - BEGIN_DMA(2); - DMA_SET_REGISTERS(SAVAGE_BITPLANEWTMASK, 1); - DMA_WRITE(data->clear1.mask); - DMA_COMMIT(); - } - for (i = 0; i < nbox; ++i) { - unsigned int x, y, w, h; - unsigned int buf; - - x = boxes[i].x1, y = boxes[i].y1; - w = boxes[i].x2 - boxes[i].x1; - h = boxes[i].y2 - boxes[i].y1; - BEGIN_DMA(nbufs * 6); - for (buf = SAVAGE_FRONT; buf <= SAVAGE_DEPTH; buf <<= 1) { - if (!(flags & buf)) - continue; - DMA_WRITE(clear_cmd); - switch (buf) { - case SAVAGE_FRONT: - DMA_WRITE(dev_priv->front_offset); - DMA_WRITE(dev_priv->front_bd); - break; - case SAVAGE_BACK: - DMA_WRITE(dev_priv->back_offset); - DMA_WRITE(dev_priv->back_bd); - break; - case SAVAGE_DEPTH: - DMA_WRITE(dev_priv->depth_offset); - DMA_WRITE(dev_priv->depth_bd); - break; - } - DMA_WRITE(data->clear1.value); - DMA_WRITE(BCI_X_Y(x, y)); - DMA_WRITE(BCI_W_H(w, h)); - } - DMA_COMMIT(); - } - if (data->clear1.mask != 0xffffffff) { - /* reset mask */ - BEGIN_DMA(2); - DMA_SET_REGISTERS(SAVAGE_BITPLANEWTMASK, 1); - DMA_WRITE(0xffffffff); - DMA_COMMIT(); - } - - return 0; -} - -static int savage_dispatch_swap(drm_savage_private_t *dev_priv, - unsigned int nbox, const struct drm_clip_rect *boxes) -{ - unsigned int swap_cmd; - unsigned int i; - DMA_LOCALS; - - if (nbox == 0) - return 0; - - swap_cmd = BCI_CMD_RECT | BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | - BCI_CMD_SRC_PBD_COLOR_NEW | BCI_CMD_DEST_GBD; - BCI_CMD_SET_ROP(swap_cmd,0xCC); - - for (i = 0; i < nbox; ++i) { - BEGIN_DMA(6); - DMA_WRITE(swap_cmd); - DMA_WRITE(dev_priv->back_offset); - DMA_WRITE(dev_priv->back_bd); - DMA_WRITE(BCI_X_Y(boxes[i].x1, boxes[i].y1)); - DMA_WRITE(BCI_X_Y(boxes[i].x1, boxes[i].y1)); - DMA_WRITE(BCI_W_H(boxes[i].x2 - boxes[i].x1, - boxes[i].y2 - boxes[i].y1)); - DMA_COMMIT(); - } - - return 0; -} - -static int savage_dispatch_draw(drm_savage_private_t *dev_priv, - const drm_savage_cmd_header_t *start, - const drm_savage_cmd_header_t *end, - const struct drm_buf *dmabuf, - const unsigned int *vtxbuf, - unsigned int vb_size, unsigned int vb_stride, - unsigned int nbox, - const struct drm_clip_rect *boxes) -{ - unsigned int i, j; - int ret; - - for (i = 0; i < nbox; ++i) { - const drm_savage_cmd_header_t *cmdbuf; - dev_priv->emit_clip_rect(dev_priv, &boxes[i]); - - cmdbuf = start; - while (cmdbuf < end) { - drm_savage_cmd_header_t cmd_header; - cmd_header = *cmdbuf; - cmdbuf++; - switch (cmd_header.cmd.cmd) { - case SAVAGE_CMD_DMA_PRIM: - ret = savage_dispatch_dma_prim( - dev_priv, &cmd_header, dmabuf); - break; - case SAVAGE_CMD_VB_PRIM: - ret = savage_dispatch_vb_prim( - dev_priv, &cmd_header, - vtxbuf, vb_size, vb_stride); - break; - case SAVAGE_CMD_DMA_IDX: - j = (cmd_header.idx.count + 3) / 4; - /* j was check in savage_bci_cmdbuf */ - ret = savage_dispatch_dma_idx(dev_priv, - &cmd_header, (const uint16_t *)cmdbuf, - dmabuf); - cmdbuf += j; - break; - case SAVAGE_CMD_VB_IDX: - j = (cmd_header.idx.count + 3) / 4; - /* j was check in savage_bci_cmdbuf */ - ret = savage_dispatch_vb_idx(dev_priv, - &cmd_header, (const uint16_t *)cmdbuf, - (const uint32_t *)vtxbuf, vb_size, - vb_stride); - cmdbuf += j; - break; - default: - /* What's the best return code? EFAULT? */ - DRM_ERROR("IMPLEMENTATION ERROR: " - "non-drawing-command %d\n", - cmd_header.cmd.cmd); - return -EINVAL; - } - - if (ret != 0) - return ret; - } - } - - return 0; -} - -int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ - drm_savage_private_t *dev_priv = dev->dev_private; - struct drm_device_dma *dma = dev->dma; - struct drm_buf *dmabuf; - drm_savage_cmdbuf_t *cmdbuf = data; - drm_savage_cmd_header_t *kcmd_addr = NULL; - drm_savage_cmd_header_t *first_draw_cmd; - unsigned int *kvb_addr = NULL; - struct drm_clip_rect *kbox_addr = NULL; - unsigned int i, j; - int ret = 0; - - DRM_DEBUG("\n"); - - LOCK_TEST_WITH_RETURN(dev, file_priv); - - if (dma && dma->buflist) { - if (cmdbuf->dma_idx > dma->buf_count) { - DRM_ERROR - ("vertex buffer index %u out of range (0-%u)\n", - cmdbuf->dma_idx, dma->buf_count - 1); - return -EINVAL; - } - dmabuf = dma->buflist[cmdbuf->dma_idx]; - } else { - dmabuf = NULL; - } - - /* Copy the user buffers into kernel temporary areas. This hasn't been - * a performance loss compared to VERIFYAREA_READ/ - * COPY_FROM_USER_UNCHECKED when done in other drivers, and is correct - * for locking on FreeBSD. - */ - if (cmdbuf->size) { - kcmd_addr = drm_alloc(cmdbuf->size * 8, DRM_MEM_DRIVER); - if (kcmd_addr == NULL) - return -ENOMEM; - - if (DRM_COPY_FROM_USER(kcmd_addr, cmdbuf->cmd_addr, - cmdbuf->size * 8)) - { - drm_free(kcmd_addr, cmdbuf->size * 8, DRM_MEM_DRIVER); - return -EFAULT; - } - cmdbuf->cmd_addr = kcmd_addr; - } - if (cmdbuf->vb_size) { - kvb_addr = drm_alloc(cmdbuf->vb_size, DRM_MEM_DRIVER); - if (kvb_addr == NULL) { - ret = -ENOMEM; - goto done; - } - - if (DRM_COPY_FROM_USER(kvb_addr, cmdbuf->vb_addr, - cmdbuf->vb_size)) { - ret = -EFAULT; - goto done; - } - cmdbuf->vb_addr = kvb_addr; - } - if (cmdbuf->nbox) { - kbox_addr = drm_alloc(cmdbuf->nbox * - sizeof(struct drm_clip_rect), - DRM_MEM_DRIVER); - if (kbox_addr == NULL) { - ret = -ENOMEM; - goto done; - } - - if (DRM_COPY_FROM_USER(kbox_addr, cmdbuf->box_addr, - cmdbuf->nbox * - sizeof(struct drm_clip_rect))) { - ret = -EFAULT; - goto done; - } - cmdbuf->box_addr = kbox_addr; - } - - /* Make sure writes to DMA buffers are finished before sending - * DMA commands to the graphics hardware. */ - DRM_MEMORYBARRIER(); - - /* Coming from user space. Don't know if the Xserver has - * emitted wait commands. Assuming the worst. */ - dev_priv->waiting = 1; - - i = 0; - first_draw_cmd = NULL; - while (i < cmdbuf->size) { - drm_savage_cmd_header_t cmd_header; - cmd_header = *(drm_savage_cmd_header_t *)cmdbuf->cmd_addr; - cmdbuf->cmd_addr++; - i++; - - /* Group drawing commands with same state to minimize - * iterations over clip rects. */ - j = 0; - switch (cmd_header.cmd.cmd) { - case SAVAGE_CMD_DMA_IDX: - case SAVAGE_CMD_VB_IDX: - j = (cmd_header.idx.count + 3) / 4; - if (i + j > cmdbuf->size) { - DRM_ERROR("indexed drawing command extends " - "beyond end of command buffer\n"); - DMA_FLUSH(); - return -EINVAL; - } - /* fall through */ - case SAVAGE_CMD_DMA_PRIM: - case SAVAGE_CMD_VB_PRIM: - if (!first_draw_cmd) - first_draw_cmd = cmdbuf->cmd_addr - 1; - cmdbuf->cmd_addr += j; - i += j; - break; - default: - if (first_draw_cmd) { - ret = savage_dispatch_draw( - dev_priv, first_draw_cmd, - cmdbuf->cmd_addr - 1, - dmabuf, cmdbuf->vb_addr, - cmdbuf->vb_size, - cmdbuf->vb_stride, - cmdbuf->nbox, cmdbuf->box_addr); - if (ret != 0) - return ret; - first_draw_cmd = NULL; - } - } - if (first_draw_cmd) - continue; - - switch (cmd_header.cmd.cmd) { - case SAVAGE_CMD_STATE: - j = (cmd_header.state.count + 1) / 2; - if (i + j > cmdbuf->size) { - DRM_ERROR("command SAVAGE_CMD_STATE extends " - "beyond end of command buffer\n"); - DMA_FLUSH(); - ret = -EINVAL; - goto done; - } - ret = savage_dispatch_state(dev_priv, &cmd_header, - (const uint32_t *)cmdbuf->cmd_addr); - cmdbuf->cmd_addr += j; - i += j; - break; - case SAVAGE_CMD_CLEAR: - if (i + 1 > cmdbuf->size) { - DRM_ERROR("command SAVAGE_CMD_CLEAR extends " - "beyond end of command buffer\n"); - DMA_FLUSH(); - ret = -EINVAL; - goto done; - } - ret = savage_dispatch_clear(dev_priv, &cmd_header, - cmdbuf->cmd_addr, - cmdbuf->nbox, - cmdbuf->box_addr); - cmdbuf->cmd_addr++; - i++; - break; - case SAVAGE_CMD_SWAP: - ret = savage_dispatch_swap(dev_priv, cmdbuf->nbox, - cmdbuf->box_addr); - break; - default: - DRM_ERROR("invalid command 0x%x\n", - cmd_header.cmd.cmd); - DMA_FLUSH(); - ret = -EINVAL; - goto done; - } - - if (ret != 0) { - DMA_FLUSH(); - goto done; - } - } - - if (first_draw_cmd) { - ret = savage_dispatch_draw( - dev_priv, first_draw_cmd, cmdbuf->cmd_addr, dmabuf, - cmdbuf->vb_addr, cmdbuf->vb_size, cmdbuf->vb_stride, - cmdbuf->nbox, cmdbuf->box_addr); - if (ret != 0) { - DMA_FLUSH(); - goto done; - } - } - - DMA_FLUSH(); - - if (dmabuf && cmdbuf->discard) { - drm_savage_buf_priv_t *buf_priv = dmabuf->dev_private; - uint16_t event; - event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D); - SET_AGE(&buf_priv->age, event, dev_priv->event_wrap); - savage_freelist_put(dev, dmabuf); - } - -done: - /* If we didn't need to allocate them, these'll be NULL */ - drm_free(kcmd_addr, cmdbuf->size * 8, DRM_MEM_DRIVER); - drm_free(kvb_addr, cmdbuf->vb_size, DRM_MEM_DRIVER); - drm_free(kbox_addr, cmdbuf->nbox * sizeof(struct drm_clip_rect), - DRM_MEM_DRIVER); - - return ret; -} diff --git a/shared-core/sis_drm.h b/shared-core/sis_drm.h deleted file mode 100644 index 30f7b382..00000000 --- a/shared-core/sis_drm.h +++ /dev/null @@ -1,67 +0,0 @@ -/* sis_drv.h -- Private header for sis driver -*- linux-c -*- */ -/* - * Copyright 2005 Eric Anholt - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - */ - -#ifndef __SIS_DRM_H__ -#define __SIS_DRM_H__ - -/* SiS specific ioctls */ -#define NOT_USED_0_3 -#define DRM_SIS_FB_ALLOC 0x04 -#define DRM_SIS_FB_FREE 0x05 -#define NOT_USED_6_12 -#define DRM_SIS_AGP_INIT 0x13 -#define DRM_SIS_AGP_ALLOC 0x14 -#define DRM_SIS_AGP_FREE 0x15 -#define DRM_SIS_FB_INIT 0x16 - -#define DRM_IOCTL_SIS_FB_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_FB_ALLOC, drm_sis_mem_t) -#define DRM_IOCTL_SIS_FB_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_FREE, drm_sis_mem_t) -#define DRM_IOCTL_SIS_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_INIT, drm_sis_agp_t) -#define DRM_IOCTL_SIS_AGP_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_ALLOC, drm_sis_mem_t) -#define DRM_IOCTL_SIS_AGP_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_AGP_FREE, drm_sis_mem_t) -#define DRM_IOCTL_SIS_FB_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_INIT, drm_sis_fb_t) -/* -#define DRM_IOCTL_SIS_FLIP DRM_IOW( 0x48, drm_sis_flip_t) -#define DRM_IOCTL_SIS_FLIP_INIT DRM_IO( 0x49) -#define DRM_IOCTL_SIS_FLIP_FINAL DRM_IO( 0x50) -*/ - -typedef struct { - int context; - unsigned int offset; - unsigned int size; - unsigned long free; -} drm_sis_mem_t; - -typedef struct { - unsigned int offset, size; -} drm_sis_agp_t; - -typedef struct { - unsigned int offset, size; -} drm_sis_fb_t; - -#endif /* __SIS_DRM_H__ */ diff --git a/shared-core/sis_drv.h b/shared-core/sis_drv.h deleted file mode 100644 index db532f3c..00000000 --- a/shared-core/sis_drv.h +++ /dev/null @@ -1,90 +0,0 @@ -/* sis_drv.h -- Private header for sis driver -*- linux-c -*- */ -/* - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _SIS_DRV_H_ -#define _SIS_DRV_H_ - -/* General customization: - */ - -#define DRIVER_AUTHOR "SIS, Tungsten Graphics" -#define DRIVER_NAME "sis" -#define DRIVER_DESC "SIS 300/630/540 and XGI V3XE/V5/V8" -#define DRIVER_DATE "20070626" -#define DRIVER_MAJOR 1 -#define DRIVER_MINOR 3 -#define DRIVER_PATCHLEVEL 0 - -enum sis_family { - SIS_OTHER = 0, - SIS_CHIP_315 = 1, -}; - -#if defined(__linux__) -#define SIS_HAVE_CORE_MM -#endif - -#ifdef SIS_HAVE_CORE_MM -#include "drm_sman.h" - -#define SIS_BASE (dev_priv->mmio) -#define SIS_READ(reg) DRM_READ32(SIS_BASE, reg); -#define SIS_WRITE(reg, val) DRM_WRITE32(SIS_BASE, reg, val); - -typedef struct drm_sis_private { - drm_local_map_t *mmio; - unsigned int idle_fault; - struct drm_sman sman; - unsigned int chipset; - int vram_initialized; - int agp_initialized; - unsigned long vram_offset; - unsigned long agp_offset; -} drm_sis_private_t; - -extern int sis_idle(struct drm_device *dev); -extern void sis_reclaim_buffers_locked(struct drm_device *dev, - struct drm_file *file_priv); -extern void sis_lastclose(struct drm_device *dev); - -#else -#include "sis_ds.h" - -typedef struct drm_sis_private { - memHeap_t *AGPHeap; - memHeap_t *FBHeap; -} drm_sis_private_t; - -extern int sis_init_context(struct drm_device * dev, int context); -extern int sis_final_context(struct drm_device * dev, int context); - -#endif - -extern struct drm_ioctl_desc sis_ioctls[]; -extern int sis_max_ioctl; - -#endif diff --git a/shared-core/sis_ds.c b/shared-core/sis_ds.c deleted file mode 100644 index 2e485d48..00000000 --- a/shared-core/sis_ds.c +++ /dev/null @@ -1,299 +0,0 @@ -/* sis_ds.c -- Private header for Direct Rendering Manager -*- linux-c -*- - * Created: Mon Jan 4 10:05:05 1999 by sclin@sis.com.tw - * - * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Sung-Ching Lin - * - */ - -#include "drmP.h" -#include "drm.h" -#include "sis_ds.h" - -/* Set Data Structure, not check repeated value - * temporarily used - */ - -set_t *setInit(void) -{ - int i; - set_t *set; - - set = (set_t *) drm_alloc(sizeof(set_t), DRM_MEM_DRIVER); - if (set != NULL) { - for (i = 0; i < SET_SIZE; i++) { - set->list[i].free_next = i + 1; - set->list[i].alloc_next = -1; - } - set->list[SET_SIZE - 1].free_next = -1; - set->free = 0; - set->alloc = -1; - set->trace = -1; - } - return set; -} - -int setAdd(set_t * set, ITEM_TYPE item) -{ - int free = set->free; - - if (free != -1) { - set->list[free].val = item; - set->free = set->list[free].free_next; - } else { - return 0; - } - - set->list[free].alloc_next = set->alloc; - set->alloc = free; - set->list[free].free_next = -1; - - return 1; -} - -int setDel(set_t * set, ITEM_TYPE item) -{ - int alloc = set->alloc; - int prev = -1; - - while (alloc != -1) { - if (set->list[alloc].val == item) { - if (prev != -1) - set->list[prev].alloc_next = - set->list[alloc].alloc_next; - else - set->alloc = set->list[alloc].alloc_next; - break; - } - prev = alloc; - alloc = set->list[alloc].alloc_next; - } - - if (alloc == -1) - return 0; - - set->list[alloc].free_next = set->free; - set->free = alloc; - set->list[alloc].alloc_next = -1; - - return 1; -} - -/* setFirst -> setAdd -> setNext is wrong */ - -int setFirst(set_t * set, ITEM_TYPE * item) -{ - if (set->alloc == -1) - return 0; - - *item = set->list[set->alloc].val; - set->trace = set->list[set->alloc].alloc_next; - - return 1; -} - -int setNext(set_t * set, ITEM_TYPE * item) -{ - if (set->trace == -1) - return 0; - - *item = set->list[set->trace].val; - set->trace = set->list[set->trace].alloc_next; - - return 1; -} - -int setDestroy(set_t * set) -{ - drm_free(set, sizeof(set_t), DRM_MEM_DRIVER); - - return 1; -} - -/* - * GLX Hardware Device Driver common code - * Copyright (C) 1999 Wittawat Yamwong - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * WITTAWAT YAMWONG, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE - * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#define ISFREE(bptr) ((bptr)->free) - -memHeap_t *mmInit(int ofs, int size) -{ - PMemBlock blocks; - - if (size <= 0) - return NULL; - - blocks = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER); - if (blocks != NULL) { - blocks->ofs = ofs; - blocks->size = size; - blocks->free = 1; - return (memHeap_t *) blocks; - } else - return NULL; -} - -/* Checks if a pointer 'b' is part of the heap 'heap' */ -int mmBlockInHeap(memHeap_t * heap, PMemBlock b) -{ - TMemBlock *p; - - if (heap == NULL || b == NULL) - return 0; - - p = heap; - while (p != NULL && p != b) { - p = p->next; - } - if (p == b) - return 1; - else - return 0; -} - -static TMemBlock *SliceBlock(TMemBlock * p, - int startofs, int size, - int reserved, int alignment) -{ - TMemBlock *newblock; - - /* break left */ - if (startofs > p->ofs) { - newblock = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), - DRM_MEM_DRIVER); - newblock->ofs = startofs; - newblock->size = p->size - (startofs - p->ofs); - newblock->free = 1; - newblock->next = p->next; - p->size -= newblock->size; - p->next = newblock; - p = newblock; - } - - /* break right */ - if (size < p->size) { - newblock = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), - DRM_MEM_DRIVER); - newblock->ofs = startofs + size; - newblock->size = p->size - size; - newblock->free = 1; - newblock->next = p->next; - p->size = size; - p->next = newblock; - } - - /* p = middle block */ - p->align = alignment; - p->free = 0; - p->reserved = reserved; - return p; -} - -PMemBlock mmAllocMem(memHeap_t * heap, int size, int align2, int startSearch) -{ - int mask, startofs, endofs; - TMemBlock *p; - - if (heap == NULL || align2 < 0 || size <= 0) - return NULL; - - mask = (1 << align2) - 1; - startofs = 0; - p = (TMemBlock *) heap; - while (p != NULL) { - if (ISFREE(p)) { - startofs = (p->ofs + mask) & ~mask; - if (startofs < startSearch) { - startofs = startSearch; - } - endofs = startofs + size; - if (endofs <= (p->ofs + p->size)) - break; - } - p = p->next; - } - if (p == NULL) - return NULL; - p = SliceBlock(p, startofs, size, 0, mask + 1); - p->heap = heap; - return p; -} - -static __inline__ int Join2Blocks(TMemBlock * p) -{ - if (p->free && p->next && p->next->free) { - TMemBlock *q = p->next; - p->size += q->size; - p->next = q->next; - drm_free(q, sizeof(TMemBlock), DRM_MEM_DRIVER); - return 1; - } - return 0; -} - -int mmFreeMem(PMemBlock b) -{ - TMemBlock *p, *prev; - - if (b == NULL) - return 0; - if (b->heap == NULL) - return -1; - - p = b->heap; - prev = NULL; - while (p != NULL && p != b) { - prev = p; - p = p->next; - } - if (p == NULL || p->free || p->reserved) - return -1; - - p->free = 1; - Join2Blocks(p); - if (prev) - Join2Blocks(prev); - return 0; -} diff --git a/shared-core/sis_ds.h b/shared-core/sis_ds.h deleted file mode 100644 index 0a3e3c7b..00000000 --- a/shared-core/sis_ds.h +++ /dev/null @@ -1,146 +0,0 @@ -/* sis_ds.h -- Private header for Direct Rendering Manager -*- linux-c -*- - * Created: Mon Jan 4 10:05:05 1999 by sclin@sis.com.tw - */ -/* - * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Sung-Ching Lin - * - */ - -#ifndef __SIS_DS_H__ -#define __SIS_DS_H__ - -/* Set Data Structure */ - -#define SET_SIZE 5000 - -typedef unsigned long ITEM_TYPE; - -typedef struct { - ITEM_TYPE val; - int alloc_next, free_next; -} list_item_t; - -typedef struct { - int alloc; - int free; - int trace; - list_item_t list[SET_SIZE]; -} set_t; - -set_t *setInit(void); -int setAdd(set_t * set, ITEM_TYPE item); -int setDel(set_t * set, ITEM_TYPE item); -int setFirst(set_t * set, ITEM_TYPE * item); -int setNext(set_t * set, ITEM_TYPE * item); -int setDestroy(set_t * set); - -/* - * GLX Hardware Device Driver common code - * Copyright (C) 1999 Wittawat Yamwong - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * WITTAWAT YAMWONG, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE - * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -struct mem_block_t { - struct mem_block_t *next; - struct mem_block_t *heap; - int ofs, size; - int align; - unsigned int free:1; - unsigned int reserved:1; -}; -typedef struct mem_block_t TMemBlock; -typedef struct mem_block_t *PMemBlock; - -/* a heap is just the first block in a chain */ -typedef struct mem_block_t memHeap_t; - -static __inline__ int mmBlockSize(PMemBlock b) -{ - return b->size; -} - -static __inline__ int mmOffset(PMemBlock b) -{ - return b->ofs; -} - -static __inline__ void mmMarkReserved(PMemBlock b) -{ - b->reserved = 1; -} - -/* - * input: total size in bytes - * return: a heap pointer if OK, NULL if error - */ -memHeap_t *mmInit(int ofs, int size); - -/* - * Allocate 'size' bytes with 2^align2 bytes alignment, - * restrict the search to free memory after 'startSearch' - * depth and back buffers should be in different 4mb banks - * to get better page hits if possible - * input: size = size of block - * align2 = 2^align2 bytes alignment - * startSearch = linear offset from start of heap to begin search - * return: pointer to the allocated block, 0 if error - */ -PMemBlock mmAllocMem(memHeap_t * heap, int size, int align2, int startSearch); - -/* - * Returns 1 if the block 'b' is part of the heap 'heap' - */ -int mmBlockInHeap(PMemBlock heap, PMemBlock b); - -/* - * Free block starts at offset - * input: pointer to a block - * return: 0 if OK, -1 if error - */ -int mmFreeMem(PMemBlock b); - -/* For debuging purpose. */ -void mmDumpMemInfo(memHeap_t * mmInit); - -#endif /* __SIS_DS_H__ */ diff --git a/shared-core/sis_mm.c b/shared-core/sis_mm.c deleted file mode 100644 index e11939fa..00000000 --- a/shared-core/sis_mm.c +++ /dev/null @@ -1,386 +0,0 @@ -/* sis_mm.c -- Private header for Direct Rendering Manager -*- linux-c -*- - * Created: Mon Jan 4 10:05:05 1999 by sclin@sis.com.tw - * - * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Sung-Ching Lin - * - */ - -#if defined(__linux__) && defined(CONFIG_FB_SIS) -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) -#include