From 52f9028c84baea81230dc673b756552e8e90aecd Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Thu, 5 Apr 2007 11:21:06 +1000
Subject: Initial import of modesetting for intel driver in DRM

---
 shared-core/i915_dma.c | 135 ++++++++------
 shared-core/i915_drv.h | 474 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 557 insertions(+), 52 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index aed3eea1..a5f1473a 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -31,13 +31,6 @@
 #include "i915_drm.h"
 #include "i915_drv.h"
 
-#define IS_I965G(dev)  (dev->pci_device == 0x2972 || \
-			dev->pci_device == 0x2982 || \
-			dev->pci_device == 0x2992 || \
-			dev->pci_device == 0x29A2 || \
-			dev->pci_device == 0x2A02)
-
-
 /* Really want an OS-independent resettable timer.  Would like to have
  * this loop run for (eg) 3 sec, but have the timer reset every time
  * the head pointer changes, so that EBUSY only happens if the ring
@@ -87,6 +80,7 @@ void i915_kernel_lost_context(drm_device_t * dev)
 
 static int i915_dma_cleanup(drm_device_t * dev)
 {
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	/* Make sure interrupts are disabled here because the uninstall ioctl
 	 * may not have been called from userspace and after dev_private
 	 * is freed, it's too late.
@@ -94,25 +88,16 @@ static int i915_dma_cleanup(drm_device_t * dev)
 	if (dev->irq)
 		drm_irq_uninstall(dev);
 
-	if (dev->dev_private) {
-		drm_i915_private_t *dev_priv =
-		    (drm_i915_private_t *) dev->dev_private;
-
-		if (dev_priv->ring.virtual_start) {
-			drm_core_ioremapfree(&dev_priv->ring.map, dev);
-		}
-
-		if (dev_priv->status_page_dmah) {
-			drm_pci_free(dev, dev_priv->status_page_dmah);
-			/* Need to rewrite hardware status page */
-			I915_WRITE(0x02080, 0x1ffff000);
-		}
-
-		drm_free(dev->dev_private, sizeof(drm_i915_private_t),
-			 DRM_MEM_DRIVER);
-
-		dev->dev_private = NULL;
+	if (dev_priv->status_page_dmah) {
+		drm_pci_free(dev, dev_priv->status_page_dmah);
+		dev_priv->status_page_dmah = NULL;
+		dev_priv->hw_status_page = NULL;
+		dev_priv->dma_status_page = 0;
+		/* Need to rewrite hardware status page */
+		I915_WRITE(0x02080, 0x1ffff000);
 	}
+	
+	dev_priv->sarea_priv = NULL;
 
 	return 0;
 }
@@ -121,8 +106,6 @@ static int i915_initialize(drm_device_t * dev,
 			   drm_i915_private_t * dev_priv,
 			   drm_i915_init_t * init)
 {
-	memset(dev_priv, 0, sizeof(drm_i915_private_t));
-
 	DRM_GETSAREA();
 	if (!dev_priv->sarea) {
 		DRM_ERROR("can not find sarea!\n");
@@ -131,14 +114,6 @@ static int i915_initialize(drm_device_t * dev,
 		return DRM_ERR(EINVAL);
 	}
 
-	dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
-	if (!dev_priv->mmio_map) {
-		dev->dev_private = (void *)dev_priv;
-		i915_dma_cleanup(dev);
-		DRM_ERROR("can not find mmio map!\n");
-		return DRM_ERR(EINVAL);
-	}
-
 	dev_priv->sarea_priv = (drm_i915_sarea_t *)
 	    ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 
@@ -195,7 +170,11 @@ static int i915_initialize(drm_device_t * dev,
 
 	I915_WRITE(0x02080, dev_priv->dma_status_page);
 	DRM_DEBUG("Enabled hardware status page\n");
-	dev->dev_private = (void *)dev_priv;
+
+	/* this probably doesn't belong here - TODO */
+	drm_framebuffer_set_object(dev, dev_priv->sarea_priv->front_handle);
+	drm_set_desired_modes(dev);
+
 	return 0;
 }
 
@@ -237,7 +216,7 @@ static int i915_dma_resume(drm_device_t * dev)
 static int i915_dma_init(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
-	drm_i915_private_t *dev_priv;
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	drm_i915_init_t init;
 	int retcode = 0;
 
@@ -246,10 +225,6 @@ static int i915_dma_init(DRM_IOCTL_ARGS)
 
 	switch (init.func) {
 	case I915_INIT_DMA:
-		dev_priv = drm_alloc(sizeof(drm_i915_private_t),
-				     DRM_MEM_DRIVER);
-		if (dev_priv == NULL)
-			return DRM_ERR(ENOMEM);
 		retcode = i915_initialize(dev, dev_priv, &init);
 		break;
 	case I915_CLEANUP_DMA:
@@ -882,6 +857,18 @@ static int i915_mmio(DRM_IOCTL_ARGS)
 
 int i915_driver_load(drm_device_t *dev, unsigned long flags)
 {
+	drm_i915_private_t *dev_priv;
+	int ret;
+	unsigned long mmiobase, mmiolen;
+
+	dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
+	if (dev_priv == NULL)
+		return DRM_ERR(ENOMEM);
+
+	memset(dev_priv, 0, sizeof(drm_i915_private_t));
+	dev->dev_private = (void *)dev_priv;
+//	dev_priv->flags = flags;
+
 	/* i915 has 4 more counters */
 	dev->counters += 4;
 	dev->types[6] = _DRM_STAT_IRQ;
@@ -889,25 +876,55 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 	dev->types[8] = _DRM_STAT_SECONDARY;
 	dev->types[9] = _DRM_STAT_DMA;
 
+	if (IS_I9XX(dev)) {
+		dev_priv->mmiobase = drm_get_resource_start(dev, 0);
+		dev_priv->mmiolen = drm_get_resource_len(dev, 0);
+	} else if (drm_get_resource_start(dev, 1)) {
+		dev_priv->mmiobase = drm_get_resource_start(dev, 1);
+		dev_priv->mmiolen = drm_get_resource_len(dev, 1);
+	} else {
+		DRM_ERROR("Unable to find MMIO registers\n");
+		return -ENODEV;
+	}
+
+	ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
+			 _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio_map);
+	if (ret != 0) {
+		DRM_ERROR("Cannot add mapping for MMIO registers\n");
+		return ret;
+	}
+ 
+	DRM_DEBUG("dev_priv->mmio map is %08X\n", dev_priv->mmio_map);
+	intel_modeset_init(dev);
+	return 0;
+}
+
+int i915_driver_unload(drm_device_t *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+
+	intel_modeset_cleanup(dev);
+	drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
+
+	dev->dev_private = NULL;
 	return 0;
 }
 
 void i915_driver_lastclose(drm_device_t * dev)
 {
-	if (dev->dev_private) {
-		drm_i915_private_t *dev_priv = dev->dev_private;
-		i915_do_cleanup_pageflip(dev);
-		i915_mem_takedown(&(dev_priv->agp_heap));
-	}
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	
+	i915_mem_takedown(&(dev_priv->agp_heap));
+
 	i915_dma_cleanup(dev);
+
+	dev_priv->mmio_map = NULL;
 }
 
 void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
 {
-	if (dev->dev_private) {
-		drm_i915_private_t *dev_priv = dev->dev_private;
-		i915_mem_release(dev, filp, dev_priv->agp_heap);
-	}
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	i915_mem_release(dev, filp, dev_priv->agp_heap);
 }
 
 drm_ioctl_desc_t i915_ioctls[] = {
@@ -950,8 +967,22 @@ int i915_driver_device_is_agp(drm_device_t * dev)
 
 int i915_driver_firstopen(struct drm_device *dev)
 {
-#ifdef I915_HAVE_BUFFER
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	int ret;
+	DRM_DEBUG("\n");
 	drm_bo_driver_init(dev);
-#endif
+
+	if (!dev_priv->mmio_map) {
+		ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
+				 _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio_map);
+		if (ret != 0) {
+			DRM_ERROR("Cannot add mapping for MMIO registers\n");
+			return ret;
+		}
+	}
+ 
+	DRM_DEBUG("dev_priv->mmio map is %08X\n", dev_priv->mmio_map);
+
 	return 0;
 }
+
diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h
index e8a7be29..f37f5873 100644
--- a/shared-core/i915_drv.h
+++ b/shared-core/i915_drv.h
@@ -92,6 +92,9 @@ typedef struct drm_i915_private {
 	drm_local_map_t *sarea;
 	drm_local_map_t *mmio_map;
 
+	unsigned long mmiobase;
+	unsigned long mmiolen;
+
 	drm_i915_sarea_t *sarea_priv;
 	drm_i915_ring_buffer_t ring;
 
@@ -145,6 +148,8 @@ extern int i915_max_ioctl;
 				/* i915_dma.c */
 extern void i915_kernel_lost_context(drm_device_t * dev);
 extern int i915_driver_load(struct drm_device *, unsigned long flags);
+extern int i915_driver_unload(drm_device_t *dev);
+extern int i915_driver_firstopen(struct drm_device *dev);
 extern void i915_driver_lastclose(drm_device_t * dev);
 extern void i915_driver_preclose(drm_device_t * dev, DRMFILE filp);
 extern int i915_driver_device_is_agp(drm_device_t * dev);
@@ -206,6 +211,12 @@ extern int i915_move(drm_buffer_object_t *bo, int evict,
 
 #endif
 
+
+/* modesetting */
+extern void intel_modeset_init(drm_device_t *dev);
+extern void intel_modeset_cleanup(drm_device_t *dev);
+
+
 #define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, (reg))
 #define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
 #define I915_READ16(reg) 	DRM_READ16(dev_priv->mmio_map, (reg))
@@ -273,6 +284,30 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
 #define I915_VBLANK_INTERRUPT_ENABLE	(1UL<<17)
 #define I915_VBLANK_CLEAR		(1UL<<1)
 
+#define GPIOA			0x5010
+#define GPIOB			0x5014
+#define GPIOC			0x5018
+#define GPIOD			0x501c
+#define GPIOE			0x5020
+#define GPIOF			0x5024
+#define GPIOG			0x5028
+#define GPIOH			0x502c
+# define GPIO_CLOCK_DIR_MASK		(1 << 0)
+# define GPIO_CLOCK_DIR_IN		(0 << 1)
+# define GPIO_CLOCK_DIR_OUT		(1 << 1)
+# define GPIO_CLOCK_VAL_MASK		(1 << 2)
+# define GPIO_CLOCK_VAL_OUT		(1 << 3)
+# define GPIO_CLOCK_VAL_IN		(1 << 4)
+# define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
+# define GPIO_DATA_DIR_MASK		(1 << 8)
+# define GPIO_DATA_DIR_IN		(0 << 9)
+# define GPIO_DATA_DIR_OUT		(1 << 9)
+# define GPIO_DATA_VAL_MASK		(1 << 10)
+# define GPIO_DATA_VAL_OUT		(1 << 11)
+# define GPIO_DATA_VAL_IN		(1 << 12)
+# define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
+
+
 #define SRX_INDEX		0x3c4
 #define SRX_DATA		0x3c5
 #define SR01			1
@@ -281,6 +316,8 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
 #define PPCR			0x61204
 #define PPCR_ON			(1<<0)
 
+#define DVOA			0x61120
+#define DVOA_ON			(1<<31)
 #define DVOB			0x61140
 #define DVOB_ON			(1<<31)
 #define DVOC			0x61160
@@ -363,4 +400,441 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
 
 #define READ_BREADCRUMB(dev_priv)  (((volatile u32*)(dev_priv->hw_status_page))[5])
 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
+
+#define BLC_PWM_CTL		0x61254
+#define BACKLIGHT_MODULATION_FREQ_SHIFT		(17)
+/**
+ * This is the most significant 15 bits of the number of backlight cycles in a
+ * complete cycle of the modulated backlight control.
+ *
+ * The actual value is this field multiplied by two.
+ */
+#define BACKLIGHT_MODULATION_FREQ_MASK		(0x7fff << 17)
+#define BLM_LEGACY_MODE				(1 << 16)
+/**
+ * This is the number of cycles out of the backlight modulation cycle for which
+ * the backlight is on.
+ *
+ * This field must be no greater than the number of cycles in the complete
+ * backlight modulation cycle.
+ */
+#define BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
+#define BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
+
+#define I915_GCFGC			0xf0
+#define I915_LOW_FREQUENCY_ENABLE		(1 << 7)
+#define I915_DISPLAY_CLOCK_190_200_MHZ		(0 << 4)
+#define I915_DISPLAY_CLOCK_333_MHZ		(4 << 4)
+#define I915_DISPLAY_CLOCK_MASK			(7 << 4)
+
+#define I855_HPLLCC			0xc0
+#define I855_CLOCK_CONTROL_MASK			(3 << 0)
+#define I855_CLOCK_133_200			(0 << 0)
+#define I855_CLOCK_100_200			(1 << 0)
+#define I855_CLOCK_100_133			(2 << 0)
+#define I855_CLOCK_166_250			(3 << 0)
+
+/* I830 CRTC registers */
+#define HTOTAL_A	0x60000
+#define HBLANK_A	0x60004
+#define HSYNC_A 	0x60008
+#define VTOTAL_A	0x6000c
+#define VBLANK_A	0x60010
+#define VSYNC_A 	0x60014
+#define PIPEASRC	0x6001c
+#define BCLRPAT_A	0x60020
+#define VSYNCSHIFT_A	0x60028
+
+#define HTOTAL_B	0x61000
+#define HBLANK_B	0x61004
+#define HSYNC_B 	0x61008
+#define VTOTAL_B	0x6100c
+#define VBLANK_B	0x61010
+#define VSYNC_B 	0x61014
+#define PIPEBSRC	0x6101c
+#define BCLRPAT_B	0x61020
+#define VSYNCSHIFT_B	0x61028
+
+#define PP_STATUS	0x61200
+# define PP_ON					(1 << 31)
+/**
+ * Indicates that all dependencies of the panel are on:
+ *
+ * - PLL enabled
+ * - pipe enabled
+ * - LVDS/DVOB/DVOC on
+ */
+# define PP_READY				(1 << 30)
+# define PP_SEQUENCE_NONE			(0 << 28)
+# define PP_SEQUENCE_ON				(1 << 28)
+# define PP_SEQUENCE_OFF			(2 << 28)
+# define PP_SEQUENCE_MASK			0x30000000
+#define PP_CONTROL	0x61204
+# define POWER_TARGET_ON			(1 << 0)
+
+#define LVDSPP_ON       0x61208
+#define LVDSPP_OFF      0x6120c
+#define PP_CYCLE        0x61210
+
+#define PFIT_CONTROL	0x61230
+# define PFIT_ENABLE				(1 << 31)
+# define VERT_INTERP_DISABLE			(0 << 10)
+# define VERT_INTERP_BILINEAR			(1 << 10)
+# define VERT_INTERP_MASK			(3 << 10)
+# define VERT_AUTO_SCALE			(1 << 9)
+# define HORIZ_INTERP_DISABLE			(0 << 6)
+# define HORIZ_INTERP_BILINEAR			(1 << 6)
+# define HORIZ_INTERP_MASK			(3 << 6)
+# define HORIZ_AUTO_SCALE			(1 << 5)
+# define PANEL_8TO6_DITHER_ENABLE		(1 << 3)
+
+#define PFIT_PGM_RATIOS	0x61234
+# define PFIT_VERT_SCALE_MASK			0xfff00000
+# define PFIT_HORIZ_SCALE_MASK			0x0000fff0
+
+#define PFIT_AUTO_RATIOS	0x61238
+
+
+#define DPLL_A		0x06014
+#define DPLL_B		0x06018
+# define DPLL_VCO_ENABLE			(1 << 31)
+# define DPLL_DVO_HIGH_SPEED			(1 << 30)
+# define DPLL_SYNCLOCK_ENABLE			(1 << 29)
+# define DPLL_VGA_MODE_DIS			(1 << 28)
+# define DPLLB_MODE_DAC_SERIAL			(1 << 26) /* i915 */
+# define DPLLB_MODE_LVDS			(2 << 26) /* i915 */
+# define DPLL_MODE_MASK				(3 << 26)
+# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10	(0 << 24) /* i915 */
+# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5		(1 << 24) /* i915 */
+# define DPLLB_LVDS_P2_CLOCK_DIV_14		(0 << 24) /* i915 */
+# define DPLLB_LVDS_P2_CLOCK_DIV_7		(1 << 24) /* i915 */
+# define DPLL_P2_CLOCK_DIV_MASK			0x03000000 /* i915 */
+# define DPLL_FPA01_P1_POST_DIV_MASK		0x00ff0000 /* i915 */
+/**
+ *  The i830 generation, in DAC/serial mode, defines p1 as two plus this
+ * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
+ */
+# define DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
+/**
+ * The i830 generation, in LVDS mode, defines P1 as the bit number set within
+ * this field (only one bit may be set).
+ */
+# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
+# define DPLL_FPA01_P1_POST_DIV_SHIFT		16
+# define PLL_P2_DIVIDE_BY_4			(1 << 23) /* i830, required in DVO non-gang */
+# define PLL_P1_DIVIDE_BY_TWO			(1 << 21) /* i830 */
+# define PLL_REF_INPUT_DREFCLK			(0 << 13)
+# define PLL_REF_INPUT_TVCLKINA			(1 << 13) /* i830 */
+# define PLL_REF_INPUT_TVCLKINBC		(2 << 13) /* SDVO TVCLKIN */
+# define PLLB_REF_INPUT_SPREADSPECTRUMIN	(3 << 13)
+# define PLL_REF_INPUT_MASK			(3 << 13)
+# define PLL_LOAD_PULSE_PHASE_SHIFT		9
+/*
+ * Parallel to Serial Load Pulse phase selection.
+ * Selects the phase for the 10X DPLL clock for the PCIe
+ * digital display port. The range is 4 to 13; 10 or more
+ * is just a flip delay. The default is 6
+ */
+# define PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
+# define DISPLAY_RATE_SELECT_FPA1		(1 << 8)
+
+/**
+ * SDVO multiplier for 945G/GM. Not used on 965.
+ *
+ * \sa DPLL_MD_UDI_MULTIPLIER_MASK
+ */
+# define SDVO_MULTIPLIER_MASK			0x000000ff
+# define SDVO_MULTIPLIER_SHIFT_HIRES		4
+# define SDVO_MULTIPLIER_SHIFT_VGA		0
+
+/** @defgroup DPLL_MD
+ * @{
+ */
+/** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
+#define DPLL_A_MD		0x0601c
+/** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
+#define DPLL_B_MD		0x06020
+/**
+ * UDI pixel divider, controlling how many pixels are stuffed into a packet.
+ *
+ * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
+ */
+# define DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
+# define DPLL_MD_UDI_DIVIDER_SHIFT		24
+/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
+# define DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
+# define DPLL_MD_VGA_UDI_DIVIDER_SHIFT		16
+/**
+ * SDVO/UDI pixel multiplier.
+ *
+ * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
+ * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
+ * modes, the bus rate would be below the limits, so SDVO allows for stuffing
+ * dummy bytes in the datastream at an increased clock rate, with both sides of
+ * the link knowing how many bytes are fill.
+ *
+ * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
+ * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
+ * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
+ * through an SDVO command.
+ *
+ * This register field has values of multiplication factor minus 1, with
+ * a maximum multiplier of 5 for SDVO.
+ */
+# define DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
+# define DPLL_MD_UDI_MULTIPLIER_SHIFT		8
+/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 
+ * This best be set to the default value (3) or the CRT won't work. No,
+ * I don't entirely understand what this does...
+ */
+# define DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
+# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
+/** @} */
+
+#define DPLL_TEST		0x606c
+# define DPLLB_TEST_SDVO_DIV_1			(0 << 22)
+# define DPLLB_TEST_SDVO_DIV_2			(1 << 22)
+# define DPLLB_TEST_SDVO_DIV_4			(2 << 22)
+# define DPLLB_TEST_SDVO_DIV_MASK		(3 << 22)
+# define DPLLB_TEST_N_BYPASS			(1 << 19)
+# define DPLLB_TEST_M_BYPASS			(1 << 18)
+# define DPLLB_INPUT_BUFFER_ENABLE		(1 << 16)
+# define DPLLA_TEST_N_BYPASS			(1 << 3)
+# define DPLLA_TEST_M_BYPASS			(1 << 2)
+# define DPLLA_INPUT_BUFFER_ENABLE		(1 << 0)
+
+#define ADPA			0x61100
+#define ADPA_DAC_ENABLE 	(1<<31)
+#define ADPA_DAC_DISABLE	0
+#define ADPA_PIPE_SELECT_MASK	(1<<30)
+#define ADPA_PIPE_A_SELECT	0
+#define ADPA_PIPE_B_SELECT	(1<<30)
+#define ADPA_USE_VGA_HVPOLARITY (1<<15)
+#define ADPA_SETS_HVPOLARITY	0
+#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
+#define ADPA_VSYNC_CNTL_ENABLE	0
+#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
+#define ADPA_HSYNC_CNTL_ENABLE	0
+#define ADPA_VSYNC_ACTIVE_HIGH	(1<<4)
+#define ADPA_VSYNC_ACTIVE_LOW	0
+#define ADPA_HSYNC_ACTIVE_HIGH	(1<<3)
+#define ADPA_HSYNC_ACTIVE_LOW	0
+
+#define FPA0		0x06040
+#define FPA1		0x06044
+#define FPB0		0x06048
+#define FPB1		0x0604c
+# define FP_N_DIV_MASK				0x003f0000
+# define FP_N_DIV_SHIFT				16
+# define FP_M1_DIV_MASK				0x00003f00
+# define FP_M1_DIV_SHIFT			8
+# define FP_M2_DIV_MASK				0x0000003f
+# define FP_M2_DIV_SHIFT			0
+
+
+#define PORT_HOTPLUG_EN		0x61110
+# define SDVOB_HOTPLUG_INT_EN			(1 << 26)
+# define SDVOC_HOTPLUG_INT_EN			(1 << 25)
+# define TV_HOTPLUG_INT_EN			(1 << 18)
+# define CRT_HOTPLUG_INT_EN			(1 << 9)
+# define CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
+
+#define PORT_HOTPLUG_STAT	0x61114
+# define CRT_HOTPLUG_INT_STATUS			(1 << 11)
+# define TV_HOTPLUG_INT_STATUS			(1 << 10)
+# define CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
+# define CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
+# define CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
+# define CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
+# define SDVOC_HOTPLUG_INT_STATUS		(1 << 7)
+# define SDVOB_HOTPLUG_INT_STATUS		(1 << 6)
+
+#define SDVOB			0x61140
+#define SDVOC			0x61160
+#define SDVO_ENABLE				(1 << 31)
+#define SDVO_PIPE_B_SELECT			(1 << 30)
+#define SDVO_STALL_SELECT			(1 << 29)
+#define SDVO_INTERRUPT_ENABLE			(1 << 26)
+/**
+ * 915G/GM SDVO pixel multiplier.
+ *
+ * Programmed value is multiplier - 1, up to 5x.
+ *
+ * \sa DPLL_MD_UDI_MULTIPLIER_MASK
+ */
+#define SDVO_PORT_MULTIPLY_MASK			(7 << 23)
+#define SDVO_PORT_MULTIPLY_SHIFT		23
+#define SDVO_PHASE_SELECT_MASK			(15 << 19)
+#define SDVO_PHASE_SELECT_DEFAULT		(6 << 19)
+#define SDVO_CLOCK_OUTPUT_INVERT		(1 << 18)
+#define SDVOC_GANG_MODE				(1 << 16)
+#define SDVO_BORDER_ENABLE			(1 << 7)
+#define SDVOB_PCIE_CONCURRENCY			(1 << 3)
+#define SDVO_DETECTED				(1 << 2)
+/* Bits to be preserved when writing */
+#define SDVOB_PRESERVE_MASK			((1 << 17) | (1 << 16) | (1 << 14))
+#define SDVOC_PRESERVE_MASK			(1 << 17)
+
+/** @defgroup LVDS
+ * @{
+ */
+/**
+ * This register controls the LVDS output enable, pipe selection, and data
+ * format selection.
+ *
+ * All of the clock/data pairs are force powered down by power sequencing.
+ */
+#define LVDS			0x61180
+/**
+ * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
+ * the DPLL semantics change when the LVDS is assigned to that pipe.
+ */
+# define LVDS_PORT_EN			(1 << 31)
+/** Selects pipe B for LVDS data.  Must be set on pre-965. */
+# define LVDS_PIPEB_SELECT		(1 << 30)
+
+/**
+ * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
+ * pixel.
+ */
+# define LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
+# define LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
+# define LVDS_A0A2_CLKA_POWER_UP	(3 << 8)
+/**
+ * Controls the A3 data pair, which contains the additional LSBs for 24 bit
+ * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
+ * on.
+ */
+# define LVDS_A3_POWER_MASK		(3 << 6)
+# define LVDS_A3_POWER_DOWN		(0 << 6)
+# define LVDS_A3_POWER_UP		(3 << 6)
+/**
+ * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
+ * is set.
+ */
+# define LVDS_CLKB_POWER_MASK		(3 << 4)
+# define LVDS_CLKB_POWER_DOWN		(0 << 4)
+# define LVDS_CLKB_POWER_UP		(3 << 4)
+
+/**
+ * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
+ * setting for whether we are in dual-channel mode.  The B3 pair will
+ * additionally only be powered up when LVDS_A3_POWER_UP is set.
+ */
+# define LVDS_B0B3_POWER_MASK		(3 << 2)
+# define LVDS_B0B3_POWER_DOWN		(0 << 2)
+# define LVDS_B0B3_POWER_UP		(3 << 2)
+
+#define PIPEACONF 0x70008
+#define PIPEACONF_ENABLE	(1<<31)
+#define PIPEACONF_DISABLE	0
+#define PIPEACONF_DOUBLE_WIDE	(1<<30)
+#define I965_PIPECONF_ACTIVE	(1<<30)
+#define PIPEACONF_SINGLE_WIDE	0
+#define PIPEACONF_PIPE_UNLOCKED 0
+#define PIPEACONF_PIPE_LOCKED	(1<<25)
+#define PIPEACONF_PALETTE	0
+#define PIPEACONF_GAMMA 	(1<<24)
+#define PIPECONF_FORCE_BORDER	(1<<25)
+#define PIPECONF_PROGRESSIVE	(0 << 21)
+#define PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
+#define PIPECONF_INTERLACE_FIELD_0_ONLY		(7 << 21)
+
+#define PIPEBCONF 0x71008
+#define PIPEBCONF_ENABLE	(1<<31)
+#define PIPEBCONF_DISABLE	0
+#define PIPEBCONF_DOUBLE_WIDE	(1<<30)
+#define PIPEBCONF_DISABLE	0
+#define PIPEBCONF_GAMMA 	(1<<24)
+#define PIPEBCONF_PALETTE	0
+
+#define PIPEBGCMAXRED		0x71010
+#define PIPEBGCMAXGREEN		0x71014
+#define PIPEBGCMAXBLUE		0x71018
+#define PIPEBSTAT		0x71024
+#define PIPEBFRAMEHIGH		0x71040
+#define PIPEBFRAMEPIXEL		0x71044
+
+#define DSPACNTR		0x70180
+#define DSPBCNTR		0x71180
+#define DISPLAY_PLANE_ENABLE 			(1<<31)
+#define DISPLAY_PLANE_DISABLE			0
+#define DISPPLANE_GAMMA_ENABLE			(1<<30)
+#define DISPPLANE_GAMMA_DISABLE			0
+#define DISPPLANE_PIXFORMAT_MASK		(0xf<<26)
+#define DISPPLANE_8BPP				(0x2<<26)
+#define DISPPLANE_15_16BPP			(0x4<<26)
+#define DISPPLANE_16BPP				(0x5<<26)
+#define DISPPLANE_32BPP_NO_ALPHA 		(0x6<<26)
+#define DISPPLANE_32BPP				(0x7<<26)
+#define DISPPLANE_STEREO_ENABLE			(1<<25)
+#define DISPPLANE_STEREO_DISABLE		0
+#define DISPPLANE_SEL_PIPE_MASK			(1<<24)
+#define DISPPLANE_SEL_PIPE_A			0
+#define DISPPLANE_SEL_PIPE_B			(1<<24)
+#define DISPPLANE_SRC_KEY_ENABLE		(1<<22)
+#define DISPPLANE_SRC_KEY_DISABLE		0
+#define DISPPLANE_LINE_DOUBLE			(1<<20)
+#define DISPPLANE_NO_LINE_DOUBLE		0
+#define DISPPLANE_STEREO_POLARITY_FIRST		0
+#define DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
+/* plane B only */
+#define DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
+#define DISPPLANE_ALPHA_TRANS_DISABLE		0
+#define DISPPLANE_SPRITE_ABOVE_DISPLAYA		0
+#define DISPPLANE_SPRITE_ABOVE_OVERLAY		(1)
+
+#define DSPABASE		0x70184
+#define DSPASTRIDE		0x70188
+
+#define DSPBBASE		0x71184
+#define DSPBADDR		DSPBBASE
+#define DSPBSTRIDE		0x71188
+
+#define DSPAKEYVAL		0x70194
+#define DSPAKEYMASK		0x70198
+
+#define DSPAPOS			0x7018C /* reserved */
+#define DSPASIZE		0x70190
+#define DSPBPOS			0x7118C
+#define DSPBSIZE		0x71190
+
+#define DSPASURF		0x7019C
+#define DSPATILEOFF		0x701A4
+
+#define DSPBSURF		0x7119C
+#define DSPBTILEOFF		0x711A4
+
+#define VGACNTRL		0x71400
+# define VGA_DISP_DISABLE			(1 << 31)
+# define VGA_2X_MODE				(1 << 30)
+# define VGA_PIPE_B_SELECT			(1 << 29)
+
+/*
+ * Palette registers
+ */
+#define PALETTE_A		0x0a000
+#define PALETTE_B		0x0a800
+
+#define IS_I830(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82830_CGC)
+#define IS_845G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82845G_IG)
+#define IS_I85X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG)
+#define IS_I855(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG)
+#define IS_I865G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82865_IG)
+
+#define IS_I915G(pI810) (dev->pci_device == PCI_DEVICE_ID_INTEL_82915G_IG)/* || dev->pci_device == PCI_DEVICE_ID_INTELPCI_CHIP_E7221_G)*/
+#define IS_I915GM(pI810) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82915GM_IG)
+#define IS_I945G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945G_IG)
+#define IS_I945GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945GM_IG)
+
+#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
+		       (dev)->pci_device == 0x2982 || \
+		       (dev)->pci_device == 0x2992 || \
+		       (dev)->pci_device == 0x29A2)
+
+
+#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810))
+
+#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810))
+
 #endif
-- 
cgit v1.2.3


From 5bffbd6e275efffbb649c20c528a11412ccf99cd Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Thu, 5 Apr 2007 13:34:50 +1000
Subject: initial userspace interface to get modes

---
 shared-core/drm.h | 72 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

(limited to 'shared-core')

diff --git a/shared-core/drm.h b/shared-core/drm.h
index 3c59cd40..33194dcc 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -888,6 +888,74 @@ typedef union drm_mm_init_arg{
 	} rep;
 } drm_mm_init_arg_t;
 
+/*
+ * Drm mode setting
+ */
+
+struct drm_mode_modeinfo {
+
+	unsigned int id;
+
+	unsigned int clock;
+	unsigned short hdisplay, hsync_start, hsync_end, htotal, hskew;
+	unsigned short vdisplay, vsync_start, vsync_end, vtotal, vscan;
+
+	unsigned int flags;
+//	int count_flag;
+//	unsigned int __user *modeFlags;
+};
+
+struct drm_mode_card_res {
+
+	unsigned int fb_id;
+
+	int count_crtcs;
+	int count_outputs;
+	int count_modes;
+        struct drm_mode_modeinfo __user *modes;
+
+};
+
+struct drm_mode_crtc {
+	unsigned int crtc_id; /**< Id */
+	unsigned int buffer_id; /**< Id of framebuffer */
+
+	int x, y; /**< Position on the frameuffer */
+	unsigned int width, height;
+	unsigned int mode; /**< Current mode used */
+
+	int count_outputs;
+	unsigned int outputs; /**< Outputs that are connected */
+
+	int count_possibles;
+	unsigned int possibles; /**< Outputs that can be connected */
+
+	unsigned int __user *set_outputs; /**< Outputs to be connected */
+
+	int gamma_size;
+
+};
+
+struct drm_mode_get_output {
+
+	unsigned int output; /**< Id */
+	unsigned int crtc; /**< Id of crtc */
+
+	unsigned int connection;
+	unsigned int width, height; /**< HxW in millimeters */
+	unsigned int subpixel;
+
+	int count_crtcs;
+	unsigned int crtcs; /**< possible crtc to connect to */
+
+	int count_clones;
+	unsigned int clones; /**< list of clones */
+
+	int count_modes;
+	unsigned int __user *modes; /**< list of modes it supports */
+
+};
+
 /**
  * \name Ioctls Definitions
  */
@@ -959,6 +1027,10 @@ typedef union drm_mm_init_arg{
 
 #define DRM_IOCTL_UPDATE_DRAW           DRM_IOW(0x3f, drm_update_draw_t)
 
+#define DRM_IOCTL_MODE_GETRESOURCES     DRM_IOWR(0xA0, struct drm_mode_card_res)
+#define DRM_IOCTL_MODE_GETCRTC          DRM_IOWR(0xA1, drm_mode_crtc_t)
+#define DRM_IOCTL_MODE_GETOUTPUT        DRM_IOWR(0xA2, drm_mode_get_output_t)
+
 /*@}*/
 
 /**
-- 
cgit v1.2.3


From 7bb112fecadc6fe42e5828b861600691071ccd91 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Thu, 5 Apr 2007 17:06:42 +1000
Subject: checkpoint commit: added getresources, crtc and output

This adds the user interfaces from Jakob and hooks them up for 3 ioctls
GetResources, GetCrtc and GetOutput.

I've made the ids for everything fbs, crtcs, outputs and modes go via idr as
per krh's suggestion on irc as it make the code nice and consistent.
---
 shared-core/drm.h | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/drm.h b/shared-core/drm.h
index 33194dcc..1af0be38 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -892,6 +892,8 @@ typedef union drm_mm_init_arg{
  * Drm mode setting
  */
 
+#define DRM_DISPLAY_MODE_LEN 32
+
 struct drm_mode_modeinfo {
 
 	unsigned int id;
@@ -901,8 +903,8 @@ struct drm_mode_modeinfo {
 	unsigned short vdisplay, vsync_start, vsync_end, vtotal, vscan;
 
 	unsigned int flags;
-//	int count_flag;
-//	unsigned int __user *modeFlags;
+
+	char name[DRM_DISPLAY_MODE_LEN];
 };
 
 struct drm_mode_card_res {
@@ -910,7 +912,11 @@ struct drm_mode_card_res {
 	unsigned int fb_id;
 
 	int count_crtcs;
+	unsigned int __user *crtc_id;
+
 	int count_outputs;
+	unsigned int __user *output_id;
+
 	int count_modes;
         struct drm_mode_modeinfo __user *modes;
 
@@ -918,10 +924,10 @@ struct drm_mode_card_res {
 
 struct drm_mode_crtc {
 	unsigned int crtc_id; /**< Id */
-	unsigned int buffer_id; /**< Id of framebuffer */
+	unsigned int fb_id; /**< Id of framebuffer */
 
 	int x, y; /**< Position on the frameuffer */
-	unsigned int width, height;
+
 	unsigned int mode; /**< Current mode used */
 
 	int count_outputs;
@@ -942,7 +948,7 @@ struct drm_mode_get_output {
 	unsigned int crtc; /**< Id of crtc */
 
 	unsigned int connection;
-	unsigned int width, height; /**< HxW in millimeters */
+	unsigned int mm_width, mm_height; /**< HxW in millimeters */
 	unsigned int subpixel;
 
 	int count_crtcs;
@@ -1028,8 +1034,8 @@ struct drm_mode_get_output {
 #define DRM_IOCTL_UPDATE_DRAW           DRM_IOW(0x3f, drm_update_draw_t)
 
 #define DRM_IOCTL_MODE_GETRESOURCES     DRM_IOWR(0xA0, struct drm_mode_card_res)
-#define DRM_IOCTL_MODE_GETCRTC          DRM_IOWR(0xA1, drm_mode_crtc_t)
-#define DRM_IOCTL_MODE_GETOUTPUT        DRM_IOWR(0xA2, drm_mode_get_output_t)
+#define DRM_IOCTL_MODE_GETCRTC          DRM_IOWR(0xA1, struct drm_mode_crtc)
+#define DRM_IOCTL_MODE_GETOUTPUT        DRM_IOWR(0xA2, struct drm_mode_get_output)
 
 /*@}*/
 
-- 
cgit v1.2.3


From b4094864f188a1346cc3b51bcb457beeacefbf82 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Thu, 5 Apr 2007 18:01:02 +1000
Subject: checkpoint commit: implement SetCrtc so modes can in theory be set
 from user

This hooks up the userspace mode set it "seems" to work.
---
 shared-core/drm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'shared-core')

diff --git a/shared-core/drm.h b/shared-core/drm.h
index 1af0be38..49bc41bc 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -1036,7 +1036,7 @@ struct drm_mode_get_output {
 #define DRM_IOCTL_MODE_GETRESOURCES     DRM_IOWR(0xA0, struct drm_mode_card_res)
 #define DRM_IOCTL_MODE_GETCRTC          DRM_IOWR(0xA1, struct drm_mode_crtc)
 #define DRM_IOCTL_MODE_GETOUTPUT        DRM_IOWR(0xA2, struct drm_mode_get_output)
-
+#define DRM_IOCTL_MODE_SETCRTC          DRM_IOWR(0xA3, struct drm_mode_crtc)
 /*@}*/
 
 /**
-- 
cgit v1.2.3


From b50bda002b824efb24e18e8d514ff0ca763c15b9 Mon Sep 17 00:00:00 2001
From: Jakob Bornecrantz <wallbraker@gmail.com>
Date: Tue, 10 Apr 2007 18:44:47 +1000
Subject: add addfb/rmfb ioctls

Originally from Jakob, cleaned up by airlied.
---
 shared-core/drm.h      | 10 ++++++++++
 shared-core/i915_dma.c |  2 --
 2 files changed, 10 insertions(+), 2 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/drm.h b/shared-core/drm.h
index 49bc41bc..8329609f 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -962,6 +962,14 @@ struct drm_mode_get_output {
 
 };
 
+struct drm_mode_fb_cmd {
+        unsigned int buffer_id;
+        unsigned int width, height;
+        unsigned int pitch;
+        unsigned int bpp;
+        unsigned int handle;
+};
+
 /**
  * \name Ioctls Definitions
  */
@@ -1037,6 +1045,8 @@ struct drm_mode_get_output {
 #define DRM_IOCTL_MODE_GETCRTC          DRM_IOWR(0xA1, struct drm_mode_crtc)
 #define DRM_IOCTL_MODE_GETOUTPUT        DRM_IOWR(0xA2, struct drm_mode_get_output)
 #define DRM_IOCTL_MODE_SETCRTC          DRM_IOWR(0xA3, struct drm_mode_crtc)
+#define DRM_IOCTL_MODE_ADDFB            DRM_IOWR(0xA4, struct drm_mode_fb_cmd)
+#define DRM_IOCTL_MODE_RMFB             DRM_IOWR(0xA5, unsigned int)
 /*@}*/
 
 /**
diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index a5f1473a..811e4bb9 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -171,8 +171,6 @@ static int i915_initialize(drm_device_t * dev,
 	I915_WRITE(0x02080, dev_priv->dma_status_page);
 	DRM_DEBUG("Enabled hardware status page\n");
 
-	/* this probably doesn't belong here - TODO */
-	drm_framebuffer_set_object(dev, dev_priv->sarea_priv->front_handle);
 	drm_set_desired_modes(dev);
 
 	return 0;
-- 
cgit v1.2.3


From 65f465ed5ad3caf773658bb2832785c963b987f6 Mon Sep 17 00:00:00 2001
From: David Airlie <airlied@asimov.stargames.com.au>
Date: Tue, 10 Apr 2007 14:49:49 +1000
Subject: fixup numerous issues with adding framebuffer support

This still isn't perfect but it fixes a few oopses and cleans up
some of the tabs and bugs in the original fb limit code
---
 shared-core/i915_dma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index 811e4bb9..2c14cb5d 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -171,7 +171,7 @@ static int i915_initialize(drm_device_t * dev,
 	I915_WRITE(0x02080, dev_priv->dma_status_page);
 	DRM_DEBUG("Enabled hardware status page\n");
 
-	drm_set_desired_modes(dev);
+//drm_set_desired_modes(dev);
 
 	return 0;
 }
-- 
cgit v1.2.3


From 40bd6dcd86d554ca426deccd4fbada693c4be8a6 Mon Sep 17 00:00:00 2001
From: David Airlie <airlied@asimov.stargames.com.au>
Date: Tue, 10 Apr 2007 15:20:50 +1000
Subject: set the base address of the CRTC correctly

---
 shared-core/i915_dma.c | 4 +++-
 shared-core/i915_drv.h | 1 +
 2 files changed, 4 insertions(+), 1 deletion(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index 2c14cb5d..c2a6d863 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -877,11 +877,13 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 	if (IS_I9XX(dev)) {
 		dev_priv->mmiobase = drm_get_resource_start(dev, 0);
 		dev_priv->mmiolen = drm_get_resource_len(dev, 0);
+		dev_priv->baseaddr = drm_get_resource_start(dev, 2) & 0xff000000;
 	} else if (drm_get_resource_start(dev, 1)) {
 		dev_priv->mmiobase = drm_get_resource_start(dev, 1);
 		dev_priv->mmiolen = drm_get_resource_len(dev, 1);
+		dev_priv->baseaddr = drm_get_resource_start(dev, 0) & 0xff000000;
 	} else {
-		DRM_ERROR("Unable to find MMIO registers\n");
+		DRM_ERROR("Unable to find MMIO registers or FB\n");
 		return -ENODEV;
 	}
 
diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h
index f37f5873..517d0bf6 100644
--- a/shared-core/i915_drv.h
+++ b/shared-core/i915_drv.h
@@ -92,6 +92,7 @@ typedef struct drm_i915_private {
 	drm_local_map_t *sarea;
 	drm_local_map_t *mmio_map;
 
+	unsigned long baseaddr;
 	unsigned long mmiobase;
 	unsigned long mmiolen;
 
-- 
cgit v1.2.3


From 1e39dc43230ba1827eedc29ab422464281ec3e1b Mon Sep 17 00:00:00 2001
From: David Airlie <airlied@asimov.stargames.com.au>
Date: Tue, 10 Apr 2007 16:25:31 +1000
Subject: export output name to userspace

---
 shared-core/drm.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'shared-core')

diff --git a/shared-core/drm.h b/shared-core/drm.h
index 8329609f..f1afc049 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -891,7 +891,7 @@ typedef union drm_mm_init_arg{
 /*
  * Drm mode setting
  */
-
+#define DRM_OUTPUT_NAME_LEN 32
 #define DRM_DISPLAY_MODE_LEN 32
 
 struct drm_mode_modeinfo {
@@ -946,6 +946,7 @@ struct drm_mode_get_output {
 
 	unsigned int output; /**< Id */
 	unsigned int crtc; /**< Id of crtc */
+	unsigned char name[DRM_OUTPUT_NAME_LEN];
 
 	unsigned int connection;
 	unsigned int mm_width, mm_height; /**< HxW in millimeters */
-- 
cgit v1.2.3


From 5130918e2531b9a8f6f6b65cdfce81f4f0904329 Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@hobbes.virtuousgeek.org>
Date: Tue, 10 Apr 2007 09:51:17 -0700
Subject: Add save/restore state for LVDS code, along with a few other LVDS
 related items to i915 private structure.

---
 shared-core/i915_drv.h | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

(limited to 'shared-core')

diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h
index f37f5873..6e81f6f8 100644
--- a/shared-core/i915_drv.h
+++ b/shared-core/i915_drv.h
@@ -133,6 +133,67 @@ typedef struct drm_i915_private {
 	spinlock_t swaps_lock;
 	drm_i915_vbl_swap_t vbl_swaps;
 	unsigned int swaps_pending;
+
+	/* LVDS info */
+	int backlight_duty_cycle;  /* restore backlight to this value */
+	bool panel_wants_dither;
+	struct drm_display_mode *panel_fixed_mode;
+
+	/* Register state */
+	u32 saveDSPACNTR;
+	u32 saveDSPBCNTR;
+	u32 savePIPEACONF;
+	u32 savePIPEBCONF;
+	u32 savePIPEASRC;
+	u32 savePIPEBSRC;
+	u32 saveFPA0;
+	u32 saveFPA1;
+	u32 saveDPLL_A;
+	u32 saveDPLL_A_MD;
+	u32 saveHTOTAL_A;
+	u32 saveHBLANK_A;
+	u32 saveHSYNC_A;
+	u32 saveVTOTAL_A;
+	u32 saveVBLANK_A;
+	u32 saveVSYNC_A;
+	u32 saveDSPASTRIDE;
+	u32 saveDSPASIZE;
+	u32 saveDSPAPOS;
+	u32 saveDSPABASE;
+	u32 saveDSPASURF;
+	u32 saveFPB0;
+	u32 saveFPB1;
+	u32 saveDPLL_B;
+	u32 saveDPLL_B_MD;
+	u32 saveHTOTAL_B;
+	u32 saveHBLANK_B;
+	u32 saveHSYNC_B;
+	u32 saveVTOTAL_B;
+	u32 saveVBLANK_B;
+	u32 saveVSYNC_B;
+	u32 saveDSPBSTRIDE;
+	u32 saveDSPBSIZE;
+	u32 saveDSPBPOS;
+	u32 saveDSPBBASE;
+	u32 saveDSPBSURF;
+	u32 saveVCLK_DIVISOR_VGA0;
+	u32 saveVCLK_DIVISOR_VGA1;
+	u32 saveVCLK_POST_DIV;
+	u32 saveVGACNTRL;
+	u32 saveADPA;
+	u32 saveLVDS;
+	u32 saveDVOA;
+	u32 saveDVOB;
+	u32 saveDVOC;
+	u32 savePP_ON;
+	u32 savePP_OFF;
+	u32 savePP_CONTROL;
+	u32 savePP_CYCLE;
+	u32 savePFIT_CONTROL;
+	u32 savePaletteA[256];
+	u32 savePaletteB[256];
+	u32 saveSWF[17];
+	u32 saveBLC_PWM_CTL;
 } drm_i915_private_t;
 
 enum intel_chip_family {
@@ -478,6 +539,8 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
 
 #define PFIT_CONTROL	0x61230
 # define PFIT_ENABLE				(1 << 31)
+# define PFIT_PIPE_MASK				(3 << 29)
+# define PFIT_PIPE_SHIFT			29
 # define VERT_INTERP_DISABLE			(0 << 10)
 # define VERT_INTERP_BILINEAR			(1 << 10)
 # define VERT_INTERP_MASK			(3 << 10)
-- 
cgit v1.2.3


From b59285d738b1a832b12d9258bd6f1db8f7e61f08 Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@hobbes.virtuousgeek.org>
Date: Tue, 10 Apr 2007 10:31:10 -0700
Subject: Move i915 init code to new file, i915_init.c, and create a new high
 level init routine that runs at driver load time.

---
 shared-core/i915_dma.c  |  76 +----------------------
 shared-core/i915_init.c | 157 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 159 insertions(+), 74 deletions(-)
 create mode 100644 shared-core/i915_init.c

(limited to 'shared-core')

diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index a5f1473a..0ba3048a 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -78,7 +78,7 @@ void i915_kernel_lost_context(drm_device_t * dev)
 		dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 }
 
-static int i915_dma_cleanup(drm_device_t * dev)
+int i915_dma_cleanup(drm_device_t * dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	/* Make sure interrupts are disabled here because the uninstall ioctl
@@ -855,78 +855,6 @@ static int i915_mmio(DRM_IOCTL_ARGS)
 	return 0;
 }
 
-int i915_driver_load(drm_device_t *dev, unsigned long flags)
-{
-	drm_i915_private_t *dev_priv;
-	int ret;
-	unsigned long mmiobase, mmiolen;
-
-	dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
-	if (dev_priv == NULL)
-		return DRM_ERR(ENOMEM);
-
-	memset(dev_priv, 0, sizeof(drm_i915_private_t));
-	dev->dev_private = (void *)dev_priv;
-//	dev_priv->flags = flags;
-
-	/* i915 has 4 more counters */
-	dev->counters += 4;
-	dev->types[6] = _DRM_STAT_IRQ;
-	dev->types[7] = _DRM_STAT_PRIMARY;
-	dev->types[8] = _DRM_STAT_SECONDARY;
-	dev->types[9] = _DRM_STAT_DMA;
-
-	if (IS_I9XX(dev)) {
-		dev_priv->mmiobase = drm_get_resource_start(dev, 0);
-		dev_priv->mmiolen = drm_get_resource_len(dev, 0);
-	} else if (drm_get_resource_start(dev, 1)) {
-		dev_priv->mmiobase = drm_get_resource_start(dev, 1);
-		dev_priv->mmiolen = drm_get_resource_len(dev, 1);
-	} else {
-		DRM_ERROR("Unable to find MMIO registers\n");
-		return -ENODEV;
-	}
-
-	ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
-			 _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio_map);
-	if (ret != 0) {
-		DRM_ERROR("Cannot add mapping for MMIO registers\n");
-		return ret;
-	}
- 
-	DRM_DEBUG("dev_priv->mmio map is %08X\n", dev_priv->mmio_map);
-	intel_modeset_init(dev);
-	return 0;
-}
-
-int i915_driver_unload(drm_device_t *dev)
-{
-	drm_i915_private_t *dev_priv = dev->dev_private;
-
-	intel_modeset_cleanup(dev);
-	drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
-
-	dev->dev_private = NULL;
-	return 0;
-}
-
-void i915_driver_lastclose(drm_device_t * dev)
-{
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	
-	i915_mem_takedown(&(dev_priv->agp_heap));
-
-	i915_dma_cleanup(dev);
-
-	dev_priv->mmio_map = NULL;
-}
-
-void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
-{
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	i915_mem_release(dev, filp, dev_priv->agp_heap);
-}
-
 drm_ioctl_desc_t i915_ioctls[] = {
 	[DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 	[DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH},
@@ -981,7 +909,7 @@ int i915_driver_firstopen(struct drm_device *dev)
 		}
 	}
  
-	DRM_DEBUG("dev_priv->mmio map is %08X\n", dev_priv->mmio_map);
+	DRM_DEBUG("dev_priv->mmio map is %p\n", dev_priv->mmio_map);
 
 	return 0;
 }
diff --git a/shared-core/i915_init.c b/shared-core/i915_init.c
new file mode 100644
index 00000000..e03ed429
--- /dev/null
+++ b/shared-core/i915_init.c
@@ -0,0 +1,157 @@
+#include "drmP.h"
+#include "drm.h"
+#include "drm_sarea.h"
+#include "i915_drm.h"
+#include "i915_drv.h"
+
+int i915_driver_load(drm_device_t *dev, unsigned long flags)
+{
+	drm_i915_private_t *dev_priv;
+	drm_i915_init_t init;
+	int ret;
+
+	dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
+	if (dev_priv == NULL)
+		return DRM_ERR(ENOMEM);
+
+	memset(dev_priv, 0, sizeof(drm_i915_private_t));
+	dev->dev_private = (void *)dev_priv;
+//	dev_priv->flags = flags;
+
+	/* i915 has 4 more counters */
+	dev->counters += 4;
+	dev->types[6] = _DRM_STAT_IRQ;
+	dev->types[7] = _DRM_STAT_PRIMARY;
+	dev->types[8] = _DRM_STAT_SECONDARY;
+	dev->types[9] = _DRM_STAT_DMA;
+
+	if (IS_I9XX(dev)) {
+		dev_priv->mmiobase = drm_get_resource_start(dev, 0);
+		dev_priv->mmiolen = drm_get_resource_len(dev, 0);
+	} else if (drm_get_resource_start(dev, 1)) {
+		dev_priv->mmiobase = drm_get_resource_start(dev, 1);
+		dev_priv->mmiolen = drm_get_resource_len(dev, 1);
+	} else {
+		DRM_ERROR("Unable to find MMIO registers\n");
+		return -ENODEV;
+	}
+
+	ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
+			 _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio_map);
+	if (ret != 0) {
+		DRM_ERROR("Cannot add mapping for MMIO registers\n");
+		return ret;
+	}
+
+	
+	ret = drm_setup(dev);
+	if (ret) {
+		DRM_ERROR("drm_setup failed\n");
+		return ret;
+	}
+
+	DRM_GETSAREA();
+	if (!dev_priv->sarea) {
+		DRM_ERROR("can not find sarea!\n");
+		dev->dev_private = (void *)dev_priv;
+		i915_dma_cleanup(dev);
+		return DRM_ERR(EINVAL);
+	}
+
+	/* FIXME: where does the sarea_priv really go? */
+	dev_priv->sarea_priv = kmalloc(sizeof(drm_i915_sarea_t), GFP_KERNEL);
+
+	/* FIXME: need real front buffer offset */
+	dev_priv->sarea_priv->front_handle = 0xa0000000 + 1024*1024;
+
+	drm_bo_driver_init(dev);
+	/* this probably doesn't belong here - TODO */
+	drm_framebuffer_set_object(dev, dev_priv->sarea_priv->front_handle);
+	intel_modeset_init(dev);
+	drm_set_desired_modes(dev);
+
+	/* FIXME: command ring needs AGP space, do we own it at this point? */
+	dev_priv->ring.Start = 0xa0000000;
+	dev_priv->ring.End = 128*1024;
+	dev_priv->ring.Size = 128*1024;
+	dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
+
+	dev_priv->ring.map.offset = dev_priv->ring.Start;
+	dev_priv->ring.map.size = dev_priv->ring.Size;
+	dev_priv->ring.map.type = 0;
+	dev_priv->ring.map.flags = 0;
+	dev_priv->ring.map.mtrr = 0;
+
+	drm_core_ioremap(&dev_priv->ring.map, dev);
+
+	if (dev_priv->ring.map.handle == NULL) {
+		dev->dev_private = (void *)dev_priv;
+		i915_dma_cleanup(dev);
+		DRM_ERROR("can not ioremap virtual address for"
+			  " ring buffer\n");
+		return DRM_ERR(ENOMEM);
+	}
+
+	dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
+	dev_priv->cpp = 4;
+	dev_priv->sarea_priv->pf_current_page = 0;
+
+	/* We are using separate values as placeholders for mechanisms for
+	 * private backbuffer/depthbuffer usage.
+	 */
+	dev_priv->use_mi_batchbuffer_start = 0;
+
+	/* Allow hardware batchbuffers unless told otherwise.
+	 */
+	dev_priv->allow_batchbuffer = 1;
+
+	/* Program Hardware Status Page */
+	dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 
+	    0xffffffff);
+
+	if (!dev_priv->status_page_dmah) {
+		dev->dev_private = (void *)dev_priv;
+		i915_dma_cleanup(dev);
+		DRM_ERROR("Can not allocate hardware status page\n");
+		return DRM_ERR(ENOMEM);
+	}
+	dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
+	dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
+	
+	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
+	DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
+
+	I915_WRITE(0x02080, dev_priv->dma_status_page);
+	DRM_DEBUG("Enabled hardware status page\n");
+
+	return 0;
+}
+
+int i915_driver_unload(drm_device_t *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+
+	intel_modeset_cleanup(dev);
+	drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
+
+	dev->dev_private = NULL;
+	return 0;
+}
+
+void i915_driver_lastclose(drm_device_t * dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	
+	i915_mem_takedown(&(dev_priv->agp_heap));
+
+	i915_dma_cleanup(dev);
+
+	dev_priv->mmio_map = NULL;
+}
+
+void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	i915_mem_release(dev, filp, dev_priv->agp_heap);
+}
+
-- 
cgit v1.2.3


From 44be9c9d5950d3b2ba4d5527189abec8dac0686f Mon Sep 17 00:00:00 2001
From: David Airlie <airlied@asimov.stargames.com.au>
Date: Wed, 11 Apr 2007 13:19:30 +1000
Subject: add an fb count + id get to the get resources code path

---
 shared-core/drm.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'shared-core')

diff --git a/shared-core/drm.h b/shared-core/drm.h
index f1afc049..a5330b28 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -909,7 +909,8 @@ struct drm_mode_modeinfo {
 
 struct drm_mode_card_res {
 
-	unsigned int fb_id;
+	int count_fbs;
+	unsigned int __user *fb_id;
 
 	int count_crtcs;
 	unsigned int __user *crtc_id;
-- 
cgit v1.2.3


From b329f91502a20cc6def44b7bea6cbc8b016edd5e Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@airlied2.(none)>
Date: Wed, 11 Apr 2007 14:04:18 +1000
Subject: use the baseaddr at least

---
 shared-core/i915_init.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_init.c b/shared-core/i915_init.c
index e454c9fc..038e3939 100644
--- a/shared-core/i915_init.c
+++ b/shared-core/i915_init.c
@@ -64,7 +64,7 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 	dev_priv->sarea_priv = kmalloc(sizeof(drm_i915_sarea_t), GFP_KERNEL);
 
 	/* FIXME: need real front buffer offset */
-	dev_priv->sarea_priv->front_handle = 0xa0000000 + 1024*1024;
+	dev_priv->sarea_priv->front_handle = dev_priv->baseaddr + 1024*1024;
 
 	drm_bo_driver_init(dev);
 	/* this probably doesn't belong here - TODO */
@@ -73,7 +73,7 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 	drm_set_desired_modes(dev);
 
 	/* FIXME: command ring needs AGP space, do we own it at this point? */
-	dev_priv->ring.Start = 0xa0000000;
+	dev_priv->ring.Start = dev_priv->baseaddr;
 	dev_priv->ring.End = 128*1024;
 	dev_priv->ring.Size = 128*1024;
 	dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
-- 
cgit v1.2.3


From 3dd5dc5728620cadec24ee5db323a20c3bb48bf0 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@airlied2.(none)>
Date: Wed, 11 Apr 2007 14:34:43 +1000
Subject: only init at driver load

---
 shared-core/i915_dma.c | 1 -
 1 file changed, 1 deletion(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index 1c8a0d45..a7603405 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -896,7 +896,6 @@ int i915_driver_firstopen(struct drm_device *dev)
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	int ret;
 	DRM_DEBUG("\n");
-	drm_bo_driver_init(dev);
 
 	if (!dev_priv->mmio_map) {
 		ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
-- 
cgit v1.2.3


From add7a928ad1819df17d5764d06fb81985b285d08 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@airlied2.(none)>
Date: Wed, 11 Apr 2007 14:43:02 +1000
Subject: comment out unworkable code

---
 shared-core/i915_init.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_init.c b/shared-core/i915_init.c
index 038e3939..61c128cb 100644
--- a/shared-core/i915_init.c
+++ b/shared-core/i915_init.c
@@ -45,7 +45,7 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 		return ret;
 	}
 
-	
+#if 0	
 	ret = drm_setup(dev);
 	if (ret) {
 		DRM_ERROR("drm_setup failed\n");
@@ -61,17 +61,17 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 	}
 
 	/* FIXME: where does the sarea_priv really go? */
-	dev_priv->sarea_priv = kmalloc(sizeof(drm_i915_sarea_t), GFP_KERNEL);
+        //	dev_priv->sarea_priv = kmalloc(sizeof(drm_i915_sarea_t), GFP_KERNEL);
 
 	/* FIXME: need real front buffer offset */
-	dev_priv->sarea_priv->front_handle = dev_priv->baseaddr + 1024*1024;
-
+        ///	dev_priv->sarea_priv->front_handle = dev_priv->baseaddr + 1024*1024;
+#endif
 	drm_bo_driver_init(dev);
 	/* this probably doesn't belong here - TODO */
 	//drm_framebuffer_set_object(dev, dev_priv->sarea_priv->front_handle);
 	intel_modeset_init(dev);
-	drm_set_desired_modes(dev);
-
+        //	drm_set_desired_modes(dev);
+#if 0
 	/* FIXME: command ring needs AGP space, do we own it at this point? */
 	dev_priv->ring.Start = dev_priv->baseaddr;
 	dev_priv->ring.End = 128*1024;
@@ -125,6 +125,7 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 
 	I915_WRITE(0x02080, dev_priv->dma_status_page);
 	DRM_DEBUG("Enabled hardware status page\n");
+#endif
 
 	return 0;
 }
-- 
cgit v1.2.3


From 32f6a58db216f23a7c71ca9c7eda56aaa8293078 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@airlied2.(none)>
Date: Wed, 11 Apr 2007 16:33:03 +1000
Subject: add initial drm_fb framebuffer

So far I can load fbcon, once I use my miniglx to add a framebuffer.
fbcon doesn't show anything on screen but baby steps and all that.
---
 shared-core/i915_init.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_init.c b/shared-core/i915_init.c
index 61c128cb..5af86f82 100644
--- a/shared-core/i915_init.c
+++ b/shared-core/i915_init.c
@@ -28,11 +28,11 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 	if (IS_I9XX(dev)) {
 		dev_priv->mmiobase = drm_get_resource_start(dev, 0);
 		dev_priv->mmiolen = drm_get_resource_len(dev, 0);
-		dev_priv->baseaddr = drm_get_resource_start(dev, 2) & 0xff000000;
+		dev->mode_config.fb_base = dev_priv->baseaddr = drm_get_resource_start(dev, 2) & 0xff000000;
 	} else if (drm_get_resource_start(dev, 1)) {
 		dev_priv->mmiobase = drm_get_resource_start(dev, 1);
 		dev_priv->mmiolen = drm_get_resource_len(dev, 1);
-		dev_priv->baseaddr = drm_get_resource_start(dev, 0) & 0xff000000;
+		dev->mode_config.fb_base = dev_priv->baseaddr = drm_get_resource_start(dev, 0) & 0xff000000;
 	} else {
 		DRM_ERROR("Unable to find MMIO registers\n");
 		return -ENODEV;
-- 
cgit v1.2.3


From a6cc6a778f8b2f86300a8ce87441d044fd67f930 Mon Sep 17 00:00:00 2001
From: David Airlie <airlied@asimov.stargames.com.au>
Date: Wed, 11 Apr 2007 17:13:45 +1000
Subject: add support for setting a framebuffer depth

---
 shared-core/drm.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core')

diff --git a/shared-core/drm.h b/shared-core/drm.h
index a5330b28..621b201c 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -970,6 +970,7 @@ struct drm_mode_fb_cmd {
         unsigned int pitch;
         unsigned int bpp;
         unsigned int handle;
+	unsigned int depth;
 };
 
 /**
-- 
cgit v1.2.3


From 78598fdaa8b23a199880a63b79f17cfd7f14cb0f Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@hobbes.virtuousgeek.org>
Date: Wed, 11 Apr 2007 07:07:54 -0700
Subject: Various changes for in-kernel modesetting:   - allow
 drm_buffer_object_create to be called w/o dev_mapping   - fixup i915 init
 code to allocate memory, fb and set modes right   - pass fb to
 drm_initial_config for setup   - change some debug output to make it easier
 to spot   - fixup lvds code to use DDC probing correctly

---
 shared-core/i915_init.c | 65 +++++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 55 insertions(+), 10 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_init.c b/shared-core/i915_init.c
index 5af86f82..d9fb485b 100644
--- a/shared-core/i915_init.c
+++ b/shared-core/i915_init.c
@@ -4,10 +4,23 @@
 #include "i915_drm.h"
 #include "i915_drv.h"
 
+/**
+ * i915_driver_load - setup chip and create an initial config
+ * @dev: DRM device
+ * @flags: startup flags
+ *
+ * The driver load routine has to do several things:
+ *   - drive output discovery via intel_modeset_init()
+ *   - initialize the memory manager
+ *   - allocate initial config memory
+ *   - setup the DRM framebuffer with the allocated memory
+ */
 int i915_driver_load(drm_device_t *dev, unsigned long flags)
 {
 	drm_i915_private_t *dev_priv;
 	drm_i915_init_t init;
+	drm_buffer_object_t *entry;
+	struct drm_framebuffer *fb;
 	int ret;
 
 	dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
@@ -45,7 +58,6 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 		return ret;
 	}
 
-#if 0	
 	ret = drm_setup(dev);
 	if (ret) {
 		DRM_ERROR("drm_setup failed\n");
@@ -60,17 +72,48 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 		return DRM_ERR(EINVAL);
 	}
 
-	/* FIXME: where does the sarea_priv really go? */
-        //	dev_priv->sarea_priv = kmalloc(sizeof(drm_i915_sarea_t), GFP_KERNEL);
+	/* FIXME: assume sarea_priv is right after SAREA */
+        dev_priv->sarea_priv = dev_priv->sarea->handle + sizeof(drm_sarea_t);
 
-	/* FIXME: need real front buffer offset */
-        ///	dev_priv->sarea_priv->front_handle = dev_priv->baseaddr + 1024*1024;
-#endif
+	/*
+	 * Initialize the memory manager for local and AGP space
+	 */
 	drm_bo_driver_init(dev);
-	/* this probably doesn't belong here - TODO */
-	//drm_framebuffer_set_object(dev, dev_priv->sarea_priv->front_handle);
+	/* FIXME: initial stolen area 8M init */
+#define SCANOUT_SIZE 1024*1024*8 /* big enough for 2048x1024 32bpp */
+	drm_bo_init_mm(dev, DRM_BO_MEM_PRIV0, dev->mode_config.fb_base,
+		       SCANOUT_SIZE);
+
+	/* Allocate scanout buffer and command ring */
+	/* FIXME: types and other args correct? */
+	drm_buffer_object_create(dev, SCANOUT_SIZE, drm_bo_type_dc,
+				 DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
+				 DRM_BO_FLAG_MEM_PRIV0 | DRM_BO_FLAG_NO_MOVE,
+				 0, PAGE_SIZE, 0,
+				 &entry);
+
+	DRM_DEBUG("allocated bo, start: 0x%lx, offset: 0x%lx\n",
+		  entry->buffer_start, entry->offset);
 	intel_modeset_init(dev);
-        //	drm_set_desired_modes(dev);
+
+	fb = drm_framebuffer_create(dev);
+	if (!fb) {
+		DRM_ERROR("failed to allocate fb\n");
+		return -EINVAL;
+	}
+
+	fb->width = 1024;
+	fb->height = 768;
+	fb->pitch = 1024;
+	fb->bits_per_pixel = 32;
+	fb->depth = 32;
+	fb->offset = entry->offset;
+	fb->bo = entry;
+
+	drm_initial_config(dev, fb, false);
+	drmfb_probe(dev, fb);
+        drm_set_desired_modes(dev);
+
 #if 0
 	/* FIXME: command ring needs AGP space, do we own it at this point? */
 	dev_priv->ring.Start = dev_priv->baseaddr;
@@ -133,8 +176,10 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 int i915_driver_unload(drm_device_t *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct drm_framebuffer *fb;
 
-	intel_modeset_cleanup(dev);
+	/* FIXME: remove framebuffer */
+	//intel_modeset_cleanup(dev);
 	drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
 
 	dev->dev_private = NULL;
-- 
cgit v1.2.3


From cc7faa4de80a68d5a7a484046b9b42de961cdbef Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@hobbes.virtuousgeek.org>
Date: Wed, 11 Apr 2007 07:21:24 -0700
Subject: fix modeset cleanup for LVDS and reenable it in i915.

---
 shared-core/i915_init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_init.c b/shared-core/i915_init.c
index d9fb485b..43c535d2 100644
--- a/shared-core/i915_init.c
+++ b/shared-core/i915_init.c
@@ -179,7 +179,7 @@ int i915_driver_unload(drm_device_t *dev)
 	struct drm_framebuffer *fb;
 
 	/* FIXME: remove framebuffer */
-	//intel_modeset_cleanup(dev);
+	intel_modeset_cleanup(dev);
 	drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
 
 	dev->dev_private = NULL;
-- 
cgit v1.2.3


From 8dd75bd601f5fbf9793afc7b869a278050aa17d5 Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@hobbes.virtuousgeek.org>
Date: Wed, 11 Apr 2007 11:47:58 -0700
Subject: Add aperture size and preallocation probing (from intelfb), cleanup
 load code to be more general.

---
 shared-core/i915_drv.h  |  21 ++++++++
 shared-core/i915_init.c | 132 +++++++++++++++++++++++++++++++++++++++++++-----
 2 files changed, 140 insertions(+), 13 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h
index b1bf0469..c22ab843 100644
--- a/shared-core/i915_drv.h
+++ b/shared-core/i915_drv.h
@@ -318,6 +318,27 @@ extern void intel_modeset_cleanup(drm_device_t *dev);
 
 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
 
+/*
+ * The Bridge device's PCI config space has information about the
+ * fb aperture size and the amount of pre-reserved memory.
+ */
+#define INTEL_GMCH_CTRL		0x52
+#define INTEL_GMCH_ENABLED	0x4
+#define INTEL_GMCH_MEM_MASK	0x1
+#define INTEL_GMCH_MEM_64M	0x1
+#define INTEL_GMCH_MEM_128M	0
+
+#define INTEL_855_GMCH_GMS_MASK		(0x7 << 4)
+#define INTEL_855_GMCH_GMS_DISABLED	(0x0 << 4)
+#define INTEL_855_GMCH_GMS_STOLEN_1M	(0x1 << 4)
+#define INTEL_855_GMCH_GMS_STOLEN_4M	(0x2 << 4)
+#define INTEL_855_GMCH_GMS_STOLEN_8M	(0x3 << 4)
+#define INTEL_855_GMCH_GMS_STOLEN_16M	(0x4 << 4)
+#define INTEL_855_GMCH_GMS_STOLEN_32M	(0x5 << 4)
+
+#define INTEL_915G_GMCH_GMS_STOLEN_48M	(0x6 << 4)
+#define INTEL_915G_GMCH_GMS_STOLEN_64M	(0x7 << 4)
+
 #define GFX_OP_USER_INTERRUPT 		((0<<29)|(2<<23))
 #define GFX_OP_BREAKPOINT_INTERRUPT	((0<<29)|(1<<23))
 #define CMD_REPORT_HEAD			(7<<23)
diff --git a/shared-core/i915_init.c b/shared-core/i915_init.c
index 43c535d2..fba633fd 100644
--- a/shared-core/i915_init.c
+++ b/shared-core/i915_init.c
@@ -1,9 +1,108 @@
+/*
+ * Copyright (c) 2007 Intel Corporation
+ *   Jesse Barnes <jesse.barnes@intel.com>
+ *
+ * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
+ *                   2004 Sylvain Meyer
+ *
+ * GPL/BSD dual license
+ */
 #include "drmP.h"
 #include "drm.h"
 #include "drm_sarea.h"
 #include "i915_drm.h"
 #include "i915_drv.h"
 
+/**
+ * i915_probe_agp - get AGP bootup configuration
+ * @pdev: PCI device
+ * @aperture_size: returns AGP aperture configured size
+ * @preallocated_size: returns size of BIOS preallocated AGP space
+ *
+ * Since Intel integrated graphics are UMA, the BIOS has to set aside
+ * some RAM for the framebuffer at early boot.  This code figures out
+ * how much was set aside so we can use it for our own purposes.
+ */
+int i915_probe_agp(struct pci_dev *pdev, unsigned long *aperture_size,
+		   unsigned long *preallocated_size)
+{
+	struct pci_dev *bridge_dev;
+	u16 tmp = 0;
+	unsigned long overhead;
+
+	bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
+	if (!bridge_dev) {
+		DRM_ERROR("bridge device not found\n");
+		return -1;
+	}
+
+	/* Get the fb aperture size and "stolen" memory amount. */
+	pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
+	pci_dev_put(bridge_dev);
+
+	*aperture_size = 1024 * 1024;
+	*preallocated_size = 1024 * 1024;
+
+	switch (pdev->device) {
+	case PCI_DEVICE_ID_INTEL_82915G_IG:
+	case PCI_DEVICE_ID_INTEL_82915GM_IG:
+	case PCI_DEVICE_ID_INTEL_82945G_IG:
+	case PCI_DEVICE_ID_INTEL_82945GM_IG:
+		/* 915 and 945 chipsets support a 256MB aperture.
+		   Aperture size is determined by inspected the
+		   base address of the aperture. */
+		if (pci_resource_start(pdev, 2) & 0x08000000)
+			*aperture_size *= 128;
+		else
+			*aperture_size *= 256;
+		break;
+	default:
+		if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
+			*aperture_size *= 64;
+		else
+			*aperture_size *= 128;
+		break;
+	}
+
+	/*
+	 * Some of the preallocated space is taken by the GTT
+	 * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
+	 */
+	overhead = (*aperture_size / 1024) + 4096;
+	switch (tmp & INTEL_855_GMCH_GMS_MASK) {
+	case INTEL_855_GMCH_GMS_STOLEN_1M:
+		break; /* 1M already */
+	case INTEL_855_GMCH_GMS_STOLEN_4M:
+		*preallocated_size *= 4;
+		break;
+	case INTEL_855_GMCH_GMS_STOLEN_8M:
+		*preallocated_size *= 8;
+		break;
+	case INTEL_855_GMCH_GMS_STOLEN_16M:
+		*preallocated_size *= 16;
+		break;
+	case INTEL_855_GMCH_GMS_STOLEN_32M:
+		*preallocated_size *= 32;
+		break;
+	case INTEL_915G_GMCH_GMS_STOLEN_48M:
+		*preallocated_size *= 48;
+		break;
+	case INTEL_915G_GMCH_GMS_STOLEN_64M:
+		*preallocated_size *= 64;
+		break;
+	case INTEL_855_GMCH_GMS_DISABLED:
+		DRM_ERROR("video memory is disabled\n");
+		return -1;
+	default:
+		DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
+			tmp & INTEL_855_GMCH_GMS_MASK);
+		return -1;
+	}
+	*preallocated_size -= overhead;
+
+	return 0;
+}
+
 /**
  * i915_driver_load - setup chip and create an initial config
  * @dev: DRM device
@@ -21,7 +120,8 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 	drm_i915_init_t init;
 	drm_buffer_object_t *entry;
 	struct drm_framebuffer *fb;
-	int ret;
+	unsigned long agp_size, prealloc_size;
+	int hsize, vsize, bytes_per_pixel, size, ret;
 
 	dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
 	if (dev_priv == NULL)
@@ -41,11 +141,13 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 	if (IS_I9XX(dev)) {
 		dev_priv->mmiobase = drm_get_resource_start(dev, 0);
 		dev_priv->mmiolen = drm_get_resource_len(dev, 0);
-		dev->mode_config.fb_base = dev_priv->baseaddr = drm_get_resource_start(dev, 2) & 0xff000000;
+		dev->mode_config.fb_base = dev_priv->baseaddr =
+			drm_get_resource_start(dev, 2) & 0xff000000;
 	} else if (drm_get_resource_start(dev, 1)) {
 		dev_priv->mmiobase = drm_get_resource_start(dev, 1);
 		dev_priv->mmiolen = drm_get_resource_len(dev, 1);
-		dev->mode_config.fb_base = dev_priv->baseaddr = drm_get_resource_start(dev, 0) & 0xff000000;
+		dev->mode_config.fb_base = dev_priv->baseaddr =
+			drm_get_resource_start(dev, 0) & 0xff000000;
 	} else {
 		DRM_ERROR("Unable to find MMIO registers\n");
 		return -ENODEV;
@@ -79,14 +181,18 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 	 * Initialize the memory manager for local and AGP space
 	 */
 	drm_bo_driver_init(dev);
-	/* FIXME: initial stolen area 8M init */
-#define SCANOUT_SIZE 1024*1024*8 /* big enough for 2048x1024 32bpp */
-	drm_bo_init_mm(dev, DRM_BO_MEM_PRIV0, dev->mode_config.fb_base,
-		       SCANOUT_SIZE);
+
+	i915_probe_agp(dev->pdev, &agp_size, &prealloc_size);
+	drm_bo_init_mm(dev, DRM_BO_MEM_PRIV0, dev_priv->baseaddr,
+		       prealloc_size);
 
 	/* Allocate scanout buffer and command ring */
 	/* FIXME: types and other args correct? */
-	drm_buffer_object_create(dev, SCANOUT_SIZE, drm_bo_type_dc,
+	hsize = 1280;
+	vsize = 800;
+	bytes_per_pixel = 4;
+	size = hsize * vsize * bytes_per_pixel;
+	drm_buffer_object_create(dev, size, drm_bo_type_dc,
 				 DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
 				 DRM_BO_FLAG_MEM_PRIV0 | DRM_BO_FLAG_NO_MOVE,
 				 0, PAGE_SIZE, 0,
@@ -102,11 +208,11 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 		return -EINVAL;
 	}
 
-	fb->width = 1024;
-	fb->height = 768;
-	fb->pitch = 1024;
-	fb->bits_per_pixel = 32;
-	fb->depth = 32;
+	fb->width = hsize;
+	fb->height = vsize;
+	fb->pitch = hsize;
+	fb->bits_per_pixel = bytes_per_pixel * 8;
+	fb->depth = bytes_per_pixel * 8;
 	fb->offset = entry->offset;
 	fb->bo = entry;
 
-- 
cgit v1.2.3


From 2e21779992bd5026d8ec4dea52466377dbe5a0ed Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@hobbes.virtuousgeek.org>
Date: Wed, 11 Apr 2007 12:51:52 -0700
Subject: Add new buffer object type for kernel allocations that don't
 initially have a user mapping.

---
 shared-core/drm.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core')

diff --git a/shared-core/drm.h b/shared-core/drm.h
index 621b201c..698f851b 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -795,6 +795,7 @@ typedef struct drm_fence_arg {
 
 typedef enum {
 	drm_bo_type_dc,
+	drm_bo_type_kernel, /* for initial kernel allocations */
 	drm_bo_type_user,
 	drm_bo_type_fake
 }drm_bo_type_t;
-- 
cgit v1.2.3


From 9d7160c43a7475b9d2ab06c5c353acb9456efa12 Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@hobbes.virtuousgeek.org>
Date: Wed, 11 Apr 2007 12:52:57 -0700
Subject: Use new kernel buffer object type and cleanup agp probing.

---
 shared-core/i915_init.c | 23 +++++++++--------------
 1 file changed, 9 insertions(+), 14 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_init.c b/shared-core/i915_init.c
index fba633fd..b942b70f 100644
--- a/shared-core/i915_init.c
+++ b/shared-core/i915_init.c
@@ -44,24 +44,19 @@ int i915_probe_agp(struct pci_dev *pdev, unsigned long *aperture_size,
 	*preallocated_size = 1024 * 1024;
 
 	switch (pdev->device) {
-	case PCI_DEVICE_ID_INTEL_82915G_IG:
-	case PCI_DEVICE_ID_INTEL_82915GM_IG:
-	case PCI_DEVICE_ID_INTEL_82945G_IG:
-	case PCI_DEVICE_ID_INTEL_82945GM_IG:
-		/* 915 and 945 chipsets support a 256MB aperture.
-		   Aperture size is determined by inspected the
-		   base address of the aperture. */
-		if (pci_resource_start(pdev, 2) & 0x08000000)
-			*aperture_size *= 128;
-		else
-			*aperture_size *= 256;
-		break;
-	default:
+	case PCI_DEVICE_ID_INTEL_82830_CGC:
+	case PCI_DEVICE_ID_INTEL_82845G_HB:
+	case PCI_DEVICE_ID_INTEL_82855GM_IG:
+	case PCI_DEVICE_ID_INTEL_82865_IG:
 		if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 			*aperture_size *= 64;
 		else
 			*aperture_size *= 128;
 		break;
+	default:
+		/* 9xx supports large sizes, just look at the length */
+		*aperture_size = pci_resource_len(pdev, 2);
+		break;
 	}
 
 	/*
@@ -192,7 +187,7 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 	vsize = 800;
 	bytes_per_pixel = 4;
 	size = hsize * vsize * bytes_per_pixel;
-	drm_buffer_object_create(dev, size, drm_bo_type_dc,
+	drm_buffer_object_create(dev, size, drm_bo_type_kernel,
 				 DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
 				 DRM_BO_FLAG_MEM_PRIV0 | DRM_BO_FLAG_NO_MOVE,
 				 0, PAGE_SIZE, 0,
-- 
cgit v1.2.3


From a81558d8b3ee17fbf46e32b10732e22fcd997858 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Thu, 12 Apr 2007 08:45:40 +1000
Subject: add getfb ioctl

---
 shared-core/drm.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core')

diff --git a/shared-core/drm.h b/shared-core/drm.h
index 698f851b..b5b0aa52 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -1051,6 +1051,7 @@ struct drm_mode_fb_cmd {
 #define DRM_IOCTL_MODE_SETCRTC          DRM_IOWR(0xA3, struct drm_mode_crtc)
 #define DRM_IOCTL_MODE_ADDFB            DRM_IOWR(0xA4, struct drm_mode_fb_cmd)
 #define DRM_IOCTL_MODE_RMFB             DRM_IOWR(0xA5, unsigned int)
+#define DRM_IOCTL_MODE_GETFB             DRM_IOWR(0xA6, struct drm_mode_fb_cmd)
 /*@}*/
 
 /**
-- 
cgit v1.2.3


From fb6c5aacb9955248300e0c62f68a5a65b40e15e1 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Thu, 12 Apr 2007 11:54:49 +1000
Subject: only initialise modes when fbcon or fbset asks for it

---
 shared-core/i915_init.c | 2 --
 1 file changed, 2 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_init.c b/shared-core/i915_init.c
index b942b70f..ebe73815 100644
--- a/shared-core/i915_init.c
+++ b/shared-core/i915_init.c
@@ -213,8 +213,6 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags)
 
 	drm_initial_config(dev, fb, false);
 	drmfb_probe(dev, fb);
-        drm_set_desired_modes(dev);
-
 #if 0
 	/* FIXME: command ring needs AGP space, do we own it at this point? */
 	dev_priv->ring.Start = dev_priv->baseaddr;
-- 
cgit v1.2.3