From ee8954cb53e4964a5565833b5a937f1cbcb60d44 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 6 May 2007 11:17:30 +1000 Subject: drm/ttm: cleanup mm_ioctl ioctls to be separate ioctls. This is the first bunch of ioctls --- shared-core/drm.h | 54 +++++++++++++++++++++++++++++++++++------------------- 1 file changed, 35 insertions(+), 19 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index b4195419..d561a082 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -862,24 +862,14 @@ typedef struct drm_bo_arg{ #define DRM_BO_MEM_TYPES 8 /* For now. */ -typedef union drm_mm_init_arg{ - struct { - enum { - mm_init, - mm_takedown, - mm_query, - mm_lock, - mm_unlock - } op; - drm_u64_t p_offset; - drm_u64_t p_size; - unsigned mem_type; - unsigned expand_pad[8]; /*Future expansion */ - } req; - struct { - drm_handle_t mm_sarea; - unsigned expand_pad[8]; /*Future expansion */ - } rep; +typedef struct drm_mm_type_arg { + unsigned int mem_type; +} drm_mm_type_arg_t; + +typedef struct drm_mm_init_arg { + drm_u64_t p_offset; + drm_u64_t p_size; + unsigned int mem_type; } drm_mm_init_arg_t; /** @@ -949,10 +939,36 @@ typedef union drm_mm_init_arg{ #define DRM_IOCTL_FENCE DRM_IOWR(0x3b, drm_fence_arg_t) #define DRM_IOCTL_BUFOBJ DRM_IOWR(0x3d, drm_bo_arg_t) -#define DRM_IOCTL_MM_INIT DRM_IOWR(0x3e, drm_mm_init_arg_t) #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, drm_update_draw_t) +#define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, drm_mm_init_arg_t) +#define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, drm_mm_type_arg_t) +#define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, drm_mm_type_arg_t) +#define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, drm_mm_type_arg_t) + +#define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, drm_fence_arg_t) +#define DRM_IOCTL_FENCE_DESTROY DRM_IOWR(0xc5, drm_fence_arg_t) +#define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, drm_fence_arg_t) +#define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, drm_fence_arg_t) +#define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, drm_fence_arg_t) +#define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, drm_fence_arg_t) +#define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, drm_fence_arg_t) +#define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcb, drm_fence_arg_t) + +#define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcc, drm_bo_arg_t) +#define DRM_IOCTL_BO_DESTROY DRM_IOWR(0xcd, drm_bo_arg_t) +#define DRM_IOCTL_BO_MAP DRM_IOWR(0xce, drm_bo_arg_t) +#define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xcf, drm_bo_arg_t) +#define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd0, drm_bo_arg_t) +#define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd1, drm_bo_arg_t) +#define DRM_IOCTL_BO_VALIDATE DRM_IOWR(0xd2, drm_bo_arg_t) +#define DRM_IOCTL_BO_FENCE DRM_IOWR(0xd3, drm_bo_arg_t) +#define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, drm_bo_arg_t) +#define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, drm_bo_arg_t) +#define DRM_IOCTL_BO_REF_FENCE DRM_IOWR(0xd6, drm_bo_arg_t) + + /*@}*/ /** -- cgit v1.2.3 From 6a62941ecaa7d2b8f14b30920856bfa52aee4775 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 6 May 2007 11:35:11 +1000 Subject: drm/ttm: cleanup most of fence ioctl split out --- shared-core/drm.h | 38 ++++++++++++++------------------------ 1 file changed, 14 insertions(+), 24 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index d561a082..9810321e 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -677,17 +677,6 @@ typedef struct drm_fence_arg { unsigned flags; unsigned signaled; unsigned expand_pad[4]; /*Future expansion */ - enum { - drm_fence_create, - drm_fence_destroy, - drm_fence_reference, - drm_fence_unreference, - drm_fence_signaled, - drm_fence_flush, - drm_fence_wait, - drm_fence_emit, - drm_fence_buffers - } op; } drm_fence_arg_t; /* Buffer permissions, referring to how the GPU uses the buffers. @@ -954,19 +943,20 @@ typedef struct drm_mm_init_arg { #define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, drm_fence_arg_t) #define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, drm_fence_arg_t) #define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, drm_fence_arg_t) -#define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcb, drm_fence_arg_t) - -#define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcc, drm_bo_arg_t) -#define DRM_IOCTL_BO_DESTROY DRM_IOWR(0xcd, drm_bo_arg_t) -#define DRM_IOCTL_BO_MAP DRM_IOWR(0xce, drm_bo_arg_t) -#define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xcf, drm_bo_arg_t) -#define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd0, drm_bo_arg_t) -#define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd1, drm_bo_arg_t) -#define DRM_IOCTL_BO_VALIDATE DRM_IOWR(0xd2, drm_bo_arg_t) -#define DRM_IOCTL_BO_FENCE DRM_IOWR(0xd3, drm_bo_arg_t) -#define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, drm_bo_arg_t) -#define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, drm_bo_arg_t) -#define DRM_IOCTL_BO_REF_FENCE DRM_IOWR(0xd6, drm_bo_arg_t) +#define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, drm_fence_arg_t) +#define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, drm_fence_arg_t) + +#define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, drm_bo_arg_t) +#define DRM_IOCTL_BO_DESTROY DRM_IOWR(0xce, drm_bo_arg_t) +#define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, drm_bo_arg_t) +#define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, drm_bo_arg_t) +#define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, drm_bo_arg_t) +#define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, drm_bo_arg_t) +#define DRM_IOCTL_BO_VALIDATE DRM_IOWR(0xd3, drm_bo_arg_t) +#define DRM_IOCTL_BO_FENCE DRM_IOWR(0xd4, drm_bo_arg_t) +#define DRM_IOCTL_BO_INFO DRM_IOWR(0xd5, drm_bo_arg_t) +#define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd6, drm_bo_arg_t) +#define DRM_IOCTL_BO_REF_FENCE DRM_IOWR(0xd7, drm_bo_arg_t) /*@}*/ -- cgit v1.2.3 From 25c51f539f254937d116699e66f8c382d78e71d4 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 8 May 2007 17:53:58 +1000 Subject: drm/ttm: ioctl cleanup for buffer object - user side only This just cleans up the xf86drm.c to what I want and drm.h, I need to fix up the kernel internals to suit these changes now. I've moved to using struct instead of typedefs for the bo and it doesn't look that bad so I'll do the same thing for mm and fence.. --- shared-core/drm.h | 112 ++++++++++++++++++++++++++++++++---------------------- 1 file changed, 66 insertions(+), 46 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index 9810321e..7b3ee153 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -782,32 +782,29 @@ typedef enum { drm_bo_type_kernel, /* for initial kernel allocations */ }drm_bo_type_t; +struct drm_bo_info_req { + unsigned int handle; + unsigned int mask; + unsigned int hint; +}; -typedef struct drm_bo_arg_request { - unsigned handle; /* User space handle */ - unsigned mask; - unsigned hint; +struct drm_bo_create_req { + unsigned int mask; + unsigned int hint; + unsigned page_alignment; drm_u64_t size; drm_bo_type_t type; - unsigned arg_handle; drm_u64_t buffer_start; - unsigned page_alignment; - unsigned expand_pad[4]; /*Future expansion */ +}; + +struct drm_bo_op_req { + struct drm_bo_info_req bo_req; + unsigned int arg_handle; enum { - drm_bo_create, drm_bo_validate, - drm_bo_map, - drm_bo_unmap, drm_bo_fence, - drm_bo_destroy, - drm_bo_reference, - drm_bo_unreference, - drm_bo_info, - drm_bo_wait_idle, - drm_bo_ref_fence } op; -} drm_bo_arg_request_t; - +}; /* * Reply flags @@ -815,30 +812,58 @@ typedef struct drm_bo_arg_request { #define DRM_BO_REP_BUSY 0x00000001 -typedef struct drm_bo_arg_reply { - int ret; - unsigned handle; - unsigned flags; +struct drm_bo_info_rep { + unsigned int handle; + unsigned int flags; drm_u64_t size; drm_u64_t offset; drm_u64_t arg_handle; - unsigned mask; + unsigned int mask; drm_u64_t buffer_start; - unsigned fence_flags; - unsigned rep_flags; - unsigned page_alignment; - unsigned expand_pad[4]; /*Future expansion */ -}drm_bo_arg_reply_t; + unsigned int fence_flags; + unsigned int rep_flags; + unsigned int page_alignment; + unsigned int expand_pad[4]; /*Future expansion */ +}; + +struct drm_bo_arg_rep { + int ret; + struct drm_bo_info_rep bo_info; +}; + +struct drm_bo_create_arg { + union { + struct drm_bo_create_req req; + struct drm_bo_info_rep rep; + } d; +}; + +struct drm_bo_handle_arg { + unsigned int handle; +}; + +struct drm_bo_reference_info_arg { + union { + struct drm_bo_handle_arg req; + struct drm_bo_info_rep rep; + } d; +}; +struct drm_bo_map_wait_idle_arg { + union { + struct drm_bo_info_req req; + struct drm_bo_info_rep rep; + } d; +}; -typedef struct drm_bo_arg{ +struct drm_bo_op_arg { int handled; drm_u64_t next; union { - drm_bo_arg_request_t req; - drm_bo_arg_reply_t rep; + struct drm_bo_op_req req; + struct drm_bo_arg_rep rep; } d; -} drm_bo_arg_t; +}; #define DRM_BO_MEM_LOCAL 0 #define DRM_BO_MEM_TT 1 @@ -926,9 +951,6 @@ typedef struct drm_mm_init_arg { #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t) -#define DRM_IOCTL_FENCE DRM_IOWR(0x3b, drm_fence_arg_t) -#define DRM_IOCTL_BUFOBJ DRM_IOWR(0x3d, drm_bo_arg_t) - #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, drm_update_draw_t) #define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, drm_mm_init_arg_t) @@ -946,17 +968,15 @@ typedef struct drm_mm_init_arg { #define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, drm_fence_arg_t) #define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, drm_fence_arg_t) -#define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, drm_bo_arg_t) -#define DRM_IOCTL_BO_DESTROY DRM_IOWR(0xce, drm_bo_arg_t) -#define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, drm_bo_arg_t) -#define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, drm_bo_arg_t) -#define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, drm_bo_arg_t) -#define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, drm_bo_arg_t) -#define DRM_IOCTL_BO_VALIDATE DRM_IOWR(0xd3, drm_bo_arg_t) -#define DRM_IOCTL_BO_FENCE DRM_IOWR(0xd4, drm_bo_arg_t) -#define DRM_IOCTL_BO_INFO DRM_IOWR(0xd5, drm_bo_arg_t) -#define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd6, drm_bo_arg_t) -#define DRM_IOCTL_BO_REF_FENCE DRM_IOWR(0xd7, drm_bo_arg_t) +#define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg) +#define DRM_IOCTL_BO_DESTROY DRM_IOWR(0xce, struct drm_bo_handle_arg) +#define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg) +#define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg) +#define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg) +#define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg) +#define DRM_IOCTL_BO_OP DRM_IOWR(0xd3, struct drm_bo_op_arg) +#define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg) +#define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg) /*@}*/ -- cgit v1.2.3 From b2a875ba8955cfbf3df2dc1ecb25915a252eef9f Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 8 May 2007 18:25:15 +1000 Subject: ttm: complete drm buffer object ioctl split retain the op operation for validate/fence operations --- shared-core/drm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index 7b3ee153..ae308be6 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -803,6 +803,7 @@ struct drm_bo_op_req { enum { drm_bo_validate, drm_bo_fence, + drm_bo_ref_fence, } op; }; -- cgit v1.2.3 From b6b5df24b962c94433afe4d8665b5f145bfa1ad3 Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Tue, 12 Jun 2007 12:21:38 +0200 Subject: Try to make buffer object / fence object ioctl args 64-bit safe. Introduce tile members for future tiled buffer support. Allow user-space to explicitly define a fence-class. Remove the implicit fence-class mechanism. 64-bit wide buffer object flag member. --- shared-core/drm.h | 103 +++++++++++++++++++++++++++++-------------------- shared-core/i915_drv.h | 4 +- shared-core/via_drv.h | 4 +- 3 files changed, 65 insertions(+), 46 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index ae308be6..bc2e718c 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -671,12 +671,13 @@ typedef struct drm_set_version { #define DRM_FENCE_TYPE_EXE 0x00000001 typedef struct drm_fence_arg { - unsigned handle; - int class; - unsigned type; - unsigned flags; - unsigned signaled; - unsigned expand_pad[4]; /*Future expansion */ + unsigned int handle; + unsigned int class; + unsigned int type; + unsigned int flags; + unsigned int signaled; + unsigned int pad_64; + drm_u64_t expand_pad[3]; /*Future expansion */ } drm_fence_arg_t; /* Buffer permissions, referring to how the GPU uses the buffers. @@ -685,9 +686,9 @@ typedef struct drm_fence_arg { * a command (batch-) buffer is exe. Can be or-ed together. */ -#define DRM_BO_FLAG_READ 0x00000001 -#define DRM_BO_FLAG_WRITE 0x00000002 -#define DRM_BO_FLAG_EXE 0x00000004 +#define DRM_BO_FLAG_READ (1ULL << 0) +#define DRM_BO_FLAG_WRITE (1ULL << 1) +#define DRM_BO_FLAG_EXE (1ULL << 2) /* * Status flags. Can be read to determine the actual state of a buffer. @@ -700,25 +701,25 @@ typedef struct drm_fence_arg { * or lock. * Flags: Acknowledge */ -#define DRM_BO_FLAG_NO_EVICT 0x00000010 +#define DRM_BO_FLAG_NO_EVICT (1ULL << 4) /* * Mask: Require that the buffer is placed in mappable memory when validated. * If not set the buffer may or may not be in mappable memory when validated. * Flags: If set, the buffer is in mappable memory. */ -#define DRM_BO_FLAG_MAPPABLE 0x00000020 +#define DRM_BO_FLAG_MAPPABLE (1ULL << 5) /* Mask: The buffer should be shareable with other processes. * Flags: The buffer is shareable with other processes. */ -#define DRM_BO_FLAG_SHAREABLE 0x00000040 +#define DRM_BO_FLAG_SHAREABLE (1ULL << 6) /* Mask: If set, place the buffer in cache-coherent memory if available. * If clear, never place the buffer in cache coherent memory if validated. * Flags: The buffer is currently in cache-coherent memory. */ -#define DRM_BO_FLAG_CACHED 0x00000080 +#define DRM_BO_FLAG_CACHED (1ULL << 7) /* Mask: Make sure that every time this buffer is validated, * it ends up on the same location provided that the memory mask is the same. @@ -727,23 +728,23 @@ typedef struct drm_fence_arg { * part of buffer manager shutdown or locking. * Flags: Acknowledge. */ -#define DRM_BO_FLAG_NO_MOVE 0x00000100 +#define DRM_BO_FLAG_NO_MOVE (1ULL << 8) /* Mask: Make sure the buffer is in cached memory when mapped for reading. * Flags: Acknowledge. */ -#define DRM_BO_FLAG_READ_CACHED 0x00080000 +#define DRM_BO_FLAG_READ_CACHED (1ULL << 16) /* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set. * Flags: Acknowledge. */ -#define DRM_BO_FLAG_FORCE_CACHING 0x00002000 +#define DRM_BO_FLAG_FORCE_CACHING (1ULL << 13) /* * Mask: Force DRM_BO_FLAG_MAPPABLE flag strictly also if it is clear. * Flags: Acknowledge. */ -#define DRM_BO_FLAG_FORCE_MAPPABLE 0x00004000 +#define DRM_BO_FLAG_FORCE_MAPPABLE (1ULL << 14) /* * Memory type flags that can be or'ed together in the mask, but only @@ -751,21 +752,25 @@ typedef struct drm_fence_arg { */ /* System memory */ -#define DRM_BO_FLAG_MEM_LOCAL 0x01000000 +#define DRM_BO_FLAG_MEM_LOCAL (1ULL << 24) /* Translation table memory */ -#define DRM_BO_FLAG_MEM_TT 0x02000000 +#define DRM_BO_FLAG_MEM_TT (1ULL << 25) /* Vram memory */ -#define DRM_BO_FLAG_MEM_VRAM 0x04000000 +#define DRM_BO_FLAG_MEM_VRAM (1ULL << 26) /* Up to the driver to define. */ -#define DRM_BO_FLAG_MEM_PRIV0 0x08000000 -#define DRM_BO_FLAG_MEM_PRIV1 0x10000000 -#define DRM_BO_FLAG_MEM_PRIV2 0x20000000 -#define DRM_BO_FLAG_MEM_PRIV3 0x40000000 -#define DRM_BO_FLAG_MEM_PRIV4 0x80000000 +#define DRM_BO_FLAG_MEM_PRIV0 (1ULL << 27) +#define DRM_BO_FLAG_MEM_PRIV1 (1ULL << 28) +#define DRM_BO_FLAG_MEM_PRIV2 (1ULL << 29) +#define DRM_BO_FLAG_MEM_PRIV3 (1ULL << 30) +#define DRM_BO_FLAG_MEM_PRIV4 (1ULL << 31) +/* We can add more of these now with a 64-bit flag type */ /* Memory flag mask */ -#define DRM_BO_MASK_MEM 0xFF000000 -#define DRM_BO_MASK_MEMTYPE 0xFF0000A0 +#define DRM_BO_MASK_MEM 0x00000000FF000000ULL +#define DRM_BO_MASK_MEMTYPE 0x00000000FF0000A0ULL + +/* Driver-private flags */ +#define DRM_BO_MASK_DRIVER 0xFFFF000000000000ULL /* Don't block on validate and map */ #define DRM_BO_HINT_DONT_BLOCK 0x00000002 @@ -774,6 +779,10 @@ typedef struct drm_fence_arg { #define DRM_BO_HINT_WAIT_LAZY 0x00000008 #define DRM_BO_HINT_ALLOW_UNFENCED_MAP 0x00000010 +#define DRM_BO_INIT_MAGIC 0xfe769812 +#define DRM_BO_INIT_MAJOR 0 +#define DRM_BO_INIT_MINOR 1 + typedef enum { drm_bo_type_dc, @@ -783,28 +792,30 @@ typedef enum { }drm_bo_type_t; struct drm_bo_info_req { - unsigned int handle; - unsigned int mask; + drm_u64_t mask; + drm_u64_t flags; + unsigned int handle; unsigned int hint; + unsigned int fence_class; }; struct drm_bo_create_req { - unsigned int mask; - unsigned int hint; - unsigned page_alignment; + drm_u64_t mask; drm_u64_t size; - drm_bo_type_t type; drm_u64_t buffer_start; + unsigned int hint; + unsigned int page_alignment; + drm_bo_type_t type; }; struct drm_bo_op_req { - struct drm_bo_info_req bo_req; - unsigned int arg_handle; enum { drm_bo_validate, drm_bo_fence, drm_bo_ref_fence, } op; + unsigned int arg_handle; + struct drm_bo_info_req bo_req; }; /* @@ -814,22 +825,26 @@ struct drm_bo_op_req { #define DRM_BO_REP_BUSY 0x00000001 struct drm_bo_info_rep { - unsigned int handle; - unsigned int flags; + drm_u64_t flags; + drm_u64_t mask; drm_u64_t size; drm_u64_t offset; drm_u64_t arg_handle; - unsigned int mask; drm_u64_t buffer_start; + unsigned int handle; unsigned int fence_flags; unsigned int rep_flags; unsigned int page_alignment; - unsigned int expand_pad[4]; /*Future expansion */ + unsigned int desired_tile_stride; + unsigned int hw_tile_stride; + unsigned int tile_info; + unsigned int pad64; + drm_u64_t expand_pad[4]; /*Future expansion */ }; struct drm_bo_arg_rep { - int ret; struct drm_bo_info_rep bo_info; + int ret; }; struct drm_bo_create_arg { @@ -859,6 +874,7 @@ struct drm_bo_map_wait_idle_arg { struct drm_bo_op_arg { int handled; + unsigned int pad_64; drm_u64_t next; union { struct drm_bo_op_req req; @@ -879,12 +895,15 @@ struct drm_bo_op_arg { typedef struct drm_mm_type_arg { unsigned int mem_type; -} drm_mm_type_arg_t; +} drm_mm_type_arg_t; typedef struct drm_mm_init_arg { + unsigned int magic; + unsigned int major; + unsigned int minor; + unsigned int mem_type; drm_u64_t p_offset; drm_u64_t p_size; - unsigned int mem_type; } drm_mm_init_arg_t; /** diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index e8a7be29..52a958d9 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -196,8 +196,8 @@ extern int i915_fence_has_irq(drm_device_t *dev, uint32_t class, uint32_t flags) #ifdef I915_HAVE_BUFFER /* i915_buffer.c */ extern drm_ttm_backend_t *i915_create_ttm_backend_entry(drm_device_t *dev); -extern int i915_fence_types(drm_buffer_object_t *bo, uint32_t *class, uint32_t *type); -extern int i915_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags); +extern int i915_fence_types(drm_buffer_object_t *bo, uint32_t *type); +extern int i915_invalidate_caches(drm_device_t *dev, uint64_t buffer_flags); extern int i915_init_mem_type(drm_device_t *dev, uint32_t type, drm_mem_type_manager_t *man); extern uint32_t i915_evict_mask(drm_buffer_object_t *bo); diff --git a/shared-core/via_drv.h b/shared-core/via_drv.h index baafbbff..b6dbf6c1 100644 --- a/shared-core/via_drv.h +++ b/shared-core/via_drv.h @@ -205,8 +205,8 @@ extern int via_fence_has_irq(struct drm_device * dev, uint32_t class, #ifdef VIA_HAVE_BUFFER extern drm_ttm_backend_t *via_create_ttm_backend_entry(drm_device_t *dev); -extern int via_fence_types(drm_buffer_object_t *bo, uint32_t *class, uint32_t *type); -extern int via_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags); +extern int via_fence_types(drm_buffer_object_t *bo, uint32_t *type); +extern int via_invalidate_caches(drm_device_t *dev, uint64_t buffer_flags); extern int via_init_mem_type(drm_device_t *dev, uint32_t type, drm_mem_type_manager_t *man); extern uint32_t via_evict_mask(drm_buffer_object_t *bo); -- cgit v1.2.3 From f984b1b8d17f285dfacb593702178f1eb2fdb4ac Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Tue, 12 Jun 2007 12:30:33 +0200 Subject: Fix some obvious bugs. --- shared-core/drm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index bc2e718c..1b0e54e3 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -733,7 +733,7 @@ typedef struct drm_fence_arg { /* Mask: Make sure the buffer is in cached memory when mapped for reading. * Flags: Acknowledge. */ -#define DRM_BO_FLAG_READ_CACHED (1ULL << 16) +#define DRM_BO_FLAG_READ_CACHED (1ULL << 19) /* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set. * Flags: Acknowledge. -- cgit v1.2.3 From 3d5d41fa9823cf44138c8f4bc954bca80539d74e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Fri, 15 Jun 2007 17:13:11 +0200 Subject: i915: Fix handling of breadcrumb counter wraparounds. --- shared-core/i915_dma.c | 8 +++++--- shared-core/i915_drv.h | 3 +++ 2 files changed, 8 insertions(+), 3 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index ebb184cc..dbc5f959 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -445,10 +445,12 @@ void i915_emit_breadcrumb(drm_device_t *dev) drm_i915_private_t *dev_priv = dev->dev_private; RING_LOCALS; - dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter; + if (++dev_priv->counter > BREADCRUMB_MASK) { + dev_priv->counter = 1; + DRM_DEBUG("Breadcrumb counter wrapped around\n"); + } - if (dev_priv->counter > 0x7FFFFFFFUL) - dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1; + dev_priv->sarea_priv->last_enqueue = dev_priv->counter; BEGIN_LP_RING(4); OUT_RING(CMD_STORE_DWORD_IDX); diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 9deee8ec..e0432996 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -363,6 +363,9 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller); #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) +#define BREADCRUMB_BITS 31 +#define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1) + #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5]) #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) #endif -- cgit v1.2.3 From 8038e7b60f62e51b7f134141fd58f334eec31a10 Mon Sep 17 00:00:00 2001 From: Oliver McFadden Date: Mon, 18 Jun 2007 08:36:50 +0000 Subject: r300: Synchronized the register defines file again. --- shared-core/r300_reg.h | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/r300_reg.h b/shared-core/r300_reg.h index 0a31f0b9..3ce09c16 100644 --- a/shared-core/r300_reg.h +++ b/shared-core/r300_reg.h @@ -116,6 +116,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */ #define R300_VAP_OUTPUT_VTX_FMT_1 0x2094 + /* each of the following is 3 bits wide, specifies number + of components */ # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 @@ -299,6 +301,18 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_221C_NORMAL 0x00000000 # define R300_221C_CLEAR 0x0001C000 +/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first + * plane is per-pixel and the second plane is per-vertex. + * + * This was determined by experimentation alone but I believe it is correct. + * + * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest. + */ +#define R300_VAP_CLIP_X_0 0x2220 +#define R300_VAP_CLIP_X_1 0x2224 +#define R300_VAP_CLIP_Y_0 0x2228 +#define R300_VAP_CLIP_Y_1 0x2230 + /* gap */ /* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between @@ -967,7 +981,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * first node is stored in NODE_2, the second node is stored in NODE_3. * * Offsets are relative to the master offset from PFS_CNTL_2. - * LAST_NODE is set for the last node, and only for the last node. */ #define R300_PFS_NODE_0 0x4610 #define R300_PFS_NODE_1 0x4614 @@ -981,7 +994,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12) # define R300_PFS_NODE_TEX_END_SHIFT 17 # define R300_PFS_NODE_TEX_END_MASK (31 << 17) -/*# define R300_PFS_NODE_LAST_NODE (1 << 22) */ # define R300_PFS_NODE_OUTPUT_COLOR (1 << 22) # define R300_PFS_NODE_OUTPUT_DEPTH (1 << 23) @@ -1591,6 +1603,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_EB_UNK1_SHIFT 24 # define R300_EB_UNK1 (0x80<<24) # define R300_EB_UNK2 0x0810 +#define R300_PACKET3_3D_DRAW_VBUF_2 0x00003400 #define R300_PACKET3_3D_DRAW_INDX_2 0x00003600 /* END: Packet 3 commands */ -- cgit v1.2.3 From 215787e4297ed4f6364bcc98869a347fc4cad00d Mon Sep 17 00:00:00 2001 From: Oliver McFadden Date: Mon, 18 Jun 2007 08:42:46 +0000 Subject: r300: Registers 0x2220-0x2230 are known as R300_VAP_CLIP_X_0-R300_VAP_CLIP_Y_1. --- shared-core/r300_cmdbuf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/r300_cmdbuf.c b/shared-core/r300_cmdbuf.c index d3c52d43..c02334a2 100644 --- a/shared-core/r300_cmdbuf.c +++ b/shared-core/r300_cmdbuf.c @@ -155,7 +155,7 @@ void r300_init_reg_flags(void) ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2); ADD_RANGE(0x21DC, 1); ADD_RANGE(R300_VAP_UNKNOWN_221C, 1); - ADD_RANGE(0x2220, 4); + ADD_RANGE(R300_VAP_CLIP_X_0, 4); ADD_RANGE(R300_VAP_UNKNOWN_2288, 1); ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2); ADD_RANGE(R300_VAP_PVS_CNTL_1, 3); -- cgit v1.2.3 From 213732af4381819113756d6d920794cf0dc30dd6 Mon Sep 17 00:00:00 2001 From: Oliver McFadden Date: Thu, 21 Jun 2007 14:32:58 +0000 Subject: r300: Allow writes to R300_VAP_PVS_WAITIDLE. --- shared-core/r300_cmdbuf.c | 1 + 1 file changed, 1 insertion(+) (limited to 'shared-core') diff --git a/shared-core/r300_cmdbuf.c b/shared-core/r300_cmdbuf.c index c02334a2..0cd5d7e2 100644 --- a/shared-core/r300_cmdbuf.c +++ b/shared-core/r300_cmdbuf.c @@ -156,6 +156,7 @@ void r300_init_reg_flags(void) ADD_RANGE(0x21DC, 1); ADD_RANGE(R300_VAP_UNKNOWN_221C, 1); ADD_RANGE(R300_VAP_CLIP_X_0, 4); + ADD_RANGE(R300_VAP_PVS_WAITIDLE, 1); ADD_RANGE(R300_VAP_UNKNOWN_2288, 1); ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2); ADD_RANGE(R300_VAP_PVS_CNTL_1, 3); -- cgit v1.2.3 From 40f6a696cb22ffa064f78198a7a241015d365967 Mon Sep 17 00:00:00 2001 From: Oliver McFadden Date: Thu, 21 Jun 2007 14:35:11 +0000 Subject: r300: Synchronized the register defines file; documentation changes. --- shared-core/r300_reg.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'shared-core') diff --git a/shared-core/r300_reg.h b/shared-core/r300_reg.h index 3ce09c16..e59919be 100644 --- a/shared-core/r300_reg.h +++ b/shared-core/r300_reg.h @@ -336,13 +336,15 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * The meaning of the two UNKNOWN fields is obviously not known. However, * experiments so far have shown that both *must* point to an instruction * inside the vertex program, otherwise the GPU locks up. + * * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and - * CNTL_1_UNKNOWN points to instruction where last write to position takes - * place. + * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to + * position takes place. + * * Most likely this is used to ignore rest of the program in cases * where group of verts arent visible. For some reason this "section" * is sometimes accepted other instruction that have no relationship with - *position calculations. + * position calculations. */ #define R300_VAP_PVS_CNTL_1 0x22D0 # define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0 -- cgit v1.2.3 From 068ffc1e1bf5607f836839a1fc621a95547251e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Fri, 22 Jun 2007 11:55:26 +0200 Subject: radeon: Acknowledge all interrupts we're interested in. Failure to do so was probably the root cause of fd.o bug 11287. --- shared-core/radeon_irq.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/radeon_irq.c b/shared-core/radeon_irq.c index 5151b4d6..a4be86e3 100644 --- a/shared-core/radeon_irq.c +++ b/shared-core/radeon_irq.c @@ -72,10 +72,14 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS) /* Only consider the bits we're interested in - others could be used * outside the DRM */ - stat = radeon_acknowledge_irqs(dev_priv, dev_priv->irq_enable_reg); + stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK | + RADEON_CRTC_VBLANK_STAT | + RADEON_CRTC2_VBLANK_STAT)); if (!stat) return IRQ_NONE; + stat &= dev_priv->irq_enable_reg; + /* SW interrupt */ if (stat & RADEON_SW_INT_TEST) { DRM_WAKEUP(&dev_priv->swi_queue); @@ -265,7 +269,8 @@ void radeon_driver_irq_preinstall(drm_device_t * dev) /* Clear bits if they're already high */ radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK | - RADEON_CRTC_VBLANK_STAT)); + RADEON_CRTC_VBLANK_STAT | + RADEON_CRTC2_VBLANK_STAT)); } void radeon_driver_irq_postinstall(drm_device_t * dev) -- cgit v1.2.3 From 5c7c07fd49b154623f9dfdab1fe1f2cda8508036 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 24 Jun 2007 18:54:36 +1000 Subject: nouveau: rename engtab functions --- shared-core/nouveau_drv.h | 30 ++++++------ shared-core/nouveau_state.c | 110 ++++++++++++++++++++++---------------------- 2 files changed, 70 insertions(+), 70 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index debee8e4..89b284c3 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -101,29 +101,29 @@ struct nouveau_config { struct nouveau_engine_func { struct { - int (*Init)(drm_device_t *dev); - void (*Takedown)(drm_device_t *dev); - } Mc; + int (*init)(drm_device_t *dev); + void (*takedown)(drm_device_t *dev); + } mc; struct { - int (*Init)(drm_device_t *dev); - void (*Takedown)(drm_device_t *dev); - } Timer; + int (*init)(drm_device_t *dev); + void (*takedown)(drm_device_t *dev); + } timer; struct { - int (*Init)(drm_device_t *dev); - void (*Takedown)(drm_device_t *dev); - } Fb; + int (*init)(drm_device_t *dev); + void (*takedown)(drm_device_t *dev); + } fb; struct { - int (*Init)(drm_device_t *dev); - void (*Takedown)(drm_device_t *dev); - } Graph; + int (*init)(drm_device_t *dev); + void (*takedown)(drm_device_t *dev); + } graph; struct { - int (*Init)(drm_device_t *dev); - void (*Takedown)(drm_device_t *dev); - } Fifo; + int (*init)(drm_device_t *dev); + void (*takedown)(drm_device_t *dev); + } fifo; }; typedef struct drm_nouveau_private { diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index e7930b9e..592797c3 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -80,64 +80,64 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) switch (dev_priv->chipset & 0xf0) { case 0x00: - engine->Mc.Init = nv04_mc_init; - engine->Mc.Takedown = nv04_mc_takedown; - engine->Timer.Init = nv04_timer_init; - engine->Timer.Takedown = nv04_timer_takedown; - engine->Fb.Init = nv04_fb_init; - engine->Fb.Takedown = nv04_fb_takedown; - engine->Graph.Init = nv04_graph_init; - engine->Graph.Takedown = nv04_graph_takedown; - engine->Fifo.Init = nouveau_fifo_init; - engine->Fifo.Takedown = nouveau_stub_takedown; + engine->mc.init = nv04_mc_init; + engine->mc.takedown = nv04_mc_takedown; + engine->timer.init = nv04_timer_init; + engine->timer.takedown = nv04_timer_takedown; + engine->fb.init = nv04_fb_init; + engine->fb.takedown = nv04_fb_takedown; + engine->graph.init = nv04_graph_init; + engine->graph.takedown = nv04_graph_takedown; + engine->fifo.init = nouveau_fifo_init; + engine->fifo.takedown = nouveau_stub_takedown; break; case 0x10: - engine->Mc.Init = nv04_mc_init; - engine->Mc.Takedown = nv04_mc_takedown; - engine->Timer.Init = nv04_timer_init; - engine->Timer.Takedown = nv04_timer_takedown; - engine->Fb.Init = nv10_fb_init; - engine->Fb.Takedown = nv10_fb_takedown; - engine->Graph.Init = nv10_graph_init; - engine->Graph.Takedown = nv10_graph_takedown; - engine->Fifo.Init = nouveau_fifo_init; - engine->Fifo.Takedown = nouveau_stub_takedown; + engine->mc.init = nv04_mc_init; + engine->mc.takedown = nv04_mc_takedown; + engine->timer.init = nv04_timer_init; + engine->timer.takedown = nv04_timer_takedown; + engine->fb.init = nv10_fb_init; + engine->fb.takedown = nv10_fb_takedown; + engine->graph.init = nv10_graph_init; + engine->graph.takedown = nv10_graph_takedown; + engine->fifo.init = nouveau_fifo_init; + engine->fifo.takedown = nouveau_stub_takedown; break; case 0x20: - engine->Mc.Init = nv04_mc_init; - engine->Mc.Takedown = nv04_mc_takedown; - engine->Timer.Init = nv04_timer_init; - engine->Timer.Takedown = nv04_timer_takedown; - engine->Fb.Init = nv10_fb_init; - engine->Fb.Takedown = nv10_fb_takedown; - engine->Graph.Init = nv20_graph_init; - engine->Graph.Takedown = nv20_graph_takedown; - engine->Fifo.Init = nouveau_fifo_init; - engine->Fifo.Takedown = nouveau_stub_takedown; + engine->mc.init = nv04_mc_init; + engine->mc.takedown = nv04_mc_takedown; + engine->timer.init = nv04_timer_init; + engine->timer.takedown = nv04_timer_takedown; + engine->fb.init = nv10_fb_init; + engine->fb.takedown = nv10_fb_takedown; + engine->graph.init = nv20_graph_init; + engine->graph.takedown = nv20_graph_takedown; + engine->fifo.init = nouveau_fifo_init; + engine->fifo.takedown = nouveau_stub_takedown; break; case 0x30: - engine->Mc.Init = nv04_mc_init; - engine->Mc.Takedown = nv04_mc_takedown; - engine->Timer.Init = nv04_timer_init; - engine->Timer.Takedown = nv04_timer_takedown; - engine->Fb.Init = nv10_fb_init; - engine->Fb.Takedown = nv10_fb_takedown; - engine->Graph.Init = nv30_graph_init; - engine->Graph.Takedown = nv30_graph_takedown; - engine->Fifo.Init = nouveau_fifo_init; - engine->Fifo.Takedown = nouveau_stub_takedown; + engine->mc.init = nv04_mc_init; + engine->mc.takedown = nv04_mc_takedown; + engine->timer.init = nv04_timer_init; + engine->timer.takedown = nv04_timer_takedown; + engine->fb.init = nv10_fb_init; + engine->fb.takedown = nv10_fb_takedown; + engine->graph.init = nv30_graph_init; + engine->graph.takedown = nv30_graph_takedown; + engine->fifo.init = nouveau_fifo_init; + engine->fifo.takedown = nouveau_stub_takedown; break; case 0x40: - engine->Mc.Init = nv40_mc_init; - engine->Mc.Takedown = nv40_mc_takedown; - engine->Timer.Init = nv04_timer_init; - engine->Timer.Takedown = nv04_timer_takedown; - engine->Fb.Init = nv40_fb_init; - engine->Fb.Takedown = nv40_fb_takedown; - engine->Graph.Init = nv40_graph_init; - engine->Graph.Takedown = nv40_graph_takedown; - engine->Fifo.Init = nouveau_fifo_init; - engine->Fifo.Takedown = nouveau_stub_takedown; + engine->mc.init = nv40_mc_init; + engine->mc.takedown = nv40_mc_takedown; + engine->timer.init = nv04_timer_init; + engine->timer.takedown = nv04_timer_takedown; + engine->fb.init = nv40_fb_init; + engine->fb.takedown = nv40_fb_takedown; + engine->graph.init = nv40_graph_init; + engine->graph.takedown = nv40_graph_takedown; + engine->fifo.init = nouveau_fifo_init; + engine->fifo.takedown = nouveau_stub_takedown; break; case 0x50: default: @@ -184,23 +184,23 @@ static int nouveau_card_init(drm_device_t *dev) /* Parse BIOS tables / Run init tables? */ /* PMC */ - ret = engine->Mc.Init(dev); + ret = engine->mc.init(dev); if (ret) return ret; /* PTIMER */ - ret = engine->Timer.Init(dev); + ret = engine->timer.init(dev); if (ret) return ret; /* PFB */ - ret = engine->Fb.Init(dev); + ret = engine->fb.init(dev); if (ret) return ret; /* PGRAPH */ - ret = engine->Graph.Init(dev); + ret = engine->graph.init(dev); if (ret) return ret; /* PFIFO */ - ret = engine->Fifo.Init(dev); + ret = engine->fifo.init(dev); if (ret) return ret; /* what about PVIDEO/PCRTC/PRAMDAC etc? */ -- cgit v1.2.3 From 24b71c318a00dfbb18b2bbf6652e3b781175c430 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 24 Jun 2007 18:54:51 +1000 Subject: nouveau: prototype PFIFO/PGRAPH engtab API --- shared-core/nouveau_drv.h | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 89b284c3..093a93c5 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -116,13 +116,23 @@ struct nouveau_engine_func { } fb; struct { - int (*init)(drm_device_t *dev); - void (*takedown)(drm_device_t *dev); + int (*init)(drm_device_t *); + void (*takedown)(drm_device_t *); + + int (*create_context)(drm_device_t *, int channel); + void (*destroy_context)(drm_device_t *, int channel); + int (*load_context)(drm_device_t *, int channel); + int (*save_context)(drm_device_t *, int channel); } graph; struct { - int (*init)(drm_device_t *dev); - void (*takedown)(drm_device_t *dev); + int (*init)(drm_device_t *); + void (*takedown)(drm_device_t *); + + int (*create_context)(drm_device_t *, int channel); + void (*destroy_context)(drm_device_t *, int channel); + int (*load_context)(drm_device_t *, int channel); + int (*save_context)(drm_device_t *, int channel); } fifo; }; -- cgit v1.2.3 From 9dbf322d26642f9e671f144b34e7cd7d295e9b8e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 24 Jun 2007 18:55:06 +1000 Subject: nouveau: (mostly) hook up put_base again --- shared-core/nouveau_drv.h | 1 + shared-core/nouveau_fifo.c | 21 ++++++++++----------- 2 files changed, 11 insertions(+), 11 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 093a93c5..da604d37 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -83,6 +83,7 @@ struct nouveau_fifo /* dma object for the command buffer itself */ struct mem_block *cmdbuf_mem; struct nouveau_object *cmdbuf_obj; + uint32_t pushbuf_base; /* PGRAPH context, for cards that keep it in RAMIN */ struct mem_block *ramin_grctx; /* objects belonging to this fifo */ diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 8e66ca2e..cc4ff127 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -232,6 +232,7 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) return DRM_ERR(ENOMEM); } + dev_priv->fifos[channel].pushbuf_base = 0; dev_priv->fifos[channel].cmdbuf_mem = cb; dev_priv->fifos[channel].cmdbuf_obj = cb_dma; return 0; @@ -460,7 +461,7 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) { int ret; drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_object *cb_obj; + struct nouveau_fifo *chan; int channel; /* @@ -478,14 +479,16 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) if (channel==nouveau_fifo_number(dev)) return DRM_ERR(EINVAL); (*chan_ret) = channel; + chan = &dev_priv->fifos[channel]; DRM_INFO("Allocating FIFO number %d\n", channel); /* that fifo is used */ - dev_priv->fifos[channel].used = 1; - dev_priv->fifos[channel].filp = filp; + chan->used = 1; + chan->filp = filp; + /* FIFO has no objects yet */ - dev_priv->fifos[channel].objs = NULL; + chan->objs = NULL; /* allocate a command buffer, and create a dma object for the gpu */ ret = nouveau_fifo_cmdbuf_alloc(dev, channel); @@ -493,7 +496,6 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) nouveau_fifo_free(dev, channel); return ret; } - cb_obj = dev_priv->fifos[channel].cmdbuf_obj; nouveau_wait_for_idle(dev); @@ -548,8 +550,8 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<pushbuf_base); + NV_WRITE(NV03_FIFO_REGS_DMAGET(channel), chan->pushbuf_base); /* If this is the first channel, setup PFIFO ourselves. For any * other case, the GPU will handle this when it switches contexts. @@ -557,10 +559,8 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) if (dev_priv->fifo_alloc_count == 0) { nouveau_fifo_context_restore(dev, channel); if (dev_priv->card_type >= NV_30) { - struct nouveau_fifo *chan; uint32_t inst; - chan = &dev_priv->fifos[channel]; inst = nouveau_chip_instance_get(dev, chan->ramin_grctx); @@ -679,8 +679,7 @@ static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) if (res) return res; - /* this should probably disappear in the next abi break? */ - init.put_base = 0; + init.put_base = dev_priv->fifos[init.channel].pushbuf_base; /* make the fifo available to user space */ /* first, the fifo control regs */ -- cgit v1.2.3 From 0afb3b518e1ece820b01f3eea64b25cff01c97bc Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 24 Jun 2007 18:55:23 +1000 Subject: nouveau: split PFIFO/PGRAPH context creation --- shared-core/nouveau_fifo.c | 38 +++++++++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 7 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index cc4ff127..5bbd1c02 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -505,18 +505,16 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000); NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000); - /* Construct inital RAMFC for new channel */ + /* Create a graphics context for new channel */ switch(dev_priv->card_type) { case NV_04: case NV_05: nv04_graph_context_create(dev, channel); - nouveau_nv04_context_init(dev, channel); break; case NV_10: case NV_17: nv10_graph_context_create(dev, channel); - nouveau_nv10_context_init(dev, channel); break; case NV_20: ret = nv20_graph_context_create(dev, channel); @@ -524,7 +522,6 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) nouveau_fifo_free(dev, channel); return ret; } - nouveau_nv10_context_init(dev, channel); break; case NV_30: ret = nv30_graph_context_create(dev, channel); @@ -532,18 +529,45 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) nouveau_fifo_free(dev, channel); return ret; } - nouveau_nv30_context_init(dev, channel); break; case NV_40: case NV_44: - case NV_50: ret = nv40_graph_context_create(dev, channel); if (ret) { nouveau_fifo_free(dev, channel); return ret; } - nouveau_nv40_context_init(dev, channel); break; + default: + DRM_ERROR("grctx: unknown card type\n"); + nouveau_fifo_free(dev, channel); + return DRM_ERR(EINVAL); + } + + /* Construct inital RAMFC for new channel */ + switch (dev_priv->card_type) { + case NV_04: + case NV_05: + nouveau_nv04_context_init(dev, channel); + break; + case NV_10: + case NV_17: + nouveau_nv10_context_init(dev, channel); + break; + case NV_20: + nouveau_nv10_context_init(dev, channel); + break; + case NV_30: + nouveau_nv30_context_init(dev, channel); + break; + case NV_40: + case NV_44: + nouveau_nv40_context_init(dev, channel); + break; + default: + DRM_ERROR("fifoctx: unknown card type\n"); + nouveau_fifo_free(dev, channel); + return DRM_ERR(EINVAL); } /* enable the fifo dma operation */ -- cgit v1.2.3 From f2e64d527699751d6b64698495ae1d48eeee6cf7 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 24 Jun 2007 18:56:01 +1000 Subject: nouveau: NV4X PFIFO engtab functions --- shared-core/nouveau_drv.h | 10 ++- shared-core/nouveau_fifo.c | 100 +++++++---------------- shared-core/nouveau_reg.h | 4 +- shared-core/nouveau_state.c | 4 + shared-core/nv40_fifo.c | 193 ++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 235 insertions(+), 76 deletions(-) create mode 100644 shared-core/nv40_fifo.c (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index da604d37..7c29a882 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -100,7 +100,7 @@ struct nouveau_config { } cmdbuf; }; -struct nouveau_engine_func { +typedef struct nouveau_engine_func { struct { int (*init)(drm_device_t *dev); void (*takedown)(drm_device_t *dev); @@ -135,7 +135,7 @@ struct nouveau_engine_func { int (*load_context)(drm_device_t *, int channel); int (*save_context)(drm_device_t *, int channel); } fifo; -}; +} nouveau_engine_func_t; typedef struct drm_nouveau_private { /* the card type, takes NV_* as values */ @@ -255,6 +255,12 @@ extern void nv10_fb_takedown(drm_device_t *dev); extern int nv40_fb_init(drm_device_t *dev); extern void nv40_fb_takedown(drm_device_t *dev); +/* nv40_fifo.c */ +extern int nv40_fifo_create_context(drm_device_t *, int channel); +extern void nv40_fifo_destroy_context(drm_device_t *, int channel); +extern int nv40_fifo_load_context(drm_device_t *, int channel); +extern int nv40_fifo_save_context(drm_device_t *, int channel); + /* nv04_graph.c */ extern void nouveau_nv04_context_switch(drm_device_t *dev); extern int nv04_graph_init(drm_device_t *dev); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 5bbd1c02..50f094b9 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -358,64 +358,6 @@ static void nouveau_nv10_context_save(drm_device_t *dev) #endif #undef RAMFC_WR -#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV40_RAMFC_##offset, (val)) -static void nouveau_nv40_context_init(drm_device_t *dev, int channel) -{ - drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - uint32_t fifoctx, cb_inst, grctx_inst; - int i; - - cb_inst = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance); - grctx_inst = nouveau_chip_instance_get(dev, chan->ramin_grctx); - fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128; - for (i=0;i<128;i+=4) - NV_WRITE(fifoctx + i, 0); - - /* Fill entries that are seen filled in dumps of nvidia driver just - * after channel's is put into DMA mode - */ - RAMFC_WR(DMA_INSTANCE , cb_inst); - RAMFC_WR(DMA_FETCH , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | -#ifdef __BIG_ENDIAN - NV_PFIFO_CACHE1_BIG_ENDIAN | -#endif - 0x30000000 /* no idea.. */); - RAMFC_WR(GRCTX_INSTANCE, grctx_inst); - RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF); -} - -static void nouveau_nv40_context_save(drm_device_t *dev) -{ - drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx; - int channel; - - channel = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1); - fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128; - - RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); - RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); - RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT)); - RAMFC_WR(DMA_INSTANCE , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE)); - RAMFC_WR(DMA_DCOUNT , NV_READ(NV10_PFIFO_CACHE1_DMA_DCOUNT)); - RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE)); - RAMFC_WR(DMA_FETCH , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH)); - RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE)); - RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1)); - RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE)); - RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP)); - RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT)); - RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE)); - RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); - RAMFC_WR(GRCTX_INSTANCE , NV_READ(NV40_PFIFO_GRCTX_INSTANCE)); - RAMFC_WR(DMA_TIMESLICE , NV_READ(NV04_PFIFO_DMA_TIMESLICE) & 0x1FFFF); - RAMFC_WR(UNK_40 , NV_READ(NV40_PFIFO_UNK32E4)); -} -#undef RAMFC_WR - /* This function should load values from RAMFC into PFIFO, but for now * it just clobbers PFIFO with what nouveau_fifo_alloc used to setup * unconditionally. @@ -461,6 +403,7 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) { int ret; drm_nouveau_private_t *dev_priv = dev->dev_private; + nouveau_engine_func_t *engine = &dev_priv->Engine; struct nouveau_fifo *chan; int channel; @@ -560,14 +503,17 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) case NV_30: nouveau_nv30_context_init(dev, channel); break; - case NV_40: - case NV_44: - nouveau_nv40_context_init(dev, channel); - break; default: - DRM_ERROR("fifoctx: unknown card type\n"); - nouveau_fifo_free(dev, channel); - return DRM_ERR(EINVAL); + if (!engine->fifo.create_context) { + DRM_ERROR("fifo.create_context == NULL\n"); + return DRM_ERR(EINVAL); + } + + ret = engine->fifo.create_context(dev, channel); + if (ret) { + nouveau_fifo_free(dev, channel); + return ret; + } } /* enable the fifo dma operation */ @@ -581,7 +527,11 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) * other case, the GPU will handle this when it switches contexts. */ if (dev_priv->fifo_alloc_count == 0) { - nouveau_fifo_context_restore(dev, channel); + if (engine->fifo.load_context) + engine->fifo.load_context(dev, channel); + else + nouveau_fifo_context_restore(dev, channel); + if (dev_priv->card_type >= NV_30) { uint32_t inst; @@ -615,6 +565,7 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) void nouveau_fifo_free(drm_device_t* dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; + nouveau_engine_func_t *engine = &dev_priv->Engine; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; int i; int ctx_size = nouveau_fifo_ctx_size(dev); @@ -629,12 +580,17 @@ void nouveau_fifo_free(drm_device_t* dev, int channel) // FIXME XXX needs more code /* Clean RAMFC */ - for (i=0;iramfc_offset + - channel*ctx_size + i)); - NV_WRITE(NV_RAMIN + dev_priv->ramfc_offset + - channel*ctx_size + i, 0); + if (engine->fifo.destroy_context) + engine->fifo.destroy_context(dev, channel); + else { + for (i=0;iramfc_offset + + channel*ctx_size + i)); + NV_WRITE(NV_RAMIN + dev_priv->ramfc_offset + + channel*ctx_size + i, 0); + } } /* Cleanup PGRAPH state */ diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index ea4a2f6b..07c54a92 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -462,6 +462,6 @@ #define NV40_RAMFC_UNK_40 0x40 #define NV40_RAMFC_UNK_44 0x44 #define NV40_RAMFC_UNK_48 0x48 -#define NV40_RAMFC_2088 0x4C -#define NV40_RAMFC_3300 0x50 +#define NV40_RAMFC_UNK_4C 0x4C +#define NV40_RAMFC_UNK_50 0x50 diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 592797c3..42860e9a 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -138,6 +138,10 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) engine->graph.takedown = nv40_graph_takedown; engine->fifo.init = nouveau_fifo_init; engine->fifo.takedown = nouveau_stub_takedown; + engine->fifo.create_context = nv40_fifo_create_context; + engine->fifo.destroy_context = nv40_fifo_destroy_context; + engine->fifo.load_context = nv40_fifo_load_context; + engine->fifo.save_context = nv40_fifo_save_context; break; case 0x50: default: diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c new file mode 100644 index 00000000..b67a7e58 --- /dev/null +++ b/shared-core/nv40_fifo.c @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2007 Ben Skeggs. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "drmP.h" +#include "nouveau_drv.h" +#include "nouveau_drm.h" + +#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV40_RAMFC_##offset, (val)) +#define RAMFC_RD(offset) NV_READ (fifoctx + NV40_RAMFC_##offset) + +int +nv40_fifo_create_context(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + uint32_t fifoctx, grctx, pushbuf; + int i; + + fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128; + for (i=0;i<128;i+=4) + NV_WRITE(fifoctx + i, 0); + + grctx = nouveau_chip_instance_get(dev, chan->ramin_grctx); + pushbuf = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance); + + /* Fill entries that are seen filled in dumps of nvidia driver just + * after channel's is put into DMA mode + */ + RAMFC_WR(DMA_PUT , chan->pushbuf_base); + RAMFC_WR(DMA_GET , chan->pushbuf_base); + RAMFC_WR(DMA_INSTANCE , pushbuf); + RAMFC_WR(DMA_FETCH , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | +#ifdef __BIG_ENDIAN + NV_PFIFO_CACHE1_BIG_ENDIAN | +#endif + 0x30000000 /* no idea.. */); + RAMFC_WR(DMA_SUBROUTINE, 0); + RAMFC_WR(GRCTX_INSTANCE, grctx); + RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF); + + return 0; +} + +void +nv40_fifo_destroy_context(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t fifoctx; + int i; + + fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128; + for (i=0;i<128;i+=4) + NV_WRITE(fifoctx + i, 0); +} + +int +nv40_fifo_load_context(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t fifoctx; + uint32_t tmp, tmp2; + + fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128; + + NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET)); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT , RAMFC_RD(DMA_PUT)); + NV_WRITE(NV10_PFIFO_CACHE1_REF_CNT , RAMFC_RD(REF_CNT)); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE , RAMFC_RD(DMA_INSTANCE)); + NV_WRITE(NV10_PFIFO_CACHE1_DMA_DCOUNT , RAMFC_RD(DMA_DCOUNT)); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE , RAMFC_RD(DMA_STATE)); + + /* No idea what 0x2058 is.. */ + tmp = RAMFC_RD(DMA_FETCH); + tmp2 = NV_READ(0x2058) & 0xFFF; + tmp2 |= (tmp & 0x30000000); + NV_WRITE(0x2058, tmp2); + tmp &= ~0x30000000; + NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH , tmp); + + NV_WRITE(NV04_PFIFO_CACHE1_ENGINE , RAMFC_RD(ENGINE)); + NV_WRITE(NV04_PFIFO_CACHE1_PULL1 , RAMFC_RD(PULL1_ENGINE)); + NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE , RAMFC_RD(ACQUIRE_VALUE)); + NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, RAMFC_RD(ACQUIRE_TIMESTAMP)); + NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT , RAMFC_RD(ACQUIRE_TIMEOUT)); + NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE , RAMFC_RD(SEMAPHORE)); + NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE , RAMFC_RD(DMA_SUBROUTINE)); + NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE , RAMFC_RD(GRCTX_INSTANCE)); + NV_WRITE(0x32e4, RAMFC_RD(UNK_40)); + /* NVIDIA does this next line twice... */ + NV_WRITE(0x32e8, RAMFC_RD(UNK_44)); + NV_WRITE(0x2088, RAMFC_RD(UNK_4C)); + NV_WRITE(0x3300, RAMFC_RD(UNK_50)); + + /* not sure what part is PUT, and which is GET.. never seen a non-zero + * value appear in a mmio-trace yet.. + */ +#if 0 + tmp = NV_READ(UNK_84); + NV_WRITE(NV_PFIFO_CACHE1_GET, tmp ???); + NV_WRITE(NV_PFIFO_CACHE1_PUT, tmp ???); +#endif + + /* Don't clobber the TIMEOUT_ENABLED flag when restoring from RAMFC */ + tmp = NV_READ(NV04_PFIFO_DMA_TIMESLICE) & ~0x1FFFF; + tmp |= RAMFC_RD(DMA_TIMESLICE) & 0x1FFFF; + NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, tmp); + + /* Set channel active, and in DMA mode */ + NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00010000 | channel); + /* Reset DMA_CTL_AT_INFO to INVALID */ + tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp); + + return 0; +} + +int +nv40_fifo_save_context(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t fifoctx; + uint32_t tmp; + + fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128; + + RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); + RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); + RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT)); + RAMFC_WR(DMA_INSTANCE , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE)); + RAMFC_WR(DMA_DCOUNT , NV_READ(NV10_PFIFO_CACHE1_DMA_DCOUNT)); + RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE)); + + tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH); + tmp |= NV_READ(0x2058) & 0x30000000; + RAMFC_WR(DMA_FETCH , tmp); + + RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE)); + RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1)); + RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE)); + tmp = NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP); + RAMFC_WR(ACQUIRE_TIMESTAMP, tmp); + RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT)); + RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE)); + + /* NVIDIA read 0x3228 first, then write DMA_GET here.. maybe something + * more involved depending on the value of 0x3228? + */ + RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); + + RAMFC_WR(GRCTX_INSTANCE , NV_READ(NV40_PFIFO_GRCTX_INSTANCE)); + + /* No idea what the below is for exactly, ripped from a mmio-trace */ + RAMFC_WR(UNK_40 , NV_READ(NV40_PFIFO_UNK32E4)); + + /* NVIDIA do this next line twice.. bug? */ + RAMFC_WR(UNK_44 , NV_READ(0x32e8)); + RAMFC_WR(UNK_4C , NV_READ(0x2088)); + RAMFC_WR(UNK_50 , NV_READ(0x3300)); + +#if 0 /* no real idea which is PUT/GET in UNK_48.. */ + tmp = NV_READ(NV04_PFIFO_CACHE1_GET); + tmp |= (NV_READ(NV04_PFIFO_CACHE1_PUT) << 16); + RAMFC_WR(UNK_48 , tmp); +#endif + + return 0; +} + -- cgit v1.2.3 From acb710d1a59788a0205cd0daf0859864e683fbd2 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 24 Jun 2007 18:56:40 +1000 Subject: nouveau: NV4X PGRAPH engtab functions --- shared-core/nouveau_drv.h | 11 ++-- shared-core/nouveau_fifo.c | 24 +++++--- shared-core/nouveau_state.c | 4 ++ shared-core/nv40_graph.c | 142 +++++++++++++++++++++++++++----------------- 4 files changed, 111 insertions(+), 70 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 7c29a882..07c40107 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -285,11 +285,12 @@ extern void nv30_graph_takedown(drm_device_t *dev); extern int nv30_graph_context_create(drm_device_t *dev, int channel); /* nv40_graph.c */ -extern int nv40_graph_init(drm_device_t *dev); -extern void nv40_graph_takedown(drm_device_t *dev); -extern int nv40_graph_context_create(drm_device_t *dev, int channel); -extern void nv40_graph_context_save_current(drm_device_t *dev); -extern void nv40_graph_context_restore(drm_device_t *dev, int channel); +extern int nv40_graph_init(drm_device_t *); +extern void nv40_graph_takedown(drm_device_t *); +extern int nv40_graph_create_context(drm_device_t *, int channel); +extern void nv40_graph_destroy_context(drm_device_t *, int channel); +extern int nv40_graph_load_context(drm_device_t *, int channel); +extern int nv40_graph_save_context(drm_device_t *, int channel); /* nv04_mc.c */ extern int nv04_mc_init(drm_device_t *dev); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 50f094b9..527a71ae 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -473,18 +473,17 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) return ret; } break; - case NV_40: - case NV_44: - ret = nv40_graph_context_create(dev, channel); + default: + if (!engine->graph.create_context) { + DRM_ERROR("graph.create_context == NULL\n"); + return DRM_ERR(EINVAL); + } + ret = engine->graph.create_context(dev, channel); if (ret) { nouveau_fifo_free(dev, channel); return ret; } break; - default: - DRM_ERROR("grctx: unknown card type\n"); - nouveau_fifo_free(dev, channel); - return DRM_ERR(EINVAL); } /* Construct inital RAMFC for new channel */ @@ -532,6 +531,13 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) else nouveau_fifo_context_restore(dev, channel); + if (engine->graph.load_context) { + ret = engine->graph.load_context(dev, channel); + if (ret) { + nouveau_fifo_free(dev, channel); + return ret; + } + } else if (dev_priv->card_type >= NV_30) { uint32_t inst; @@ -594,8 +600,8 @@ void nouveau_fifo_free(drm_device_t* dev, int channel) } /* Cleanup PGRAPH state */ - if (dev_priv->card_type >= NV_40) - nouveau_instmem_free(dev, chan->ramin_grctx); + if (engine->graph.destroy_context) + engine->graph.destroy_context(dev, channel); else if (dev_priv->card_type >= NV_30) { } else if (dev_priv->card_type >= NV_20) { diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 42860e9a..d113f234 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -136,6 +136,10 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) engine->fb.takedown = nv40_fb_takedown; engine->graph.init = nv40_graph_init; engine->graph.takedown = nv40_graph_takedown; + engine->graph.create_context = nv40_graph_create_context; + engine->graph.destroy_context = nv40_graph_destroy_context; + engine->graph.load_context = nv40_graph_load_context; + engine->graph.save_context = nv40_graph_save_context; engine->fifo.init = nouveau_fifo_init; engine->fifo.takedown = nouveau_stub_takedown; engine->fifo.create_context = nv40_fifo_create_context; diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index 792734ed..245da54d 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -1,7 +1,32 @@ +/* + * Copyright (C) 2007 Ben Skeggs. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + #include "drmP.h" #include "drm.h" #include "nouveau_drv.h" -#include "nouveau_drm.h" /* The sizes are taken from the difference between the start of two * grctx addresses while running the nvidia driver. Probably slightly @@ -755,7 +780,7 @@ static void nv4e_graph_context_init(drm_device_t *dev, struct mem_block *ctx) } int -nv40_graph_context_create(drm_device_t *dev, int channel) +nv40_graph_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; @@ -808,89 +833,94 @@ nv40_graph_context_create(drm_device_t *dev, int channel) return 0; } -/* Save current context (from PGRAPH) into the channel's context - *XXX: fails sometimes, not sure why.. - */ void -nv40_graph_context_save_current(drm_device_t *dev) +nv40_graph_destroy_context(drm_device_t *dev, int channel) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; - uint32_t instance; - int i; - - NV_WRITE(NV04_PGRAPH_FIFO, 0); + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - instance = NV_READ(0x40032C) & 0xFFFFF; - if (!instance) { - NV_WRITE(NV04_PGRAPH_FIFO, 1); - return; + if (chan->ramin_grctx) { + nouveau_instmem_free(dev, chan->ramin_grctx); + chan->ramin_grctx = NULL; } +} + +static int +nv40_graph_transfer_context(drm_device_t *dev, uint32_t inst, int save) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t old_cp, tv = 1000; + int i; - NV_WRITE(0x400784, instance); - NV_WRITE(0x400310, NV_READ(0x400310) | 0x20); + old_cp = NV_READ(0x400784); + NV_WRITE(0x400784, inst); + NV_WRITE(0x400310, save ? 0x20 : 0x40); NV_WRITE(0x400304, 1); - /* just in case, we don't want to spin in-kernel forever */ - for (i=0; i<1000; i++) { - if (NV_READ(0x40030C) == 0) + + for (i = 0; i < tv; i++) { + if (NV_READ(0x40030c) == 0) break; } - if (i==1000) { - DRM_ERROR("failed to save current grctx to ramin\n"); - DRM_ERROR("instance = 0x%08x\n", NV_READ(0x40032C)); - DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C)); - NV_WRITE(NV04_PGRAPH_FIFO, 1); - return; + NV_WRITE(0x400784, old_cp); + + if (i == tv) { + DRM_ERROR("failed: inst=0x%08x save=%d\n", inst, save); + DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030c)); + return DRM_ERR(EBUSY); } - NV_WRITE(NV04_PGRAPH_FIFO, 1); + return 0; +} + +/* Save current context (from PGRAPH) into the channel's context + *XXX: fails sometimes, not sure why.. + */ +int +nv40_graph_save_context(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + uint32_t inst; + + if (!chan->ramin_grctx) + return DRM_ERR(EINVAL); + inst = nouveau_chip_instance_get(dev, chan->ramin_grctx); + + return nv40_graph_transfer_context(dev, inst, 1); } /* Restore the context for a specific channel into PGRAPH * XXX: fails sometimes.. not sure why */ -void -nv40_graph_context_restore(drm_device_t *dev, int channel) +int +nv40_graph_load_context(drm_device_t *dev, int channel) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; + drm_nouveau_private_t *dev_priv = dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - uint32_t instance; - int i; - - instance = nouveau_chip_instance_get(dev, chan->ramin_grctx); + uint32_t inst; + int ret; - NV_WRITE(NV04_PGRAPH_FIFO, 0); - NV_WRITE(0x400784, instance); - NV_WRITE(0x400310, NV_READ(0x400310) | 0x40); - NV_WRITE(0x400304, 1); - /* just in case, we don't want to spin in-kernel forever */ - for (i=0; i<1000; i++) { - if (NV_READ(0x40030C) == 0) - break; - } - if (i==1000) { - DRM_ERROR("failed to restore grctx for ch%d to PGRAPH\n", - channel); - DRM_ERROR("instance = 0x%08x\n", instance); - DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C)); - NV_WRITE(NV04_PGRAPH_FIFO, 1); - return; - } + if (!chan->ramin_grctx) + return DRM_ERR(EINVAL); + inst = nouveau_chip_instance_get(dev, chan->ramin_grctx); + ret = nv40_graph_transfer_context(dev, inst, 0); + if (ret) + return ret; /* 0x40032C, no idea of it's exact function. Could simply be a * record of the currently active PGRAPH context. It's currently * unknown as to what bit 24 does. The nv ddx has it set, so we will * set it here too. */ - NV_WRITE(0x40032C, instance | 0x01000000); + NV_WRITE(0x400784, inst); + NV_WRITE(0x40032C, inst | 0x01000000); /* 0x32E0 records the instance address of the active FIFO's PGRAPH * context. If at any time this doesn't match 0x40032C, you will * recieve PGRAPH_INTR_CONTEXT_SWITCH */ - NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, instance); - NV_WRITE(NV04_PGRAPH_FIFO, 1); + NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, inst); + return 0; } /* Some voodoo that makes context switching work without the binary driver -- cgit v1.2.3 From 05d86d950a10b77ffaa708e9d89b2a87c11fed01 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 24 Jun 2007 18:57:09 +1000 Subject: nouveau: NV04 PFIFO engtab functions --- shared-core/nouveau_drv.h | 6 +++ shared-core/nouveau_fifo.c | 32 ----------- shared-core/nouveau_reg.h | 5 +- shared-core/nouveau_state.c | 4 ++ shared-core/nv04_fifo.c | 126 ++++++++++++++++++++++++++++++++++++++++++++ shared-core/nv40_fifo.c | 4 +- 6 files changed, 142 insertions(+), 35 deletions(-) create mode 100644 shared-core/nv04_fifo.c (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 07c40107..3e32c2db 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -255,6 +255,12 @@ extern void nv10_fb_takedown(drm_device_t *dev); extern int nv40_fb_init(drm_device_t *dev); extern void nv40_fb_takedown(drm_device_t *dev); +/* nv04_fifo.c */ +extern int nv04_fifo_create_context(drm_device_t *dev, int channel); +extern void nv04_fifo_destroy_context(drm_device_t *dev, int channel); +extern int nv04_fifo_load_context(drm_device_t *dev, int channel); +extern int nv04_fifo_save_context(drm_device_t *dev, int channel); + /* nv40_fifo.c */ extern int nv40_fifo_create_context(drm_device_t *, int channel); extern void nv40_fifo_destroy_context(drm_device_t *, int channel); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 527a71ae..58408a1e 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -238,34 +238,6 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) return 0; } -#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV04_RAMFC_##offset, (val)) -static void nouveau_nv04_context_init(drm_device_t *dev, int channel) -{ - drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_object *cb_obj; - uint32_t fifoctx, ctx_size = 32; - int i; - - cb_obj = dev_priv->fifos[channel].cmdbuf_obj; - - fifoctx=NV_RAMIN+dev_priv->ramfc_offset+channel*ctx_size; - - // clear the fifo context - for(i=0;iinstance)); - - RAMFC_WR(DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 | -#ifdef __BIG_ENDIAN - NV_PFIFO_CACHE1_BIG_ENDIAN | -#endif - 0x00000000); -} -#undef RAMFC_WR - #define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV10_RAMFC_##offset, (val)) static void nouveau_nv10_context_init(drm_device_t *dev, int channel) { @@ -488,10 +460,6 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) /* Construct inital RAMFC for new channel */ switch (dev_priv->card_type) { - case NV_04: - case NV_05: - nouveau_nv04_context_init(dev, channel); - break; case NV_10: case NV_17: nouveau_nv10_context_init(dev, channel); diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 07c54a92..ba61f997 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -404,7 +404,7 @@ #define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C #define NV03_PFIFO_CACHE1_GET 0x00003270 #define NV04_PFIFO_CACHE1_ENGINE 0x00003280 -#define NV10_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0 +#define NV04_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0 #define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0 #define NV40_PFIFO_UNK32E4 0x000032E4 #define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8)) @@ -427,7 +427,10 @@ #define NV04_RAMFC_DMA_PUT 0x00 #define NV04_RAMFC_DMA_GET 0x04 #define NV04_RAMFC_DMA_INSTANCE 0x08 +#define NV04_RAMFC_DMA_STATE 0x0C #define NV04_RAMFC_DMA_FETCH 0x10 +#define NV04_RAMFC_ENGINE 0x14 +#define NV04_RAMFC_PULL1_ENGINE 0x18 #define NV10_RAMFC_DMA_PUT 0x00 #define NV10_RAMFC_DMA_GET 0x04 diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index d113f234..ed200e85 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -90,6 +90,10 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) engine->graph.takedown = nv04_graph_takedown; engine->fifo.init = nouveau_fifo_init; engine->fifo.takedown = nouveau_stub_takedown; + engine->fifo.create_context = nv04_fifo_create_context; + engine->fifo.destroy_context = nv04_fifo_destroy_context; + engine->fifo.load_context = nv04_fifo_load_context; + engine->fifo.save_context = nv04_fifo_save_context; break; case 0x10: engine->mc.init = nv04_mc_init; diff --git a/shared-core/nv04_fifo.c b/shared-core/nv04_fifo.c new file mode 100644 index 00000000..34a497b7 --- /dev/null +++ b/shared-core/nv04_fifo.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2007 Ben Skeggs. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "drmP.h" +#include "drm.h" +#include "nouveau_drv.h" + +#define NV04_RAMFC (NV_RAMIN + dev_priv->ramfc_offset) +#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV04_RAMFC_##offset, (val)) +#define RAMFC_RD(offset) NV_READ(fifoctx + NV04_RAMFC_##offset) +#define NV04_FIFO_CONTEXT_SIZE 32 + +int +nv04_fifo_create_context(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_object *pb = chan->cmdbuf_obj; + int fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE); + int i; + + if (!pb || !pb->instance) + return DRM_ERR(EINVAL); + + /* Clear RAMFC */ + for (i=0; ipushbuf_base); + RAMFC_WR(DMA_GET, chan->pushbuf_base); + RAMFC_WR(DMA_INSTANCE, nouveau_chip_instance_get(dev, pb->instance)); + /* NOTE: nvidia use TRIG_128/SIZE_128/MAX_REQS_8 */ + RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 | +#ifdef __BIG_ENDIAN + NV_PFIFO_CACHE1_BIG_ENDIAN | +#endif + 0)); + return 0; +} + +void +nv04_fifo_destroy_context(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t fifoctx; + int i; + + fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE); + for (i=0; idev_private; + int fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE); + uint32_t tmp; + + NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT)); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET)); + + tmp = RAMFC_RD(DMA_INSTANCE); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16); + + NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, RAMFC_RD(DMA_STATE)); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, RAMFC_RD(DMA_FETCH)); + NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, RAMFC_RD(ENGINE)); + NV_WRITE(NV04_PFIFO_CACHE1_PULL1, RAMFC_RD(PULL1_ENGINE)); + + /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */ + tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp); + + return 0; +} + +int +nv04_fifo_save_context(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + int fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE); + uint32_t tmp; + + RAMFC_WR(DMA_PUT, NV04_PFIFO_CACHE1_DMA_PUT); + RAMFC_WR(DMA_GET, NV04_PFIFO_CACHE1_DMA_GET); + + tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16; + tmp |= NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE); + RAMFC_WR(DMA_INSTANCE, tmp); + + RAMFC_WR(DMA_STATE, NV_READ(NV04_PFIFO_CACHE1_DMA_STATE)); + RAMFC_WR(DMA_FETCH, NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH)); + RAMFC_WR(ENGINE, NV_READ(NV04_PFIFO_CACHE1_ENGINE)); + RAMFC_WR(PULL1_ENGINE, NV_READ(NV04_PFIFO_CACHE1_PULL1)); + + return 0; +} + diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c index b67a7e58..9d7afbe5 100644 --- a/shared-core/nv40_fifo.c +++ b/shared-core/nv40_fifo.c @@ -91,7 +91,7 @@ nv40_fifo_load_context(drm_device_t *dev, int channel) NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT , RAMFC_RD(DMA_PUT)); NV_WRITE(NV10_PFIFO_CACHE1_REF_CNT , RAMFC_RD(REF_CNT)); NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE , RAMFC_RD(DMA_INSTANCE)); - NV_WRITE(NV10_PFIFO_CACHE1_DMA_DCOUNT , RAMFC_RD(DMA_DCOUNT)); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT , RAMFC_RD(DMA_DCOUNT)); NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE , RAMFC_RD(DMA_STATE)); /* No idea what 0x2058 is.. */ @@ -152,7 +152,7 @@ nv40_fifo_save_context(drm_device_t *dev, int channel) RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT)); RAMFC_WR(DMA_INSTANCE , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE)); - RAMFC_WR(DMA_DCOUNT , NV_READ(NV10_PFIFO_CACHE1_DMA_DCOUNT)); + RAMFC_WR(DMA_DCOUNT , NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT)); RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE)); tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH); -- cgit v1.2.3 From 341bc7820749024e09275de6e689b10c2908689a Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 24 Jun 2007 18:58:14 +1000 Subject: nouveau: NV1X/2X/3X PFIFO engtab functions Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC entry size. --- shared-core/nouveau_drv.h | 6 ++ shared-core/nouveau_fifo.c | 177 ++------------------------------------------ shared-core/nouveau_state.c | 19 +++++ shared-core/nv10_fifo.c | 143 +++++++++++++++++++++++++++++++++++ 4 files changed, 174 insertions(+), 171 deletions(-) create mode 100644 shared-core/nv10_fifo.c (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 3e32c2db..c7872c33 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -261,6 +261,12 @@ extern void nv04_fifo_destroy_context(drm_device_t *dev, int channel); extern int nv04_fifo_load_context(drm_device_t *dev, int channel); extern int nv04_fifo_save_context(drm_device_t *dev, int channel); +/* nv10_fifo.c */ +extern int nv10_fifo_create_context(drm_device_t *dev, int channel); +extern void nv10_fifo_destroy_context(drm_device_t *dev, int channel); +extern int nv10_fifo_load_context(drm_device_t *dev, int channel); +extern int nv10_fifo_save_context(drm_device_t *dev, int channel); + /* nv40_fifo.c */ extern int nv40_fifo_create_context(drm_device_t *, int channel); extern void nv40_fifo_destroy_context(drm_device_t *, int channel); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 58408a1e..0a883647 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -238,138 +238,6 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) return 0; } -#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV10_RAMFC_##offset, (val)) -static void nouveau_nv10_context_init(drm_device_t *dev, int channel) -{ - drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_object *cb_obj; - uint32_t fifoctx; - int ctx_size = nouveau_fifo_ctx_size(dev); - int i; - cb_obj = dev_priv->fifos[channel].cmdbuf_obj; - fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*ctx_size; - - for (i=0;iinstance)); - - RAMFC_WR(DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 | -#ifdef __BIG_ENDIAN - NV_PFIFO_CACHE1_BIG_ENDIAN | -#endif - 0x00000000); -} - -static void nouveau_nv30_context_init(drm_device_t *dev, int channel) -{ - drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - struct nouveau_object *cb_obj; - uint32_t fifoctx, grctx_inst, cb_inst, ctx_size = 64; - int i; - - cb_obj = dev_priv->fifos[channel].cmdbuf_obj; - cb_inst = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance); - grctx_inst = nouveau_chip_instance_get(dev, chan->ramin_grctx); - fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel * ctx_size; - - for (i = 0; i < ctx_size; i += 4) - NV_WRITE(fifoctx + i, 0); - - RAMFC_WR(REF_CNT, NV_READ(NV10_PFIFO_CACHE1_REF_CNT)); - RAMFC_WR(DMA_INSTANCE, cb_inst); - RAMFC_WR(DMA_STATE, NV_READ(NV04_PFIFO_CACHE1_DMA_STATE)); - RAMFC_WR(DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | -#ifdef __BIG_ENDIAN - NV_PFIFO_CACHE1_BIG_ENDIAN | -#endif - 0x00000000); - - RAMFC_WR(ENGINE, NV_READ(NV04_PFIFO_CACHE1_ENGINE)); - RAMFC_WR(PULL1_ENGINE, NV_READ(NV04_PFIFO_CACHE1_PULL1)); - RAMFC_WR(ACQUIRE_VALUE, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE)); - RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP)); - RAMFC_WR(ACQUIRE_TIMEOUT, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT)); - RAMFC_WR(SEMAPHORE, NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE)); -} - -#if 0 -static void nouveau_nv10_context_save(drm_device_t *dev) -{ - drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx; - int channel; - - channel = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1); - fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64; - - RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); - RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); - RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT)); - RAMFC_WR(DMA_INSTANCE , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE)); - RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE)); - RAMFC_WR(DMA_FETCH , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH)); - RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE)); - RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1)); - RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE)); - RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP)); - RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT)); - RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE)); - RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV10_PFIFO_CACHE1_DMA_SUBROUTINE)); -} -#endif -#undef RAMFC_WR - -/* This function should load values from RAMFC into PFIFO, but for now - * it just clobbers PFIFO with what nouveau_fifo_alloc used to setup - * unconditionally. - */ -static void -nouveau_fifo_context_restore(drm_device_t *dev, int channel) -{ - drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - uint32_t cb_inst; - - cb_inst = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance); - - // FIXME check if we need to refill the time quota with something like NV_WRITE(0x204C, 0x0003FFFF); - - if (dev_priv->card_type >= NV_40) - NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00010000|channel); - else - NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00000100|channel); - - NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0 /*RAMFC_DMA_PUT*/); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, 0 /*RAMFC_DMA_GET*/); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, cb_inst); - NV_WRITE(NV04_PFIFO_SIZE , 0x0000FFFF); - NV_WRITE(NV04_PFIFO_CACHE1_HASH, 0x0000FFFF); - - NV_WRITE(NV04_PFIFO_CACHE0_PULL1, 0x00000001); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, 0x00000000); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000); - NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, 0x00000000); - - NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 | -#ifdef __BIG_ENDIAN - NV_PFIFO_CACHE1_BIG_ENDIAN | -#endif - 0x00000000); -} - /* allocates and initializes a fifo for user space consumption */ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) { @@ -459,28 +327,10 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) } /* Construct inital RAMFC for new channel */ - switch (dev_priv->card_type) { - case NV_10: - case NV_17: - nouveau_nv10_context_init(dev, channel); - break; - case NV_20: - nouveau_nv10_context_init(dev, channel); - break; - case NV_30: - nouveau_nv30_context_init(dev, channel); - break; - default: - if (!engine->fifo.create_context) { - DRM_ERROR("fifo.create_context == NULL\n"); - return DRM_ERR(EINVAL); - } - - ret = engine->fifo.create_context(dev, channel); - if (ret) { - nouveau_fifo_free(dev, channel); - return ret; - } + ret = engine->fifo.create_context(dev, channel); + if (ret) { + nouveau_fifo_free(dev, channel); + return ret; } /* enable the fifo dma operation */ @@ -494,10 +344,7 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) * other case, the GPU will handle this when it switches contexts. */ if (dev_priv->fifo_alloc_count == 0) { - if (engine->fifo.load_context) - engine->fifo.load_context(dev, channel); - else - nouveau_fifo_context_restore(dev, channel); + engine->fifo.load_context(dev, channel); if (engine->graph.load_context) { ret = engine->graph.load_context(dev, channel); @@ -553,19 +400,7 @@ void nouveau_fifo_free(drm_device_t* dev, int channel) NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<fifo.destroy_context) - engine->fifo.destroy_context(dev, channel); - else { - for (i=0;iramfc_offset + - channel*ctx_size + i)); - NV_WRITE(NV_RAMIN + dev_priv->ramfc_offset + - channel*ctx_size + i, 0); - } - } + engine->fifo.destroy_context(dev, channel); /* Cleanup PGRAPH state */ if (engine->graph.destroy_context) diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index ed200e85..55d10b8c 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -106,6 +106,17 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) engine->graph.takedown = nv10_graph_takedown; engine->fifo.init = nouveau_fifo_init; engine->fifo.takedown = nouveau_stub_takedown; + if (dev_priv->chipset < 0x17) { + engine->fifo.create_context = nv04_fifo_create_context; + engine->fifo.destroy_context = nv04_fifo_destroy_context; + engine->fifo.load_context = nv04_fifo_load_context; + engine->fifo.save_context = nv04_fifo_save_context; + } else { + engine->fifo.create_context = nv10_fifo_create_context; + engine->fifo.destroy_context = nv10_fifo_destroy_context; + engine->fifo.load_context = nv10_fifo_load_context; + engine->fifo.save_context = nv10_fifo_save_context; + } break; case 0x20: engine->mc.init = nv04_mc_init; @@ -118,6 +129,10 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) engine->graph.takedown = nv20_graph_takedown; engine->fifo.init = nouveau_fifo_init; engine->fifo.takedown = nouveau_stub_takedown; + engine->fifo.create_context = nv10_fifo_create_context; + engine->fifo.destroy_context = nv10_fifo_destroy_context; + engine->fifo.load_context = nv10_fifo_load_context; + engine->fifo.save_context = nv10_fifo_save_context; break; case 0x30: engine->mc.init = nv04_mc_init; @@ -130,6 +145,10 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) engine->graph.takedown = nv30_graph_takedown; engine->fifo.init = nouveau_fifo_init; engine->fifo.takedown = nouveau_stub_takedown; + engine->fifo.create_context = nv10_fifo_create_context; + engine->fifo.destroy_context = nv10_fifo_destroy_context; + engine->fifo.load_context = nv10_fifo_load_context; + engine->fifo.save_context = nv10_fifo_save_context; break; case 0x40: engine->mc.init = nv40_mc_init; diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c new file mode 100644 index 00000000..8dad45aa --- /dev/null +++ b/shared-core/nv10_fifo.c @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2007 Ben Skeggs. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "drmP.h" +#include "drm.h" +#include "nouveau_drv.h" + +#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV10_RAMFC_##offset, (val)) +#define RAMFC_RD(offset) NV_READ (fifoctx + NV10_RAMFC_##offset) +#define NV10_FIFO_CONTEXT_SIZE 64 + +int +nv10_fifo_create_context(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + uint32_t fifoctx, pushbuf; + int i; + + pushbuf = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance); + + fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64; + for (i=0; ipushbuf_base); + RAMFC_WR(DMA_GET , chan->pushbuf_base); + RAMFC_WR(DMA_INSTANCE , pushbuf); + RAMFC_WR(DMA_FETCH , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | +#ifdef __BIG_ENDIAN + NV_PFIFO_CACHE1_BIG_ENDIAN | +#endif + 0); + + return 0; +} + +void +nv10_fifo_destroy_context(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t fifoctx; + int i; + + fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64; + for (i=0; idev_private; + uint32_t fifoctx; + uint32_t tmp; + + fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64; + + NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00000100 | channel); + + NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET)); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT , RAMFC_RD(DMA_PUT)); + NV_WRITE(NV10_PFIFO_CACHE1_REF_CNT , RAMFC_RD(REF_CNT)); + + tmp = RAMFC_RD(DMA_INSTANCE); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE , tmp & 0xFFFF); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT , tmp >> 16); + + NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE , RAMFC_RD(DMA_STATE)); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH , RAMFC_RD(DMA_FETCH)); + NV_WRITE(NV04_PFIFO_CACHE1_ENGINE , RAMFC_RD(ENGINE)); + NV_WRITE(NV04_PFIFO_CACHE1_PULL1 , RAMFC_RD(PULL1_ENGINE)); + NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE , RAMFC_RD(ACQUIRE_VALUE)); + NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, RAMFC_RD(ACQUIRE_TIMESTAMP)); + NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT , RAMFC_RD(ACQUIRE_TIMEOUT)); + NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE , RAMFC_RD(SEMAPHORE)); + NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE , RAMFC_RD(DMA_SUBROUTINE)); + + /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */ + tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp); + + return 0; +} + +int +nv10_fifo_save_context(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t fifoctx; + uint32_t tmp; + + fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64; + + RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); + RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); + RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT)); + + tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE) & 0xFFFF; + tmp |= (NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16); + RAMFC_WR(DMA_INSTANCE , tmp); + + RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE)); + RAMFC_WR(DMA_FETCH , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH)); + RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE)); + RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1)); + RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE)); + RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP)); + RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT)); + RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE)); + RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); + + return 0; +} + -- cgit v1.2.3 From 5d55b0655cb480b7d6ab4cf2467dac6dc6d8df25 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 24 Jun 2007 18:58:38 +1000 Subject: nouveau: NV3X PGRAPH engtab functions --- shared-core/nouveau_drv.h | 7 +++-- shared-core/nouveau_fifo.c | 9 ------- shared-core/nouveau_state.c | 4 +++ shared-core/nv30_graph.c | 66 ++++++++++++++++++++++++++++++++++++++++++++- 4 files changed, 74 insertions(+), 12 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index c7872c33..a4a37648 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -292,9 +292,12 @@ extern void nv20_graph_takedown(drm_device_t *dev); extern int nv20_graph_context_create(drm_device_t *dev, int channel); /* nv30_graph.c */ -extern int nv30_graph_init(drm_device_t *dev); +extern int nv30_graph_init(drm_device_t *dev); extern void nv30_graph_takedown(drm_device_t *dev); -extern int nv30_graph_context_create(drm_device_t *dev, int channel); +extern int nv30_graph_create_context(drm_device_t *, int channel); +extern void nv30_graph_destroy_context(drm_device_t *, int channel); +extern int nv30_graph_load_context(drm_device_t *, int channel); +extern int nv30_graph_save_context(drm_device_t *, int channel); /* nv40_graph.c */ extern int nv40_graph_init(drm_device_t *); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 0a883647..1ef5a425 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -306,13 +306,6 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) return ret; } break; - case NV_30: - ret = nv30_graph_context_create(dev, channel); - if (ret) { - nouveau_fifo_free(dev, channel); - return ret; - } - break; default: if (!engine->graph.create_context) { DRM_ERROR("graph.create_context == NULL\n"); @@ -388,8 +381,6 @@ void nouveau_fifo_free(drm_device_t* dev, int channel) drm_nouveau_private_t *dev_priv = dev->dev_private; nouveau_engine_func_t *engine = &dev_priv->Engine; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - int i; - int ctx_size = nouveau_fifo_ctx_size(dev); chan->used = 0; DRM_INFO("%s: freeing fifo %d\n", __func__, channel); diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 55d10b8c..a997b075 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -143,6 +143,10 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) engine->fb.takedown = nv10_fb_takedown; engine->graph.init = nv30_graph_init; engine->graph.takedown = nv30_graph_takedown; + engine->graph.create_context = nv30_graph_create_context; + engine->graph.destroy_context = nv30_graph_destroy_context; + engine->graph.load_context = nv30_graph_load_context; + engine->graph.save_context = nv30_graph_save_context; engine->fifo.init = nouveau_fifo_init; engine->fifo.takedown = nouveau_stub_takedown; engine->fifo.create_context = nv10_fifo_create_context; diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index f4faadd8..9f064a0a 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -100,7 +100,7 @@ static void nv30_graph_context_init(drm_device_t *dev, struct mem_block *ctx) } -int nv30_graph_context_create(drm_device_t *dev, int channel) +int nv30_graph_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; @@ -132,6 +132,70 @@ int nv30_graph_context_create(drm_device_t *dev, int channel) return 0; } +void nv30_graph_destroy_context(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = + (drm_nouveau_private_t *)dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + + if (chan->ramin_grctx) { + nouveau_instmem_free(dev, chan->ramin_grctx); + chan->ramin_grctx = NULL; + } + + INSTANCE_WR(dev_priv->ctx_table, channel, 0); +} + +static int +nouveau_graph_wait_idle(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + int tv = 1000; + + while (tv--) { + if (NV_READ(0x400700) == 0) + break; + } + + if (NV_READ(0x400700)) { + DRM_ERROR("timeout!\n"); + return DRM_ERR(EBUSY); + } + return 0; +} + +int nv30_graph_load_context(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + uint32_t inst; + + if (!chan->ramin_grctx) + return DRM_ERR(EINVAL); + inst = nouveau_chip_instance_get(dev, chan->ramin_grctx); + + NV_WRITE(0x400784, inst); + NV_WRITE(0x400788, 1); + + return nouveau_graph_wait_idle(dev); +} + +int nv30_graph_save_context(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + uint32_t inst; + + if (!chan->ramin_grctx) + return DRM_ERR(EINVAL); + inst = nouveau_chip_instance_get(dev, chan->ramin_grctx); + + NV_WRITE(0x400784, inst); + NV_WRITE(0x400788, 2); + + return nouveau_graph_wait_idle(dev); +} + int nv30_graph_init(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = -- cgit v1.2.3 From 5f05cd7086c54bccf1c2f0b003b78a08dc55472a Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 24 Jun 2007 19:00:26 +1000 Subject: nouveau: NV04/NV10/NV20 PGRAPH engtab functions NV04/NV10 load_context()/save_context() are stubs. I don't know enough about how they work to implement them sanely. The "old" context_switch() code remains hooked up, so it shouldn't break anything. NV20 will probably break if load_context() works. No inital context values are filled in, so when the first channel is created PGRAPH will probably end up having its state zeroed. Some setup from nv20_graph_init() will probably need to be moved to the per-channel context setup. --- shared-core/nouveau_drv.h | 21 +++++++++++++++------ shared-core/nouveau_fifo.c | 32 ++++---------------------------- shared-core/nouveau_state.c | 12 ++++++++++++ shared-core/nv04_graph.c | 17 ++++++++++++++++- shared-core/nv10_graph.c | 17 ++++++++++++++++- shared-core/nv20_graph.c | 33 +++++++++++++++++++++++---------- 6 files changed, 86 insertions(+), 46 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index a4a37648..b3122d8a 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -275,21 +275,30 @@ extern int nv40_fifo_save_context(drm_device_t *, int channel); /* nv04_graph.c */ extern void nouveau_nv04_context_switch(drm_device_t *dev); -extern int nv04_graph_init(drm_device_t *dev); +extern int nv04_graph_init(drm_device_t *dev); extern void nv04_graph_takedown(drm_device_t *dev); -extern int nv04_graph_context_create(drm_device_t *dev, int channel); +extern int nv04_graph_create_context(drm_device_t *dev, int channel); +extern void nv04_graph_destroy_context(drm_device_t *dev, int channel); +extern int nv04_graph_load_context(drm_device_t *dev, int channel); +extern int nv04_graph_save_context(drm_device_t *dev, int channel); /* nv10_graph.c */ extern void nouveau_nv10_context_switch(drm_device_t *dev); -extern int nv10_graph_init(drm_device_t *dev); +extern int nv10_graph_init(drm_device_t *dev); extern void nv10_graph_takedown(drm_device_t *dev); -extern int nv10_graph_context_create(drm_device_t *dev, int channel); +extern int nv10_graph_create_context(drm_device_t *dev, int channel); +extern void nv10_graph_destroy_context(drm_device_t *dev, int channel); +extern int nv10_graph_load_context(drm_device_t *dev, int channel); +extern int nv10_graph_save_context(drm_device_t *dev, int channel); /* nv20_graph.c */ extern void nouveau_nv20_context_switch(drm_device_t *dev); -extern int nv20_graph_init(drm_device_t *dev); +extern int nv20_graph_init(drm_device_t *dev); extern void nv20_graph_takedown(drm_device_t *dev); -extern int nv20_graph_context_create(drm_device_t *dev, int channel); +extern int nv20_graph_create_context(drm_device_t *dev, int channel); +extern void nv20_graph_destroy_context(drm_device_t *dev, int channel); +extern int nv20_graph_load_context(drm_device_t *dev, int channel); +extern int nv20_graph_save_context(drm_device_t *dev, int channel); /* nv30_graph.c */ extern int nv30_graph_init(drm_device_t *dev); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 1ef5a425..b47d4e0c 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -289,34 +289,10 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000); /* Create a graphics context for new channel */ - switch(dev_priv->card_type) - { - case NV_04: - case NV_05: - nv04_graph_context_create(dev, channel); - break; - case NV_10: - case NV_17: - nv10_graph_context_create(dev, channel); - break; - case NV_20: - ret = nv20_graph_context_create(dev, channel); - if (ret) { - nouveau_fifo_free(dev, channel); - return ret; - } - break; - default: - if (!engine->graph.create_context) { - DRM_ERROR("graph.create_context == NULL\n"); - return DRM_ERR(EINVAL); - } - ret = engine->graph.create_context(dev, channel); - if (ret) { - nouveau_fifo_free(dev, channel); - return ret; - } - break; + ret = engine->graph.create_context(dev, channel); + if (ret) { + nouveau_fifo_free(dev, channel); + return ret; } /* Construct inital RAMFC for new channel */ diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index a997b075..b3562e2f 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -88,6 +88,10 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) engine->fb.takedown = nv04_fb_takedown; engine->graph.init = nv04_graph_init; engine->graph.takedown = nv04_graph_takedown; + engine->graph.create_context = nv04_graph_create_context; + engine->graph.destroy_context = nv04_graph_destroy_context; + engine->graph.load_context = nv04_graph_load_context; + engine->graph.save_context = nv04_graph_save_context; engine->fifo.init = nouveau_fifo_init; engine->fifo.takedown = nouveau_stub_takedown; engine->fifo.create_context = nv04_fifo_create_context; @@ -104,6 +108,10 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) engine->fb.takedown = nv10_fb_takedown; engine->graph.init = nv10_graph_init; engine->graph.takedown = nv10_graph_takedown; + engine->graph.create_context = nv10_graph_create_context; + engine->graph.destroy_context = nv10_graph_destroy_context; + engine->graph.load_context = nv10_graph_load_context; + engine->graph.save_context = nv10_graph_save_context; engine->fifo.init = nouveau_fifo_init; engine->fifo.takedown = nouveau_stub_takedown; if (dev_priv->chipset < 0x17) { @@ -127,6 +135,10 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) engine->fb.takedown = nv10_fb_takedown; engine->graph.init = nv20_graph_init; engine->graph.takedown = nv20_graph_takedown; + engine->graph.create_context = nv20_graph_create_context; + engine->graph.destroy_context = nv20_graph_destroy_context; + engine->graph.load_context = nv20_graph_load_context; + engine->graph.save_context = nv20_graph_save_context; engine->fifo.init = nouveau_fifo_init; engine->fifo.takedown = nouveau_stub_takedown; engine->fifo.create_context = nv10_fifo_create_context; diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c index 0cd4d3b8..1aaae33c 100644 --- a/shared-core/nv04_graph.c +++ b/shared-core/nv04_graph.c @@ -336,7 +336,7 @@ void nouveau_nv04_context_switch(drm_device_t *dev) NV_WRITE(NV04_PGRAPH_FIFO,0x1); } -int nv04_graph_context_create(drm_device_t *dev, int channel) { +int nv04_graph_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; DRM_DEBUG("nv04_graph_context_create %d\n", channel); @@ -351,6 +351,21 @@ int nv04_graph_context_create(drm_device_t *dev, int channel) { return 0; } +void nv04_graph_destroy_context(drm_device_t *dev, int channel) +{ +} + +int nv04_graph_load_context(drm_device_t *dev, int channel) +{ + DRM_ERROR("stub!\n"); + return 0; +} + +int nv04_graph_save_context(drm_device_t *dev, int channel) +{ + DRM_ERROR("stub!\n"); + return 0; +} int nv04_graph_init(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index fb189709..d1fe0a54 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -611,7 +611,7 @@ void nouveau_nv10_context_switch(drm_device_t *dev) if (offset > 0) \ fifo->pgraph_ctx[offset] = val; \ } while (0) -int nv10_graph_context_create(drm_device_t *dev, int channel) { +int nv10_graph_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; struct nouveau_fifo *fifo = &dev_priv->fifos[channel]; uint32_t tmp, vramsz; @@ -663,6 +663,21 @@ int nv10_graph_context_create(drm_device_t *dev, int channel) { return 0; } +void nv10_graph_destroy_context(drm_device_t *dev, int channel) +{ +} + +int nv10_graph_load_context(drm_device_t *dev, int channel) +{ + DRM_ERROR("stub!\n"); + return 0; +} + +int nv10_graph_save_context(drm_device_t *dev, int channel) +{ + DRM_ERROR("stub!\n"); + return 0; +} int nv10_graph_init(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 7190fc84..1b8a6727 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -29,7 +29,7 @@ #define NV20_GRCTX_SIZE (3529*4) -int nv20_graph_context_create(drm_device_t *dev, int channel) { +int nv20_graph_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; @@ -47,10 +47,21 @@ int nv20_graph_context_create(drm_device_t *dev, int channel) { INSTANCE_WR(chan->ramin_grctx, 10, channel << 24); /* CTX_USER */ INSTANCE_WR(dev_priv->ctx_table, channel, nouveau_chip_instance_get(dev, chan->ramin_grctx)); - return 0; } +void nv20_graph_destroy_context(drm_device_t *dev, int channel) { + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + + if (chan->ramin_grctx) { + nouveau_instmem_free(dev, chan->ramin_grctx); + chan->ramin_grctx = NULL; + } + + INSTANCE_WR(dev_priv->ctx_table, channel, 0); +} + static void nv20_graph_rdi(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; @@ -65,40 +76,42 @@ static void nv20_graph_rdi(drm_device_t *dev) { /* Save current context (from PGRAPH) into the channel's context */ -static void nv20_graph_context_save_current(drm_device_t *dev, int channel) { +int nv20_graph_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; uint32_t instance; instance = INSTANCE_RD(dev_priv->ctx_table, channel); if (!instance) { - return; + return DRM_ERR(EINVAL); } if (instance != nouveau_chip_instance_get(dev, dev_priv->fifos[channel].ramin_grctx)) - DRM_ERROR("nv20_graph_context_save_current : bad instance\n"); + DRM_ERROR("nv20_graph_save_context : bad instance\n"); NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance); NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 2 /* save ctx */); + return 0; } /* Restore the context for a specific channel into PGRAPH */ -static void nv20_graph_context_restore(drm_device_t *dev, int channel) { +int nv20_graph_load_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; uint32_t instance; instance = INSTANCE_RD(dev_priv->ctx_table, channel); if (!instance) { - return; + return DRM_ERR(EINVAL); } if (instance != nouveau_chip_instance_get(dev, dev_priv->fifos[channel].ramin_grctx)) - DRM_ERROR("nv20_graph_context_restore_current : bad instance\n"); + DRM_ERROR("nv20_graph_load_context_current : bad instance\n"); NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24); NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance); NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 1 /* restore ctx */); + return 0; } void nouveau_nv20_context_switch(drm_device_t *dev) @@ -113,13 +126,13 @@ void nouveau_nv20_context_switch(drm_device_t *dev) NV_WRITE(NV04_PGRAPH_FIFO,0x0); - nv20_graph_context_save_current(dev, channel_old); + nv20_graph_save_context(dev, channel_old); nouveau_wait_for_idle(dev); NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000000); - nv20_graph_context_restore(dev, channel); + nv20_graph_load_context(dev, channel); nouveau_wait_for_idle(dev); -- cgit v1.2.3 From 3dfc13e2da10e86051c7106feb5683542907acdc Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 24 Jun 2007 19:00:44 +1000 Subject: nouveau: kill some dead code --- shared-core/nouveau_fifo.c | 41 +++++++++++------------------------------ 1 file changed, 11 insertions(+), 30 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index b47d4e0c..3c07b0da 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -313,27 +313,16 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) * other case, the GPU will handle this when it switches contexts. */ if (dev_priv->fifo_alloc_count == 0) { - engine->fifo.load_context(dev, channel); - - if (engine->graph.load_context) { - ret = engine->graph.load_context(dev, channel); - if (ret) { - nouveau_fifo_free(dev, channel); - return ret; - } - } else - if (dev_priv->card_type >= NV_30) { - uint32_t inst; - - inst = nouveau_chip_instance_get(dev, - chan->ramin_grctx); - - /* see comments in nv40_graph_context_restore() */ - NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, inst); - if (dev_priv->card_type >= NV_40) { - NV_WRITE(0x40032C, inst | 0x01000000); - NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, inst); - } + ret = engine->fifo.load_context(dev, channel); + if (ret) { + nouveau_fifo_free(dev, channel); + return ret; + } + + ret = engine->graph.load_context(dev, channel); + if (ret) { + nouveau_fifo_free(dev, channel); + return ret; } } @@ -370,15 +359,7 @@ void nouveau_fifo_free(drm_device_t* dev, int channel) engine->fifo.destroy_context(dev, channel); /* Cleanup PGRAPH state */ - if (engine->graph.destroy_context) - engine->graph.destroy_context(dev, channel); - else if (dev_priv->card_type >= NV_30) { - } - else if (dev_priv->card_type >= NV_20) { - /* clear ctx table */ - INSTANCE_WR(dev_priv->ctx_table, channel, 0); - nouveau_instmem_free(dev, chan->ramin_grctx); - } + engine->graph.destroy_context(dev, channel); /* reenable the fifo caches */ NV_WRITE(NV03_PFIFO_CACHES, 0x00000001); -- cgit v1.2.3 From 9f617522d9cb8cd33e588d12a13f427dbe5171c2 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 25 Jun 2007 01:57:57 +1000 Subject: nouveau: NV49/NV4B PGRAPH setup from jb17bsome and stephan_2303 --- shared-core/nouveau_fifo.c | 2 + shared-core/nv40_graph.c | 497 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 494 insertions(+), 5 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 3c07b0da..1a06f913 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -83,6 +83,8 @@ static int nouveau_fifo_instmem_configure(drm_device_t *dev) case NV_50: case NV_40: NV_WRITE(NV40_PFIFO_RAMFC, 0x30002); + if((dev_priv->chipset == 0x49) || (dev_priv->chipset == 0x4b)) + NV_WRITE(0x2230,0x00000001); break; case NV_44: NV_WRITE(NV40_PFIFO_RAMFC, ((nouveau_mem_fb_amount(dev)-512*1024+dev_priv->ramfc_offset)>>16) | diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index 245da54d..acd0cb0f 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -36,7 +36,9 @@ #define NV40_GRCTX_SIZE (175*1024) #define NV43_GRCTX_SIZE (70*1024) #define NV46_GRCTX_SIZE (70*1024) /* probably ~64KiB */ +#define NV49_GRCTX_SIZE (164640) #define NV4A_GRCTX_SIZE (64*1024) +#define NV4B_GRCTX_SIZE (164640) #define NV4C_GRCTX_SIZE (25*1024) #define NV4E_GRCTX_SIZE (25*1024) @@ -44,7 +46,8 @@ * contexts are taken from dumps just after the 3D object is * created. */ -static void nv40_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +static void +nv40_graph_context_init(drm_device_t *dev, struct mem_block *ctx) { drm_nouveau_private_t *dev_priv = dev->dev_private; int i; @@ -300,7 +303,8 @@ nv43_graph_context_init(drm_device_t *dev, struct mem_block *ctx) INSTANCE_WR(ctx, i/4, 0x3f800000); }; -static void nv46_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +static void +nv46_graph_context_init(drm_device_t *dev, struct mem_block *ctx) { drm_nouveau_private_t *dev_priv = dev->dev_private; int i; @@ -450,7 +454,231 @@ static void nv46_graph_context_init(drm_device_t *dev, struct mem_block *ctx) INSTANCE_WR(ctx, i/4, 0x3f800000); } -static void nv4a_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +static void +nv49_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + int i; + + INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx)); + INSTANCE_WR(ctx, 0x00004/4, 0x0000c040); + INSTANCE_WR(ctx, 0x00008/4, 0x0000c040); + INSTANCE_WR(ctx, 0x0000c/4, 0x0000c040); + INSTANCE_WR(ctx, 0x00010/4, 0x0000c040); + INSTANCE_WR(ctx, 0x00014/4, 0x0000c040); + INSTANCE_WR(ctx, 0x00018/4, 0x0000c040); + INSTANCE_WR(ctx, 0x0001c/4, 0x0000c040); + INSTANCE_WR(ctx, 0x00020/4, 0x0000c040); + INSTANCE_WR(ctx, 0x000c4/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x000c8/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x000d0/4, 0x00000001); + INSTANCE_WR(ctx, 0x001bc/4, 0x20010001); + INSTANCE_WR(ctx, 0x001c0/4, 0x0f73ef00); + INSTANCE_WR(ctx, 0x001c8/4, 0x02008821); + INSTANCE_WR(ctx, 0x00218/4, 0x00000040); + INSTANCE_WR(ctx, 0x0021c/4, 0x00000040); + INSTANCE_WR(ctx, 0x00220/4, 0x00000040); + INSTANCE_WR(ctx, 0x00228/4, 0x00000040); + INSTANCE_WR(ctx, 0x00234/4, 0x80000000); + INSTANCE_WR(ctx, 0x00238/4, 0x80000000); + INSTANCE_WR(ctx, 0x0023c/4, 0x80000000); + INSTANCE_WR(ctx, 0x00240/4, 0x80000000); + INSTANCE_WR(ctx, 0x00244/4, 0x80000000); + INSTANCE_WR(ctx, 0x00248/4, 0x80000000); + INSTANCE_WR(ctx, 0x0024c/4, 0x80000000); + INSTANCE_WR(ctx, 0x00250/4, 0x80000000); + INSTANCE_WR(ctx, 0x00270/4, 0x0b0b0b0c); + INSTANCE_WR(ctx, 0x003e0/4, 0x00040000); + INSTANCE_WR(ctx, 0x003f0/4, 0x55555555); + INSTANCE_WR(ctx, 0x003f4/4, 0x55555555); + INSTANCE_WR(ctx, 0x003f8/4, 0x55555555); + INSTANCE_WR(ctx, 0x003fc/4, 0x55555555); + INSTANCE_WR(ctx, 0x00428/4, 0x00000008); + INSTANCE_WR(ctx, 0x0043c/4, 0x00001010); + INSTANCE_WR(ctx, 0x00460/4, 0x00000111); + INSTANCE_WR(ctx, 0x00464/4, 0x00000111); + INSTANCE_WR(ctx, 0x00468/4, 0x00000111); + INSTANCE_WR(ctx, 0x0046c/4, 0x00000111); + INSTANCE_WR(ctx, 0x00470/4, 0x00000111); + INSTANCE_WR(ctx, 0x00474/4, 0x00000111); + INSTANCE_WR(ctx, 0x00478/4, 0x00000111); + INSTANCE_WR(ctx, 0x0047c/4, 0x00000111); + INSTANCE_WR(ctx, 0x00480/4, 0x00000111); + INSTANCE_WR(ctx, 0x00484/4, 0x00000111); + INSTANCE_WR(ctx, 0x00488/4, 0x00000111); + INSTANCE_WR(ctx, 0x0048c/4, 0x00000111); + INSTANCE_WR(ctx, 0x00490/4, 0x00000111); + INSTANCE_WR(ctx, 0x00494/4, 0x00000111); + INSTANCE_WR(ctx, 0x00498/4, 0x00000111); + INSTANCE_WR(ctx, 0x0049c/4, 0x00000111); + INSTANCE_WR(ctx, 0x004f4/4, 0x00000111); + INSTANCE_WR(ctx, 0x004f8/4, 0x00080060); + INSTANCE_WR(ctx, 0x00514/4, 0x00000080); + INSTANCE_WR(ctx, 0x00518/4, 0xffff0000); + INSTANCE_WR(ctx, 0x0051c/4, 0x00000001); + INSTANCE_WR(ctx, 0x00530/4, 0x46400000); + INSTANCE_WR(ctx, 0x00540/4, 0xffff0000); + INSTANCE_WR(ctx, 0x00544/4, 0x88888888); + INSTANCE_WR(ctx, 0x00548/4, 0x88888888); + INSTANCE_WR(ctx, 0x0054c/4, 0x88888888); + INSTANCE_WR(ctx, 0x00550/4, 0x88888888); + INSTANCE_WR(ctx, 0x00554/4, 0x88888888); + INSTANCE_WR(ctx, 0x00558/4, 0x88888888); + INSTANCE_WR(ctx, 0x0055c/4, 0x88888888); + INSTANCE_WR(ctx, 0x00560/4, 0x88888888); + INSTANCE_WR(ctx, 0x00564/4, 0x88888888); + INSTANCE_WR(ctx, 0x00568/4, 0x88888888); + INSTANCE_WR(ctx, 0x0056c/4, 0x88888888); + INSTANCE_WR(ctx, 0x00570/4, 0x88888888); + INSTANCE_WR(ctx, 0x00574/4, 0x88888888); + INSTANCE_WR(ctx, 0x00578/4, 0x88888888); + INSTANCE_WR(ctx, 0x0057c/4, 0x88888888); + INSTANCE_WR(ctx, 0x00580/4, 0x88888888); + INSTANCE_WR(ctx, 0x00594/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x00598/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x005a0/4, 0x00011100); + INSTANCE_WR(ctx, 0x005bc/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005c0/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005c4/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005c8/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005cc/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005d0/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005d4/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005d8/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005dc/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005e0/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005e4/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005e8/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005ec/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005f0/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005f4/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005f8/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x00604/4, 0x4b7fffff); + INSTANCE_WR(ctx, 0x0062c/4, 0x30201000); + INSTANCE_WR(ctx, 0x00630/4, 0x70605040); + INSTANCE_WR(ctx, 0x00634/4, 0xb8a89888); + INSTANCE_WR(ctx, 0x00638/4, 0xf8e8d8c8); + INSTANCE_WR(ctx, 0x0064c/4, 0x40100000); + INSTANCE_WR(ctx, 0x00668/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x0069c/4, 0x435185d6); + INSTANCE_WR(ctx, 0x006a0/4, 0x2155b699); + INSTANCE_WR(ctx, 0x006a4/4, 0xfedcba98); + INSTANCE_WR(ctx, 0x006a8/4, 0x00000098); + INSTANCE_WR(ctx, 0x006b8/4, 0xffffffff); + INSTANCE_WR(ctx, 0x006bc/4, 0x00ff7000); + INSTANCE_WR(ctx, 0x006c0/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x006d0/4, 0x00ff0000); + INSTANCE_WR(ctx, 0x0070c/4, 0x00ffff00); + for (i=0x00750; i<=0x0078c; i+=4) + INSTANCE_WR(ctx, i/4, 0x00018488); + for (i=0x00790; i<=0x007cc; i+=4) + INSTANCE_WR(ctx, i/4, 0x00028202); + for (i=0x00810; i<=0x0084c; i+=4) + INSTANCE_WR(ctx, i/4, 0x0000aae4); + for (i=0x00850; i<=0x0088c; i+=4) + INSTANCE_WR(ctx, i/4, 0x01012000); + for (i=0x00890; i<=0x008cc; i+=4) + INSTANCE_WR(ctx, i/4, 0x00080008); + for (i=0x00910; i<=0x0094c; i+=4) + INSTANCE_WR(ctx, i/4, 0x00100008); + for (i=0x009a0; i<=0x009ac; i+=4) + INSTANCE_WR(ctx, i/4, 0x0001bc80); + for (i=0x009b0; i<=0x009bc; i+=4) + INSTANCE_WR(ctx, i/4, 0x00000202); + for (i=0x009d0; i<=0x009dc; i+=4) + INSTANCE_WR(ctx, i/4, 0x00000008); + for (i=0x009f0; i<=0x009fc; i+=4) + INSTANCE_WR(ctx, i/4, 0x00080008); + INSTANCE_WR(ctx, 0x00a10/4, 0x00000002); + INSTANCE_WR(ctx, 0x00a44/4, 0x00000421); + INSTANCE_WR(ctx, 0x00a48/4, 0x030c30c3); + INSTANCE_WR(ctx, 0x00a54/4, 0x3e020200); + INSTANCE_WR(ctx, 0x00a58/4, 0x00ffffff); + INSTANCE_WR(ctx, 0x00a5c/4, 0x20103f00); + INSTANCE_WR(ctx, 0x00a68/4, 0x00040000); + INSTANCE_WR(ctx, 0x00aa0/4, 0x00008100); + INSTANCE_WR(ctx, 0x00b2c/4, 0x00000001); + INSTANCE_WR(ctx, 0x00b70/4, 0x00001001); + INSTANCE_WR(ctx, 0x00b7c/4, 0x00000003); + INSTANCE_WR(ctx, 0x00b80/4, 0x00888001); + INSTANCE_WR(ctx, 0x00bb0/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bb4/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bb8/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bbc/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bc0/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bc4/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bc8/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bcc/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bd0/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bd4/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bd8/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bdc/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00be0/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00be4/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00be8/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bec/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bf0/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bf4/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bf8/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bfc/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c00/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c04/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c08/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c0c/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c10/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c14/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c18/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c1c/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c20/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c24/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c28/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c2c/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c54/4, 0x00000005); + INSTANCE_WR(ctx, 0x00c60/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x00c7c/4, 0x00005555); + INSTANCE_WR(ctx, 0x00c80/4, 0x00005555); + INSTANCE_WR(ctx, 0x00c84/4, 0x00005555); + INSTANCE_WR(ctx, 0x00c88/4, 0x00005555); + INSTANCE_WR(ctx, 0x00c8c/4, 0x00005555); + INSTANCE_WR(ctx, 0x00c90/4, 0x00005555); + INSTANCE_WR(ctx, 0x00c94/4, 0x00005555); + INSTANCE_WR(ctx, 0x00c98/4, 0x00005555); + INSTANCE_WR(ctx, 0x00c9c/4, 0x00000001); + INSTANCE_WR(ctx, 0x00cd4/4, 0x00000001); + INSTANCE_WR(ctx, 0x00cd8/4, 0x08e00001); + INSTANCE_WR(ctx, 0x00cdc/4, 0x000e3000); + for(i=0x030a0; i<=0x03118; i+=8) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for(i=0x098a0; i<=0x0ba90; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for(i=0x0baa0; i<=0x0be90; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for(i=0x0e2e0; i<=0x0fff0; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for(i=0x10008; i<=0x104d0; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for(i=0x104e0; i<=0x108d0; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for(i=0x12d20; i<=0x14f10; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for(i=0x14f20; i<=0x15310; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for(i=0x17760; i<=0x19950; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for(i=0x19960; i<=0x19d50; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for(i=0x1c1a0; i<=0x1e390; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for(i=0x1e3a0; i<=0x1e790; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for(i=0x20be0; i<=0x22dd0; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for(i=0x22de0; i<=0x231d0; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); +} + +static void +nv4a_graph_context_init(drm_device_t *dev, struct mem_block *ctx) { drm_nouveau_private_t *dev_priv = dev->dev_private; int i; @@ -566,8 +794,223 @@ static void nv4a_graph_context_init(drm_device_t *dev, struct mem_block *ctx) INSTANCE_WR(ctx, i/4, 0x3f800000); } +static void +nv4b_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + int i; + + INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx)); + INSTANCE_WR(ctx, 0x00004/4, 0x0000c040); + INSTANCE_WR(ctx, 0x00008/4, 0x0000c040); + INSTANCE_WR(ctx, 0x0000c/4, 0x0000c040); + INSTANCE_WR(ctx, 0x00010/4, 0x0000c040); + INSTANCE_WR(ctx, 0x00014/4, 0x0000c040); + INSTANCE_WR(ctx, 0x00018/4, 0x0000c040); + INSTANCE_WR(ctx, 0x0001c/4, 0x0000c040); + INSTANCE_WR(ctx, 0x00020/4, 0x0000c040); + INSTANCE_WR(ctx, 0x000c4/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x000c8/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x000d0/4, 0x00000001); + INSTANCE_WR(ctx, 0x001bc/4, 0x20010001); + INSTANCE_WR(ctx, 0x001c0/4, 0x0f73ef00); + INSTANCE_WR(ctx, 0x001c8/4, 0x02008821); + INSTANCE_WR(ctx, 0x00218/4, 0x00000040); + INSTANCE_WR(ctx, 0x0021c/4, 0x00000040); + INSTANCE_WR(ctx, 0x00220/4, 0x00000040); + INSTANCE_WR(ctx, 0x00228/4, 0x00000040); + INSTANCE_WR(ctx, 0x00234/4, 0x80000000); + INSTANCE_WR(ctx, 0x00238/4, 0x80000000); + INSTANCE_WR(ctx, 0x0023c/4, 0x80000000); + INSTANCE_WR(ctx, 0x00240/4, 0x80000000); + INSTANCE_WR(ctx, 0x00244/4, 0x80000000); + INSTANCE_WR(ctx, 0x00248/4, 0x80000000); + INSTANCE_WR(ctx, 0x0024c/4, 0x80000000); + INSTANCE_WR(ctx, 0x00250/4, 0x80000000); + INSTANCE_WR(ctx, 0x00270/4, 0x0b0b0b0c); + INSTANCE_WR(ctx, 0x003e0/4, 0x00040000); + INSTANCE_WR(ctx, 0x003f0/4, 0x55555555); + INSTANCE_WR(ctx, 0x003f4/4, 0x55555555); + INSTANCE_WR(ctx, 0x003f8/4, 0x55555555); + INSTANCE_WR(ctx, 0x003fc/4, 0x55555555); + INSTANCE_WR(ctx, 0x00428/4, 0x00000008); + INSTANCE_WR(ctx, 0x0043c/4, 0x00001010); + INSTANCE_WR(ctx, 0x00460/4, 0x00000111); + INSTANCE_WR(ctx, 0x00464/4, 0x00000111); + INSTANCE_WR(ctx, 0x00468/4, 0x00000111); + INSTANCE_WR(ctx, 0x0046c/4, 0x00000111); + INSTANCE_WR(ctx, 0x00470/4, 0x00000111); + INSTANCE_WR(ctx, 0x00474/4, 0x00000111); + INSTANCE_WR(ctx, 0x00478/4, 0x00000111); + INSTANCE_WR(ctx, 0x0047c/4, 0x00000111); + INSTANCE_WR(ctx, 0x00480/4, 0x00000111); + INSTANCE_WR(ctx, 0x00484/4, 0x00000111); + INSTANCE_WR(ctx, 0x00488/4, 0x00000111); + INSTANCE_WR(ctx, 0x0048c/4, 0x00000111); + INSTANCE_WR(ctx, 0x00490/4, 0x00000111); + INSTANCE_WR(ctx, 0x00494/4, 0x00000111); + INSTANCE_WR(ctx, 0x00498/4, 0x00000111); + INSTANCE_WR(ctx, 0x0049c/4, 0x00000111); + INSTANCE_WR(ctx, 0x004f4/4, 0x00000111); + INSTANCE_WR(ctx, 0x004f8/4, 0x00080060); + INSTANCE_WR(ctx, 0x00514/4, 0x00000080); + INSTANCE_WR(ctx, 0x00518/4, 0xffff0000); + INSTANCE_WR(ctx, 0x0051c/4, 0x00000001); + INSTANCE_WR(ctx, 0x00530/4, 0x46400000); + INSTANCE_WR(ctx, 0x00540/4, 0xffff0000); + INSTANCE_WR(ctx, 0x00544/4, 0x88888888); + INSTANCE_WR(ctx, 0x00548/4, 0x88888888); + INSTANCE_WR(ctx, 0x0054c/4, 0x88888888); + INSTANCE_WR(ctx, 0x00550/4, 0x88888888); + INSTANCE_WR(ctx, 0x00554/4, 0x88888888); + INSTANCE_WR(ctx, 0x00558/4, 0x88888888); + INSTANCE_WR(ctx, 0x0055c/4, 0x88888888); + INSTANCE_WR(ctx, 0x00560/4, 0x88888888); + INSTANCE_WR(ctx, 0x00564/4, 0x88888888); + INSTANCE_WR(ctx, 0x00568/4, 0x88888888); + INSTANCE_WR(ctx, 0x0056c/4, 0x88888888); + INSTANCE_WR(ctx, 0x00570/4, 0x88888888); + INSTANCE_WR(ctx, 0x00574/4, 0x88888888); + INSTANCE_WR(ctx, 0x00578/4, 0x88888888); + INSTANCE_WR(ctx, 0x0057c/4, 0x88888888); + INSTANCE_WR(ctx, 0x00580/4, 0x88888888); + INSTANCE_WR(ctx, 0x00594/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x00598/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x005a0/4, 0x00011100); + INSTANCE_WR(ctx, 0x005bc/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005c0/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005c4/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005c8/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005cc/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005d0/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005d4/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005d8/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005dc/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005e0/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005e4/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005e8/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005ec/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005f0/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005f4/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005f8/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x00604/4, 0x4b7fffff); + INSTANCE_WR(ctx, 0x0062c/4, 0x30201000); + INSTANCE_WR(ctx, 0x00630/4, 0x70605040); + INSTANCE_WR(ctx, 0x00634/4, 0xb8a89888); + INSTANCE_WR(ctx, 0x00638/4, 0xf8e8d8c8); + INSTANCE_WR(ctx, 0x0064c/4, 0x40100000); + INSTANCE_WR(ctx, 0x00668/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x0069c/4, 0x435185d6); + INSTANCE_WR(ctx, 0x006a0/4, 0x2155b699); + INSTANCE_WR(ctx, 0x006a4/4, 0xfedcba98); + INSTANCE_WR(ctx, 0x006a8/4, 0x00000098); + INSTANCE_WR(ctx, 0x006b8/4, 0xffffffff); + INSTANCE_WR(ctx, 0x006bc/4, 0x00ff7000); + INSTANCE_WR(ctx, 0x006c0/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x006d0/4, 0x00ff0000); + INSTANCE_WR(ctx, 0x0070c/4, 0x00ffff00); + for (i=0x00750; i<=0x0078c; i+=4) + INSTANCE_WR(ctx, i/4, 0x00018488); + for (i=0x00790; i<=0x007cc; i+=4) + INSTANCE_WR(ctx, i/4, 0x00028202); + for (i=0x00810; i<=0x0084c; i+=4) + INSTANCE_WR(ctx, i/4, 0x0000aae4); + for (i=0x00850; i<=0x0088c; i+=4) + INSTANCE_WR(ctx, i/4, 0x01012000); + for (i=0x00890; i<=0x008cc; i+=4) + INSTANCE_WR(ctx, i/4, 0x00080008); + for (i=0x00910; i<=0x0094c; i+=4) + INSTANCE_WR(ctx, i/4, 0x00100008); + for (i=0x009a0; i<=0x009ac; i+=4) + INSTANCE_WR(ctx, i/4, 0x0001bc80); + for (i=0x009b0; i<=0x009bc; i+=4) + INSTANCE_WR(ctx, i/4, 0x00000202); + for (i=0x009d0; i<=0x009dc; i+=4) + INSTANCE_WR(ctx, i/4, 0x00000008); + for (i=0x009f0; i<=0x009fc; i+=4) + INSTANCE_WR(ctx, i/4, 0x00080008); + INSTANCE_WR(ctx, 0x00a10/4, 0x00000002); + INSTANCE_WR(ctx, 0x00a44/4, 0x00000421); + INSTANCE_WR(ctx, 0x00a48/4, 0x030c30c3); + INSTANCE_WR(ctx, 0x00a54/4, 0x3e020200); + INSTANCE_WR(ctx, 0x00a58/4, 0x00ffffff); + INSTANCE_WR(ctx, 0x00a5c/4, 0x20103f00); + INSTANCE_WR(ctx, 0x00a68/4, 0x00040000); + INSTANCE_WR(ctx, 0x00aa0/4, 0x00008100); + INSTANCE_WR(ctx, 0x00b2c/4, 0x00000001); + INSTANCE_WR(ctx, 0x00b70/4, 0x00001001); + INSTANCE_WR(ctx, 0x00b7c/4, 0x00000003); + INSTANCE_WR(ctx, 0x00b80/4, 0x00888001); + INSTANCE_WR(ctx, 0x00bb0/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bb4/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bb8/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bbc/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bc0/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bc4/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bc8/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bcc/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bd0/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bd4/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bd8/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bdc/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00be0/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00be4/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00be8/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bec/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bf0/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bf4/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bf8/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00bfc/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c00/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c04/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c08/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c0c/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c10/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c14/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c18/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c1c/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c20/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c24/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c28/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c2c/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00c54/4, 0x00000005); + INSTANCE_WR(ctx, 0x00c60/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x00c7c/4, 0x00005555); + INSTANCE_WR(ctx, 0x00c80/4, 0x00005555); + INSTANCE_WR(ctx, 0x00c84/4, 0x00005555); + INSTANCE_WR(ctx, 0x00c88/4, 0x00005555); + INSTANCE_WR(ctx, 0x00c8c/4, 0x00005555); + INSTANCE_WR(ctx, 0x00c90/4, 0x00005555); + INSTANCE_WR(ctx, 0x00c94/4, 0x00005555); + INSTANCE_WR(ctx, 0x00c98/4, 0x00005555); + INSTANCE_WR(ctx, 0x00c9c/4, 0x00000001); + INSTANCE_WR(ctx, 0x00cd4/4, 0x00000001); + INSTANCE_WR(ctx, 0x00cd8/4, 0x08e00001); + INSTANCE_WR(ctx, 0x00cdc/4, 0x000e3000); + for(i=0x030a0; i<=0x03118; i+=8) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for(i=0x098a0; i<=0x0ba90; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for(i=0x0baa0; i<=0x0be90; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for(i=0x0e2e0; i<=0x0fff0; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for(i=0x10008; i<=0x104d0; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for(i=0x104e0; i<=0x108d0; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for(i=0x12d20; i<=0x14f10; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for(i=0x14f20; i<=0x15310; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for(i=0x17760; i<=0x19950; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for(i=0x19960; i<=0x19d50; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); +} -static void nv4c_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +static void +nv4c_graph_context_init(drm_device_t *dev, struct mem_block *ctx) { drm_nouveau_private_t *dev_priv = dev->dev_private; int i; @@ -673,7 +1116,8 @@ static void nv4c_graph_context_init(drm_device_t *dev, struct mem_block *ctx) INSTANCE_WR(ctx, i/4, 0x3f800000); } -static void nv4e_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +static void +nv4e_graph_context_init(drm_device_t *dev, struct mem_block *ctx) { drm_nouveau_private_t *dev_priv = dev->dev_private; int i; @@ -802,10 +1246,18 @@ nv40_graph_create_context(drm_device_t *dev, int channel) ctx_size = NV46_GRCTX_SIZE; ctx_init = nv46_graph_context_init; break; + case 0x49: + ctx_size = NV49_GRCTX_SIZE; + ctx_init = nv49_graph_context_init; + break; case 0x4a: ctx_size = NV4A_GRCTX_SIZE; ctx_init = nv4a_graph_context_init; break; + case 0x4b: + ctx_size = NV4B_GRCTX_SIZE; + ctx_init = nv4b_graph_context_init; + break; case 0x4c: ctx_size = NV4C_GRCTX_SIZE; ctx_init = nv4c_graph_context_init; @@ -1037,6 +1489,39 @@ static uint32_t nv46_ctx_voodoo[] = { 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0 }; +//this is used for nv49 and nv4b +static uint32_t nv49_4b_ctx_voodoo[] ={ + 0x00400564, 0x00400505, 0x00408165, 0x00408206, 0x00409e68, 0x00200020, + 0x0060000a, 0x00700080, 0x00104042, 0x00200020, 0x0060000a, 0x00700000, + 0x001040c5, 0x00400f26, 0x00401068, 0x0060000d, 0x0070008f, 0x0070000e, + 0x00408d68, 0x004015e6, 0x007000a0, 0x00700080, 0x0040180f, 0x00700000, + 0x00200029, 0x0060000a, 0x0011814d, 0x00110158, 0x00105401, 0x0020003a, + 0x00100051, 0x001040c5, 0x0010c1c4, 0x001041c9, 0x0010c1dc, 0x00150210, + 0x0012c225, 0x00108238, 0x0010823e, 0x001242c0, 0x00200040, 0x00100280, + 0x00128100, 0x00128120, 0x00128143, 0x0011415f, 0x0010815c, 0x0010c140, + 0x00104029, 0x00110400, 0x00104d12, 0x00500060, 0x004071e6, 0x00200118, + 0x0060000a, 0x00200020, 0x00100620, 0x00154650, 0x00104668, 0x0017466d, + 0x0011068b, 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, + 0x001146c6, 0x00200022, 0x001006cc, 0x001246f0, 0x002000c0, 0x00100700, + 0x0010c3d7, 0x001043e1, 0x00500060, 0x00200290, 0x0060000a, 0x00104800, + 0x00108901, 0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00144a00, + 0x00104a19, 0x0010ca1c, 0x00110b00, 0x00200028, 0x00100b08, 0x00134c2e, + 0x0010cd00, 0x0010cd04, 0x00120d08, 0x00104d80, 0x00104e00, 0x0012d600, + 0x00105c00, 0x00104f06, 0x00105406, 0x00105709, 0x00200340, 0x0060000a, + 0x00300000, 0x00200680, 0x00406a0f, 0x00200684, 0x00800001, 0x00200b88, + 0x0060000a, 0x00209540, 0x0040708a, 0x00201350, 0x00800041, 0x00407c0f, + 0x00600006, 0x00407ce6, 0x00700080, 0x002000a2, 0x0060000a, 0x00104280, + 0x00200340, 0x0060000a, 0x00200004, 0x00800001, 0x0070008e, 0x00408d68, + 0x0040020f, 0x00600006, 0x00409e68, 0x00600007, 0x0070000f, 0x0070000e, + 0x00408d68, 0x0091a880, 0x00901ffe, 0x10940000, 0x00200020, 0x0060000b, + 0x00500069, 0x0060000c, 0x00401568, 0x00700000, 0x00200001, 0x0040910e, + 0x00200021, 0x0060000a, 0x00409b0d, 0x00104a40, 0x00104a50, 0x00104a60, + 0x00104a70, 0x00104a80, 0x00104a90, 0x00104aa0, 0x00104ab0, 0x00407e0e, + 0x0040130f, 0x00408568, 0x0040a006, 0x0040a105, 0x00600009, 0x00700005, + 0x00700006, 0x0060000e, ~0 +}; + + static uint32_t nv4a_ctx_voodoo[] = { 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409965, 0x00409e06, @@ -1130,7 +1615,9 @@ nv40_graph_init(drm_device_t *dev) case 0x40: ctx_voodoo = nv40_ctx_voodoo; break; case 0x43: ctx_voodoo = nv43_ctx_voodoo; break; case 0x46: ctx_voodoo = nv46_ctx_voodoo; break; + case 0x49: ctx_voodoo = nv49_4b_ctx_voodoo; break; case 0x4a: ctx_voodoo = nv4a_ctx_voodoo; break; + case 0x4b: ctx_voodoo = nv49_4b_ctx_voodoo; break; case 0x4e: ctx_voodoo = nv4e_ctx_voodoo; break; default: DRM_ERROR("Unknown ctx_voodoo for chipset 0x%02x\n", -- cgit v1.2.3 From 5c27f8a70e6e3684d8d58661a9cc918a3514fd14 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 26 Jun 2007 09:51:55 -0700 Subject: Add support SiS based XGI chips to SiS DRM. --- shared-core/drm_pciids.txt | 2 ++ shared-core/sis_drv.h | 8 ++++---- 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index ba02aa89..ad9994ec 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -211,6 +211,8 @@ 0x1039 0x6300 0 "SiS 630" 0x1039 0x6330 SIS_CHIP_315 "SiS 661" 0x1039 0x7300 0 "SiS 730" +0x18CA 0x0040 SIS_CHIP_315 "Volari V3XT/V5/V8" +0x18CA 0x0042 SIS_CHIP_315 "Volari Unknown" [tdfx] 0x121a 0x0003 0 "3dfx Voodoo Banshee" diff --git a/shared-core/sis_drv.h b/shared-core/sis_drv.h index 006d148c..ec572ad4 100644 --- a/shared-core/sis_drv.h +++ b/shared-core/sis_drv.h @@ -33,11 +33,11 @@ #define DRIVER_AUTHOR "SIS, Tungsten Graphics" #define DRIVER_NAME "sis" -#define DRIVER_DESC "SIS 300/630/540" -#define DRIVER_DATE "20060619" +#define DRIVER_DESC "SIS 300/630/540 and XGI V3XE/V5/V8" +#define DRIVER_DATE "20070626" #define DRIVER_MAJOR 1 -#define DRIVER_MINOR 2 -#define DRIVER_PATCHLEVEL 1 +#define DRIVER_MINOR 3 +#define DRIVER_PATCHLEVEL 0 enum sis_family { SIS_OTHER = 0, -- cgit v1.2.3 From 9b9a127ed0fe9a6a8e2fde84739ccff6fa0bc5ac Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Tue, 26 Jun 2007 23:25:40 +0200 Subject: More 64-bit padding. --- shared-core/drm.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index 1b0e54e3..e017c023 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -676,7 +676,7 @@ typedef struct drm_fence_arg { unsigned int type; unsigned int flags; unsigned int signaled; - unsigned int pad_64; + unsigned int pad64; drm_u64_t expand_pad[3]; /*Future expansion */ } drm_fence_arg_t; @@ -797,6 +797,7 @@ struct drm_bo_info_req { unsigned int handle; unsigned int hint; unsigned int fence_class; + unsigned int pad64; }; struct drm_bo_create_req { @@ -806,6 +807,7 @@ struct drm_bo_create_req { unsigned int hint; unsigned int page_alignment; drm_bo_type_t type; + unsigned int pad64; }; struct drm_bo_op_req { @@ -838,13 +840,14 @@ struct drm_bo_info_rep { unsigned int desired_tile_stride; unsigned int hw_tile_stride; unsigned int tile_info; - unsigned int pad64; + unsigned int pad64; drm_u64_t expand_pad[4]; /*Future expansion */ }; struct drm_bo_arg_rep { struct drm_bo_info_rep bo_info; int ret; + unsigned int pad64; }; struct drm_bo_create_arg { @@ -873,13 +876,13 @@ struct drm_bo_map_wait_idle_arg { }; struct drm_bo_op_arg { - int handled; - unsigned int pad_64; drm_u64_t next; union { struct drm_bo_op_req req; struct drm_bo_arg_rep rep; } d; + int handled; + unsigned int pad64; }; #define DRM_BO_MEM_LOCAL 0 -- cgit v1.2.3 From 4f2dd78ff3b6efeee97b72cca6bbfaef485a08d9 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 28 Jun 2007 02:56:30 +1000 Subject: nouveau/nv04: Set NV_PFIFO_CACHE1_PUSH1 correctly + small tweaks --- shared-core/nv04_fifo.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv04_fifo.c b/shared-core/nv04_fifo.c index 34a497b7..783514a7 100644 --- a/shared-core/nv04_fifo.c +++ b/shared-core/nv04_fifo.c @@ -53,10 +53,9 @@ nv04_fifo_create_context(drm_device_t *dev, int channel) RAMFC_WR(DMA_PUT, chan->pushbuf_base); RAMFC_WR(DMA_GET, chan->pushbuf_base); RAMFC_WR(DMA_INSTANCE, nouveau_chip_instance_get(dev, pb->instance)); - /* NOTE: nvidia use TRIG_128/SIZE_128/MAX_REQS_8 */ - RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES | + RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 | + NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | #ifdef __BIG_ENDIAN NV_PFIFO_CACHE1_BIG_ENDIAN | #endif @@ -83,8 +82,10 @@ nv04_fifo_load_context(drm_device_t *dev, int channel) int fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE); uint32_t tmp; - NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT)); + NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, (1<<8) | channel); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET)); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT)); tmp = RAMFC_RD(DMA_INSTANCE); NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF); -- cgit v1.2.3 From 695599f18d907bb277805581bbe208b0e083e7d9 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 24 Jun 2007 19:03:35 +1000 Subject: nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7) For various reasons, this ioctl was a bad idea. At channel creation we now automatically create DMA objects covering available VRAM and GART memory, where the client used to do this themselves. However, there is still a need to be able to create DMA objects pointing at specific areas of memory (ie. notifiers). Each channel is now allocated a small amount of memory from which a client can suballocate things (such as notifiers), and have a DMA object created which covers the suballocated area. The NOTIFIER_ALLOC ioctl exposes this functionality. --- shared-core/nouveau_drm.h | 28 ++++---- shared-core/nouveau_drv.h | 28 +++++++- shared-core/nouveau_fifo.c | 45 +++++++++--- shared-core/nouveau_mem.c | 51 +++++++++----- shared-core/nouveau_notifier.c | 154 +++++++++++++++++++++++++++++++++++++++++ shared-core/nouveau_object.c | 143 +++++++++++++------------------------- shared-core/nouveau_state.c | 3 +- 7 files changed, 313 insertions(+), 139 deletions(-) create mode 100644 shared-core/nouveau_notifier.c (limited to 'shared-core') diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h index 1e7322e0..0758991a 100644 --- a/shared-core/nouveau_drm.h +++ b/shared-core/nouveau_drm.h @@ -25,9 +25,12 @@ #ifndef __NOUVEAU_DRM_H__ #define __NOUVEAU_DRM_H__ -#define NOUVEAU_DRM_HEADER_PATCHLEVEL 6 +#define NOUVEAU_DRM_HEADER_PATCHLEVEL 7 typedef struct drm_nouveau_fifo_alloc { + uint32_t fb_ctxdma_handle; + uint32_t tt_ctxdma_handle; + int channel; uint32_t put_base; /* FIFO control regs */ @@ -36,29 +39,30 @@ typedef struct drm_nouveau_fifo_alloc { /* DMA command buffer */ drm_handle_t cmdbuf; int cmdbuf_size; + /* Notifier memory */ + drm_handle_t notifier; + int notifier_size; } drm_nouveau_fifo_alloc_t; -typedef struct drm_nouveau_object_init { +typedef struct drm_nouveau_grobj_alloc { int channel; uint32_t handle; int class; } -drm_nouveau_object_init_t; +drm_nouveau_grobj_alloc_t; #define NOUVEAU_MEM_ACCESS_RO 1 #define NOUVEAU_MEM_ACCESS_WO 2 #define NOUVEAU_MEM_ACCESS_RW 3 -typedef struct drm_nouveau_dma_object_init { +typedef struct drm_nouveau_notifier_alloc { int channel; uint32_t handle; - int class; - int access; - int target; + int count; + uint32_t offset; - int size; } -drm_nouveau_dma_object_init_t; +drm_nouveau_notifier_alloc_t; #define NOUVEAU_MEM_FB 0x00000001 #define NOUVEAU_MEM_AGP 0x00000002 @@ -68,7 +72,7 @@ drm_nouveau_dma_object_init_t; #define NOUVEAU_MEM_USER_BACKED 0x00000020 #define NOUVEAU_MEM_MAPPED 0x00000040 #define NOUVEAU_MEM_INSTANCE 0x00000080 /* internal */ - +#define NOUVEAU_MEM_NOTIFIER 0x00000100 /* internal */ typedef struct drm_nouveau_mem_alloc { int flags; int alignment; @@ -141,8 +145,8 @@ typedef struct drm_nouveau_sarea { drm_nouveau_sarea_t; #define DRM_NOUVEAU_FIFO_ALLOC 0x00 -#define DRM_NOUVEAU_OBJECT_INIT 0x01 -#define DRM_NOUVEAU_DMA_OBJECT_INIT 0x02 +#define DRM_NOUVEAU_GROBJ_ALLOC 0x01 +#define DRM_NOUVEAU_NOTIFIER_ALLOC 0x02 #define DRM_NOUVEAU_MEM_ALLOC 0x03 #define DRM_NOUVEAU_MEM_FREE 0x04 #define DRM_NOUVEAU_GETPARAM 0x05 diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index b3122d8a..7a1ca3d5 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -34,7 +34,7 @@ #define DRIVER_MAJOR 0 #define DRIVER_MINOR 0 -#define DRIVER_PATCHLEVEL 6 +#define DRIVER_PATCHLEVEL 7 #define NOUVEAU_FAMILY 0x0000FFFF #define NOUVEAU_FLAGS 0xFFFF0000 @@ -84,6 +84,10 @@ struct nouveau_fifo struct mem_block *cmdbuf_mem; struct nouveau_object *cmdbuf_obj; uint32_t pushbuf_base; + /* notifier memory */ + struct mem_block *notifier_block; + struct mem_block *notifier_heap; + drm_local_map_t *notifier_map; /* PGRAPH context, for cards that keep it in RAMIN */ struct mem_block *ramin_grctx; /* objects belonging to this fifo */ @@ -197,6 +201,12 @@ extern void nouveau_wait_for_idle(struct drm_device *dev); extern int nouveau_ioctl_card_init(DRM_IOCTL_ARGS); /* nouveau_mem.c */ +extern int nouveau_mem_init_heap(struct mem_block **, + uint64_t start, uint64_t size); +extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *, + uint64_t size, int align2, + DRMFILE); +extern void nouveau_mem_free_block(struct mem_block *); extern uint64_t nouveau_mem_fb_amount(struct drm_device *dev); extern void nouveau_mem_release(DRMFILE filp, struct mem_block *heap); extern int nouveau_ioctl_mem_alloc(DRM_IOCTL_ARGS); @@ -216,6 +226,13 @@ extern void nouveau_instmem_w32(drm_nouveau_private_t *dev_priv, struct mem_block *mem, int index, uint32_t val); +/* nouveau_notifier.c */ +extern int nouveau_notifier_init_channel(drm_device_t *, int channel, DRMFILE); +extern void nouveau_notifier_takedown_channel(drm_device_t *, int channel); +extern int nouveau_notifier_alloc(drm_device_t *, int channel, + uint32_t handle, int cout, uint32_t *offset); +extern int nouveau_ioctl_notifier_alloc(DRM_IOCTL_ARGS); + /* nouveau_fifo.c */ extern int nouveau_fifo_init(drm_device_t *dev); extern int nouveau_fifo_number(drm_device_t *dev); @@ -225,7 +242,13 @@ extern int nouveau_fifo_owner(drm_device_t *dev, DRMFILE filp, int channel); extern void nouveau_fifo_free(drm_device_t *dev, int channel); /* nouveau_object.c */ +extern int nouveau_object_init_channel(drm_device_t *, int channel, + uint32_t vram_handle, + uint32_t tt_handle); +extern void nouveau_object_takedown_channel(drm_device_t *dev, int channel); extern void nouveau_object_cleanup(drm_device_t *dev, int channel); +extern int nouveau_ht_object_insert(drm_device_t *, int channel, + uint32_t handle, struct nouveau_object *); extern struct nouveau_object * nouveau_object_gr_create(drm_device_t *dev, int channel, int class); extern struct nouveau_object * @@ -233,8 +256,7 @@ nouveau_object_dma_create(drm_device_t *dev, int channel, int class, uint32_t offset, uint32_t size, int access, int target); extern void nouveau_object_free(drm_device_t *dev, struct nouveau_object *obj); -extern int nouveau_ioctl_object_init(DRM_IOCTL_ARGS); -extern int nouveau_ioctl_dma_object_init(DRM_IOCTL_ARGS); +extern int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS); extern uint32_t nouveau_chip_instance_get(drm_device_t *dev, struct mem_block *mem); /* nouveau_irq.c */ diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 1a06f913..f179af63 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -241,7 +241,8 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) } /* allocates and initializes a fifo for user space consumption */ -static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) +int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp, + uint32_t vram_handle, uint32_t tt_handle) { int ret; drm_nouveau_private_t *dev_priv = dev->dev_private; @@ -282,6 +283,20 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp) return ret; } + /* Setup channel's default objects */ + ret = nouveau_object_init_channel(dev, channel, vram_handle, tt_handle); + if (ret) { + nouveau_fifo_free(dev, channel); + return ret; + } + + /* Allocate space for per-channel fixed notifier memory */ + ret = nouveau_notifier_init_channel(dev, channel, filp); + if (ret) { + nouveau_fifo_free(dev, channel); + return ret; + } + nouveau_wait_for_idle(dev); /* disable the fifo caches */ @@ -370,6 +385,8 @@ void nouveau_fifo_free(drm_device_t* dev, int channel) if (chan->cmdbuf_mem) nouveau_mem_free(dev, chan->cmdbuf_mem); + nouveau_notifier_takedown_channel(dev, channel); + /* Destroy objects belonging to the channel */ nouveau_object_cleanup(dev, channel); @@ -408,30 +425,42 @@ static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan; drm_nouveau_fifo_alloc_t init; int res; DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_fifo_alloc_t __user *) data, sizeof(init)); - res = nouveau_fifo_alloc(dev, &init.channel, filp); + res = nouveau_fifo_alloc(dev, &init.channel, filp, + init.fb_ctxdma_handle, + init.tt_ctxdma_handle); if (res) return res; + chan = &dev_priv->fifos[init.channel]; - init.put_base = dev_priv->fifos[init.channel].pushbuf_base; + init.put_base = chan->pushbuf_base; /* make the fifo available to user space */ /* first, the fifo control regs */ init.ctrl = dev_priv->mmio->offset + NV03_FIFO_REGS(init.channel); init.ctrl_size = NV03_FIFO_REGS_SIZE; res = drm_addmap(dev, init.ctrl, init.ctrl_size, _DRM_REGISTERS, - 0, &dev_priv->fifos[init.channel].regs); + 0, &chan->regs); if (res != 0) return res; /* pass back FIFO map info to the caller */ - init.cmdbuf = dev_priv->fifos[init.channel].cmdbuf_mem->start; - init.cmdbuf_size = dev_priv->fifos[init.channel].cmdbuf_mem->size; + init.cmdbuf = chan->cmdbuf_mem->start; + init.cmdbuf_size = chan->cmdbuf_mem->size; + + /* and the notifier block */ + init.notifier = chan->notifier_block->start; + init.notifier_size = chan->notifier_block->size; + res = drm_addmap(dev, init.notifier, init.notifier_size, _DRM_REGISTERS, + 0, &chan->notifier_map); + if (res != 0) + return res; DRM_COPY_TO_USER_IOCTL((drm_nouveau_fifo_alloc_t __user *)data, init, sizeof(init)); @@ -444,8 +473,8 @@ static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) drm_ioctl_desc_t nouveau_ioctls[] = { [DRM_IOCTL_NR(DRM_NOUVEAU_FIFO_ALLOC)] = {nouveau_ioctl_fifo_alloc, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_NOUVEAU_OBJECT_INIT)] = {nouveau_ioctl_object_init, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_NOUVEAU_DMA_OBJECT_INIT)] = {nouveau_ioctl_dma_object_init, DRM_AUTH}, + [DRM_IOCTL_NR(DRM_NOUVEAU_GROBJ_ALLOC)] = {nouveau_ioctl_grobj_alloc, DRM_AUTH}, + [DRM_IOCTL_NR(DRM_NOUVEAU_NOTIFIER_ALLOC)] = {nouveau_ioctl_notifier_alloc, DRM_AUTH}, [DRM_IOCTL_NR(DRM_NOUVEAU_MEM_ALLOC)] = {nouveau_ioctl_mem_alloc, DRM_AUTH}, [DRM_IOCTL_NR(DRM_NOUVEAU_MEM_FREE)] = {nouveau_ioctl_mem_free, DRM_AUTH}, [DRM_IOCTL_NR(DRM_NOUVEAU_GETPARAM)] = {nouveau_ioctl_getparam, DRM_AUTH}, diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index a5343b99..edfc9d3f 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -77,8 +77,8 @@ out: return p; } -static struct mem_block *alloc_block(struct mem_block *heap, uint64_t size, - int align2, DRMFILE filp) +struct mem_block *nouveau_mem_alloc_block(struct mem_block *heap, uint64_t size, + int align2, DRMFILE filp) { struct mem_block *p; uint64_t mask = (1 << align2) - 1; @@ -106,7 +106,7 @@ static struct mem_block *find_block(struct mem_block *heap, uint64_t start) return NULL; } -static void free_block(struct mem_block *p) +void nouveau_mem_free_block(struct mem_block *p) { p->filp = NULL; @@ -132,7 +132,8 @@ static void free_block(struct mem_block *p) /* Initialize. How to check for an uninitialized heap? */ -static int init_heap(struct mem_block **heap, uint64_t start, uint64_t size) +int nouveau_mem_init_heap(struct mem_block **heap, uint64_t start, + uint64_t size) { struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFS); @@ -331,7 +332,9 @@ int nouveau_mem_init(struct drm_device *dev) goto no_agp; } - if (init_heap(&dev_priv->agp_heap, info.aperture_base, info.aperture_size)) + if (nouveau_mem_init_heap(&dev_priv->agp_heap, + info.aperture_base, + info.aperture_size)) goto no_agp; dev_priv->agp_phys = info.aperture_base; @@ -357,12 +360,19 @@ no_agp: if (fb_size>256*1024*1024) { /* On cards with > 256Mb, you can't map everything. * So we create a second FB heap for that type of memory */ - if (init_heap(&dev_priv->fb_heap, drm_get_resource_start(dev,1), 256*1024*1024)) + if (nouveau_mem_init_heap(&dev_priv->fb_heap, + drm_get_resource_start(dev,1), + 256*1024*1024)) return DRM_ERR(ENOMEM); - if (init_heap(&dev_priv->fb_nomap_heap, drm_get_resource_start(dev,1)+256*1024*1024, fb_size-256*1024*1024)) + if (nouveau_mem_init_heap(&dev_priv->fb_nomap_heap, + drm_get_resource_start(dev,1) + + 256*1024*1024, + fb_size-256*1024*1024)) return DRM_ERR(ENOMEM); } else { - if (init_heap(&dev_priv->fb_heap, drm_get_resource_start(dev,1), fb_size)) + if (nouveau_mem_init_heap(&dev_priv->fb_heap, + drm_get_resource_start(dev,1), + fb_size)) return DRM_ERR(ENOMEM); dev_priv->fb_nomap_heap=NULL; } @@ -397,21 +407,25 @@ struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment, uint6 if (flags&NOUVEAU_MEM_AGP) { type=NOUVEAU_MEM_AGP; - block = alloc_block(dev_priv->agp_heap, size, alignment, filp); + block = nouveau_mem_alloc_block(dev_priv->agp_heap, size, + alignment, filp); if (block) goto alloc_ok; } if (flags&(NOUVEAU_MEM_FB|NOUVEAU_MEM_FB_ACCEPTABLE)) { type=NOUVEAU_MEM_FB; if (!(flags&NOUVEAU_MEM_MAPPED)) { - block = alloc_block(dev_priv->fb_nomap_heap, size, alignment, filp); + block = nouveau_mem_alloc_block(dev_priv->fb_nomap_heap, + size, alignment, filp); if (block) goto alloc_ok; } - block = alloc_block(dev_priv->fb_heap, size, alignment, filp); + block = nouveau_mem_alloc_block(dev_priv->fb_heap, size, + alignment, filp); if (block) goto alloc_ok; } if (flags&NOUVEAU_MEM_AGP_ACCEPTABLE) { type=NOUVEAU_MEM_AGP; - block = alloc_block(dev_priv->agp_heap, size, alignment, filp); + block = nouveau_mem_alloc_block(dev_priv->agp_heap, size, + alignment, filp); if (block) goto alloc_ok; } @@ -432,7 +446,7 @@ alloc_ok: ret = drm_addmap(dev, block->start, block->size, _DRM_FRAME_BUFFER, 0, &block->map); if (ret) { - free_block(block); + nouveau_mem_free_block(block); return NULL; } } @@ -446,7 +460,7 @@ void nouveau_mem_free(struct drm_device* dev, struct mem_block* block) DRM_INFO("freeing 0x%llx\n", block->start); if (block->flags&NOUVEAU_MEM_MAPPED) drm_rmmap(dev, block->map); - free_block(block); + nouveau_mem_free_block(block); } static void @@ -549,8 +563,8 @@ int nouveau_instmem_init(struct drm_device *dev) * the space that was reserved for RAMHT/FC/RO. */ offset = dev_priv->ramfc_offset + dev_priv->ramfc_size; - ret = init_heap(&dev_priv->ramin_heap, - offset, dev_priv->ramin_size - offset); + ret = nouveau_mem_init_heap(&dev_priv->ramin_heap, + offset, dev_priv->ramin_size - offset); if (ret) { dev_priv->ramin_heap = NULL; DRM_ERROR("Failed to init RAMIN heap\n"); @@ -570,7 +584,8 @@ struct mem_block *nouveau_instmem_alloc(struct drm_device *dev, return NULL; } - block = alloc_block(dev_priv->ramin_heap, size, align, (DRMFILE)-2); + block = nouveau_mem_alloc_block(dev_priv->ramin_heap, size, align, + (DRMFILE)-2); if (block) { block->flags = NOUVEAU_MEM_INSTANCE; DRM_DEBUG("instance(size=%d, align=%d) alloc'd at 0x%08x\n", @@ -583,7 +598,7 @@ struct mem_block *nouveau_instmem_alloc(struct drm_device *dev, void nouveau_instmem_free(struct drm_device *dev, struct mem_block *block) { if (dev && block) { - free_block(block); + nouveau_mem_free_block(block); } } diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c new file mode 100644 index 00000000..ab6f8c2d --- /dev/null +++ b/shared-core/nouveau_notifier.c @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2007 Ben Skeggs. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "drmP.h" +#include "drm.h" +#include "nouveau_drv.h" + +int +nouveau_notifier_init_channel(drm_device_t *dev, int channel, DRMFILE filp) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + int flags, ret; + + /*TODO: PCI notifier blocks */ + if (dev_priv->agp_heap) + flags = NOUVEAU_MEM_AGP | NOUVEAU_MEM_FB_ACCEPTABLE; + else + flags = NOUVEAU_MEM_FB; + + chan->notifier_block = nouveau_mem_alloc(dev, 0, PAGE_SIZE, flags,filp); + if (!chan->notifier_block) + return DRM_ERR(ENOMEM); + + ret = nouveau_mem_init_heap(&chan->notifier_heap, + 0, chan->notifier_block->size); + if (ret) + return ret; + + return 0; +} + +void +nouveau_notifier_takedown_channel(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + + if (chan->notifier_block) { + nouveau_mem_free(dev, chan->notifier_block); + chan->notifier_block = NULL; + } + + /*XXX: heap destroy */ +} + +int +nouveau_notifier_alloc(drm_device_t *dev, int channel, uint32_t handle, + int count, uint32_t *b_offset) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_object *obj; + struct mem_block *mem; + uint32_t offset; + int target; + + if (!chan->notifier_heap) { + DRM_ERROR("Channel %d doesn't have a notifier heap!\n", + channel); + return DRM_ERR(EINVAL); + } + + mem = nouveau_mem_alloc_block(chan->notifier_heap, 32, 0, chan->filp); + if (!mem) { + DRM_ERROR("Channel %d notifier block full\n", channel); + return DRM_ERR(ENOMEM); + } + mem->flags = NOUVEAU_MEM_NOTIFIER; + + offset = chan->notifier_block->start + mem->start; + if (chan->notifier_block->flags & NOUVEAU_MEM_FB) { + offset -= drm_get_resource_start(dev, 1); + target = NV_DMA_TARGET_VIDMEM; + } else if (chan->notifier_block->flags & NOUVEAU_MEM_AGP) { + offset -= dev_priv->agp_phys; + target = NV_DMA_TARGET_AGP; + } else { + DRM_ERROR("Bad DMA target, flags 0x%08x!\n", + chan->notifier_block->flags); + return DRM_ERR(EINVAL); + } + + obj = nouveau_object_dma_create(dev, channel, NV_CLASS_DMA_IN_MEMORY, + offset, mem->size, NV_DMA_ACCESS_RW, + target); + if (!obj) { + nouveau_mem_free_block(mem); + DRM_ERROR("Error creating notifier ctxdma\n"); + return DRM_ERR(ENOMEM); + } + + obj->handle = handle; + if (nouveau_ht_object_insert(dev, channel, handle, obj)) { + nouveau_object_free(dev, obj); + nouveau_mem_free_block(mem); + DRM_ERROR("Error inserting notifier ctxdma into RAMHT\n"); + return DRM_ERR(ENOMEM); + } + + *b_offset = mem->start; + return 0; +} + +int +nouveau_ioctl_notifier_alloc(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + drm_nouveau_notifier_alloc_t na; + int ret; + + DRM_COPY_FROM_USER_IOCTL(na, (drm_nouveau_notifier_alloc_t __user*)data, + sizeof(na)); + + if (!nouveau_fifo_owner(dev, filp, na.channel)) { + DRM_ERROR("pid %d doesn't own channel %d\n", + DRM_CURRENTPID, na.channel); + return DRM_ERR(EPERM); + } + + ret = nouveau_notifier_alloc(dev, na.channel, na.handle, + na.count, &na.offset); + if (ret) + return ret; + + DRM_COPY_TO_USER_IOCTL((drm_nouveau_notifier_alloc_t __user*)data, + na, sizeof(na)); + return 0; +} + diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index e36568c6..e7528e23 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -153,13 +153,13 @@ nouveau_ht_handle_hash(drm_device_t *dev, int channel, uint32_t handle) return hash << 3; } -static int +int nouveau_ht_object_insert(drm_device_t* dev, int channel, uint32_t handle, struct nouveau_object *obj) { drm_nouveau_private_t *dev_priv=dev->dev_private; int ht_base = NV_RAMIN + dev_priv->ramht_offset; - int ht_end = ht_base + dev_priv->ramht_size; +/* int ht_end = ht_base + dev_priv->ramht_size; */ int o_ofs, ofs; obj->handle = handle; @@ -461,115 +461,70 @@ nouveau_object_free(drm_device_t *dev, struct nouveau_object *obj) drm_free(obj, sizeof(struct nouveau_object), DRM_MEM_DRIVER); } -void nouveau_object_cleanup(drm_device_t *dev, int channel) -{ - drm_nouveau_private_t *dev_priv=dev->dev_private; - - while (dev_priv->fifos[channel].objs) { - nouveau_object_free(dev, dev_priv->fifos[channel].objs); - } -} - -int nouveau_ioctl_object_init(DRM_IOCTL_ARGS) +int +nouveau_object_init_channel(drm_device_t *dev, int channel, + uint32_t vram_handle, + uint32_t tt_handle) { - DRM_DEVICE; - drm_nouveau_object_init_t init; - struct nouveau_object *obj; - - DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_object_init_t __user *) - data, sizeof(init)); - - if (!nouveau_fifo_owner(dev, filp, init.channel)) { - DRM_ERROR("pid %d doesn't own channel %d\n", - DRM_CURRENTPID, init.channel); - return DRM_ERR(EINVAL); + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_object *gpuobj; + int ret; + + /* VRAM ctxdma */ + gpuobj = nouveau_object_dma_create(dev, channel, NV_CLASS_DMA_IN_MEMORY, + 0, dev_priv->fb_available_size, + NV_DMA_ACCESS_RW, + NV_DMA_TARGET_VIDMEM); + if (!gpuobj) { + DRM_ERROR("Error creating VRAM ctxdma: %d\n", DRM_ERR(ENOMEM)); + return DRM_ERR(ENOMEM); } - //FIXME: check args, only allow trusted objects to be created - - if (nouveau_object_handle_find(dev, init.channel, init.handle)) { - DRM_ERROR("Channel %d: handle 0x%08x already exists\n", - init.channel, init.handle); - return DRM_ERR(EINVAL); + ret = nouveau_ht_object_insert(dev, channel, vram_handle, gpuobj); + if (ret) { + DRM_ERROR("Error referencing VRAM ctxdma: %d\n", ret); + return ret; } - obj = nouveau_object_gr_create(dev, init.channel, init.class); - if (!obj) + /* non-AGP unimplemented */ + if (dev_priv->agp_heap == NULL) + return 0; + + /* GART ctxdma */ + gpuobj = nouveau_object_dma_create(dev, channel, NV_CLASS_DMA_IN_MEMORY, + 0, dev_priv->agp_available_size, + NV_DMA_ACCESS_RW, + NV_DMA_TARGET_AGP); + if (!gpuobj) { + DRM_ERROR("Error creating TT ctxdma: %d\n", DRM_ERR(ENOMEM)); return DRM_ERR(ENOMEM); + } - if (nouveau_ht_object_insert(dev, init.channel, init.handle, obj)) { - nouveau_object_free(dev, obj); - return DRM_ERR(ENOMEM); + ret = nouveau_ht_object_insert(dev, channel, tt_handle, gpuobj); + if (ret) { + DRM_ERROR("Error referencing TT ctxdma: %d\n", ret); + return ret; } return 0; } -static int -nouveau_dma_object_check_access(drm_device_t *dev, - drm_nouveau_dma_object_init_t *init) +void nouveau_object_cleanup(drm_device_t *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; - uint64_t limit; - - /* Check for known DMA object classes */ - switch (init->class) { - case NV_CLASS_DMA_IN_MEMORY: - case NV_CLASS_DMA_FROM_MEMORY: - case NV_CLASS_DMA_TO_MEMORY: - break; - default: - DRM_ERROR("invalid class = 0x%x\n", init->class); - return DRM_ERR(EPERM); - } - - /* Check access mode, and translate to NV_DMA_ACCESS_* */ - switch (init->access) { - case NOUVEAU_MEM_ACCESS_RO: - init->access = NV_DMA_ACCESS_RO; - break; - case NOUVEAU_MEM_ACCESS_WO: - init->access = NV_DMA_ACCESS_WO; - break; - case NOUVEAU_MEM_ACCESS_RW: - init->access = NV_DMA_ACCESS_RW; - break; - default: - DRM_ERROR("invalid access mode = %d\n", init->access); - return DRM_ERR(EPERM); - } - - /* Check that request is within the allowed limits of "target" */ - switch (init->target) { - case NOUVEAU_MEM_FB: - limit = dev_priv->fb_available_size; - init->target = NV_DMA_TARGET_VIDMEM; - break; - case NOUVEAU_MEM_AGP: - limit = dev_priv->agp_available_size; - init->target = NV_DMA_TARGET_AGP; - break; - default: - DRM_ERROR("invalid target = 0x%x\n", init->target); - return DRM_ERR(EPERM); - } + drm_nouveau_private_t *dev_priv=dev->dev_private; - if ((init->offset > limit) || (init->offset + init->size) > limit) { - DRM_ERROR("access out of allowed range (%d,0x%08x,0x%08x)\n", - init->target, init->offset, init->size); - return DRM_ERR(EPERM); + while (dev_priv->fifos[channel].objs) { + nouveau_object_free(dev, dev_priv->fifos[channel].objs); } - - return 0; } -int nouveau_ioctl_dma_object_init(DRM_IOCTL_ARGS) +int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_nouveau_dma_object_init_t init; + drm_nouveau_grobj_alloc_t init; struct nouveau_object *obj; - DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_dma_object_init_t __user *) + DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_grobj_alloc_t __user *) data, sizeof(init)); if (!nouveau_fifo_owner(dev, filp, init.channel)) { @@ -578,8 +533,7 @@ int nouveau_ioctl_dma_object_init(DRM_IOCTL_ARGS) return DRM_ERR(EINVAL); } - if (nouveau_dma_object_check_access(dev, &init)) - return DRM_ERR(EPERM); + //FIXME: check args, only allow trusted objects to be created if (nouveau_object_handle_find(dev, init.channel, init.handle)) { DRM_ERROR("Channel %d: handle 0x%08x already exists\n", @@ -587,13 +541,10 @@ int nouveau_ioctl_dma_object_init(DRM_IOCTL_ARGS) return DRM_ERR(EINVAL); } - obj = nouveau_object_dma_create(dev, init.channel, init.class, - init.offset, init.size, - init.access, init.target); + obj = nouveau_object_gr_create(dev, init.channel, init.class); if (!obj) return DRM_ERR(ENOMEM); - obj->handle = init.handle; if (nouveau_ht_object_insert(dev, init.channel, init.handle, obj)) { nouveau_object_free(dev, obj); return DRM_ERR(ENOMEM); diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index b3562e2f..68392c3a 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -260,9 +260,9 @@ void nouveau_preclose(drm_device_t * dev, DRMFILE filp) { drm_nouveau_private_t *dev_priv = dev->dev_private; + nouveau_fifo_cleanup(dev, filp); nouveau_mem_release(filp,dev_priv->fb_heap); nouveau_mem_release(filp,dev_priv->agp_heap); - nouveau_fifo_cleanup(dev, filp); } /* first module load, setup the mmio/fb mapping */ @@ -282,7 +282,6 @@ int nouveau_firstopen(struct drm_device *dev) int nouveau_load(struct drm_device *dev, unsigned long flags) { drm_nouveau_private_t *dev_priv; - int ret; if (flags==NV_UNKNOWN) return DRM_ERR(EINVAL); -- cgit v1.2.3 From ce0d528d3ca78348a7c1ad7c402757824fb6cf95 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 24 Jun 2007 20:49:19 +1000 Subject: nouveau/nv50: skeletal backend --- shared-core/drm_pciids.txt | 8 +++++ shared-core/nouveau_drv.h | 20 +++++++++++ shared-core/nouveau_state.c | 21 ++++++++++++ shared-core/nv50_fifo.c | 83 ++++++++++++++++++++++++++++++++++++++++++++ shared-core/nv50_graph.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ shared-core/nv50_mc.c | 42 +++++++++++++++++++++++ 6 files changed, 258 insertions(+) create mode 100644 shared-core/nv50_fifo.c create mode 100644 shared-core/nv50_graph.c create mode 100644 shared-core/nv50_mc.c (limited to 'shared-core') diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index ad9994ec..126974d0 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -596,6 +596,9 @@ 0x10de 0x018d NV_17 "GeForce4 448 Go" 0x10de 0x0191 NV_50 "GeForce 8800 GTX" 0x10de 0x0193 NV_50 "GeForce 8800 GTS" +0x10de 0x0194 NV_50 "GeForce 8800 Ultra" +0x10de 0x019d NV_50 "Quadro FX 5600" +0x10de 0x019e NV_50 "Quadro FX 4600" 0x10de 0x01a0 NV_11|NV_NFORCE "GeForce2 MX Integrated Graphics" 0x10de 0x01d1 NV_44 "GeForce 7300 LE" 0x10de 0x01d6 NV_44 "GeForce Go 7200" @@ -702,6 +705,11 @@ 0x10de 0x03d1 NV_44 "GeForce 6100 nForce 405" 0x10de 0x03d2 NV_44 "GeForce 6100 nForce 400" 0x10de 0x03d5 NV_44 "GeForce 6100 nForce 420" +0x10de 0x0400 NV_50 "GeForce 8600 GTS" +0x10de 0x0402 NV_50 "GeForce 8600 GT" +0x10de 0x0421 NV_50 "GeForce 8500 GT" +0x10de 0x0422 NV_50 "GeForce 8400 GS" +0x10de 0x0423 NV_50 "GeForce 8300 GS" 0x12d2 0x0008 NV_03 "NV1" 0x12d2 0x0009 NV_03 "DAC64" 0x12d2 0x0018 NV_03 "Riva128" diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 7a1ca3d5..f549e600 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -295,6 +295,14 @@ extern void nv40_fifo_destroy_context(drm_device_t *, int channel); extern int nv40_fifo_load_context(drm_device_t *, int channel); extern int nv40_fifo_save_context(drm_device_t *, int channel); +/* nv50_fifo.c */ +extern int nv50_fifo_init(drm_device_t *); +extern void nv50_fifo_takedown(drm_device_t *); +extern int nv50_fifo_create_context(drm_device_t *, int channel); +extern void nv50_fifo_destroy_context(drm_device_t *, int channel); +extern int nv50_fifo_load_context(drm_device_t *, int channel); +extern int nv50_fifo_save_context(drm_device_t *, int channel); + /* nv04_graph.c */ extern void nouveau_nv04_context_switch(drm_device_t *dev); extern int nv04_graph_init(drm_device_t *dev); @@ -338,6 +346,14 @@ extern void nv40_graph_destroy_context(drm_device_t *, int channel); extern int nv40_graph_load_context(drm_device_t *, int channel); extern int nv40_graph_save_context(drm_device_t *, int channel); +/* nv50_graph.c */ +extern int nv50_graph_init(drm_device_t *); +extern void nv50_graph_takedown(drm_device_t *); +extern int nv50_graph_create_context(drm_device_t *, int channel); +extern void nv50_graph_destroy_context(drm_device_t *, int channel); +extern int nv50_graph_load_context(drm_device_t *, int channel); +extern int nv50_graph_save_context(drm_device_t *, int channel); + /* nv04_mc.c */ extern int nv04_mc_init(drm_device_t *dev); extern void nv04_mc_takedown(drm_device_t *dev); @@ -346,6 +362,10 @@ extern void nv04_mc_takedown(drm_device_t *dev); extern int nv40_mc_init(drm_device_t *dev); extern void nv40_mc_takedown(drm_device_t *dev); +/* nv50_mc.c */ +extern int nv50_mc_init(drm_device_t *dev); +extern void nv50_mc_takedown(drm_device_t *dev); + /* nv04_timer.c */ extern int nv04_timer_init(drm_device_t *dev); extern void nv04_timer_takedown(drm_device_t *dev); diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 68392c3a..0cb82355 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -72,6 +72,7 @@ static int nouveau_init_card_mappings(drm_device_t *dev) return 0; } +static int nouveau_stub_init(drm_device_t *dev) { return 0; } static void nouveau_stub_takedown(drm_device_t *dev) {} static int nouveau_init_engine_ptrs(drm_device_t *dev) { @@ -187,6 +188,26 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) engine->fifo.save_context = nv40_fifo_save_context; break; case 0x50: + case 0x80: /* gotta love NVIDIA's consistency.. */ + engine->mc.init = nv50_mc_init; + engine->mc.takedown = nv50_mc_takedown; + engine->timer.init = nouveau_stub_init; + engine->timer.takedown = nouveau_stub_takedown; + engine->fb.init = nouveau_stub_init; + engine->fb.takedown = nouveau_stub_takedown; + engine->graph.init = nv50_graph_init; + engine->graph.takedown = nv50_graph_takedown; + engine->graph.create_context = nv50_graph_create_context; + engine->graph.destroy_context = nv50_graph_destroy_context; + engine->graph.load_context = nv50_graph_load_context; + engine->graph.save_context = nv50_graph_save_context; + engine->fifo.init = nv50_fifo_init; + engine->fifo.takedown = nv50_fifo_takedown; + engine->fifo.create_context = nv50_fifo_create_context; + engine->fifo.destroy_context = nv50_fifo_destroy_context; + engine->fifo.load_context = nv50_fifo_load_context; + engine->fifo.save_context = nv50_fifo_save_context; + break; default: DRM_ERROR("NV%02x unsupported\n", dev_priv->chipset); return 1; diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c new file mode 100644 index 00000000..e5d37949 --- /dev/null +++ b/shared-core/nv50_fifo.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2007 Ben Skeggs. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "drmP.h" +#include "drm.h" +#include "nouveau_drv.h" + +static void +nv50_fifo_init_reset(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t pmc_e; + + pmc_e = NV_READ(NV03_PMC_ENABLE); + NV_WRITE(NV03_PMC_ENABLE, pmc_e & ~NV_PMC_ENABLE_PFIFO); + pmc_e = NV_READ(NV03_PMC_ENABLE); + NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PFIFO); +} + +int +nv50_fifo_init(drm_device_t *dev) +{ + nv50_fifo_init_reset(dev); + + DRM_ERROR("stub!\n"); + return 0; +} + +void +nv50_fifo_takedown(drm_device_t *dev) +{ + DRM_ERROR("stub!\n"); +} + +int +nv50_fifo_create_context(drm_device_t *dev, int channel) +{ + DRM_ERROR("stub!\n"); + return 0; +} + +void +nv50_fifo_destroy_context(drm_device_t *dev, int channel) +{ +} + +int +nv50_fifo_load_context(drm_device_t *dev, int channel) +{ + DRM_ERROR("stub!\n"); + return 0; +} + +int +nv50_fifo_save_context(drm_device_t *dev, int channel) +{ + DRM_ERROR("stub!\n"); + return 0; +} + diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c new file mode 100644 index 00000000..8c3e2b9b --- /dev/null +++ b/shared-core/nv50_graph.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2007 Ben Skeggs. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "drmP.h" +#include "drm.h" +#include "nouveau_drv.h" + +static void +nv50_graph_init_reset(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t pmc_e; + + pmc_e = NV_READ(NV03_PMC_ENABLE); + NV_WRITE(NV03_PMC_ENABLE, pmc_e & ~NV_PMC_ENABLE_PGRAPH); + pmc_e = NV_READ(NV03_PMC_ENABLE); + NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PGRAPH); +} + +int +nv50_graph_init(drm_device_t *dev) +{ + nv50_graph_init_reset(dev); + + DRM_ERROR("stub!\n"); + return 0; +} + +void +nv50_graph_takedown(drm_device_t *dev) +{ + DRM_ERROR("stub!\n"); +} + +int +nv50_graph_create_context(drm_device_t *dev, int channel) +{ + DRM_ERROR("stub!\n"); + return 0; +} + +void +nv50_graph_destroy_context(drm_device_t *dev, int channel) +{ + DRM_ERROR("stub!\n"); +} + +int +nv50_graph_load_context(drm_device_t *dev, int channel) +{ + DRM_ERROR("stub!\n"); + return 0; +} + +int +nv50_graph_save_context(drm_device_t *dev, int channel) +{ + DRM_ERROR("stub!\n"); + return 0; +} + diff --git a/shared-core/nv50_mc.c b/shared-core/nv50_mc.c new file mode 100644 index 00000000..7f7537f0 --- /dev/null +++ b/shared-core/nv50_mc.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2007 Ben Skeggs. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "drmP.h" +#include "drm.h" +#include "nouveau_drv.h" + +int +nv50_mc_init(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + + NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF); + return 0; +} + +void nv50_mc_takedown(drm_device_t *dev) +{ +} -- cgit v1.2.3 From 38617b6a26d893bbd7b235019159e609f6cdd84b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 25 Jun 2007 03:52:06 +1000 Subject: nouveau: name some regs --- shared-core/nouveau_reg.h | 15 +++++++++++++++ shared-core/nv30_graph.c | 10 ++++++---- shared-core/nv40_graph.c | 29 +++++++++++++++++------------ 3 files changed, 38 insertions(+), 16 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index ba61f997..4c013c53 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -135,6 +135,17 @@ #define NV10_PGRAPH_CTX_CACHE4 0x004001C0 #define NV04_PGRAPH_CTX_CACHE4 0x004001E0 #define NV10_PGRAPH_CTX_CACHE5 0x004001E0 +#define NV40_PGRAPH_CTXCTL_0304 0x00400304 +#define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001 +#define NV40_PGRAPH_CTXCTL_0310 0x00400310 +#define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE 0x00000020 +#define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD 0x00000040 +#define NV40_PGRAPH_CTXCTL_030C 0x0040030c +#define NV40_PGRAPH_CTXCTL_UCODE_INDEX 0x00400324 +#define NV40_PGRAPH_CTXCTL_UCODE_DATA 0x00400328 +#define NV40_PGRAPH_CTXCTL_CUR 0x0040032c +#define NV40_PGRAPH_CTXCTL_CUR_LOADED 0x01000000 +#define NV40_PGRAPH_CTXCTL_CUR_INST_MASK 0x000FFFFF #define NV03_PGRAPH_ABS_X_RAM 0x00400400 #define NV03_PGRAPH_ABS_Y_RAM 0x00400480 #define NV03_PGRAPH_X_MISC 0x00400500 @@ -230,7 +241,11 @@ #define NV10_PGRAPH_SCALED_FORMAT 0x00400778 #define NV10_PGRAPH_CHANNEL_CTX_TABLE 0x00400780 #define NV10_PGRAPH_CHANNEL_CTX_SIZE 0x00400784 +#define NV20_PGRAPH_CHANNEL_CTX_POINTER 0x00400784 #define NV10_PGRAPH_CHANNEL_CTX_POINTER 0x00400788 +#define NV20_PGRAPH_CHANNEL_CTX_XFER 0x00400788 +#define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD 0x00000001 +#define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE 0x00000002 #define NV04_PGRAPH_PATT_COLOR0 0x00400800 #define NV04_PGRAPH_PATT_COLOR1 0x00400804 #define NV04_PGRAPH_PATTERN 0x00400808 diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index 9f064a0a..7a87990a 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -174,8 +174,9 @@ int nv30_graph_load_context(drm_device_t *dev, int channel) return DRM_ERR(EINVAL); inst = nouveau_chip_instance_get(dev, chan->ramin_grctx); - NV_WRITE(0x400784, inst); - NV_WRITE(0x400788, 1); + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER, + NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD); return nouveau_graph_wait_idle(dev); } @@ -190,8 +191,9 @@ int nv30_graph_save_context(drm_device_t *dev, int channel) return DRM_ERR(EINVAL); inst = nouveau_chip_instance_get(dev, chan->ramin_grctx); - NV_WRITE(0x400784, inst); - NV_WRITE(0x400788, 2); + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER, + NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE); return nouveau_graph_wait_idle(dev); } diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index acd0cb0f..6fb575db 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -1304,20 +1304,23 @@ nv40_graph_transfer_context(drm_device_t *dev, uint32_t inst, int save) uint32_t old_cp, tv = 1000; int i; - old_cp = NV_READ(0x400784); - NV_WRITE(0x400784, inst); - NV_WRITE(0x400310, save ? 0x20 : 0x40); - NV_WRITE(0x400304, 1); + old_cp = NV_READ(NV20_PGRAPH_CHANNEL_CTX_POINTER); + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); + NV_WRITE(NV40_PGRAPH_CTXCTL_0310, + save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE : + NV40_PGRAPH_CTXCTL_0310_XFER_LOAD); + NV_WRITE(NV40_PGRAPH_CTXCTL_0304, NV40_PGRAPH_CTXCTL_0304_XFER_CTX); for (i = 0; i < tv; i++) { - if (NV_READ(0x40030c) == 0) + if (NV_READ(NV40_PGRAPH_CTXCTL_030C) == 0) break; } - NV_WRITE(0x400784, old_cp); + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp); if (i == tv) { DRM_ERROR("failed: inst=0x%08x save=%d\n", inst, save); - DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030c)); + DRM_ERROR("0x40030C = 0x%08x\n", + NV_READ(NV40_PGRAPH_CTXCTL_030C)); return DRM_ERR(EBUSY); } @@ -1365,8 +1368,10 @@ nv40_graph_load_context(drm_device_t *dev, int channel) * unknown as to what bit 24 does. The nv ddx has it set, so we will * set it here too. */ - NV_WRITE(0x400784, inst); - NV_WRITE(0x40032C, inst | 0x01000000); + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); + NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, + (inst & NV40_PGRAPH_CTXCTL_CUR_INST_MASK) | + NV40_PGRAPH_CTXCTL_CUR_LOADED); /* 0x32E0 records the instance address of the active FIFO's PGRAPH * context. If at any time this doesn't match 0x40032C, you will * recieve PGRAPH_INTR_CONTEXT_SWITCH @@ -1631,15 +1636,15 @@ nv40_graph_init(drm_device_t *dev) DRM_DEBUG("Loading context-switch voodoo\n"); i = 0; - NV_WRITE(0x400324, 0); + NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0); while (ctx_voodoo[i] != ~0) { - NV_WRITE(0x400328, ctx_voodoo[i]); + NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, ctx_voodoo[i]); i++; } } /* No context present currently */ - NV_WRITE(0x40032C, 0x00000000); + NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, 0x00000000); NV_WRITE(NV03_PGRAPH_INTR_EN, 0x00000000); NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); -- cgit v1.2.3 From 18a6d1c9c380b6b19524f654d9173a79e19aa1df Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 25 Jun 2007 15:16:19 +1000 Subject: nouveau: simplify PRAMIN access --- shared-core/nouveau_drv.h | 18 +++++++++++------- shared-core/nouveau_mem.c | 32 -------------------------------- shared-core/nouveau_state.c | 18 ++++++++++++++++-- 3 files changed, 27 insertions(+), 41 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index f549e600..b2ddf0a6 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -220,11 +220,6 @@ extern struct mem_block* nouveau_instmem_alloc(struct drm_device *dev, uint32_t size, uint32_t align); extern void nouveau_instmem_free(struct drm_device *dev, struct mem_block *block); -extern uint32_t nouveau_instmem_r32(drm_nouveau_private_t *dev_priv, - struct mem_block *mem, int index); -extern void nouveau_instmem_w32(drm_nouveau_private_t *dev_priv, - struct mem_block *mem, int index, - uint32_t val); /* nouveau_notifier.c */ extern int nouveau_notifier_init_channel(drm_device_t *, int channel, DRMFILE); @@ -381,8 +376,17 @@ extern long nouveau_compat_ioctl(struct file *filp, unsigned int cmd, #define NV_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) #endif -#define INSTANCE_WR(mem,ofs,val) nouveau_instmem_w32(dev_priv,(mem),(ofs),(val)) -#define INSTANCE_RD(mem,ofs) nouveau_instmem_r32(dev_priv,(mem),(ofs)) +/* PRAMIN access */ +#if defined(__powerpc__) +#define NV_RI32(o) in_be32((void __iomem *)(dev_priv->ramin)->handle+(o)) +#define NV_WI32(o,v) out_be32((void __iomem*)(dev_priv->ramin)->handle+(o), (v)) +#else +#define NV_RI32(o) DRM_READ32(dev_priv->ramin, (o)) +#define NV_WI32(o,v) DRM_WRITE32(dev_priv->ramin, (o), (v)) +#endif + +#define INSTANCE_RD(o,i) NV_RI32((o)->start + ((i)<<2)) +#define INSTANCE_WR(o,i,v) NV_WI32((o)->start + ((i)<<2), (v)) #endif /* __NOUVEAU_DRV_H__ */ diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index edfc9d3f..4c6d0d5c 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -602,38 +602,6 @@ void nouveau_instmem_free(struct drm_device *dev, struct mem_block *block) } } -uint32_t nouveau_instmem_r32(drm_nouveau_private_t *dev_priv, - struct mem_block *mem, int index) -{ - uint32_t ofs = (uint32_t)mem->start + (index<<2); - - if (dev_priv->ramin) { -#if defined(__powerpc__) - return in_be32((void __iomem *)(dev_priv->ramin)->handle + ofs); -#else - return DRM_READ32(dev_priv->ramin, ofs); -#endif - } else { - return NV_READ(NV_RAMIN+ofs); - } -} - -void nouveau_instmem_w32(drm_nouveau_private_t *dev_priv, - struct mem_block *mem, int index, uint32_t val) -{ - uint32_t ofs = (uint32_t)mem->start + (index<<2); - - if (dev_priv->ramin) { -#if defined(__powerpc__) - out_be32((void __iomem *)(dev_priv->ramin)->handle + ofs, val); -#else - DRM_WRITE32(dev_priv->ramin, ofs, val); -#endif - } else { - NV_WRITE(NV_RAMIN+ofs, val); - } -} - /* * Ioctls */ diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 0cb82355..94d8081c 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -51,6 +51,7 @@ static int nouveau_init_card_mappings(drm_device_t *dev) DRM_DEBUG("regs mapped ok at 0x%lx\n", dev_priv->mmio->offset); /* map larger RAMIN aperture on NV40 cards */ + dev_priv->ramin = NULL; if (dev_priv->card_type >= NV_40) { int ramin_resource = 2; if (drm_get_resource_len(dev, ramin_resource) == 0) @@ -66,8 +67,21 @@ static int nouveau_init_card_mappings(drm_device_t *dev) "limited instance memory available\n"); dev_priv->ramin = NULL; } - } else - dev_priv->ramin = NULL; + } + + /* On older cards (or if the above failed), create a map covering + * the BAR0 PRAMIN aperture */ + if (!dev_priv->ramin) { + ret = drm_addmap(dev, + drm_get_resource_start(dev, 0) + NV_RAMIN, + (1*1024*1024), + _DRM_REGISTERS, _DRM_READ_ONLY, + &dev_priv->ramin); + if (ret) { + DRM_ERROR("Failed to map BAR0 PRAMIN: %d\n", ret); + return ret; + } + } return 0; } -- cgit v1.2.3 From 68ecf61647e9ec16d59cc8f50550d11478eb3118 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 25 Jun 2007 15:42:55 +1000 Subject: nouveau: never touch PRAMIN with NV_WRITE, cleanup RAMHT code a bit --- shared-core/nouveau_drv.h | 5 +- shared-core/nouveau_mem.c | 9 +-- shared-core/nouveau_notifier.c | 2 +- shared-core/nouveau_object.c | 133 +++++++++++++++++++++++++---------------- shared-core/nv04_fifo.c | 10 ++-- shared-core/nv10_fifo.c | 16 ++--- shared-core/nv40_fifo.c | 16 ++--- 7 files changed, 106 insertions(+), 85 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index b2ddf0a6..3cca07fc 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -64,7 +64,6 @@ struct nouveau_object int channel; struct mem_block *instance; - uint32_t ht_loc; uint32_t handle; int class; @@ -242,8 +241,8 @@ extern int nouveau_object_init_channel(drm_device_t *, int channel, uint32_t tt_handle); extern void nouveau_object_takedown_channel(drm_device_t *dev, int channel); extern void nouveau_object_cleanup(drm_device_t *dev, int channel); -extern int nouveau_ht_object_insert(drm_device_t *, int channel, - uint32_t handle, struct nouveau_object *); +extern int nouveau_ramht_insert(drm_device_t *, int channel, + uint32_t handle, struct nouveau_object *); extern struct nouveau_object * nouveau_object_gr_create(drm_device_t *dev, int channel, int class); extern struct nouveau_object * diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 4c6d0d5c..d8ae52b7 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -489,13 +489,8 @@ nouveau_instmem_determine_amount(struct drm_device *dev) DRM_DEBUG("RAMIN size: %dKiB\n", dev_priv->ramin_size>>10); /* Clear all of it, except the BIOS image that's in the first 64KiB */ - if (dev_priv->ramin) { - for (i=(64*1024); iramin_size; i+=4) - DRM_WRITE32(dev_priv->ramin, i, 0x00000000); - } else { - for (i=(64*1024); iramin_size; i+=4) - DRM_WRITE32(dev_priv->mmio, NV_RAMIN + i, 0x00000000); - } + for (i=(64*1024); iramin_size; i+=4) + NV_WI32(i, 0x00000000); } static void diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index ab6f8c2d..0cfe733e 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -115,7 +115,7 @@ nouveau_notifier_alloc(drm_device_t *dev, int channel, uint32_t handle, } obj->handle = handle; - if (nouveau_ht_object_insert(dev, channel, handle, obj)) { + if (nouveau_ramht_insert(dev, channel, handle, obj)) { nouveau_object_free(dev, obj); nouveau_mem_free_block(mem); DRM_ERROR("Error inserting notifier ctxdma into RAMHT\n"); diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index e7528e23..dac08df4 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -139,7 +139,7 @@ nouveau_object_handle_find(drm_device_t *dev, int channel, uint32_t handle) is given as: */ static uint32_t -nouveau_ht_handle_hash(drm_device_t *dev, int channel, uint32_t handle) +nouveau_ramht_hash_handle(drm_device_t *dev, int channel, uint32_t handle) { drm_nouveau_private_t *dev_priv=dev->dev_private; uint32_t hash = 0; @@ -153,63 +153,90 @@ nouveau_ht_handle_hash(drm_device_t *dev, int channel, uint32_t handle) return hash << 3; } +static int +nouveau_ramht_entry_valid(drm_device_t *dev, uint32_t ramht, uint32_t offset) +{ + drm_nouveau_private_t *dev_priv=dev->dev_private; + uint32_t ctx = NV_RI32(ramht + offset + 4); + + if (dev_priv->card_type < NV_40) + return ((ctx & NV_RAMHT_CONTEXT_VALID) != 0); + return (ctx != 0); +} + int -nouveau_ht_object_insert(drm_device_t* dev, int channel, uint32_t handle, - struct nouveau_object *obj) +nouveau_ramht_insert(drm_device_t* dev, int channel, uint32_t handle, + struct nouveau_object *obj) { drm_nouveau_private_t *dev_priv=dev->dev_private; - int ht_base = NV_RAMIN + dev_priv->ramht_offset; -/* int ht_end = ht_base + dev_priv->ramht_size; */ - int o_ofs, ofs; - - obj->handle = handle; - o_ofs = ofs = nouveau_ht_handle_hash(dev, channel, obj->handle); - - while (NV_READ(ht_base + ofs) || NV_READ(ht_base + ofs + 4)) { - ofs += 8; - if (ofs == dev_priv->ramht_size) ofs = 0; - if (ofs == o_ofs) { - DRM_ERROR("no free hash table entries\n"); - return 1; - } + uint32_t ramht = dev_priv->ramht_offset; + uint32_t ctx, co, ho; + uint32_t inst; + + inst = nouveau_chip_instance_get(dev, obj->instance); + if (dev_priv->card_type < NV_40) { + ctx = NV_RAMHT_CONTEXT_VALID | inst | + (channel << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) | + (obj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT); + } else + if (dev_priv->card_type < NV_50) { + ctx = inst | + (channel << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) | + (obj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT); + } else { + ctx = inst | + (obj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT); } - ofs += ht_base; - - DRM_DEBUG("Channel %d - Handle 0x%08x at 0x%08x\n", - channel, obj->handle, ofs); - - NV_WRITE(NV_RAMHT_HANDLE_OFFSET + ofs, obj->handle); - if (dev_priv->card_type >= NV_40) - NV_WRITE(NV_RAMHT_CONTEXT_OFFSET + ofs, - (channel << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) | - (obj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT) | - nouveau_chip_instance_get(dev, obj->instance) - ); - else - NV_WRITE(NV_RAMHT_CONTEXT_OFFSET + ofs, - NV_RAMHT_CONTEXT_VALID | - (channel << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) | - (obj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT) | - nouveau_chip_instance_get(dev, obj->instance) - ); - - obj->ht_loc = ofs; - return 0; + + co = ho = nouveau_ramht_hash_handle(dev, channel, handle); + do { + if (!nouveau_ramht_entry_valid(dev, ramht, co)) { + DRM_DEBUG("insert ch%d 0x%08x: h=0x%08x, c=0x%08x\n", + channel, co, handle, ctx); + NV_WI32(ramht + co + 0, handle); + NV_WI32(ramht + co + 4, ctx); + obj->handle = handle; + return 0; + } + DRM_DEBUG("collision ch%d 0x%08x: h=0x%08x\n", + channel, co, NV_RI32(ramht + co)); + + co += 8; + if (co == dev_priv->ramht_size) + co = 0; + } while (co != ho); + + DRM_ERROR("RAMHT space exhausted. ch=%d\n", channel); + return DRM_ERR(ENOMEM); } -static void nouveau_hash_table_remove(drm_device_t* dev, - struct nouveau_object *obj) +static void +nouveau_ramht_remove(drm_device_t* dev, struct nouveau_object *obj) { drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t ramht = dev_priv->ramht_offset; + uint32_t co, ho; + + co = ho = nouveau_ramht_hash_handle(dev, obj->channel, obj->handle); + do { + if (nouveau_ramht_entry_valid(dev, ramht, co) && + (obj->handle == NV_RI32(ramht + co))) { + DRM_DEBUG("remove ch%d 0x%08x: h=0x%08x, c=0x%08x\n", + obj->channel, co, obj->handle, + NV_RI32(ramht + co + 4)); + NV_WI32(ramht + co + 0, 0x00000000); + NV_WI32(ramht + co + 4, 0x00000000); + obj->handle = ~0; + return; + } - DRM_DEBUG("Remove handle 0x%08x at 0x%08x from HT\n", - obj->handle, obj->ht_loc); - if (obj->ht_loc) { - DRM_DEBUG("... HT entry was: 0x%08x/0x%08x\n", - NV_READ(obj->ht_loc), NV_READ(obj->ht_loc+4)); - NV_WRITE(obj->ht_loc , 0x00000000); - NV_WRITE(obj->ht_loc+4, 0x00000000); - } + co += 8; + if (co == dev_priv->ramht_size) + co = 0; + } while (co != ho); + + DRM_ERROR("RAMHT entry not found. ch=%d, handle=0x%08x\n", + obj->channel, obj->handle); } static struct nouveau_object * @@ -457,7 +484,7 @@ nouveau_object_free(drm_device_t *dev, struct nouveau_object *obj) { nouveau_object_instance_free(dev, obj); if (obj->handle != ~0) - nouveau_hash_table_remove(dev, obj); + nouveau_ramht_remove(dev, obj); drm_free(obj, sizeof(struct nouveau_object), DRM_MEM_DRIVER); } @@ -480,7 +507,7 @@ nouveau_object_init_channel(drm_device_t *dev, int channel, return DRM_ERR(ENOMEM); } - ret = nouveau_ht_object_insert(dev, channel, vram_handle, gpuobj); + ret = nouveau_ramht_insert(dev, channel, vram_handle, gpuobj); if (ret) { DRM_ERROR("Error referencing VRAM ctxdma: %d\n", ret); return ret; @@ -500,7 +527,7 @@ nouveau_object_init_channel(drm_device_t *dev, int channel, return DRM_ERR(ENOMEM); } - ret = nouveau_ht_object_insert(dev, channel, tt_handle, gpuobj); + ret = nouveau_ramht_insert(dev, channel, tt_handle, gpuobj); if (ret) { DRM_ERROR("Error referencing TT ctxdma: %d\n", ret); return ret; @@ -545,7 +572,7 @@ int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS) if (!obj) return DRM_ERR(ENOMEM); - if (nouveau_ht_object_insert(dev, init.channel, init.handle, obj)) { + if (nouveau_ramht_insert(dev, init.channel, init.handle, obj)) { nouveau_object_free(dev, obj); return DRM_ERR(ENOMEM); } diff --git a/shared-core/nv04_fifo.c b/shared-core/nv04_fifo.c index 783514a7..57010182 100644 --- a/shared-core/nv04_fifo.c +++ b/shared-core/nv04_fifo.c @@ -28,9 +28,9 @@ #include "drm.h" #include "nouveau_drv.h" -#define NV04_RAMFC (NV_RAMIN + dev_priv->ramfc_offset) -#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV04_RAMFC_##offset, (val)) -#define RAMFC_RD(offset) NV_READ(fifoctx + NV04_RAMFC_##offset) +#define NV04_RAMFC dev_priv->ramfc_offset +#define RAMFC_WR(offset, val) NV_WI32(fifoctx + NV04_RAMFC_##offset, (val)) +#define RAMFC_RD(offset) NV_RI32(fifoctx + NV04_RAMFC_##offset) #define NV04_FIFO_CONTEXT_SIZE 32 int @@ -47,7 +47,7 @@ nv04_fifo_create_context(drm_device_t *dev, int channel) /* Clear RAMFC */ for (i=0; ipushbuf_base); @@ -72,7 +72,7 @@ nv04_fifo_destroy_context(drm_device_t *dev, int channel) fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE); for (i=0; icmdbuf_obj->instance); - fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64; + fifoctx = dev_priv->ramfc_offset + channel*64; for (i=0; iramfc_offset + channel*64; + fifoctx = dev_priv->ramfc_offset + channel*64; for (i=0; iramfc_offset + channel*64; + fifoctx = dev_priv->ramfc_offset + channel*64; NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00000100 | channel); @@ -118,7 +118,7 @@ nv10_fifo_save_context(drm_device_t *dev, int channel) uint32_t fifoctx; uint32_t tmp; - fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64; + fifoctx = dev_priv->ramfc_offset + channel*64; RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c index 9d7afbe5..945fe228 100644 --- a/shared-core/nv40_fifo.c +++ b/shared-core/nv40_fifo.c @@ -28,8 +28,8 @@ #include "nouveau_drv.h" #include "nouveau_drm.h" -#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV40_RAMFC_##offset, (val)) -#define RAMFC_RD(offset) NV_READ (fifoctx + NV40_RAMFC_##offset) +#define RAMFC_WR(offset, val) NV_WI32(fifoctx + NV40_RAMFC_##offset, (val)) +#define RAMFC_RD(offset) NV_RI32(fifoctx + NV40_RAMFC_##offset) int nv40_fifo_create_context(drm_device_t *dev, int channel) @@ -39,9 +39,9 @@ nv40_fifo_create_context(drm_device_t *dev, int channel) uint32_t fifoctx, grctx, pushbuf; int i; - fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128; + fifoctx = dev_priv->ramfc_offset + channel*128; for (i=0;i<128;i+=4) - NV_WRITE(fifoctx + i, 0); + NV_WI32(fifoctx + i, 0); grctx = nouveau_chip_instance_get(dev, chan->ramin_grctx); pushbuf = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance); @@ -73,9 +73,9 @@ nv40_fifo_destroy_context(drm_device_t *dev, int channel) uint32_t fifoctx; int i; - fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128; + fifoctx = dev_priv->ramfc_offset + channel*128; for (i=0;i<128;i+=4) - NV_WRITE(fifoctx + i, 0); + NV_WI32(fifoctx + i, 0); } int @@ -85,7 +85,7 @@ nv40_fifo_load_context(drm_device_t *dev, int channel) uint32_t fifoctx; uint32_t tmp, tmp2; - fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128; + fifoctx = dev_priv->ramfc_offset + channel*128; NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET)); NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT , RAMFC_RD(DMA_PUT)); @@ -146,7 +146,7 @@ nv40_fifo_save_context(drm_device_t *dev, int channel) uint32_t fifoctx; uint32_t tmp; - fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128; + fifoctx = dev_priv->ramfc_offset + channel*128; RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); -- cgit v1.2.3 From 2dd85772aa4e134730f294d77b4ff030a175a4ab Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 28 Jun 2007 04:23:17 +1000 Subject: nouveau/nv10: Fix earlier NV1x chips Can't use nv04 code for them, since an extra field was inserted into RAMFC after DMA_PUT/GET. --- shared-core/nouveau_state.c | 7 ------ shared-core/nv10_fifo.c | 57 +++++++++++++++++++++++++++------------------ 2 files changed, 34 insertions(+), 30 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 94d8081c..fa773d28 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -129,17 +129,10 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) engine->graph.save_context = nv10_graph_save_context; engine->fifo.init = nouveau_fifo_init; engine->fifo.takedown = nouveau_stub_takedown; - if (dev_priv->chipset < 0x17) { - engine->fifo.create_context = nv04_fifo_create_context; - engine->fifo.destroy_context = nv04_fifo_destroy_context; - engine->fifo.load_context = nv04_fifo_load_context; - engine->fifo.save_context = nv04_fifo_save_context; - } else { engine->fifo.create_context = nv10_fifo_create_context; engine->fifo.destroy_context = nv10_fifo_destroy_context; engine->fifo.load_context = nv10_fifo_load_context; engine->fifo.save_context = nv10_fifo_save_context; - } break; case 0x20: engine->mc.init = nv04_mc_init; diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c index 710a47f7..b84971de 100644 --- a/shared-core/nv10_fifo.c +++ b/shared-core/nv10_fifo.c @@ -30,20 +30,20 @@ #define RAMFC_WR(offset, val) NV_WI32(fifoctx + NV10_RAMFC_##offset, (val)) #define RAMFC_RD(offset) NV_RI32(fifoctx + NV10_RAMFC_##offset) -#define NV10_FIFO_CONTEXT_SIZE 64 +#define NV10_RAMFC(c) (dev_priv->ramfc_offset + NV10_RAMFC__SIZE) +#define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32) int nv10_fifo_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - uint32_t fifoctx, pushbuf; + uint32_t fifoctx = NV10_RAMFC(channel), pushbuf; int i; pushbuf = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance); - fifoctx = dev_priv->ramfc_offset + channel*64; - for (i=0; idev_private; - uint32_t fifoctx; + uint32_t fifoctx = NV10_RAMFC(channel); int i; - fifoctx = dev_priv->ramfc_offset + channel*64; - for (i=0; idev_private; - uint32_t fifoctx; + uint32_t fifoctx = NV10_RAMFC(channel); uint32_t tmp; - fifoctx = dev_priv->ramfc_offset + channel*64; - NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00000100 | channel); NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET)); @@ -98,11 +95,19 @@ nv10_fifo_load_context(drm_device_t *dev, int channel) NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH , RAMFC_RD(DMA_FETCH)); NV_WRITE(NV04_PFIFO_CACHE1_ENGINE , RAMFC_RD(ENGINE)); NV_WRITE(NV04_PFIFO_CACHE1_PULL1 , RAMFC_RD(PULL1_ENGINE)); - NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE , RAMFC_RD(ACQUIRE_VALUE)); - NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, RAMFC_RD(ACQUIRE_TIMESTAMP)); - NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT , RAMFC_RD(ACQUIRE_TIMEOUT)); - NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE , RAMFC_RD(SEMAPHORE)); - NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE , RAMFC_RD(DMA_SUBROUTINE)); + + if (dev_priv->chipset >= 0x17) { + NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE, + RAMFC_RD(ACQUIRE_VALUE)); + NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, + RAMFC_RD(ACQUIRE_TIMESTAMP)); + NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT, + RAMFC_RD(ACQUIRE_TIMEOUT)); + NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE, + RAMFC_RD(SEMAPHORE)); + NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE, + RAMFC_RD(DMA_SUBROUTINE)); + } /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */ tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31); @@ -115,11 +120,9 @@ int nv10_fifo_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx; + uint32_t fifoctx = NV10_RAMFC(channel); uint32_t tmp; - fifoctx = dev_priv->ramfc_offset + channel*64; - RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT)); @@ -132,11 +135,19 @@ nv10_fifo_save_context(drm_device_t *dev, int channel) RAMFC_WR(DMA_FETCH , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH)); RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE)); RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1)); - RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE)); - RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP)); - RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT)); - RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE)); - RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); + + if (dev_priv->chipset >= 0x17) { + RAMFC_WR(ACQUIRE_VALUE, + NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE)); + RAMFC_WR(ACQUIRE_TIMESTAMP, + NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP)); + RAMFC_WR(ACQUIRE_TIMEOUT, + NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT)); + RAMFC_WR(SEMAPHORE, + NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE)); + RAMFC_WR(DMA_SUBROUTINE, + NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); + } return 0; } -- cgit v1.2.3 From 1c32fecd6d2286af075976167c4887b9096e8312 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 28 Jun 2007 21:01:17 +1000 Subject: nouveau: Hack around possible Xv blit adaptor breakage --- shared-core/nouveau_fifo.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index f179af63..81dbfcda 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -341,6 +341,19 @@ int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp, nouveau_fifo_free(dev, channel); return ret; } + + /* Temporary hack, to avoid breaking Xv on cards where the + * initial context value for 0x400710 doesn't have these bits + * set. Proper fix would be to find which object+method is + * responsible for modifying this state. + */ + if (dev_priv->chipset >= 0x10) { + uint32_t tmp; + tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; + NV_WRITE(NV10_PGRAPH_SURFACE, tmp); + tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100; + NV_WRITE(NV10_PGRAPH_SURFACE, tmp); + } } NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001); -- cgit v1.2.3 From e26ec51146e77eec2a45f61c9506e9800fc2fba2 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 29 Jun 2007 13:52:55 +1000 Subject: nouveau: small RAMFC cleanups --- shared-core/nv04_fifo.c | 17 ++++++++--------- shared-core/nv40_fifo.c | 20 ++++++++------------ 2 files changed, 16 insertions(+), 21 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv04_fifo.c b/shared-core/nv04_fifo.c index 57010182..bfae432e 100644 --- a/shared-core/nv04_fifo.c +++ b/shared-core/nv04_fifo.c @@ -28,10 +28,10 @@ #include "drm.h" #include "nouveau_drv.h" -#define NV04_RAMFC dev_priv->ramfc_offset #define RAMFC_WR(offset, val) NV_WI32(fifoctx + NV04_RAMFC_##offset, (val)) #define RAMFC_RD(offset) NV_RI32(fifoctx + NV04_RAMFC_##offset) -#define NV04_FIFO_CONTEXT_SIZE 32 +#define NV04_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV04_RAMFC__SIZE)) +#define NV04_RAMFC__SIZE 32 int nv04_fifo_create_context(drm_device_t *dev, int channel) @@ -39,14 +39,14 @@ nv04_fifo_create_context(drm_device_t *dev, int channel) drm_nouveau_private_t *dev_priv = dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; struct nouveau_object *pb = chan->cmdbuf_obj; - int fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE); + uint32_t fifoctx = NV04_RAMFC(channel); int i; if (!pb || !pb->instance) return DRM_ERR(EINVAL); /* Clear RAMFC */ - for (i=0; idev_private; - uint32_t fifoctx; + uint32_t fifoctx = NV04_RAMFC(channel); int i; - fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE); - for (i=0; idev_private; - int fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE); + uint32_t fifoctx = NV04_RAMFC(channel); uint32_t tmp; NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, (1<<8) | channel); @@ -107,7 +106,7 @@ int nv04_fifo_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - int fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE); + uint32_t fifoctx = NV04_RAMFC(channel); uint32_t tmp; RAMFC_WR(DMA_PUT, NV04_PFIFO_CACHE1_DMA_PUT); diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c index 945fe228..6f25349c 100644 --- a/shared-core/nv40_fifo.c +++ b/shared-core/nv40_fifo.c @@ -30,17 +30,18 @@ #define RAMFC_WR(offset, val) NV_WI32(fifoctx + NV40_RAMFC_##offset, (val)) #define RAMFC_RD(offset) NV_RI32(fifoctx + NV40_RAMFC_##offset) +#define NV40_RAMFC(c) (dev_priv->ramfc_offset + ((c)*NV40_RAMFC__SIZE)) +#define NV40_RAMFC__SIZE 128 int nv40_fifo_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - uint32_t fifoctx, grctx, pushbuf; + uint32_t fifoctx = NV40_RAMFC(channel), grctx, pushbuf; int i; - fifoctx = dev_priv->ramfc_offset + channel*128; - for (i=0;i<128;i+=4) + for (i = 0; i < NV40_RAMFC__SIZE; i+=4) NV_WI32(fifoctx + i, 0); grctx = nouveau_chip_instance_get(dev, chan->ramin_grctx); @@ -70,11 +71,10 @@ void nv40_fifo_destroy_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx; + uint32_t fifoctx = NV40_RAMFC(channel); int i; - fifoctx = dev_priv->ramfc_offset + channel*128; - for (i=0;i<128;i+=4) + for (i = 0; i < NV40_RAMFC__SIZE; i+=4) NV_WI32(fifoctx + i, 0); } @@ -82,11 +82,9 @@ int nv40_fifo_load_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx; + uint32_t fifoctx = NV40_RAMFC(channel); uint32_t tmp, tmp2; - fifoctx = dev_priv->ramfc_offset + channel*128; - NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET)); NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT , RAMFC_RD(DMA_PUT)); NV_WRITE(NV10_PFIFO_CACHE1_REF_CNT , RAMFC_RD(REF_CNT)); @@ -143,11 +141,9 @@ int nv40_fifo_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx; + uint32_t fifoctx = NV40_RAMFC(channel); uint32_t tmp; - fifoctx = dev_priv->ramfc_offset + channel*128; - RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT)); -- cgit v1.2.3 From 91990946fa3f7e8e725af18d1f3a63e0c7892308 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Tue, 3 Jul 2007 12:33:51 +0200 Subject: One more spinlock initializer cleanup. --- shared-core/i915_irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c index dc00f983..2f6a6b95 100644 --- a/shared-core/i915_irq.c +++ b/shared-core/i915_irq.c @@ -719,7 +719,7 @@ void i915_driver_irq_postinstall(drm_device_t * dev) INIT_LIST_HEAD(&dev_priv->vbl_swaps.head); dev_priv->swaps_pending = 0; - dev_priv->user_irq_lock = SPIN_LOCK_UNLOCKED; + spin_lock_init(&dev_priv->user_irq_lock); dev_priv->user_irq_refcount = 0; i915_enable_interrupt(dev); -- cgit v1.2.3 From 163f8526123ffa38783fc911b5f7a19debce7f73 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 2 Jul 2007 19:31:18 +1000 Subject: nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object. --- shared-core/nouveau_drv.h | 118 ++++-- shared-core/nouveau_fifo.c | 66 ++-- shared-core/nouveau_mem.c | 9 +- shared-core/nouveau_notifier.c | 24 +- shared-core/nouveau_object.c | 827 ++++++++++++++++++++++++++++------------- shared-core/nouveau_state.c | 20 +- shared-core/nv04_fifo.c | 35 +- shared-core/nv10_fifo.c | 33 +- shared-core/nv20_graph.c | 53 ++- shared-core/nv30_graph.c | 53 ++- shared-core/nv40_fifo.c | 36 +- shared-core/nv40_graph.c | 58 ++- 12 files changed, 844 insertions(+), 488 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 3cca07fc..73793b34 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -57,18 +57,38 @@ enum nouveau_flags { NV_NFORCE2 =0x20000000 }; -struct nouveau_object -{ - struct nouveau_object *next; - struct nouveau_object *prev; - int channel; +#define NVOBJ_ENGINE_SW 0 +#define NVOBJ_ENGINE_GR 1 +#define NVOBJ_ENGINE_INT 0xdeadbeef - struct mem_block *instance; +#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0) +#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) +#define NVOBJ_FLAG_ZERO_FREE (1 << 2) +#define NVOBJ_FLAG_FAKE (1 << 3) +typedef struct nouveau_gpuobj { + struct nouveau_gpuobj *next; + struct nouveau_gpuobj *prev; - uint32_t handle; - int class; - int engine; -}; + int im_channel; + struct mem_block *im_pramin; + struct mem_block *im_backing; + + uint32_t flags; + int refcount; + + uint32_t engine; + uint32_t class; +} nouveau_gpuobj_t; + +typedef struct nouveau_gpuobj_ref { + struct nouveau_gpuobj_ref *next; + + nouveau_gpuobj_t *gpuobj; + uint32_t instance; + + int channel; + int handle; +} nouveau_gpuobj_ref_t; struct nouveau_fifo { @@ -79,21 +99,29 @@ struct nouveau_fifo drm_local_map_t *map; /* mapping of the regs controling the fifo */ drm_local_map_t *regs; - /* dma object for the command buffer itself */ - struct mem_block *cmdbuf_mem; - struct nouveau_object *cmdbuf_obj; - uint32_t pushbuf_base; - /* notifier memory */ + + /* DMA push buffer */ + struct mem_block *cmdbuf_mem; + nouveau_gpuobj_ref_t *pushbuf; + uint32_t pushbuf_base; + + /* Notifier memory */ struct mem_block *notifier_block; struct mem_block *notifier_heap; drm_local_map_t *notifier_map; - /* PGRAPH context, for cards that keep it in RAMIN */ - struct mem_block *ramin_grctx; - /* objects belonging to this fifo */ - struct nouveau_object *objs; - /* XXX dynamic alloc ? */ - uint32_t pgraph_ctx [340]; + /* PFIFO context */ + nouveau_gpuobj_ref_t *ramfc; + + /* PGRAPH context */ + nouveau_gpuobj_ref_t *ramin_grctx; + uint32_t pgraph_ctx [340]; /* XXX dynamic alloc ? */ + + /* Objects */ + nouveau_gpuobj_ref_t *ramin; /* Private instmem */ + struct mem_block *ramin_heap; /* Private PRAMIN heap */ + nouveau_gpuobj_ref_t *ramht; /* Hash table */ + nouveau_gpuobj_ref_t *ramht_refs; /* Objects referenced by RAMHT */ }; struct nouveau_config { @@ -157,6 +185,7 @@ typedef struct drm_nouveau_private { struct nouveau_engine_func Engine; /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ + nouveau_gpuobj_t *ramht; uint32_t ramin_size; uint32_t ramht_offset; uint32_t ramht_size; @@ -182,9 +211,11 @@ typedef struct drm_nouveau_private { /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */ uint32_t ctx_table_size; - struct mem_block *ctx_table; + nouveau_gpuobj_ref_t *ctx_table; struct nouveau_config config; + + nouveau_gpuobj_t *gpuobj_all; } drm_nouveau_private_t; @@ -205,6 +236,7 @@ extern int nouveau_mem_init_heap(struct mem_block **, extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *, uint64_t size, int align2, DRMFILE); +extern void nouveau_mem_takedown(struct mem_block **heap); extern void nouveau_mem_free_block(struct mem_block *); extern uint64_t nouveau_mem_fb_amount(struct drm_device *dev); extern void nouveau_mem_release(DRMFILE filp, struct mem_block *heap); @@ -236,22 +268,28 @@ extern int nouveau_fifo_owner(drm_device_t *dev, DRMFILE filp, int channel); extern void nouveau_fifo_free(drm_device_t *dev, int channel); /* nouveau_object.c */ -extern int nouveau_object_init_channel(drm_device_t *, int channel, - uint32_t vram_handle, - uint32_t tt_handle); -extern void nouveau_object_takedown_channel(drm_device_t *dev, int channel); -extern void nouveau_object_cleanup(drm_device_t *dev, int channel); -extern int nouveau_ramht_insert(drm_device_t *, int channel, - uint32_t handle, struct nouveau_object *); -extern struct nouveau_object * -nouveau_object_gr_create(drm_device_t *dev, int channel, int class); -extern struct nouveau_object * -nouveau_object_dma_create(drm_device_t *dev, int channel, int class, - uint32_t offset, uint32_t size, - int access, int target); -extern void nouveau_object_free(drm_device_t *dev, struct nouveau_object *obj); -extern int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS); -extern uint32_t nouveau_chip_instance_get(drm_device_t *dev, struct mem_block *mem); +extern void nouveau_gpuobj_takedown(drm_device_t *dev); +extern int nouveau_gpuobj_channel_init(drm_device_t *, int channel, + uint32_t vram_h, uint32_t tt_h); +extern void nouveau_gpuobj_channel_takedown(drm_device_t *, int channel); +extern int nouveau_gpuobj_new(drm_device_t *, int channel, int size, int align, + uint32_t flags, nouveau_gpuobj_t **); +extern int nouveau_gpuobj_del(drm_device_t *, nouveau_gpuobj_t **); +extern int nouveau_gpuobj_ref_add(drm_device_t *, int channel, uint32_t handle, + nouveau_gpuobj_t *, nouveau_gpuobj_ref_t **); +extern int nouveau_gpuobj_ref_del(drm_device_t *, nouveau_gpuobj_ref_t **); +extern int nouveau_gpuobj_new_ref(drm_device_t *, int chan_obj, int chan_ref, + uint32_t handle, int size, int align, + uint32_t flags, nouveau_gpuobj_ref_t **); +extern int nouveau_gpuobj_new_fake(drm_device_t *, uint32_t offset, + uint32_t size, uint32_t flags, + nouveau_gpuobj_t**, nouveau_gpuobj_ref_t**); +extern int nouveau_gpuobj_dma_new(drm_device_t *, int channel, int class, + uint64_t offset, uint64_t size, + int access, int target, nouveau_gpuobj_t **); +extern int nouveau_gpuobj_gr_new(drm_device_t *, int channel, int class, + nouveau_gpuobj_t **); +extern int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS); /* nouveau_irq.c */ extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); @@ -384,8 +422,8 @@ extern long nouveau_compat_ioctl(struct file *filp, unsigned int cmd, #define NV_WI32(o,v) DRM_WRITE32(dev_priv->ramin, (o), (v)) #endif -#define INSTANCE_RD(o,i) NV_RI32((o)->start + ((i)<<2)) -#define INSTANCE_WR(o,i,v) NV_WI32((o)->start + ((i)<<2), (v)) +#define INSTANCE_RD(o,i) NV_RI32((o)->im_pramin->start + ((i)<<2)) +#define INSTANCE_WR(o,i,v) NV_WI32((o)->im_pramin->start + ((i)<<2), (v)) #endif /* __NOUVEAU_DRV_H__ */ diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 81dbfcda..9f916307 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -186,10 +186,12 @@ static int nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; struct nouveau_config *config = &dev_priv->config; struct mem_block *cb; - struct nouveau_object *cb_dma = NULL; int cb_min_size = max(NV03_FIFO_SIZE,PAGE_SIZE); + nouveau_gpuobj_t *pushbuf = NULL; + int ret; /* Defaults for unconfigured values */ if (!config->cmdbuf.location) @@ -206,37 +208,42 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) } if (cb->flags & NOUVEAU_MEM_AGP) { - cb_dma = nouveau_object_dma_create(dev, channel, - NV_CLASS_DMA_IN_MEMORY, - cb->start - dev_priv->agp_phys, - cb->size, - NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP); + ret = nouveau_gpuobj_dma_new + (dev, channel, NV_CLASS_DMA_IN_MEMORY, + cb->start - dev_priv->agp_phys, + cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP, + &pushbuf); } else if (dev_priv->card_type != NV_04) { - cb_dma = nouveau_object_dma_create(dev, channel, - NV_CLASS_DMA_IN_MEMORY, - cb->start - drm_get_resource_start(dev, 1), - cb->size, - NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM); + ret = nouveau_gpuobj_dma_new + (dev, channel, NV_CLASS_DMA_IN_MEMORY, + cb->start - drm_get_resource_start(dev, 1), + cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM, + &pushbuf); } else { /* NV04 cmdbuf hack, from original ddx.. not sure of it's * exact reason for existing :) PCI access to cmdbuf in * VRAM. */ - cb_dma = nouveau_object_dma_create(dev, channel, - NV_CLASS_DMA_IN_MEMORY, - cb->start, cb->size, - NV_DMA_ACCESS_RO, NV_DMA_TARGET_PCI); + ret = nouveau_gpuobj_dma_new + (dev, channel, NV_CLASS_DMA_IN_MEMORY, + cb->start, cb->size, NV_DMA_ACCESS_RO, + NV_DMA_TARGET_PCI, &pushbuf); } - if (!cb_dma) { + if (ret) { nouveau_mem_free(dev, cb); - DRM_ERROR("Failed to alloc DMA object for command buffer\n"); - return DRM_ERR(ENOMEM); + DRM_ERROR("Error creating push buffer ctxdma: %d\n", ret); + return ret; + } + + if ((ret = nouveau_gpuobj_ref_add(dev, channel, 0, pushbuf, + &chan->pushbuf))) { + DRM_ERROR("Error referencing push buffer ctxdma: %d\n", ret); + return ret; } dev_priv->fifos[channel].pushbuf_base = 0; dev_priv->fifos[channel].cmdbuf_mem = cb; - dev_priv->fifos[channel].cmdbuf_obj = cb_dma; return 0; } @@ -266,6 +273,7 @@ int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp, return DRM_ERR(EINVAL); (*chan_ret) = channel; chan = &dev_priv->fifos[channel]; + memset(chan, sizeof(*chan), 0); DRM_INFO("Allocating FIFO number %d\n", channel); @@ -273,18 +281,15 @@ int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp, chan->used = 1; chan->filp = filp; - /* FIFO has no objects yet */ - chan->objs = NULL; - - /* allocate a command buffer, and create a dma object for the gpu */ - ret = nouveau_fifo_cmdbuf_alloc(dev, channel); + /* Setup channel's default objects */ + ret = nouveau_gpuobj_channel_init(dev, channel, vram_handle, tt_handle); if (ret) { nouveau_fifo_free(dev, channel); return ret; } - /* Setup channel's default objects */ - ret = nouveau_object_init_channel(dev, channel, vram_handle, tt_handle); + /* allocate a command buffer, and create a dma object for the gpu */ + ret = nouveau_fifo_cmdbuf_alloc(dev, channel); if (ret) { nouveau_fifo_free(dev, channel); return ret; @@ -395,13 +400,18 @@ void nouveau_fifo_free(drm_device_t* dev, int channel) NV_WRITE(NV03_PFIFO_CACHES, 0x00000001); /* Deallocate command buffer */ - if (chan->cmdbuf_mem) + if (chan->pushbuf) + nouveau_gpuobj_ref_del(dev, &chan->pushbuf); + + if (chan->cmdbuf_mem) { nouveau_mem_free(dev, chan->cmdbuf_mem); + chan->cmdbuf_mem = NULL; + } nouveau_notifier_takedown_channel(dev, channel); /* Destroy objects belonging to the channel */ - nouveau_object_cleanup(dev, channel); + nouveau_gpuobj_channel_takedown(dev, channel); dev_priv->fifo_alloc_count--; } diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index d8ae52b7..49041862 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -189,7 +189,7 @@ void nouveau_mem_release(DRMFILE filp, struct mem_block *heap) /* * Cleanup everything */ -static void nouveau_mem_takedown(struct mem_block **heap) +void nouveau_mem_takedown(struct mem_block **heap) { struct mem_block *p; @@ -554,6 +554,13 @@ int nouveau_instmem_init(struct drm_device *dev) nouveau_instmem_determine_amount(dev); nouveau_instmem_configure_fixed_tables(dev); + if ((ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramht_offset, + dev_priv->ramht_size, + NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_ALLOW_NO_REFS, + &dev_priv->ramht, NULL))) + return ret; + /* Create a heap to manage RAMIN allocations, we don't allocate * the space that was reserved for RAMHT/FC/RO. */ diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index 0cfe733e..4d5e26ab 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -74,10 +74,10 @@ nouveau_notifier_alloc(drm_device_t *dev, int channel, uint32_t handle, { drm_nouveau_private_t *dev_priv = dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - struct nouveau_object *obj; + nouveau_gpuobj_t *nobj = NULL; struct mem_block *mem; uint32_t offset; - int target; + int target, ret; if (!chan->notifier_heap) { DRM_ERROR("Channel %d doesn't have a notifier heap!\n", @@ -105,21 +105,19 @@ nouveau_notifier_alloc(drm_device_t *dev, int channel, uint32_t handle, return DRM_ERR(EINVAL); } - obj = nouveau_object_dma_create(dev, channel, NV_CLASS_DMA_IN_MEMORY, - offset, mem->size, NV_DMA_ACCESS_RW, - target); - if (!obj) { + if ((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, + offset, mem->size, + NV_DMA_ACCESS_RW, target, &nobj))) { nouveau_mem_free_block(mem); - DRM_ERROR("Error creating notifier ctxdma\n"); - return DRM_ERR(ENOMEM); + DRM_ERROR("Error creating notifier ctxdma: %d\n", ret); + return ret; } - obj->handle = handle; - if (nouveau_ramht_insert(dev, channel, handle, obj)) { - nouveau_object_free(dev, obj); + if ((ret = nouveau_gpuobj_ref_add(dev, channel, handle, nobj, NULL))) { + nouveau_gpuobj_del(dev, &nobj); nouveau_mem_free_block(mem); - DRM_ERROR("Error inserting notifier ctxdma into RAMHT\n"); - return DRM_ERR(ENOMEM); + DRM_ERROR("Error referencing notifier ctxdma: %d\n", ret); + return ret; } *b_offset = mem->start; diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index dac08df4..79875ca1 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -35,79 +35,6 @@ #include "nouveau_drv.h" #include "nouveau_drm.h" -/* TODO - * - Check object class, deny unsafe objects (add card-specific versioning?) - * - Get rid of DMA object creation, this should be wrapped by MM routines. - */ - -/* Translate a RAMIN offset into a value the card understands, will be useful - * in the future when we can access more instance ram which isn't mapped into - * the PRAMIN aperture - */ -uint32_t -nouveau_chip_instance_get(drm_device_t *dev, struct mem_block *mem) -{ - uint32_t inst = (uint32_t)mem->start >> 4; - DRM_DEBUG("****** on-chip instance for 0x%016llx = 0x%08x\n", - mem->start, inst); - return inst; -} - -static void -nouveau_object_link(drm_device_t *dev, struct nouveau_object *obj) -{ - drm_nouveau_private_t *dev_priv=dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[obj->channel]; - - if (!chan->objs) { - chan->objs = obj; - return; - } - - obj->prev = NULL; - obj->next = chan->objs; - - chan->objs->prev = obj; - chan->objs = obj; -} - -static void -nouveau_object_unlink(drm_device_t *dev, struct nouveau_object *obj) -{ - drm_nouveau_private_t *dev_priv=dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[obj->channel]; - - if (obj->prev == NULL) { - if (obj->next) - obj->next->prev = NULL; - chan->objs = obj->next; - } else if (obj->next == NULL) { - if (obj->prev) - obj->prev->next = NULL; - } else { - obj->prev->next = obj->next; - obj->next->prev = obj->prev; - } -} - -static struct nouveau_object * -nouveau_object_handle_find(drm_device_t *dev, int channel, uint32_t handle) -{ - drm_nouveau_private_t *dev_priv=dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - struct nouveau_object *obj = chan->objs; - - DRM_DEBUG("Looking for handle 0x%08x\n", handle); - while (obj) { - if (obj->handle == handle) - return obj; - obj = obj->next; - } - - DRM_DEBUG("...couldn't find handle\n"); - return NULL; -} - /* NVidia uses context objects to drive drawing operations. Context objects can be selected into 8 subchannels in the FIFO, @@ -150,146 +77,439 @@ nouveau_ramht_hash_handle(drm_device_t *dev, int channel, uint32_t handle) handle >>= dev_priv->ramht_bits; } hash ^= channel << (dev_priv->ramht_bits - 4); - return hash << 3; + hash <<= 3; + + DRM_DEBUG("ch%d handle=0x%08x hash=0x%08x\n", channel, handle, hash); + return hash; } static int -nouveau_ramht_entry_valid(drm_device_t *dev, uint32_t ramht, uint32_t offset) +nouveau_ramht_entry_valid(drm_device_t *dev, nouveau_gpuobj_t *ramht, + uint32_t offset) { drm_nouveau_private_t *dev_priv=dev->dev_private; - uint32_t ctx = NV_RI32(ramht + offset + 4); + uint32_t ctx = INSTANCE_RD(ramht, (offset + 4)/4); if (dev_priv->card_type < NV_40) return ((ctx & NV_RAMHT_CONTEXT_VALID) != 0); return (ctx != 0); } -int -nouveau_ramht_insert(drm_device_t* dev, int channel, uint32_t handle, - struct nouveau_object *obj) +static int +nouveau_ramht_insert(drm_device_t* dev, nouveau_gpuobj_ref_t *ref) { drm_nouveau_private_t *dev_priv=dev->dev_private; - uint32_t ramht = dev_priv->ramht_offset; + struct nouveau_fifo *chan = &dev_priv->fifos[ref->channel]; + nouveau_gpuobj_t *ramht = chan->ramht ? chan->ramht->gpuobj : NULL; + nouveau_gpuobj_t *gpuobj = ref->gpuobj; uint32_t ctx, co, ho; - uint32_t inst; - inst = nouveau_chip_instance_get(dev, obj->instance); + if (!ramht) { + DRM_ERROR("No hash table!\n"); + return DRM_ERR(EINVAL); + } + if (dev_priv->card_type < NV_40) { - ctx = NV_RAMHT_CONTEXT_VALID | inst | - (channel << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) | - (obj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT); + ctx = NV_RAMHT_CONTEXT_VALID | (ref->instance >> 4) | + (ref->channel << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) | + (gpuobj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT); } else if (dev_priv->card_type < NV_50) { - ctx = inst | - (channel << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) | - (obj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT); + ctx = (ref->instance >> 4) | + (ref->channel << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) | + (gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT); } else { - ctx = inst | - (obj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT); + ctx = (ref->instance >> 4) | + (gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT); } - co = ho = nouveau_ramht_hash_handle(dev, channel, handle); + co = ho = nouveau_ramht_hash_handle(dev, ref->channel, ref->handle); do { if (!nouveau_ramht_entry_valid(dev, ramht, co)) { DRM_DEBUG("insert ch%d 0x%08x: h=0x%08x, c=0x%08x\n", - channel, co, handle, ctx); - NV_WI32(ramht + co + 0, handle); - NV_WI32(ramht + co + 4, ctx); - obj->handle = handle; + ref->channel, co, ref->handle, ctx); + INSTANCE_WR(ramht, (co + 0)/4, ref->handle); + INSTANCE_WR(ramht, (co + 4)/4, ctx); return 0; } DRM_DEBUG("collision ch%d 0x%08x: h=0x%08x\n", - channel, co, NV_RI32(ramht + co)); + ref->channel, co, INSTANCE_RD(ramht, co/4)); co += 8; - if (co == dev_priv->ramht_size) + if (co >= dev_priv->ramht_size) co = 0; } while (co != ho); - DRM_ERROR("RAMHT space exhausted. ch=%d\n", channel); + DRM_ERROR("RAMHT space exhausted. ch=%d\n", ref->channel); return DRM_ERR(ENOMEM); } static void -nouveau_ramht_remove(drm_device_t* dev, struct nouveau_object *obj) +nouveau_ramht_remove(drm_device_t* dev, nouveau_gpuobj_ref_t *ref) { drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t ramht = dev_priv->ramht_offset; + struct nouveau_fifo *chan = &dev_priv->fifos[ref->channel]; + nouveau_gpuobj_t *ramht = chan->ramht ? chan->ramht->gpuobj : NULL; uint32_t co, ho; - co = ho = nouveau_ramht_hash_handle(dev, obj->channel, obj->handle); + if (!ramht) { + DRM_ERROR("No hash table!\n"); + return; + } + + co = ho = nouveau_ramht_hash_handle(dev, ref->channel, ref->handle); do { if (nouveau_ramht_entry_valid(dev, ramht, co) && - (obj->handle == NV_RI32(ramht + co))) { + (ref->handle == INSTANCE_RD(ramht, (co/4)))) { DRM_DEBUG("remove ch%d 0x%08x: h=0x%08x, c=0x%08x\n", - obj->channel, co, obj->handle, - NV_RI32(ramht + co + 4)); - NV_WI32(ramht + co + 0, 0x00000000); - NV_WI32(ramht + co + 4, 0x00000000); - obj->handle = ~0; + ref->channel, co, ref->handle, + INSTANCE_RD(ramht, (co + 4))); + INSTANCE_WR(ramht, (co + 0)/4, 0x00000000); + INSTANCE_WR(ramht, (co + 4)/4, 0x00000000); return; } co += 8; - if (co == dev_priv->ramht_size) + if (co >= dev_priv->ramht_size) co = 0; } while (co != ho); DRM_ERROR("RAMHT entry not found. ch=%d, handle=0x%08x\n", - obj->channel, obj->handle); + ref->channel, ref->handle); } -static struct nouveau_object * -nouveau_object_instance_alloc(drm_device_t* dev, int channel) +int +nouveau_gpuobj_new(drm_device_t *dev, int channel, int size, int align, + uint32_t flags, nouveau_gpuobj_t **gpuobj_ret) { - drm_nouveau_private_t *dev_priv=dev->dev_private; - struct nouveau_object *obj; + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = NULL; + nouveau_gpuobj_t *gpuobj; + struct mem_block *pramin = NULL; + + DRM_DEBUG("ch%d size=%d align=%d flags=0x%08x\n", + channel, size, align, flags); - /* Create object struct */ - obj = drm_calloc(1, sizeof(struct nouveau_object), DRM_MEM_DRIVER); - if (!obj) { - DRM_ERROR("couldn't alloc memory for object\n"); - return NULL; + if (!dev_priv || !gpuobj_ret || *gpuobj_ret != NULL) + return DRM_ERR(EINVAL); + + if (channel >= 0) { + if (channel > nouveau_fifo_number(dev)) + return DRM_ERR(EINVAL); + chan = &dev_priv->fifos[channel]; } - /* Allocate instance memory */ - obj->instance = nouveau_instmem_alloc(dev, - (dev_priv->card_type >= NV_40 ? 32 : 16), 4); - if (!obj->instance) { - DRM_ERROR("couldn't alloc RAMIN for object\n"); - drm_free(obj, sizeof(struct nouveau_object), DRM_MEM_DRIVER); - return NULL; + gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER); + if (!gpuobj) + return DRM_ERR(ENOMEM); + DRM_DEBUG("gpuobj %p\n", gpuobj); + gpuobj->flags = flags; + gpuobj->im_channel = channel; + + /* Choose between global instmem heap, and per-channel private + * instmem heap. On ramin_heap) { + DRM_DEBUG("private heap\n"); + pramin = chan->ramin_heap; + } else + if (dev_priv->card_type < NV_50) { + DRM_DEBUG("global heap fallback\n"); + pramin = dev_priv->ramin_heap; + } + } else { + DRM_DEBUG("global heap\n"); + pramin = dev_priv->ramin_heap; + } + + if (!pramin) { + DRM_ERROR("No PRAMIN heap!\n"); + return DRM_ERR(EINVAL); } - /* Bind object to channel */ - obj->channel = channel; - obj->handle = ~0; - nouveau_object_link(dev, obj); + /* Allocate a chunk of the PRAMIN aperture */ + gpuobj->im_pramin = nouveau_mem_alloc_block(pramin, size, + drm_order(align), + (DRMFILE)-2); + if (!gpuobj->im_pramin) { + nouveau_gpuobj_del(dev, &gpuobj); + return DRM_ERR(ENOMEM); + } + gpuobj->im_pramin->flags = NOUVEAU_MEM_INSTANCE; + + /* On NV50 the PRAMIN aperture is paged. When allocating from the + * global instmem heap, alloc and bind VRAM pages into the PRAMIN + * aperture. + */ + if (!chan && dev_priv->card_type >= NV_50) { + DRM_ERROR("back aperture with vram pages\n"); + nouveau_gpuobj_del(dev, &gpuobj); + return DRM_ERR(EINVAL); + } - return obj; + if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) { + int i; + + for (i = 0; i < gpuobj->im_pramin->size; i += 4) + INSTANCE_WR(gpuobj, i/4, 0); + } + + if (dev_priv->gpuobj_all) { + gpuobj->next = dev_priv->gpuobj_all; + gpuobj->next->prev = gpuobj; + } + dev_priv->gpuobj_all = gpuobj; + + *gpuobj_ret = gpuobj; + return 0; } -static void -nouveau_object_instance_free(drm_device_t *dev, struct nouveau_object *obj) +void nouveau_gpuobj_takedown(drm_device_t *dev) { - drm_nouveau_private_t *dev_priv=dev->dev_private; + drm_nouveau_private_t *dev_priv = dev->dev_private; + nouveau_gpuobj_t *gpuobj = NULL; + + DRM_DEBUG("\n"); + + while ((gpuobj = dev_priv->gpuobj_all)) { + DRM_ERROR("gpuobj %p still exists at takedown, refs=%d\n", + gpuobj, gpuobj->refcount); + gpuobj->refcount = 0; + nouveau_gpuobj_del(dev, &gpuobj); + } +} + +int nouveau_gpuobj_del(drm_device_t *dev, nouveau_gpuobj_t **pgpuobj) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + nouveau_gpuobj_t *gpuobj; + + DRM_DEBUG("gpuobj %p\n", pgpuobj ? *pgpuobj : NULL); + + if (!dev_priv || !pgpuobj || !(*pgpuobj)) + return DRM_ERR(EINVAL); + gpuobj = *pgpuobj; + + if (gpuobj->refcount != 0) { + DRM_ERROR("gpuobj refcount is %d\n", gpuobj->refcount); + return DRM_ERR(EINVAL); + } + + if (gpuobj->im_pramin) { + if (gpuobj->flags & NVOBJ_FLAG_FAKE) + drm_free(gpuobj->im_pramin, sizeof(*gpuobj->im_pramin), + DRM_MEM_DRIVER); + else + nouveau_mem_free_block(gpuobj->im_pramin); + } + + if (gpuobj->im_backing) + nouveau_mem_free(dev, gpuobj->im_backing); + + if (gpuobj->next) + gpuobj->next->prev = gpuobj->prev; + if (gpuobj->prev) + gpuobj->prev->next = gpuobj->next; + else + dev_priv->gpuobj_all = gpuobj->next; + + *pgpuobj = NULL; + drm_free(gpuobj, sizeof(*gpuobj), DRM_MEM_DRIVER); + return 0; +} + +static int +nouveau_gpuobj_instance_get(drm_device_t *dev, int channel, + nouveau_gpuobj_t *gpuobj, uint32_t *inst) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + nouveau_gpuobj_t *cpramin; + + if ((channel > 0) && gpuobj->im_channel != channel) { + DRM_ERROR("Channel mismatch: obj %d, ref %d\n", + gpuobj->im_channel, channel); + return DRM_ERR(EINVAL); + } + + /* card_type < NV_50) { + *inst = gpuobj->im_pramin->start; + return 0; + } + + /* NV50 channel-local instance */ + if (channel > 0) { + cpramin = dev_priv->fifos[channel].ramin->gpuobj; + *inst = gpuobj->im_pramin->start - cpramin->im_pramin->start; + return 0; + } + + /* NV50 global (VRAM) instance */ + if (gpuobj->im_channel < 0) { + /* ...from global heap */ + if (!gpuobj->im_backing) { + DRM_ERROR("AII, no VRAM backing gpuobj\n"); + return DRM_ERR(EINVAL); + } + *inst = gpuobj->im_backing->start - dev_priv->fb_phys; + return 0; + } else { + /* ...from local heap */ + cpramin = dev_priv->fifos[gpuobj->im_channel].ramin->gpuobj; + *inst = (cpramin->im_backing->start - dev_priv->fb_phys) + + (gpuobj->im_pramin->start - cpramin->im_pramin->start); + return 0; + } + + return DRM_ERR(EINVAL); +} + +int +nouveau_gpuobj_ref_add(drm_device_t *dev, int channel, uint32_t handle, + nouveau_gpuobj_t *gpuobj, nouveau_gpuobj_ref_t **ref_ret) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = NULL; + nouveau_gpuobj_ref_t *ref; + uint32_t instance; + int ret; + + DRM_DEBUG("ch%d h=0x%08x gpuobj=%p\n", channel, handle, gpuobj); + + if (!dev_priv || !gpuobj || (ref_ret && *ref_ret != NULL)) + return DRM_ERR(EINVAL); + + if (channel >= 0) { + if (channel > nouveau_fifo_number(dev)) + return DRM_ERR(EINVAL); + chan = &dev_priv->fifos[channel]; + } else + if (!ref_ret) + return DRM_ERR(EINVAL); + + ret = nouveau_gpuobj_instance_get(dev, channel, gpuobj, &instance); + if (ret) + return ret; + + ref = drm_calloc(1, sizeof(*ref), DRM_MEM_DRIVER); + if (!ref) + return DRM_ERR(ENOMEM); + ref->gpuobj = gpuobj; + ref->channel = channel; + ref->instance = instance; + + if (!ref_ret) { + ref->handle = handle; + + ret = nouveau_ramht_insert(dev, ref); + if (ret) { + drm_free(ref, sizeof(*ref), DRM_MEM_DRIVER); + return ret; + } + + ref->next = chan->ramht_refs; + chan->ramht_refs = ref; + } else { + ref->handle = ~0; + *ref_ret = ref; + } + + ref->gpuobj->refcount++; + return 0; +} + +int nouveau_gpuobj_ref_del(drm_device_t *dev, nouveau_gpuobj_ref_t **pref) +{ + nouveau_gpuobj_ref_t *ref; + + DRM_DEBUG("ref %p\n", pref ? *pref : NULL); + + if (!dev || !pref || *pref == NULL) + return DRM_ERR(EINVAL); + ref = *pref; + + if (ref->handle != ~0) + nouveau_ramht_remove(dev, ref); + + if (ref->gpuobj) { + ref->gpuobj->refcount--; + + if (ref->gpuobj->refcount == 0) { + if (!(ref->gpuobj->flags & NVOBJ_FLAG_ALLOW_NO_REFS)) + nouveau_gpuobj_del(dev, &ref->gpuobj); + } + } + + *pref = NULL; + drm_free(ref, sizeof(ref), DRM_MEM_DRIVER); + return 0; +} + +int +nouveau_gpuobj_new_ref(drm_device_t *dev, int oc, int rc, uint32_t handle, + int size, int align, uint32_t flags, + nouveau_gpuobj_ref_t **ref) +{ + nouveau_gpuobj_t *gpuobj = NULL; + int ret; + + if ((ret = nouveau_gpuobj_new(dev, oc, size, align, flags, &gpuobj))) + return ret; + + if ((ret = nouveau_gpuobj_ref_add(dev, rc, handle, gpuobj, ref))) { + nouveau_gpuobj_del(dev, &gpuobj); + return ret; + } + + return 0; +} + +int +nouveau_gpuobj_new_fake(drm_device_t *dev, uint32_t offset, uint32_t size, + uint32_t flags, nouveau_gpuobj_t **pgpuobj, + nouveau_gpuobj_ref_t **pref) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + nouveau_gpuobj_t *gpuobj = NULL; int i; - /* Unbind object from channel */ - nouveau_object_unlink(dev, obj); + DRM_DEBUG("offset=0x%08x size=0x%08x flags=0x%08x\n", + offset, size, flags); + + gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER); + if (!gpuobj) + return DRM_ERR(ENOMEM); + DRM_DEBUG("gpuobj %p\n", gpuobj); + gpuobj->im_channel = -1; + gpuobj->flags = flags | NVOBJ_FLAG_FAKE; + + gpuobj->im_pramin = drm_calloc(1, sizeof(struct mem_block), + DRM_MEM_DRIVER); + if (!gpuobj->im_pramin) { + nouveau_gpuobj_del(dev, &gpuobj); + return DRM_ERR(ENOMEM); + } + gpuobj->im_pramin->start = offset; + gpuobj->im_pramin->size = size; + + if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) { + for (i = 0; i < gpuobj->im_pramin->size; i += 4) + INSTANCE_WR(gpuobj, i/4, 0); + } - /* Clean RAMIN entry */ - DRM_DEBUG("Instance entry for 0x%08x" - "(engine %d, class 0x%x) before destroy:\n", - obj->handle, obj->engine, obj->class); - for (i=0; i<(obj->instance->size/4); i++) { - DRM_DEBUG(" +0x%02x: 0x%08x\n", (i*4), - INSTANCE_RD(obj->instance, i)); - INSTANCE_WR(obj->instance, i, 0x00000000); + if (pref) { + if ((i = nouveau_gpuobj_ref_add(dev, -1, 0, gpuobj, pref))) { + nouveau_gpuobj_del(dev, &gpuobj); + return i; + } } - /* Free RAMIN */ - nouveau_instmem_free(dev, obj->instance); + if (pgpuobj) + *pgpuobj = gpuobj; + return 0; } /* @@ -317,64 +537,70 @@ nouveau_object_instance_free(drm_device_t *dev, struct nouveau_object *obj) to it that can be used to set up context objects. */ -struct nouveau_object * -nouveau_object_dma_create(drm_device_t* dev, int channel, int class, - uint32_t offset, uint32_t size, - int access, int target) +static int +nouveau_gpuobj_class_instmem_size(drm_device_t *dev, int class) { - drm_nouveau_private_t *dev_priv=dev->dev_private; - struct nouveau_object *obj; - uint32_t frame, adjust; - uint32_t pte_flags = 0; - - DRM_DEBUG("offset:0x%08x, size:0x%08x, target:%d, access:%d\n", - offset, size, target, access); + drm_nouveau_private_t *dev_priv = dev->dev_private; - switch (target) { - case NV_DMA_TARGET_AGP: - offset += dev_priv->agp_phys; - break; - default: - break; - } + /*XXX: dodgy hack for now */ + if (dev_priv->card_type >= NV_50) + return 24; + if (dev_priv->card_type >= NV_40) + return 32; + return 16; +} - switch (access) { - case NV_DMA_ACCESS_RO: - break; - case NV_DMA_ACCESS_WO: - case NV_DMA_ACCESS_RW: - pte_flags |= (1 << 1); - break; - default: - DRM_ERROR("invalid access mode=%d\n", access); - return NULL; - } +int +nouveau_gpuobj_dma_new(drm_device_t *dev, int channel, int class, + uint64_t offset, uint64_t size, int access, int target, + nouveau_gpuobj_t **gpuobj) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + int ret; - frame = offset & ~0x00000FFF; - adjust = offset & 0x00000FFF; + DRM_DEBUG("ch%d class=0x%04x offset=0x%llx size=0x%llx\n", + channel, class, offset, size); + DRM_DEBUG("access=%d target=%d\n", access, target); - obj = nouveau_object_instance_alloc(dev, channel); - if (!obj) { - DRM_ERROR("couldn't allocate DMA object\n"); - return obj; + ret = nouveau_gpuobj_new(dev, channel, + nouveau_gpuobj_class_instmem_size(dev, class), + 16, + NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, + gpuobj); + if (ret) { + DRM_ERROR("Error creating gpuobj: %d\n", ret); + return ret; } - obj->engine = 0; - obj->class = class; - - INSTANCE_WR(obj->instance, 0, ((1<<12) | (1<<13) | - (adjust << 20) | - (access << 14) | - (target << 16) | - class)); - INSTANCE_WR(obj->instance, 1, size-1); - INSTANCE_WR(obj->instance, 2, frame | pte_flags); - INSTANCE_WR(obj->instance, 3, frame | pte_flags); + if (dev_priv->card_type < NV_50) { + uint32_t frame, adjust, pte_flags = 0; + + if (target == NV_DMA_TARGET_AGP) + offset += dev_priv->agp_phys; + if (access != NV_DMA_ACCESS_RO) + pte_flags |= (1<<1); + frame = offset & ~0x00000fff; + adjust = offset & 0x00000fff; + + INSTANCE_WR(*gpuobj, 0, ((1<<12) | (1<<13) | + (adjust << 20) | + (access << 14) | + (target << 16) | + class)); + INSTANCE_WR(*gpuobj, 1, size - 1); + INSTANCE_WR(*gpuobj, 2, frame | pte_flags); + INSTANCE_WR(*gpuobj, 3, frame | pte_flags); + } else { + nouveau_gpuobj_del(dev, gpuobj); + DRM_ERROR("stub\n"); + return DRM_ERR(EINVAL); + } - return obj; + (*gpuobj)->engine = NVOBJ_ENGINE_SW; + (*gpuobj)->class = class; + return 0; } - /* Context objects in the instance RAM have the following structure. * On NV40 they are 32 byte long, on NV30 and smaller 16 bytes. @@ -426,89 +652,142 @@ nouveau_object_dma_create(drm_device_t* dev, int channel, int class, entry[5]: set to 0? */ -struct nouveau_object * -nouveau_object_gr_create(drm_device_t* dev, int channel, int class) +int +nouveau_gpuobj_gr_new(drm_device_t *dev, int channel, int class, + nouveau_gpuobj_t **gpuobj) { - drm_nouveau_private_t *dev_priv=dev->dev_private; - struct nouveau_object *obj; + drm_nouveau_private_t *dev_priv = dev->dev_private; + int ret; - DRM_DEBUG("class=%x\n", class); + DRM_DEBUG("ch%d class=0x%04x\n", channel, class); - obj = nouveau_object_instance_alloc(dev, channel); - if (!obj) { - DRM_ERROR("couldn't allocate context object\n"); - return obj; + ret = nouveau_gpuobj_new(dev, channel, + nouveau_gpuobj_class_instmem_size(dev, class), + 16, + NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, + gpuobj); + if (ret) { + DRM_ERROR("Error creating gpuobj: %d\n", ret); + return ret; } - obj->engine = 1; - obj->class = class; + if (dev_priv->card_type >= NV_50) { + nouveau_gpuobj_del(dev, gpuobj); + DRM_ERROR("stub!\n"); + return DRM_ERR(EINVAL); + } switch (class) { case NV_CLASS_NULL: - INSTANCE_WR(obj->instance, 0, 0x00001030); - INSTANCE_WR(obj->instance, 1, 0xFFFFFFFF); - INSTANCE_WR(obj->instance, 2, 0x00000000); - INSTANCE_WR(obj->instance, 2, 0x00000000); + INSTANCE_WR(*gpuobj, 0, 0x00001030); + INSTANCE_WR(*gpuobj, 1, 0xFFFFFFFF); break; default: if (dev_priv->card_type >= NV_40) { - INSTANCE_WR(obj->instance, 0, obj->class); - INSTANCE_WR(obj->instance, 1, 0x00000000); + INSTANCE_WR(*gpuobj, 0, class); #ifdef __BIG_ENDIAN - INSTANCE_WR(obj->instance, 2, 0x01000000); -#else - INSTANCE_WR(obj->instance, 2, 0x00000000); + INSTANCE_WR(*gpuobj, 2, 0x01000000); #endif - INSTANCE_WR(obj->instance, 3, 0x00000000); - INSTANCE_WR(obj->instance, 4, 0x00000000); - INSTANCE_WR(obj->instance, 5, 0x00000000); - INSTANCE_WR(obj->instance, 6, 0x00000000); - INSTANCE_WR(obj->instance, 7, 0x00000000); } else { #ifdef __BIG_ENDIAN - INSTANCE_WR(obj->instance, 0, obj->class | 0x00080000); + INSTANCE_WR(*gpuobj, 0, class | 0x00080000); #else - INSTANCE_WR(obj->instance, 0, obj->class); + INSTANCE_WR(*gpuobj, 0, class); #endif - INSTANCE_WR(obj->instance, 1, 0x00000000); - INSTANCE_WR(obj->instance, 2, 0x00000000); - INSTANCE_WR(obj->instance, 3, 0x00000000); } } - return obj; + (*gpuobj)->engine = NVOBJ_ENGINE_GR; + (*gpuobj)->class = class; + return 0; } -void -nouveau_object_free(drm_device_t *dev, struct nouveau_object *obj) +static int +nouveau_gpuobj_channel_init_pramin(drm_device_t *dev, int channel) { - nouveau_object_instance_free(dev, obj); - if (obj->handle != ~0) - nouveau_ramht_remove(dev, obj); - drm_free(obj, sizeof(struct nouveau_object), DRM_MEM_DRIVER); + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + nouveau_gpuobj_t *pramin = NULL; + int size, base, ret; + + DRM_DEBUG("ch%d\n", channel); + + /* Base amount for object storage (4KiB enough?) */ + size = 0x1000; + base = 0; + + /* PGRAPH context */ + + if (dev_priv->card_type == NV_50) { + /* RAMHT, RAMFC, PD, funny header thingo */ + } + + DRM_DEBUG("ch%d PRAMIN size: 0x%08x bytes, base alloc=0x%08x\n", + channel, size, base); + ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, size, 0x1000, 0, + &chan->ramin); + if (ret) { + DRM_ERROR("Error allocating channel PRAMIN: %d\n", ret); + return ret; + } + pramin = chan->ramin->gpuobj; + + ret = nouveau_mem_init_heap(&chan->ramin_heap, + pramin->im_pramin->start + base, size); + if (ret) { + DRM_ERROR("Error creating PRAMIN heap: %d\n", ret); + nouveau_gpuobj_ref_del(dev, &chan->ramin); + return ret; + } + + return 0; } int -nouveau_object_init_channel(drm_device_t *dev, int channel, - uint32_t vram_handle, - uint32_t tt_handle) +nouveau_gpuobj_channel_init(drm_device_t *dev, int channel, + uint32_t vram_h, uint32_t tt_h) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_object *gpuobj; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + nouveau_gpuobj_t *vram = NULL, *tt = NULL; int ret; + DRM_DEBUG("ch%d vram=0x%08x tt=0x%08x\n", channel, vram_h, tt_h); + + /* Reserve a block of PRAMIN for the channel + *XXX: maybe on card_type == NV_50) { + ret = nouveau_gpuobj_channel_init_pramin(dev, channel); + if (ret) + return ret; + } + + /* RAMHT */ + if (dev_priv->card_type < NV_50) { + ret = nouveau_gpuobj_ref_add(dev, -1, 0, dev_priv->ramht, + &chan->ramht); + if (ret) + return ret; + } else { + ret = nouveau_gpuobj_new_ref(dev, channel, channel, 0, + 0x8000, 16, + NVOBJ_FLAG_ZERO_ALLOC, + &chan->ramht); + if (ret) + return ret; + } + /* VRAM ctxdma */ - gpuobj = nouveau_object_dma_create(dev, channel, NV_CLASS_DMA_IN_MEMORY, - 0, dev_priv->fb_available_size, - NV_DMA_ACCESS_RW, - NV_DMA_TARGET_VIDMEM); - if (!gpuobj) { - DRM_ERROR("Error creating VRAM ctxdma: %d\n", DRM_ERR(ENOMEM)); - return DRM_ERR(ENOMEM); + if ((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, + 0, dev_priv->fb_available_size, + NV_DMA_ACCESS_RW, + NV_DMA_TARGET_VIDMEM, &vram))) { + DRM_ERROR("Error creating VRAM ctxdma: %d\n", ret); + return ret; } - ret = nouveau_ramht_insert(dev, channel, vram_handle, gpuobj); - if (ret) { + if ((ret = nouveau_gpuobj_ref_add(dev, channel, vram_h, vram, NULL))) { DRM_ERROR("Error referencing VRAM ctxdma: %d\n", ret); return ret; } @@ -518,17 +797,15 @@ nouveau_object_init_channel(drm_device_t *dev, int channel, return 0; /* GART ctxdma */ - gpuobj = nouveau_object_dma_create(dev, channel, NV_CLASS_DMA_IN_MEMORY, - 0, dev_priv->agp_available_size, - NV_DMA_ACCESS_RW, - NV_DMA_TARGET_AGP); - if (!gpuobj) { - DRM_ERROR("Error creating TT ctxdma: %d\n", DRM_ERR(ENOMEM)); - return DRM_ERR(ENOMEM); + if ((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, + 0, dev_priv->agp_available_size, + NV_DMA_ACCESS_RW, NV_DMA_TARGET_AGP, + &tt))) { + DRM_ERROR("Error creating TT ctxdma: %d\n", ret); + return ret; } - ret = nouveau_ramht_insert(dev, channel, tt_handle, gpuobj); - if (ret) { + if ((ret = nouveau_gpuobj_ref_add(dev, channel, tt_h, tt, NULL))) { DRM_ERROR("Error referencing TT ctxdma: %d\n", ret); return ret; } @@ -536,20 +813,34 @@ nouveau_object_init_channel(drm_device_t *dev, int channel, return 0; } -void nouveau_object_cleanup(drm_device_t *dev, int channel) +void +nouveau_gpuobj_channel_takedown(drm_device_t *dev, int channel) { - drm_nouveau_private_t *dev_priv=dev->dev_private; + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + nouveau_gpuobj_ref_t *ref; + + DRM_DEBUG("ch%d\n", channel); - while (dev_priv->fifos[channel].objs) { - nouveau_object_free(dev, dev_priv->fifos[channel].objs); + while ((ref = chan->ramht_refs)) { + chan->ramht_refs = ref->next; + nouveau_gpuobj_ref_del(dev, &ref); } + nouveau_gpuobj_ref_del(dev, &chan->ramht); + + if (chan->ramin_heap) + nouveau_mem_takedown(&chan->ramin_heap); + if (chan->ramin) + nouveau_gpuobj_ref_del(dev, &chan->ramin); + } int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_nouveau_grobj_alloc_t init; - struct nouveau_object *obj; + nouveau_gpuobj_t *gr = NULL; + int ret; DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_grobj_alloc_t __user *) data, sizeof(init)); @@ -561,20 +852,20 @@ int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS) } //FIXME: check args, only allow trusted objects to be created + //FIXME: check for pre-existing handle - if (nouveau_object_handle_find(dev, init.channel, init.handle)) { - DRM_ERROR("Channel %d: handle 0x%08x already exists\n", - init.channel, init.handle); - return DRM_ERR(EINVAL); + if ((ret = nouveau_gpuobj_gr_new(dev, init.channel, init.class, &gr))) { + DRM_ERROR("Error creating gr object: %d (%d/0x%08x)\n", + ret, init.channel, init.handle); + return ret; } - obj = nouveau_object_gr_create(dev, init.channel, init.class); - if (!obj) - return DRM_ERR(ENOMEM); - - if (nouveau_ramht_insert(dev, init.channel, init.handle, obj)) { - nouveau_object_free(dev, obj); - return DRM_ERR(ENOMEM); + if ((ret = nouveau_gpuobj_ref_add(dev, init.channel, init.handle, + gr, NULL))) { + DRM_ERROR("Error referencing gr object: %d (%d/0x%08x\n)", + ret, init.channel, init.handle); + nouveau_gpuobj_del(dev, &gr); + return ret; } return 0; diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index fa773d28..13bc930a 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -283,6 +283,20 @@ static int nouveau_card_init(drm_device_t *dev) return 0; } +static void nouveau_card_takedown(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + nouveau_engine_func_t *engine = &dev_priv->Engine; + + engine->fifo.takedown(dev); + engine->graph.takedown(dev); + engine->fb.takedown(dev); + engine->timer.takedown(dev); + engine->mc.takedown(dev); + nouveau_gpuobj_takedown(dev); + nouveau_mem_close(dev); +} + /* here a client dies, release the stuff that was allocated for its filp */ void nouveau_preclose(drm_device_t * dev, DRMFILE filp) { @@ -314,11 +328,10 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) if (flags==NV_UNKNOWN) return DRM_ERR(EINVAL); - dev_priv = drm_alloc(sizeof(drm_nouveau_private_t), DRM_MEM_DRIVER); + dev_priv = drm_calloc(1, sizeof(*dev_priv), DRM_MEM_DRIVER); if (!dev_priv) return DRM_ERR(ENOMEM); - memset(dev_priv, 0, sizeof(drm_nouveau_private_t)); dev_priv->card_type=flags&NOUVEAU_FAMILY; dev_priv->flags=flags&NOUVEAU_FLAGS; @@ -338,6 +351,9 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) void nouveau_lastclose(struct drm_device *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; + + nouveau_card_takedown(dev); + if(dev_priv->fb_mtrr>0) { drm_mtrr_del(dev_priv->fb_mtrr, drm_get_resource_start(dev, 1),nouveau_mem_fb_amount(dev), DRM_MTRR_WC); diff --git a/shared-core/nv04_fifo.c b/shared-core/nv04_fifo.c index bfae432e..b84f74c1 100644 --- a/shared-core/nv04_fifo.c +++ b/shared-core/nv04_fifo.c @@ -28,8 +28,10 @@ #include "drm.h" #include "nouveau_drv.h" -#define RAMFC_WR(offset, val) NV_WI32(fifoctx + NV04_RAMFC_##offset, (val)) -#define RAMFC_RD(offset) NV_RI32(fifoctx + NV04_RAMFC_##offset) +#define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \ + NV04_RAMFC_##offset/4, (val)) +#define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \ + NV04_RAMFC_##offset/4) #define NV04_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV04_RAMFC__SIZE)) #define NV04_RAMFC__SIZE 32 @@ -38,21 +40,19 @@ nv04_fifo_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - struct nouveau_object *pb = chan->cmdbuf_obj; - uint32_t fifoctx = NV04_RAMFC(channel); - int i; + int ret; - if (!pb || !pb->instance) - return DRM_ERR(EINVAL); + if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(channel), + NV04_RAMFC__SIZE, + NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_ZERO_FREE, + NULL, &chan->ramfc))) + return ret; - /* Clear RAMFC */ - for (i=0; ipushbuf_base); RAMFC_WR(DMA_GET, chan->pushbuf_base); - RAMFC_WR(DMA_INSTANCE, nouveau_chip_instance_get(dev, pb->instance)); + RAMFC_WR(DMA_INSTANCE, chan->pushbuf->instance >> 4); RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | @@ -67,18 +67,17 @@ void nv04_fifo_destroy_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx = NV04_RAMFC(channel); - int i; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - for (i=0; iramfc) + nouveau_gpuobj_ref_del(dev, &chan->ramfc); } int nv04_fifo_load_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx = NV04_RAMFC(channel); + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; uint32_t tmp; NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, (1<<8) | channel); @@ -106,7 +105,7 @@ int nv04_fifo_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx = NV04_RAMFC(channel); + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; uint32_t tmp; RAMFC_WR(DMA_PUT, NV04_PFIFO_CACHE1_DMA_PUT); diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c index b84971de..07ec4635 100644 --- a/shared-core/nv10_fifo.c +++ b/shared-core/nv10_fifo.c @@ -28,8 +28,11 @@ #include "drm.h" #include "nouveau_drv.h" -#define RAMFC_WR(offset, val) NV_WI32(fifoctx + NV10_RAMFC_##offset, (val)) -#define RAMFC_RD(offset) NV_RI32(fifoctx + NV10_RAMFC_##offset) + +#define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \ + NV10_RAMFC_##offset/4, (val)) +#define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \ + NV10_RAMFC_##offset/4) #define NV10_RAMFC(c) (dev_priv->ramfc_offset + NV10_RAMFC__SIZE) #define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32) @@ -38,20 +41,21 @@ nv10_fifo_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - uint32_t fifoctx = NV10_RAMFC(channel), pushbuf; - int i; - - pushbuf = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance); + int ret; - for (i=0; iramfc))) + return ret; /* Fill entries that are seen filled in dumps of nvidia driver just * after channel's is put into DMA mode */ RAMFC_WR(DMA_PUT , chan->pushbuf_base); RAMFC_WR(DMA_GET , chan->pushbuf_base); - RAMFC_WR(DMA_INSTANCE , pushbuf); + RAMFC_WR(DMA_INSTANCE , chan->pushbuf->instance >> 4); RAMFC_WR(DMA_FETCH , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | @@ -67,18 +71,17 @@ void nv10_fifo_destroy_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx = NV10_RAMFC(channel); - int i; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - for (i=0; iramfc) + nouveau_gpuobj_ref_del(dev, &chan->ramfc); } int nv10_fifo_load_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx = NV10_RAMFC(channel); + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; uint32_t tmp; NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00000100 | channel); @@ -120,7 +123,7 @@ int nv10_fifo_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx = NV10_RAMFC(channel); + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; uint32_t tmp; RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 1b8a6727..13271051 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -34,19 +34,18 @@ int nv20_graph_create_context(drm_device_t *dev, int channel) { (drm_nouveau_private_t *)dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; unsigned int ctx_size = NV20_GRCTX_SIZE; - int i; + int ret; - /* Alloc and clear RAMIN to store the context */ - chan->ramin_grctx = nouveau_instmem_alloc(dev, ctx_size, 4); - if (!chan->ramin_grctx) - return DRM_ERR(ENOMEM); - for (i=0; iramin_grctx, i/4, 0x00000000); + if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, ctx_size, 16, + NVOBJ_FLAG_ZERO_ALLOC, + &chan->ramin_grctx))) + return ret; /* Initialise default context values */ - INSTANCE_WR(chan->ramin_grctx, 10, channel << 24); /* CTX_USER */ + INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, channel<<24); /* CTX_USER */ - INSTANCE_WR(dev_priv->ctx_table, channel, nouveau_chip_instance_get(dev, chan->ramin_grctx)); + INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, + chan->ramin_grctx->instance >> 4); return 0; } @@ -54,12 +53,10 @@ void nv20_graph_destroy_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - if (chan->ramin_grctx) { - nouveau_instmem_free(dev, chan->ramin_grctx); - chan->ramin_grctx = NULL; - } + if (chan->ramin_grctx) + nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); - INSTANCE_WR(dev_priv->ctx_table, channel, 0); + INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, 0); } static void nv20_graph_rdi(drm_device_t *dev) { @@ -79,13 +76,14 @@ static void nv20_graph_rdi(drm_device_t *dev) { int nv20_graph_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; uint32_t instance; - instance = INSTANCE_RD(dev_priv->ctx_table, channel); + instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel); if (!instance) { return DRM_ERR(EINVAL); } - if (instance != nouveau_chip_instance_get(dev, dev_priv->fifos[channel].ramin_grctx)) + if (instance != (chan->ramin_grctx->instance >> 4)) DRM_ERROR("nv20_graph_save_context : bad instance\n"); NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance); @@ -99,13 +97,14 @@ int nv20_graph_save_context(drm_device_t *dev, int channel) { int nv20_graph_load_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; uint32_t instance; - instance = INSTANCE_RD(dev_priv->ctx_table, channel); + instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel); if (!instance) { return DRM_ERR(EINVAL); } - if (instance != nouveau_chip_instance_get(dev, dev_priv->fifos[channel].ramin_grctx)) + if (instance != (chan->ramin_grctx->instance >> 4)) DRM_ERROR("nv20_graph_load_context_current : bad instance\n"); NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24); @@ -148,8 +147,8 @@ void nouveau_nv20_context_switch(drm_device_t *dev) int nv20_graph_init(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; - int i; uint32_t tmp, vramsz; + int ret, i; NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH); @@ -158,14 +157,14 @@ int nv20_graph_init(drm_device_t *dev) { /* Create Context Pointer Table */ dev_priv->ctx_table_size = 32 * 4; - dev_priv->ctx_table = nouveau_instmem_alloc(dev, dev_priv->ctx_table_size, 4); - if (!dev_priv->ctx_table) - return DRM_ERR(ENOMEM); - - for (i=0; i< dev_priv->ctx_table_size; i+=4) - INSTANCE_WR(dev_priv->ctx_table, i/4, 0x00000000); - - NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table)); + if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, + dev_priv->ctx_table_size, 16, + NVOBJ_FLAG_ZERO_ALLOC, + &dev_priv->ctx_table))) + return ret; + + NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, + dev_priv->ctx_table->instance >> 4); //XXX need to be done and save/restore for each fifo ??? nv20_graph_rdi(dev); diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index 7a87990a..65f4f868 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -16,7 +16,7 @@ * contexts are taken from dumps just after the 3D object is * created. */ -static void nv30_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +static void nv30_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) { drm_nouveau_private_t *dev_priv = dev->dev_private; int i; @@ -105,9 +105,9 @@ int nv30_graph_create_context(drm_device_t *dev, int channel) drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - void (*ctx_init)(drm_device_t *, struct mem_block *); + void (*ctx_init)(drm_device_t *, nouveau_gpuobj_t *); unsigned int ctx_size; - int i; + int ret; switch (dev_priv->chipset) { default: @@ -116,18 +116,17 @@ int nv30_graph_create_context(drm_device_t *dev, int channel) break; } - /* Alloc and clear RAMIN to store the context */ - chan->ramin_grctx = nouveau_instmem_alloc(dev, ctx_size, 4); - if (!chan->ramin_grctx) - return DRM_ERR(ENOMEM); - for (i=0; iramin_grctx, i/4, 0x00000000); + if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, ctx_size, 16, + NVOBJ_FLAG_ZERO_ALLOC, + &chan->ramin_grctx))) + return ret; /* Initialise default context values */ - ctx_init(dev, chan->ramin_grctx); + ctx_init(dev, chan->ramin_grctx->gpuobj); - INSTANCE_WR(chan->ramin_grctx, 10, channel << 24); /* CTX_USER */ - INSTANCE_WR(dev_priv->ctx_table, channel, nouveau_chip_instance_get(dev, chan->ramin_grctx)); + INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, channel<<24); /* CTX_USER */ + INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, + chan->ramin_grctx->instance >> 4); return 0; } @@ -138,12 +137,10 @@ void nv30_graph_destroy_context(drm_device_t *dev, int channel) (drm_nouveau_private_t *)dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - if (chan->ramin_grctx) { - nouveau_instmem_free(dev, chan->ramin_grctx); - chan->ramin_grctx = NULL; - } + if (chan->ramin_grctx) + nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); - INSTANCE_WR(dev_priv->ctx_table, channel, 0); + INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, 0); } static int @@ -172,7 +169,7 @@ int nv30_graph_load_context(drm_device_t *dev, int channel) if (!chan->ramin_grctx) return DRM_ERR(EINVAL); - inst = nouveau_chip_instance_get(dev, chan->ramin_grctx); + inst = chan->ramin_grctx->instance >> 4; NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER, @@ -189,7 +186,7 @@ int nv30_graph_save_context(drm_device_t *dev, int channel) if (!chan->ramin_grctx) return DRM_ERR(EINVAL); - inst = nouveau_chip_instance_get(dev, chan->ramin_grctx); + inst = chan->ramin_grctx->instance >> 4; NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER, @@ -203,7 +200,7 @@ int nv30_graph_init(drm_device_t *dev) drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; uint32_t vramsz, tmp; - int i; + int ret, i; NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH); @@ -212,14 +209,14 @@ int nv30_graph_init(drm_device_t *dev) /* Create Context Pointer Table */ dev_priv->ctx_table_size = 32 * 4; - dev_priv->ctx_table = nouveau_instmem_alloc(dev, dev_priv->ctx_table_size, 4); - if (!dev_priv->ctx_table) - return DRM_ERR(ENOMEM); - - for (i=0; i< dev_priv->ctx_table_size; i+=4) - INSTANCE_WR(dev_priv->ctx_table, i/4, 0x00000000); - - NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table)); + if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, + dev_priv->ctx_table_size, 16, + NVOBJ_FLAG_ZERO_ALLOC, + &dev_priv->ctx_table))) + return ret; + + NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, + dev_priv->ctx_table->instance >> 4); NV_WRITE(NV03_PGRAPH_INTR_EN, 0x00000000); NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c index 6f25349c..eed3e45b 100644 --- a/shared-core/nv40_fifo.c +++ b/shared-core/nv40_fifo.c @@ -28,8 +28,11 @@ #include "nouveau_drv.h" #include "nouveau_drm.h" -#define RAMFC_WR(offset, val) NV_WI32(fifoctx + NV40_RAMFC_##offset, (val)) -#define RAMFC_RD(offset) NV_RI32(fifoctx + NV40_RAMFC_##offset) + +#define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \ + NV40_RAMFC_##offset/4, (val)) +#define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \ + NV40_RAMFC_##offset/4) #define NV40_RAMFC(c) (dev_priv->ramfc_offset + ((c)*NV40_RAMFC__SIZE)) #define NV40_RAMFC__SIZE 128 @@ -38,21 +41,21 @@ nv40_fifo_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - uint32_t fifoctx = NV40_RAMFC(channel), grctx, pushbuf; - int i; - - for (i = 0; i < NV40_RAMFC__SIZE; i+=4) - NV_WI32(fifoctx + i, 0); + int ret; - grctx = nouveau_chip_instance_get(dev, chan->ramin_grctx); - pushbuf = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance); + if ((ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(channel), + NV40_RAMFC__SIZE, + NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_ZERO_FREE, + NULL, &chan->ramfc))) + return ret; /* Fill entries that are seen filled in dumps of nvidia driver just * after channel's is put into DMA mode */ RAMFC_WR(DMA_PUT , chan->pushbuf_base); RAMFC_WR(DMA_GET , chan->pushbuf_base); - RAMFC_WR(DMA_INSTANCE , pushbuf); + RAMFC_WR(DMA_INSTANCE , chan->pushbuf->instance >> 4); RAMFC_WR(DMA_FETCH , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | @@ -61,7 +64,7 @@ nv40_fifo_create_context(drm_device_t *dev, int channel) #endif 0x30000000 /* no idea.. */); RAMFC_WR(DMA_SUBROUTINE, 0); - RAMFC_WR(GRCTX_INSTANCE, grctx); + RAMFC_WR(GRCTX_INSTANCE, chan->ramin_grctx->instance >> 4); RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF); return 0; @@ -71,18 +74,17 @@ void nv40_fifo_destroy_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx = NV40_RAMFC(channel); - int i; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - for (i = 0; i < NV40_RAMFC__SIZE; i+=4) - NV_WI32(fifoctx + i, 0); + if (chan->ramfc) + nouveau_gpuobj_ref_del(dev, &chan->ramfc); } int nv40_fifo_load_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx = NV40_RAMFC(channel); + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; uint32_t tmp, tmp2; NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET)); @@ -141,7 +143,7 @@ int nv40_fifo_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t fifoctx = NV40_RAMFC(channel); + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; uint32_t tmp; RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index 6fb575db..3f33cee6 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -47,13 +47,13 @@ * created. */ static void -nv40_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +nv40_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) { drm_nouveau_private_t *dev_priv = dev->dev_private; int i; /* Always has the "instance address" of itself at offset 0 */ - INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx)); + INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); /* unknown */ INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff); INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff); @@ -188,12 +188,12 @@ nv40_graph_context_init(drm_device_t *dev, struct mem_block *ctx) } static void -nv43_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +nv43_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) { drm_nouveau_private_t *dev_priv = dev->dev_private; int i; - INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx)); + INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff); INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff); INSTANCE_WR(ctx, 0x00030/4, 0x00000001); @@ -304,12 +304,12 @@ nv43_graph_context_init(drm_device_t *dev, struct mem_block *ctx) }; static void -nv46_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +nv46_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) { drm_nouveau_private_t *dev_priv = dev->dev_private; int i; - INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx)); + INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); INSTANCE_WR(ctx, 0x00040/4, 0x0000ffff); INSTANCE_WR(ctx, 0x00044/4, 0x0000ffff); INSTANCE_WR(ctx, 0x0004c/4, 0x00000001); @@ -455,12 +455,12 @@ nv46_graph_context_init(drm_device_t *dev, struct mem_block *ctx) } static void -nv49_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +nv49_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) { drm_nouveau_private_t *dev_priv = dev->dev_private; int i; - INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx)); + INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); INSTANCE_WR(ctx, 0x00004/4, 0x0000c040); INSTANCE_WR(ctx, 0x00008/4, 0x0000c040); INSTANCE_WR(ctx, 0x0000c/4, 0x0000c040); @@ -678,12 +678,12 @@ nv49_graph_context_init(drm_device_t *dev, struct mem_block *ctx) } static void -nv4a_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +nv4a_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) { drm_nouveau_private_t *dev_priv = dev->dev_private; int i; - INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx)); + INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff); INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff); INSTANCE_WR(ctx, 0x00030/4, 0x00000001); @@ -795,12 +795,12 @@ nv4a_graph_context_init(drm_device_t *dev, struct mem_block *ctx) } static void -nv4b_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +nv4b_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) { drm_nouveau_private_t *dev_priv = dev->dev_private; int i; - INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx)); + INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); INSTANCE_WR(ctx, 0x00004/4, 0x0000c040); INSTANCE_WR(ctx, 0x00008/4, 0x0000c040); INSTANCE_WR(ctx, 0x0000c/4, 0x0000c040); @@ -1010,12 +1010,12 @@ nv4b_graph_context_init(drm_device_t *dev, struct mem_block *ctx) } static void -nv4c_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +nv4c_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) { drm_nouveau_private_t *dev_priv = dev->dev_private; int i; - INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx)); + INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff); INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff); INSTANCE_WR(ctx, 0x00030/4, 0x00000001); @@ -1117,12 +1117,12 @@ nv4c_graph_context_init(drm_device_t *dev, struct mem_block *ctx) } static void -nv4e_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +nv4e_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) { drm_nouveau_private_t *dev_priv = dev->dev_private; int i; - INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx)); + INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff); INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff); INSTANCE_WR(ctx, 0x00030/4, 0x00000001); @@ -1229,9 +1229,9 @@ nv40_graph_create_context(drm_device_t *dev, int channel) drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - void (*ctx_init)(drm_device_t *, struct mem_block *); + void (*ctx_init)(drm_device_t *, nouveau_gpuobj_t *); unsigned int ctx_size; - int i; + int ret; switch (dev_priv->chipset) { case 0x40: @@ -1272,15 +1272,13 @@ nv40_graph_create_context(drm_device_t *dev, int channel) break; } - /* Alloc and clear RAMIN to store the context */ - chan->ramin_grctx = nouveau_instmem_alloc(dev, ctx_size, 4); - if (!chan->ramin_grctx) - return DRM_ERR(ENOMEM); - for (i=0; iramin_grctx, i/4, 0x00000000); + if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, ctx_size, 16, + NVOBJ_FLAG_ZERO_ALLOC, + &chan->ramin_grctx))) + return ret; /* Initialise default context values */ - ctx_init(dev, chan->ramin_grctx); + ctx_init(dev, chan->ramin_grctx->gpuobj); return 0; } @@ -1291,10 +1289,8 @@ nv40_graph_destroy_context(drm_device_t *dev, int channel) drm_nouveau_private_t *dev_priv = dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - if (chan->ramin_grctx) { - nouveau_instmem_free(dev, chan->ramin_grctx); - chan->ramin_grctx = NULL; - } + if (chan->ramin_grctx) + nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); } static int @@ -1339,7 +1335,7 @@ nv40_graph_save_context(drm_device_t *dev, int channel) if (!chan->ramin_grctx) return DRM_ERR(EINVAL); - inst = nouveau_chip_instance_get(dev, chan->ramin_grctx); + inst = chan->ramin_grctx->instance >> 4; return nv40_graph_transfer_context(dev, inst, 1); } @@ -1357,7 +1353,7 @@ nv40_graph_load_context(drm_device_t *dev, int channel) if (!chan->ramin_grctx) return DRM_ERR(EINVAL); - inst = nouveau_chip_instance_get(dev, chan->ramin_grctx); + inst = chan->ramin_grctx->instance >> 4; ret = nv40_graph_transfer_context(dev, inst, 0); if (ret) -- cgit v1.2.3 From 3324342e42b78aef8e90e11273776dd2b3b92074 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 4 Jul 2007 15:31:01 +1000 Subject: nouveau: enable reporting for all PFIFO/PGRAPH irqs --- shared-core/nouveau_irq.c | 26 +++----------------------- 1 file changed, 3 insertions(+), 23 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 8de6e705..72b12e0c 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -87,34 +87,14 @@ void nouveau_irq_postinstall(drm_device_t *dev) DRM_DEBUG("IRQ: postinst\n"); /* Enable PFIFO error reporting */ - NV_WRITE(NV03_PFIFO_INTR_EN_0 , - NV_PFIFO_INTR_CACHE_ERROR | - NV_PFIFO_INTR_RUNOUT | - NV_PFIFO_INTR_RUNOUT_OVERFLOW | - NV_PFIFO_INTR_DMA_PUSHER | - NV_PFIFO_INTR_DMA_PT | - NV_PFIFO_INTR_SEMAPHORE | - NV_PFIFO_INTR_ACQUIRE_TIMEOUT - ); + NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF); NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF); /* Enable PGRAPH interrupts */ if (dev_priv->card_type Date: Thu, 5 Jul 2007 00:12:33 +1000 Subject: nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80. --- shared-core/nouveau_drv.h | 46 ++++++-- shared-core/nouveau_fifo.c | 99 +++++++++------- shared-core/nouveau_irq.c | 15 ++- shared-core/nouveau_mem.c | 143 +--------------------- shared-core/nouveau_notifier.c | 6 +- shared-core/nouveau_object.c | 70 ++++++----- shared-core/nouveau_reg.h | 12 +- shared-core/nouveau_state.c | 41 ++++++- shared-core/nv04_fifo.c | 13 +- shared-core/nv04_graph.c | 10 +- shared-core/nv04_instmem.c | 165 ++++++++++++++++++++++++++ shared-core/nv10_fifo.c | 12 +- shared-core/nv10_graph.c | 8 +- shared-core/nv20_graph.c | 8 +- shared-core/nv30_graph.c | 8 +- shared-core/nv40_fifo.c | 12 +- shared-core/nv40_graph.c | 8 +- shared-core/nv50_fifo.c | 259 +++++++++++++++++++++++++++++++++++++++- shared-core/nv50_graph.c | 231 ++++++++++++++++++++++++++++++++++-- shared-core/nv50_instmem.c | 262 +++++++++++++++++++++++++++++++++++++++++ 20 files changed, 1152 insertions(+), 276 deletions(-) create mode 100644 shared-core/nv04_instmem.c create mode 100644 shared-core/nv50_instmem.c (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 73793b34..81972db5 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -72,6 +72,7 @@ typedef struct nouveau_gpuobj { int im_channel; struct mem_block *im_pramin; struct mem_block *im_backing; + int im_bound; uint32_t flags; int refcount; @@ -92,7 +93,6 @@ typedef struct nouveau_gpuobj_ref { struct nouveau_fifo { - int used; /* owner of this fifo */ DRMFILE filp; /* mapping of the fifo itself */ @@ -101,8 +101,8 @@ struct nouveau_fifo drm_local_map_t *regs; /* DMA push buffer */ - struct mem_block *cmdbuf_mem; nouveau_gpuobj_ref_t *pushbuf; + struct mem_block *pushbuf_mem; uint32_t pushbuf_base; /* Notifier memory */ @@ -132,6 +132,19 @@ struct nouveau_config { }; typedef struct nouveau_engine_func { + struct { + void *priv; + + int (*init)(drm_device_t *dev); + void (*takedown)(drm_device_t *dev); + + int (*populate)(drm_device_t *, nouveau_gpuobj_t *, + uint32_t *size); + void (*clear)(drm_device_t *, nouveau_gpuobj_t *); + int (*bind)(drm_device_t *, nouveau_gpuobj_t *); + int (*unbind)(drm_device_t *, nouveau_gpuobj_t *); + } instmem; + struct { int (*init)(drm_device_t *dev); void (*takedown)(drm_device_t *dev); @@ -158,6 +171,8 @@ typedef struct nouveau_engine_func { } graph; struct { + void *priv; + int (*init)(drm_device_t *); void (*takedown)(drm_device_t *); @@ -180,13 +195,13 @@ typedef struct drm_nouveau_private { drm_local_map_t *ramin; /* NV40 onwards */ int fifo_alloc_count; - struct nouveau_fifo fifos[NV_MAX_FIFO_NUMBER]; + struct nouveau_fifo *fifos[NV_MAX_FIFO_NUMBER]; struct nouveau_engine_func Engine; /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ nouveau_gpuobj_t *ramht; - uint32_t ramin_size; + uint32_t ramin_rsvd_vram; uint32_t ramht_offset; uint32_t ramht_size; uint32_t ramht_bits; @@ -246,11 +261,6 @@ extern struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment extern void nouveau_mem_free(struct drm_device* dev, struct mem_block*); extern int nouveau_mem_init(struct drm_device *dev); extern void nouveau_mem_close(struct drm_device *dev); -extern int nouveau_instmem_init(struct drm_device *dev); -extern struct mem_block* nouveau_instmem_alloc(struct drm_device *dev, - uint32_t size, uint32_t align); -extern void nouveau_instmem_free(struct drm_device *dev, - struct mem_block *block); /* nouveau_notifier.c */ extern int nouveau_notifier_init_channel(drm_device_t *, int channel, DRMFILE); @@ -386,6 +396,24 @@ extern void nv50_graph_destroy_context(drm_device_t *, int channel); extern int nv50_graph_load_context(drm_device_t *, int channel); extern int nv50_graph_save_context(drm_device_t *, int channel); +/* nv04_instmem.c */ +extern int nv04_instmem_init(drm_device_t *dev); +extern void nv04_instmem_takedown(drm_device_t *dev); +extern int nv04_instmem_populate(drm_device_t*, nouveau_gpuobj_t*, + uint32_t *size); +extern void nv04_instmem_clear(drm_device_t*, nouveau_gpuobj_t*); +extern int nv04_instmem_bind(drm_device_t*, nouveau_gpuobj_t*); +extern int nv04_instmem_unbind(drm_device_t*, nouveau_gpuobj_t*); + +/* nv50_instmem.c */ +extern int nv50_instmem_init(drm_device_t *dev); +extern void nv50_instmem_takedown(drm_device_t *dev); +extern int nv50_instmem_populate(drm_device_t*, nouveau_gpuobj_t*, + uint32_t *size); +extern void nv50_instmem_clear(drm_device_t*, nouveau_gpuobj_t*); +extern int nv50_instmem_bind(drm_device_t*, nouveau_gpuobj_t*); +extern int nv50_instmem_unbind(drm_device_t*, nouveau_gpuobj_t*); + /* nv04_mc.c */ extern int nv04_mc_init(drm_device_t *dev); extern void nv04_mc_takedown(drm_device_t *dev); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 9f916307..c140a634 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -39,6 +39,8 @@ int nouveau_fifo_number(drm_device_t* dev) case NV_04: case NV_05: return 16; + case NV_50: + return 128; default: return 32; } @@ -186,7 +188,7 @@ static int nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; struct nouveau_config *config = &dev_priv->config; struct mem_block *cb; int cb_min_size = max(NV03_FIFO_SIZE,PAGE_SIZE); @@ -242,8 +244,8 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) return ret; } - dev_priv->fifos[channel].pushbuf_base = 0; - dev_priv->fifos[channel].cmdbuf_mem = cb; + dev_priv->fifos[channel]->pushbuf_base = 0; + dev_priv->fifos[channel]->pushbuf_mem = cb; return 0; } @@ -265,22 +267,27 @@ int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp, * (woo, full userspace command submission !) * When there are no more contexts, you lost */ - for(channel=0; channelfifos[channel].used==0) + for(channel=0; channelcard_type == NV_50) && (channel == 0)) + continue; + if (dev_priv->fifos[channel] == NULL) break; + } /* no more fifos. you lost. */ if (channel==nouveau_fifo_number(dev)) return DRM_ERR(EINVAL); (*chan_ret) = channel; - chan = &dev_priv->fifos[channel]; - memset(chan, sizeof(*chan), 0); - - DRM_INFO("Allocating FIFO number %d\n", channel); - /* that fifo is used */ - chan->used = 1; + dev_priv->fifos[channel] = drm_calloc(1, sizeof(struct nouveau_fifo), + DRM_MEM_DRIVER); + if (!dev_priv->fifos[channel]) + return DRM_ERR(ENOMEM); + dev_priv->fifo_alloc_count++; + chan = dev_priv->fifos[channel]; chan->filp = filp; + DRM_INFO("Allocating FIFO number %d\n", channel); + /* Setup channel's default objects */ ret = nouveau_gpuobj_channel_init(dev, channel, vram_handle, tt_handle); if (ret) { @@ -324,17 +331,19 @@ int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp, return ret; } - /* enable the fifo dma operation */ - NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<pushbuf_base); - NV_WRITE(NV03_FIFO_REGS_DMAGET(channel), chan->pushbuf_base); + if (dev_priv->card_type < NV_50) { + NV_WRITE(NV03_FIFO_REGS_DMAPUT(channel), chan->pushbuf_base); + NV_WRITE(NV03_FIFO_REGS_DMAGET(channel), chan->pushbuf_base); + } else { + NV_WRITE(NV50_FIFO_REGS_DMAPUT(channel), chan->pushbuf_base); + NV_WRITE(NV50_FIFO_REGS_DMAGET(channel), chan->pushbuf_base); + } /* If this is the first channel, setup PFIFO ourselves. For any * other case, the GPU will handle this when it switches contexts. */ - if (dev_priv->fifo_alloc_count == 0) { + if (dev_priv->fifo_alloc_count == 1) { ret = engine->fifo.load_context(dev, channel); if (ret) { nouveau_fifo_free(dev, channel); @@ -352,7 +361,7 @@ int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp, * set. Proper fix would be to find which object+method is * responsible for modifying this state. */ - if (dev_priv->chipset >= 0x10) { + if (dev_priv->chipset >= 0x10 && dev_priv->chipset < 0x50) { uint32_t tmp; tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; NV_WRITE(NV10_PGRAPH_SURFACE, tmp); @@ -361,15 +370,14 @@ int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp, } } - NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, + NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) | 1); NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001); NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001); NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001); /* reenable the fifo caches */ - NV_WRITE(NV03_PFIFO_CACHES, 0x00000001); - - dev_priv->fifo_alloc_count++; + NV_WRITE(NV03_PFIFO_CACHES, 1); DRM_INFO("%s: initialised FIFO %d\n", __func__, channel); return 0; @@ -380,17 +388,20 @@ void nouveau_fifo_free(drm_device_t* dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; nouveau_engine_func_t *engine = &dev_priv->Engine; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + + if (!chan) { + DRM_ERROR("Freeing non-existant channel %d\n", channel); + return; + } - chan->used = 0; DRM_INFO("%s: freeing fifo %d\n", __func__, channel); /* disable the fifo caches */ NV_WRITE(NV03_PFIFO_CACHES, 0x00000000); - NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<fifo.destroy_context(dev, channel); /* Cleanup PGRAPH state */ @@ -399,13 +410,11 @@ void nouveau_fifo_free(drm_device_t* dev, int channel) /* reenable the fifo caches */ NV_WRITE(NV03_PFIFO_CACHES, 0x00000001); - /* Deallocate command buffer */ - if (chan->pushbuf) - nouveau_gpuobj_ref_del(dev, &chan->pushbuf); - - if (chan->cmdbuf_mem) { - nouveau_mem_free(dev, chan->cmdbuf_mem); - chan->cmdbuf_mem = NULL; + /* Deallocate push buffer */ + nouveau_gpuobj_ref_del(dev, &chan->pushbuf); + if (chan->pushbuf_mem) { + nouveau_mem_free(dev, chan->pushbuf_mem); + chan->pushbuf_mem = NULL; } nouveau_notifier_takedown_channel(dev, channel); @@ -413,7 +422,9 @@ void nouveau_fifo_free(drm_device_t* dev, int channel) /* Destroy objects belonging to the channel */ nouveau_gpuobj_channel_takedown(dev, channel); + dev_priv->fifos[channel] = NULL; dev_priv->fifo_alloc_count--; + drm_free(chan, sizeof(*chan), DRM_MEM_DRIVER); } /* cleanups all the fifos from filp */ @@ -424,7 +435,7 @@ void nouveau_fifo_cleanup(drm_device_t* dev, DRMFILE filp) DRM_DEBUG("clearing FIFO enables from filp\n"); for(i=0;ififos[i].used && dev_priv->fifos[i].filp==filp) + if (dev_priv->fifos[i] && dev_priv->fifos[i]->filp==filp) nouveau_fifo_free(dev,i); } @@ -435,9 +446,9 @@ nouveau_fifo_owner(drm_device_t *dev, DRMFILE filp, int channel) if (channel >= nouveau_fifo_number(dev)) return 0; - if (dev_priv->fifos[channel].used == 0) + if (dev_priv->fifos[channel] == NULL) return 0; - return (dev_priv->fifos[channel].filp == filp); + return (dev_priv->fifos[channel]->filp == filp); } /*********************************** @@ -460,22 +471,28 @@ static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) init.tt_ctxdma_handle); if (res) return res; - chan = &dev_priv->fifos[init.channel]; + chan = dev_priv->fifos[init.channel]; init.put_base = chan->pushbuf_base; /* make the fifo available to user space */ /* first, the fifo control regs */ - init.ctrl = dev_priv->mmio->offset + NV03_FIFO_REGS(init.channel); - init.ctrl_size = NV03_FIFO_REGS_SIZE; + init.ctrl = dev_priv->mmio->offset; + if (dev_priv->card_type < NV_50) { + init.ctrl += NV03_FIFO_REGS(init.channel); + init.ctrl_size = NV03_FIFO_REGS_SIZE; + } else { + init.ctrl += NV50_FIFO_REGS(init.channel); + init.ctrl_size = NV50_FIFO_REGS_SIZE; + } res = drm_addmap(dev, init.ctrl, init.ctrl_size, _DRM_REGISTERS, 0, &chan->regs); if (res != 0) return res; /* pass back FIFO map info to the caller */ - init.cmdbuf = chan->cmdbuf_mem->start; - init.cmdbuf_size = chan->cmdbuf_mem->size; + init.cmdbuf = chan->pushbuf_mem->start; + init.cmdbuf_size = chan->pushbuf_mem->size; /* and the notifier block */ init.notifier = chan->notifier_block->start; diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 72b12e0c..b4102dd8 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -251,22 +251,25 @@ nouveau_graph_dump_trap_info(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; uint32_t address; - uint32_t channel; + uint32_t channel, class; uint32_t method, subc, data; address = NV_READ(0x400704); - data = NV_READ(0x400708); channel = (address >> 20) & 0x1F; subc = (address >> 16) & 0x7; method = address & 0x1FFC; + data = NV_READ(0x400708); + if (dev_priv->card_type < NV_50) { + class = NV_READ(0x400160 + subc*4) & 0xFFFF; + } else { + class = NV_READ(0x400814); + } DRM_ERROR("NV: nSource: 0x%08x, nStatus: 0x%08x\n", NV_READ(0x400108), NV_READ(0x400104)); DRM_ERROR("NV: Channel %d/%d (class 0x%04x) -" "Method 0x%04x, Data 0x%08x\n", - channel, subc, - NV_READ(0x400160+subc*4) & 0xFFFF, - method, data + channel, subc, class, method, data ); } @@ -294,7 +297,7 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev) instance = NV_READ(0x00400158); notify = NV_READ(0x00400150) >> 16; DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n", - nsource, nstatus); + instance, notify); } status &= ~NV_PGRAPH_INTR_NOTIFY; diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 49041862..c75a9356 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -353,7 +353,7 @@ no_agp: /* On at least NV40, RAMIN is actually at the end of vram. * We don't want to allocate this... */ if (dev_priv->card_type >= NV_40) - fb_size -= dev_priv->ramin_size; + fb_size -= dev_priv->ramin_rsvd_vram; dev_priv->fb_available_size = fb_size; DRM_DEBUG("Available VRAM: %dKiB\n", fb_size>>10); @@ -463,147 +463,6 @@ void nouveau_mem_free(struct drm_device* dev, struct mem_block* block) nouveau_mem_free_block(block); } -static void -nouveau_instmem_determine_amount(struct drm_device *dev) -{ - drm_nouveau_private_t *dev_priv = dev->dev_private; - int i; - - /* Figure out how much instance memory we need */ - switch (dev_priv->card_type) { - case NV_40: - /* We'll want more instance memory than this on some NV4x cards. - * There's a 16MB aperture to play with that maps onto the end - * of vram. For now, only reserve a small piece until we know - * more about what each chipset requires. - */ - dev_priv->ramin_size = (1*1024* 1024); - break; - default: - /*XXX: what *are* the limits on ramin_size = (512*1024); - break; - } - DRM_DEBUG("RAMIN size: %dKiB\n", dev_priv->ramin_size>>10); - - /* Clear all of it, except the BIOS image that's in the first 64KiB */ - for (i=(64*1024); iramin_size; i+=4) - NV_WI32(i, 0x00000000); -} - -static void -nouveau_instmem_configure_fixed_tables(struct drm_device *dev) -{ - drm_nouveau_private_t *dev_priv = dev->dev_private; - - /* FIFO hash table (RAMHT) - * use 4k hash table at RAMIN+0x10000 - * TODO: extend the hash table - */ - dev_priv->ramht_offset = 0x10000; - dev_priv->ramht_bits = 9; - dev_priv->ramht_size = (1 << dev_priv->ramht_bits); - DRM_DEBUG("RAMHT offset=0x%x, size=%d\n", dev_priv->ramht_offset, - dev_priv->ramht_size); - - /* FIFO runout table (RAMRO) - 512k at 0x11200 */ - dev_priv->ramro_offset = 0x11200; - dev_priv->ramro_size = 512; - DRM_DEBUG("RAMRO offset=0x%x, size=%d\n", dev_priv->ramro_offset, - dev_priv->ramro_size); - - /* FIFO context table (RAMFC) - * NV40 : Not sure exactly how to position RAMFC on some cards, - * 0x30002 seems to position it at RAMIN+0x20000 on these - * cards. RAMFC is 4kb (32 fifos, 128byte entries). - * Others: Position RAMFC at RAMIN+0x11400 - */ - switch(dev_priv->card_type) - { - case NV_50: - case NV_40: - case NV_44: - dev_priv->ramfc_offset = 0x20000; - dev_priv->ramfc_size = nouveau_fifo_number(dev) * - nouveau_fifo_ctx_size(dev); - break; - case NV_30: - case NV_20: - case NV_17: - case NV_10: - case NV_04: - case NV_03: - default: - dev_priv->ramfc_offset = 0x11400; - dev_priv->ramfc_size = nouveau_fifo_number(dev) * - nouveau_fifo_ctx_size(dev); - break; - } - DRM_DEBUG("RAMFC offset=0x%x, size=%d\n", dev_priv->ramfc_offset, - dev_priv->ramfc_size); -} - -int nouveau_instmem_init(struct drm_device *dev) -{ - drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t offset; - int ret = 0; - - nouveau_instmem_determine_amount(dev); - nouveau_instmem_configure_fixed_tables(dev); - - if ((ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramht_offset, - dev_priv->ramht_size, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ALLOW_NO_REFS, - &dev_priv->ramht, NULL))) - return ret; - - /* Create a heap to manage RAMIN allocations, we don't allocate - * the space that was reserved for RAMHT/FC/RO. - */ - offset = dev_priv->ramfc_offset + dev_priv->ramfc_size; - ret = nouveau_mem_init_heap(&dev_priv->ramin_heap, - offset, dev_priv->ramin_size - offset); - if (ret) { - dev_priv->ramin_heap = NULL; - DRM_ERROR("Failed to init RAMIN heap\n"); - } - - return ret; -} - -struct mem_block *nouveau_instmem_alloc(struct drm_device *dev, - uint32_t size, uint32_t align) -{ - drm_nouveau_private_t *dev_priv = dev->dev_private; - struct mem_block *block; - - if (!dev_priv->ramin_heap) { - DRM_ERROR("instmem alloc called without init\n"); - return NULL; - } - - block = nouveau_mem_alloc_block(dev_priv->ramin_heap, size, align, - (DRMFILE)-2); - if (block) { - block->flags = NOUVEAU_MEM_INSTANCE; - DRM_DEBUG("instance(size=%d, align=%d) alloc'd at 0x%08x\n", - size, (1<start); - } - - return block; -} - -void nouveau_instmem_free(struct drm_device *dev, struct mem_block *block) -{ - if (dev && block) { - nouveau_mem_free_block(block); - } -} - /* * Ioctls */ diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index 4d5e26ab..9e792e57 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -33,7 +33,7 @@ int nouveau_notifier_init_channel(drm_device_t *dev, int channel, DRMFILE filp) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; int flags, ret; /*TODO: PCI notifier blocks */ @@ -58,7 +58,7 @@ void nouveau_notifier_takedown_channel(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; if (chan->notifier_block) { nouveau_mem_free(dev, chan->notifier_block); @@ -73,7 +73,7 @@ nouveau_notifier_alloc(drm_device_t *dev, int channel, uint32_t handle, int count, uint32_t *b_offset) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; nouveau_gpuobj_t *nobj = NULL; struct mem_block *mem; uint32_t offset; diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 79875ca1..a394ae6e 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -76,7 +76,8 @@ nouveau_ramht_hash_handle(drm_device_t *dev, int channel, uint32_t handle) hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1)); handle >>= dev_priv->ramht_bits; } - hash ^= channel << (dev_priv->ramht_bits - 4); + if (dev_priv->card_type < NV_50) + hash ^= channel << (dev_priv->ramht_bits - 4); hash <<= 3; DRM_DEBUG("ch%d handle=0x%08x hash=0x%08x\n", channel, handle, hash); @@ -99,7 +100,7 @@ static int nouveau_ramht_insert(drm_device_t* dev, nouveau_gpuobj_ref_t *ref) { drm_nouveau_private_t *dev_priv=dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[ref->channel]; + struct nouveau_fifo *chan = dev_priv->fifos[ref->channel]; nouveau_gpuobj_t *ramht = chan->ramht ? chan->ramht->gpuobj : NULL; nouveau_gpuobj_t *gpuobj = ref->gpuobj; uint32_t ctx, co, ho; @@ -148,7 +149,7 @@ static void nouveau_ramht_remove(drm_device_t* dev, nouveau_gpuobj_ref_t *ref) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[ref->channel]; + struct nouveau_fifo *chan = dev_priv->fifos[ref->channel]; nouveau_gpuobj_t *ramht = chan->ramht ? chan->ramht->gpuobj : NULL; uint32_t co, ho; @@ -183,9 +184,11 @@ nouveau_gpuobj_new(drm_device_t *dev, int channel, int size, int align, uint32_t flags, nouveau_gpuobj_t **gpuobj_ret) { drm_nouveau_private_t *dev_priv = dev->dev_private; + nouveau_engine_func_t *engine = &dev_priv->Engine; struct nouveau_fifo *chan = NULL; nouveau_gpuobj_t *gpuobj; struct mem_block *pramin = NULL; + int ret; DRM_DEBUG("ch%d size=%d align=%d flags=0x%08x\n", channel, size, align, flags); @@ -196,7 +199,7 @@ nouveau_gpuobj_new(drm_device_t *dev, int channel, int size, int align, if (channel >= 0) { if (channel > nouveau_fifo_number(dev)) return DRM_ERR(EINVAL); - chan = &dev_priv->fifos[channel]; + chan = dev_priv->fifos[channel]; } gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER); @@ -230,6 +233,11 @@ nouveau_gpuobj_new(drm_device_t *dev, int channel, int size, int align, return DRM_ERR(EINVAL); } + if (!chan && (ret = engine->instmem.populate(dev, gpuobj, &size))) { + nouveau_gpuobj_del(dev, &gpuobj); + return ret; + } + /* Allocate a chunk of the PRAMIN aperture */ gpuobj->im_pramin = nouveau_mem_alloc_block(pramin, size, drm_order(align), @@ -240,14 +248,9 @@ nouveau_gpuobj_new(drm_device_t *dev, int channel, int size, int align, } gpuobj->im_pramin->flags = NOUVEAU_MEM_INSTANCE; - /* On NV50 the PRAMIN aperture is paged. When allocating from the - * global instmem heap, alloc and bind VRAM pages into the PRAMIN - * aperture. - */ - if (!chan && dev_priv->card_type >= NV_50) { - DRM_ERROR("back aperture with vram pages\n"); + if (!chan && (ret = engine->instmem.bind(dev, gpuobj))) { nouveau_gpuobj_del(dev, &gpuobj); - return DRM_ERR(EINVAL); + return ret; } if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) { @@ -285,6 +288,7 @@ void nouveau_gpuobj_takedown(drm_device_t *dev) int nouveau_gpuobj_del(drm_device_t *dev, nouveau_gpuobj_t **pgpuobj) { drm_nouveau_private_t *dev_priv = dev->dev_private; + nouveau_engine_func_t *engine = &dev_priv->Engine; nouveau_gpuobj_t *gpuobj; DRM_DEBUG("gpuobj %p\n", pgpuobj ? *pgpuobj : NULL); @@ -298,6 +302,8 @@ int nouveau_gpuobj_del(drm_device_t *dev, nouveau_gpuobj_t **pgpuobj) return DRM_ERR(EINVAL); } + engine->instmem.clear(dev, gpuobj); + if (gpuobj->im_pramin) { if (gpuobj->flags & NVOBJ_FLAG_FAKE) drm_free(gpuobj->im_pramin, sizeof(*gpuobj->im_pramin), @@ -306,9 +312,6 @@ int nouveau_gpuobj_del(drm_device_t *dev, nouveau_gpuobj_t **pgpuobj) nouveau_mem_free_block(gpuobj->im_pramin); } - if (gpuobj->im_backing) - nouveau_mem_free(dev, gpuobj->im_backing); - if (gpuobj->next) gpuobj->next->prev = gpuobj->prev; if (gpuobj->prev) @@ -342,7 +345,7 @@ nouveau_gpuobj_instance_get(drm_device_t *dev, int channel, /* NV50 channel-local instance */ if (channel > 0) { - cpramin = dev_priv->fifos[channel].ramin->gpuobj; + cpramin = dev_priv->fifos[channel]->ramin->gpuobj; *inst = gpuobj->im_pramin->start - cpramin->im_pramin->start; return 0; } @@ -358,7 +361,7 @@ nouveau_gpuobj_instance_get(drm_device_t *dev, int channel, return 0; } else { /* ...from local heap */ - cpramin = dev_priv->fifos[gpuobj->im_channel].ramin->gpuobj; + cpramin = dev_priv->fifos[gpuobj->im_channel]->ramin->gpuobj; *inst = (cpramin->im_backing->start - dev_priv->fb_phys) + (gpuobj->im_pramin->start - cpramin->im_pramin->start); return 0; @@ -385,7 +388,7 @@ nouveau_gpuobj_ref_add(drm_device_t *dev, int channel, uint32_t handle, if (channel >= 0) { if (channel > nouveau_fifo_number(dev)) return DRM_ERR(EINVAL); - chan = &dev_priv->fifos[channel]; + chan = dev_priv->fifos[channel]; } else if (!ref_ret) return DRM_ERR(EINVAL); @@ -591,9 +594,10 @@ nouveau_gpuobj_dma_new(drm_device_t *dev, int channel, int class, INSTANCE_WR(*gpuobj, 2, frame | pte_flags); INSTANCE_WR(*gpuobj, 3, frame | pte_flags); } else { - nouveau_gpuobj_del(dev, gpuobj); - DRM_ERROR("stub\n"); - return DRM_ERR(EINVAL); + INSTANCE_WR(*gpuobj, 0, 0x00190000 | class); + INSTANCE_WR(*gpuobj, 1, offset + size - 1); + INSTANCE_WR(*gpuobj, 2, offset); + INSTANCE_WR(*gpuobj, 5, 0x00010000); } (*gpuobj)->engine = NVOBJ_ENGINE_SW; @@ -672,11 +676,9 @@ nouveau_gpuobj_gr_new(drm_device_t *dev, int channel, int class, } if (dev_priv->card_type >= NV_50) { - nouveau_gpuobj_del(dev, gpuobj); - DRM_ERROR("stub!\n"); - return DRM_ERR(EINVAL); - } - + INSTANCE_WR(*gpuobj, 0, class); + INSTANCE_WR(*gpuobj, 5, 0x00010000); + } else { switch (class) { case NV_CLASS_NULL: INSTANCE_WR(*gpuobj, 0, 0x00001030); @@ -696,6 +698,7 @@ nouveau_gpuobj_gr_new(drm_device_t *dev, int channel, int class, #endif } } + } (*gpuobj)->engine = NVOBJ_ENGINE_GR; (*gpuobj)->class = class; @@ -706,7 +709,7 @@ static int nouveau_gpuobj_channel_init_pramin(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; nouveau_gpuobj_t *pramin = NULL; int size, base, ret; @@ -719,7 +722,16 @@ nouveau_gpuobj_channel_init_pramin(drm_device_t *dev, int channel) /* PGRAPH context */ if (dev_priv->card_type == NV_50) { - /* RAMHT, RAMFC, PD, funny header thingo */ + /* Various fixed table thingos */ + size += 0x1400; /* mostly unknown stuff */ + size += 0x4000; /* vm pd */ + base = 0x6000; + /* RAMHT, not sure about setting size yet, 32KiB to be safe */ + size += 0x8000; + /* RAMFC */ + size += 0x1000; + /* PGRAPH context */ + size += 0x60000; } DRM_DEBUG("ch%d PRAMIN size: 0x%08x bytes, base alloc=0x%08x\n", @@ -748,7 +760,7 @@ nouveau_gpuobj_channel_init(drm_device_t *dev, int channel, uint32_t vram_h, uint32_t tt_h) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; nouveau_gpuobj_t *vram = NULL, *tt = NULL; int ret; @@ -817,7 +829,7 @@ void nouveau_gpuobj_channel_takedown(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; nouveau_gpuobj_ref_t *ref; DRM_DEBUG("ch%d\n", channel); diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 4c013c53..c2ebc714 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -47,11 +47,15 @@ #define NV_CLASS_DMA_IN_MEMORY 0x0000003D #define NV03_FIFO_SIZE 0x8000UL -#define NV_MAX_FIFO_NUMBER 32 +#define NV_MAX_FIFO_NUMBER 128 #define NV03_FIFO_REGS_SIZE 0x10000 #define NV03_FIFO_REGS(i) (0x00800000+i*NV03_FIFO_REGS_SIZE) # define NV03_FIFO_REGS_DMAPUT(i) (NV03_FIFO_REGS(i)+0x40) # define NV03_FIFO_REGS_DMAGET(i) (NV03_FIFO_REGS(i)+0x44) +#define NV50_FIFO_REGS_SIZE 0x2000 +#define NV50_FIFO_REGS(i) (0x00c00000+i*NV50_FIFO_REGS_SIZE) +# define NV50_FIFO_REGS_DMAPUT(i) (NV50_FIFO_REGS(i)+0x40) +# define NV50_FIFO_REGS_DMAGET(i) (NV50_FIFO_REGS(i)+0x44) #define NV03_PMC_BOOT_0 0x00000000 #define NV03_PMC_INTR_0 0x00000100 @@ -332,6 +336,12 @@ #define NV04_PFIFO_MODE 0x00002504 #define NV04_PFIFO_DMA 0x00002508 #define NV04_PFIFO_SIZE 0x0000250c +#define NV50_PFIFO_CTX_TABLE(c) (0x2600+(c)*4) +#define NV50_PFIFO_CTX_TABLE__SIZE 128 +#define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED (1<<31) +#define NV50_PFIFO_CTX_TABLE_UNK30_BAD (1<<30) +#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 0x0FFFFFFF +#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 0x00FFFFFF #define NV03_PFIFO_CACHE0_PUSH0 0x00003000 #define NV03_PFIFO_CACHE0_PULL0 0x00003040 #define NV04_PFIFO_CACHE0_PULL0 0x00003050 diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 13bc930a..bcb974bf 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -95,6 +95,12 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) switch (dev_priv->chipset & 0xf0) { case 0x00: + engine->instmem.init = nv04_instmem_init; + engine->instmem.takedown= nv04_instmem_takedown; + engine->instmem.populate = nv04_instmem_populate; + engine->instmem.clear = nv04_instmem_clear; + engine->instmem.bind = nv04_instmem_bind; + engine->instmem.unbind = nv04_instmem_unbind; engine->mc.init = nv04_mc_init; engine->mc.takedown = nv04_mc_takedown; engine->timer.init = nv04_timer_init; @@ -115,6 +121,12 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) engine->fifo.save_context = nv04_fifo_save_context; break; case 0x10: + engine->instmem.init = nv04_instmem_init; + engine->instmem.takedown= nv04_instmem_takedown; + engine->instmem.populate = nv04_instmem_populate; + engine->instmem.clear = nv04_instmem_clear; + engine->instmem.bind = nv04_instmem_bind; + engine->instmem.unbind = nv04_instmem_unbind; engine->mc.init = nv04_mc_init; engine->mc.takedown = nv04_mc_takedown; engine->timer.init = nv04_timer_init; @@ -135,6 +147,12 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) engine->fifo.save_context = nv10_fifo_save_context; break; case 0x20: + engine->instmem.init = nv04_instmem_init; + engine->instmem.takedown= nv04_instmem_takedown; + engine->instmem.populate = nv04_instmem_populate; + engine->instmem.clear = nv04_instmem_clear; + engine->instmem.bind = nv04_instmem_bind; + engine->instmem.unbind = nv04_instmem_unbind; engine->mc.init = nv04_mc_init; engine->mc.takedown = nv04_mc_takedown; engine->timer.init = nv04_timer_init; @@ -155,6 +173,12 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) engine->fifo.save_context = nv10_fifo_save_context; break; case 0x30: + engine->instmem.init = nv04_instmem_init; + engine->instmem.takedown= nv04_instmem_takedown; + engine->instmem.populate = nv04_instmem_populate; + engine->instmem.clear = nv04_instmem_clear; + engine->instmem.bind = nv04_instmem_bind; + engine->instmem.unbind = nv04_instmem_unbind; engine->mc.init = nv04_mc_init; engine->mc.takedown = nv04_mc_takedown; engine->timer.init = nv04_timer_init; @@ -175,6 +199,12 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) engine->fifo.save_context = nv10_fifo_save_context; break; case 0x40: + engine->instmem.init = nv04_instmem_init; + engine->instmem.takedown= nv04_instmem_takedown; + engine->instmem.populate = nv04_instmem_populate; + engine->instmem.clear = nv04_instmem_clear; + engine->instmem.bind = nv04_instmem_bind; + engine->instmem.unbind = nv04_instmem_unbind; engine->mc.init = nv40_mc_init; engine->mc.takedown = nv40_mc_takedown; engine->timer.init = nv04_timer_init; @@ -196,6 +226,12 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) break; case 0x50: case 0x80: /* gotta love NVIDIA's consistency.. */ + engine->instmem.init = nv50_instmem_init; + engine->instmem.takedown= nv50_instmem_takedown; + engine->instmem.populate = nv50_instmem_populate; + engine->instmem.clear = nv50_instmem_clear; + engine->instmem.bind = nv50_instmem_bind; + engine->instmem.unbind = nv50_instmem_unbind; engine->mc.init = nv50_mc_init; engine->mc.takedown = nv50_mc_takedown; engine->timer.init = nouveau_stub_init; @@ -249,7 +285,7 @@ static int nouveau_card_init(drm_device_t *dev) * know exactly how much VRAM we're able to use for "normal" * purposes. */ - ret = nouveau_instmem_init(dev); + ret = engine->instmem.init(dev); if (ret) return ret; /* Setup the memory manager */ @@ -295,6 +331,7 @@ static void nouveau_card_takedown(drm_device_t *dev) engine->mc.takedown(dev); nouveau_gpuobj_takedown(dev); nouveau_mem_close(dev); + engine->instmem.takedown(dev); } /* here a client dies, release the stuff that was allocated for its filp */ @@ -456,6 +493,8 @@ void nouveau_wait_for_idle(struct drm_device *dev) case NV_03: while(NV_READ(NV03_PGRAPH_STATUS)); break; + case NV_50: + break; default: while(NV_READ(NV04_PGRAPH_STATUS)); break; diff --git a/shared-core/nv04_fifo.c b/shared-core/nv04_fifo.c index b84f74c1..e2e934d7 100644 --- a/shared-core/nv04_fifo.c +++ b/shared-core/nv04_fifo.c @@ -39,7 +39,7 @@ int nv04_fifo_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; int ret; if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(channel), @@ -60,6 +60,9 @@ nv04_fifo_create_context(drm_device_t *dev, int channel) NV_PFIFO_CACHE1_BIG_ENDIAN | #endif 0)); + + /* enable the fifo dma operation */ + NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + + NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<ramfc) nouveau_gpuobj_ref_del(dev, &chan->ramfc); @@ -77,7 +82,7 @@ int nv04_fifo_load_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, (1<<8) | channel); @@ -105,7 +110,7 @@ int nv04_fifo_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; RAMFC_WR(DMA_PUT, NV04_PFIFO_CACHE1_DMA_PUT); diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c index 1aaae33c..df23d279 100644 --- a/shared-core/nv04_graph.c +++ b/shared-core/nv04_graph.c @@ -309,7 +309,7 @@ void nouveau_nv04_context_switch(drm_device_t *dev) for (i = 0; ififos[channel_old].pgraph_ctx[index] = NV_READ(nv04_graph_ctx_regs[i].reg+j*4); + dev_priv->fifos[channel_old]->pgraph_ctx[index] = NV_READ(nv04_graph_ctx_regs[i].reg+j*4); index++; } @@ -321,7 +321,7 @@ void nouveau_nv04_context_switch(drm_device_t *dev) for (i = 0; ififos[channel].pgraph_ctx[index]); + NV_WRITE(nv04_graph_ctx_regs[i].reg+j*4, dev_priv->fifos[channel]->pgraph_ctx[index]); index++; } @@ -340,10 +340,10 @@ int nv04_graph_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; DRM_DEBUG("nv04_graph_context_create %d\n", channel); - memset(dev_priv->fifos[channel].pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].pgraph_ctx)); + memset(dev_priv->fifos[channel]->pgraph_ctx, 0, sizeof(dev_priv->fifos[channel]->pgraph_ctx)); //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; - dev_priv->fifos[channel].pgraph_ctx[0] = 0x0001ffff; + dev_priv->fifos[channel]->pgraph_ctx[0] = 0x0001ffff; /* is it really needed ??? */ //dev_priv->fifos[channel].pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4); //dev_priv->fifos[channel].pgraph_ctx[2] = NV_READ(0x004006b0); @@ -379,7 +379,7 @@ int nv04_graph_init(drm_device_t *dev) { // check the context is big enough for ( i = 0 ; isizeof(dev_priv->fifos[0].pgraph_ctx) ) + if ( sum*4>sizeof(dev_priv->fifos[0]->pgraph_ctx) ) DRM_ERROR("pgraph_ctx too small\n"); NV_WRITE(NV03_PGRAPH_INTR_EN, 0x00000000); diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c new file mode 100644 index 00000000..ac7d4347 --- /dev/null +++ b/shared-core/nv04_instmem.c @@ -0,0 +1,165 @@ +#include "drmP.h" +#include "drm.h" +#include "nouveau_drv.h" + +static void +nv04_instmem_determine_amount(struct drm_device *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + int i; + + /* Figure out how much instance memory we need */ + switch (dev_priv->card_type) { + case NV_40: + /* We'll want more instance memory than this on some NV4x cards. + * There's a 16MB aperture to play with that maps onto the end + * of vram. For now, only reserve a small piece until we know + * more about what each chipset requires. + */ + dev_priv->ramin_rsvd_vram = (1*1024* 1024); + break; + default: + /*XXX: what *are* the limits on ramin_rsvd_vram = (512*1024); + break; + } + DRM_DEBUG("RAMIN size: %dKiB\n", dev_priv->ramin_rsvd_vram>>10); + + /* Clear all of it, except the BIOS image that's in the first 64KiB */ + for (i=(64*1024); iramin_rsvd_vram; i+=4) + NV_WI32(i, 0x00000000); +} + +static void +nv04_instmem_configure_fixed_tables(struct drm_device *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + + /* FIFO hash table (RAMHT) + * use 4k hash table at RAMIN+0x10000 + * TODO: extend the hash table + */ + dev_priv->ramht_offset = 0x10000; + dev_priv->ramht_bits = 9; + dev_priv->ramht_size = (1 << dev_priv->ramht_bits); + DRM_DEBUG("RAMHT offset=0x%x, size=%d\n", dev_priv->ramht_offset, + dev_priv->ramht_size); + + /* FIFO runout table (RAMRO) - 512k at 0x11200 */ + dev_priv->ramro_offset = 0x11200; + dev_priv->ramro_size = 512; + DRM_DEBUG("RAMRO offset=0x%x, size=%d\n", dev_priv->ramro_offset, + dev_priv->ramro_size); + + /* FIFO context table (RAMFC) + * NV40 : Not sure exactly how to position RAMFC on some cards, + * 0x30002 seems to position it at RAMIN+0x20000 on these + * cards. RAMFC is 4kb (32 fifos, 128byte entries). + * Others: Position RAMFC at RAMIN+0x11400 + */ + switch(dev_priv->card_type) + { + case NV_40: + case NV_44: + dev_priv->ramfc_offset = 0x20000; + dev_priv->ramfc_size = nouveau_fifo_number(dev) * + nouveau_fifo_ctx_size(dev); + break; + case NV_30: + case NV_20: + case NV_17: + case NV_10: + case NV_04: + case NV_03: + default: + dev_priv->ramfc_offset = 0x11400; + dev_priv->ramfc_size = nouveau_fifo_number(dev) * + nouveau_fifo_ctx_size(dev); + break; + } + DRM_DEBUG("RAMFC offset=0x%x, size=%d\n", dev_priv->ramfc_offset, + dev_priv->ramfc_size); +} + +int nv04_instmem_init(struct drm_device *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t offset; + int ret = 0; + + nv04_instmem_determine_amount(dev); + nv04_instmem_configure_fixed_tables(dev); + + if ((ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramht_offset, + dev_priv->ramht_size, + NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_ALLOW_NO_REFS, + &dev_priv->ramht, NULL))) + return ret; + + /* Create a heap to manage RAMIN allocations, we don't allocate + * the space that was reserved for RAMHT/FC/RO. + */ + offset = dev_priv->ramfc_offset + dev_priv->ramfc_size; + ret = nouveau_mem_init_heap(&dev_priv->ramin_heap, + offset, dev_priv->ramin_rsvd_vram - offset); + if (ret) { + dev_priv->ramin_heap = NULL; + DRM_ERROR("Failed to init RAMIN heap\n"); + } + + return ret; +} + +void +nv04_instmem_takedown(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + + nouveau_gpuobj_del(dev, &dev_priv->ramht); +} + +int +nv04_instmem_populate(drm_device_t *dev, nouveau_gpuobj_t *gpuobj, uint32_t *sz) +{ + if (gpuobj->im_backing) + return DRM_ERR(EINVAL); + + return 0; +} + +void +nv04_instmem_clear(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + + if (gpuobj && gpuobj->im_backing) { + if (gpuobj->im_bound) + dev_priv->Engine.instmem.unbind(dev, gpuobj); + nouveau_mem_free(dev, gpuobj->im_backing); + gpuobj->im_backing = NULL; + } +} + +int +nv04_instmem_bind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +{ + if (!gpuobj->im_pramin || gpuobj->im_bound) + return DRM_ERR(EINVAL); + + gpuobj->im_bound = 1; + return 0; +} + +int +nv04_instmem_unbind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +{ + if (gpuobj->im_bound == 0) + return DRM_ERR(EINVAL); + + gpuobj->im_bound = 0; + return 0; +} + diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c index 07ec4635..2d8d5a0d 100644 --- a/shared-core/nv10_fifo.c +++ b/shared-core/nv10_fifo.c @@ -40,7 +40,7 @@ int nv10_fifo_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; int ret; if ((ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(channel), @@ -64,6 +64,8 @@ nv10_fifo_create_context(drm_device_t *dev, int channel) #endif 0); + /* enable the fifo dma operation */ + NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + + NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<ramfc) nouveau_gpuobj_ref_del(dev, &chan->ramfc); @@ -81,7 +85,7 @@ int nv10_fifo_load_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00000100 | channel); @@ -123,7 +127,7 @@ int nv10_fifo_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index d1fe0a54..c544afac 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -547,7 +547,7 @@ static int nv10_graph_ctx_regs_find_offset(drm_device_t *dev, int reg) static void restore_ctx_regs(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *fifo = &dev_priv->fifos[channel]; + struct nouveau_fifo *fifo = dev_priv->fifos[channel]; int i, j; for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) NV_WRITE(nv10_graph_ctx_regs[i], fifo->pgraph_ctx[i]); @@ -577,10 +577,10 @@ void nouveau_nv10_context_switch(drm_device_t *dev) // save PGRAPH context for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) - dev_priv->fifos[channel_old].pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); + dev_priv->fifos[channel_old]->pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); if (dev_priv->chipset>=0x17) { for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) - dev_priv->fifos[channel_old].pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); + dev_priv->fifos[channel_old]->pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); } nouveau_wait_for_idle(dev); @@ -613,7 +613,7 @@ void nouveau_nv10_context_switch(drm_device_t *dev) } while (0) int nv10_graph_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *fifo = &dev_priv->fifos[channel]; + struct nouveau_fifo *fifo = dev_priv->fifos[channel]; uint32_t tmp, vramsz; DRM_DEBUG("nv10_graph_context_create %d\n", channel); diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 13271051..06d7e440 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -32,7 +32,7 @@ int nv20_graph_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; unsigned int ctx_size = NV20_GRCTX_SIZE; int ret; @@ -51,7 +51,7 @@ int nv20_graph_create_context(drm_device_t *dev, int channel) { void nv20_graph_destroy_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; if (chan->ramin_grctx) nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); @@ -76,7 +76,7 @@ static void nv20_graph_rdi(drm_device_t *dev) { int nv20_graph_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t instance; instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel); @@ -97,7 +97,7 @@ int nv20_graph_save_context(drm_device_t *dev, int channel) { int nv20_graph_load_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t instance; instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel); diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index 65f4f868..a83ad714 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -104,7 +104,7 @@ int nv30_graph_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; void (*ctx_init)(drm_device_t *, nouveau_gpuobj_t *); unsigned int ctx_size; int ret; @@ -135,7 +135,7 @@ void nv30_graph_destroy_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; if (chan->ramin_grctx) nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); @@ -164,7 +164,7 @@ nouveau_graph_wait_idle(drm_device_t *dev) int nv30_graph_load_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t inst; if (!chan->ramin_grctx) @@ -181,7 +181,7 @@ int nv30_graph_load_context(drm_device_t *dev, int channel) int nv30_graph_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t inst; if (!chan->ramin_grctx) diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c index eed3e45b..818a9024 100644 --- a/shared-core/nv40_fifo.c +++ b/shared-core/nv40_fifo.c @@ -40,7 +40,7 @@ int nv40_fifo_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; int ret; if ((ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(channel), @@ -67,6 +67,8 @@ nv40_fifo_create_context(drm_device_t *dev, int channel) RAMFC_WR(GRCTX_INSTANCE, chan->ramin_grctx->instance >> 4); RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF); + /* enable the fifo dma operation */ + NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + + NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<ramfc) nouveau_gpuobj_ref_del(dev, &chan->ramfc); @@ -84,7 +88,7 @@ int nv40_fifo_load_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp, tmp2; NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET)); @@ -143,7 +147,7 @@ int nv40_fifo_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index 3f33cee6..94d76505 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -1228,7 +1228,7 @@ nv40_graph_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; void (*ctx_init)(drm_device_t *, nouveau_gpuobj_t *); unsigned int ctx_size; int ret; @@ -1287,7 +1287,7 @@ void nv40_graph_destroy_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; if (chan->ramin_grctx) nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); @@ -1330,7 +1330,7 @@ int nv40_graph_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t inst; if (!chan->ramin_grctx) @@ -1347,7 +1347,7 @@ int nv40_graph_load_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t inst; int ret; diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index e5d37949..d4c3ca87 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -28,55 +28,306 @@ #include "drm.h" #include "nouveau_drv.h" +typedef struct { + nouveau_gpuobj_ref_t *thingo; + nouveau_gpuobj_ref_t *dummyctx; +} nv50_fifo_priv; + +#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50) + +static void +nv50_fifo_init_thingo(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; + nouveau_gpuobj_ref_t *thingo = priv->thingo; + int i, fi=2; + + DRM_DEBUG("\n"); + + INSTANCE_WR(thingo->gpuobj, 0, 0x7e); + INSTANCE_WR(thingo->gpuobj, 1, 0x7e); + for (i = 0; i fifos[i]) { + INSTANCE_WR(thingo->gpuobj, fi, i); + fi++; + } + } + + NV_WRITE(0x32f4, thingo->instance >> 12); + NV_WRITE(0x32ec, fi); + NV_WRITE(0x2500, 0x101); +} + +static int +nv50_fifo_channel_enable(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + + DRM_DEBUG("ch%d\n", channel); + + if (IS_G80) { + if (!chan->ramin) + return DRM_ERR(EINVAL); + + NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), + (chan->ramin->instance >> 12) | + NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); + } else { + if (!chan->ramfc) + return DRM_ERR(EINVAL); + + NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), + (chan->ramfc->instance >> 8) | + NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); + } + + nv50_fifo_init_thingo(dev); + return 0; +} + +static void +nv50_fifo_channel_disable(drm_device_t *dev, int channel, int nt) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + + DRM_DEBUG("ch%d, nt=%d\n", channel, nt); + + if (IS_G80) { + NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), + NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80); + } else { + NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), + NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84); + } + + if (!nt) nv50_fifo_init_thingo(dev); +} + static void nv50_fifo_init_reset(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; uint32_t pmc_e; + DRM_DEBUG("\n"); + pmc_e = NV_READ(NV03_PMC_ENABLE); NV_WRITE(NV03_PMC_ENABLE, pmc_e & ~NV_PMC_ENABLE_PFIFO); pmc_e = NV_READ(NV03_PMC_ENABLE); NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PFIFO); } +static void +nv50_fifo_init_context_table(drm_device_t *dev) +{ + int i; + + DRM_DEBUG("\n"); + + for (i = 0; i < NV50_PFIFO_CTX_TABLE__SIZE; i++) + nv50_fifo_channel_disable(dev, i, 1); + nv50_fifo_init_thingo(dev); +} + +static void +nv50_fifo_init_regs__nv(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + + DRM_DEBUG("\n"); + + NV_WRITE(0x250c, 0x6f3cfc34); +} + +static int +nv50_fifo_init_regs(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; + int ret; + + DRM_DEBUG("\n"); + + if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, 0x1000, + 0x1000, + NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_ZERO_FREE, + &priv->dummyctx))) + return ret; + + NV_WRITE(0x2500, 0); + NV_WRITE(0x3250, 0); + NV_WRITE(0x3220, 0); + NV_WRITE(0x3204, 0); + NV_WRITE(0x3210, 0); + NV_WRITE(0x3270, 0); + + if (IS_G80) { + NV_WRITE(0x2600, (priv->dummyctx->instance>>8) | (1<<31)); + NV_WRITE(0x27fc, (priv->dummyctx->instance>>8) | (1<<31)); + } else { + NV_WRITE(0x2600, (priv->dummyctx->instance>>12) | (1<<31)); + NV_WRITE(0x27fc, (priv->dummyctx->instance>>12) | (1<<31)); + } + + return 0; +} + int nv50_fifo_init(drm_device_t *dev) { + drm_nouveau_private_t *dev_priv = dev->dev_private; + nv50_fifo_priv *priv; + int ret; + + DRM_DEBUG("\n"); + + priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER); + if (!priv) + return DRM_ERR(ENOMEM); + dev_priv->Engine.fifo.priv = priv; + nv50_fifo_init_reset(dev); - DRM_ERROR("stub!\n"); + if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, (128+2)*4, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC, + &priv->thingo))) { + DRM_ERROR("error creating thingo: %d\n", ret); + return ret; + } + nv50_fifo_init_context_table(dev); + + nv50_fifo_init_regs__nv(dev); + if ((ret = nv50_fifo_init_regs(dev))) + return ret; + return 0; } void nv50_fifo_takedown(drm_device_t *dev) { - DRM_ERROR("stub!\n"); + drm_nouveau_private_t *dev_priv = dev->dev_private; + nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; + + DRM_DEBUG("\n"); + + if (!priv) + return; + + nouveau_gpuobj_ref_del(dev, &priv->thingo); + nouveau_gpuobj_ref_del(dev, &priv->dummyctx); + + dev_priv->Engine.fifo.priv = NULL; + drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER); } int nv50_fifo_create_context(drm_device_t *dev, int channel) { - DRM_ERROR("stub!\n"); + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + nouveau_gpuobj_t *ramfc = NULL; + int ret; + + DRM_DEBUG("ch%d\n", channel); + + if (IS_G80) { + uint32_t ramfc_offset; + ramfc_offset = chan->ramin->gpuobj->im_pramin->start + 0x1000; + if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, 0x100, + NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_ZERO_FREE, + &ramfc, &chan->ramfc))) + return ret; + } else { + if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, 0x100, + 256, + NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_ZERO_FREE, + &chan->ramfc))) + return ret; + ramfc = chan->ramfc->gpuobj; + } + + INSTANCE_WR(ramfc, 0x48/4, chan->pushbuf->instance >> 4); + INSTANCE_WR(ramfc, 0x80/4, (0xc << 24) | (chan->ramht->instance >> 4)); + INSTANCE_WR(ramfc, 0x3c/4, 0x000f0078); /* fetch? */ + INSTANCE_WR(ramfc, 0x44/4, 0x2101ffff); + INSTANCE_WR(ramfc, 0x60/4, 0x7fffffff); + INSTANCE_WR(ramfc, 0x10/4, 0x00000000); + INSTANCE_WR(ramfc, 0x08/4, 0x00000000); + INSTANCE_WR(ramfc, 0x40/4, 0x00000000); + INSTANCE_WR(ramfc, 0x50/4, 0x2039b2e0); + INSTANCE_WR(ramfc, 0x54/4, 0x000f0000); + INSTANCE_WR(ramfc, 0x7c/4, 0x30000001); + INSTANCE_WR(ramfc, 0x78/4, 0x00000000); + INSTANCE_WR(ramfc, 0x4c/4, 0x00007fff); + + if (!IS_G80) { + INSTANCE_WR(chan->ramin->gpuobj, 0, channel); + INSTANCE_WR(chan->ramin->gpuobj, 1, chan->ramfc->instance); + + INSTANCE_WR(ramfc, 0x88/4, 0x3d520); /* some vram addy >> 10 */ + INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12); + } + + if ((ret = nv50_fifo_channel_enable(dev, channel))) { + DRM_ERROR("error enabling ch%d: %d\n", channel, ret); + nouveau_gpuobj_ref_del(dev, &chan->ramfc); + return ret; + } + return 0; } void nv50_fifo_destroy_context(drm_device_t *dev, int channel) { + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + + DRM_DEBUG("ch%d\n", channel); + + nv50_fifo_channel_disable(dev, channel, 0); + nouveau_gpuobj_ref_del(dev, &chan->ramfc); } int nv50_fifo_load_context(drm_device_t *dev, int channel) { - DRM_ERROR("stub!\n"); + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + nouveau_gpuobj_t *ramfc = chan->ramfc->gpuobj; + + DRM_DEBUG("ch%d\n", channel); + + /*XXX: incomplete, only touches the regs that NV does */ + + NV_WRITE(0x3244, 0); + NV_WRITE(0x3240, 0); + + NV_WRITE(0x3224, INSTANCE_RD(ramfc, 0x3c/4)); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, INSTANCE_RD(ramfc, 0x48/4)); + NV_WRITE(0x3234, INSTANCE_RD(ramfc, 0x4c/4)); + NV_WRITE(0x3254, 1); + NV_WRITE(NV03_PFIFO_RAMHT, INSTANCE_RD(ramfc, 0x80/4)); + + if (!IS_G80) { + NV_WRITE(0x340c, INSTANCE_RD(ramfc, 0x88/4)); + NV_WRITE(0x3410, INSTANCE_RD(ramfc, 0x98/4)); + } + + NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, channel | (1<<16)); return 0; } int nv50_fifo_save_context(drm_device_t *dev, int channel) { + DRM_DEBUG("ch%d\n", channel); DRM_ERROR("stub!\n"); return 0; } diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c index 8c3e2b9b..271ed733 100644 --- a/shared-core/nv50_graph.c +++ b/shared-core/nv50_graph.c @@ -28,57 +28,274 @@ #include "drm.h" #include "nouveau_drv.h" +#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50) + static void nv50_graph_init_reset(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; uint32_t pmc_e; + DRM_DEBUG("\n"); + pmc_e = NV_READ(NV03_PMC_ENABLE); NV_WRITE(NV03_PMC_ENABLE, pmc_e & ~NV_PMC_ENABLE_PGRAPH); pmc_e = NV_READ(NV03_PMC_ENABLE); NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PGRAPH); } +static void +nv50_graph_init_regs__nv(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + + DRM_DEBUG("\n"); + + NV_WRITE(0x400804, 0xc0000000); + NV_WRITE(0x406800, 0xc0000000); + NV_WRITE(0x400c04, 0xc0000000); + NV_WRITE(0x401804, 0xc0000000); + NV_WRITE(0x405018, 0xc0000000); + NV_WRITE(0x402000, 0xc0000000); + + NV_WRITE(0x400108, 0xffffffff); + NV_WRITE(0x400100, 0xffffffff); + + NV_WRITE(0x400824, 0x00004000); + NV_WRITE(0x400500, 0x00010001); +} + +static void +nv50_graph_init_regs(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + + DRM_DEBUG("\n"); + + NV_WRITE(NV04_PGRAPH_DEBUG_3, (1<<2) /* HW_CONTEXT_SWITCH_ENABLED */); +} + +static uint32_t nv84_ctx_voodoo[] = { + 0x0070008e, 0x0070009c, 0x00200020, 0x00600008, 0x0050004c, 0x00400e89, + 0x00200000, 0x00600007, 0x00300000, 0x00c000ff, 0x00200000, 0x008000ff, + 0x00700009, 0x0041634d, 0x00402944, 0x00402905, 0x0040290d, 0x00413e06, + 0x00600005, 0x004015c5, 0x00600011, 0x0040270b, 0x004021c5, 0x00700000, + 0x00700081, 0x00600004, 0x0050004a, 0x00216f40, 0x00600007, 0x00c02801, + 0x0020002e, 0x00800001, 0x005000cb, 0x0090ffff, 0x0091ffff, 0x00200020, + 0x00600008, 0x0050004c, 0x00600009, 0x00413e45, 0x0041594d, 0x0070009d, + 0x00402dcf, 0x0070009f, 0x0050009f, 0x00402ac0, 0x00200200, 0x00600008, + 0x00402a4f, 0x00402ac0, 0x004030cc, 0x00700081, 0x00200000, 0x00600006, + 0x00700000, 0x00111bfc, 0x00700083, 0x00300000, 0x00216f40, 0x00600007, + 0x00c00b01, 0x0020001e, 0x00800001, 0x005000cb, 0x00c000ff, 0x00700080, + 0x00700083, 0x00200047, 0x00600006, 0x0011020a, 0x00200480, 0x00600007, + 0x00300000, 0x00c000ff, 0x00c800ff, 0x00414907, 0x00202916, 0x008000ff, + 0x0040508c, 0x005000cb, 0x00a0023f, 0x00200040, 0x00600006, 0x0070000f, + 0x00170202, 0x0011020a, 0x00200032, 0x0010020d, 0x001c0242, 0x00120302, + 0x00140402, 0x00180500, 0x00130509, 0x00150550, 0x00110605, 0x0020000f, + 0x00100607, 0x00110700, 0x00110900, 0x00120902, 0x00110a00, 0x00160b02, + 0x00120b28, 0x00140b2b, 0x00110c01, 0x00111400, 0x00111405, 0x00111407, + 0x00111409, 0x0011140b, 0x002000cb, 0x00101500, 0x0040790f, 0x0040794b, + 0x00214d40, 0x00600007, 0x0020043e, 0x008800ff, 0x0070008f, 0x0040798c, + 0x005000cb, 0x00000000, 0x0020002b, 0x00101a05, 0x00131c00, 0x00121c04, + 0x00141c20, 0x00111c25, 0x00131c40, 0x00121c44, 0x00141c60, 0x00111c65, + 0x00131c80, 0x00121c84, 0x00141ca0, 0x00111ca5, 0x00131cc0, 0x00121cc4, + 0x00141ce0, 0x00111ce5, 0x00131f00, 0x00191f40, 0x0040a1e0, 0x002001ed, + 0x00600006, 0x00200044, 0x00102080, 0x001120c6, 0x001520c9, 0x001920d0, + 0x00122100, 0x00122103, 0x00162200, 0x00122207, 0x00112280, 0x00112300, + 0x00112302, 0x00122380, 0x0011238b, 0x00112394, 0x0011239c, 0x0040bee1, + 0x00200254, 0x00600006, 0x00200044, 0x00102480, 0x0040af0f, 0x0040af4b, + 0x00214d40, 0x00600007, 0x0020043e, 0x008800ff, 0x0070008f, 0x0040af8c, + 0x005000cb, 0x00000000, 0x001124c6, 0x001524c9, 0x001924d0, 0x00122500, + 0x00122503, 0x00162600, 0x00122607, 0x00112680, 0x00112700, 0x00112702, + 0x00122780, 0x0011278b, 0x00112794, 0x0011279c, 0x0040d1e2, 0x002002bb, + 0x00600006, 0x00200044, 0x00102880, 0x001128c6, 0x001528c9, 0x001928d0, + 0x00122900, 0x00122903, 0x00162a00, 0x00122a07, 0x00112a80, 0x00112b00, + 0x00112b02, 0x00122b80, 0x00112b8b, 0x00112b94, 0x00112b9c, 0x0040eee3, + 0x00200322, 0x00600006, 0x00200044, 0x00102c80, 0x0040df0f, 0x0040df4b, + 0x00214d40, 0x00600007, 0x0020043e, 0x008800ff, 0x0070008f, 0x0040df8c, + 0x005000cb, 0x00000000, 0x00112cc6, 0x00152cc9, 0x00192cd0, 0x00122d00, + 0x00122d03, 0x00162e00, 0x00122e07, 0x00112e80, 0x00112f00, 0x00112f02, + 0x00122f80, 0x00112f8b, 0x00112f94, 0x00112f9c, 0x004101e4, 0x00200389, + 0x00600006, 0x00200044, 0x00103080, 0x001130c6, 0x001530c9, 0x001930d0, + 0x00123100, 0x00123103, 0x00163200, 0x00123207, 0x00113280, 0x00113300, + 0x00113302, 0x00123380, 0x0011338b, 0x00113394, 0x0011339c, 0x00411ee5, + 0x002003f0, 0x00600006, 0x00200044, 0x00103480, 0x00410f0f, 0x00410f4b, + 0x00214d40, 0x00600007, 0x0020043e, 0x008800ff, 0x0070008f, 0x00410f8c, + 0x005000cb, 0x00000000, 0x001134c6, 0x001534c9, 0x001934d0, 0x00123500, + 0x00123503, 0x00163600, 0x00123607, 0x00113680, 0x00113700, 0x00113702, + 0x00123780, 0x0011378b, 0x00113794, 0x0011379c, 0x00000000, 0x0041250f, + 0x005000cb, 0x00214d40, 0x00600007, 0x0020043e, 0x008800ff, 0x005000cb, + 0x00412887, 0x0060000a, 0x00000000, 0x00413700, 0x007000a0, 0x00700080, + 0x00200480, 0x00600007, 0x00200004, 0x00c000ff, 0x008000ff, 0x005000cb, + 0x00700000, 0x00200000, 0x00600006, 0x00111bfe, 0x0041594d, 0x00700000, + 0x00200000, 0x00600006, 0x00111bfe, 0x00700080, 0x0070001d, 0x0040114d, + 0x00700081, 0x00600004, 0x0050004a, 0x00414388, 0x0060000b, 0x00200000, + 0x00600006, 0x00700000, 0x0041590b, 0x00111bfd, 0x0040424d, 0x00202916, + 0x008000fd, 0x005000cb, 0x00c00002, 0x00200480, 0x00600007, 0x00200160, + 0x00800002, 0x005000cb, 0x00c01802, 0x002027b6, 0x00800002, 0x005000cb, + 0x00404e4d, 0x0060000b, 0x0041574d, 0x00700001, 0x005000cf, 0x00700003, + 0x00415e06, 0x00415f05, 0x0060000d, 0x00700005, 0x0070000d, 0x00700006, + 0x0070000b, 0x0070000e, 0x0070001c, 0x0060000c, ~0 +}; + +static void +nv50_graph_init_ctxctl(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t *voodoo; + + DRM_DEBUG("\n"); + + switch (dev_priv->chipset) { + case 0x84: + voodoo = nv84_ctx_voodoo; + break; + default: + DRM_ERROR("no voodoo for chipset NV%02x\n", dev_priv->chipset); + break; + } + + if (voodoo) { + NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0); + while (*voodoo != ~0) { + NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, *voodoo); + voodoo++; + } + } + + NV_WRITE(0x400320, 4); + NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, 0); + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, 0); +} + int nv50_graph_init(drm_device_t *dev) { + DRM_DEBUG("\n"); + nv50_graph_init_reset(dev); + nv50_graph_init_regs__nv(dev); + nv50_graph_init_regs(dev); + nv50_graph_init_ctxctl(dev); - DRM_ERROR("stub!\n"); return 0; } void nv50_graph_takedown(drm_device_t *dev) { - DRM_ERROR("stub!\n"); + DRM_DEBUG("\n"); } int nv50_graph_create_context(drm_device_t *dev, int channel) { - DRM_ERROR("stub!\n"); + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + nouveau_gpuobj_t *ramin = chan->ramin->gpuobj; + int grctx_size = 0x60000, hdr; + int ret; + + DRM_DEBUG("ch%d\n", channel); + + if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, + grctx_size, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_ZERO_FREE, + &chan->ramin_grctx))) + return ret; + + hdr = IS_G80 ? 0x200 : 0x20; + INSTANCE_WR(ramin, (hdr + 0x00)/4, 0x00190002); + INSTANCE_WR(ramin, (hdr + 0x04)/4, chan->ramin_grctx->instance + + grctx_size - 1); + INSTANCE_WR(ramin, (hdr + 0x08)/4, chan->ramin_grctx->instance); + INSTANCE_WR(ramin, (hdr + 0x0c)/4, 0); + INSTANCE_WR(ramin, (hdr + 0x10)/4, 0); + INSTANCE_WR(ramin, (hdr + 0x14)/4, 0x00010000); + return 0; } void nv50_graph_destroy_context(drm_device_t *dev, int channel) { - DRM_ERROR("stub!\n"); + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + int i, hdr; + + DRM_DEBUG("ch%d\n", channel); + + hdr = IS_G80 ? 0x200 : 0x20; + for (i=hdr; iramin->gpuobj, i/4, 0); + + nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); +} + +static int +nv50_graph_transfer_context(drm_device_t *dev, uint32_t inst, int save) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t old_cp, tv = 20000; + int i; + + DRM_DEBUG("inst=0x%08x, save=%d\n", inst, save); + + old_cp = NV_READ(NV20_PGRAPH_CHANNEL_CTX_POINTER); + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst | (1<<31)); + NV_WRITE(0x400824, NV_READ(0x400824) | + (save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE : + NV40_PGRAPH_CTXCTL_0310_XFER_LOAD)); + NV_WRITE(NV40_PGRAPH_CTXCTL_0304, NV40_PGRAPH_CTXCTL_0304_XFER_CTX); + + for (i = 0; i < tv; i++) { + if (NV_READ(NV40_PGRAPH_CTXCTL_030C) == 0) + break; + } + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp); + + if (i == tv) { + DRM_ERROR("failed: inst=0x%08x save=%d\n", inst, save); + DRM_ERROR("0x40030C = 0x%08x\n", + NV_READ(NV40_PGRAPH_CTXCTL_030C)); + return DRM_ERR(EBUSY); + } + + return 0; } int nv50_graph_load_context(drm_device_t *dev, int channel) { - DRM_ERROR("stub!\n"); + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + uint32_t inst = ((chan->ramin->instance >> 12) | (1<<31)); + int ret; + + DRM_DEBUG("ch%d\n", channel); + +#if 0 + if ((ret = nv50_graph_transfer_context(dev, inst, 0))) + return ret; +#endif + + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); + NV_WRITE(0x400320, 4); + NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, inst); + return 0; } int nv50_graph_save_context(drm_device_t *dev, int channel) { - DRM_ERROR("stub!\n"); - return 0; + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + uint32_t inst = ((chan->ramin->instance >> 12) | (1<<31)); + + DRM_DEBUG("ch%d\n", channel); + + return nv50_graph_transfer_context(dev, inst, 1); } diff --git a/shared-core/nv50_instmem.c b/shared-core/nv50_instmem.c new file mode 100644 index 00000000..4aca9e7d --- /dev/null +++ b/shared-core/nv50_instmem.c @@ -0,0 +1,262 @@ +/* + * Copyright (C) 2007 Ben Skeggs. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "drmP.h" +#include "drm.h" +#include "nouveau_drv.h" + +typedef struct { + uint32_t save1700[5]; /* 0x1700->0x1710 */ +} nv50_instmem_priv; + +#define NV50_INSTMEM_PAGE_SHIFT 12 +#define NV50_INSTMEM_PAGE_SIZE (1 << NV50_INSTMEM_PAGE_SHIFT) +#define NV50_INSTMEM_RSVD_SIZE (64 * 1024) +#define NV50_INSTMEM_PT_SIZE(a) (((a) >> 12) << 3) + +int +nv50_instmem_init(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + nv50_instmem_priv *priv; + uint32_t rv, pt, pts, cb, cb0, cb1, unk, as; + uint32_t i, v; + int ret; + + priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER); + if (!priv) + return DRM_ERR(ENOMEM); + dev_priv->Engine.instmem.priv = priv; + + /* Save current state */ + for (i = 0x1700; i <= 0x1710; i+=4) + priv->save1700[(i-0x1700)/4] = NV_READ(i); + + as = dev_priv->ramin->size; + rv = nouveau_mem_fb_amount(dev) - (1*1024*1024); + pt = rv + 0xd0000; + pts = NV50_INSTMEM_PT_SIZE(as); + cb = rv + 0xc8000; + if ((dev_priv->chipset & 0xf0) != 0x50) { + unk = cb + 0x4200; + cb0 = cb + 0x4240; + cb1 = cb + 0x278; + } else { + unk = cb + 0x5400; + cb0 = cb + 0x5440; + cb1 = cb + 0x1438; + } + + DRM_DEBUG("PRAMIN config:\n"); + DRM_DEBUG(" Rsvd VRAM base: 0x%08x\n", rv); + DRM_DEBUG(" Aperture size: %i MiB\n", as >> 20); + DRM_DEBUG(" PT base: 0x%08x\n", pt); + DRM_DEBUG(" PT size: %d KiB\n", pts >> 10); + DRM_DEBUG(" BIOS image: 0x%08x\n", (NV_READ(0x619f04)&~0xff)<<8); + DRM_DEBUG(" Config base: 0x%08x\n", cb); + DRM_DEBUG(" ctxdma Config0: 0x%08x\n", cb0); + DRM_DEBUG(" Config1: 0x%08x\n", cb1); + + /* Map first MiB of reserved vram into BAR0 PRAMIN aperture */ + NV_WRITE(0x1700, (rv>>16)); + /* Poke some regs.. */ + NV_WRITE(0x1704, (cb>>12)); + NV_WRITE(0x1710, (((unk-cb)>>4))|(1<<31)); + NV_WRITE(0x1704, (cb>>12)|(1<<30)); + + /* CB0, some DMA object, NFI what it points at... Needed however, + * or the PRAMIN aperture doesn't operate as expected. + */ + NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x00, 0x7fc00000); + NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x04, 0xe1ffffff); + NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x08, 0xe0000000); + NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x0c, 0x01000001); + NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x10, 0x00000000); + NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x14, 0x00000000); + + /* CB1, points at PRAMIN PT */ + NV_WRITE(NV_RAMIN + (cb1 - rv) + 0, pt | 0x63); + NV_WRITE(NV_RAMIN + (cb1 - rv) + 4, 0x00000000); + + /* Zero PRAMIN page table */ + v = NV_RAMIN + (pt - rv); + for (i = v; i < v + pts; i += 8) { + NV_WRITE(i + 0x00, 0x00000009); + NV_WRITE(i + 0x04, 0x00000000); + } + + /* Map page table into PRAMIN aperture */ + for (i = pt; i < pt + pts; i += 0x1000) { + uint32_t pte = NV_RAMIN + (pt-rv) + (((i-pt) >> 12) << 3); + DRM_DEBUG("PRAMIN PTE = 0x%08x @ 0x%08x\n", i, pte); + NV_WRITE(pte + 0x00, i | 1); + NV_WRITE(pte + 0x04, 0x00000000); + } + + /* Points at CB0 */ + NV_WRITE(0x170c, (((cb0 - cb)>>4)|(1<<31))); + + /* Confirm it all worked, should be able to read back the page table's + * PTEs from the PRAMIN BAR + */ + NV_WRITE(0x1700, pt >> 16); + if (NV_READ(0x700000) != NV_RI32(0)) { + DRM_ERROR("Failed to init PRAMIN page table\n"); + return DRM_ERR(EINVAL); + } + + /* Create a heap to manage PRAMIN aperture allocations */ + ret = nouveau_mem_init_heap(&dev_priv->ramin_heap, pts, as-pts); + if (ret) { + DRM_ERROR("Failed to init PRAMIN heap\n"); + return DRM_ERR(ENOMEM); + } + DRM_DEBUG("NV50: PRAMIN setup ok\n"); + + /* Don't alloc the last MiB of VRAM, probably too much, but be safe + * at least for now. + */ + dev_priv->ramin_rsvd_vram = 1*1024*1024; + + /*XXX: probably incorrect, but needed to make hash func "work" */ + dev_priv->ramht_offset = 0x10000; + dev_priv->ramht_bits = 9; + dev_priv->ramht_size = (1 << dev_priv->ramht_bits); + return 0; +} + +void +nv50_instmem_takedown(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv; + int i; + + if (!priv) + return; + + /* Restore state from before init */ + for (i = 0x1700; i <= 0x1710; i+=4) + NV_WRITE(i, priv->save1700[(i-0x1700)/4]); + + dev_priv->Engine.instmem.priv = NULL; + drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER); +} + +int +nv50_instmem_populate(drm_device_t *dev, nouveau_gpuobj_t *gpuobj, uint32_t *sz) +{ + if (gpuobj->im_backing) + return DRM_ERR(EINVAL); + + *sz = (*sz + (NV50_INSTMEM_PAGE_SIZE-1)) & ~(NV50_INSTMEM_PAGE_SIZE-1); + if (*sz == 0) + return DRM_ERR(EINVAL); + + gpuobj->im_backing = nouveau_mem_alloc(dev, NV50_INSTMEM_PAGE_SIZE, + *sz, NOUVEAU_MEM_FB, + (DRMFILE)-2); + if (!gpuobj->im_backing) { + DRM_ERROR("Couldn't allocate vram to back PRAMIN pages\n"); + return DRM_ERR(ENOMEM); + } + + return 0; +} + +void +nv50_instmem_clear(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + + if (gpuobj && gpuobj->im_backing) { + if (gpuobj->im_bound) + dev_priv->Engine.instmem.unbind(dev, gpuobj); + nouveau_mem_free(dev, gpuobj->im_backing); + gpuobj->im_backing = NULL; + } +} + +int +nv50_instmem_bind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t pte, pte_end, vram; + + if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound) + return DRM_ERR(EINVAL); + + DRM_DEBUG("st=0x%0llx sz=0x%0llx\n", + gpuobj->im_pramin->start, gpuobj->im_pramin->size); + + pte = (gpuobj->im_pramin->start >> 12) << 3; + pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte; + vram = gpuobj->im_backing->start - dev_priv->fb_phys; + + if (pte == pte_end) { + DRM_ERROR("WARNING: badness in bind() pte calc\n"); + pte_end++; + } + + DRM_DEBUG("pramin=0x%llx, pte=%d, pte_end=%d\n", + gpuobj->im_pramin->start, pte, pte_end); + DRM_DEBUG("first vram page: 0x%llx\n", + gpuobj->im_backing->start); + + while (pte < pte_end) { + NV_WI32(pte + 0, vram | 1); + NV_WI32(pte + 4, 0x00000000); + + pte += 8; + vram += NV50_INSTMEM_PAGE_SIZE; + } + + gpuobj->im_bound = 1; + return 0; +} + +int +nv50_instmem_unbind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t pte, pte_end; + + if (gpuobj->im_bound == 0) + return DRM_ERR(EINVAL); + + pte = (gpuobj->im_pramin->start >> 12) << 3; + pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte; + while (pte < pte_end) { + NV_WI32(pte + 0, 0x00000000); + NV_WI32(pte + 4, 0x00000000); + pte += 8; + } + + gpuobj->im_bound = 0; + return 0; +} + -- cgit v1.2.3 From 3c58195ccd346cc61f98b9f89cf074edf6886723 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 9 Jul 2007 15:37:37 +1000 Subject: nouveau: Avoid oops Turns out lastclose() gets called even if firstopen() has never been... --- shared-core/nouveau_drv.h | 6 ++++++ shared-core/nouveau_state.c | 23 +++++++++++++++-------- 2 files changed, 21 insertions(+), 8 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 81972db5..12b78a7e 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -184,6 +184,12 @@ typedef struct nouveau_engine_func { } nouveau_engine_func_t; typedef struct drm_nouveau_private { + enum { + NOUVEAU_CARD_INIT_DOWN, + NOUVEAU_CARD_INIT_DONE, + NOUVEAU_CARD_INIT_FAILED + } init_state; + /* the card type, takes NV_* as values */ int card_type; /* exact chipset, derived from NV_PMC_BOOT_0 */ diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index bcb974bf..c51d7d5d 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -280,6 +280,7 @@ static int nouveau_card_init(drm_device_t *dev) ret = nouveau_init_engine_ptrs(dev); if (ret) return ret; engine = &dev_priv->Engine; + dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED; /* Initialise instance memory, must happen before mem_init so we * know exactly how much VRAM we're able to use for "normal" @@ -316,6 +317,7 @@ static int nouveau_card_init(drm_device_t *dev) /* what about PVIDEO/PCRTC/PRAMDAC etc? */ + dev_priv->init_state = NOUVEAU_CARD_INIT_DONE; return 0; } @@ -324,14 +326,18 @@ static void nouveau_card_takedown(drm_device_t *dev) drm_nouveau_private_t *dev_priv = dev->dev_private; nouveau_engine_func_t *engine = &dev_priv->Engine; - engine->fifo.takedown(dev); - engine->graph.takedown(dev); - engine->fb.takedown(dev); - engine->timer.takedown(dev); - engine->mc.takedown(dev); - nouveau_gpuobj_takedown(dev); - nouveau_mem_close(dev); - engine->instmem.takedown(dev); + if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) { + engine->fifo.takedown(dev); + engine->graph.takedown(dev); + engine->fb.takedown(dev); + engine->timer.takedown(dev); + engine->mc.takedown(dev); + nouveau_gpuobj_takedown(dev); + nouveau_mem_close(dev); + engine->instmem.takedown(dev); + + dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN; + } } /* here a client dies, release the stuff that was allocated for its filp */ @@ -371,6 +377,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) dev_priv->card_type=flags&NOUVEAU_FAMILY; dev_priv->flags=flags&NOUVEAU_FLAGS; + dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN; dev->dev_private = (void *)dev_priv; -- cgit v1.2.3 From 31e33813e8c1b085683e68524e680882368e59a9 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 9 Jul 2007 20:02:14 +1000 Subject: nouveau: Don't be so strict on dev_private; nouveau_gpuobj_t *cpramin; - if ((channel > 0) && gpuobj->im_channel != channel) { - DRM_ERROR("Channel mismatch: obj %d, ref %d\n", - gpuobj->im_channel, channel); - return DRM_ERR(EINVAL); - } - /* card_type < NV_50) { *inst = gpuobj->im_pramin->start; return 0; } + if ((channel > 0) && gpuobj->im_channel != channel) { + DRM_ERROR("Channel mismatch: obj %d, ref %d\n", + gpuobj->im_channel, channel); + return DRM_ERR(EINVAL); + } + /* NV50 channel-local instance */ if (channel > 0) { cpramin = dev_priv->fifos[channel]->ramin->gpuobj; -- cgit v1.2.3 From 023f7d9c0064f912415c92a85c3a9d722191909f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 9 Jul 2007 23:58:00 +1000 Subject: nouveau: Allocate mappable VRAM for notifiers.. --- shared-core/nouveau_fifo.c | 4 ---- shared-core/nouveau_notifier.c | 1 + 2 files changed, 1 insertion(+), 4 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index c140a634..4095a57f 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -497,10 +497,6 @@ static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) /* and the notifier block */ init.notifier = chan->notifier_block->start; init.notifier_size = chan->notifier_block->size; - res = drm_addmap(dev, init.notifier, init.notifier_size, _DRM_REGISTERS, - 0, &chan->notifier_map); - if (res != 0) - return res; DRM_COPY_TO_USER_IOCTL((drm_nouveau_fifo_alloc_t __user *)data, init, sizeof(init)); diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index 9e792e57..30216293 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -41,6 +41,7 @@ nouveau_notifier_init_channel(drm_device_t *dev, int channel, DRMFILE filp) flags = NOUVEAU_MEM_AGP | NOUVEAU_MEM_FB_ACCEPTABLE; else flags = NOUVEAU_MEM_FB; + flags |= NOUVEAU_MEM_MAPPED; chan->notifier_block = nouveau_mem_alloc(dev, 0, PAGE_SIZE, flags,filp); if (!chan->notifier_block) -- cgit v1.2.3 From 1f4e24b429789710f5d69fc78335f20c023569bb Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Mon, 9 Jul 2007 16:33:14 -0700 Subject: Move types shared with user mode to xgi_drm.h. --- shared-core/Makefile.am | 3 +- shared-core/xgi_drm.h | 176 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 178 insertions(+), 1 deletion(-) create mode 100644 shared-core/xgi_drm.h (limited to 'shared-core') diff --git a/shared-core/Makefile.am b/shared-core/Makefile.am index f0ebf2a3..7193e527 100644 --- a/shared-core/Makefile.am +++ b/shared-core/Makefile.am @@ -36,4 +36,5 @@ klibdrminclude_HEADERS = \ sis_drm.h \ via_drm.h \ r300_reg.h \ - via_3d_reg.h + via_3d_reg.h \ + xgi_drm.h diff --git a/shared-core/xgi_drm.h b/shared-core/xgi_drm.h new file mode 100644 index 00000000..3a5dbc65 --- /dev/null +++ b/shared-core/xgi_drm.h @@ -0,0 +1,176 @@ +/**************************************************************************** + * Copyright (C) 2003-2006 by XGI Technology, Taiwan. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR + * ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + ***************************************************************************/ + +#ifndef _XGI_DRM_H_ +#define _XGI_DRM_H_ + +#include +#include + +struct xgi_chip_info { + __u16 device_id; + __u16 vendor_id; + + char device_name[32]; + unsigned int curr_display_mode; //Singe, DualView(Contained), MHS + unsigned int fb_size; + unsigned long sarea_bus_addr; + unsigned int sarea_size; +}; + +enum xgi_mem_location { + XGI_MEMLOC_NON_LOCAL = 0, + XGI_MEMLOC_LOCAL = 1, + XGI_MEMLOC_INVALID = 0x7fffffff +}; + +struct xgi_mem_alloc { + unsigned int location; + unsigned int size; + unsigned int is_front; + unsigned int owner; + + /** + * Address of the memory from the graphics hardware's point of view. + */ + __u32 hw_addr; + + /** + * Physical address of the memory from the processor's point of view. + */ + unsigned long bus_addr; +}; + +struct xgi_screen_info { + unsigned int scrn_start; + unsigned int scrn_xres; + unsigned int scrn_yres; + unsigned int scrn_bpp; + unsigned int scrn_pitch; +}; + +struct xgi_sarea_info { + unsigned long bus_addr; + unsigned int size; +}; + +enum xgi_batch_type { + BTYPE_2D = 0, + BTYPE_3D = 1, + BTYPE_FLIP = 2, + BTYPE_CTRL = 3, + BTYPE_NONE = 0x7fffffff +}; + +struct xgi_cmd_info { + unsigned int _firstBeginType; + __u32 _firstBeginAddr; + __u32 _firstSize; + __u32 _curDebugID; + __u32 _lastBeginAddr; + unsigned int _beginCount; + +}; + +struct xgi_state_info { + unsigned int _fromState; + unsigned int _toState; +}; + +struct xgi_mmio_info { + unsigned long mmio_base; + unsigned int size; +}; + + +/* + * Ioctl definitions + */ + +#define XGI_IOCTL_MAGIC 'x' /* use 'x' as magic number */ + +#define XGI_IOCTL_BASE 0 +#define XGI_ESC_DEVICE_INFO (XGI_IOCTL_BASE + 0) +#define XGI_ESC_POST_VBIOS (XGI_IOCTL_BASE + 1) + +#define XGI_ESC_FB_INIT (XGI_IOCTL_BASE + 2) +#define XGI_ESC_FB_ALLOC (XGI_IOCTL_BASE + 3) +#define XGI_ESC_FB_FREE (XGI_IOCTL_BASE + 4) +#define XGI_ESC_PCIE_INIT (XGI_IOCTL_BASE + 5) +#define XGI_ESC_PCIE_ALLOC (XGI_IOCTL_BASE + 6) +#define XGI_ESC_PCIE_FREE (XGI_IOCTL_BASE + 7) +#define XGI_ESC_SUBMIT_CMDLIST (XGI_IOCTL_BASE + 8) +#define XGI_ESC_PUT_SCREEN_INFO (XGI_IOCTL_BASE + 9) +#define XGI_ESC_GET_SCREEN_INFO (XGI_IOCTL_BASE + 10) +#define XGI_ESC_GE_RESET (XGI_IOCTL_BASE + 11) +#define XGI_ESC_SAREA_INFO (XGI_IOCTL_BASE + 12) +#define XGI_ESC_DUMP_REGISTER (XGI_IOCTL_BASE + 13) +#define XGI_ESC_DEBUG_INFO (XGI_IOCTL_BASE + 14) +#define XGI_ESC_TEST_RWINKERNEL (XGI_IOCTL_BASE + 16) +#define XGI_ESC_STATE_CHANGE (XGI_IOCTL_BASE + 17) +#define XGI_ESC_MMIO_INFO (XGI_IOCTL_BASE + 18) +#define XGI_ESC_PCIE_CHECK (XGI_IOCTL_BASE + 19) +#define XGI_ESC_MEM_COLLECT (XGI_IOCTL_BASE + 20) + +#define XGI_IOCTL_DEVICE_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_DEVICE_INFO, struct xgi_chip_info) +#define XGI_IOCTL_POST_VBIOS _IO(XGI_IOCTL_MAGIC, XGI_ESC_POST_VBIOS) + +#define XGI_IOCTL_FB_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_FB_INIT) +#define XGI_IOCTL_FB_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_FB_ALLOC, struct xgi_mem_req) +#define XGI_IOCTL_FB_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_FB_FREE, unsigned long) + +#define XGI_IOCTL_PCIE_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_INIT) +#define XGI_IOCTL_PCIE_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_ALLOC, struct xgi_mem_req) +#define XGI_IOCTL_PCIE_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_FREE, unsigned long) + +#define XGI_IOCTL_PUT_SCREEN_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PUT_SCREEN_INFO, struct xgi_screen_info) +#define XGI_IOCTL_GET_SCREEN_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_GET_SCREEN_INFO, struct xgi_screen_info) + +#define XGI_IOCTL_GE_RESET _IO(XGI_IOCTL_MAGIC, XGI_ESC_GE_RESET) +#define XGI_IOCTL_SAREA_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_SAREA_INFO, struct xgi_sarea_info) +#define XGI_IOCTL_DUMP_REGISTER _IO(XGI_IOCTL_MAGIC, XGI_ESC_DUMP_REGISTER) +#define XGI_IOCTL_DEBUG_INFO _IO(XGI_IOCTL_MAGIC, XGI_ESC_DEBUG_INFO) +#define XGI_IOCTL_MMIO_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_MMIO_INFO, struct xgi_mmio_info) + +#define XGI_IOCTL_SUBMIT_CMDLIST _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_SUBMIT_CMDLIST, struct xgi_cmd_info) +#define XGI_IOCTL_TEST_RWINKERNEL _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_TEST_RWINKERNEL, unsigned long) +#define XGI_IOCTL_STATE_CHANGE _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_STATE_CHANGE, struct xgi_state_info) + +#define XGI_IOCTL_PCIE_CHECK _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_CHECK) +#define XGI_IOCTL_MAXNR 30 + +/* + * flags + */ +#define XGI_FLAG_OPEN 0x0001 +#define XGI_FLAG_NEEDS_POSTING 0x0002 +#define XGI_FLAG_WAS_POSTED 0x0004 +#define XGI_FLAG_CONTROL 0x0010 +#define XGI_FLAG_MAP_REGS_EARLY 0x0200 + + +#endif /* _XGI_DRM_H_ */ -- cgit v1.2.3 From a9c49be6f8a0aa199a9dc0ffd0a9aa2b85cd796d Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Mon, 9 Jul 2007 18:52:43 -0700 Subject: Fix ioctl types. I had moved code from xgi_drv.h to xgi_drm.h before changing the ioctl types for XGI_IOCTL_(FB|PCIE)_ALLOC. --- shared-core/xgi_drm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/xgi_drm.h b/shared-core/xgi_drm.h index 3a5dbc65..0abf390a 100644 --- a/shared-core/xgi_drm.h +++ b/shared-core/xgi_drm.h @@ -140,11 +140,11 @@ struct xgi_mmio_info { #define XGI_IOCTL_POST_VBIOS _IO(XGI_IOCTL_MAGIC, XGI_ESC_POST_VBIOS) #define XGI_IOCTL_FB_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_FB_INIT) -#define XGI_IOCTL_FB_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_FB_ALLOC, struct xgi_mem_req) +#define XGI_IOCTL_FB_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_FB_ALLOC, struct xgi_mem_alloc) #define XGI_IOCTL_FB_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_FB_FREE, unsigned long) #define XGI_IOCTL_PCIE_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_INIT) -#define XGI_IOCTL_PCIE_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_ALLOC, struct xgi_mem_req) +#define XGI_IOCTL_PCIE_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_ALLOC, struct xgi_mem_alloc) #define XGI_IOCTL_PCIE_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_FREE, unsigned long) #define XGI_IOCTL_PUT_SCREEN_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PUT_SCREEN_INFO, struct xgi_screen_info) -- cgit v1.2.3 From 694e1c5c3f768436651ddf95e11ab5a89ccc8ffa Mon Sep 17 00:00:00 2001 From: Arthur Huillet Date: Wed, 11 Jul 2007 02:35:10 +0200 Subject: Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel. --- shared-core/nouveau_drm.h | 16 +++-- shared-core/nouveau_drv.h | 3 +- shared-core/nouveau_fifo.c | 18 +++-- shared-core/nouveau_mem.c | 89 +++++++++++++++++------- shared-core/nouveau_object.c | 161 ++++++++++++++++++++++++++++++------------- shared-core/nouveau_reg.h | 2 + shared-core/nouveau_state.c | 12 ++++ 7 files changed, 215 insertions(+), 86 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h index 0758991a..7abe82e0 100644 --- a/shared-core/nouveau_drm.h +++ b/shared-core/nouveau_drm.h @@ -25,7 +25,7 @@ #ifndef __NOUVEAU_DRM_H__ #define __NOUVEAU_DRM_H__ -#define NOUVEAU_DRM_HEADER_PATCHLEVEL 7 +#define NOUVEAU_DRM_HEADER_PATCHLEVEL 8 typedef struct drm_nouveau_fifo_alloc { uint32_t fb_ctxdma_handle; @@ -68,11 +68,14 @@ drm_nouveau_notifier_alloc_t; #define NOUVEAU_MEM_AGP 0x00000002 #define NOUVEAU_MEM_FB_ACCEPTABLE 0x00000004 #define NOUVEAU_MEM_AGP_ACCEPTABLE 0x00000008 -#define NOUVEAU_MEM_PINNED 0x00000010 -#define NOUVEAU_MEM_USER_BACKED 0x00000020 -#define NOUVEAU_MEM_MAPPED 0x00000040 -#define NOUVEAU_MEM_INSTANCE 0x00000080 /* internal */ -#define NOUVEAU_MEM_NOTIFIER 0x00000100 /* internal */ +#define NOUVEAU_MEM_PCI 0x00000010 +#define NOUVEAU_MEM_PCI_ACCEPTABLE 0x00000020 +#define NOUVEAU_MEM_PINNED 0x00000040 +#define NOUVEAU_MEM_USER_BACKED 0x00000080 +#define NOUVEAU_MEM_MAPPED 0x00000100 +#define NOUVEAU_MEM_INSTANCE 0x00000200 /* internal */ +#define NOUVEAU_MEM_NOTIFIER 0x00000400 /* internal */ + typedef struct drm_nouveau_mem_alloc { int flags; int alignment; @@ -95,6 +98,7 @@ drm_nouveau_mem_free_t; #define NOUVEAU_GETPARAM_AGP_PHYSICAL 7 #define NOUVEAU_GETPARAM_FB_SIZE 8 #define NOUVEAU_GETPARAM_AGP_SIZE 9 +#define NOUVEAU_GETPARAM_PCI_PHYSICAL 10 typedef struct drm_nouveau_getparam { uint64_t param; uint64_t value; diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 12b78a7e..ea03fe37 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -34,7 +34,7 @@ #define DRIVER_MAJOR 0 #define DRIVER_MINOR 0 -#define DRIVER_PATCHLEVEL 7 +#define DRIVER_PATCHLEVEL 8 #define NOUVEAU_FAMILY 0x0000FFFF #define NOUVEAU_FLAGS 0xFFFF0000 @@ -229,6 +229,7 @@ typedef struct drm_nouveau_private { struct mem_block *fb_heap; struct mem_block *fb_nomap_heap; struct mem_block *ramin_heap; + struct mem_block *pci_heap; /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */ uint32_t ctx_table_size; diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 4095a57f..bc3a9948 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -210,11 +210,19 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) } if (cb->flags & NOUVEAU_MEM_AGP) { - ret = nouveau_gpuobj_dma_new - (dev, channel, NV_CLASS_DMA_IN_MEMORY, - cb->start - dev_priv->agp_phys, - cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP, - &pushbuf); + DRM_DEBUG("Creating CB in AGP memory\n"); + ret = nouveau_gpuobj_dma_new(dev, channel, + NV_CLASS_DMA_IN_MEMORY, + cb->start - dev_priv->agp_phys, + cb->size, + NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP, &pushbuf); + } else if ( cb->flags & NOUVEAU_MEM_PCI) { + DRM_DEBUG("Creating CB in PCI memory starting at virt 0x%08llx size %d\n", cb->start, cb->size); + ret = nouveau_gpuobj_dma_new(dev, channel, + NV_CLASS_DMA_IN_MEMORY, + cb->start, + cb->size, + NV_DMA_ACCESS_RO, NV_DMA_TARGET_PCI_NONLINEAR, &pushbuf); } else if (dev_priv->card_type != NV_04) { ret = nouveau_gpuobj_dma_new (dev, channel, NV_CLASS_DMA_IN_MEMORY, diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index c75a9356..79f94fd4 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -211,6 +211,10 @@ void nouveau_mem_close(struct drm_device *dev) drm_nouveau_private_t *dev_priv = dev->dev_private; nouveau_mem_takedown(&dev_priv->agp_heap); nouveau_mem_takedown(&dev_priv->fb_heap); + if ( dev_priv->pci_heap ) + { + nouveau_mem_takedown(&dev_priv->pci_heap); + } } /* returns the amount of FB ram in bytes */ @@ -283,8 +287,10 @@ int nouveau_mem_init(struct drm_device *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; uint32_t fb_size; + drm_scatter_gather_t sgreq; dev_priv->agp_phys=0; dev_priv->fb_phys=0; + sgreq . size = 4 << 20; //4MB of PCI scatter-gather zone /* init AGP */ dev_priv->agp_heap=NULL; @@ -340,8 +346,26 @@ int nouveau_mem_init(struct drm_device *dev) dev_priv->agp_phys = info.aperture_base; dev_priv->agp_available_size = info.aperture_size; } + +goto have_agp; no_agp: + dev_priv->pci_heap = NULL; + DRM_DEBUG("Allocating sg memory for PCI DMA\n"); + if ( drm_sg_alloc(dev, &sgreq) ) + { + DRM_ERROR("Unable to allocate 4MB of scatter-gather pages for PCI DMA!"); + goto no_pci; + } + DRM_DEBUG("Got %d KiB\n", (dev->sg->pages * PAGE_SIZE) >> 10); + if ( nouveau_mem_init_heap(&dev_priv->pci_heap, dev->sg->virtual, dev->sg->pages * PAGE_SIZE)) + { + DRM_ERROR("Unable to initialize pci_heap!"); + goto no_pci; + } + +no_pci: +have_agp: /* setup a mtrr over the FB */ dev_priv->fb_mtrr = drm_mtrr_add(drm_get_resource_start(dev, 1), nouveau_mem_fb_amount(dev), @@ -405,29 +429,40 @@ struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment, uint6 if (size & (~PAGE_MASK)) size = ((size/PAGE_SIZE) + 1) * PAGE_SIZE; - if (flags&NOUVEAU_MEM_AGP) { - type=NOUVEAU_MEM_AGP; - block = nouveau_mem_alloc_block(dev_priv->agp_heap, size, - alignment, filp); - if (block) goto alloc_ok; - } - if (flags&(NOUVEAU_MEM_FB|NOUVEAU_MEM_FB_ACCEPTABLE)) { - type=NOUVEAU_MEM_FB; - if (!(flags&NOUVEAU_MEM_MAPPED)) { - block = nouveau_mem_alloc_block(dev_priv->fb_nomap_heap, - size, alignment, filp); - if (block) goto alloc_ok; - } - block = nouveau_mem_alloc_block(dev_priv->fb_heap, size, - alignment, filp); - if (block) goto alloc_ok; - } - if (flags&NOUVEAU_MEM_AGP_ACCEPTABLE) { - type=NOUVEAU_MEM_AGP; - block = nouveau_mem_alloc_block(dev_priv->agp_heap, size, - alignment, filp); - if (block) goto alloc_ok; - } + +#define NOUVEAU_MEM_ALLOC_AGP {\ + type=NOUVEAU_MEM_AGP;\ + block = nouveau_mem_alloc_block(dev_priv->agp_heap, size,\ + alignment, filp);\ + if (block) goto alloc_ok;\ + } + +#define NOUVEAU_MEM_ALLOC_PCI {\ + type = NOUVEAU_MEM_PCI;\ + block = nouveau_mem_alloc_block(dev_priv->pci_heap, size, alignment, filp);\ + if ( block ) goto alloc_ok;\ + } + +#define NOUVEAU_MEM_ALLOC_FB {\ + type=NOUVEAU_MEM_FB;\ + if (!(flags&NOUVEAU_MEM_MAPPED)) {\ + block = nouveau_mem_alloc_block(dev_priv->fb_nomap_heap,\ + size, alignment, filp); \ + if (block) goto alloc_ok;\ + }\ + block = nouveau_mem_alloc_block(dev_priv->fb_heap, size,\ + alignment, filp);\ + if (block) goto alloc_ok;\ + } + + + if (flags&NOUVEAU_MEM_FB) NOUVEAU_MEM_ALLOC_FB + if (flags&NOUVEAU_MEM_AGP) NOUVEAU_MEM_ALLOC_AGP + if (flags&NOUVEAU_MEM_PCI) NOUVEAU_MEM_ALLOC_PCI + if (flags&NOUVEAU_MEM_FB_ACCEPTABLE) NOUVEAU_MEM_ALLOC_FB + if (flags&NOUVEAU_MEM_AGP_ACCEPTABLE) NOUVEAU_MEM_ALLOC_AGP + if (flags&NOUVEAU_MEM_PCI_ACCEPTABLE) NOUVEAU_MEM_ALLOC_PCI + return NULL; @@ -436,15 +471,19 @@ alloc_ok: if (flags&NOUVEAU_MEM_MAPPED) { - int ret; + int ret = 0; block->flags|=NOUVEAU_MEM_MAPPED; if (type == NOUVEAU_MEM_AGP) ret = drm_addmap(dev, block->start - dev->agp->base, block->size, _DRM_AGP, 0, &block->map); - else + else if (type == NOUVEAU_MEM_FB) ret = drm_addmap(dev, block->start, block->size, _DRM_FRAME_BUFFER, 0, &block->map); + else if (type == NOUVEAU_MEM_PCI) + ret = drm_addmap(dev, block->start - (unsigned long int)dev->sg->virtual, block->size, + _DRM_SCATTER_GATHER, 0, &block->map); + if (ret) { nouveau_mem_free_block(block); return NULL; diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index bf811b4b..dcb29b40 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -515,6 +515,20 @@ nouveau_gpuobj_new_fake(drm_device_t *dev, uint32_t offset, uint32_t size, return 0; } + +static int +nouveau_gpuobj_class_instmem_size(drm_device_t *dev, int class) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + + /*XXX: dodgy hack for now */ + if (dev_priv->card_type >= NV_50) + return 24; + if (dev_priv->card_type >= NV_40) + return 32; + return 16; +} + /* DMA objects are used to reference a piece of memory in the framebuffer, PCI or AGP address space. Each object is 16 bytes big @@ -528,31 +542,20 @@ nouveau_gpuobj_new_fake(drm_device_t *dev, uint32_t offset, uint32_t size, 17:16 target: 0 NV memory, 1 NV memory tiled, 2 PCI, 3 AGP 31:20 dma adjust (bits 0-11 of the address) entry[1] - dma limit - entry[2] + dma limit (size of transfer) + entry[X] 1 0 readonly, 1 readwrite - 31:12 dma frame address (bits 12-31 of the address) + 31:12 dma frame address of the page (bits 12-31 of the address) + entry[N] + page table terminator, same value as the first pte, as does nvidia + rivatv uses 0xffffffff - Non linear page tables seem to need a list of frame addresses afterwards, - the rivatv project has some info on this. + Non linear page tables need a list of frame addresses afterwards, + the rivatv project has some info on this. The method below creates a DMA object in instance RAM and returns a handle to it that can be used to set up context objects. */ - -static int -nouveau_gpuobj_class_instmem_size(drm_device_t *dev, int class) -{ - drm_nouveau_private_t *dev_priv = dev->dev_private; - - /*XXX: dodgy hack for now */ - if (dev_priv->card_type >= NV_50) - return 24; - if (dev_priv->card_type >= NV_40) - return 32; - return 16; -} - int nouveau_gpuobj_dma_new(drm_device_t *dev, int channel, int class, uint64_t offset, uint64_t size, int access, int target, @@ -560,13 +563,28 @@ nouveau_gpuobj_dma_new(drm_device_t *dev, int channel, int class, { drm_nouveau_private_t *dev_priv = dev->dev_private; int ret; - + uint32_t is_scatter_gather = 0; + DRM_DEBUG("ch%d class=0x%04x offset=0x%llx size=0x%llx\n", channel, class, offset, size); DRM_DEBUG("access=%d target=%d\n", access, target); + switch (target) { + case NV_DMA_TARGET_AGP: + offset += dev_priv->agp_phys; + break; + case NV_DMA_TARGET_PCI_NONLINEAR: + /*assume the "offset" is a virtual memory address*/ + is_scatter_gather = 1; + /*put back the right value*/ + target = NV_DMA_TARGET_PCI; + break; + default: + break; + } + ret = nouveau_gpuobj_new(dev, channel, - nouveau_gpuobj_class_instmem_size(dev, class), + is_scatter_gather ? ((((size + PAGE_SIZE - 1) / PAGE_SIZE) << 2) + 12) : nouveau_gpuobj_class_instmem_size(dev, class), 16, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, gpuobj); @@ -577,22 +595,53 @@ nouveau_gpuobj_dma_new(drm_device_t *dev, int channel, int class, if (dev_priv->card_type < NV_50) { uint32_t frame, adjust, pte_flags = 0; - - if (target == NV_DMA_TARGET_AGP) - offset += dev_priv->agp_phys; - if (access != NV_DMA_ACCESS_RO) - pte_flags |= (1<<1); - frame = offset & ~0x00000fff; adjust = offset & 0x00000fff; - - INSTANCE_WR(*gpuobj, 0, ((1<<12) | (1<<13) | - (adjust << 20) | + if (access != NV_DMA_ACCESS_RO) + pte_flags |= (1<<1); + + if ( ! is_scatter_gather ) + { + frame = offset & ~0x00000fff; + + INSTANCE_WR(*gpuobj, 0, ((1<<12) | (1<<13) | + (adjust << 20) | (access << 14) | (target << 16) | class)); - INSTANCE_WR(*gpuobj, 1, size - 1); - INSTANCE_WR(*gpuobj, 2, frame | pte_flags); - INSTANCE_WR(*gpuobj, 3, frame | pte_flags); + INSTANCE_WR(*gpuobj, 1, size - 1); + INSTANCE_WR(*gpuobj, 2, frame | pte_flags); + INSTANCE_WR(*gpuobj, 3, frame | pte_flags); + } + else + { + uint32_t instance_offset; + uint32_t bus_addr; + size = (uint32_t) size; + + DRM_DEBUG("Creating PCI DMA object using virtual zone starting at 0x%08x, size %d\n", (uint32_t) offset, (uint32_t)size); + INSTANCE_WR(*gpuobj, 0, ((1<<12) | (0<<13) | + (adjust << 20) | + (access << 14) | + (target << 16) | + class)); + INSTANCE_WR(*gpuobj, 1, size-1); + + /*write starting at the third dword*/ + instance_offset = 2; + + /*for each PAGE, get its bus address, fill in the page table entry, and advance*/ + while ( size > 0 ) { + bus_addr = (uint32_t) page_address(vmalloc_to_page((void *) (uint32_t) offset)); + bus_addr |= (offset & ~PAGE_MASK); + bus_addr = virt_to_bus((void *)bus_addr); + frame = bus_addr & ~0x00000FFF; + INSTANCE_WR(*gpuobj, instance_offset, frame | pte_flags); + offset += PAGE_SIZE; + instance_offset ++; + size -= PAGE_SIZE; + } + + } } else { INSTANCE_WR(*gpuobj, 0, 0x00190000 | class); INSTANCE_WR(*gpuobj, 1, offset + size - 1); @@ -804,24 +853,38 @@ nouveau_gpuobj_channel_init(drm_device_t *dev, int channel, return ret; } - /* non-AGP unimplemented */ - if (dev_priv->agp_heap == NULL) - return 0; - - /* GART ctxdma */ - if ((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, - 0, dev_priv->agp_available_size, - NV_DMA_ACCESS_RW, NV_DMA_TARGET_AGP, - &tt))) { - DRM_ERROR("Error creating TT ctxdma: %d\n", ret); - return ret; + if (dev_priv->agp_heap) { + /* AGPGART ctxdma */ + if ((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, + 0, dev_priv->agp_available_size, + NV_DMA_ACCESS_RW, + NV_DMA_TARGET_AGP, &tt))) { + DRM_ERROR("Error creating AGP TT ctxdma: %d\n", DRM_ERR(ENOMEM)); + return DRM_ERR(ENOMEM); + } + + ret = nouveau_gpuobj_ref_add(dev, channel, tt_h, tt, NULL); + if (ret) { + DRM_ERROR("Error referencing AGP TT ctxdma: %d\n", ret); + return ret; + } } - - if ((ret = nouveau_gpuobj_ref_add(dev, channel, tt_h, tt, NULL))) { - DRM_ERROR("Error referencing TT ctxdma: %d\n", ret); - return ret; + else { + /*PCI*/ + if((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, + (unsigned int) dev->sg->virtual, dev->sg->pages * PAGE_SIZE, + NV_DMA_ACCESS_RW, + NV_DMA_TARGET_PCI_NONLINEAR, &tt))) { + DRM_ERROR("Error creating PCI TT ctxdma: %d\n", DRM_ERR(ENOMEM)); + return DRM_ERR(ENOMEM); + } + + ret = nouveau_gpuobj_ref_add(dev, channel, tt_h, tt, NULL); + if (ret) { + DRM_ERROR("Error referencing PCI TT ctxdma: %d\n", ret); + return ret; + } } - return 0; } diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index c2ebc714..a66d2d34 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -39,6 +39,8 @@ #define NV_DMA_TARGET_VIDMEM 0 #define NV_DMA_TARGET_PCI 2 #define NV_DMA_TARGET_AGP 3 +/*The following is not a real value used by nvidia cards, it's changed by nouveau_object_dma_create*/ +#define NV_DMA_TARGET_PCI_NONLINEAR 8 /* Some object classes we care about in the drm */ #define NV_CLASS_DMA_FROM_MEMORY 0x00000002 diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index c51d7d5d..14b33a4a 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -348,6 +348,7 @@ void nouveau_preclose(drm_device_t * dev, DRMFILE filp) nouveau_fifo_cleanup(dev, filp); nouveau_mem_release(filp,dev_priv->fb_heap); nouveau_mem_release(filp,dev_priv->agp_heap); + nouveau_mem_release(filp,dev_priv->pci_heap); } /* first module load, setup the mmio/fb mapping */ @@ -442,6 +443,15 @@ int nouveau_ioctl_getparam(DRM_IOCTL_ARGS) case NOUVEAU_GETPARAM_AGP_PHYSICAL: getparam.value=dev_priv->agp_phys; break; + case NOUVEAU_GETPARAM_PCI_PHYSICAL: + if ( dev -> sg ) + getparam.value=dev->sg->virtual; + else + { + DRM_ERROR("Requested PCIGART address, while no PCIGART was created\n"); + DRM_ERR(EINVAL); + } + break; case NOUVEAU_GETPARAM_FB_SIZE: getparam.value=dev_priv->fb_available_size; break; @@ -472,6 +482,8 @@ int nouveau_ioctl_setparam(DRM_IOCTL_ARGS) switch (setparam.value) { case NOUVEAU_MEM_AGP: case NOUVEAU_MEM_FB: + case NOUVEAU_MEM_PCI: + case NOUVEAU_MEM_AGP | NOUVEAU_MEM_PCI_ACCEPTABLE: break; default: DRM_ERROR("invalid CMDBUF_LOCATION value=%lld\n", -- cgit v1.2.3 From 13e1377044d581d692af77656e3bc32c9eb183f7 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 11 Jul 2007 12:38:48 +1000 Subject: nouveau: Some checks on userspace object handles. --- shared-core/nouveau_fifo.c | 3 +++ shared-core/nouveau_object.c | 26 +++++++++++++++++++++++++- 2 files changed, 28 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index bc3a9948..fcdc14c8 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -474,6 +474,9 @@ static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_fifo_alloc_t __user *) data, sizeof(init)); + if (init.fb_ctxdma_handle == ~0 || init.tt_ctxdma_handle == ~0) + return DRM_ERR(EINVAL); + res = nouveau_fifo_alloc(dev, &init.channel, filp, init.fb_ctxdma_handle, init.tt_ctxdma_handle); diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index dcb29b40..82944c2b 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -470,6 +470,26 @@ nouveau_gpuobj_new_ref(drm_device_t *dev, int oc, int rc, uint32_t handle, return 0; } +static int +nouveau_gpuobj_ref_find(drm_device_t *dev, int channel, uint32_t handle, + nouveau_gpuobj_ref_t **ref_ret) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + nouveau_gpuobj_ref_t *ref = chan->ramht_refs; + + while (ref) { + if (ref->handle == handle) { + if (ref_ret) + *ref_ret = ref; + return 0; + } + ref = ref->next; + } + + return DRM_ERR(EINVAL); +} + int nouveau_gpuobj_new_fake(drm_device_t *dev, uint32_t offset, uint32_t size, uint32_t flags, nouveau_gpuobj_t **pgpuobj, @@ -927,7 +947,11 @@ int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS) } //FIXME: check args, only allow trusted objects to be created - //FIXME: check for pre-existing handle + + if (init.handle == ~0) + return DRM_ERR(EINVAL); + if (nouveau_gpuobj_ref_find(dev, init.channel, init.handle, NULL) == 0) + return DRM_ERR(EEXIST); if ((ret = nouveau_gpuobj_gr_new(dev, init.channel, init.class, &gr))) { DRM_ERROR("Error creating gr object: %d (%d/0x%08x)\n", -- cgit v1.2.3 From 5ccadac9e3b1beb8ac0177c7a39862094fe3b6de Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 11 Jul 2007 14:22:59 +1000 Subject: nouveau/nv50: G80 fixes. Again, no hardware, so no idea if it'll even work yet. I understand how the PRAMIN setup works now, un-hardcoding stuff will come "RealSoonNow(tm)". --- shared-core/nv50_fifo.c | 3 +-- shared-core/nv50_instmem.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index d4c3ca87..ee1fb887 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -235,8 +235,7 @@ nv50_fifo_create_context(drm_device_t *dev, int channel) DRM_DEBUG("ch%d\n", channel); if (IS_G80) { - uint32_t ramfc_offset; - ramfc_offset = chan->ramin->gpuobj->im_pramin->start + 0x1000; + uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start; if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, 0x100, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, diff --git a/shared-core/nv50_instmem.c b/shared-core/nv50_instmem.c index 4aca9e7d..1ea64b35 100644 --- a/shared-core/nv50_instmem.c +++ b/shared-core/nv50_instmem.c @@ -68,7 +68,7 @@ nv50_instmem_init(drm_device_t *dev) } else { unk = cb + 0x5400; cb0 = cb + 0x5440; - cb1 = cb + 0x1438; + cb1 = cb + 0x1478; } DRM_DEBUG("PRAMIN config:\n"); -- cgit v1.2.3 From d26ae22c2b17e0f193334cefec7d141befcfa1ee Mon Sep 17 00:00:00 2001 From: Arthur Huillet Date: Wed, 11 Jul 2007 14:56:27 +0200 Subject: fixed bug that prevented PCIE cards from actually using PCIGART - NV50 will probably still have a problem --- shared-core/nouveau_fifo.c | 2 +- shared-core/nouveau_mem.c | 5 ++--- shared-core/nouveau_state.c | 4 ++-- 3 files changed, 5 insertions(+), 6 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index fcdc14c8..88f66d70 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -217,7 +217,7 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP, &pushbuf); } else if ( cb->flags & NOUVEAU_MEM_PCI) { - DRM_DEBUG("Creating CB in PCI memory starting at virt 0x%08llx size %d\n", cb->start, cb->size); + DRM_DEBUG("Creating CB in PCI memory\n", cb->start, cb->size); ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, cb->start, diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 79f94fd4..c545acf2 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -345,9 +345,9 @@ int nouveau_mem_init(struct drm_device *dev) dev_priv->agp_phys = info.aperture_base; dev_priv->agp_available_size = info.aperture_size; + goto have_agp; } -goto have_agp; no_agp: dev_priv->pci_heap = NULL; DRM_DEBUG("Allocating sg memory for PCI DMA\n"); @@ -357,8 +357,7 @@ no_agp: goto no_pci; } - DRM_DEBUG("Got %d KiB\n", (dev->sg->pages * PAGE_SIZE) >> 10); - if ( nouveau_mem_init_heap(&dev_priv->pci_heap, dev->sg->virtual, dev->sg->pages * PAGE_SIZE)) + if ( nouveau_mem_init_heap(&dev_priv->pci_heap, (uint64_t) dev->sg->virtual, dev->sg->pages * PAGE_SIZE)) { DRM_ERROR("Unable to initialize pci_heap!"); goto no_pci; diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 14b33a4a..fe3db168 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -445,11 +445,11 @@ int nouveau_ioctl_getparam(DRM_IOCTL_ARGS) break; case NOUVEAU_GETPARAM_PCI_PHYSICAL: if ( dev -> sg ) - getparam.value=dev->sg->virtual; + getparam.value=(uint64_t) dev->sg->virtual; else { DRM_ERROR("Requested PCIGART address, while no PCIGART was created\n"); - DRM_ERR(EINVAL); + return DRM_ERR(EINVAL); } break; case NOUVEAU_GETPARAM_FB_SIZE: -- cgit v1.2.3 From b301a9051b3fd9ad3dce6bcf32b06da7953a8b91 Mon Sep 17 00:00:00 2001 From: Arthur Huillet Date: Wed, 11 Jul 2007 15:01:37 +0200 Subject: NV50 will not attempt to use PCIGART now --- shared-core/nouveau_mem.c | 3 +++ shared-core/nouveau_object.c | 2 ++ 2 files changed, 5 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index c545acf2..a428b813 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -349,6 +349,9 @@ int nouveau_mem_init(struct drm_device *dev) } no_agp: + + if ( dev_priv->card_type >= NV_50 ) goto no_pci; + dev_priv->pci_heap = NULL; DRM_DEBUG("Allocating sg memory for PCI DMA\n"); if ( drm_sg_alloc(dev, &sgreq) ) diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 82944c2b..0fe32fda 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -890,6 +890,8 @@ nouveau_gpuobj_channel_init(drm_device_t *dev, int channel, } } else { + if ( dev_priv -> card_type >= NV_50 ) return 0; /*no PCIGART for NV50*/ + /*PCI*/ if((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, (unsigned int) dev->sg->virtual, dev->sg->pages * PAGE_SIZE, -- cgit v1.2.3 From 5fbdf9da8bda996c0a474d13fe69d260f12ffce7 Mon Sep 17 00:00:00 2001 From: Arthur Huillet Date: Thu, 12 Jul 2007 02:35:39 +0200 Subject: fixed object creation code to not Oops on 64bits, worked around memalloc not working on 64bit for PCIGART --- shared-core/nouveau_fifo.c | 2 +- shared-core/nouveau_mem.c | 2 ++ shared-core/nouveau_object.c | 39 +++++++++++++++++++++++++++++++++------ 3 files changed, 36 insertions(+), 7 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 88f66d70..7bcb1c8f 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -217,7 +217,7 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP, &pushbuf); } else if ( cb->flags & NOUVEAU_MEM_PCI) { - DRM_DEBUG("Creating CB in PCI memory\n", cb->start, cb->size); + DRM_DEBUG("Creating CB in PCI memory\n"); ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, cb->start, diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index a428b813..790f6b5b 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -549,6 +549,8 @@ int nouveau_ioctl_mem_free(DRM_IOCTL_ARGS) block = find_block(dev_priv->fb_heap, memfree.region_offset); else if (memfree.flags&NOUVEAU_MEM_AGP) block = find_block(dev_priv->agp_heap, memfree.region_offset); + else if (memfree.flags&NOUVEAU_MEM_PCI) + block = find_block(dev_priv->pci_heap, memfree.region_offset); if (!block) return DRM_ERR(EFAULT); if (block->filp != filp) diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 0fe32fda..4f7ad111 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -635,10 +635,10 @@ nouveau_gpuobj_dma_new(drm_device_t *dev, int channel, int class, else { uint32_t instance_offset; - uint32_t bus_addr; + uint64_t bus_addr; size = (uint32_t) size; - DRM_DEBUG("Creating PCI DMA object using virtual zone starting at 0x%08x, size %d\n", (uint32_t) offset, (uint32_t)size); + DRM_DEBUG("Creating PCI DMA object using virtual zone starting at %#llx, size %d\n", offset, (uint32_t)size); INSTANCE_WR(*gpuobj, 0, ((1<<12) | (0<<13) | (adjust << 20) | (access << 14) | @@ -651,10 +651,37 @@ nouveau_gpuobj_dma_new(drm_device_t *dev, int channel, int class, /*for each PAGE, get its bus address, fill in the page table entry, and advance*/ while ( size > 0 ) { - bus_addr = (uint32_t) page_address(vmalloc_to_page((void *) (uint32_t) offset)); + bus_addr = vmalloc_to_page(offset); + if ( ! bus_addr ) + { + DRM_ERROR("Couldn't map virtual address %#llx to a page number\n", offset); + nouveau_gpuobj_del(dev, gpuobj); + return DRM_ERR(ENOMEM); + } + bus_addr = (uint64_t) page_address(bus_addr); + if ( ! bus_addr ) + { + DRM_ERROR("Couldn't find page address for address %#llx\n", offset); + nouveau_gpuobj_del(dev, gpuobj); + return DRM_ERR(ENOMEM); + } bus_addr |= (offset & ~PAGE_MASK); bus_addr = virt_to_bus((void *)bus_addr); - frame = bus_addr & ~0x00000FFF; + if ( ! bus_addr ) + { + DRM_ERROR("Couldn't get bus address for %#llx\n", offset); + nouveau_gpuobj_del(dev, gpuobj); + return DRM_ERR(ENOMEM); + } + + /*if ( bus_addr >= 1 << 32 ) + { + DRM_ERROR("Bus address %#llx is over 32 bits, Nvidia cards cannot address it !\n", bus_addr); + nouveau_gpuobj_del(dev, gpuobj); + return DRM_ERR(EINVAL); + }*/ + + frame = (uint32_t) bus_addr & ~0x00000FFF; INSTANCE_WR(*gpuobj, instance_offset, frame | pte_flags); offset += PAGE_SIZE; instance_offset ++; @@ -894,11 +921,11 @@ nouveau_gpuobj_channel_init(drm_device_t *dev, int channel, /*PCI*/ if((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, - (unsigned int) dev->sg->virtual, dev->sg->pages * PAGE_SIZE, + dev->sg->virtual, dev->sg->pages * PAGE_SIZE, NV_DMA_ACCESS_RW, NV_DMA_TARGET_PCI_NONLINEAR, &tt))) { DRM_ERROR("Error creating PCI TT ctxdma: %d\n", DRM_ERR(ENOMEM)); - return DRM_ERR(ENOMEM); + return 0; //this is noncritical } ret = nouveau_gpuobj_ref_add(dev, channel, tt_h, tt, NULL); -- cgit v1.2.3 From 750371cb6ea9a64c9d4d4d3b9716c3c68d810d48 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 12 Jul 2007 10:15:16 +1000 Subject: nouveau: separate region_offset into map_handle and offset. --- shared-core/nouveau_drm.h | 7 +++--- shared-core/nouveau_drv.h | 3 ++- shared-core/nouveau_fifo.c | 20 ++++++++++++------ shared-core/nouveau_mem.c | 48 ++++++++++++++++++++++++------------------ shared-core/nouveau_notifier.c | 2 -- shared-core/nouveau_object.c | 6 +++--- shared-core/nv50_instmem.c | 2 +- 7 files changed, 50 insertions(+), 38 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h index 7abe82e0..78ab9508 100644 --- a/shared-core/nouveau_drm.h +++ b/shared-core/nouveau_drm.h @@ -25,7 +25,7 @@ #ifndef __NOUVEAU_DRM_H__ #define __NOUVEAU_DRM_H__ -#define NOUVEAU_DRM_HEADER_PATCHLEVEL 8 +#define NOUVEAU_DRM_HEADER_PATCHLEVEL 9 typedef struct drm_nouveau_fifo_alloc { uint32_t fb_ctxdma_handle; @@ -80,12 +80,13 @@ typedef struct drm_nouveau_mem_alloc { int flags; int alignment; uint64_t size; // in bytes - uint64_t region_offset; + uint64_t offset; + drm_handle_t map_handle; } drm_nouveau_mem_alloc_t; typedef struct drm_nouveau_mem_free { - uint64_t region_offset; + uint64_t offset; int flags; } drm_nouveau_mem_free_t; diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index ea03fe37..99ddb586 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -34,7 +34,7 @@ #define DRIVER_MAJOR 0 #define DRIVER_MINOR 0 -#define DRIVER_PATCHLEVEL 8 +#define DRIVER_PATCHLEVEL 9 #define NOUVEAU_FAMILY 0x0000FFFF #define NOUVEAU_FLAGS 0xFFFF0000 @@ -50,6 +50,7 @@ struct mem_block { DRMFILE filp; /* 0: free, -1: heap, other: real files */ int flags; drm_local_map_t *map; + drm_handle_t map_handle; }; enum nouveau_flags { diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 7bcb1c8f..7114a931 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -213,8 +213,7 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) DRM_DEBUG("Creating CB in AGP memory\n"); ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, - cb->start - dev_priv->agp_phys, - cb->size, + cb->start, cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP, &pushbuf); } else if ( cb->flags & NOUVEAU_MEM_PCI) { DRM_DEBUG("Creating CB in PCI memory\n"); @@ -226,7 +225,7 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) } else if (dev_priv->card_type != NV_04) { ret = nouveau_gpuobj_dma_new (dev, channel, NV_CLASS_DMA_IN_MEMORY, - cb->start - drm_get_resource_start(dev, 1), + cb->start, cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM, &pushbuf); } else { @@ -236,7 +235,8 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) */ ret = nouveau_gpuobj_dma_new (dev, channel, NV_CLASS_DMA_IN_MEMORY, - cb->start, cb->size, NV_DMA_ACCESS_RO, + cb->start + drm_get_resource_start(dev, 1), + cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_PCI, &pushbuf); } @@ -467,8 +467,9 @@ static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan; drm_nouveau_fifo_alloc_t init; + drm_map_list_t *entry; + struct nouveau_fifo *chan; int res; DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_fifo_alloc_t __user *) data, @@ -501,12 +502,17 @@ static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) if (res != 0) return res; + entry = drm_find_matching_map(dev, chan->regs); + if (!entry) + return DRM_ERR(EINVAL); + init.ctrl = entry->user_token; + /* pass back FIFO map info to the caller */ - init.cmdbuf = chan->pushbuf_mem->start; + init.cmdbuf = chan->pushbuf_mem->map_handle; init.cmdbuf_size = chan->pushbuf_mem->size; /* and the notifier block */ - init.notifier = chan->notifier_block->start; + init.notifier = chan->notifier_block->map_handle; init.notifier_size = chan->notifier_block->size; DRM_COPY_TO_USER_IOCTL((drm_nouveau_fifo_alloc_t __user *)data, diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 790f6b5b..d4b2bc04 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -339,8 +339,7 @@ int nouveau_mem_init(struct drm_device *dev) } if (nouveau_mem_init_heap(&dev_priv->agp_heap, - info.aperture_base, - info.aperture_size)) + 0, info.aperture_size)) goto no_agp; dev_priv->agp_phys = info.aperture_base; @@ -360,7 +359,8 @@ no_agp: goto no_pci; } - if ( nouveau_mem_init_heap(&dev_priv->pci_heap, (uint64_t) dev->sg->virtual, dev->sg->pages * PAGE_SIZE)) + if ( nouveau_mem_init_heap(&dev_priv->pci_heap, 0, + dev->sg->pages * PAGE_SIZE)) { DRM_ERROR("Unable to initialize pci_heap!"); goto no_pci; @@ -387,18 +387,13 @@ have_agp: /* On cards with > 256Mb, you can't map everything. * So we create a second FB heap for that type of memory */ if (nouveau_mem_init_heap(&dev_priv->fb_heap, - drm_get_resource_start(dev,1), - 256*1024*1024)) + 0, 256*1024*1024)) return DRM_ERR(ENOMEM); if (nouveau_mem_init_heap(&dev_priv->fb_nomap_heap, - drm_get_resource_start(dev,1) + - 256*1024*1024, - fb_size-256*1024*1024)) + 256*1024*1024, fb_size-256*1024*1024)) return DRM_ERR(ENOMEM); } else { - if (nouveau_mem_init_heap(&dev_priv->fb_heap, - drm_get_resource_start(dev,1), - fb_size)) + if (nouveau_mem_init_heap(&dev_priv->fb_heap, 0, fb_size)) return DRM_ERR(ENOMEM); dev_priv->fb_nomap_heap=NULL; } @@ -473,23 +468,33 @@ alloc_ok: if (flags&NOUVEAU_MEM_MAPPED) { + drm_map_list_t *entry; int ret = 0; block->flags|=NOUVEAU_MEM_MAPPED; if (type == NOUVEAU_MEM_AGP) - ret = drm_addmap(dev, block->start - dev->agp->base, block->size, - _DRM_AGP, 0, &block->map); + ret = drm_addmap(dev, block->start + dev->agp->base, + block->size, _DRM_AGP, 0, &block->map); else if (type == NOUVEAU_MEM_FB) - ret = drm_addmap(dev, block->start, block->size, - _DRM_FRAME_BUFFER, 0, &block->map); + ret = drm_addmap(dev, block->start + dev_priv->fb_phys, + block->size, _DRM_FRAME_BUFFER, + 0, &block->map); else if (type == NOUVEAU_MEM_PCI) - ret = drm_addmap(dev, block->start - (unsigned long int)dev->sg->virtual, block->size, - _DRM_SCATTER_GATHER, 0, &block->map); + ret = drm_addmap(dev, block->start, block->size, + _DRM_SCATTER_GATHER, 0, &block->map); if (ret) { nouveau_mem_free_block(block); return NULL; } + + entry = drm_find_matching_map(dev, block->map); + if (!entry) { + nouveau_mem_free_block(block); + return NULL; + } + DRM_ERROR("user_token=0x%08x\n", entry->user_token); + block->map_handle = entry->user_token; } DRM_INFO("allocated 0x%llx\n", block->start); @@ -526,7 +531,8 @@ int nouveau_ioctl_mem_alloc(DRM_IOCTL_ARGS) block=nouveau_mem_alloc(dev, alloc.alignment, alloc.size, alloc.flags, filp); if (!block) return DRM_ERR(ENOMEM); - alloc.region_offset=block->start; + alloc.map_handle=block->map_handle; + alloc.offset=block->start; alloc.flags=block->flags; DRM_COPY_TO_USER_IOCTL((drm_nouveau_mem_alloc_t __user *) data, alloc, sizeof(alloc)); @@ -546,11 +552,11 @@ int nouveau_ioctl_mem_free(DRM_IOCTL_ARGS) block=NULL; if (memfree.flags&NOUVEAU_MEM_FB) - block = find_block(dev_priv->fb_heap, memfree.region_offset); + block = find_block(dev_priv->fb_heap, memfree.offset); else if (memfree.flags&NOUVEAU_MEM_AGP) - block = find_block(dev_priv->agp_heap, memfree.region_offset); + block = find_block(dev_priv->agp_heap, memfree.offset); else if (memfree.flags&NOUVEAU_MEM_PCI) - block = find_block(dev_priv->pci_heap, memfree.region_offset); + block = find_block(dev_priv->pci_heap, memfree.offset); if (!block) return DRM_ERR(EFAULT); if (block->filp != filp) diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index 30216293..7d892064 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -95,10 +95,8 @@ nouveau_notifier_alloc(drm_device_t *dev, int channel, uint32_t handle, offset = chan->notifier_block->start + mem->start; if (chan->notifier_block->flags & NOUVEAU_MEM_FB) { - offset -= drm_get_resource_start(dev, 1); target = NV_DMA_TARGET_VIDMEM; } else if (chan->notifier_block->flags & NOUVEAU_MEM_AGP) { - offset -= dev_priv->agp_phys; target = NV_DMA_TARGET_AGP; } else { DRM_ERROR("Bad DMA target, flags 0x%08x!\n", diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 4f7ad111..e8ed708f 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -357,12 +357,12 @@ nouveau_gpuobj_instance_get(drm_device_t *dev, int channel, DRM_ERROR("AII, no VRAM backing gpuobj\n"); return DRM_ERR(EINVAL); } - *inst = gpuobj->im_backing->start - dev_priv->fb_phys; + *inst = gpuobj->im_backing->start; return 0; } else { /* ...from local heap */ cpramin = dev_priv->fifos[gpuobj->im_channel]->ramin->gpuobj; - *inst = (cpramin->im_backing->start - dev_priv->fb_phys) + + *inst = cpramin->im_backing->start + (gpuobj->im_pramin->start - cpramin->im_pramin->start); return 0; } @@ -917,7 +917,7 @@ nouveau_gpuobj_channel_init(drm_device_t *dev, int channel, } } else { - if ( dev_priv -> card_type >= NV_50 ) return 0; /*no PCIGART for NV50*/ + if (dev_priv -> card_type >= NV_50 ) return 0; /*no PCIGART for NV50*/ /*PCI*/ if((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, diff --git a/shared-core/nv50_instmem.c b/shared-core/nv50_instmem.c index 1ea64b35..81c60829 100644 --- a/shared-core/nv50_instmem.c +++ b/shared-core/nv50_instmem.c @@ -215,7 +215,7 @@ nv50_instmem_bind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) pte = (gpuobj->im_pramin->start >> 12) << 3; pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte; - vram = gpuobj->im_backing->start - dev_priv->fb_phys; + vram = gpuobj->im_backing->start; if (pte == pte_end) { DRM_ERROR("WARNING: badness in bind() pte calc\n"); -- cgit v1.2.3 From 522a0c868c79b48c5434f39faab1a02ca4425a90 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 12 Jul 2007 11:39:45 +1000 Subject: nouveau: nuke left over debug message --- shared-core/nouveau_mem.c | 1 - 1 file changed, 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index d4b2bc04..9bfa8365 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -493,7 +493,6 @@ alloc_ok: nouveau_mem_free_block(block); return NULL; } - DRM_ERROR("user_token=0x%08x\n", entry->user_token); block->map_handle = entry->user_token; } -- cgit v1.2.3 From af317f1cc7136dbf03b39ced64c42202703c5066 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 12 Jul 2007 11:55:47 +1000 Subject: nouveau: mem_alloc() returns offsets, not absolute addresses now. --- shared-core/nouveau_object.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index e8ed708f..16b38e95 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -646,6 +646,8 @@ nouveau_gpuobj_dma_new(drm_device_t *dev, int channel, int class, class)); INSTANCE_WR(*gpuobj, 1, size-1); + offset += dev->sg->virtual; + /*write starting at the third dword*/ instance_offset = 2; @@ -921,7 +923,7 @@ nouveau_gpuobj_channel_init(drm_device_t *dev, int channel, /*PCI*/ if((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, - dev->sg->virtual, dev->sg->pages * PAGE_SIZE, + 0, dev->sg->pages * PAGE_SIZE, NV_DMA_ACCESS_RW, NV_DMA_TARGET_PCI_NONLINEAR, &tt))) { DRM_ERROR("Error creating PCI TT ctxdma: %d\n", DRM_ERR(ENOMEM)); -- cgit v1.2.3 From 851c950d988e5a47fa6add71427e5ef8d4dcf231 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 13 Jul 2007 02:18:59 +1000 Subject: nouveau: unbreak AGP --- shared-core/nouveau_mem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 9bfa8365..79d1bb87 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -473,8 +473,8 @@ alloc_ok: block->flags|=NOUVEAU_MEM_MAPPED; if (type == NOUVEAU_MEM_AGP) - ret = drm_addmap(dev, block->start + dev->agp->base, - block->size, _DRM_AGP, 0, &block->map); + ret = drm_addmap(dev, block->start, block->size, + _DRM_AGP, 0, &block->map); else if (type == NOUVEAU_MEM_FB) ret = drm_addmap(dev, block->start + dev_priv->fb_phys, block->size, _DRM_FRAME_BUFFER, -- cgit v1.2.3 From 0029713451af6f5f216079775ff77cae9b423c0e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 13 Jul 2007 15:09:31 +1000 Subject: nouveau: nuke internal typedefs, and drm_device_t use. --- shared-core/nouveau_drm.h | 40 +++--- shared-core/nouveau_drv.h | 320 +++++++++++++++++++++-------------------- shared-core/nouveau_fifo.c | 49 +++---- shared-core/nouveau_irq.c | 36 ++--- shared-core/nouveau_mem.c | 25 ++-- shared-core/nouveau_notifier.c | 23 +-- shared-core/nouveau_object.c | 133 ++++++++--------- shared-core/nouveau_state.c | 54 +++---- shared-core/nv04_fb.c | 6 +- shared-core/nv04_fifo.c | 16 +-- shared-core/nv04_graph.c | 20 +-- shared-core/nv04_instmem.c | 20 +-- shared-core/nv04_mc.c | 6 +- shared-core/nv04_timer.c | 6 +- shared-core/nv10_fb.c | 6 +- shared-core/nv10_fifo.c | 16 +-- shared-core/nv10_graph.c | 32 ++--- shared-core/nv20_graph.c | 40 +++--- shared-core/nv30_graph.c | 38 ++--- shared-core/nv40_fb.c | 6 +- shared-core/nv40_fifo.c | 16 +-- shared-core/nv40_graph.c | 64 ++++----- shared-core/nv40_mc.c | 6 +- shared-core/nv50_fifo.c | 58 ++++---- shared-core/nv50_graph.c | 42 +++--- shared-core/nv50_instmem.c | 22 +-- shared-core/nv50_mc.c | 6 +- 27 files changed, 554 insertions(+), 552 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h index 78ab9508..e2a9ea83 100644 --- a/shared-core/nouveau_drm.h +++ b/shared-core/nouveau_drm.h @@ -27,7 +27,7 @@ #define NOUVEAU_DRM_HEADER_PATCHLEVEL 9 -typedef struct drm_nouveau_fifo_alloc { +struct drm_nouveau_fifo_alloc { uint32_t fb_ctxdma_handle; uint32_t tt_ctxdma_handle; @@ -42,27 +42,24 @@ typedef struct drm_nouveau_fifo_alloc { /* Notifier memory */ drm_handle_t notifier; int notifier_size; -} -drm_nouveau_fifo_alloc_t; +}; -typedef struct drm_nouveau_grobj_alloc { +struct drm_nouveau_grobj_alloc { int channel; uint32_t handle; int class; -} -drm_nouveau_grobj_alloc_t; +}; #define NOUVEAU_MEM_ACCESS_RO 1 #define NOUVEAU_MEM_ACCESS_WO 2 #define NOUVEAU_MEM_ACCESS_RW 3 -typedef struct drm_nouveau_notifier_alloc { +struct drm_nouveau_notifier_alloc { int channel; uint32_t handle; int count; uint32_t offset; -} -drm_nouveau_notifier_alloc_t; +}; #define NOUVEAU_MEM_FB 0x00000001 #define NOUVEAU_MEM_AGP 0x00000002 @@ -76,20 +73,18 @@ drm_nouveau_notifier_alloc_t; #define NOUVEAU_MEM_INSTANCE 0x00000200 /* internal */ #define NOUVEAU_MEM_NOTIFIER 0x00000400 /* internal */ -typedef struct drm_nouveau_mem_alloc { +struct drm_nouveau_mem_alloc { int flags; int alignment; uint64_t size; // in bytes uint64_t offset; drm_handle_t map_handle; -} -drm_nouveau_mem_alloc_t; +}; -typedef struct drm_nouveau_mem_free { +struct drm_nouveau_mem_free { uint64_t offset; int flags; -} -drm_nouveau_mem_free_t; +}; /* FIXME : maybe unify {GET,SET}PARAMs */ #define NOUVEAU_GETPARAM_PCI_VENDOR 3 @@ -100,19 +95,17 @@ drm_nouveau_mem_free_t; #define NOUVEAU_GETPARAM_FB_SIZE 8 #define NOUVEAU_GETPARAM_AGP_SIZE 9 #define NOUVEAU_GETPARAM_PCI_PHYSICAL 10 -typedef struct drm_nouveau_getparam { +struct drm_nouveau_getparam { uint64_t param; uint64_t value; -} -drm_nouveau_getparam_t; +}; #define NOUVEAU_SETPARAM_CMDBUF_LOCATION 1 #define NOUVEAU_SETPARAM_CMDBUF_SIZE 2 -typedef struct drm_nouveau_setparam { +struct drm_nouveau_setparam { uint64_t param; uint64_t value; -} -drm_nouveau_setparam_t; +}; enum nouveau_card_type { NV_UNKNOWN =0, @@ -142,12 +135,11 @@ enum nouveau_bus_type { #define NOUVEAU_MAX_SAREA_CLIPRECTS 16 -typedef struct drm_nouveau_sarea { +struct drm_nouveau_sarea { /* the cliprects */ drm_clip_rect_t boxes[NOUVEAU_MAX_SAREA_CLIPRECTS]; unsigned int nbox; -} -drm_nouveau_sarea_t; +}; #define DRM_NOUVEAU_FIFO_ALLOC 0x00 #define DRM_NOUVEAU_GROBJ_ALLOC 0x01 diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 99ddb586..4fa979e6 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -66,7 +66,7 @@ enum nouveau_flags { #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) #define NVOBJ_FLAG_ZERO_FREE (1 << 2) #define NVOBJ_FLAG_FAKE (1 << 3) -typedef struct nouveau_gpuobj { +struct nouveau_gpuobj { struct nouveau_gpuobj *next; struct nouveau_gpuobj *prev; @@ -80,17 +80,17 @@ typedef struct nouveau_gpuobj { uint32_t engine; uint32_t class; -} nouveau_gpuobj_t; +}; -typedef struct nouveau_gpuobj_ref { +struct nouveau_gpuobj_ref { struct nouveau_gpuobj_ref *next; - nouveau_gpuobj_t *gpuobj; + struct nouveau_gpuobj *gpuobj; uint32_t instance; int channel; int handle; -} nouveau_gpuobj_ref_t; +}; struct nouveau_fifo { @@ -102,9 +102,9 @@ struct nouveau_fifo drm_local_map_t *regs; /* DMA push buffer */ - nouveau_gpuobj_ref_t *pushbuf; - struct mem_block *pushbuf_mem; - uint32_t pushbuf_base; + struct nouveau_gpuobj_ref *pushbuf; + struct mem_block *pushbuf_mem; + uint32_t pushbuf_base; /* Notifier memory */ struct mem_block *notifier_block; @@ -112,17 +112,17 @@ struct nouveau_fifo drm_local_map_t *notifier_map; /* PFIFO context */ - nouveau_gpuobj_ref_t *ramfc; + struct nouveau_gpuobj_ref *ramfc; /* PGRAPH context */ - nouveau_gpuobj_ref_t *ramin_grctx; + struct nouveau_gpuobj_ref *ramin_grctx; uint32_t pgraph_ctx [340]; /* XXX dynamic alloc ? */ /* Objects */ - nouveau_gpuobj_ref_t *ramin; /* Private instmem */ - struct mem_block *ramin_heap; /* Private PRAMIN heap */ - nouveau_gpuobj_ref_t *ramht; /* Hash table */ - nouveau_gpuobj_ref_t *ramht_refs; /* Objects referenced by RAMHT */ + struct nouveau_gpuobj_ref *ramin; /* Private instmem */ + struct mem_block *ramin_heap; /* Private PRAMIN heap */ + struct nouveau_gpuobj_ref *ramht; /* Hash table */ + struct nouveau_gpuobj_ref *ramht_refs; /* Objects referenced by RAMHT */ }; struct nouveau_config { @@ -132,59 +132,59 @@ struct nouveau_config { } cmdbuf; }; -typedef struct nouveau_engine_func { +struct nouveau_engine_func { struct { void *priv; - int (*init)(drm_device_t *dev); - void (*takedown)(drm_device_t *dev); + int (*init)(struct drm_device *dev); + void (*takedown)(struct drm_device *dev); - int (*populate)(drm_device_t *, nouveau_gpuobj_t *, + int (*populate)(struct drm_device *, struct nouveau_gpuobj *, uint32_t *size); - void (*clear)(drm_device_t *, nouveau_gpuobj_t *); - int (*bind)(drm_device_t *, nouveau_gpuobj_t *); - int (*unbind)(drm_device_t *, nouveau_gpuobj_t *); + void (*clear)(struct drm_device *, struct nouveau_gpuobj *); + int (*bind)(struct drm_device *, struct nouveau_gpuobj *); + int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); } instmem; struct { - int (*init)(drm_device_t *dev); - void (*takedown)(drm_device_t *dev); + int (*init)(struct drm_device *dev); + void (*takedown)(struct drm_device *dev); } mc; struct { - int (*init)(drm_device_t *dev); - void (*takedown)(drm_device_t *dev); + int (*init)(struct drm_device *dev); + void (*takedown)(struct drm_device *dev); } timer; struct { - int (*init)(drm_device_t *dev); - void (*takedown)(drm_device_t *dev); + int (*init)(struct drm_device *dev); + void (*takedown)(struct drm_device *dev); } fb; struct { - int (*init)(drm_device_t *); - void (*takedown)(drm_device_t *); + int (*init)(struct drm_device *); + void (*takedown)(struct drm_device *); - int (*create_context)(drm_device_t *, int channel); - void (*destroy_context)(drm_device_t *, int channel); - int (*load_context)(drm_device_t *, int channel); - int (*save_context)(drm_device_t *, int channel); + int (*create_context)(struct drm_device *, int channel); + void (*destroy_context)(struct drm_device *, int channel); + int (*load_context)(struct drm_device *, int channel); + int (*save_context)(struct drm_device *, int channel); } graph; struct { void *priv; - int (*init)(drm_device_t *); - void (*takedown)(drm_device_t *); + int (*init)(struct drm_device *); + void (*takedown)(struct drm_device *); - int (*create_context)(drm_device_t *, int channel); - void (*destroy_context)(drm_device_t *, int channel); - int (*load_context)(drm_device_t *, int channel); - int (*save_context)(drm_device_t *, int channel); + int (*create_context)(struct drm_device *, int channel); + void (*destroy_context)(struct drm_device *, int channel); + int (*load_context)(struct drm_device *, int channel); + int (*save_context)(struct drm_device *, int channel); } fifo; -} nouveau_engine_func_t; +}; -typedef struct drm_nouveau_private { +struct drm_nouveau_private { enum { NOUVEAU_CARD_INIT_DOWN, NOUVEAU_CARD_INIT_DONE, @@ -207,7 +207,7 @@ typedef struct drm_nouveau_private { struct nouveau_engine_func Engine; /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ - nouveau_gpuobj_t *ramht; + struct nouveau_gpuobj *ramht; uint32_t ramin_rsvd_vram; uint32_t ramht_offset; uint32_t ramht_size; @@ -234,16 +234,15 @@ typedef struct drm_nouveau_private { /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */ uint32_t ctx_table_size; - nouveau_gpuobj_ref_t *ctx_table; + struct nouveau_gpuobj_ref *ctx_table; struct nouveau_config config; - nouveau_gpuobj_t *gpuobj_all; -} -drm_nouveau_private_t; + struct nouveau_gpuobj *gpuobj_all; +}; /* nouveau_state.c */ -extern void nouveau_preclose(drm_device_t * dev, DRMFILE filp); +extern void nouveau_preclose(struct drm_device * dev, DRMFILE filp); extern int nouveau_load(struct drm_device *dev, unsigned long flags); extern int nouveau_firstopen(struct drm_device *dev); extern void nouveau_lastclose(struct drm_device *dev); @@ -271,172 +270,175 @@ extern int nouveau_mem_init(struct drm_device *dev); extern void nouveau_mem_close(struct drm_device *dev); /* nouveau_notifier.c */ -extern int nouveau_notifier_init_channel(drm_device_t *, int channel, DRMFILE); -extern void nouveau_notifier_takedown_channel(drm_device_t *, int channel); -extern int nouveau_notifier_alloc(drm_device_t *, int channel, +extern int nouveau_notifier_init_channel(struct drm_device *, int channel, DRMFILE); +extern void nouveau_notifier_takedown_channel(struct drm_device *, int channel); +extern int nouveau_notifier_alloc(struct drm_device *, int channel, uint32_t handle, int cout, uint32_t *offset); extern int nouveau_ioctl_notifier_alloc(DRM_IOCTL_ARGS); /* nouveau_fifo.c */ -extern int nouveau_fifo_init(drm_device_t *dev); -extern int nouveau_fifo_number(drm_device_t *dev); -extern int nouveau_fifo_ctx_size(drm_device_t *dev); -extern void nouveau_fifo_cleanup(drm_device_t *dev, DRMFILE filp); -extern int nouveau_fifo_owner(drm_device_t *dev, DRMFILE filp, int channel); -extern void nouveau_fifo_free(drm_device_t *dev, int channel); +extern int nouveau_fifo_init(struct drm_device *dev); +extern int nouveau_fifo_number(struct drm_device *dev); +extern int nouveau_fifo_ctx_size(struct drm_device *dev); +extern void nouveau_fifo_cleanup(struct drm_device *dev, DRMFILE filp); +extern int nouveau_fifo_owner(struct drm_device *dev, DRMFILE filp, int channel); +extern void nouveau_fifo_free(struct drm_device *dev, int channel); /* nouveau_object.c */ -extern void nouveau_gpuobj_takedown(drm_device_t *dev); -extern int nouveau_gpuobj_channel_init(drm_device_t *, int channel, +extern void nouveau_gpuobj_takedown(struct drm_device *dev); +extern int nouveau_gpuobj_channel_init(struct drm_device *, int channel, uint32_t vram_h, uint32_t tt_h); -extern void nouveau_gpuobj_channel_takedown(drm_device_t *, int channel); -extern int nouveau_gpuobj_new(drm_device_t *, int channel, int size, int align, - uint32_t flags, nouveau_gpuobj_t **); -extern int nouveau_gpuobj_del(drm_device_t *, nouveau_gpuobj_t **); -extern int nouveau_gpuobj_ref_add(drm_device_t *, int channel, uint32_t handle, - nouveau_gpuobj_t *, nouveau_gpuobj_ref_t **); -extern int nouveau_gpuobj_ref_del(drm_device_t *, nouveau_gpuobj_ref_t **); -extern int nouveau_gpuobj_new_ref(drm_device_t *, int chan_obj, int chan_ref, +extern void nouveau_gpuobj_channel_takedown(struct drm_device *, int channel); +extern int nouveau_gpuobj_new(struct drm_device *, int channel, int size, int align, + uint32_t flags, struct nouveau_gpuobj **); +extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **); +extern int nouveau_gpuobj_ref_add(struct drm_device *, int channel, uint32_t handle, + struct nouveau_gpuobj *, + struct nouveau_gpuobj_ref **); +extern int nouveau_gpuobj_ref_del(struct drm_device *, struct nouveau_gpuobj_ref **); +extern int nouveau_gpuobj_new_ref(struct drm_device *, int chan_obj, int chan_ref, uint32_t handle, int size, int align, - uint32_t flags, nouveau_gpuobj_ref_t **); -extern int nouveau_gpuobj_new_fake(drm_device_t *, uint32_t offset, + uint32_t flags, struct nouveau_gpuobj_ref **); +extern int nouveau_gpuobj_new_fake(struct drm_device *, uint32_t offset, uint32_t size, uint32_t flags, - nouveau_gpuobj_t**, nouveau_gpuobj_ref_t**); -extern int nouveau_gpuobj_dma_new(drm_device_t *, int channel, int class, + struct nouveau_gpuobj**, + struct nouveau_gpuobj_ref**); +extern int nouveau_gpuobj_dma_new(struct drm_device *, int channel, int class, uint64_t offset, uint64_t size, - int access, int target, nouveau_gpuobj_t **); -extern int nouveau_gpuobj_gr_new(drm_device_t *, int channel, int class, - nouveau_gpuobj_t **); + int access, int target, + struct nouveau_gpuobj **); +extern int nouveau_gpuobj_gr_new(struct drm_device *, int channel, int class, + struct nouveau_gpuobj **); extern int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS); /* nouveau_irq.c */ extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); -extern void nouveau_irq_preinstall(drm_device_t*); -extern void nouveau_irq_postinstall(drm_device_t*); -extern void nouveau_irq_uninstall(drm_device_t*); +extern void nouveau_irq_preinstall(struct drm_device*); +extern void nouveau_irq_postinstall(struct drm_device*); +extern void nouveau_irq_uninstall(struct drm_device*); /* nv04_fb.c */ -extern int nv04_fb_init(drm_device_t *dev); -extern void nv04_fb_takedown(drm_device_t *dev); +extern int nv04_fb_init(struct drm_device *dev); +extern void nv04_fb_takedown(struct drm_device *dev); /* nv10_fb.c */ -extern int nv10_fb_init(drm_device_t *dev); -extern void nv10_fb_takedown(drm_device_t *dev); +extern int nv10_fb_init(struct drm_device *dev); +extern void nv10_fb_takedown(struct drm_device *dev); /* nv40_fb.c */ -extern int nv40_fb_init(drm_device_t *dev); -extern void nv40_fb_takedown(drm_device_t *dev); +extern int nv40_fb_init(struct drm_device *dev); +extern void nv40_fb_takedown(struct drm_device *dev); /* nv04_fifo.c */ -extern int nv04_fifo_create_context(drm_device_t *dev, int channel); -extern void nv04_fifo_destroy_context(drm_device_t *dev, int channel); -extern int nv04_fifo_load_context(drm_device_t *dev, int channel); -extern int nv04_fifo_save_context(drm_device_t *dev, int channel); +extern int nv04_fifo_create_context(struct drm_device *dev, int channel); +extern void nv04_fifo_destroy_context(struct drm_device *dev, int channel); +extern int nv04_fifo_load_context(struct drm_device *dev, int channel); +extern int nv04_fifo_save_context(struct drm_device *dev, int channel); /* nv10_fifo.c */ -extern int nv10_fifo_create_context(drm_device_t *dev, int channel); -extern void nv10_fifo_destroy_context(drm_device_t *dev, int channel); -extern int nv10_fifo_load_context(drm_device_t *dev, int channel); -extern int nv10_fifo_save_context(drm_device_t *dev, int channel); +extern int nv10_fifo_create_context(struct drm_device *dev, int channel); +extern void nv10_fifo_destroy_context(struct drm_device *dev, int channel); +extern int nv10_fifo_load_context(struct drm_device *dev, int channel); +extern int nv10_fifo_save_context(struct drm_device *dev, int channel); /* nv40_fifo.c */ -extern int nv40_fifo_create_context(drm_device_t *, int channel); -extern void nv40_fifo_destroy_context(drm_device_t *, int channel); -extern int nv40_fifo_load_context(drm_device_t *, int channel); -extern int nv40_fifo_save_context(drm_device_t *, int channel); +extern int nv40_fifo_create_context(struct drm_device *, int channel); +extern void nv40_fifo_destroy_context(struct drm_device *, int channel); +extern int nv40_fifo_load_context(struct drm_device *, int channel); +extern int nv40_fifo_save_context(struct drm_device *, int channel); /* nv50_fifo.c */ -extern int nv50_fifo_init(drm_device_t *); -extern void nv50_fifo_takedown(drm_device_t *); -extern int nv50_fifo_create_context(drm_device_t *, int channel); -extern void nv50_fifo_destroy_context(drm_device_t *, int channel); -extern int nv50_fifo_load_context(drm_device_t *, int channel); -extern int nv50_fifo_save_context(drm_device_t *, int channel); +extern int nv50_fifo_init(struct drm_device *); +extern void nv50_fifo_takedown(struct drm_device *); +extern int nv50_fifo_create_context(struct drm_device *, int channel); +extern void nv50_fifo_destroy_context(struct drm_device *, int channel); +extern int nv50_fifo_load_context(struct drm_device *, int channel); +extern int nv50_fifo_save_context(struct drm_device *, int channel); /* nv04_graph.c */ -extern void nouveau_nv04_context_switch(drm_device_t *dev); -extern int nv04_graph_init(drm_device_t *dev); -extern void nv04_graph_takedown(drm_device_t *dev); -extern int nv04_graph_create_context(drm_device_t *dev, int channel); -extern void nv04_graph_destroy_context(drm_device_t *dev, int channel); -extern int nv04_graph_load_context(drm_device_t *dev, int channel); -extern int nv04_graph_save_context(drm_device_t *dev, int channel); +extern void nouveau_nv04_context_switch(struct drm_device *dev); +extern int nv04_graph_init(struct drm_device *dev); +extern void nv04_graph_takedown(struct drm_device *dev); +extern int nv04_graph_create_context(struct drm_device *dev, int channel); +extern void nv04_graph_destroy_context(struct drm_device *dev, int channel); +extern int nv04_graph_load_context(struct drm_device *dev, int channel); +extern int nv04_graph_save_context(struct drm_device *dev, int channel); /* nv10_graph.c */ -extern void nouveau_nv10_context_switch(drm_device_t *dev); -extern int nv10_graph_init(drm_device_t *dev); -extern void nv10_graph_takedown(drm_device_t *dev); -extern int nv10_graph_create_context(drm_device_t *dev, int channel); -extern void nv10_graph_destroy_context(drm_device_t *dev, int channel); -extern int nv10_graph_load_context(drm_device_t *dev, int channel); -extern int nv10_graph_save_context(drm_device_t *dev, int channel); +extern void nouveau_nv10_context_switch(struct drm_device *dev); +extern int nv10_graph_init(struct drm_device *dev); +extern void nv10_graph_takedown(struct drm_device *dev); +extern int nv10_graph_create_context(struct drm_device *dev, int channel); +extern void nv10_graph_destroy_context(struct drm_device *dev, int channel); +extern int nv10_graph_load_context(struct drm_device *dev, int channel); +extern int nv10_graph_save_context(struct drm_device *dev, int channel); /* nv20_graph.c */ -extern void nouveau_nv20_context_switch(drm_device_t *dev); -extern int nv20_graph_init(drm_device_t *dev); -extern void nv20_graph_takedown(drm_device_t *dev); -extern int nv20_graph_create_context(drm_device_t *dev, int channel); -extern void nv20_graph_destroy_context(drm_device_t *dev, int channel); -extern int nv20_graph_load_context(drm_device_t *dev, int channel); -extern int nv20_graph_save_context(drm_device_t *dev, int channel); +extern void nouveau_nv20_context_switch(struct drm_device *dev); +extern int nv20_graph_init(struct drm_device *dev); +extern void nv20_graph_takedown(struct drm_device *dev); +extern int nv20_graph_create_context(struct drm_device *dev, int channel); +extern void nv20_graph_destroy_context(struct drm_device *dev, int channel); +extern int nv20_graph_load_context(struct drm_device *dev, int channel); +extern int nv20_graph_save_context(struct drm_device *dev, int channel); /* nv30_graph.c */ -extern int nv30_graph_init(drm_device_t *dev); -extern void nv30_graph_takedown(drm_device_t *dev); -extern int nv30_graph_create_context(drm_device_t *, int channel); -extern void nv30_graph_destroy_context(drm_device_t *, int channel); -extern int nv30_graph_load_context(drm_device_t *, int channel); -extern int nv30_graph_save_context(drm_device_t *, int channel); +extern int nv30_graph_init(struct drm_device *dev); +extern void nv30_graph_takedown(struct drm_device *dev); +extern int nv30_graph_create_context(struct drm_device *, int channel); +extern void nv30_graph_destroy_context(struct drm_device *, int channel); +extern int nv30_graph_load_context(struct drm_device *, int channel); +extern int nv30_graph_save_context(struct drm_device *, int channel); /* nv40_graph.c */ -extern int nv40_graph_init(drm_device_t *); -extern void nv40_graph_takedown(drm_device_t *); -extern int nv40_graph_create_context(drm_device_t *, int channel); -extern void nv40_graph_destroy_context(drm_device_t *, int channel); -extern int nv40_graph_load_context(drm_device_t *, int channel); -extern int nv40_graph_save_context(drm_device_t *, int channel); +extern int nv40_graph_init(struct drm_device *); +extern void nv40_graph_takedown(struct drm_device *); +extern int nv40_graph_create_context(struct drm_device *, int channel); +extern void nv40_graph_destroy_context(struct drm_device *, int channel); +extern int nv40_graph_load_context(struct drm_device *, int channel); +extern int nv40_graph_save_context(struct drm_device *, int channel); /* nv50_graph.c */ -extern int nv50_graph_init(drm_device_t *); -extern void nv50_graph_takedown(drm_device_t *); -extern int nv50_graph_create_context(drm_device_t *, int channel); -extern void nv50_graph_destroy_context(drm_device_t *, int channel); -extern int nv50_graph_load_context(drm_device_t *, int channel); -extern int nv50_graph_save_context(drm_device_t *, int channel); +extern int nv50_graph_init(struct drm_device *); +extern void nv50_graph_takedown(struct drm_device *); +extern int nv50_graph_create_context(struct drm_device *, int channel); +extern void nv50_graph_destroy_context(struct drm_device *, int channel); +extern int nv50_graph_load_context(struct drm_device *, int channel); +extern int nv50_graph_save_context(struct drm_device *, int channel); /* nv04_instmem.c */ -extern int nv04_instmem_init(drm_device_t *dev); -extern void nv04_instmem_takedown(drm_device_t *dev); -extern int nv04_instmem_populate(drm_device_t*, nouveau_gpuobj_t*, +extern int nv04_instmem_init(struct drm_device *dev); +extern void nv04_instmem_takedown(struct drm_device *dev); +extern int nv04_instmem_populate(struct drm_device*, struct nouveau_gpuobj*, uint32_t *size); -extern void nv04_instmem_clear(drm_device_t*, nouveau_gpuobj_t*); -extern int nv04_instmem_bind(drm_device_t*, nouveau_gpuobj_t*); -extern int nv04_instmem_unbind(drm_device_t*, nouveau_gpuobj_t*); +extern void nv04_instmem_clear(struct drm_device*, struct nouveau_gpuobj*); +extern int nv04_instmem_bind(struct drm_device*, struct nouveau_gpuobj*); +extern int nv04_instmem_unbind(struct drm_device*, struct nouveau_gpuobj*); /* nv50_instmem.c */ -extern int nv50_instmem_init(drm_device_t *dev); -extern void nv50_instmem_takedown(drm_device_t *dev); -extern int nv50_instmem_populate(drm_device_t*, nouveau_gpuobj_t*, +extern int nv50_instmem_init(struct drm_device *dev); +extern void nv50_instmem_takedown(struct drm_device *dev); +extern int nv50_instmem_populate(struct drm_device*, struct nouveau_gpuobj*, uint32_t *size); -extern void nv50_instmem_clear(drm_device_t*, nouveau_gpuobj_t*); -extern int nv50_instmem_bind(drm_device_t*, nouveau_gpuobj_t*); -extern int nv50_instmem_unbind(drm_device_t*, nouveau_gpuobj_t*); +extern void nv50_instmem_clear(struct drm_device*, struct nouveau_gpuobj*); +extern int nv50_instmem_bind(struct drm_device*, struct nouveau_gpuobj*); +extern int nv50_instmem_unbind(struct drm_device*, struct nouveau_gpuobj*); /* nv04_mc.c */ -extern int nv04_mc_init(drm_device_t *dev); -extern void nv04_mc_takedown(drm_device_t *dev); +extern int nv04_mc_init(struct drm_device *dev); +extern void nv04_mc_takedown(struct drm_device *dev); /* nv40_mc.c */ -extern int nv40_mc_init(drm_device_t *dev); -extern void nv40_mc_takedown(drm_device_t *dev); +extern int nv40_mc_init(struct drm_device *dev); +extern void nv40_mc_takedown(struct drm_device *dev); /* nv50_mc.c */ -extern int nv50_mc_init(drm_device_t *dev); -extern void nv50_mc_takedown(drm_device_t *dev); +extern int nv50_mc_init(struct drm_device *dev); +extern void nv50_mc_takedown(struct drm_device *dev); /* nv04_timer.c */ -extern int nv04_timer_init(drm_device_t *dev); -extern void nv04_timer_takedown(drm_device_t *dev); +extern int nv04_timer_init(struct drm_device *dev); +extern void nv04_timer_takedown(struct drm_device *dev); extern long nouveau_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 7114a931..c769f58f 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -29,9 +29,9 @@ /* returns the number of hw fifos */ -int nouveau_fifo_number(drm_device_t* dev) +int nouveau_fifo_number(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv=dev->dev_private; + struct drm_nouveau_private *dev_priv=dev->dev_private; switch(dev_priv->card_type) { case NV_03: @@ -47,9 +47,9 @@ int nouveau_fifo_number(drm_device_t* dev) } /* returns the size of fifo context */ -int nouveau_fifo_ctx_size(drm_device_t* dev) +int nouveau_fifo_ctx_size(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv=dev->dev_private; + struct drm_nouveau_private *dev_priv=dev->dev_private; if (dev_priv->card_type >= NV_40) return 128; @@ -68,9 +68,9 @@ int nouveau_fifo_ctx_size(drm_device_t* dev) * voir nv_driver.c : NVPreInit */ -static int nouveau_fifo_instmem_configure(drm_device_t *dev) +static int nouveau_fifo_instmem_configure(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; NV_WRITE(NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | @@ -109,9 +109,9 @@ static int nouveau_fifo_instmem_configure(drm_device_t *dev) return 0; } -int nouveau_fifo_init(drm_device_t *dev) +int nouveau_fifo_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & @@ -187,12 +187,12 @@ int nouveau_fifo_init(drm_device_t *dev) static int nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; struct nouveau_config *config = &dev_priv->config; struct mem_block *cb; int cb_min_size = max(NV03_FIFO_SIZE,PAGE_SIZE); - nouveau_gpuobj_t *pushbuf = NULL; + struct nouveau_gpuobj *pushbuf = NULL; int ret; /* Defaults for unconfigured values */ @@ -258,12 +258,12 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) } /* allocates and initializes a fifo for user space consumption */ -int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp, +int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret, DRMFILE filp, uint32_t vram_handle, uint32_t tt_handle) { int ret; - drm_nouveau_private_t *dev_priv = dev->dev_private; - nouveau_engine_func_t *engine = &dev_priv->Engine; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_engine_func *engine = &dev_priv->Engine; struct nouveau_fifo *chan; int channel; @@ -392,10 +392,10 @@ int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp, } /* stops a fifo */ -void nouveau_fifo_free(drm_device_t* dev, int channel) +void nouveau_fifo_free(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; - nouveau_engine_func_t *engine = &dev_priv->Engine; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_engine_func *engine = &dev_priv->Engine; struct nouveau_fifo *chan = dev_priv->fifos[channel]; if (!chan) { @@ -436,10 +436,10 @@ void nouveau_fifo_free(drm_device_t* dev, int channel) } /* cleanups all the fifos from filp */ -void nouveau_fifo_cleanup(drm_device_t* dev, DRMFILE filp) +void nouveau_fifo_cleanup(struct drm_device *dev, DRMFILE filp) { int i; - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; DRM_DEBUG("clearing FIFO enables from filp\n"); for(i=0;idev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; if (channel >= nouveau_fifo_number(dev)) return 0; @@ -466,13 +466,14 @@ nouveau_fifo_owner(drm_device_t *dev, DRMFILE filp, int channel) static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_nouveau_private_t *dev_priv = dev->dev_private; - drm_nouveau_fifo_alloc_t init; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct drm_nouveau_fifo_alloc init; drm_map_list_t *entry; struct nouveau_fifo *chan; int res; - DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_fifo_alloc_t __user *) data, + DRM_COPY_FROM_USER_IOCTL(init, + (struct drm_nouveau_fifo_alloc __user *) data, sizeof(init)); if (init.fb_ctxdma_handle == ~0 || init.tt_ctxdma_handle == ~0) @@ -515,7 +516,7 @@ static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) init.notifier = chan->notifier_block->map_handle; init.notifier_size = chan->notifier_block->size; - DRM_COPY_TO_USER_IOCTL((drm_nouveau_fifo_alloc_t __user *)data, + DRM_COPY_TO_USER_IOCTL((struct drm_nouveau_fifo_alloc __user *)data, init, sizeof(init)); return 0; } diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index b4102dd8..451262a1 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -36,9 +36,9 @@ #include "nouveau_drv.h" #include "nouveau_reg.h" -void nouveau_irq_preinstall(drm_device_t *dev) +void nouveau_irq_preinstall(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; DRM_DEBUG("IRQ: preinst\n"); @@ -71,9 +71,9 @@ void nouveau_irq_preinstall(drm_device_t *dev) NV_WRITE(NV03_PMC_INTR_EN_0, 0); } -void nouveau_irq_postinstall(drm_device_t *dev) +void nouveau_irq_postinstall(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; if (!dev_priv) { DRM_ERROR("AIII, no dev_priv\n"); @@ -107,9 +107,9 @@ void nouveau_irq_postinstall(drm_device_t *dev) NV_WRITE(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE); } -void nouveau_irq_uninstall(drm_device_t *dev) +void nouveau_irq_uninstall(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; if (!dev_priv) { DRM_ERROR("AIII, no dev_priv\n"); @@ -138,10 +138,10 @@ void nouveau_irq_uninstall(drm_device_t *dev) NV_WRITE(NV03_PMC_INTR_EN_0, 0); } -static void nouveau_fifo_irq_handler(drm_device_t *dev) +static void nouveau_fifo_irq_handler(struct drm_device *dev) { uint32_t status, chmode, chstat, channel; - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; status = NV_READ(NV03_PFIFO_INTR_0); if (!status) @@ -200,9 +200,9 @@ static void nouveau_fifo_irq_handler(drm_device_t *dev) } #if 0 -static void nouveau_nv04_context_switch(drm_device_t *dev) +static void nouveau_nv04_context_switch(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t channel,i; uint32_t max=0; NV_WRITE(NV04_PGRAPH_FIFO,0x0); @@ -247,9 +247,9 @@ static void nouveau_nv04_context_switch(drm_device_t *dev) #endif static void -nouveau_graph_dump_trap_info(drm_device_t *dev) +nouveau_graph_dump_trap_info(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t address; uint32_t channel, class; uint32_t method, subc, data; @@ -273,10 +273,10 @@ nouveau_graph_dump_trap_info(drm_device_t *dev) ); } -static void nouveau_pgraph_irq_handler(drm_device_t *dev) +static void nouveau_pgraph_irq_handler(struct drm_device *dev) { uint32_t status; - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; status = NV_READ(NV03_PGRAPH_INTR); if (!status) @@ -379,9 +379,9 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev) NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING); } -static void nouveau_crtc_irq_handler(drm_device_t *dev, int crtc) +static void nouveau_crtc_irq_handler(struct drm_device *dev, int crtc) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; if (crtc&1) { NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK); } @@ -393,8 +393,8 @@ static void nouveau_crtc_irq_handler(drm_device_t *dev, int crtc) irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS) { - drm_device_t *dev = (drm_device_t*)arg; - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_device *dev = (struct drm_device*)arg; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t status; status = NV_READ(NV03_PMC_INTR_0); diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 79d1bb87..2b2418fb 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -208,7 +208,7 @@ void nouveau_mem_takedown(struct mem_block **heap) void nouveau_mem_close(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; nouveau_mem_takedown(&dev_priv->agp_heap); nouveau_mem_takedown(&dev_priv->fb_heap); if ( dev_priv->pci_heap ) @@ -220,7 +220,7 @@ void nouveau_mem_close(struct drm_device *dev) /* returns the amount of FB ram in bytes */ uint64_t nouveau_mem_fb_amount(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv=dev->dev_private; + struct drm_nouveau_private *dev_priv=dev->dev_private; switch(dev_priv->card_type) { case NV_03: @@ -285,7 +285,7 @@ uint64_t nouveau_mem_fb_amount(struct drm_device *dev) int nouveau_mem_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t fb_size; drm_scatter_gather_t sgreq; dev_priv->agp_phys=0; @@ -405,7 +405,7 @@ struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment, uint6 { struct mem_block *block; int type; - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; /* * Make things easier on ourselves: all allocations are page-aligned. @@ -515,8 +515,8 @@ void nouveau_mem_free(struct drm_device* dev, struct mem_block* block) int nouveau_ioctl_mem_alloc(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_nouveau_private_t *dev_priv = dev->dev_private; - drm_nouveau_mem_alloc_t alloc; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct drm_nouveau_mem_alloc alloc; struct mem_block *block; if (!dev_priv) { @@ -524,7 +524,8 @@ int nouveau_ioctl_mem_alloc(DRM_IOCTL_ARGS) return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL(alloc, (drm_nouveau_mem_alloc_t __user *) data, + DRM_COPY_FROM_USER_IOCTL(alloc, + (struct drm_nouveau_mem_alloc_t __user *) data, sizeof(alloc)); block=nouveau_mem_alloc(dev, alloc.alignment, alloc.size, alloc.flags, filp); @@ -534,7 +535,8 @@ int nouveau_ioctl_mem_alloc(DRM_IOCTL_ARGS) alloc.offset=block->start; alloc.flags=block->flags; - DRM_COPY_TO_USER_IOCTL((drm_nouveau_mem_alloc_t __user *) data, alloc, sizeof(alloc)); + DRM_COPY_TO_USER_IOCTL((struct drm_nouveau_mem_alloc __user *)data, + alloc, sizeof(alloc)); return 0; } @@ -542,11 +544,12 @@ int nouveau_ioctl_mem_alloc(DRM_IOCTL_ARGS) int nouveau_ioctl_mem_free(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_nouveau_private_t *dev_priv = dev->dev_private; - drm_nouveau_mem_free_t memfree; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct drm_nouveau_mem_free memfree; struct mem_block *block; - DRM_COPY_FROM_USER_IOCTL(memfree, (drm_nouveau_mem_free_t __user *) data, + DRM_COPY_FROM_USER_IOCTL(memfree, + (struct drm_nouveau_mem_free_t __user *)data, sizeof(memfree)); block=NULL; diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index 7d892064..36dba654 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -30,9 +30,9 @@ #include "nouveau_drv.h" int -nouveau_notifier_init_channel(drm_device_t *dev, int channel, DRMFILE filp) +nouveau_notifier_init_channel(struct drm_device *dev, int channel, DRMFILE filp) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; int flags, ret; @@ -56,9 +56,9 @@ nouveau_notifier_init_channel(drm_device_t *dev, int channel, DRMFILE filp) } void -nouveau_notifier_takedown_channel(drm_device_t *dev, int channel) +nouveau_notifier_takedown_channel(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; if (chan->notifier_block) { @@ -70,12 +70,12 @@ nouveau_notifier_takedown_channel(drm_device_t *dev, int channel) } int -nouveau_notifier_alloc(drm_device_t *dev, int channel, uint32_t handle, +nouveau_notifier_alloc(struct drm_device *dev, int channel, uint32_t handle, int count, uint32_t *b_offset) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; - nouveau_gpuobj_t *nobj = NULL; + struct nouveau_gpuobj *nobj = NULL; struct mem_block *mem; uint32_t offset; int target, ret; @@ -127,11 +127,12 @@ int nouveau_ioctl_notifier_alloc(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_nouveau_notifier_alloc_t na; + struct drm_nouveau_notifier_alloc na; int ret; - DRM_COPY_FROM_USER_IOCTL(na, (drm_nouveau_notifier_alloc_t __user*)data, - sizeof(na)); + DRM_COPY_FROM_USER_IOCTL(na, + (struct drm_nouveau_notifier_alloc __user*)data, + sizeof(na)); if (!nouveau_fifo_owner(dev, filp, na.channel)) { DRM_ERROR("pid %d doesn't own channel %d\n", @@ -144,7 +145,7 @@ nouveau_ioctl_notifier_alloc(DRM_IOCTL_ARGS) if (ret) return ret; - DRM_COPY_TO_USER_IOCTL((drm_nouveau_notifier_alloc_t __user*)data, + DRM_COPY_TO_USER_IOCTL((struct drm_nouveau_notifier_alloc __user*)data, na, sizeof(na)); return 0; } diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 16b38e95..c5697d8e 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -66,9 +66,9 @@ is given as: */ static uint32_t -nouveau_ramht_hash_handle(drm_device_t *dev, int channel, uint32_t handle) +nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle) { - drm_nouveau_private_t *dev_priv=dev->dev_private; + struct drm_nouveau_private *dev_priv=dev->dev_private; uint32_t hash = 0; int i; @@ -85,10 +85,10 @@ nouveau_ramht_hash_handle(drm_device_t *dev, int channel, uint32_t handle) } static int -nouveau_ramht_entry_valid(drm_device_t *dev, nouveau_gpuobj_t *ramht, +nouveau_ramht_entry_valid(struct drm_device *dev, struct nouveau_gpuobj *ramht, uint32_t offset) { - drm_nouveau_private_t *dev_priv=dev->dev_private; + struct drm_nouveau_private *dev_priv=dev->dev_private; uint32_t ctx = INSTANCE_RD(ramht, (offset + 4)/4); if (dev_priv->card_type < NV_40) @@ -97,12 +97,12 @@ nouveau_ramht_entry_valid(drm_device_t *dev, nouveau_gpuobj_t *ramht, } static int -nouveau_ramht_insert(drm_device_t* dev, nouveau_gpuobj_ref_t *ref) +nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) { - drm_nouveau_private_t *dev_priv=dev->dev_private; + struct drm_nouveau_private *dev_priv=dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[ref->channel]; - nouveau_gpuobj_t *ramht = chan->ramht ? chan->ramht->gpuobj : NULL; - nouveau_gpuobj_t *gpuobj = ref->gpuobj; + struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL; + struct nouveau_gpuobj *gpuobj = ref->gpuobj; uint32_t ctx, co, ho; if (!ramht) { @@ -146,11 +146,11 @@ nouveau_ramht_insert(drm_device_t* dev, nouveau_gpuobj_ref_t *ref) } static void -nouveau_ramht_remove(drm_device_t* dev, nouveau_gpuobj_ref_t *ref) +nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[ref->channel]; - nouveau_gpuobj_t *ramht = chan->ramht ? chan->ramht->gpuobj : NULL; + struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL; uint32_t co, ho; if (!ramht) { @@ -180,13 +180,13 @@ nouveau_ramht_remove(drm_device_t* dev, nouveau_gpuobj_ref_t *ref) } int -nouveau_gpuobj_new(drm_device_t *dev, int channel, int size, int align, - uint32_t flags, nouveau_gpuobj_t **gpuobj_ret) +nouveau_gpuobj_new(struct drm_device *dev, int channel, int size, int align, + uint32_t flags, struct nouveau_gpuobj **gpuobj_ret) { - drm_nouveau_private_t *dev_priv = dev->dev_private; - nouveau_engine_func_t *engine = &dev_priv->Engine; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_engine_func *engine = &dev_priv->Engine; struct nouveau_fifo *chan = NULL; - nouveau_gpuobj_t *gpuobj; + struct nouveau_gpuobj *gpuobj; struct mem_block *pramin = NULL; int ret; @@ -270,10 +270,10 @@ nouveau_gpuobj_new(drm_device_t *dev, int channel, int size, int align, return 0; } -void nouveau_gpuobj_takedown(drm_device_t *dev) +void nouveau_gpuobj_takedown(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; - nouveau_gpuobj_t *gpuobj = NULL; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_gpuobj *gpuobj = NULL; DRM_DEBUG("\n"); @@ -285,11 +285,11 @@ void nouveau_gpuobj_takedown(drm_device_t *dev) } } -int nouveau_gpuobj_del(drm_device_t *dev, nouveau_gpuobj_t **pgpuobj) +int nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj) { - drm_nouveau_private_t *dev_priv = dev->dev_private; - nouveau_engine_func_t *engine = &dev_priv->Engine; - nouveau_gpuobj_t *gpuobj; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_engine_func *engine = &dev_priv->Engine; + struct nouveau_gpuobj *gpuobj; DRM_DEBUG("gpuobj %p\n", pgpuobj ? *pgpuobj : NULL); @@ -325,11 +325,11 @@ int nouveau_gpuobj_del(drm_device_t *dev, nouveau_gpuobj_t **pgpuobj) } static int -nouveau_gpuobj_instance_get(drm_device_t *dev, int channel, - nouveau_gpuobj_t *gpuobj, uint32_t *inst) +nouveau_gpuobj_instance_get(struct drm_device *dev, int channel, + struct nouveau_gpuobj *gpuobj, uint32_t *inst) { - drm_nouveau_private_t *dev_priv = dev->dev_private; - nouveau_gpuobj_t *cpramin; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_gpuobj *cpramin; /* card_type < NV_50) { @@ -371,12 +371,12 @@ nouveau_gpuobj_instance_get(drm_device_t *dev, int channel, } int -nouveau_gpuobj_ref_add(drm_device_t *dev, int channel, uint32_t handle, - nouveau_gpuobj_t *gpuobj, nouveau_gpuobj_ref_t **ref_ret) +nouveau_gpuobj_ref_add(struct drm_device *dev, int channel, uint32_t handle, + struct nouveau_gpuobj *gpuobj, struct nouveau_gpuobj_ref **ref_ret) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = NULL; - nouveau_gpuobj_ref_t *ref; + struct nouveau_gpuobj_ref *ref; uint32_t instance; int ret; @@ -424,9 +424,9 @@ nouveau_gpuobj_ref_add(drm_device_t *dev, int channel, uint32_t handle, return 0; } -int nouveau_gpuobj_ref_del(drm_device_t *dev, nouveau_gpuobj_ref_t **pref) +int nouveau_gpuobj_ref_del(struct drm_device *dev, struct nouveau_gpuobj_ref **pref) { - nouveau_gpuobj_ref_t *ref; + struct nouveau_gpuobj_ref *ref; DRM_DEBUG("ref %p\n", pref ? *pref : NULL); @@ -452,11 +452,11 @@ int nouveau_gpuobj_ref_del(drm_device_t *dev, nouveau_gpuobj_ref_t **pref) } int -nouveau_gpuobj_new_ref(drm_device_t *dev, int oc, int rc, uint32_t handle, +nouveau_gpuobj_new_ref(struct drm_device *dev, int oc, int rc, uint32_t handle, int size, int align, uint32_t flags, - nouveau_gpuobj_ref_t **ref) + struct nouveau_gpuobj_ref **ref) { - nouveau_gpuobj_t *gpuobj = NULL; + struct nouveau_gpuobj *gpuobj = NULL; int ret; if ((ret = nouveau_gpuobj_new(dev, oc, size, align, flags, &gpuobj))) @@ -471,12 +471,12 @@ nouveau_gpuobj_new_ref(drm_device_t *dev, int oc, int rc, uint32_t handle, } static int -nouveau_gpuobj_ref_find(drm_device_t *dev, int channel, uint32_t handle, - nouveau_gpuobj_ref_t **ref_ret) +nouveau_gpuobj_ref_find(struct drm_device *dev, int channel, uint32_t handle, + struct nouveau_gpuobj_ref **ref_ret) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; - nouveau_gpuobj_ref_t *ref = chan->ramht_refs; + struct nouveau_gpuobj_ref *ref = chan->ramht_refs; while (ref) { if (ref->handle == handle) { @@ -491,12 +491,12 @@ nouveau_gpuobj_ref_find(drm_device_t *dev, int channel, uint32_t handle, } int -nouveau_gpuobj_new_fake(drm_device_t *dev, uint32_t offset, uint32_t size, - uint32_t flags, nouveau_gpuobj_t **pgpuobj, - nouveau_gpuobj_ref_t **pref) +nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t offset, uint32_t size, + uint32_t flags, struct nouveau_gpuobj **pgpuobj, + struct nouveau_gpuobj_ref **pref) { - drm_nouveau_private_t *dev_priv = dev->dev_private; - nouveau_gpuobj_t *gpuobj = NULL; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_gpuobj *gpuobj = NULL; int i; DRM_DEBUG("offset=0x%08x size=0x%08x flags=0x%08x\n", @@ -537,9 +537,9 @@ nouveau_gpuobj_new_fake(drm_device_t *dev, uint32_t offset, uint32_t size, static int -nouveau_gpuobj_class_instmem_size(drm_device_t *dev, int class) +nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; /*XXX: dodgy hack for now */ if (dev_priv->card_type >= NV_50) @@ -577,11 +577,11 @@ nouveau_gpuobj_class_instmem_size(drm_device_t *dev, int class) to it that can be used to set up context objects. */ int -nouveau_gpuobj_dma_new(drm_device_t *dev, int channel, int class, +nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class, uint64_t offset, uint64_t size, int access, int target, - nouveau_gpuobj_t **gpuobj) + struct nouveau_gpuobj **gpuobj) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; uint32_t is_scatter_gather = 0; @@ -755,10 +755,10 @@ nouveau_gpuobj_dma_new(drm_device_t *dev, int channel, int class, set to 0? */ int -nouveau_gpuobj_gr_new(drm_device_t *dev, int channel, int class, - nouveau_gpuobj_t **gpuobj) +nouveau_gpuobj_gr_new(struct drm_device *dev, int channel, int class, + struct nouveau_gpuobj **gpuobj) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; DRM_DEBUG("ch%d class=0x%04x\n", channel, class); @@ -804,11 +804,11 @@ nouveau_gpuobj_gr_new(drm_device_t *dev, int channel, int class, } static int -nouveau_gpuobj_channel_init_pramin(drm_device_t *dev, int channel) +nouveau_gpuobj_channel_init_pramin(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; - nouveau_gpuobj_t *pramin = NULL; + struct nouveau_gpuobj *pramin = NULL; int size, base, ret; DRM_DEBUG("ch%d\n", channel); @@ -854,12 +854,12 @@ nouveau_gpuobj_channel_init_pramin(drm_device_t *dev, int channel) } int -nouveau_gpuobj_channel_init(drm_device_t *dev, int channel, +nouveau_gpuobj_channel_init(struct drm_device *dev, int channel, uint32_t vram_h, uint32_t tt_h) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; - nouveau_gpuobj_t *vram = NULL, *tt = NULL; + struct nouveau_gpuobj *vram = NULL, *tt = NULL; int ret; DRM_DEBUG("ch%d vram=0x%08x tt=0x%08x\n", channel, vram_h, tt_h); @@ -940,11 +940,11 @@ nouveau_gpuobj_channel_init(drm_device_t *dev, int channel, } void -nouveau_gpuobj_channel_takedown(drm_device_t *dev, int channel) +nouveau_gpuobj_channel_takedown(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; - nouveau_gpuobj_ref_t *ref; + struct nouveau_gpuobj_ref *ref; DRM_DEBUG("ch%d\n", channel); @@ -964,12 +964,13 @@ nouveau_gpuobj_channel_takedown(drm_device_t *dev, int channel) int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_nouveau_grobj_alloc_t init; - nouveau_gpuobj_t *gr = NULL; + struct drm_nouveau_grobj_alloc init; + struct nouveau_gpuobj *gr = NULL; int ret; - DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_grobj_alloc_t __user *) - data, sizeof(init)); + DRM_COPY_FROM_USER_IOCTL(init, + (struct drm_nouveau_grobj_alloc_t __user*)data, + sizeof(init)); if (!nouveau_fifo_owner(dev, filp, init.channel)) { DRM_ERROR("pid %d doesn't own channel %d\n", diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index fe3db168..69e9c221 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -28,9 +28,9 @@ #include "nouveau_drv.h" #include "nouveau_drm.h" -static int nouveau_init_card_mappings(drm_device_t *dev) +static int nouveau_init_card_mappings(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; /* resource 0 is mmio regs */ @@ -86,11 +86,11 @@ static int nouveau_init_card_mappings(drm_device_t *dev) return 0; } -static int nouveau_stub_init(drm_device_t *dev) { return 0; } -static void nouveau_stub_takedown(drm_device_t *dev) {} -static int nouveau_init_engine_ptrs(drm_device_t *dev) +static int nouveau_stub_init(struct drm_device *dev) { return 0; } +static void nouveau_stub_takedown(struct drm_device *dev) {} +static int nouveau_init_engine_ptrs(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_engine_func *engine = &dev_priv->Engine; switch (dev_priv->chipset & 0xf0) { @@ -259,9 +259,9 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev) return 0; } -static int nouveau_card_init(drm_device_t *dev) +static int nouveau_card_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_engine_func *engine; int ret; @@ -321,10 +321,10 @@ static int nouveau_card_init(drm_device_t *dev) return 0; } -static void nouveau_card_takedown(drm_device_t *dev) +static void nouveau_card_takedown(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; - nouveau_engine_func_t *engine = &dev_priv->Engine; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_engine_func *engine = &dev_priv->Engine; if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) { engine->fifo.takedown(dev); @@ -341,9 +341,9 @@ static void nouveau_card_takedown(drm_device_t *dev) } /* here a client dies, release the stuff that was allocated for its filp */ -void nouveau_preclose(drm_device_t * dev, DRMFILE filp) +void nouveau_preclose(struct drm_device *dev, DRMFILE filp) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; nouveau_fifo_cleanup(dev, filp); nouveau_mem_release(filp,dev_priv->fb_heap); @@ -367,7 +367,7 @@ int nouveau_firstopen(struct drm_device *dev) int nouveau_load(struct drm_device *dev, unsigned long flags) { - drm_nouveau_private_t *dev_priv; + struct drm_nouveau_private *dev_priv; if (flags==NV_UNKNOWN) return DRM_ERR(EINVAL); @@ -395,7 +395,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) void nouveau_lastclose(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; nouveau_card_takedown(dev); @@ -416,11 +416,12 @@ int nouveau_unload(struct drm_device *dev) int nouveau_ioctl_getparam(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_nouveau_private_t *dev_priv = dev->dev_private; - drm_nouveau_getparam_t getparam; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct drm_nouveau_getparam getparam; - DRM_COPY_FROM_USER_IOCTL(getparam, (drm_nouveau_getparam_t __user *)data, - sizeof(getparam)); + DRM_COPY_FROM_USER_IOCTL(getparam, + (struct drm_nouveau_getparam __user *)data, + sizeof(getparam)); switch (getparam.param) { case NOUVEAU_GETPARAM_PCI_VENDOR: @@ -463,19 +464,20 @@ int nouveau_ioctl_getparam(DRM_IOCTL_ARGS) return DRM_ERR(EINVAL); } - DRM_COPY_TO_USER_IOCTL((drm_nouveau_getparam_t __user *)data, getparam, - sizeof(getparam)); + DRM_COPY_TO_USER_IOCTL((struct drm_nouveau_getparam __user *)data, + getparam, sizeof(getparam)); return 0; } int nouveau_ioctl_setparam(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_nouveau_private_t *dev_priv = dev->dev_private; - drm_nouveau_setparam_t setparam; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct drm_nouveau_setparam setparam; - DRM_COPY_FROM_USER_IOCTL(setparam, (drm_nouveau_setparam_t __user *)data, - sizeof(setparam)); + DRM_COPY_FROM_USER_IOCTL(setparam, + (struct drm_nouveau_setparam __user *)data, + sizeof(setparam)); switch (setparam.param) { case NOUVEAU_SETPARAM_CMDBUF_LOCATION: @@ -506,7 +508,7 @@ int nouveau_ioctl_setparam(DRM_IOCTL_ARGS) /* waits for idle */ void nouveau_wait_for_idle(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv=dev->dev_private; + struct drm_nouveau_private *dev_priv=dev->dev_private; switch(dev_priv->card_type) { case NV_03: diff --git a/shared-core/nv04_fb.c b/shared-core/nv04_fb.c index 06b1c994..534fb50b 100644 --- a/shared-core/nv04_fb.c +++ b/shared-core/nv04_fb.c @@ -4,9 +4,9 @@ #include "nouveau_drm.h" int -nv04_fb_init(drm_device_t *dev) +nv04_fb_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; /* This is what the DDX did for NV_ARCH_04, but a mmio-trace shows * nvidia reading PFB_CFG_0, then writing back its original value. @@ -18,7 +18,7 @@ nv04_fb_init(drm_device_t *dev) } void -nv04_fb_takedown(drm_device_t *dev) +nv04_fb_takedown(struct drm_device *dev) { } diff --git a/shared-core/nv04_fifo.c b/shared-core/nv04_fifo.c index e2e934d7..564efd0b 100644 --- a/shared-core/nv04_fifo.c +++ b/shared-core/nv04_fifo.c @@ -36,9 +36,9 @@ #define NV04_RAMFC__SIZE 32 int -nv04_fifo_create_context(drm_device_t *dev, int channel) +nv04_fifo_create_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; int ret; @@ -67,9 +67,9 @@ nv04_fifo_create_context(drm_device_t *dev, int channel) } void -nv04_fifo_destroy_context(drm_device_t *dev, int channel) +nv04_fifo_destroy_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; @@ -107,9 +107,9 @@ nv04_fifo_load_context(drm_device_t *dev, int channel) } int -nv04_fifo_save_context(drm_device_t *dev, int channel) +nv04_fifo_save_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c index df23d279..e35e3071 100644 --- a/shared-core/nv04_graph.c +++ b/shared-core/nv04_graph.c @@ -287,9 +287,9 @@ struct reg_interval }; -void nouveau_nv04_context_switch(drm_device_t *dev) +void nouveau_nv04_context_switch(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int channel, channel_old, i, j, index; channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); @@ -336,8 +336,8 @@ void nouveau_nv04_context_switch(drm_device_t *dev) NV_WRITE(NV04_PGRAPH_FIFO,0x1); } -int nv04_graph_create_context(drm_device_t *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; +int nv04_graph_create_context(struct drm_device *dev, int channel) { + struct drm_nouveau_private *dev_priv = dev->dev_private; DRM_DEBUG("nv04_graph_context_create %d\n", channel); memset(dev_priv->fifos[channel]->pgraph_ctx, 0, sizeof(dev_priv->fifos[channel]->pgraph_ctx)); @@ -351,24 +351,24 @@ int nv04_graph_create_context(drm_device_t *dev, int channel) { return 0; } -void nv04_graph_destroy_context(drm_device_t *dev, int channel) +void nv04_graph_destroy_context(struct drm_device *dev, int channel) { } -int nv04_graph_load_context(drm_device_t *dev, int channel) +int nv04_graph_load_context(struct drm_device *dev, int channel) { DRM_ERROR("stub!\n"); return 0; } -int nv04_graph_save_context(drm_device_t *dev, int channel) +int nv04_graph_save_context(struct drm_device *dev, int channel) { DRM_ERROR("stub!\n"); return 0; } -int nv04_graph_init(drm_device_t *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; +int nv04_graph_init(struct drm_device *dev) { + struct drm_nouveau_private *dev_priv = dev->dev_private; int i,sum=0; NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & @@ -406,7 +406,7 @@ int nv04_graph_init(drm_device_t *dev) { return 0; } -void nv04_graph_takedown(drm_device_t *dev) +void nv04_graph_takedown(struct drm_device *dev) { } diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index ac7d4347..fc3b116d 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -5,7 +5,7 @@ static void nv04_instmem_determine_amount(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int i; /* Figure out how much instance memory we need */ @@ -35,7 +35,7 @@ nv04_instmem_determine_amount(struct drm_device *dev) static void nv04_instmem_configure_fixed_tables(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; /* FIFO hash table (RAMHT) * use 4k hash table at RAMIN+0x10000 @@ -85,7 +85,7 @@ nv04_instmem_configure_fixed_tables(struct drm_device *dev) int nv04_instmem_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t offset; int ret = 0; @@ -114,15 +114,15 @@ int nv04_instmem_init(struct drm_device *dev) } void -nv04_instmem_takedown(drm_device_t *dev) +nv04_instmem_takedown(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; nouveau_gpuobj_del(dev, &dev_priv->ramht); } int -nv04_instmem_populate(drm_device_t *dev, nouveau_gpuobj_t *gpuobj, uint32_t *sz) +nv04_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz) { if (gpuobj->im_backing) return DRM_ERR(EINVAL); @@ -131,9 +131,9 @@ nv04_instmem_populate(drm_device_t *dev, nouveau_gpuobj_t *gpuobj, uint32_t *sz) } void -nv04_instmem_clear(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +nv04_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; if (gpuobj && gpuobj->im_backing) { if (gpuobj->im_bound) @@ -144,7 +144,7 @@ nv04_instmem_clear(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) } int -nv04_instmem_bind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +nv04_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { if (!gpuobj->im_pramin || gpuobj->im_bound) return DRM_ERR(EINVAL); @@ -154,7 +154,7 @@ nv04_instmem_bind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) } int -nv04_instmem_unbind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +nv04_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { if (gpuobj->im_bound == 0) return DRM_ERR(EINVAL); diff --git a/shared-core/nv04_mc.c b/shared-core/nv04_mc.c index 0e23efb2..1d998851 100644 --- a/shared-core/nv04_mc.c +++ b/shared-core/nv04_mc.c @@ -4,9 +4,9 @@ #include "nouveau_drm.h" int -nv04_mc_init(drm_device_t *dev) +nv04_mc_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; /* Power up everything, resetting each individual unit will * be done later if needed. @@ -19,7 +19,7 @@ nv04_mc_init(drm_device_t *dev) } void -nv04_mc_takedown(drm_device_t *dev) +nv04_mc_takedown(struct drm_device *dev) { } diff --git a/shared-core/nv04_timer.c b/shared-core/nv04_timer.c index a4b4e826..efe78da7 100644 --- a/shared-core/nv04_timer.c +++ b/shared-core/nv04_timer.c @@ -4,9 +4,9 @@ #include "nouveau_drm.h" int -nv04_timer_init(drm_device_t *dev) +nv04_timer_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; NV_WRITE(NV04_PTIMER_INTR_EN_0, 0x00000000); NV_WRITE(NV04_PTIMER_INTR_0, 0xFFFFFFFF); @@ -18,7 +18,7 @@ nv04_timer_init(drm_device_t *dev) } void -nv04_timer_takedown(drm_device_t *dev) +nv04_timer_takedown(struct drm_device *dev) { } diff --git a/shared-core/nv10_fb.c b/shared-core/nv10_fb.c index e8336a2d..7fff5b3f 100644 --- a/shared-core/nv10_fb.c +++ b/shared-core/nv10_fb.c @@ -4,9 +4,9 @@ #include "nouveau_drm.h" int -nv10_fb_init(drm_device_t *dev) +nv10_fb_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t fb_bar_size; int i; @@ -20,7 +20,7 @@ nv10_fb_init(drm_device_t *dev) } void -nv10_fb_takedown(drm_device_t *dev) +nv10_fb_takedown(struct drm_device *dev) { } diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c index 2d8d5a0d..7b9c665b 100644 --- a/shared-core/nv10_fifo.c +++ b/shared-core/nv10_fifo.c @@ -37,9 +37,9 @@ #define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32) int -nv10_fifo_create_context(drm_device_t *dev, int channel) +nv10_fifo_create_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; int ret; @@ -70,9 +70,9 @@ nv10_fifo_create_context(drm_device_t *dev, int channel) } void -nv10_fifo_destroy_context(drm_device_t *dev, int channel) +nv10_fifo_destroy_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; @@ -124,9 +124,9 @@ nv10_fifo_load_context(drm_device_t *dev, int channel) } int -nv10_fifo_save_context(drm_device_t *dev, int channel) +nv10_fifo_save_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index c544afac..930fcbdf 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -28,8 +28,8 @@ #include "nouveau_drv.h" -static void nv10_praph_pipe(drm_device_t *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; +static void nv10_praph_pipe(struct drm_device *dev) { + struct drm_nouveau_private *dev_priv = dev->dev_private; int i; nouveau_wait_for_idle(dev); @@ -527,9 +527,9 @@ NV10_PGRAPH_DEBUG_4, 0x00400a04, }; -static int nv10_graph_ctx_regs_find_offset(drm_device_t *dev, int reg) +static int nv10_graph_ctx_regs_find_offset(struct drm_device *dev, int reg) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int i, j; for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) { if (nv10_graph_ctx_regs[i] == reg) @@ -544,9 +544,9 @@ static int nv10_graph_ctx_regs_find_offset(drm_device_t *dev, int reg) return -1; } -static void restore_ctx_regs(drm_device_t *dev, int channel) +static void restore_ctx_regs(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *fifo = dev_priv->fifos[channel]; int i, j; for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) @@ -558,9 +558,9 @@ static void restore_ctx_regs(drm_device_t *dev, int channel) nouveau_wait_for_idle(dev); } -void nouveau_nv10_context_switch(drm_device_t *dev) +void nouveau_nv10_context_switch(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int channel, channel_old, i, j; channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); @@ -611,8 +611,8 @@ void nouveau_nv10_context_switch(drm_device_t *dev) if (offset > 0) \ fifo->pgraph_ctx[offset] = val; \ } while (0) -int nv10_graph_create_context(drm_device_t *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; +int nv10_graph_create_context(struct drm_device *dev, int channel) { + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *fifo = dev_priv->fifos[channel]; uint32_t tmp, vramsz; @@ -663,24 +663,24 @@ int nv10_graph_create_context(drm_device_t *dev, int channel) { return 0; } -void nv10_graph_destroy_context(drm_device_t *dev, int channel) +void nv10_graph_destroy_context(struct drm_device *dev, int channel) { } -int nv10_graph_load_context(drm_device_t *dev, int channel) +int nv10_graph_load_context(struct drm_device *dev, int channel) { DRM_ERROR("stub!\n"); return 0; } -int nv10_graph_save_context(drm_device_t *dev, int channel) +int nv10_graph_save_context(struct drm_device *dev, int channel) { DRM_ERROR("stub!\n"); return 0; } -int nv10_graph_init(drm_device_t *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; +int nv10_graph_init(struct drm_device *dev) { + struct drm_nouveau_private *dev_priv = dev->dev_private; int i; NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & @@ -714,7 +714,7 @@ int nv10_graph_init(drm_device_t *dev) { return 0; } -void nv10_graph_takedown(drm_device_t *dev) +void nv10_graph_takedown(struct drm_device *dev) { } diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 06d7e440..e6aa1e2a 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -29,9 +29,9 @@ #define NV20_GRCTX_SIZE (3529*4) -int nv20_graph_create_context(drm_device_t *dev, int channel) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; +int nv20_graph_create_context(struct drm_device *dev, int channel) { + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; unsigned int ctx_size = NV20_GRCTX_SIZE; int ret; @@ -49,8 +49,8 @@ int nv20_graph_create_context(drm_device_t *dev, int channel) { return 0; } -void nv20_graph_destroy_context(drm_device_t *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; +void nv20_graph_destroy_context(struct drm_device *dev, int channel) { + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; if (chan->ramin_grctx) @@ -59,9 +59,9 @@ void nv20_graph_destroy_context(drm_device_t *dev, int channel) { INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, 0); } -static void nv20_graph_rdi(drm_device_t *dev) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; +static void nv20_graph_rdi(struct drm_device *dev) { + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; int i; NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000); @@ -73,9 +73,9 @@ static void nv20_graph_rdi(drm_device_t *dev) { /* Save current context (from PGRAPH) into the channel's context */ -int nv20_graph_save_context(drm_device_t *dev, int channel) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; +int nv20_graph_save_context(struct drm_device *dev, int channel) { + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t instance; @@ -94,9 +94,9 @@ int nv20_graph_save_context(drm_device_t *dev, int channel) { /* Restore the context for a specific channel into PGRAPH */ -int nv20_graph_load_context(drm_device_t *dev, int channel) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; +int nv20_graph_load_context(struct drm_device *dev, int channel) { + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t instance; @@ -113,9 +113,9 @@ int nv20_graph_load_context(drm_device_t *dev, int channel) { return 0; } -void nouveau_nv20_context_switch(drm_device_t *dev) +void nouveau_nv20_context_switch(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int channel, channel_old; channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); @@ -144,9 +144,9 @@ void nouveau_nv20_context_switch(drm_device_t *dev) NV_WRITE(NV04_PGRAPH_FIFO,0x1); } -int nv20_graph_init(drm_device_t *dev) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; +int nv20_graph_init(struct drm_device *dev) { + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; uint32_t tmp, vramsz; int ret, i; @@ -240,7 +240,7 @@ int nv20_graph_init(drm_device_t *dev) { return 0; } -void nv20_graph_takedown(drm_device_t *dev) +void nv20_graph_takedown(struct drm_device *dev) { } diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index a83ad714..23e0f7f0 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -16,9 +16,9 @@ * contexts are taken from dumps just after the 3D object is * created. */ -static void nv30_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) +static void nv30_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int i; INSTANCE_WR(ctx, 0x28/4, 0x10000000); @@ -100,12 +100,12 @@ static void nv30_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) } -int nv30_graph_create_context(drm_device_t *dev, int channel) +int nv30_graph_create_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; - void (*ctx_init)(drm_device_t *, nouveau_gpuobj_t *); + void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *); unsigned int ctx_size; int ret; @@ -131,10 +131,10 @@ int nv30_graph_create_context(drm_device_t *dev, int channel) return 0; } -void nv30_graph_destroy_context(drm_device_t *dev, int channel) +void nv30_graph_destroy_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; if (chan->ramin_grctx) @@ -144,9 +144,9 @@ void nv30_graph_destroy_context(drm_device_t *dev, int channel) } static int -nouveau_graph_wait_idle(drm_device_t *dev) +nouveau_graph_wait_idle(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int tv = 1000; while (tv--) { @@ -161,9 +161,9 @@ nouveau_graph_wait_idle(drm_device_t *dev) return 0; } -int nv30_graph_load_context(drm_device_t *dev, int channel) +int nv30_graph_load_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t inst; @@ -178,9 +178,9 @@ int nv30_graph_load_context(drm_device_t *dev, int channel) return nouveau_graph_wait_idle(dev); } -int nv30_graph_save_context(drm_device_t *dev, int channel) +int nv30_graph_save_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t inst; @@ -195,10 +195,10 @@ int nv30_graph_save_context(drm_device_t *dev, int channel) return nouveau_graph_wait_idle(dev); } -int nv30_graph_init(drm_device_t *dev) +int nv30_graph_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; uint32_t vramsz, tmp; int ret, i; @@ -279,7 +279,7 @@ int nv30_graph_init(drm_device_t *dev) return 0; } -void nv30_graph_takedown(drm_device_t *dev) +void nv30_graph_takedown(struct drm_device *dev) { } diff --git a/shared-core/nv40_fb.c b/shared-core/nv40_fb.c index 83a7580e..2cbb40e4 100644 --- a/shared-core/nv40_fb.c +++ b/shared-core/nv40_fb.c @@ -4,9 +4,9 @@ #include "nouveau_drm.h" int -nv40_fb_init(drm_device_t *dev) +nv40_fb_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t fb_bar_size, tmp; int num_tiles; int i; @@ -50,7 +50,7 @@ nv40_fb_init(drm_device_t *dev) } void -nv40_fb_takedown(drm_device_t *dev) +nv40_fb_takedown(struct drm_device *dev) { } diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c index 818a9024..ecb1d21e 100644 --- a/shared-core/nv40_fifo.c +++ b/shared-core/nv40_fifo.c @@ -37,9 +37,9 @@ #define NV40_RAMFC__SIZE 128 int -nv40_fifo_create_context(drm_device_t *dev, int channel) +nv40_fifo_create_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; int ret; @@ -73,9 +73,9 @@ nv40_fifo_create_context(drm_device_t *dev, int channel) } void -nv40_fifo_destroy_context(drm_device_t *dev, int channel) +nv40_fifo_destroy_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp, tmp2; @@ -144,9 +144,9 @@ nv40_fifo_load_context(drm_device_t *dev, int channel) } int -nv40_fifo_save_context(drm_device_t *dev, int channel) +nv40_fifo_save_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index 94d76505..d8fccb7e 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -47,9 +47,9 @@ * created. */ static void -nv40_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) +nv40_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int i; /* Always has the "instance address" of itself at offset 0 */ @@ -188,9 +188,9 @@ nv40_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) } static void -nv43_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) +nv43_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int i; INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); @@ -304,9 +304,9 @@ nv43_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) }; static void -nv46_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) +nv46_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int i; INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); @@ -455,9 +455,9 @@ nv46_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) } static void -nv49_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) +nv49_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int i; INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); @@ -678,9 +678,9 @@ nv49_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) } static void -nv4a_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) +nv4a_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int i; INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); @@ -795,9 +795,9 @@ nv4a_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) } static void -nv4b_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) +nv4b_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int i; INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); @@ -1010,9 +1010,9 @@ nv4b_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) } static void -nv4c_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) +nv4c_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int i; INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); @@ -1117,9 +1117,9 @@ nv4c_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) } static void -nv4e_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) +nv4e_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int i; INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); @@ -1224,12 +1224,12 @@ nv4e_graph_context_init(drm_device_t *dev, nouveau_gpuobj_t *ctx) } int -nv40_graph_create_context(drm_device_t *dev, int channel) +nv40_graph_create_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; - void (*ctx_init)(drm_device_t *, nouveau_gpuobj_t *); + void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *); unsigned int ctx_size; int ret; @@ -1284,9 +1284,9 @@ nv40_graph_create_context(drm_device_t *dev, int channel) } void -nv40_graph_destroy_context(drm_device_t *dev, int channel) +nv40_graph_destroy_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; if (chan->ramin_grctx) @@ -1294,9 +1294,9 @@ nv40_graph_destroy_context(drm_device_t *dev, int channel) } static int -nv40_graph_transfer_context(drm_device_t *dev, uint32_t inst, int save) +nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t old_cp, tv = 1000; int i; @@ -1327,9 +1327,9 @@ nv40_graph_transfer_context(drm_device_t *dev, uint32_t inst, int save) *XXX: fails sometimes, not sure why.. */ int -nv40_graph_save_context(drm_device_t *dev, int channel) +nv40_graph_save_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t inst; @@ -1344,9 +1344,9 @@ nv40_graph_save_context(drm_device_t *dev, int channel) * XXX: fails sometimes.. not sure why */ int -nv40_graph_load_context(drm_device_t *dev, int channel) +nv40_graph_load_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t inst; int ret; @@ -1599,10 +1599,10 @@ static uint32_t nv4e_ctx_voodoo[] = { * C51 0x4e */ int -nv40_graph_init(drm_device_t *dev) +nv40_graph_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; uint32_t *ctx_voodoo; uint32_t vramsz, tmp; int i, j; @@ -1829,7 +1829,7 @@ nv40_graph_init(drm_device_t *dev) return 0; } -void nv40_graph_takedown(drm_device_t *dev) +void nv40_graph_takedown(struct drm_device *dev) { } diff --git a/shared-core/nv40_mc.c b/shared-core/nv40_mc.c index 8dbd96fd..8bb6b083 100644 --- a/shared-core/nv40_mc.c +++ b/shared-core/nv40_mc.c @@ -4,9 +4,9 @@ #include "nouveau_drm.h" int -nv40_mc_init(drm_device_t *dev) +nv40_mc_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t tmp; /* Power up everything, resetting each individual unit will @@ -35,7 +35,7 @@ nv40_mc_init(drm_device_t *dev) } void -nv40_mc_takedown(drm_device_t *dev) +nv40_mc_takedown(struct drm_device *dev) { } diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index ee1fb887..feab24c4 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -29,18 +29,18 @@ #include "nouveau_drv.h" typedef struct { - nouveau_gpuobj_ref_t *thingo; - nouveau_gpuobj_ref_t *dummyctx; + struct nouveau_gpuobj_ref *thingo; + struct nouveau_gpuobj_ref *dummyctx; } nv50_fifo_priv; #define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50) static void -nv50_fifo_init_thingo(drm_device_t *dev) +nv50_fifo_init_thingo(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; - nouveau_gpuobj_ref_t *thingo = priv->thingo; + struct nouveau_gpuobj_ref *thingo = priv->thingo; int i, fi=2; DRM_DEBUG("\n"); @@ -60,9 +60,9 @@ nv50_fifo_init_thingo(drm_device_t *dev) } static int -nv50_fifo_channel_enable(drm_device_t *dev, int channel) +nv50_fifo_channel_enable(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; DRM_DEBUG("ch%d\n", channel); @@ -88,9 +88,9 @@ nv50_fifo_channel_enable(drm_device_t *dev, int channel) } static void -nv50_fifo_channel_disable(drm_device_t *dev, int channel, int nt) +nv50_fifo_channel_disable(struct drm_device *dev, int channel, int nt) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; DRM_DEBUG("ch%d, nt=%d\n", channel, nt); @@ -106,9 +106,9 @@ nv50_fifo_channel_disable(drm_device_t *dev, int channel, int nt) } static void -nv50_fifo_init_reset(drm_device_t *dev) +nv50_fifo_init_reset(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t pmc_e; DRM_DEBUG("\n"); @@ -120,7 +120,7 @@ nv50_fifo_init_reset(drm_device_t *dev) } static void -nv50_fifo_init_context_table(drm_device_t *dev) +nv50_fifo_init_context_table(struct drm_device *dev) { int i; @@ -132,9 +132,9 @@ nv50_fifo_init_context_table(drm_device_t *dev) } static void -nv50_fifo_init_regs__nv(drm_device_t *dev) +nv50_fifo_init_regs__nv(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; DRM_DEBUG("\n"); @@ -142,9 +142,9 @@ nv50_fifo_init_regs__nv(drm_device_t *dev) } static int -nv50_fifo_init_regs(drm_device_t *dev) +nv50_fifo_init_regs(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; int ret; @@ -176,9 +176,9 @@ nv50_fifo_init_regs(drm_device_t *dev) } int -nv50_fifo_init(drm_device_t *dev) +nv50_fifo_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; nv50_fifo_priv *priv; int ret; @@ -207,9 +207,9 @@ nv50_fifo_init(drm_device_t *dev) } void -nv50_fifo_takedown(drm_device_t *dev) +nv50_fifo_takedown(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; DRM_DEBUG("\n"); @@ -225,11 +225,11 @@ nv50_fifo_takedown(drm_device_t *dev) } int -nv50_fifo_create_context(drm_device_t *dev, int channel) +nv50_fifo_create_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; - nouveau_gpuobj_t *ramfc = NULL; + struct nouveau_gpuobj *ramfc = NULL; int ret; DRM_DEBUG("ch%d\n", channel); @@ -283,9 +283,9 @@ nv50_fifo_create_context(drm_device_t *dev, int channel) } void -nv50_fifo_destroy_context(drm_device_t *dev, int channel) +nv50_fifo_destroy_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; DRM_DEBUG("ch%d\n", channel); @@ -295,11 +295,11 @@ nv50_fifo_destroy_context(drm_device_t *dev, int channel) } int -nv50_fifo_load_context(drm_device_t *dev, int channel) +nv50_fifo_load_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; - nouveau_gpuobj_t *ramfc = chan->ramfc->gpuobj; + struct nouveau_gpuobj *ramfc = chan->ramfc->gpuobj; DRM_DEBUG("ch%d\n", channel); @@ -324,7 +324,7 @@ nv50_fifo_load_context(drm_device_t *dev, int channel) } int -nv50_fifo_save_context(drm_device_t *dev, int channel) +nv50_fifo_save_context(struct drm_device *dev, int channel) { DRM_DEBUG("ch%d\n", channel); DRM_ERROR("stub!\n"); diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c index 271ed733..54fe498b 100644 --- a/shared-core/nv50_graph.c +++ b/shared-core/nv50_graph.c @@ -31,9 +31,9 @@ #define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50) static void -nv50_graph_init_reset(drm_device_t *dev) +nv50_graph_init_reset(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t pmc_e; DRM_DEBUG("\n"); @@ -45,9 +45,9 @@ nv50_graph_init_reset(drm_device_t *dev) } static void -nv50_graph_init_regs__nv(drm_device_t *dev) +nv50_graph_init_regs__nv(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; DRM_DEBUG("\n"); @@ -66,9 +66,9 @@ nv50_graph_init_regs__nv(drm_device_t *dev) } static void -nv50_graph_init_regs(drm_device_t *dev) +nv50_graph_init_regs(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; DRM_DEBUG("\n"); @@ -139,9 +139,9 @@ static uint32_t nv84_ctx_voodoo[] = { }; static void -nv50_graph_init_ctxctl(drm_device_t *dev) +nv50_graph_init_ctxctl(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t *voodoo; DRM_DEBUG("\n"); @@ -169,7 +169,7 @@ nv50_graph_init_ctxctl(drm_device_t *dev) } int -nv50_graph_init(drm_device_t *dev) +nv50_graph_init(struct drm_device *dev) { DRM_DEBUG("\n"); @@ -182,17 +182,17 @@ nv50_graph_init(drm_device_t *dev) } void -nv50_graph_takedown(drm_device_t *dev) +nv50_graph_takedown(struct drm_device *dev) { DRM_DEBUG("\n"); } int -nv50_graph_create_context(drm_device_t *dev, int channel) +nv50_graph_create_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; - nouveau_gpuobj_t *ramin = chan->ramin->gpuobj; + struct nouveau_gpuobj *ramin = chan->ramin->gpuobj; int grctx_size = 0x60000, hdr; int ret; @@ -218,9 +218,9 @@ nv50_graph_create_context(drm_device_t *dev, int channel) } void -nv50_graph_destroy_context(drm_device_t *dev, int channel) +nv50_graph_destroy_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; int i, hdr; @@ -234,9 +234,9 @@ nv50_graph_destroy_context(drm_device_t *dev, int channel) } static int -nv50_graph_transfer_context(drm_device_t *dev, uint32_t inst, int save) +nv50_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t old_cp, tv = 20000; int i; @@ -266,9 +266,9 @@ nv50_graph_transfer_context(drm_device_t *dev, uint32_t inst, int save) } int -nv50_graph_load_context(drm_device_t *dev, int channel) +nv50_graph_load_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t inst = ((chan->ramin->instance >> 12) | (1<<31)); int ret; @@ -288,9 +288,9 @@ nv50_graph_load_context(drm_device_t *dev, int channel) } int -nv50_graph_save_context(drm_device_t *dev, int channel) +nv50_graph_save_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t inst = ((chan->ramin->instance >> 12) | (1<<31)); diff --git a/shared-core/nv50_instmem.c b/shared-core/nv50_instmem.c index 81c60829..027d3ffb 100644 --- a/shared-core/nv50_instmem.c +++ b/shared-core/nv50_instmem.c @@ -39,9 +39,9 @@ typedef struct { #define NV50_INSTMEM_PT_SIZE(a) (((a) >> 12) << 3) int -nv50_instmem_init(drm_device_t *dev) +nv50_instmem_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; nv50_instmem_priv *priv; uint32_t rv, pt, pts, cb, cb0, cb1, unk, as; uint32_t i, v; @@ -150,9 +150,9 @@ nv50_instmem_init(drm_device_t *dev) } void -nv50_instmem_takedown(drm_device_t *dev) +nv50_instmem_takedown(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv; int i; @@ -168,7 +168,7 @@ nv50_instmem_takedown(drm_device_t *dev) } int -nv50_instmem_populate(drm_device_t *dev, nouveau_gpuobj_t *gpuobj, uint32_t *sz) +nv50_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz) { if (gpuobj->im_backing) return DRM_ERR(EINVAL); @@ -189,9 +189,9 @@ nv50_instmem_populate(drm_device_t *dev, nouveau_gpuobj_t *gpuobj, uint32_t *sz) } void -nv50_instmem_clear(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +nv50_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; if (gpuobj && gpuobj->im_backing) { if (gpuobj->im_bound) @@ -202,9 +202,9 @@ nv50_instmem_clear(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) } int -nv50_instmem_bind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t pte, pte_end, vram; if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound) @@ -240,9 +240,9 @@ nv50_instmem_bind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) } int -nv50_instmem_unbind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t pte, pte_end; if (gpuobj->im_bound == 0) diff --git a/shared-core/nv50_mc.c b/shared-core/nv50_mc.c index 7f7537f0..952dea9f 100644 --- a/shared-core/nv50_mc.c +++ b/shared-core/nv50_mc.c @@ -29,14 +29,14 @@ #include "nouveau_drv.h" int -nv50_mc_init(drm_device_t *dev) +nv50_mc_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF); return 0; } -void nv50_mc_takedown(drm_device_t *dev) +void nv50_mc_takedown(struct drm_device *dev) { } -- cgit v1.2.3 From 5ae3ad4f015aa072180a0c55255832be4e7557cf Mon Sep 17 00:00:00 2001 From: Arthur Huillet Date: Fri, 13 Jul 2007 15:57:17 +0200 Subject: now attempting to create PCI object only when there is a pci_heap --- shared-core/nouveau_object.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index c5697d8e..aab2e3ac 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -918,7 +918,7 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel, return ret; } } - else { + else if ( dev_priv->pci_heap) { if (dev_priv -> card_type >= NV_50 ) return 0; /*no PCIGART for NV50*/ /*PCI*/ -- cgit v1.2.3 From aa6d9199fa7b0cbe04a936312db7be75bb53bdc8 Mon Sep 17 00:00:00 2001 From: Arthur Huillet Date: Fri, 13 Jul 2007 20:51:52 +0200 Subject: applied patch from Ian Romanick fixing PCI DMA object creation code --- shared-core/nouveau_object.c | 77 +++++++++++++++++++++----------------------- 1 file changed, 37 insertions(+), 40 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index aab2e3ac..146c4f1c 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -585,6 +585,11 @@ nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class, int ret; uint32_t is_scatter_gather = 0; + /* Total number of pages covered by the request. + */ + const unsigned int page_count = (size + PAGE_SIZE - 1) / PAGE_SIZE; + + DRM_DEBUG("ch%d class=0x%04x offset=0x%llx size=0x%llx\n", channel, class, offset, size); DRM_DEBUG("access=%d target=%d\n", access, target); @@ -604,7 +609,7 @@ nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class, } ret = nouveau_gpuobj_new(dev, channel, - is_scatter_gather ? ((((size + PAGE_SIZE - 1) / PAGE_SIZE) << 2) + 12) : nouveau_gpuobj_class_instmem_size(dev, class), + is_scatter_gather ? ((page_count << 2) + 12) : nouveau_gpuobj_class_instmem_size(dev, class), 16, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, gpuobj); @@ -634,9 +639,19 @@ nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class, } else { + /* Intial page entry in the scatter-gather area that + * corresponds to the base offset + */ + unsigned int idx = offset / PAGE_SIZE; + uint32_t instance_offset; - uint64_t bus_addr; - size = (uint32_t) size; + unsigned int i; + + if ((idx + page_count) > dev->sg->pages) { + DRM_ERROR("Requested page range exceedes " + "allocated scatter-gather range!"); + return DRM_ERR(E2BIG); + } DRM_DEBUG("Creating PCI DMA object using virtual zone starting at %#llx, size %d\n", offset, (uint32_t)size); INSTANCE_WR(*gpuobj, 0, ((1<<12) | (0<<13) | @@ -644,52 +659,34 @@ nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class, (access << 14) | (target << 16) | class)); - INSTANCE_WR(*gpuobj, 1, size-1); + INSTANCE_WR(*gpuobj, 1, (uint32_t) size-1); - offset += dev->sg->virtual; /*write starting at the third dword*/ instance_offset = 2; /*for each PAGE, get its bus address, fill in the page table entry, and advance*/ - while ( size > 0 ) { - bus_addr = vmalloc_to_page(offset); - if ( ! bus_addr ) - { - DRM_ERROR("Couldn't map virtual address %#llx to a page number\n", offset); - nouveau_gpuobj_del(dev, gpuobj); - return DRM_ERR(ENOMEM); + for (i = 0; i < page_count; i++) { + if (dev->sg->busaddr[idx] == 0) { + dev->sg->busaddr[idx] = + pci_map_page(dev->pdev, + dev->sg->pagelist[idx], + 0, + DMA_31BIT_MASK, + DMA_BIDIRECTIONAL); + + if (dev->sg->busaddr[idx] == 0) { + return DRM_ERR(ENOMEM); } - bus_addr = (uint64_t) page_address(bus_addr); - if ( ! bus_addr ) - { - DRM_ERROR("Couldn't find page address for address %#llx\n", offset); - nouveau_gpuobj_del(dev, gpuobj); - return DRM_ERR(ENOMEM); - } - bus_addr |= (offset & ~PAGE_MASK); - bus_addr = virt_to_bus((void *)bus_addr); - if ( ! bus_addr ) - { - DRM_ERROR("Couldn't get bus address for %#llx\n", offset); - nouveau_gpuobj_del(dev, gpuobj); - return DRM_ERR(ENOMEM); - } - - /*if ( bus_addr >= 1 << 32 ) - { - DRM_ERROR("Bus address %#llx is over 32 bits, Nvidia cards cannot address it !\n", bus_addr); - nouveau_gpuobj_del(dev, gpuobj); - return DRM_ERR(EINVAL); - }*/ - - frame = (uint32_t) bus_addr & ~0x00000FFF; - INSTANCE_WR(*gpuobj, instance_offset, frame | pte_flags); - offset += PAGE_SIZE; - instance_offset ++; - size -= PAGE_SIZE; } + frame = (uint32_t) dev->sg->busaddr[idx]; + INSTANCE_WR(*gpuobj, instance_offset, + frame | pte_flags); + + idx++; + instance_offset ++; + } } } else { INSTANCE_WR(*gpuobj, 0, 0x00190000 | class); -- cgit v1.2.3 From bc7d6c76fab2ff4d2f11b6bd84ca8b8f124729fd Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Sat, 14 Jul 2007 18:32:11 +0200 Subject: nouveau: nv10 and nv11/15 are different --- shared-core/nouveau_drm.h | 4 ++-- shared-core/nouveau_fifo.c | 1 + shared-core/nouveau_irq.c | 1 + shared-core/nouveau_mem.c | 1 + shared-core/nv04_instmem.c | 1 + 5 files changed, 6 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h index e2a9ea83..b39a7932 100644 --- a/shared-core/nouveau_drm.h +++ b/shared-core/nouveau_drm.h @@ -114,8 +114,8 @@ enum nouveau_card_type { NV_04 =4, NV_05 =5, NV_10 =10, - NV_11 =10, - NV_15 =10, + NV_11 =11, + NV_15 =11, NV_17 =17, NV_20 =20, NV_25 =20, diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index c769f58f..236dd4a1 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -99,6 +99,7 @@ static int nouveau_fifo_instmem_configure(struct drm_device *dev) (1 << 16) /* 64 Bytes entry*/); /* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */ break; + case NV_11: case NV_10: case NV_04: case NV_03: diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 451262a1..84319219 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -355,6 +355,7 @@ static void nouveau_pgraph_irq_handler(struct drm_device *dev) nouveau_nv04_context_switch(dev); break; case NV_10: + case NV_11: case NV_17: nouveau_nv10_context_switch(dev); break; diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 2b2418fb..f09bcea7 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -253,6 +253,7 @@ uint64_t nouveau_mem_fb_amount(struct drm_device *dev) } break; case NV_10: + case NV_11: case NV_17: case NV_20: case NV_30: diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index fc3b116d..7cf06269 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -70,6 +70,7 @@ nv04_instmem_configure_fixed_tables(struct drm_device *dev) case NV_30: case NV_20: case NV_17: + case NV_11: case NV_10: case NV_04: case NV_03: -- cgit v1.2.3 From f174f835ffac330bbd373d8ba5091205be28f327 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 16 Jul 2007 10:13:58 +1000 Subject: drm: remove typedefs in drm.h to their own section --- shared-core/drm.h | 231 ++++++++++++++++++++++++++++++++---------------------- 1 file changed, 138 insertions(+), 93 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index e017c023..f8912b3b 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -152,31 +152,31 @@ typedef unsigned int drm_magic_t; /**< Magic for authentication */ * \note KW: Actually it's illegal to change either for * backwards-compatibility reasons. */ -typedef struct drm_clip_rect { +struct drm_clip_rect { unsigned short x1; unsigned short y1; unsigned short x2; unsigned short y2; -} drm_clip_rect_t; +}; /** * Drawable information. */ -typedef struct drm_drawable_info { +struct drm_drawable_info { unsigned int num_rects; - drm_clip_rect_t *rects; -} drm_drawable_info_t; + struct drm_clip_rect *rects; +}; /** * Texture region, */ -typedef struct drm_tex_region { +struct drm_tex_region { unsigned char next; unsigned char prev; unsigned char in_use; unsigned char padding; unsigned int age; -} drm_tex_region_t; +}; /** * Hardware lock. @@ -185,10 +185,10 @@ typedef struct drm_tex_region { * processor bus contention on a multiprocessor system, there should not be any * other data stored in the same cache line. */ -typedef struct drm_hw_lock { +struct drm_hw_lock { __volatile__ unsigned int lock; /**< lock variable */ char padding[60]; /**< Pad to cache line */ -} drm_hw_lock_t; +}; /* This is beyond ugly, and only works on GCC. However, it allows me to use * drm.h in places (i.e., in the X-server) where I can't use size_t. The real @@ -211,7 +211,7 @@ typedef struct drm_hw_lock { * * \sa drmGetVersion(). */ -typedef struct drm_version { +struct drm_version { int version_major; /**< Major version */ int version_minor; /**< Minor version */ int version_patchlevel; /**< Patch level */ @@ -221,35 +221,35 @@ typedef struct drm_version { char __user *date; /**< User-space buffer to hold date */ DRM_SIZE_T desc_len; /**< Length of desc buffer */ char __user *desc; /**< User-space buffer to hold desc */ -} drm_version_t; +}; /** * DRM_IOCTL_GET_UNIQUE ioctl argument type. * * \sa drmGetBusid() and drmSetBusId(). */ -typedef struct drm_unique { +struct drm_unique { DRM_SIZE_T unique_len; /**< Length of unique */ char __user *unique; /**< Unique name for driver instantiation */ -} drm_unique_t; +}; #undef DRM_SIZE_T -typedef struct drm_list { +struct drm_list { int count; /**< Length of user-space structures */ - drm_version_t __user *version; -} drm_list_t; + struct drm_version __user *version; +}; -typedef struct drm_block { +struct drm_block { int unused; -} drm_block_t; +}; /** * DRM_IOCTL_CONTROL ioctl argument type. * * \sa drmCtlInstHandler() and drmCtlUninstHandler(). */ -typedef struct drm_control { +struct drm_control { enum { DRM_ADD_COMMAND, DRM_RM_COMMAND, @@ -257,12 +257,12 @@ typedef struct drm_control { DRM_UNINST_HANDLER } func; int irq; -} drm_control_t; +}; /** * Type of memory to map. */ -typedef enum drm_map_type { +enum drm_map_type { _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ _DRM_REGISTERS = 1, /**< no caching, no core dump */ _DRM_SHM = 2, /**< shared, cached */ @@ -270,12 +270,12 @@ typedef enum drm_map_type { _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ _DRM_TTM = 6 -} drm_map_type_t; +}; /** * Memory mapping flags. */ -typedef enum drm_map_flags { +enum drm_map_flags { _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ _DRM_READ_ONLY = 0x02, _DRM_LOCKED = 0x04, /**< shared, cached, locked */ @@ -283,12 +283,12 @@ typedef enum drm_map_flags { _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ _DRM_REMOVABLE = 0x40 /**< Removable mapping */ -} drm_map_flags_t; +}; -typedef struct drm_ctx_priv_map { +struct drm_ctx_priv_map { unsigned int ctx_id; /**< Context requesting private mapping */ void *handle; /**< Handle of map */ -} drm_ctx_priv_map_t; +}; /** * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls @@ -296,30 +296,30 @@ typedef struct drm_ctx_priv_map { * * \sa drmAddMap(). */ -typedef struct drm_map { +struct drm_map { unsigned long offset; /**< Requested physical address (0 for SAREA)*/ unsigned long size; /**< Requested physical size (bytes) */ - drm_map_type_t type; /**< Type of memory to map */ - drm_map_flags_t flags; /**< Flags */ + enum drm_map_type type; /**< Type of memory to map */ + enum drm_map_flags flags; /**< Flags */ void *handle; /**< User-space: "Handle" to pass to mmap() */ /**< Kernel-space: kernel-virtual address */ int mtrr; /**< MTRR slot used */ /* Private data */ -} drm_map_t; +}; /** * DRM_IOCTL_GET_CLIENT ioctl argument type. */ -typedef struct drm_client { +struct drm_client { int idx; /**< Which client desired? */ int auth; /**< Is client authenticated? */ unsigned long pid; /**< Process ID */ unsigned long uid; /**< User ID */ unsigned long magic; /**< Magic */ unsigned long iocs; /**< Ioctl count */ -} drm_client_t; +}; -typedef enum { +enum drm_stat_type { _DRM_STAT_LOCK, _DRM_STAT_OPENS, _DRM_STAT_CLOSES, @@ -337,23 +337,23 @@ typedef enum { _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ _DRM_STAT_MISSED /**< Missed DMA opportunity */ /* Add to the *END* of the list */ -} drm_stat_type_t; +}; /** * DRM_IOCTL_GET_STATS ioctl argument type. */ -typedef struct drm_stats { +struct drm_stats { unsigned long count; struct { unsigned long value; - drm_stat_type_t type; + enum drm_stat_type type; } data[15]; -} drm_stats_t; +}; /** * Hardware locking flags. */ -typedef enum drm_lock_flags { +enum drm_lock_flags { _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ @@ -363,17 +363,17 @@ typedef enum drm_lock_flags { full-screen DGA-like mode. */ _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ -} drm_lock_flags_t; +}; /** * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. * * \sa drmGetLock() and drmUnlock(). */ -typedef struct drm_lock { +struct drm_lock { int context; - drm_lock_flags_t flags; -} drm_lock_t; + enum drm_lock_flags flags; +}; /** * DMA flags @@ -383,7 +383,7 @@ typedef struct drm_lock { * * \sa drm_dma. */ -typedef enum drm_dma_flags { +enum drm_dma_flags { /* Flags for DMA buffer dispatch */ _DRM_DMA_BLOCK = 0x01, /**< * Block until buffer dispatched. @@ -402,14 +402,14 @@ typedef enum drm_dma_flags { _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ -} drm_dma_flags_t; +}; /** * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. * * \sa drmAddBufs(). */ -typedef struct drm_buf_desc { +struct drm_buf_desc { int count; /**< Number of buffers of this size */ int size; /**< Size in bytes */ int low_mark; /**< Low water mark */ @@ -425,48 +425,48 @@ typedef struct drm_buf_desc { * Start address of where the AGP buffers are * in the AGP aperture */ -} drm_buf_desc_t; +}; /** * DRM_IOCTL_INFO_BUFS ioctl argument type. */ -typedef struct drm_buf_info { +struct drm_buf_info { int count; /**< Number of buffers described in list */ - drm_buf_desc_t __user *list; /**< List of buffer descriptions */ -} drm_buf_info_t; + struct drm_buf_desc __user *list; /**< List of buffer descriptions */ +}; /** * DRM_IOCTL_FREE_BUFS ioctl argument type. */ -typedef struct drm_buf_free { +struct drm_buf_free { int count; int __user *list; -} drm_buf_free_t; +}; /** * Buffer information * * \sa drm_buf_map. */ -typedef struct drm_buf_pub { +struct drm_buf_pub { int idx; /**< Index into the master buffer list */ int total; /**< Buffer size */ int used; /**< Amount of buffer in use (for DMA) */ void __user *address; /**< Address of buffer */ -} drm_buf_pub_t; +}; /** * DRM_IOCTL_MAP_BUFS ioctl argument type. */ -typedef struct drm_buf_map { +struct drm_buf_map { int count; /**< Length of the buffer list */ #if defined(__cplusplus) void __user *c_virtual; #else void __user *virtual; /**< Mmap'd area in user-virtual */ #endif - drm_buf_pub_t __user *list; /**< Buffer information */ -} drm_buf_map_t; + struct drm_buf_pub __user *list; /**< Buffer information */ +}; /** * DRM_IOCTL_DMA ioctl argument type. @@ -475,48 +475,48 @@ typedef struct drm_buf_map { * * \sa drmDMA(). */ -typedef struct drm_dma { +struct drm_dma { int context; /**< Context handle */ int send_count; /**< Number of buffers to send */ int __user *send_indices; /**< List of handles to buffers */ int __user *send_sizes; /**< Lengths of data to send */ - drm_dma_flags_t flags; /**< Flags */ + enum drm_dma_flags flags; /**< Flags */ int request_count; /**< Number of buffers requested */ int request_size; /**< Desired size for buffers */ int __user *request_indices; /**< Buffer information */ int __user *request_sizes; int granted_count; /**< Number of buffers granted */ -} drm_dma_t; +}; -typedef enum { +enum drm_ctx_flags { _DRM_CONTEXT_PRESERVED = 0x01, _DRM_CONTEXT_2DONLY = 0x02 -} drm_ctx_flags_t; +}; /** * DRM_IOCTL_ADD_CTX ioctl argument type. * * \sa drmCreateContext() and drmDestroyContext(). */ -typedef struct drm_ctx { +struct drm_ctx { drm_context_t handle; - drm_ctx_flags_t flags; -} drm_ctx_t; + enum drm_ctx_flags flags; +}; /** * DRM_IOCTL_RES_CTX ioctl argument type. */ -typedef struct drm_ctx_res { +struct drm_ctx_res { int count; - drm_ctx_t __user *contexts; -} drm_ctx_res_t; + struct drm_ctx __user *contexts; +}; /** * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. */ -typedef struct drm_draw { +struct drm_draw { drm_drawable_t handle; -} drm_draw_t; +}; /** * DRM_IOCTL_UPDATE_DRAW ioctl argument type. @@ -525,53 +525,53 @@ typedef enum { DRM_DRAWABLE_CLIPRECTS, } drm_drawable_info_type_t; -typedef struct drm_update_draw { +struct drm_update_draw { drm_drawable_t handle; unsigned int type; unsigned int num; unsigned long long data; -} drm_update_draw_t; +}; /** * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. */ -typedef struct drm_auth { +struct drm_auth { drm_magic_t magic; -} drm_auth_t; +}; /** * DRM_IOCTL_IRQ_BUSID ioctl argument type. * * \sa drmGetInterruptFromBusID(). */ -typedef struct drm_irq_busid { +struct drm_irq_busid { int irq; /**< IRQ number */ int busnum; /**< bus number */ int devnum; /**< device number */ int funcnum; /**< function number */ -} drm_irq_busid_t; +}; -typedef enum { +enum drm_vblank_seq_type { _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ -} drm_vblank_seq_type_t; +}; #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \ _DRM_VBLANK_NEXTONMISS) struct drm_wait_vblank_request { - drm_vblank_seq_type_t type; + enum drm_vblank_seq_type type; unsigned int sequence; unsigned long signal; }; struct drm_wait_vblank_reply { - drm_vblank_seq_type_t type; + enum drm_vblank_seq_type type; unsigned int sequence; long tval_sec; long tval_usec; @@ -582,41 +582,41 @@ struct drm_wait_vblank_reply { * * \sa drmWaitVBlank(). */ -typedef union drm_wait_vblank { +union drm_wait_vblank { struct drm_wait_vblank_request request; struct drm_wait_vblank_reply reply; -} drm_wait_vblank_t; +}; /** * DRM_IOCTL_AGP_ENABLE ioctl argument type. * * \sa drmAgpEnable(). */ -typedef struct drm_agp_mode { +struct drm_agp_mode { unsigned long mode; /**< AGP mode */ -} drm_agp_mode_t; +}; /** * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. * * \sa drmAgpAlloc() and drmAgpFree(). */ -typedef struct drm_agp_buffer { +struct drm_agp_buffer { unsigned long size; /**< In bytes -- will round to page boundary */ unsigned long handle; /**< Used for binding / unbinding */ unsigned long type; /**< Type of memory to allocate */ unsigned long physical; /**< Physical used by i810 */ -} drm_agp_buffer_t; +}; /** * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. * * \sa drmAgpBind() and drmAgpUnbind(). */ -typedef struct drm_agp_binding { +struct drm_agp_binding { unsigned long handle; /**< From drm_agp_buffer */ unsigned long offset; /**< In bytes -- will round to page boundary */ -} drm_agp_binding_t; +}; /** * DRM_IOCTL_AGP_INFO ioctl argument type. @@ -625,7 +625,7 @@ typedef struct drm_agp_binding { * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), * drmAgpVendorId() and drmAgpDeviceId(). */ -typedef struct drm_agp_info { +struct drm_agp_info { int agp_version_major; int agp_version_minor; unsigned long mode; @@ -639,25 +639,25 @@ typedef struct drm_agp_info { unsigned short id_vendor; unsigned short id_device; /*@} */ -} drm_agp_info_t; +}; /** * DRM_IOCTL_SG_ALLOC ioctl argument type. */ -typedef struct drm_scatter_gather { +struct drm_scatter_gather { unsigned long size; /**< In bytes -- will round to page boundary */ unsigned long handle; /**< Used for mapping / unmapping */ -} drm_scatter_gather_t; +}; /** * DRM_IOCTL_SET_VERSION ioctl argument type. */ -typedef struct drm_set_version { +struct drm_set_version { int drm_di_major; int drm_di_minor; int drm_dd_major; int drm_dd_minor; -} drm_set_version_t; +}; #define DRM_FENCE_FLAG_EMIT 0x00000001 @@ -1015,4 +1015,49 @@ typedef struct drm_mm_init_arg { #define DRM_COMMAND_BASE 0x40 #define DRM_COMMAND_END 0xA0 +/* typedef area */ +#if 1 +/*!defined(__KERNEL__) || defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__)*/ +typedef struct drm_clip_rect drm_clip_rect_t; +typedef struct drm_drawable_info drm_drawable_info_t; +typedef struct drm_tex_region drm_tex_region_t; +typedef struct drm_hw_lock drm_hw_lock_t; +typedef struct drm_version drm_version_t; +typedef struct drm_unique drm_unique_t; +typedef struct drm_list drm_list_t; +typedef struct drm_block drm_block_t; +typedef struct drm_control drm_control_t; +typedef enum drm_map_type drm_map_type_t; +typedef enum drm_map_flags drm_map_flags_t; +typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; +typedef struct drm_map drm_map_t; +typedef struct drm_client drm_client_t; +typedef enum drm_stat_type drm_stat_type_t; +typedef struct drm_stats drm_stats_t; +typedef enum drm_lock_flags drm_lock_flags_t; +typedef struct drm_lock drm_lock_t; +typedef enum drm_dma_flags drm_dma_flags_t; +typedef struct drm_buf_desc drm_buf_desc_t; +typedef struct drm_buf_info drm_buf_info_t; +typedef struct drm_buf_free drm_buf_free_t; +typedef struct drm_buf_pub drm_buf_pub_t; +typedef struct drm_buf_map drm_buf_map_t; +typedef struct drm_dma drm_dma_t; +typedef union drm_wait_vblank drm_wait_vblank_t; +typedef struct drm_agp_mode drm_agp_mode_t; +typedef enum drm_ctx_flags drm_ctx_flags_t; +typedef struct drm_ctx drm_ctx_t; +typedef struct drm_ctx_res drm_ctx_res_t; +typedef struct drm_draw drm_draw_t; +typedef struct drm_update_draw drm_update_draw_t; +typedef struct drm_auth drm_auth_t; +typedef struct drm_irq_busid drm_irq_busid_t; +typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; +typedef struct drm_agp_buffer drm_agp_buffer_t; +typedef struct drm_agp_binding drm_agp_binding_t; +typedef struct drm_agp_info drm_agp_info_t; +typedef struct drm_scatter_gather drm_scatter_gather_t; +typedef struct drm_set_version drm_set_version_t; +#endif + #endif -- cgit v1.2.3 From b95ac8b7b313ad3eadc9e8bb0ead155303b7fa92 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 16 Jul 2007 11:22:15 +1000 Subject: drm: detypedef drm.h and fixup all problems --- shared-core/drm.h | 101 ++++++++++++++++++++++----------------------- shared-core/drm_sarea.h | 26 +++++++----- shared-core/i915_dma.c | 10 ++--- shared-core/i915_drm.h | 8 ++-- shared-core/i915_irq.c | 13 +++--- shared-core/i915_mem.c | 2 +- shared-core/mach64_dma.c | 12 +++--- shared-core/mach64_drm.h | 4 +- shared-core/mach64_state.c | 8 ++-- shared-core/mga_dma.c | 26 ++++++------ shared-core/mga_drm.h | 6 +-- shared-core/mga_state.c | 12 +++--- shared-core/nouveau_drm.h | 2 +- shared-core/nouveau_mem.c | 10 ++--- shared-core/r128_cce.c | 6 +-- shared-core/r128_drm.h | 4 +- shared-core/r128_state.c | 6 +-- shared-core/r300_cmdbuf.c | 2 +- shared-core/radeon_cp.c | 6 +-- shared-core/radeon_drm.h | 6 +-- shared-core/radeon_drv.h | 2 +- shared-core/radeon_state.c | 12 +++--- shared-core/savage_bci.c | 8 ++-- shared-core/savage_drm.h | 4 +- shared-core/savage_drv.h | 6 +-- shared-core/savage_state.c | 18 ++++---- shared-core/via_drm.h | 4 +- 27 files changed, 165 insertions(+), 159 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index f8912b3b..816a8ced 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -920,61 +920,61 @@ typedef struct drm_mm_init_arg { #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) -#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t) -#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t) -#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t) -#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t) -#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t) -#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t) -#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t) -#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t) - -#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t) -#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t) -#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t) -#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t) -#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t) -#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t) -#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t) -#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t) -#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t) -#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t) -#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t) - -#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t) - -#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t) -#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t) - -#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t) -#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t) -#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t) -#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t) -#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t) -#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t) -#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t) -#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t) -#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t) -#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t) -#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t) -#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t) -#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t) +#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) +#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) +#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) +#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) +#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) +#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) +#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) +#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) + +#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) +#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) +#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) +#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) +#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) +#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) +#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) +#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) +#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) +#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) +#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) + +#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) + +#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) +#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) + +#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) +#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) +#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) +#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) +#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) +#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) +#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) +#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) +#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) +#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) +#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) +#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) +#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) -#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t) -#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t) -#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t) -#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t) -#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t) -#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t) +#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) +#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) +#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) +#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) +#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) +#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) -#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t) -#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t) +#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, struct drm_scatter_gather) +#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) -#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t) +#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) -#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, drm_update_draw_t) +#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) #define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, drm_mm_init_arg_t) #define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, drm_mm_type_arg_t) @@ -1016,8 +1016,7 @@ typedef struct drm_mm_init_arg { #define DRM_COMMAND_END 0xA0 /* typedef area */ -#if 1 -/*!defined(__KERNEL__) || defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__)*/ +#if !defined(__KERNEL__) || defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) typedef struct drm_clip_rect drm_clip_rect_t; typedef struct drm_drawable_info drm_drawable_info_t; typedef struct drm_tex_region drm_tex_region_t; diff --git a/shared-core/drm_sarea.h b/shared-core/drm_sarea.h index 43d1114f..34050a6d 100644 --- a/shared-core/drm_sarea.h +++ b/shared-core/drm_sarea.h @@ -50,29 +50,35 @@ #define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000 /** SAREA drawable */ -typedef struct drm_sarea_drawable { +struct drm_sarea_drawable { unsigned int stamp; unsigned int flags; -} drm_sarea_drawable_t; +}; /** SAREA frame */ -typedef struct drm_sarea_frame { +struct drm_sarea_frame { unsigned int x; unsigned int y; unsigned int width; unsigned int height; unsigned int fullscreen; -} drm_sarea_frame_t; +}; /** SAREA */ -typedef struct drm_sarea { +struct drm_sarea { /** first thing is always the DRM locking structure */ - drm_hw_lock_t lock; + struct drm_hw_lock lock; /** \todo Use readers/writer lock for drm_sarea::drawable_lock */ - drm_hw_lock_t drawable_lock; - drm_sarea_drawable_t drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ - drm_sarea_frame_t frame; /**< frame */ + struct drm_hw_lock drawable_lock; + struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ + struct drm_sarea_frame frame; /**< frame */ drm_context_t dummy_context; -} drm_sarea_t; +}; + +#ifndef __KERNEL__ +typedef struct drm_sarea_drawable drm_sarea_drawable_t; +typedef struct drm_sarea_frame drm_sarea_frame_t; +typedef struct drm_sarea drm_sarea_t; +#endif #endif /* _DRM_SAREA_H_ */ diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index dbc5f959..f7d3fab4 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -398,11 +398,11 @@ static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords) } static int i915_emit_box(drm_device_t * dev, - drm_clip_rect_t __user * boxes, + struct drm_clip_rect __user * boxes, int i, int DR1, int DR4) { drm_i915_private_t *dev_priv = dev->dev_private; - drm_clip_rect_t box; + struct drm_clip_rect box; RING_LOCALS; if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) { @@ -524,7 +524,7 @@ static int i915_dispatch_batchbuffer(drm_device_t * dev, drm_i915_batchbuffer_t * batch) { drm_i915_private_t *dev_priv = dev->dev_private; - drm_clip_rect_t __user *boxes = batch->cliprects; + struct drm_clip_rect __user *boxes = batch->cliprects; int nbox = batch->num_cliprects; int i = 0, count; RING_LOCALS; @@ -683,7 +683,7 @@ static int i915_batchbuffer(DRM_IOCTL_ARGS) if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects, batch.num_cliprects * - sizeof(drm_clip_rect_t))) + sizeof(struct drm_clip_rect))) return DRM_ERR(EFAULT); ret = i915_dispatch_batchbuffer(dev, &batch); @@ -712,7 +712,7 @@ static int i915_cmdbuffer(DRM_IOCTL_ARGS) if (cmdbuf.num_cliprects && DRM_VERIFYAREA_READ(cmdbuf.cliprects, cmdbuf.num_cliprects * - sizeof(drm_clip_rect_t))) { + sizeof(struct drm_clip_rect))) { DRM_ERROR("Fault accessing cliprects\n"); return DRM_ERR(EFAULT); } diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h index 1c6ff4d3..3a90df6e 100644 --- a/shared-core/i915_drm.h +++ b/shared-core/i915_drm.h @@ -64,7 +64,7 @@ typedef struct _drm_i915_init { } drm_i915_init_t; typedef struct _drm_i915_sarea { - drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1]; + struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; int last_upload; /* last time texture was uploaded */ int last_enqueue; /* last time a buffer was enqueued */ int last_dispatch; /* age of the most recently dispatched buffer */ @@ -194,7 +194,7 @@ typedef struct _drm_i915_batchbuffer { int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ int num_cliprects; /* mulitpass with multiple cliprects? */ - drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */ + struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ } drm_i915_batchbuffer_t; /* As above, but pass a pointer to userspace buffer which can be @@ -206,7 +206,7 @@ typedef struct _drm_i915_cmdbuffer { int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ int num_cliprects; /* mulitpass with multiple cliprects? */ - drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */ + struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ } drm_i915_cmdbuffer_t; /* Userspace can request & wait on irq's: @@ -283,7 +283,7 @@ typedef struct drm_i915_vblank_pipe { */ typedef struct drm_i915_vblank_swap { drm_drawable_t drawable; - drm_vblank_seq_type_t seqtype; + enum drm_vblank_seq_type seqtype; unsigned int sequence; } drm_i915_vblank_swap_t; diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c index 2f6a6b95..eb32e194 100644 --- a/shared-core/i915_irq.c +++ b/shared-core/i915_irq.c @@ -43,7 +43,8 @@ * This function must be called with the drawable spinlock held. */ static void -i915_dispatch_vsync_flip(drm_device_t *dev, drm_drawable_info_t *drw, int pipe) +i915_dispatch_vsync_flip(drm_device_t *dev, struct drm_drawable_info *drw, + int pipe) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -67,7 +68,7 @@ i915_dispatch_vsync_flip(drm_device_t *dev, drm_drawable_info_t *drw, int pipe) if (x2 > 0 && y2 > 0) { int i, num_rects = drw->num_rects; - drm_clip_rect_t *rect = drw->rects; + struct drm_clip_rect *rect = drw->rects; for (i = 0; i < num_rects; i++) if (!(rect[i].x1 >= x2 || rect[i].y1 >= y2 || @@ -94,7 +95,7 @@ static void i915_vblank_tasklet(drm_device_t *dev) int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages; unsigned counter[2] = { atomic_read(&dev->vbl_received), atomic_read(&dev->vbl_received2) }; - drm_drawable_info_t *drw; + struct drm_drawable_info *drw; drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; u32 cpp = dev_priv->cpp, offsets[3]; u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD | @@ -139,7 +140,7 @@ static void i915_vblank_tasklet(drm_device_t *dev) list_for_each(hit, &hits) { drm_i915_vbl_swap_t *swap_cmp = list_entry(hit, drm_i915_vbl_swap_t, head); - drm_drawable_info_t *drw_cmp = + struct drm_drawable_info *drw_cmp = drm_get_drawable_info(dev, swap_cmp->drw_id); if (drw_cmp && @@ -198,7 +199,7 @@ static void i915_vblank_tasklet(drm_device_t *dev) list_for_each(hit, &hits) { drm_i915_vbl_swap_t *swap_hit = list_entry(hit, drm_i915_vbl_swap_t, head); - drm_clip_rect_t *rect; + struct drm_clip_rect *rect; int num_rects, pipe, front, back; unsigned short top, bottom; @@ -625,7 +626,7 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) swap.sequence--; if ((curseq - swap.sequence) <= (1<<23)) { - drm_drawable_info_t *drw; + struct drm_drawable_info *drw; LOCK_TEST_WITH_RETURN(dev, filp); diff --git a/shared-core/i915_mem.c b/shared-core/i915_mem.c index 13f19f3a..c66edfab 100644 --- a/shared-core/i915_mem.c +++ b/shared-core/i915_mem.c @@ -47,7 +47,7 @@ static void mark_block(drm_device_t * dev, struct mem_block *p, int in_use) { drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_tex_region_t *list; + struct drm_tex_region *list; unsigned shift, nr; unsigned start; unsigned end; diff --git a/shared-core/mach64_dma.c b/shared-core/mach64_dma.c index 60f55900..47340165 100644 --- a/shared-core/mach64_dma.c +++ b/shared-core/mach64_dma.c @@ -1462,10 +1462,10 @@ int mach64_freelist_put(drm_mach64_private_t * dev_priv, drm_buf_t * copy_buf) /*@{*/ static int mach64_dma_get_buffers(DRMFILE filp, drm_device_t * dev, - drm_dma_t * d) + struct drm_dma * d) { int i; - drm_buf_t *buf; + struct drm_buf *buf; drm_mach64_private_t *dev_priv = dev->dev_private; for (i = d->granted_count; i < d->request_count; i++) { @@ -1495,13 +1495,13 @@ static int mach64_dma_get_buffers(DRMFILE filp, drm_device_t * dev, int mach64_dma_buffers(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_device_dma_t *dma = dev->dma; - drm_dma_t d; + struct drm_device_dma *dma = dev->dma; + struct drm_dma d; int ret = 0; LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL(d, (drm_dma_t *) data, sizeof(d)); + DRM_COPY_FROM_USER_IOCTL(d, (struct drm_dma *) data, sizeof(d)); /* Please don't send us buffers. */ @@ -1525,7 +1525,7 @@ int mach64_dma_buffers(DRM_IOCTL_ARGS) ret = mach64_dma_get_buffers(filp, dev, &d); } - DRM_COPY_TO_USER_IOCTL((drm_dma_t *) data, d, sizeof(d)); + DRM_COPY_TO_USER_IOCTL((struct drm_dma *) data, d, sizeof(d)); return ret; } diff --git a/shared-core/mach64_drm.h b/shared-core/mach64_drm.h index 083f959d..1f5fd842 100644 --- a/shared-core/mach64_drm.h +++ b/shared-core/mach64_drm.h @@ -130,7 +130,7 @@ typedef struct drm_mach64_sarea { /* The current cliprects, or a subset thereof. */ - drm_clip_rect_t boxes[MACH64_NR_SAREA_CLIPRECTS]; + struct drm_clip_rect boxes[MACH64_NR_SAREA_CLIPRECTS]; unsigned int nbox; /* Counters for client-side throttling of rendering clients. @@ -139,7 +139,7 @@ typedef struct drm_mach64_sarea { /* Texture memory LRU. */ - drm_tex_region_t tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS + + struct drm_tex_region tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS + 1]; unsigned int tex_age[MACH64_NR_TEX_HEAPS]; int ctx_owner; diff --git a/shared-core/mach64_state.c b/shared-core/mach64_state.c index 38cefca9..a1047cbd 100644 --- a/shared-core/mach64_state.c +++ b/shared-core/mach64_state.c @@ -86,10 +86,10 @@ static void mach64_print_dirty(const char *msg, unsigned int flags) * negative for an error */ static int mach64_emit_cliprect(DRMFILE filp, drm_mach64_private_t * dev_priv, - drm_clip_rect_t * box) + struct drm_clip_rect * box) { u32 sc_left_right, sc_top_bottom; - drm_clip_rect_t scissor; + struct drm_clip_rect scissor; drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mach64_context_regs_t *regs = &sarea_priv->context_state; DMALOCALS; @@ -222,7 +222,7 @@ static int mach64_dma_dispatch_clear(DRMFILE filp, drm_device_t * dev, drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mach64_context_regs_t *ctx = &sarea_priv->context_state; int nbox = sarea_priv->nbox; - drm_clip_rect_t *pbox = sarea_priv->boxes; + struct drm_clip_rect *pbox = sarea_priv->boxes; u32 fb_bpp, depth_bpp; int i; DMALOCALS; @@ -360,7 +360,7 @@ static int mach64_dma_dispatch_swap(DRMFILE filp, drm_device_t * dev) drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; - drm_clip_rect_t *pbox = sarea_priv->boxes; + struct drm_clip_rect *pbox = sarea_priv->boxes; u32 fb_bpp; int i; DMALOCALS; diff --git a/shared-core/mga_dma.c b/shared-core/mga_dma.c index d48313c7..ea6212fe 100644 --- a/shared-core/mga_dma.c +++ b/shared-core/mga_dma.c @@ -443,11 +443,11 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev, const unsigned secondary_size = dma_bs->secondary_bin_count * dma_bs->secondary_bin_size; const unsigned agp_size = (dma_bs->agp_size << 20); - drm_buf_desc_t req; - drm_agp_mode_t mode; - drm_agp_info_t info; - drm_agp_buffer_t agp_req; - drm_agp_binding_t bind_req; + struct drm_buf_desc req; + struct drm_agp_mode mode; + struct drm_agp_info info; + struct drm_agp_buffer agp_req; + struct drm_agp_binding bind_req; /* Acquire AGP. */ err = drm_agp_acquire(dev); @@ -611,7 +611,7 @@ static int mga_do_pci_dma_bootstrap(drm_device_t * dev, unsigned int primary_size; unsigned int bin_count; int err; - drm_buf_desc_t req; + struct drm_buf_desc req; if (dev->dma == NULL) { @@ -967,8 +967,8 @@ static int mga_do_cleanup_dma(drm_device_t * dev, int full_cleanup) if (dev_priv->used_new_dma_init) { if (dev_priv->agp_handle != 0) { - drm_agp_binding_t unbind_req; - drm_agp_buffer_t free_req; + struct drm_agp_binding unbind_req; + struct drm_agp_buffer free_req; unbind_req.handle = dev_priv->agp_handle; drm_agp_unbind(dev, &unbind_req); @@ -1043,11 +1043,11 @@ int mga_dma_flush(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - drm_lock_t lock; + struct drm_lock lock; LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL(lock, (drm_lock_t __user *) data, + DRM_COPY_FROM_USER_IOCTL(lock, (struct drm_lock __user *) data, sizeof(lock)); DRM_DEBUG("%s%s%s\n", @@ -1089,7 +1089,7 @@ int mga_dma_reset(DRM_IOCTL_ARGS) * DMA buffer management */ -static int mga_dma_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d) +static int mga_dma_get_buffers(DRMFILE filp, drm_device_t * dev, struct drm_dma * d) { drm_buf_t *buf; int i; @@ -1118,8 +1118,8 @@ int mga_dma_buffers(DRM_IOCTL_ARGS) DRM_DEVICE; drm_device_dma_t *dma = dev->dma; drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - drm_dma_t __user *argp = (void __user *)data; - drm_dma_t d; + struct drm_dma __user *argp = (void __user *)data; + struct drm_dma d; int ret = 0; LOCK_TEST_WITH_RETURN(dev, filp); diff --git a/shared-core/mga_drm.h b/shared-core/mga_drm.h index 5bcdbfab..15c2dea2 100644 --- a/shared-core/mga_drm.h +++ b/shared-core/mga_drm.h @@ -181,7 +181,7 @@ typedef struct _drm_mga_sarea { /* The current cliprects, or a subset thereof. */ - drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS]; + struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS]; unsigned int nbox; /* Information about the most recently used 3d drawable. The @@ -202,7 +202,7 @@ typedef struct _drm_mga_sarea { unsigned int exported_nback; int exported_back_x, exported_front_x, exported_w; int exported_back_y, exported_front_y, exported_h; - drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS]; + struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS]; /* Counters for aging textures and for client-side throttling. */ @@ -216,7 +216,7 @@ typedef struct _drm_mga_sarea { /* LRU lists for texture memory in agp space and on the card. */ - drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; + struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; unsigned int texAge[MGA_NR_TEX_HEAPS]; /* Mechanism to validate card state. diff --git a/shared-core/mga_state.c b/shared-core/mga_state.c index 8e5cb334..527f6ce7 100644 --- a/shared-core/mga_state.c +++ b/shared-core/mga_state.c @@ -43,7 +43,7 @@ */ static void mga_emit_clip_rect(drm_mga_private_t * dev_priv, - drm_clip_rect_t * box) + struct drm_clip_rect * box) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; @@ -509,7 +509,7 @@ static void mga_dma_dispatch_clear(drm_device_t * dev, drm_mga_clear_t * clear) drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - drm_clip_rect_t *pbox = sarea_priv->boxes; + struct drm_clip_rect *pbox = sarea_priv->boxes; int nbox = sarea_priv->nbox; int i; DMA_LOCALS; @@ -525,7 +525,7 @@ static void mga_dma_dispatch_clear(drm_device_t * dev, drm_mga_clear_t * clear) ADVANCE_DMA(); for (i = 0; i < nbox; i++) { - drm_clip_rect_t *box = &pbox[i]; + struct drm_clip_rect *box = &pbox[i]; u32 height = box->y2 - box->y1; DRM_DEBUG(" from=%d,%d to=%d,%d\n", @@ -599,7 +599,7 @@ static void mga_dma_dispatch_swap(drm_device_t * dev) drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - drm_clip_rect_t *pbox = sarea_priv->boxes; + struct drm_clip_rect *pbox = sarea_priv->boxes; int nbox = sarea_priv->nbox; int i; DMA_LOCALS; @@ -626,7 +626,7 @@ static void mga_dma_dispatch_swap(drm_device_t * dev) MGA_DWGCTL, MGA_DWGCTL_COPY); for (i = 0; i < nbox; i++) { - drm_clip_rect_t *box = &pbox[i]; + struct drm_clip_rect *box = &pbox[i]; u32 height = box->y2 - box->y1; u32 start = box->y1 * dev_priv->front_pitch; @@ -805,7 +805,7 @@ static void mga_dma_dispatch_blit(drm_device_t * dev, drm_mga_blit_t * blit) drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - drm_clip_rect_t *pbox = sarea_priv->boxes; + struct drm_clip_rect *pbox = sarea_priv->boxes; int nbox = sarea_priv->nbox; u32 scandir = 0, i; DMA_LOCALS; diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h index b39a7932..4016f004 100644 --- a/shared-core/nouveau_drm.h +++ b/shared-core/nouveau_drm.h @@ -137,7 +137,7 @@ enum nouveau_bus_type { struct drm_nouveau_sarea { /* the cliprects */ - drm_clip_rect_t boxes[NOUVEAU_MAX_SAREA_CLIPRECTS]; + struct drm_clip_rect boxes[NOUVEAU_MAX_SAREA_CLIPRECTS]; unsigned int nbox; }; diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index f09bcea7..ef9df359 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -288,7 +288,7 @@ int nouveau_mem_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t fb_size; - drm_scatter_gather_t sgreq; + struct drm_scatter_gather sgreq; dev_priv->agp_phys=0; dev_priv->fb_phys=0; sgreq . size = 4 << 20; //4MB of PCI scatter-gather zone @@ -298,10 +298,10 @@ int nouveau_mem_init(struct drm_device *dev) if (drm_device_is_agp(dev)) { int err; - drm_agp_info_t info; - drm_agp_mode_t mode; - drm_agp_buffer_t agp_req; - drm_agp_binding_t bind_req; + struct drm_agp_info info; + struct drm_agp_mode mode; + struct drm_agp_buffer agp_req; + struct drm_agp_binding bind_req; err = drm_agp_acquire(dev); if (err) { diff --git a/shared-core/r128_cce.c b/shared-core/r128_cce.c index a2ee18b7..2d650b47 100644 --- a/shared-core/r128_cce.c +++ b/shared-core/r128_cce.c @@ -884,7 +884,7 @@ int r128_wait_ring(drm_r128_private_t * dev_priv, int n) return DRM_ERR(EBUSY); } -static int r128_cce_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d) +static int r128_cce_get_buffers(DRMFILE filp, drm_device_t * dev, struct drm_dma * d) { int i; drm_buf_t *buf; @@ -913,8 +913,8 @@ int r128_cce_buffers(DRM_IOCTL_ARGS) DRM_DEVICE; drm_device_dma_t *dma = dev->dma; int ret = 0; - drm_dma_t __user *argp = (void __user *)data; - drm_dma_t d; + struct drm_dma __user *argp = (void __user *)data; + struct drm_dma d; LOCK_TEST_WITH_RETURN(dev, filp); diff --git a/shared-core/r128_drm.h b/shared-core/r128_drm.h index 6e8af313..e94a39c6 100644 --- a/shared-core/r128_drm.h +++ b/shared-core/r128_drm.h @@ -153,7 +153,7 @@ typedef struct drm_r128_sarea { /* The current cliprects, or a subset thereof. */ - drm_clip_rect_t boxes[R128_NR_SAREA_CLIPRECTS]; + struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS]; unsigned int nbox; /* Counters for client-side throttling of rendering clients. @@ -161,7 +161,7 @@ typedef struct drm_r128_sarea { unsigned int last_frame; unsigned int last_dispatch; - drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1]; + struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1]; unsigned int tex_age[R128_NR_TEX_HEAPS]; int ctx_owner; int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ diff --git a/shared-core/r128_state.c b/shared-core/r128_state.c index 17b11e7d..565e0d4f 100644 --- a/shared-core/r128_state.c +++ b/shared-core/r128_state.c @@ -38,7 +38,7 @@ */ static void r128_emit_clip_rects(drm_r128_private_t * dev_priv, - drm_clip_rect_t * boxes, int count) + struct drm_clip_rect * boxes, int count) { u32 aux_sc_cntl = 0x00000000; RING_LOCALS; @@ -358,7 +358,7 @@ static void r128_cce_dispatch_clear(drm_device_t * dev, drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; - drm_clip_rect_t *pbox = sarea_priv->boxes; + struct drm_clip_rect *pbox = sarea_priv->boxes; unsigned int flags = clear->flags; int i; RING_LOCALS; @@ -463,7 +463,7 @@ static void r128_cce_dispatch_swap(drm_device_t * dev) drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; - drm_clip_rect_t *pbox = sarea_priv->boxes; + struct drm_clip_rect *pbox = sarea_priv->boxes; int i; RING_LOCALS; DRM_DEBUG("%s\n", __FUNCTION__); diff --git a/shared-core/r300_cmdbuf.c b/shared-core/r300_cmdbuf.c index 0cd5d7e2..ab4f1cae 100644 --- a/shared-core/r300_cmdbuf.c +++ b/shared-core/r300_cmdbuf.c @@ -55,7 +55,7 @@ static const int r300_cliprect_cntl[4] = { static int r300_emit_cliprects(drm_radeon_private_t *dev_priv, drm_radeon_kcmd_buffer_t *cmdbuf, int n) { - drm_clip_rect_t box; + struct drm_clip_rect box; int nr; int i; RING_LOCALS; diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index ec2e688b..ba06443f 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -2191,7 +2191,7 @@ int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) } static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev, - drm_dma_t * d) + struct drm_dma * d) { int i; drm_buf_t *buf; @@ -2220,8 +2220,8 @@ int radeon_cp_buffers(DRM_IOCTL_ARGS) DRM_DEVICE; drm_device_dma_t *dma = dev->dma; int ret = 0; - drm_dma_t __user *argp = (void __user *)data; - drm_dma_t d; + struct drm_dma __user *argp = (void __user *)data; + struct drm_dma d; LOCK_TEST_WITH_RETURN(dev, filp); diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h index 6a57b804..b0ef702b 100644 --- a/shared-core/radeon_drm.h +++ b/shared-core/radeon_drm.h @@ -417,7 +417,7 @@ typedef struct { /* The current cliprects, or a subset thereof. */ - drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS]; + struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; unsigned int nbox; /* Counters for client-side throttling of rendering clients. @@ -426,7 +426,7 @@ typedef struct { unsigned int last_dispatch; unsigned int last_clear; - drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + + struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 1]; unsigned int tex_age[RADEON_NR_TEX_HEAPS]; int ctx_owner; @@ -604,7 +604,7 @@ typedef struct drm_radeon_cmd_buffer { int bufsz; char __user *buf; int nbox; - drm_clip_rect_t __user *boxes; + struct drm_clip_rect __user *boxes; } drm_radeon_cmd_buffer_t; typedef struct drm_radeon_tex_image { diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 92a9b65e..03d2e7f2 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -312,7 +312,7 @@ typedef struct drm_radeon_kcmd_buffer { int bufsz; char *buf; int nbox; - drm_clip_rect_t __user *boxes; + struct drm_clip_rect __user *boxes; } drm_radeon_kcmd_buffer_t; extern int radeon_no_wb; diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c index 8ccd0981..882cd323 100644 --- a/shared-core/radeon_state.c +++ b/shared-core/radeon_state.c @@ -421,7 +421,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * */ static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv, - drm_clip_rect_t * box) + struct drm_clip_rect * box) { RING_LOCALS; @@ -852,7 +852,7 @@ static void radeon_cp_dispatch_clear(drm_device_t * dev, drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear; int nbox = sarea_priv->nbox; - drm_clip_rect_t *pbox = sarea_priv->boxes; + struct drm_clip_rect *pbox = sarea_priv->boxes; unsigned int flags = clear->flags; u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0; int i; @@ -1340,7 +1340,7 @@ static void radeon_cp_dispatch_swap(drm_device_t * dev) drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; - drm_clip_rect_t *pbox = sarea_priv->boxes; + struct drm_clip_rect *pbox = sarea_priv->boxes; int i; RING_LOCALS; DRM_DEBUG("\n"); @@ -1415,7 +1415,7 @@ static void radeon_cp_dispatch_swap(drm_device_t * dev) static void radeon_cp_dispatch_flip(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; - drm_sarea_t *sarea = (drm_sarea_t *) dev_priv->sarea->handle; + struct drm_sarea *sarea = (struct drm_sarea *) dev_priv->sarea->handle; int offset = (dev_priv->sarea_priv->pfCurrentPage == 1) ? dev_priv->front_offset : dev_priv->back_offset; RING_LOCALS; @@ -2795,10 +2795,10 @@ static int radeon_emit_packet3_cliprect(drm_device_t *dev, int orig_nbox) { drm_radeon_private_t *dev_priv = dev->dev_private; - drm_clip_rect_t box; + struct drm_clip_rect box; unsigned int cmdsz; int ret; - drm_clip_rect_t __user *boxes = cmdbuf->boxes; + struct drm_clip_rect __user *boxes = cmdbuf->boxes; int i = 0; RING_LOCALS; diff --git a/shared-core/savage_bci.c b/shared-core/savage_bci.c index 9a3ae1f1..7492a38c 100644 --- a/shared-core/savage_bci.c +++ b/shared-core/savage_bci.c @@ -1006,7 +1006,7 @@ static int savage_bci_event_wait(DRM_IOCTL_ARGS) * DMA buffer management */ -static int savage_bci_get_buffers(DRMFILE filp, drm_device_t *dev, drm_dma_t *d) +static int savage_bci_get_buffers(DRMFILE filp, drm_device_t *dev, struct drm_dma *d) { drm_buf_t *buf; int i; @@ -1034,12 +1034,12 @@ int savage_bci_buffers(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_device_dma_t *dma = dev->dma; - drm_dma_t d; + struct drm_dma d; int ret = 0; LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL(d, (drm_dma_t __user *)data, sizeof(d)); + DRM_COPY_FROM_USER_IOCTL(d, (struct drm_dma __user *)data, sizeof(d)); /* Please don't send us buffers. */ @@ -1063,7 +1063,7 @@ int savage_bci_buffers(DRM_IOCTL_ARGS) ret = savage_bci_get_buffers(filp, dev, &d); } - DRM_COPY_TO_USER_IOCTL((drm_dma_t __user *)data, d, sizeof(d)); + DRM_COPY_TO_USER_IOCTL((struct drm_dma __user *)data, d, sizeof(d)); return ret; } diff --git a/shared-core/savage_drm.h b/shared-core/savage_drm.h index 6526c9aa..b960d557 100644 --- a/shared-core/savage_drm.h +++ b/shared-core/savage_drm.h @@ -47,7 +47,7 @@ typedef struct _drm_savage_sarea { /* LRU lists for texture memory in agp space and on the card. */ - drm_tex_region_t texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS+1]; + struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS+1]; unsigned int texAge[SAVAGE_NR_TEX_HEAPS]; /* Mechanism to validate card state. @@ -112,7 +112,7 @@ typedef struct drm_savage_cmdbuf { unsigned int vb_size; /* size of client vertex buffer in bytes */ unsigned int vb_stride; /* stride of vertices in 32bit words */ /* boxes in client's address space */ - drm_clip_rect_t __user *box_addr; + struct drm_clip_rect __user *box_addr; unsigned int nbox; /* number of clipping boxes */ } drm_savage_cmdbuf_t; diff --git a/shared-core/savage_drv.h b/shared-core/savage_drv.h index 88c571e1..8d04d43b 100644 --- a/shared-core/savage_drv.h +++ b/shared-core/savage_drv.h @@ -192,7 +192,7 @@ typedef struct drm_savage_private { /* Err, there is a macro wait_event in include/linux/wait.h. * Avoid unwanted macro expansion. */ void (*emit_clip_rect)(struct drm_savage_private *dev_priv, - const drm_clip_rect_t *pbox); + const struct drm_clip_rect *pbox); void (*dma_flush)(struct drm_savage_private *dev_priv); } drm_savage_private_t; @@ -216,9 +216,9 @@ extern void savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp); /* state functions */ extern void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv, - const drm_clip_rect_t *pbox); + const struct drm_clip_rect *pbox); extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv, - const drm_clip_rect_t *pbox); + const struct drm_clip_rect *pbox); #define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */ #define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */ diff --git a/shared-core/savage_state.c b/shared-core/savage_state.c index acc98f89..54b9169b 100644 --- a/shared-core/savage_state.c +++ b/shared-core/savage_state.c @@ -27,7 +27,7 @@ #include "savage_drv.h" void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv, - const drm_clip_rect_t *pbox) + const struct drm_clip_rect *pbox) { uint32_t scstart = dev_priv->state.s3d.new_scstart; uint32_t scend = dev_priv->state.s3d.new_scend; @@ -53,7 +53,7 @@ void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv, } void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv, - const drm_clip_rect_t *pbox) + const struct drm_clip_rect *pbox) { uint32_t drawctrl0 = dev_priv->state.s4.new_drawctrl0; uint32_t drawctrl1 = dev_priv->state.s4.new_drawctrl1; @@ -790,7 +790,7 @@ static int savage_dispatch_clear(drm_savage_private_t *dev_priv, const drm_savage_cmd_header_t *cmd_header, const drm_savage_cmd_header_t *data, unsigned int nbox, - const drm_clip_rect_t *boxes) + const struct drm_clip_rect *boxes) { unsigned int flags = cmd_header->clear0.flags; unsigned int clear_cmd; @@ -860,7 +860,7 @@ static int savage_dispatch_clear(drm_savage_private_t *dev_priv, } static int savage_dispatch_swap(drm_savage_private_t *dev_priv, - unsigned int nbox, const drm_clip_rect_t *boxes) + unsigned int nbox, const struct drm_clip_rect *boxes) { unsigned int swap_cmd; unsigned int i; @@ -895,7 +895,7 @@ static int savage_dispatch_draw(drm_savage_private_t *dev_priv, const unsigned int *vtxbuf, unsigned int vb_size, unsigned int vb_stride, unsigned int nbox, - const drm_clip_rect_t *boxes) + const struct drm_clip_rect *boxes) { unsigned int i, j; int ret; @@ -962,7 +962,7 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) drm_savage_cmd_header_t *kcmd_addr = NULL; drm_savage_cmd_header_t *first_draw_cmd; unsigned int *kvb_addr = NULL; - drm_clip_rect_t *kbox_addr = NULL; + struct drm_clip_rect *kbox_addr = NULL; unsigned int i, j; int ret = 0; @@ -1018,7 +1018,7 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) cmdbuf.vb_addr = kvb_addr; } if (cmdbuf.nbox) { - kbox_addr = drm_alloc(cmdbuf.nbox * sizeof(drm_clip_rect_t), + kbox_addr = drm_alloc(cmdbuf.nbox * sizeof(struct drm_clip_rect), DRM_MEM_DRIVER); if (kbox_addr == NULL) { ret = DRM_ERR(ENOMEM); @@ -1026,7 +1026,7 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) } if (DRM_COPY_FROM_USER(kbox_addr, cmdbuf.box_addr, - cmdbuf.nbox * sizeof(drm_clip_rect_t))) { + cmdbuf.nbox * sizeof(struct drm_clip_rect))) { ret = DRM_ERR(EFAULT); goto done; } @@ -1157,7 +1157,7 @@ done: /* If we didn't need to allocate them, these'll be NULL */ drm_free(kcmd_addr, cmdbuf.size * 8, DRM_MEM_DRIVER); drm_free(kvb_addr, cmdbuf.vb_size, DRM_MEM_DRIVER); - drm_free(kbox_addr, cmdbuf.nbox * sizeof(drm_clip_rect_t), + drm_free(kbox_addr, cmdbuf.nbox * sizeof(struct drm_clip_rect), DRM_MEM_DRIVER); return ret; diff --git a/shared-core/via_drm.h b/shared-core/via_drm.h index 635e4637..b15785b3 100644 --- a/shared-core/via_drm.h +++ b/shared-core/via_drm.h @@ -54,7 +54,7 @@ #define VIA_NR_XVMC_LOCKS 5 #define VIA_MAX_CACHELINE_SIZE 64 #define XVMCLOCKPTR(saPriv,lockNo) \ - ((volatile drm_hw_lock_t *)(((((unsigned long) (saPriv)->XvMCLockArea) + \ + ((volatile struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \ (VIA_MAX_CACHELINE_SIZE - 1)) & \ ~(VIA_MAX_CACHELINE_SIZE - 1)) + \ VIA_MAX_CACHELINE_SIZE*(lockNo))) @@ -187,7 +187,7 @@ typedef struct _drm_via_tex_region { typedef struct _drm_via_sarea { unsigned int dirty; unsigned int nbox; - drm_clip_rect_t boxes[VIA_NR_SAREA_CLIPRECTS]; + struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS]; drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1]; int texAge; /* last time texture was uploaded */ int ctxOwner; /* last context to upload state */ -- cgit v1.2.3 From 1a07256d601a94466b7905680f5b929bf3f2390a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 16 Jul 2007 11:30:53 +1000 Subject: drm: remove ttm userspace typedefs --- shared-core/drm.h | 51 ++++++++++++++++++++++++++++----------------------- 1 file changed, 28 insertions(+), 23 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index 816a8ced..3ab63d5d 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -670,7 +670,7 @@ struct drm_set_version { #define DRM_FENCE_TYPE_EXE 0x00000001 -typedef struct drm_fence_arg { +struct drm_fence_arg { unsigned int handle; unsigned int class; unsigned int type; @@ -678,7 +678,7 @@ typedef struct drm_fence_arg { unsigned int signaled; unsigned int pad64; drm_u64_t expand_pad[3]; /*Future expansion */ -} drm_fence_arg_t; +}; /* Buffer permissions, referring to how the GPU uses the buffers. * these translate to fence types used for the buffers. @@ -784,12 +784,12 @@ typedef struct drm_fence_arg { #define DRM_BO_INIT_MINOR 1 -typedef enum { +enum drm_bo_type { drm_bo_type_dc, drm_bo_type_user, drm_bo_type_fake, drm_bo_type_kernel, /* for initial kernel allocations */ -}drm_bo_type_t; +}; struct drm_bo_info_req { drm_u64_t mask; @@ -806,7 +806,7 @@ struct drm_bo_create_req { drm_u64_t buffer_start; unsigned int hint; unsigned int page_alignment; - drm_bo_type_t type; + enum drm_bo_type type; unsigned int pad64; }; @@ -896,18 +896,18 @@ struct drm_bo_op_arg { #define DRM_BO_MEM_TYPES 8 /* For now. */ -typedef struct drm_mm_type_arg { +struct drm_mm_type_arg { unsigned int mem_type; -} drm_mm_type_arg_t; +}; -typedef struct drm_mm_init_arg { +struct drm_mm_init_arg { unsigned int magic; unsigned int major; unsigned int minor; unsigned int mem_type; drm_u64_t p_offset; drm_u64_t p_size; -} drm_mm_init_arg_t; +}; /** * \name Ioctls Definitions @@ -976,20 +976,20 @@ typedef struct drm_mm_init_arg { #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) -#define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, drm_mm_init_arg_t) -#define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, drm_mm_type_arg_t) -#define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, drm_mm_type_arg_t) -#define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, drm_mm_type_arg_t) - -#define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, drm_fence_arg_t) -#define DRM_IOCTL_FENCE_DESTROY DRM_IOWR(0xc5, drm_fence_arg_t) -#define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, drm_fence_arg_t) -#define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, drm_fence_arg_t) -#define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, drm_fence_arg_t) -#define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, drm_fence_arg_t) -#define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, drm_fence_arg_t) -#define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, drm_fence_arg_t) -#define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, drm_fence_arg_t) +#define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, struct drm_mm_init_arg) +#define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, struct drm_mm_type_arg) +#define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, struct drm_mm_type_arg) +#define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg) + +#define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg) +#define DRM_IOCTL_FENCE_DESTROY DRM_IOWR(0xc5, struct drm_fence_arg) +#define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg) +#define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg) +#define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg) +#define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, struct drm_fence_arg) +#define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, struct drm_fence_arg) +#define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, struct drm_fence_arg) +#define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg) #define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg) #define DRM_IOCTL_BO_DESTROY DRM_IOWR(0xce, struct drm_bo_handle_arg) @@ -1057,6 +1057,11 @@ typedef struct drm_agp_binding drm_agp_binding_t; typedef struct drm_agp_info drm_agp_info_t; typedef struct drm_scatter_gather drm_scatter_gather_t; typedef struct drm_set_version drm_set_version_t; + +typedef struct drm_fence_arg drm_fence_arg_t; +typedef struct drm_mm_type_arg drm_mm_type_arg_t; +typedef struct drm_mm_init_arg drm_mm_init_arg_t; +typedef enum drm_bo_type drm_bo_type_t; #endif #endif -- cgit v1.2.3 From 21ee6fbfb8f2219a454458204afc9c5fcd89f9a8 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 16 Jul 2007 12:32:51 +1000 Subject: drm: remove drmP.h internal typedefs --- shared-core/i915_dma.c | 40 ++++++++++---------- shared-core/i915_drv.h | 46 +++++++++++------------ shared-core/i915_irq.c | 24 ++++++------ shared-core/i915_mem.c | 4 +- shared-core/mach64_dma.c | 16 ++++---- shared-core/mach64_drv.h | 18 ++++----- shared-core/mach64_irq.c | 10 ++--- shared-core/mach64_state.c | 10 ++--- shared-core/mga_dma.c | 42 ++++++++++----------- shared-core/mga_drv.h | 22 +++++------ shared-core/mga_irq.c | 12 +++--- shared-core/mga_state.c | 24 ++++++------ shared-core/nouveau_fifo.c | 4 +- shared-core/nouveau_mem.c | 2 +- shared-core/r128_cce.c | 34 ++++++++--------- shared-core/r128_drv.h | 20 +++++----- shared-core/r128_irq.c | 10 ++--- shared-core/r128_state.c | 56 ++++++++++++++-------------- shared-core/r300_cmdbuf.c | 8 ++-- shared-core/radeon_cp.c | 34 ++++++++--------- shared-core/radeon_drv.h | 36 +++++++++--------- shared-core/radeon_irq.c | 24 ++++++------ shared-core/radeon_state.c | 92 +++++++++++++++++++++++----------------------- shared-core/savage_bci.c | 32 ++++++++-------- shared-core/savage_drv.h | 14 +++---- shared-core/savage_state.c | 2 +- shared-core/sis_drv.h | 12 +++--- shared-core/via_dma.c | 12 +++--- shared-core/via_drv.h | 42 ++++++++++----------- shared-core/via_irq.c | 12 +++--- shared-core/via_map.c | 8 ++-- shared-core/via_verifier.c | 8 ++-- shared-core/via_verifier.h | 6 +-- 33 files changed, 368 insertions(+), 368 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index f7d3fab4..fbad27c0 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -47,7 +47,7 @@ * the head pointer changes, so that EBUSY only happens if the ring * actually stalls for (eg) 3 seconds. */ -int i915_wait_ring(drm_device_t * dev, int n, const char *caller) +int i915_wait_ring(struct drm_device * dev, int n, const char *caller) { drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_ring_buffer_t *ring = &(dev_priv->ring); @@ -74,7 +74,7 @@ int i915_wait_ring(drm_device_t * dev, int n, const char *caller) return DRM_ERR(EBUSY); } -void i915_kernel_lost_context(drm_device_t * dev) +void i915_kernel_lost_context(struct drm_device * dev) { drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_ring_buffer_t *ring = &(dev_priv->ring); @@ -89,7 +89,7 @@ void i915_kernel_lost_context(drm_device_t * dev) dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; } -static int i915_dma_cleanup(drm_device_t * dev) +static int i915_dma_cleanup(struct drm_device * dev) { /* Make sure interrupts are disabled here because the uninstall ioctl * may not have been called from userspace and after dev_private @@ -125,7 +125,7 @@ static int i915_dma_cleanup(drm_device_t * dev) return 0; } -static int i915_initialize(drm_device_t * dev, +static int i915_initialize(struct drm_device * dev, drm_i915_private_t * dev_priv, drm_i915_init_t * init) { @@ -212,7 +212,7 @@ static int i915_initialize(drm_device_t * dev, return 0; } -static int i915_dma_resume(drm_device_t * dev) +static int i915_dma_resume(struct drm_device * dev) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; @@ -358,7 +358,7 @@ static int validate_cmd(int cmd) return ret; } -static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords) +static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords) { drm_i915_private_t *dev_priv = dev->dev_private; int i; @@ -397,7 +397,7 @@ static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords) return 0; } -static int i915_emit_box(drm_device_t * dev, +static int i915_emit_box(struct drm_device * dev, struct drm_clip_rect __user * boxes, int i, int DR1, int DR4) { @@ -440,7 +440,7 @@ static int i915_emit_box(drm_device_t * dev, * emit. For now, do it in both places: */ -void i915_emit_breadcrumb(drm_device_t *dev) +void i915_emit_breadcrumb(struct drm_device *dev) { drm_i915_private_t *dev_priv = dev->dev_private; RING_LOCALS; @@ -461,7 +461,7 @@ void i915_emit_breadcrumb(drm_device_t *dev) } -int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush) +int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush) { drm_i915_private_t *dev_priv = dev->dev_private; uint32_t flush_cmd = CMD_MI_FLUSH; @@ -482,7 +482,7 @@ int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush) } -static int i915_dispatch_cmdbuffer(drm_device_t * dev, +static int i915_dispatch_cmdbuffer(struct drm_device * dev, drm_i915_cmdbuffer_t * cmd) { #ifdef I915_HAVE_FENCE @@ -520,7 +520,7 @@ static int i915_dispatch_cmdbuffer(drm_device_t * dev, return 0; } -static int i915_dispatch_batchbuffer(drm_device_t * dev, +static int i915_dispatch_batchbuffer(struct drm_device * dev, drm_i915_batchbuffer_t * batch) { drm_i915_private_t *dev_priv = dev->dev_private; @@ -568,7 +568,7 @@ static int i915_dispatch_batchbuffer(drm_device_t * dev, return 0; } -static void i915_do_dispatch_flip(drm_device_t * dev, int pipe, int sync) +static void i915_do_dispatch_flip(struct drm_device * dev, int pipe, int sync) { drm_i915_private_t *dev_priv = dev->dev_private; u32 num_pages, current_page, next_page, dspbase; @@ -620,7 +620,7 @@ static void i915_do_dispatch_flip(drm_device_t * dev, int pipe, int sync) dev_priv->sarea_priv->pf_current_page |= next_page << shift; } -void i915_dispatch_flip(drm_device_t * dev, int pipes, int sync) +void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync) { drm_i915_private_t *dev_priv = dev->dev_private; int i; @@ -642,7 +642,7 @@ void i915_dispatch_flip(drm_device_t * dev, int pipes, int sync) #endif } -static int i915_quiescent(drm_device_t * dev) +static int i915_quiescent(struct drm_device * dev) { drm_i915_private_t *dev_priv = dev->dev_private; @@ -727,7 +727,7 @@ static int i915_cmdbuffer(DRM_IOCTL_ARGS) return 0; } -static int i915_do_cleanup_pageflip(drm_device_t * dev) +static int i915_do_cleanup_pageflip(struct drm_device * dev) { drm_i915_private_t *dev_priv = dev->dev_private; int i, pipes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2; @@ -939,7 +939,7 @@ static int i915_set_status_page(DRM_IOCTL_ARGS) return 0; } -int i915_driver_load(drm_device_t *dev, unsigned long flags) +int i915_driver_load(struct drm_device *dev, unsigned long flags) { /* i915 has 4 more counters */ dev->counters += 4; @@ -951,7 +951,7 @@ int i915_driver_load(drm_device_t *dev, unsigned long flags) return 0; } -void i915_driver_lastclose(drm_device_t * dev) +void i915_driver_lastclose(struct drm_device * dev) { if (dev->dev_private) { drm_i915_private_t *dev_priv = dev->dev_private; @@ -961,7 +961,7 @@ void i915_driver_lastclose(drm_device_t * dev) i915_dma_cleanup(dev); } -void i915_driver_preclose(drm_device_t * dev, DRMFILE filp) +void i915_driver_preclose(struct drm_device * dev, DRMFILE filp) { if (dev->dev_private) { drm_i915_private_t *dev_priv = dev->dev_private; @@ -969,7 +969,7 @@ void i915_driver_preclose(drm_device_t * dev, DRMFILE filp) } } -drm_ioctl_desc_t i915_ioctls[] = { +struct drm_ioctl_desc i915_ioctls[] = { [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH}, [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, DRM_AUTH}, @@ -1003,7 +1003,7 @@ int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); * \returns * A value of 1 is always retured to indictate every i9x5 is AGP. */ -int i915_driver_device_is_agp(drm_device_t * dev) +int i915_driver_device_is_agp(struct drm_device * dev) { return 1; } diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index e19d372a..1ed37c63 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -141,35 +141,35 @@ enum intel_chip_family { CHIP_I965 = 0x08, }; -extern drm_ioctl_desc_t i915_ioctls[]; +extern struct drm_ioctl_desc i915_ioctls[]; extern int i915_max_ioctl; /* i915_dma.c */ -extern void i915_kernel_lost_context(drm_device_t * dev); +extern void i915_kernel_lost_context(struct drm_device * dev); extern int i915_driver_load(struct drm_device *, unsigned long flags); -extern void i915_driver_lastclose(drm_device_t * dev); -extern void i915_driver_preclose(drm_device_t * dev, DRMFILE filp); -extern int i915_driver_device_is_agp(drm_device_t * dev); +extern void i915_driver_lastclose(struct drm_device * dev); +extern void i915_driver_preclose(struct drm_device * dev, DRMFILE filp); +extern int i915_driver_device_is_agp(struct drm_device * dev); extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); -extern void i915_emit_breadcrumb(drm_device_t *dev); -extern void i915_dispatch_flip(drm_device_t * dev, int pipes, int sync); -extern int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush); +extern void i915_emit_breadcrumb(struct drm_device *dev); +extern void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync); +extern int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush); extern int i915_driver_firstopen(struct drm_device *dev); /* i915_irq.c */ extern int i915_irq_emit(DRM_IOCTL_ARGS); extern int i915_irq_wait(DRM_IOCTL_ARGS); -extern int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); -extern int i915_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence); +extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence); +extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence); extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); -extern void i915_driver_irq_preinstall(drm_device_t * dev); -extern void i915_driver_irq_postinstall(drm_device_t * dev); -extern void i915_driver_irq_uninstall(drm_device_t * dev); +extern void i915_driver_irq_preinstall(struct drm_device * dev); +extern void i915_driver_irq_postinstall(struct drm_device * dev); +extern void i915_driver_irq_uninstall(struct drm_device * dev); extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS); extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS); -extern int i915_emit_irq(drm_device_t * dev); +extern int i915_emit_irq(struct drm_device * dev); extern void i915_user_irq_on(drm_i915_private_t *dev_priv); extern void i915_user_irq_off(drm_i915_private_t *dev_priv); extern int i915_vblank_swap(DRM_IOCTL_ARGS); @@ -180,27 +180,27 @@ extern int i915_mem_free(DRM_IOCTL_ARGS); extern int i915_mem_init_heap(DRM_IOCTL_ARGS); extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS); extern void i915_mem_takedown(struct mem_block **heap); -extern void i915_mem_release(drm_device_t * dev, +extern void i915_mem_release(struct drm_device * dev, DRMFILE filp, struct mem_block *heap); #ifdef I915_HAVE_FENCE /* i915_fence.c */ -extern void i915_fence_handler(drm_device_t *dev); -extern int i915_fence_emit_sequence(drm_device_t *dev, uint32_t class, +extern void i915_fence_handler(struct drm_device *dev); +extern int i915_fence_emit_sequence(struct drm_device *dev, uint32_t class, uint32_t flags, uint32_t *sequence, uint32_t *native_type); -extern void i915_poke_flush(drm_device_t *dev, uint32_t class); -extern int i915_fence_has_irq(drm_device_t *dev, uint32_t class, uint32_t flags); +extern void i915_poke_flush(struct drm_device *dev, uint32_t class); +extern int i915_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t flags); #endif #ifdef I915_HAVE_BUFFER /* i915_buffer.c */ -extern drm_ttm_backend_t *i915_create_ttm_backend_entry(drm_device_t *dev); +extern drm_ttm_backend_t *i915_create_ttm_backend_entry(struct drm_device *dev); extern int i915_fence_types(drm_buffer_object_t *bo, uint32_t *type); -extern int i915_invalidate_caches(drm_device_t *dev, uint64_t buffer_flags); -extern int i915_init_mem_type(drm_device_t *dev, uint32_t type, +extern int i915_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags); +extern int i915_init_mem_type(struct drm_device *dev, uint32_t type, drm_mem_type_manager_t *man); extern uint32_t i915_evict_mask(drm_buffer_object_t *bo); extern int i915_move(drm_buffer_object_t *bo, int evict, @@ -245,7 +245,7 @@ extern int i915_move(drm_buffer_object_t *bo, int evict, I915_WRITE(LP_RING + RING_TAIL, outring); \ } while(0) -extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller); +extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c index eb32e194..17cccac3 100644 --- a/shared-core/i915_irq.c +++ b/shared-core/i915_irq.c @@ -43,7 +43,7 @@ * This function must be called with the drawable spinlock held. */ static void -i915_dispatch_vsync_flip(drm_device_t *dev, struct drm_drawable_info *drw, +i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw, int pipe) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; @@ -87,7 +87,7 @@ i915_dispatch_vsync_flip(drm_device_t *dev, struct drm_drawable_info *drw, * * This function will be called with the HW lock held. */ -static void i915_vblank_tasklet(drm_device_t *dev) +static void i915_vblank_tasklet(struct drm_device *dev) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; unsigned long irqflags; @@ -277,7 +277,7 @@ static void i915_vblank_tasklet(drm_device_t *dev) irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) { - drm_device_t *dev = (drm_device_t *) arg; + struct drm_device *dev = (struct drm_device *) arg; drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; u16 temp; u32 pipea_stats, pipeb_stats; @@ -339,7 +339,7 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) return IRQ_HANDLED; } -int i915_emit_irq(drm_device_t * dev) +int i915_emit_irq(struct drm_device * dev) { drm_i915_private_t *dev_priv = dev->dev_private; @@ -383,7 +383,7 @@ void i915_user_irq_off(drm_i915_private_t *dev_priv) } -static int i915_wait_irq(drm_device_t * dev, int irq_nr) +static int i915_wait_irq(struct drm_device * dev, int irq_nr) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; int ret = 0; @@ -411,7 +411,7 @@ static int i915_wait_irq(drm_device_t * dev, int irq_nr) return ret; } -static int i915_driver_vblank_do_wait(drm_device_t *dev, unsigned int *sequence, +static int i915_driver_vblank_do_wait(struct drm_device *dev, unsigned int *sequence, atomic_t *counter) { drm_i915_private_t *dev_priv = dev->dev_private; @@ -432,12 +432,12 @@ static int i915_driver_vblank_do_wait(drm_device_t *dev, unsigned int *sequence, return ret; } -int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) +int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence) { return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received); } -int i915_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence) +int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence) { return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received2); } @@ -490,7 +490,7 @@ int i915_irq_wait(DRM_IOCTL_ARGS) return i915_wait_irq(dev, irqwait.irq_seq); } -static void i915_enable_interrupt (drm_device_t *dev) +static void i915_enable_interrupt (struct drm_device *dev) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; @@ -703,7 +703,7 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) /* drm_dma.h hooks */ -void i915_driver_irq_preinstall(drm_device_t * dev) +void i915_driver_irq_preinstall(struct drm_device * dev) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; @@ -712,7 +712,7 @@ void i915_driver_irq_preinstall(drm_device_t * dev) I915_WRITE16(I915REG_INT_ENABLE_R, 0x0); } -void i915_driver_irq_postinstall(drm_device_t * dev) +void i915_driver_irq_postinstall(struct drm_device * dev) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; @@ -733,7 +733,7 @@ void i915_driver_irq_postinstall(drm_device_t * dev) I915_WRITE(I915REG_INSTPM, ( 1 << 5) | ( 1 << 21)); } -void i915_driver_irq_uninstall(drm_device_t * dev) +void i915_driver_irq_uninstall(struct drm_device * dev) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; u16 temp; diff --git a/shared-core/i915_mem.c b/shared-core/i915_mem.c index c66edfab..582687ad 100644 --- a/shared-core/i915_mem.c +++ b/shared-core/i915_mem.c @@ -43,7 +43,7 @@ * block to allocate, and the ring is drained prior to allocations -- * in other words allocation is expensive. */ -static void mark_block(drm_device_t * dev, struct mem_block *p, int in_use) +static void mark_block(struct drm_device * dev, struct mem_block *p, int in_use) { drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -208,7 +208,7 @@ static int init_heap(struct mem_block **heap, int start, int size) /* Free all blocks associated with the releasing file. */ -void i915_mem_release(drm_device_t * dev, DRMFILE filp, struct mem_block *heap) +void i915_mem_release(struct drm_device * dev, DRMFILE filp, struct mem_block *heap) { struct mem_block *p; diff --git a/shared-core/mach64_dma.c b/shared-core/mach64_dma.c index 47340165..c787260a 100644 --- a/shared-core/mach64_dma.c +++ b/shared-core/mach64_dma.c @@ -572,7 +572,7 @@ void mach64_dump_ring_info(drm_mach64_private_t * dev_priv) * DMA operation. It is left here since it so tricky to get DMA operating * properly in some architectures and hardware. */ -static int mach64_bm_dma_test(drm_device_t * dev) +static int mach64_bm_dma_test(struct drm_device * dev) { drm_mach64_private_t *dev_priv = dev->dev_private; drm_dma_handle_t *cpu_addr_dmah; @@ -752,7 +752,7 @@ static int mach64_bm_dma_test(drm_device_t * dev) * Called during the DMA initialization ioctl to initialize all the necessary * software and hardware state for DMA operation. */ -static int mach64_do_dma_init(drm_device_t * dev, drm_mach64_init_t * init) +static int mach64_do_dma_init(struct drm_device * dev, drm_mach64_init_t * init) { drm_mach64_private_t *dev_priv; u32 tmp; @@ -1117,7 +1117,7 @@ int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t * dev_priv) /** \name DMA cleanup */ /*@{*/ -int mach64_do_cleanup_dma(drm_device_t * dev) +int mach64_do_cleanup_dma(struct drm_device * dev) { DRM_DEBUG("%s\n", __FUNCTION__); @@ -1223,9 +1223,9 @@ int mach64_engine_reset(DRM_IOCTL_ARGS) /** \name Freelist management */ /*@{*/ -int mach64_init_freelist(drm_device_t * dev) +int mach64_init_freelist(struct drm_device * dev) { - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_freelist_t *entry; struct list_head *ptr; @@ -1249,7 +1249,7 @@ int mach64_init_freelist(drm_device_t * dev) return 0; } -void mach64_destroy_freelist(drm_device_t * dev) +void mach64_destroy_freelist(struct drm_device * dev) { drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_freelist_t *entry; @@ -1461,7 +1461,7 @@ int mach64_freelist_put(drm_mach64_private_t * dev_priv, drm_buf_t * copy_buf) /** \name DMA buffer request and submission IOCTL handler */ /*@{*/ -static int mach64_dma_get_buffers(DRMFILE filp, drm_device_t * dev, +static int mach64_dma_get_buffers(DRMFILE filp, struct drm_device * dev, struct drm_dma * d) { int i; @@ -1530,7 +1530,7 @@ int mach64_dma_buffers(DRM_IOCTL_ARGS) return ret; } -void mach64_driver_lastclose(drm_device_t * dev) +void mach64_driver_lastclose(struct drm_device * dev) { mach64_do_cleanup_dma(dev); } diff --git a/shared-core/mach64_drv.h b/shared-core/mach64_drv.h index bb8b309e..31b8247a 100644 --- a/shared-core/mach64_drv.h +++ b/shared-core/mach64_drv.h @@ -108,7 +108,7 @@ typedef struct drm_mach64_private { drm_local_map_t *agp_textures; } drm_mach64_private_t; -extern drm_ioctl_desc_t mach64_ioctls[]; +extern struct drm_ioctl_desc mach64_ioctls[]; extern int mach64_max_ioctl; /* mach64_dma.c */ @@ -117,10 +117,10 @@ extern int mach64_dma_idle(DRM_IOCTL_ARGS); extern int mach64_dma_flush(DRM_IOCTL_ARGS); extern int mach64_engine_reset(DRM_IOCTL_ARGS); extern int mach64_dma_buffers(DRM_IOCTL_ARGS); -extern void mach64_driver_lastclose(drm_device_t * dev); +extern void mach64_driver_lastclose(struct drm_device * dev); -extern int mach64_init_freelist(drm_device_t * dev); -extern void mach64_destroy_freelist(drm_device_t * dev); +extern int mach64_init_freelist(struct drm_device * dev); +extern void mach64_destroy_freelist(struct drm_device * dev); extern drm_buf_t *mach64_freelist_get(drm_mach64_private_t * dev_priv); extern int mach64_freelist_put(drm_mach64_private_t * dev_priv, drm_buf_t * copy_buf); @@ -137,7 +137,7 @@ extern int mach64_do_engine_reset(drm_mach64_private_t * dev_priv); extern int mach64_do_dma_idle(drm_mach64_private_t * dev_priv); extern int mach64_do_dma_flush(drm_mach64_private_t * dev_priv); -extern int mach64_do_cleanup_dma(drm_device_t * dev); +extern int mach64_do_cleanup_dma(struct drm_device * dev); /* mach64_state.c */ extern int mach64_dma_clear(DRM_IOCTL_ARGS); @@ -145,13 +145,13 @@ extern int mach64_dma_swap(DRM_IOCTL_ARGS); extern int mach64_dma_vertex(DRM_IOCTL_ARGS); extern int mach64_dma_blit(DRM_IOCTL_ARGS); extern int mach64_get_param(DRM_IOCTL_ARGS); -extern int mach64_driver_vblank_wait(drm_device_t * dev, +extern int mach64_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence); extern irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS); -extern void mach64_driver_irq_preinstall(drm_device_t * dev); -extern void mach64_driver_irq_postinstall(drm_device_t * dev); -extern void mach64_driver_irq_uninstall(drm_device_t * dev); +extern void mach64_driver_irq_preinstall(struct drm_device * dev); +extern void mach64_driver_irq_postinstall(struct drm_device * dev); +extern void mach64_driver_irq_uninstall(struct drm_device * dev); /* ================================================================ * Registers diff --git a/shared-core/mach64_irq.c b/shared-core/mach64_irq.c index 663642db..4122dd91 100644 --- a/shared-core/mach64_irq.c +++ b/shared-core/mach64_irq.c @@ -42,7 +42,7 @@ irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS) { - drm_device_t *dev = (drm_device_t *) arg; + struct drm_device *dev = (struct drm_device *) arg; drm_mach64_private_t *dev_priv = (drm_mach64_private_t *) dev->dev_private; int status; @@ -70,7 +70,7 @@ irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS) return IRQ_NONE; } -int mach64_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) +int mach64_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence) { unsigned int cur_vblank; int ret = 0; @@ -90,7 +90,7 @@ int mach64_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) /* drm_dma.h hooks */ -void mach64_driver_irq_preinstall(drm_device_t * dev) +void mach64_driver_irq_preinstall(struct drm_device * dev) { drm_mach64_private_t *dev_priv = (drm_mach64_private_t *) dev->dev_private; @@ -104,7 +104,7 @@ void mach64_driver_irq_preinstall(drm_device_t * dev) | MACH64_CRTC_VBLANK_INT); } -void mach64_driver_irq_postinstall(drm_device_t * dev) +void mach64_driver_irq_postinstall(struct drm_device * dev) { drm_mach64_private_t *dev_priv = (drm_mach64_private_t *) dev->dev_private; @@ -118,7 +118,7 @@ void mach64_driver_irq_postinstall(drm_device_t * dev) } -void mach64_driver_irq_uninstall(drm_device_t * dev) +void mach64_driver_irq_uninstall(struct drm_device * dev) { drm_mach64_private_t *dev_priv = (drm_mach64_private_t *) dev->dev_private; diff --git a/shared-core/mach64_state.c b/shared-core/mach64_state.c index a1047cbd..4e8291af 100644 --- a/shared-core/mach64_state.c +++ b/shared-core/mach64_state.c @@ -40,7 +40,7 @@ * 1.0 - Initial mach64 DRM * */ -drm_ioctl_desc_t mach64_ioctls[] = { +struct drm_ioctl_desc mach64_ioctls[] = { [DRM_IOCTL_NR(DRM_MACH64_INIT)] = {mach64_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, [DRM_IOCTL_NR(DRM_MACH64_CLEAR)] = {mach64_dma_clear, DRM_AUTH}, [DRM_IOCTL_NR(DRM_MACH64_SWAP)] = {mach64_dma_swap, DRM_AUTH}, @@ -212,7 +212,7 @@ static __inline__ int mach64_emit_state(DRMFILE filp, * DMA command dispatch functions */ -static int mach64_dma_dispatch_clear(DRMFILE filp, drm_device_t * dev, +static int mach64_dma_dispatch_clear(DRMFILE filp, struct drm_device * dev, unsigned int flags, int cx, int cy, int cw, int ch, unsigned int clear_color, @@ -355,7 +355,7 @@ static int mach64_dma_dispatch_clear(DRMFILE filp, drm_device_t * dev, return 0; } -static int mach64_dma_dispatch_swap(DRMFILE filp, drm_device_t * dev) +static int mach64_dma_dispatch_swap(DRMFILE filp, struct drm_device * dev) { drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -545,7 +545,7 @@ static __inline__ int copy_from_user_vertex(u32 *to, } } -static int mach64_dma_dispatch_vertex(DRMFILE filp, drm_device_t * dev, +static int mach64_dma_dispatch_vertex(DRMFILE filp, struct drm_device * dev, drm_mach64_vertex_t * vertex) { drm_mach64_private_t *dev_priv = dev->dev_private; @@ -640,7 +640,7 @@ static __inline__ int copy_from_user_blit(u32 *to, return 0; } -static int mach64_dma_dispatch_blit(DRMFILE filp, drm_device_t * dev, +static int mach64_dma_dispatch_blit(DRMFILE filp, struct drm_device * dev, drm_mach64_blit_t * blit) { drm_mach64_private_t *dev_priv = dev->dev_private; diff --git a/shared-core/mga_dma.c b/shared-core/mga_dma.c index ea6212fe..0a3c2729 100644 --- a/shared-core/mga_dma.c +++ b/shared-core/mga_dma.c @@ -46,7 +46,7 @@ #define MINIMAL_CLEANUP 0 #define FULL_CLEANUP 1 -static int mga_do_cleanup_dma(drm_device_t * dev, int full_cleanup); +static int mga_do_cleanup_dma(struct drm_device * dev, int full_cleanup); /* ================================================================ * Engine control @@ -224,7 +224,7 @@ void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv) #define MGA_BUFFER_FREE 0 #if MGA_FREELIST_DEBUG -static void mga_freelist_print(drm_device_t * dev) +static void mga_freelist_print(struct drm_device * dev) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_freelist_t *entry; @@ -245,10 +245,10 @@ static void mga_freelist_print(drm_device_t * dev) } #endif -static int mga_freelist_init(drm_device_t * dev, drm_mga_private_t * dev_priv) +static int mga_freelist_init(struct drm_device * dev, drm_mga_private_t * dev_priv) { - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; + struct drm_device_dma *dma = dev->dma; + struct drm_buf *buf; drm_mga_buf_priv_t *buf_priv; drm_mga_freelist_t *entry; int i; @@ -291,7 +291,7 @@ static int mga_freelist_init(drm_device_t * dev, drm_mga_private_t * dev_priv) return 0; } -static void mga_freelist_cleanup(drm_device_t * dev) +static void mga_freelist_cleanup(struct drm_device * dev) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_freelist_t *entry; @@ -311,7 +311,7 @@ static void mga_freelist_cleanup(drm_device_t * dev) #if 0 /* FIXME: Still needed? */ -static void mga_freelist_reset(drm_device_t * dev) +static void mga_freelist_reset(struct drm_device * dev) { drm_device_dma_t *dma = dev->dma; drm_buf_t *buf; @@ -326,7 +326,7 @@ static void mga_freelist_reset(drm_device_t * dev) } #endif -static drm_buf_t *mga_freelist_get(drm_device_t * dev) +static drm_buf_t *mga_freelist_get(struct drm_device * dev) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_freelist_t *next; @@ -359,7 +359,7 @@ static drm_buf_t *mga_freelist_get(drm_device_t * dev) return NULL; } -int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf) +int mga_freelist_put(struct drm_device * dev, drm_buf_t * buf) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; @@ -393,7 +393,7 @@ int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf) * DMA initialization, cleanup */ -int mga_driver_load(drm_device_t *dev, unsigned long flags) +int mga_driver_load(struct drm_device *dev, unsigned long flags) { drm_mga_private_t * dev_priv; @@ -433,7 +433,7 @@ int mga_driver_load(drm_device_t *dev, unsigned long flags) * * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap */ -static int mga_do_agp_dma_bootstrap(drm_device_t * dev, +static int mga_do_agp_dma_bootstrap(struct drm_device *dev, drm_mga_dma_bootstrap_t * dma_bs) { drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private; @@ -548,7 +548,7 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev, #ifdef __linux__ { - drm_map_list_t *_entry; + struct drm_map_list *_entry; unsigned long agp_token = 0; list_for_each_entry(_entry, &dev->maplist, head) { @@ -603,7 +603,7 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev, * * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap */ -static int mga_do_pci_dma_bootstrap(drm_device_t * dev, +static int mga_do_pci_dma_bootstrap(struct drm_device * dev, drm_mga_dma_bootstrap_t * dma_bs) { drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private; @@ -696,7 +696,7 @@ static int mga_do_pci_dma_bootstrap(drm_device_t * dev, } -static int mga_do_dma_bootstrap(drm_device_t * dev, +static int mga_do_dma_bootstrap(struct drm_device * dev, drm_mga_dma_bootstrap_t * dma_bs) { const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev); @@ -799,7 +799,7 @@ int mga_dma_bootstrap(DRM_IOCTL_ARGS) } -static int mga_do_init_dma(drm_device_t * dev, drm_mga_init_t * init) +static int mga_do_init_dma(struct drm_device * dev, drm_mga_init_t * init) { drm_mga_private_t *dev_priv; int ret; @@ -939,7 +939,7 @@ static int mga_do_init_dma(drm_device_t * dev, drm_mga_init_t * init) return 0; } -static int mga_do_cleanup_dma(drm_device_t * dev, int full_cleanup) +static int mga_do_cleanup_dma(struct drm_device * dev, int full_cleanup) { int err = 0; DRM_DEBUG("\n"); @@ -1089,7 +1089,7 @@ int mga_dma_reset(DRM_IOCTL_ARGS) * DMA buffer management */ -static int mga_dma_get_buffers(DRMFILE filp, drm_device_t * dev, struct drm_dma * d) +static int mga_dma_get_buffers(DRMFILE filp, struct drm_device * dev, struct drm_dma * d) { drm_buf_t *buf; int i; @@ -1116,7 +1116,7 @@ static int mga_dma_get_buffers(DRMFILE filp, drm_device_t * dev, struct drm_dma int mga_dma_buffers(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; struct drm_dma __user *argp = (void __user *)data; struct drm_dma d; @@ -1158,7 +1158,7 @@ int mga_dma_buffers(DRM_IOCTL_ARGS) /** * Called just before the module is unloaded. */ -int mga_driver_unload(drm_device_t * dev) +int mga_driver_unload(struct drm_device * dev) { drm_free(dev->dev_private, sizeof(drm_mga_private_t), DRM_MEM_DRIVER); dev->dev_private = NULL; @@ -1169,12 +1169,12 @@ int mga_driver_unload(drm_device_t * dev) /** * Called when the last opener of the device is closed. */ -void mga_driver_lastclose(drm_device_t * dev) +void mga_driver_lastclose(struct drm_device * dev) { mga_do_cleanup_dma(dev, FULL_CLEANUP); } -int mga_driver_dma_quiescent(drm_device_t * dev) +int mga_driver_dma_quiescent(struct drm_device * dev) { drm_mga_private_t *dev_priv = dev->dev_private; return mga_do_wait_for_idle(dev_priv); diff --git a/shared-core/mga_drv.h b/shared-core/mga_drv.h index bce82135..e1fdf403 100644 --- a/shared-core/mga_drv.h +++ b/shared-core/mga_drv.h @@ -148,7 +148,7 @@ typedef struct drm_mga_private { unsigned int agp_size; } drm_mga_private_t; -extern drm_ioctl_desc_t mga_ioctls[]; +extern struct drm_ioctl_desc mga_ioctls[]; extern int mga_max_ioctl; /* mga_dma.c */ @@ -157,10 +157,10 @@ extern int mga_dma_init(DRM_IOCTL_ARGS); extern int mga_dma_flush(DRM_IOCTL_ARGS); extern int mga_dma_reset(DRM_IOCTL_ARGS); extern int mga_dma_buffers(DRM_IOCTL_ARGS); -extern int mga_driver_load(drm_device_t *dev, unsigned long flags); -extern int mga_driver_unload(drm_device_t * dev); -extern void mga_driver_lastclose(drm_device_t * dev); -extern int mga_driver_dma_quiescent(drm_device_t * dev); +extern int mga_driver_load(struct drm_device *dev, unsigned long flags); +extern int mga_driver_unload(struct drm_device * dev); +extern void mga_driver_lastclose(struct drm_device * dev); +extern int mga_driver_dma_quiescent(struct drm_device * dev); extern int mga_do_wait_for_idle(drm_mga_private_t * dev_priv); @@ -168,7 +168,7 @@ extern void mga_do_dma_flush(drm_mga_private_t * dev_priv); extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv); extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv); -extern int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf); +extern int mga_freelist_put(struct drm_device * dev, drm_buf_t * buf); /* mga_warp.c */ extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv); @@ -176,12 +176,12 @@ extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv); extern int mga_warp_init(drm_mga_private_t * dev_priv); /* mga_irq.c */ -extern int mga_driver_fence_wait(drm_device_t * dev, unsigned int *sequence); -extern int mga_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence); +extern int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence); +extern int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence); extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS); -extern void mga_driver_irq_preinstall(drm_device_t * dev); -extern void mga_driver_irq_postinstall(drm_device_t * dev); -extern void mga_driver_irq_uninstall(drm_device_t * dev); +extern void mga_driver_irq_preinstall(struct drm_device * dev); +extern void mga_driver_irq_postinstall(struct drm_device * dev); +extern void mga_driver_irq_uninstall(struct drm_device * dev); extern long mga_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); diff --git a/shared-core/mga_irq.c b/shared-core/mga_irq.c index 490d1fbb..8b555e2e 100644 --- a/shared-core/mga_irq.c +++ b/shared-core/mga_irq.c @@ -38,7 +38,7 @@ irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS) { - drm_device_t *dev = (drm_device_t *) arg; + struct drm_device *dev = (struct drm_device *) arg; drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; int status; int handled = 0; @@ -80,7 +80,7 @@ irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS) return IRQ_NONE; } -int mga_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) +int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence) { unsigned int cur_vblank; int ret = 0; @@ -98,7 +98,7 @@ int mga_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) return ret; } -int mga_driver_fence_wait(drm_device_t * dev, unsigned int *sequence) +int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence) { drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; unsigned int cur_fence; @@ -117,7 +117,7 @@ int mga_driver_fence_wait(drm_device_t * dev, unsigned int *sequence) return ret; } -void mga_driver_irq_preinstall(drm_device_t * dev) +void mga_driver_irq_preinstall(struct drm_device * dev) { drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; @@ -127,7 +127,7 @@ void mga_driver_irq_preinstall(drm_device_t * dev) MGA_WRITE(MGA_ICLEAR, ~0); } -void mga_driver_irq_postinstall(drm_device_t * dev) +void mga_driver_irq_postinstall(struct drm_device * dev) { drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; @@ -137,7 +137,7 @@ void mga_driver_irq_postinstall(drm_device_t * dev) MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN); } -void mga_driver_irq_uninstall(drm_device_t * dev) +void mga_driver_irq_uninstall(struct drm_device * dev) { drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; if (!dev_priv) diff --git a/shared-core/mga_state.c b/shared-core/mga_state.c index 527f6ce7..72db0ced 100644 --- a/shared-core/mga_state.c +++ b/shared-core/mga_state.c @@ -504,7 +504,7 @@ static int mga_verify_blit(drm_mga_private_t * dev_priv, * */ -static void mga_dma_dispatch_clear(drm_device_t * dev, drm_mga_clear_t * clear) +static void mga_dma_dispatch_clear(struct drm_device * dev, drm_mga_clear_t * clear) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -594,7 +594,7 @@ static void mga_dma_dispatch_clear(drm_device_t * dev, drm_mga_clear_t * clear) FLUSH_DMA(); } -static void mga_dma_dispatch_swap(drm_device_t * dev) +static void mga_dma_dispatch_swap(struct drm_device * dev) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -651,7 +651,7 @@ static void mga_dma_dispatch_swap(drm_device_t * dev) DRM_DEBUG("%s... done.\n", __FUNCTION__); } -static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf) +static void mga_dma_dispatch_vertex(struct drm_device * dev, drm_buf_t * buf) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; @@ -698,7 +698,7 @@ static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf) FLUSH_DMA(); } -static void mga_dma_dispatch_indices(drm_device_t * dev, drm_buf_t * buf, +static void mga_dma_dispatch_indices(struct drm_device * dev, drm_buf_t * buf, unsigned int start, unsigned int end) { drm_mga_private_t *dev_priv = dev->dev_private; @@ -747,7 +747,7 @@ static void mga_dma_dispatch_indices(drm_device_t * dev, drm_buf_t * buf, /* This copies a 64 byte aligned agp region to the frambuffer with a * standard blit, the ioctl needs to do checking. */ -static void mga_dma_dispatch_iload(drm_device_t * dev, drm_buf_t * buf, +static void mga_dma_dispatch_iload(struct drm_device * dev, drm_buf_t * buf, unsigned int dstorg, unsigned int length) { drm_mga_private_t *dev_priv = dev->dev_private; @@ -800,7 +800,7 @@ static void mga_dma_dispatch_iload(drm_device_t * dev, drm_buf_t * buf, FLUSH_DMA(); } -static void mga_dma_dispatch_blit(drm_device_t * dev, drm_mga_blit_t * blit) +static void mga_dma_dispatch_blit(struct drm_device * dev, drm_mga_blit_t * blit) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -917,8 +917,8 @@ static int mga_dma_vertex(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; + struct drm_device_dma *dma = dev->dma; + struct drm_buf *buf; drm_mga_buf_priv_t *buf_priv; drm_mga_vertex_t vertex; @@ -957,8 +957,8 @@ static int mga_dma_indices(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; + struct drm_device_dma *dma = dev->dma; + struct drm_buf *buf; drm_mga_buf_priv_t *buf_priv; drm_mga_indices_t indices; @@ -996,7 +996,7 @@ static int mga_dma_indices(DRM_IOCTL_ARGS) static int mga_dma_iload(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; drm_mga_private_t *dev_priv = dev->dev_private; drm_buf_t *buf; drm_mga_buf_priv_t *buf_priv; @@ -1158,7 +1158,7 @@ static int mga_wait_fence(DRM_IOCTL_ARGS) return 0; } -drm_ioctl_desc_t mga_ioctls[] = { +struct drm_ioctl_desc mga_ioctls[] = { [DRM_IOCTL_NR(DRM_MGA_INIT)] = {mga_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = {mga_dma_flush, DRM_AUTH}, [DRM_IOCTL_NR(DRM_MGA_RESET)] = {mga_dma_reset, DRM_AUTH}, diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 236dd4a1..56c25a6e 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -469,7 +469,7 @@ static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) DRM_DEVICE; struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_fifo_alloc init; - drm_map_list_t *entry; + struct drm_map_list *entry; struct nouveau_fifo *chan; int res; @@ -526,7 +526,7 @@ static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) * finally, the ioctl table ***********************************/ -drm_ioctl_desc_t nouveau_ioctls[] = { +struct drm_ioctl_desc nouveau_ioctls[] = { [DRM_IOCTL_NR(DRM_NOUVEAU_FIFO_ALLOC)] = {nouveau_ioctl_fifo_alloc, DRM_AUTH}, [DRM_IOCTL_NR(DRM_NOUVEAU_GROBJ_ALLOC)] = {nouveau_ioctl_grobj_alloc, DRM_AUTH}, [DRM_IOCTL_NR(DRM_NOUVEAU_NOTIFIER_ALLOC)] = {nouveau_ioctl_notifier_alloc, DRM_AUTH}, diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index ef9df359..e5906867 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -469,7 +469,7 @@ alloc_ok: if (flags&NOUVEAU_MEM_MAPPED) { - drm_map_list_t *entry; + struct drm_map_list *entry; int ret = 0; block->flags|=NOUVEAU_MEM_MAPPED; diff --git a/shared-core/r128_cce.c b/shared-core/r128_cce.c index 2d650b47..167fc070 100644 --- a/shared-core/r128_cce.c +++ b/shared-core/r128_cce.c @@ -81,7 +81,7 @@ static u32 r128_cce_microcode[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; -static int R128_READ_PLL(drm_device_t * dev, int addr) +static int R128_READ_PLL(struct drm_device * dev, int addr) { drm_r128_private_t *dev_priv = dev->dev_private; @@ -271,7 +271,7 @@ static void r128_do_cce_stop(drm_r128_private_t * dev_priv) /* Reset the engine. This will stop the CCE if it is running. */ -static int r128_do_engine_reset(drm_device_t * dev) +static int r128_do_engine_reset(struct drm_device * dev) { drm_r128_private_t *dev_priv = dev->dev_private; u32 clock_cntl_index, mclk_cntl, gen_reset_cntl; @@ -308,7 +308,7 @@ static int r128_do_engine_reset(drm_device_t * dev) return 0; } -static void r128_cce_init_ring_buffer(drm_device_t * dev, +static void r128_cce_init_ring_buffer(struct drm_device * dev, drm_r128_private_t * dev_priv) { u32 ring_start; @@ -347,7 +347,7 @@ static void r128_cce_init_ring_buffer(drm_device_t * dev, R128_WRITE(R128_BUS_CNTL, tmp); } -static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init) +static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) { drm_r128_private_t *dev_priv; @@ -584,7 +584,7 @@ static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init) return 0; } -int r128_do_cleanup_cce(drm_device_t * dev) +int r128_do_cleanup_cce(struct drm_device * dev) { /* Make sure interrupts are disabled here because the uninstall ioctl @@ -767,11 +767,11 @@ int r128_fullscreen(DRM_IOCTL_ARGS) #define R128_BUFFER_FREE 0 #if 0 -static int r128_freelist_init(drm_device_t * dev) +static int r128_freelist_init(struct drm_device * dev) { - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; drm_r128_private_t *dev_priv = dev->dev_private; - drm_buf_t *buf; + struct drm_buf *buf; drm_r128_buf_priv_t *buf_priv; drm_r128_freelist_t *entry; int i; @@ -813,12 +813,12 @@ static int r128_freelist_init(drm_device_t * dev) } #endif -static drm_buf_t *r128_freelist_get(drm_device_t * dev) +static struct drm_buf *r128_freelist_get(struct drm_device * dev) { - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_buf_priv_t *buf_priv; - drm_buf_t *buf; + struct drm_buf *buf; int i, t; /* FIXME: Optimize -- use freelist code */ @@ -851,13 +851,13 @@ static drm_buf_t *r128_freelist_get(drm_device_t * dev) return NULL; } -void r128_freelist_reset(drm_device_t * dev) +void r128_freelist_reset(struct drm_device * dev) { - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; int i; for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[i]; + struct drm_buf *buf = dma->buflist[i]; drm_r128_buf_priv_t *buf_priv = buf->dev_private; buf_priv->age = 0; } @@ -884,10 +884,10 @@ int r128_wait_ring(drm_r128_private_t * dev_priv, int n) return DRM_ERR(EBUSY); } -static int r128_cce_get_buffers(DRMFILE filp, drm_device_t * dev, struct drm_dma * d) +static int r128_cce_get_buffers(DRMFILE filp, struct drm_device * dev, struct drm_dma * d) { int i; - drm_buf_t *buf; + struct drm_buf *buf; for (i = d->granted_count; i < d->request_count; i++) { buf = r128_freelist_get(dev); @@ -911,7 +911,7 @@ static int r128_cce_get_buffers(DRMFILE filp, drm_device_t * dev, struct drm_dma int r128_cce_buffers(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; int ret = 0; struct drm_dma __user *argp = (void __user *)data; struct drm_dma d; diff --git a/shared-core/r128_drv.h b/shared-core/r128_drv.h index 90868356..0791713a 100644 --- a/shared-core/r128_drv.h +++ b/shared-core/r128_drv.h @@ -118,7 +118,7 @@ typedef struct drm_r128_private { drm_local_map_t *cce_ring; drm_local_map_t *ring_rptr; drm_local_map_t *agp_textures; - drm_ati_pcigart_info gart_info; + struct ati_pcigart_info gart_info; } drm_r128_private_t; typedef struct drm_r128_buf_priv { @@ -129,7 +129,7 @@ typedef struct drm_r128_buf_priv { drm_r128_freelist_t *list_entry; } drm_r128_buf_priv_t; -extern drm_ioctl_desc_t r128_ioctls[]; +extern struct drm_ioctl_desc r128_ioctls[]; extern int r128_max_ioctl; /* r128_cce.c */ @@ -142,21 +142,21 @@ extern int r128_engine_reset(DRM_IOCTL_ARGS); extern int r128_fullscreen(DRM_IOCTL_ARGS); extern int r128_cce_buffers(DRM_IOCTL_ARGS); -extern void r128_freelist_reset(drm_device_t * dev); +extern void r128_freelist_reset(struct drm_device * dev); extern int r128_wait_ring(drm_r128_private_t * dev_priv, int n); extern int r128_do_cce_idle(drm_r128_private_t * dev_priv); -extern int r128_do_cleanup_cce(drm_device_t * dev); +extern int r128_do_cleanup_cce(struct drm_device * dev); -extern int r128_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence); +extern int r128_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence); extern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS); -extern void r128_driver_irq_preinstall(drm_device_t * dev); -extern void r128_driver_irq_postinstall(drm_device_t * dev); -extern void r128_driver_irq_uninstall(drm_device_t * dev); -extern void r128_driver_lastclose(drm_device_t * dev); -extern void r128_driver_preclose(drm_device_t * dev, DRMFILE filp); +extern void r128_driver_irq_preinstall(struct drm_device * dev); +extern void r128_driver_irq_postinstall(struct drm_device * dev); +extern void r128_driver_irq_uninstall(struct drm_device * dev); +extern void r128_driver_lastclose(struct drm_device * dev); +extern void r128_driver_preclose(struct drm_device * dev, DRMFILE filp); extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); diff --git a/shared-core/r128_irq.c b/shared-core/r128_irq.c index 87f8ca2b..c76fdca7 100644 --- a/shared-core/r128_irq.c +++ b/shared-core/r128_irq.c @@ -37,7 +37,7 @@ irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS) { - drm_device_t *dev = (drm_device_t *) arg; + struct drm_device *dev = (struct drm_device *) arg; drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; int status; @@ -54,7 +54,7 @@ irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS) return IRQ_NONE; } -int r128_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) +int r128_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence) { unsigned int cur_vblank; int ret = 0; @@ -72,7 +72,7 @@ int r128_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) return ret; } -void r128_driver_irq_preinstall(drm_device_t * dev) +void r128_driver_irq_preinstall(struct drm_device * dev) { drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; @@ -82,7 +82,7 @@ void r128_driver_irq_preinstall(drm_device_t * dev) R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK); } -void r128_driver_irq_postinstall(drm_device_t * dev) +void r128_driver_irq_postinstall(struct drm_device * dev) { drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; @@ -90,7 +90,7 @@ void r128_driver_irq_postinstall(drm_device_t * dev) R128_WRITE(R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN); } -void r128_driver_irq_uninstall(drm_device_t * dev) +void r128_driver_irq_uninstall(struct drm_device * dev) { drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; if (!dev_priv) diff --git a/shared-core/r128_state.c b/shared-core/r128_state.c index 565e0d4f..b793d94b 100644 --- a/shared-core/r128_state.c +++ b/shared-core/r128_state.c @@ -352,7 +352,7 @@ static void r128_print_dirty(const char *msg, unsigned int flags) (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : ""); } -static void r128_cce_dispatch_clear(drm_device_t * dev, +static void r128_cce_dispatch_clear(struct drm_device * dev, drm_r128_clear_t * clear) { drm_r128_private_t *dev_priv = dev->dev_private; @@ -458,7 +458,7 @@ static void r128_cce_dispatch_clear(drm_device_t * dev, } } -static void r128_cce_dispatch_swap(drm_device_t * dev) +static void r128_cce_dispatch_swap(struct drm_device * dev) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -524,7 +524,7 @@ static void r128_cce_dispatch_swap(drm_device_t * dev) ADVANCE_RING(); } -static void r128_cce_dispatch_flip(drm_device_t * dev) +static void r128_cce_dispatch_flip(struct drm_device * dev) { drm_r128_private_t *dev_priv = dev->dev_private; RING_LOCALS; @@ -567,7 +567,7 @@ static void r128_cce_dispatch_flip(drm_device_t * dev) ADVANCE_RING(); } -static void r128_cce_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf) +static void r128_cce_dispatch_vertex(struct drm_device * dev, struct drm_buf * buf) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_buf_priv_t *buf_priv = buf->dev_private; @@ -637,8 +637,8 @@ static void r128_cce_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf) sarea_priv->nbox = 0; } -static void r128_cce_dispatch_indirect(drm_device_t * dev, - drm_buf_t * buf, int start, int end) +static void r128_cce_dispatch_indirect(struct drm_device * dev, + struct drm_buf * buf, int start, int end) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_buf_priv_t *buf_priv = buf->dev_private; @@ -692,8 +692,8 @@ static void r128_cce_dispatch_indirect(drm_device_t * dev, dev_priv->sarea_priv->last_dispatch++; } -static void r128_cce_dispatch_indices(drm_device_t * dev, - drm_buf_t * buf, +static void r128_cce_dispatch_indices(struct drm_device * dev, + struct drm_buf * buf, int start, int end, int count) { drm_r128_private_t *dev_priv = dev->dev_private; @@ -777,11 +777,11 @@ static void r128_cce_dispatch_indices(drm_device_t * dev, } static int r128_cce_dispatch_blit(DRMFILE filp, - drm_device_t * dev, drm_r128_blit_t * blit) + struct drm_device * dev, drm_r128_blit_t * blit) { drm_r128_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; + struct drm_device_dma *dma = dev->dma; + struct drm_buf *buf; drm_r128_buf_priv_t *buf_priv; u32 *data; int dword_shift, dwords; @@ -887,7 +887,7 @@ static int r128_cce_dispatch_blit(DRMFILE filp, * have hardware stencil support. */ -static int r128_cce_dispatch_write_span(drm_device_t * dev, +static int r128_cce_dispatch_write_span(struct drm_device * dev, drm_r128_depth_t * depth) { drm_r128_private_t *dev_priv = dev->dev_private; @@ -983,7 +983,7 @@ static int r128_cce_dispatch_write_span(drm_device_t * dev, return 0; } -static int r128_cce_dispatch_write_pixels(drm_device_t * dev, +static int r128_cce_dispatch_write_pixels(struct drm_device * dev, drm_r128_depth_t * depth) { drm_r128_private_t *dev_priv = dev->dev_private; @@ -1105,7 +1105,7 @@ static int r128_cce_dispatch_write_pixels(drm_device_t * dev, return 0; } -static int r128_cce_dispatch_read_span(drm_device_t * dev, +static int r128_cce_dispatch_read_span(struct drm_device * dev, drm_r128_depth_t * depth) { drm_r128_private_t *dev_priv = dev->dev_private; @@ -1148,7 +1148,7 @@ static int r128_cce_dispatch_read_span(drm_device_t * dev, return 0; } -static int r128_cce_dispatch_read_pixels(drm_device_t * dev, +static int r128_cce_dispatch_read_pixels(struct drm_device * dev, drm_r128_depth_t * depth) { drm_r128_private_t *dev_priv = dev->dev_private; @@ -1220,7 +1220,7 @@ static int r128_cce_dispatch_read_pixels(drm_device_t * dev, * Polygon stipple */ -static void r128_cce_dispatch_stipple(drm_device_t * dev, u32 * stipple) +static void r128_cce_dispatch_stipple(struct drm_device * dev, u32 * stipple) { drm_r128_private_t *dev_priv = dev->dev_private; int i; @@ -1269,7 +1269,7 @@ static int r128_cce_clear(DRM_IOCTL_ARGS) return 0; } -static int r128_do_init_pageflip(drm_device_t * dev) +static int r128_do_init_pageflip(struct drm_device * dev) { drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); @@ -1288,7 +1288,7 @@ static int r128_do_init_pageflip(drm_device_t * dev) return 0; } -static int r128_do_cleanup_pageflip(drm_device_t * dev) +static int r128_do_cleanup_pageflip(struct drm_device * dev) { drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); @@ -1354,8 +1354,8 @@ static int r128_cce_vertex(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; + struct drm_device_dma *dma = dev->dma; + struct drm_buf *buf; drm_r128_buf_priv_t *buf_priv; drm_r128_vertex_t vertex; @@ -1413,8 +1413,8 @@ static int r128_cce_indices(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; + struct drm_device_dma *dma = dev->dma; + struct drm_buf *buf; drm_r128_buf_priv_t *buf_priv; drm_r128_indices_t elts; int count; @@ -1483,7 +1483,7 @@ static int r128_cce_indices(DRM_IOCTL_ARGS) static int r128_cce_blit(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_blit_t blit; int ret; @@ -1571,8 +1571,8 @@ static int r128_cce_indirect(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; + struct drm_device_dma *dma = dev->dma; + struct drm_buf *buf; drm_r128_buf_priv_t *buf_priv; drm_r128_indirect_t indirect; #if 0 @@ -1675,7 +1675,7 @@ static int r128_getparam(DRM_IOCTL_ARGS) return 0; } -void r128_driver_preclose(drm_device_t * dev, DRMFILE filp) +void r128_driver_preclose(struct drm_device * dev, DRMFILE filp) { if (dev->dev_private) { drm_r128_private_t *dev_priv = dev->dev_private; @@ -1685,12 +1685,12 @@ void r128_driver_preclose(drm_device_t * dev, DRMFILE filp) } } -void r128_driver_lastclose(drm_device_t * dev) +void r128_driver_lastclose(struct drm_device * dev) { r128_do_cleanup_cce(dev); } -drm_ioctl_desc_t r128_ioctls[] = { +struct drm_ioctl_desc r128_ioctls[] = { [DRM_IOCTL_NR(DRM_R128_INIT)] = {r128_cce_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, [DRM_IOCTL_NR(DRM_R128_CCE_START)] = {r128_cce_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, [DRM_IOCTL_NR(DRM_R128_CCE_STOP)] = {r128_cce_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, diff --git a/shared-core/r300_cmdbuf.c b/shared-core/r300_cmdbuf.c index ab4f1cae..08015ecf 100644 --- a/shared-core/r300_cmdbuf.c +++ b/shared-core/r300_cmdbuf.c @@ -706,7 +706,7 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv) * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must * be careful about how this function is called. */ -static void r300_discard_buffer(drm_device_t * dev, drm_buf_t * buf) +static void r300_discard_buffer(struct drm_device * dev, drm_buf_t * buf) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_buf_priv_t *buf_priv = buf->dev_private; @@ -778,13 +778,13 @@ static int r300_scratch(drm_radeon_private_t *dev_priv, * commands on the DMA ring buffer. * Called by the ioctl handler function radeon_cp_cmdbuf. */ -int r300_do_cp_cmdbuf(drm_device_t *dev, +int r300_do_cp_cmdbuf(struct drm_device *dev, DRMFILE filp, - drm_file_t *filp_priv, + struct drm_file *filp_priv, drm_radeon_kcmd_buffer_t *cmdbuf) { drm_radeon_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; drm_buf_t *buf = NULL; int emit_dispatch_age = 0; int ret = 0; diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index ba06443f..cef47ca0 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -36,7 +36,7 @@ #define RADEON_FIFO_DEBUG 0 -static int radeon_do_cleanup_cp(drm_device_t * dev); +static int radeon_do_cleanup_cp(struct drm_device * dev); /* CP microcode (from ATI) */ static const u32 R200_cp_microcode[][2] = { @@ -816,7 +816,7 @@ static const u32 R300_cp_microcode[][2] = { { 0000000000, 0000000000 }, }; -static int RADEON_READ_PLL(drm_device_t * dev, int addr) +static int RADEON_READ_PLL(struct drm_device * dev, int addr) { drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1066,7 +1066,7 @@ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) /* Reset the engine. This will stop the CP if it is running. */ -static int radeon_do_engine_reset(drm_device_t * dev) +static int radeon_do_engine_reset(struct drm_device * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; @@ -1122,7 +1122,7 @@ static int radeon_do_engine_reset(drm_device_t * dev) return 0; } -static void radeon_cp_init_ring_buffer(drm_device_t * dev, +static void radeon_cp_init_ring_buffer(struct drm_device * dev, drm_radeon_private_t * dev_priv) { u32 ring_start, cur_read_ptr; @@ -1174,7 +1174,7 @@ static void radeon_cp_init_ring_buffer(drm_device_t * dev, } else #endif { - drm_sg_mem_t *entry = dev->sg; + struct drm_sg_mem *entry = dev->sg; unsigned long tmp_ofs, page_ofs; tmp_ofs = dev_priv->ring_rptr->offset - @@ -1390,7 +1390,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) } } -static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init) +static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) { drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1750,7 +1750,7 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init) return 0; } -static int radeon_do_cleanup_cp(drm_device_t * dev) +static int radeon_do_cleanup_cp(struct drm_device * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); @@ -1806,7 +1806,7 @@ static int radeon_do_cleanup_cp(drm_device_t * dev) * * Charl P. Botha */ -static int radeon_do_resume_cp(drm_device_t * dev) +static int radeon_do_resume_cp(struct drm_device * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1933,7 +1933,7 @@ int radeon_cp_stop(DRM_IOCTL_ARGS) return 0; } -void radeon_do_release(drm_device_t * dev) +void radeon_do_release(struct drm_device * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; int i, ret; @@ -2066,9 +2066,9 @@ int radeon_fullscreen(DRM_IOCTL_ARGS) * they can't get the lock. */ -drm_buf_t *radeon_freelist_get(drm_device_t * dev) +drm_buf_t *radeon_freelist_get(struct drm_device * dev) { - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_buf_priv_t *buf_priv; drm_buf_t *buf; @@ -2106,9 +2106,9 @@ drm_buf_t *radeon_freelist_get(drm_device_t * dev) } #if 0 -drm_buf_t *radeon_freelist_get(drm_device_t * dev) +drm_buf_t *radeon_freelist_get(struct drm_device * dev) { - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_buf_priv_t *buf_priv; drm_buf_t *buf; @@ -2140,9 +2140,9 @@ drm_buf_t *radeon_freelist_get(drm_device_t * dev) } #endif -void radeon_freelist_reset(drm_device_t * dev) +void radeon_freelist_reset(struct drm_device * dev) { - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; drm_radeon_private_t *dev_priv = dev->dev_private; int i; @@ -2190,7 +2190,7 @@ int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) return DRM_ERR(EBUSY); } -static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev, +static int radeon_cp_get_buffers(DRMFILE filp, struct drm_device * dev, struct drm_dma * d) { int i; @@ -2218,7 +2218,7 @@ static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev, int radeon_cp_buffers(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; int ret = 0; struct drm_dma __user *argp = (void __user *)data; struct drm_dma d; diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 03d2e7f2..dfa811c2 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -295,7 +295,7 @@ typedef struct drm_radeon_private { unsigned long pcigart_offset; unsigned int pcigart_offset_set; - drm_ati_pcigart_info gart_info; + struct ati_pcigart_info gart_info; u32 scratch_ages[5]; @@ -316,7 +316,7 @@ typedef struct drm_radeon_kcmd_buffer { } drm_radeon_kcmd_buffer_t; extern int radeon_no_wb; -extern drm_ioctl_desc_t radeon_ioctls[]; +extern struct drm_ioctl_desc radeon_ioctls[]; extern int radeon_max_ioctl; /* Check whether the given hardware address is inside the framebuffer or the @@ -345,8 +345,8 @@ extern int radeon_engine_reset(DRM_IOCTL_ARGS); extern int radeon_fullscreen(DRM_IOCTL_ARGS); extern int radeon_cp_buffers(DRM_IOCTL_ARGS); -extern void radeon_freelist_reset(drm_device_t * dev); -extern drm_buf_t *radeon_freelist_get(drm_device_t * dev); +extern void radeon_freelist_reset(struct drm_device * dev); +extern drm_buf_t *radeon_freelist_get(struct drm_device * dev); extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); @@ -362,33 +362,33 @@ extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap); extern int radeon_irq_emit(DRM_IOCTL_ARGS); extern int radeon_irq_wait(DRM_IOCTL_ARGS); -extern void radeon_do_release(drm_device_t * dev); -extern int radeon_driver_vblank_wait(drm_device_t * dev, +extern void radeon_do_release(struct drm_device * dev); +extern int radeon_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence); -extern int radeon_driver_vblank_wait2(drm_device_t * dev, +extern int radeon_driver_vblank_wait2(struct drm_device * dev, unsigned int *sequence); extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); -extern void radeon_driver_irq_preinstall(drm_device_t * dev); -extern void radeon_driver_irq_postinstall(drm_device_t * dev); -extern void radeon_driver_irq_uninstall(drm_device_t * dev); -extern int radeon_vblank_crtc_get(drm_device_t *dev); -extern int radeon_vblank_crtc_set(drm_device_t *dev, int64_t value); +extern void radeon_driver_irq_preinstall(struct drm_device * dev); +extern void radeon_driver_irq_postinstall(struct drm_device * dev); +extern void radeon_driver_irq_uninstall(struct drm_device * dev); +extern int radeon_vblank_crtc_get(struct drm_device *dev); +extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); extern int radeon_driver_unload(struct drm_device *dev); extern int radeon_driver_firstopen(struct drm_device *dev); -extern void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp); -extern void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp); -extern void radeon_driver_lastclose(drm_device_t * dev); -extern int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv); +extern void radeon_driver_preclose(struct drm_device * dev, DRMFILE filp); +extern void radeon_driver_postclose(struct drm_device * dev, struct drm_file * filp); +extern void radeon_driver_lastclose(struct drm_device * dev); +extern int radeon_driver_open(struct drm_device * dev, struct drm_file * filp_priv); extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); /* r300_cmdbuf.c */ extern void r300_init_reg_flags(void); -extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp, - drm_file_t* filp_priv, +extern int r300_do_cp_cmdbuf(struct drm_device *dev, DRMFILE filp, + struct drm_file* filp_priv, drm_radeon_kcmd_buffer_t* cmdbuf); /* Flags for stats.boxes diff --git a/shared-core/radeon_irq.c b/shared-core/radeon_irq.c index a4be86e3..ad8a0ac7 100644 --- a/shared-core/radeon_irq.c +++ b/shared-core/radeon_irq.c @@ -64,7 +64,7 @@ static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS) { - drm_device_t *dev = (drm_device_t *) arg; + struct drm_device *dev = (struct drm_device *) arg; drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; u32 stat; @@ -109,7 +109,7 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS) return IRQ_HANDLED; } -static int radeon_emit_irq(drm_device_t * dev) +static int radeon_emit_irq(struct drm_device * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; unsigned int ret; @@ -127,7 +127,7 @@ static int radeon_emit_irq(drm_device_t * dev) return ret; } -static int radeon_wait_irq(drm_device_t * dev, int swi_nr) +static int radeon_wait_irq(struct drm_device * dev, int swi_nr) { drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; @@ -144,7 +144,7 @@ static int radeon_wait_irq(drm_device_t * dev, int swi_nr) return ret; } -int radeon_driver_vblank_do_wait(drm_device_t * dev, unsigned int *sequence, +int radeon_driver_vblank_do_wait(struct drm_device * dev, unsigned int *sequence, int crtc) { drm_radeon_private_t *dev_priv = @@ -184,12 +184,12 @@ int radeon_driver_vblank_do_wait(drm_device_t * dev, unsigned int *sequence, return ret; } -int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) +int radeon_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence) { return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC1); } -int radeon_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence) +int radeon_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence) { return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC2); } @@ -242,7 +242,7 @@ int radeon_irq_wait(DRM_IOCTL_ARGS) return radeon_wait_irq(dev, irqwait.irq_seq); } -static void radeon_enable_interrupt(drm_device_t *dev) +static void radeon_enable_interrupt(struct drm_device *dev) { drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; @@ -259,7 +259,7 @@ static void radeon_enable_interrupt(drm_device_t *dev) /* drm_dma.h hooks */ -void radeon_driver_irq_preinstall(drm_device_t * dev) +void radeon_driver_irq_preinstall(struct drm_device * dev) { drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; @@ -273,7 +273,7 @@ void radeon_driver_irq_preinstall(drm_device_t * dev) RADEON_CRTC2_VBLANK_STAT)); } -void radeon_driver_irq_postinstall(drm_device_t * dev) +void radeon_driver_irq_postinstall(struct drm_device * dev) { drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; @@ -284,7 +284,7 @@ void radeon_driver_irq_postinstall(drm_device_t * dev) radeon_enable_interrupt(dev); } -void radeon_driver_irq_uninstall(drm_device_t * dev) +void radeon_driver_irq_uninstall(struct drm_device * dev) { drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; @@ -298,7 +298,7 @@ void radeon_driver_irq_uninstall(drm_device_t * dev) } -int radeon_vblank_crtc_get(drm_device_t *dev) +int radeon_vblank_crtc_get(struct drm_device *dev) { drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; u32 flag; @@ -315,7 +315,7 @@ int radeon_vblank_crtc_get(drm_device_t *dev) return value; } -int radeon_vblank_crtc_set(drm_device_t *dev, int64_t value) +int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value) { drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) { diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c index 882cd323..13b09d44 100644 --- a/shared-core/radeon_state.c +++ b/shared-core/radeon_state.c @@ -39,7 +39,7 @@ static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t * dev_priv, - drm_file_t * filp_priv, + struct drm_file * filp_priv, u32 * offset) { u64 off = *offset; @@ -90,7 +90,7 @@ static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t * static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * dev_priv, - drm_file_t * filp_priv, + struct drm_file * filp_priv, int id, u32 *data) { switch (id) { @@ -264,7 +264,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * dev_priv, - drm_file_t *filp_priv, + struct drm_file *filp_priv, drm_radeon_kcmd_buffer_t * cmdbuf, unsigned int *cmdsz) @@ -439,7 +439,7 @@ static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv, /* Emit 1.1 state */ static int radeon_emit_state(drm_radeon_private_t * dev_priv, - drm_file_t * filp_priv, + struct drm_file * filp_priv, drm_radeon_context_regs_t * ctx, drm_radeon_texture_regs_t * tex, unsigned int dirty) @@ -608,7 +608,7 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv, /* Emit 1.2 state */ static int radeon_emit_state2(drm_radeon_private_t * dev_priv, - drm_file_t * filp_priv, + struct drm_file * filp_priv, drm_radeon_state_t * state) { RING_LOCALS; @@ -844,7 +844,7 @@ static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv) * CP command dispatch functions */ -static void radeon_cp_dispatch_clear(drm_device_t * dev, +static void radeon_cp_dispatch_clear(struct drm_device * dev, drm_radeon_clear_t * clear, drm_radeon_clear_rect_t * depth_boxes) { @@ -1335,7 +1335,7 @@ static void radeon_cp_dispatch_clear(drm_device_t * dev, ADVANCE_RING(); } -static void radeon_cp_dispatch_swap(drm_device_t * dev) +static void radeon_cp_dispatch_swap(struct drm_device * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -1412,7 +1412,7 @@ static void radeon_cp_dispatch_swap(drm_device_t * dev) ADVANCE_RING(); } -static void radeon_cp_dispatch_flip(drm_device_t * dev) +static void radeon_cp_dispatch_flip(struct drm_device * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; struct drm_sarea *sarea = (struct drm_sarea *) dev_priv->sarea->handle; @@ -1491,8 +1491,8 @@ typedef struct { unsigned int vc_format; } drm_radeon_tcl_prim_t; -static void radeon_cp_dispatch_vertex(drm_device_t * dev, - drm_buf_t * buf, +static void radeon_cp_dispatch_vertex(struct drm_device * dev, + struct drm_buf * buf, drm_radeon_tcl_prim_t * prim) { drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1537,7 +1537,7 @@ static void radeon_cp_dispatch_vertex(drm_device_t * dev, } while (i < nbox); } -static void radeon_cp_discard_buffer(drm_device_t * dev, drm_buf_t * buf) +static void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_buf_priv_t *buf_priv = buf->dev_private; @@ -1554,8 +1554,8 @@ static void radeon_cp_discard_buffer(drm_device_t * dev, drm_buf_t * buf) buf->used = 0; } -static void radeon_cp_dispatch_indirect(drm_device_t * dev, - drm_buf_t * buf, int start, int end) +static void radeon_cp_dispatch_indirect(struct drm_device * dev, + struct drm_buf * buf, int start, int end) { drm_radeon_private_t *dev_priv = dev->dev_private; RING_LOCALS; @@ -1588,8 +1588,8 @@ static void radeon_cp_dispatch_indirect(drm_device_t * dev, } } -static void radeon_cp_dispatch_indices(drm_device_t * dev, - drm_buf_t * elt_buf, +static void radeon_cp_dispatch_indices(struct drm_device * dev, + struct drm_buf * elt_buf, drm_radeon_tcl_prim_t * prim) { drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1647,13 +1647,13 @@ static void radeon_cp_dispatch_indices(drm_device_t * dev, #define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE static int radeon_cp_dispatch_texture(DRMFILE filp, - drm_device_t * dev, + struct drm_device * dev, drm_radeon_texture_t * tex, drm_radeon_tex_image_t * image) { drm_radeon_private_t *dev_priv = dev->dev_private; - drm_file_t *filp_priv; - drm_buf_t *buf; + struct drm_file *filp_priv; + struct drm_buf *buf; u32 format; u32 *buffer; const u8 __user *data; @@ -1881,7 +1881,7 @@ static int radeon_cp_dispatch_texture(DRMFILE filp, return 0; } -static void radeon_cp_dispatch_stipple(drm_device_t * dev, u32 * stipple) +static void radeon_cp_dispatch_stipple(struct drm_device * dev, u32 * stipple) { drm_radeon_private_t *dev_priv = dev->dev_private; int i; @@ -2144,7 +2144,7 @@ static int radeon_cp_clear(DRM_IOCTL_ARGS) /* Not sure why this isn't set all the time: */ -static int radeon_do_init_pageflip(drm_device_t * dev) +static int radeon_do_init_pageflip(struct drm_device * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; RING_LOCALS; @@ -2216,10 +2216,10 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_file_t *filp_priv; + struct drm_file *filp_priv; drm_radeon_sarea_t *sarea_priv; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; + struct drm_device_dma *dma = dev->dma; + struct drm_buf *buf; drm_radeon_vertex_t vertex; drm_radeon_tcl_prim_t prim; @@ -2306,10 +2306,10 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_file_t *filp_priv; + struct drm_file *filp_priv; drm_radeon_sarea_t *sarea_priv; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; + struct drm_device_dma *dma = dev->dma; + struct drm_buf *buf; drm_radeon_indices_t elts; drm_radeon_tcl_prim_t prim; int count; @@ -2461,8 +2461,8 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; + struct drm_device_dma *dma = dev->dma; + struct drm_buf *buf; drm_radeon_indirect_t indirect; RING_LOCALS; @@ -2535,10 +2535,10 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_file_t *filp_priv; + struct drm_file *filp_priv; drm_radeon_sarea_t *sarea_priv; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; + struct drm_device_dma *dma = dev->dma; + struct drm_buf *buf; drm_radeon_vertex2_t vertex; int i; unsigned char laststate; @@ -2638,7 +2638,7 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) } static int radeon_emit_packets(drm_radeon_private_t * dev_priv, - drm_file_t * filp_priv, + struct drm_file * filp_priv, drm_radeon_cmd_header_t header, drm_radeon_kcmd_buffer_t *cmdbuf) { @@ -2763,8 +2763,8 @@ static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv, return 0; } -static int radeon_emit_packet3(drm_device_t * dev, - drm_file_t * filp_priv, +static int radeon_emit_packet3(struct drm_device * dev, + struct drm_file * filp_priv, drm_radeon_kcmd_buffer_t *cmdbuf) { drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2789,8 +2789,8 @@ static int radeon_emit_packet3(drm_device_t * dev, return 0; } -static int radeon_emit_packet3_cliprect(drm_device_t *dev, - drm_file_t *filp_priv, +static int radeon_emit_packet3_cliprect(struct drm_device *dev, + struct drm_file *filp_priv, drm_radeon_kcmd_buffer_t *cmdbuf, int orig_nbox) { @@ -2851,7 +2851,7 @@ static int radeon_emit_packet3_cliprect(drm_device_t *dev, return 0; } -static int radeon_emit_wait(drm_device_t * dev, int flags) +static int radeon_emit_wait(struct drm_device * dev, int flags) { drm_radeon_private_t *dev_priv = dev->dev_private; RING_LOCALS; @@ -2884,9 +2884,9 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_file_t *filp_priv; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf = NULL; + struct drm_file *filp_priv; + struct drm_device_dma *dma = dev->dma; + struct drm_buf *buf = NULL; int idx; drm_radeon_kcmd_buffer_t cmdbuf; drm_radeon_cmd_header_t header; @@ -3151,7 +3151,7 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_file_t *filp_priv; + struct drm_file *filp_priv; drm_radeon_setparam_t sp; struct drm_radeon_driver_file_fields *radeon_priv; @@ -3213,7 +3213,7 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS) * * DRM infrastructure takes care of reclaiming dma buffers. */ -void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp) +void radeon_driver_preclose(struct drm_device * dev, DRMFILE filp) { if (dev->dev_private) { drm_radeon_private_t *dev_priv = dev->dev_private; @@ -3224,7 +3224,7 @@ void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp) } } -void radeon_driver_lastclose(drm_device_t * dev) +void radeon_driver_lastclose(struct drm_device * dev) { if (dev->dev_private) { drm_radeon_private_t *dev_priv = dev->dev_private; @@ -3237,7 +3237,7 @@ void radeon_driver_lastclose(drm_device_t * dev) radeon_do_release(dev); } -int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv) +int radeon_driver_open(struct drm_device * dev, struct drm_file * filp_priv) { drm_radeon_private_t *dev_priv = dev->dev_private; struct drm_radeon_driver_file_fields *radeon_priv; @@ -3259,7 +3259,7 @@ int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv) return 0; } -void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp_priv) +void radeon_driver_postclose(struct drm_device * dev, struct drm_file * filp_priv) { struct drm_radeon_driver_file_fields *radeon_priv = filp_priv->driver_priv; @@ -3267,7 +3267,7 @@ void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp_priv) drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); } -drm_ioctl_desc_t radeon_ioctls[] = { +struct drm_ioctl_desc radeon_ioctls[] = { [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = {radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = {radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = {radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, diff --git a/shared-core/savage_bci.c b/shared-core/savage_bci.c index 7492a38c..5a41b238 100644 --- a/shared-core/savage_bci.c +++ b/shared-core/savage_bci.c @@ -32,7 +32,7 @@ #define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */ #define SAVAGE_FREELIST_DEBUG 0 -static int savage_do_cleanup_bci(drm_device_t *dev); +static int savage_do_cleanup_bci(struct drm_device *dev); static int savage_bci_wait_fifo_shadow(drm_savage_private_t *dev_priv, unsigned int n) @@ -203,10 +203,10 @@ uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, /* * Freelist management */ -static int savage_freelist_init(drm_device_t *dev) +static int savage_freelist_init(struct drm_device *dev) { drm_savage_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; drm_buf_t *buf; drm_savage_buf_priv_t *entry; int i; @@ -236,7 +236,7 @@ static int savage_freelist_init(drm_device_t *dev) return 0; } -static drm_buf_t *savage_freelist_get(drm_device_t *dev) +static drm_buf_t *savage_freelist_get(struct drm_device *dev) { drm_savage_private_t *dev_priv = dev->dev_private; drm_savage_buf_priv_t *tail = dev_priv->tail.prev; @@ -269,7 +269,7 @@ static drm_buf_t *savage_freelist_get(drm_device_t *dev) return NULL; } -void savage_freelist_put(drm_device_t *dev, drm_buf_t *buf) +void savage_freelist_put(struct drm_device *dev, drm_buf_t *buf) { drm_savage_private_t *dev_priv = dev->dev_private; drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next; @@ -535,7 +535,7 @@ static void savage_fake_dma_flush(drm_savage_private_t *dev_priv) dev_priv->first_dma_page = dev_priv->current_dma_page = 0; } -int savage_driver_load(drm_device_t *dev, unsigned long chipset) +int savage_driver_load(struct drm_device *dev, unsigned long chipset) { drm_savage_private_t *dev_priv; @@ -557,7 +557,7 @@ int savage_driver_load(drm_device_t *dev, unsigned long chipset) * in drm_addmap. Therefore we add them manually before the maps are * initialized, and tear them down on last close. */ -int savage_driver_firstopen(drm_device_t *dev) +int savage_driver_firstopen(struct drm_device *dev) { drm_savage_private_t *dev_priv = dev->dev_private; unsigned long mmio_base, fb_base, fb_size, aperture_base; @@ -654,7 +654,7 @@ int savage_driver_firstopen(drm_device_t *dev) /* * Delete MTRRs and free device-private data. */ -void savage_driver_lastclose(drm_device_t *dev) +void savage_driver_lastclose(struct drm_device *dev) { drm_savage_private_t *dev_priv = dev->dev_private; int i; @@ -666,7 +666,7 @@ void savage_driver_lastclose(drm_device_t *dev) dev_priv->mtrr[i].size, DRM_MTRR_WC); } -int savage_driver_unload(drm_device_t *dev) +int savage_driver_unload(struct drm_device *dev) { drm_savage_private_t *dev_priv = dev->dev_private; @@ -675,7 +675,7 @@ int savage_driver_unload(drm_device_t *dev) return 0; } -static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init) +static int savage_do_init_bci(struct drm_device *dev, drm_savage_init_t *init) { drm_savage_private_t *dev_priv = dev->dev_private; @@ -897,7 +897,7 @@ static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init) return 0; } -static int savage_do_cleanup_bci(drm_device_t *dev) +static int savage_do_cleanup_bci(struct drm_device *dev) { drm_savage_private_t *dev_priv = dev->dev_private; @@ -1006,7 +1006,7 @@ static int savage_bci_event_wait(DRM_IOCTL_ARGS) * DMA buffer management */ -static int savage_bci_get_buffers(DRMFILE filp, drm_device_t *dev, struct drm_dma *d) +static int savage_bci_get_buffers(DRMFILE filp, struct drm_device *dev, struct drm_dma *d) { drm_buf_t *buf; int i; @@ -1033,7 +1033,7 @@ static int savage_bci_get_buffers(DRMFILE filp, drm_device_t *dev, struct drm_dm int savage_bci_buffers(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; struct drm_dma d; int ret = 0; @@ -1068,9 +1068,9 @@ int savage_bci_buffers(DRM_IOCTL_ARGS) return ret; } -void savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp) +void savage_reclaim_buffers(struct drm_device *dev, DRMFILE filp) { - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; drm_savage_private_t *dev_priv = dev->dev_private; int i; @@ -1100,7 +1100,7 @@ void savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp) drm_core_reclaim_buffers(dev, filp); } -drm_ioctl_desc_t savage_ioctls[] = { +struct drm_ioctl_desc savage_ioctls[] = { [DRM_IOCTL_NR(DRM_SAVAGE_BCI_INIT)] = {savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, [DRM_IOCTL_NR(DRM_SAVAGE_BCI_CMDBUF)] = {savage_bci_cmdbuf, DRM_AUTH}, [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_EMIT)] = {savage_bci_event_emit, DRM_AUTH}, diff --git a/shared-core/savage_drv.h b/shared-core/savage_drv.h index 8d04d43b..39c2c751 100644 --- a/shared-core/savage_drv.h +++ b/shared-core/savage_drv.h @@ -104,7 +104,7 @@ enum savage_family { S3_LAST }; -extern drm_ioctl_desc_t savage_ioctls[]; +extern struct drm_ioctl_desc savage_ioctls[]; extern int savage_max_ioctl; #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) @@ -203,16 +203,16 @@ extern int savage_bci_buffers(DRM_IOCTL_ARGS); /* BCI functions */ extern uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, unsigned int flags); -extern void savage_freelist_put(drm_device_t *dev, drm_buf_t *buf); +extern void savage_freelist_put(struct drm_device *dev, drm_buf_t *buf); extern void savage_dma_reset(drm_savage_private_t *dev_priv); extern void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page); extern uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, unsigned int n); -extern int savage_driver_load(drm_device_t *dev, unsigned long chipset); -extern int savage_driver_firstopen(drm_device_t *dev); -extern void savage_driver_lastclose(drm_device_t *dev); -extern int savage_driver_unload(drm_device_t *dev); -extern void savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp); +extern int savage_driver_load(struct drm_device *dev, unsigned long chipset); +extern int savage_driver_firstopen(struct drm_device *dev); +extern void savage_driver_lastclose(struct drm_device *dev); +extern int savage_driver_unload(struct drm_device *dev); +extern void savage_reclaim_buffers(struct drm_device *dev, DRMFILE filp); /* state functions */ extern void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv, diff --git a/shared-core/savage_state.c b/shared-core/savage_state.c index 54b9169b..93d2081b 100644 --- a/shared-core/savage_state.c +++ b/shared-core/savage_state.c @@ -956,7 +956,7 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_savage_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; + struct drm_device_dma *dma = dev->dma; drm_buf_t *dmabuf; drm_savage_cmdbuf_t cmdbuf; drm_savage_cmd_header_t *kcmd_addr = NULL; diff --git a/shared-core/sis_drv.h b/shared-core/sis_drv.h index ec572ad4..c174e294 100644 --- a/shared-core/sis_drv.h +++ b/shared-core/sis_drv.h @@ -66,9 +66,9 @@ typedef struct drm_sis_private { unsigned long agp_offset; } drm_sis_private_t; -extern int sis_idle(drm_device_t *dev); -extern void sis_reclaim_buffers_locked(drm_device_t *dev, struct file *filp); -extern void sis_lastclose(drm_device_t *dev); +extern int sis_idle(struct drm_device *dev); +extern void sis_reclaim_buffers_locked(struct drm_device *dev, struct file *filp); +extern void sis_lastclose(struct drm_device *dev); #else #include "sis_ds.h" @@ -78,14 +78,14 @@ typedef struct drm_sis_private { memHeap_t *FBHeap; } drm_sis_private_t; -extern int sis_init_context(drm_device_t * dev, int context); -extern int sis_final_context(drm_device_t * dev, int context); +extern int sis_init_context(struct drm_device * dev, int context); +extern int sis_final_context(struct drm_device * dev, int context); #endif -extern drm_ioctl_desc_t sis_ioctls[]; +extern struct drm_ioctl_desc sis_ioctls[]; extern int sis_max_ioctl; #endif diff --git a/shared-core/via_dma.c b/shared-core/via_dma.c index 333c4bcf..48f46938 100644 --- a/shared-core/via_dma.c +++ b/shared-core/via_dma.c @@ -139,7 +139,7 @@ static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv, return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); } -int via_dma_cleanup(drm_device_t * dev) +int via_dma_cleanup(struct drm_device * dev) { if (dev->dev_private) { drm_via_private_t *dev_priv = @@ -157,7 +157,7 @@ int via_dma_cleanup(drm_device_t * dev) return 0; } -static int via_initialize(drm_device_t * dev, +static int via_initialize(struct drm_device * dev, drm_via_private_t * dev_priv, drm_via_dma_init_t * init) { @@ -252,7 +252,7 @@ static int via_dma_init(DRM_IOCTL_ARGS) -static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd) +static int via_dispatch_cmdbuffer(struct drm_device * dev, drm_via_cmdbuffer_t * cmd) { drm_via_private_t *dev_priv; uint32_t *vb; @@ -306,7 +306,7 @@ static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd) return 0; } -int via_driver_dma_quiescent(drm_device_t * dev) +int via_driver_dma_quiescent(struct drm_device * dev) { drm_via_private_t *dev_priv = dev->dev_private; @@ -346,7 +346,7 @@ static int via_cmdbuffer(DRM_IOCTL_ARGS) return 0; } -static int via_dispatch_pci_cmdbuffer(drm_device_t * dev, +static int via_dispatch_pci_cmdbuffer(struct drm_device * dev, drm_via_cmdbuffer_t * cmd) { drm_via_private_t *dev_priv = dev->dev_private; @@ -718,7 +718,7 @@ via_dma_blit( DRM_IOCTL_ARGS ) { } #endif -drm_ioctl_desc_t via_ioctls[] = { +struct drm_ioctl_desc via_ioctls[] = { [DRM_IOCTL_NR(DRM_VIA_ALLOCMEM)] = {via_mem_alloc, DRM_AUTH}, [DRM_IOCTL_NR(DRM_VIA_FREEMEM)] = {via_mem_free, DRM_AUTH}, [DRM_IOCTL_NR(DRM_VIA_AGP_INIT)] = {via_agp_init, DRM_AUTH|DRM_MASTER}, diff --git a/shared-core/via_drv.h b/shared-core/via_drv.h index b6dbf6c1..85ddc53a 100644 --- a/shared-core/via_drv.h +++ b/shared-core/via_drv.h @@ -148,7 +148,7 @@ enum via_family { #define VIA_READ8(reg) DRM_READ8(VIA_BASE, reg) #define VIA_WRITE8(reg,val) DRM_WRITE8(VIA_BASE, reg, val) -extern drm_ioctl_desc_t via_ioctls[]; +extern struct drm_ioctl_desc via_ioctls[]; extern int via_max_ioctl; extern int via_fb_init(DRM_IOCTL_ARGS); @@ -161,41 +161,41 @@ extern int via_wait_irq(DRM_IOCTL_ARGS); extern int via_dma_blit_sync( DRM_IOCTL_ARGS ); extern int via_dma_blit( DRM_IOCTL_ARGS ); -extern int via_driver_load(drm_device_t *dev, unsigned long chipset); -extern int via_driver_unload(drm_device_t *dev); -extern int via_final_context(drm_device_t * dev, int context); +extern int via_driver_load(struct drm_device *dev, unsigned long chipset); +extern int via_driver_unload(struct drm_device *dev); +extern int via_final_context(struct drm_device * dev, int context); -extern int via_do_cleanup_map(drm_device_t * dev); -extern int via_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence); +extern int via_do_cleanup_map(struct drm_device * dev); +extern int via_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence); extern irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS); -extern void via_driver_irq_preinstall(drm_device_t * dev); -extern void via_driver_irq_postinstall(drm_device_t * dev); -extern void via_driver_irq_uninstall(drm_device_t * dev); +extern void via_driver_irq_preinstall(struct drm_device * dev); +extern void via_driver_irq_postinstall(struct drm_device * dev); +extern void via_driver_irq_uninstall(struct drm_device * dev); -extern int via_dma_cleanup(drm_device_t * dev); +extern int via_dma_cleanup(struct drm_device * dev); extern void via_init_command_verifier(void); -extern int via_driver_dma_quiescent(drm_device_t * dev); +extern int via_driver_dma_quiescent(struct drm_device * dev); extern void via_init_futex(drm_via_private_t *dev_priv); extern void via_cleanup_futex(drm_via_private_t *dev_priv); extern void via_release_futex(drm_via_private_t *dev_priv, int context); #ifdef VIA_HAVE_CORE_MM -extern void via_reclaim_buffers_locked(drm_device_t *dev, struct file *filp); -extern void via_lastclose(drm_device_t *dev); +extern void via_reclaim_buffers_locked(struct drm_device *dev, struct file *filp); +extern void via_lastclose(struct drm_device *dev); #else -extern int via_init_context(drm_device_t * dev, int context); +extern int via_init_context(struct drm_device * dev, int context); #endif #ifdef VIA_HAVE_DMABLIT -extern void via_dmablit_handler(drm_device_t *dev, int engine, int from_irq); -extern void via_init_dmablit(drm_device_t *dev); +extern void via_dmablit_handler(struct drm_device *dev, int engine, int from_irq); +extern void via_init_dmablit(struct drm_device *dev); #endif #ifdef VIA_HAVE_FENCE extern void via_fence_timer(unsigned long data); -extern void via_poke_flush(drm_device_t * dev, uint32_t class); -extern int via_fence_emit_sequence(drm_device_t * dev, uint32_t class, +extern void via_poke_flush(struct drm_device * dev, uint32_t class); +extern int via_fence_emit_sequence(struct drm_device * dev, uint32_t class, uint32_t flags, uint32_t * sequence, uint32_t * native_type); @@ -204,10 +204,10 @@ extern int via_fence_has_irq(struct drm_device * dev, uint32_t class, #endif #ifdef VIA_HAVE_BUFFER -extern drm_ttm_backend_t *via_create_ttm_backend_entry(drm_device_t *dev); +extern drm_ttm_backend_t *via_create_ttm_backend_entry(struct drm_device *dev); extern int via_fence_types(drm_buffer_object_t *bo, uint32_t *type); -extern int via_invalidate_caches(drm_device_t *dev, uint64_t buffer_flags); -extern int via_init_mem_type(drm_device_t *dev, uint32_t type, +extern int via_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags); +extern int via_init_mem_type(struct drm_device *dev, uint32_t type, drm_mem_type_manager_t *man); extern uint32_t via_evict_mask(drm_buffer_object_t *bo); extern int via_move(drm_buffer_object_t *bo, int evict, diff --git a/shared-core/via_irq.c b/shared-core/via_irq.c index 2ac86970..040df548 100644 --- a/shared-core/via_irq.c +++ b/shared-core/via_irq.c @@ -99,7 +99,7 @@ static unsigned time_diff(struct timeval *now,struct timeval *then) irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS) { - drm_device_t *dev = (drm_device_t *) arg; + struct drm_device *dev = (struct drm_device *) arg; drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; u32 status; int handled = 0; @@ -171,7 +171,7 @@ static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv) } } -int via_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) +int via_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence) { drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; unsigned int cur_vblank; @@ -199,7 +199,7 @@ int via_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) } static int -via_driver_irq_wait(drm_device_t * dev, unsigned int irq, int force_sequence, +via_driver_irq_wait(struct drm_device * dev, unsigned int irq, int force_sequence, unsigned int *sequence) { drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; @@ -253,7 +253,7 @@ via_driver_irq_wait(drm_device_t * dev, unsigned int irq, int force_sequence, * drm_dma.h hooks */ -void via_driver_irq_preinstall(drm_device_t * dev) +void via_driver_irq_preinstall(struct drm_device * dev) { drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; u32 status; @@ -302,7 +302,7 @@ void via_driver_irq_preinstall(drm_device_t * dev) } } -void via_driver_irq_postinstall(drm_device_t * dev) +void via_driver_irq_postinstall(struct drm_device * dev) { drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; u32 status; @@ -321,7 +321,7 @@ void via_driver_irq_postinstall(drm_device_t * dev) } } -void via_driver_irq_uninstall(drm_device_t * dev) +void via_driver_irq_uninstall(struct drm_device * dev) { drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; u32 status; diff --git a/shared-core/via_map.c b/shared-core/via_map.c index 037a1c2c..2381eaa9 100644 --- a/shared-core/via_map.c +++ b/shared-core/via_map.c @@ -25,7 +25,7 @@ #include "via_drm.h" #include "via_drv.h" -static int via_do_init_map(drm_device_t * dev, drm_via_init_t * init) +static int via_do_init_map(struct drm_device * dev, drm_via_init_t * init) { drm_via_private_t *dev_priv = dev->dev_private; int ret = 0; @@ -83,7 +83,7 @@ static int via_do_init_map(drm_device_t * dev, drm_via_init_t * init) } -int via_do_cleanup_map(drm_device_t * dev) +int via_do_cleanup_map(struct drm_device * dev) { via_dma_cleanup(dev); @@ -111,7 +111,7 @@ int via_map_init(DRM_IOCTL_ARGS) return -EINVAL; } -int via_driver_load(drm_device_t *dev, unsigned long chipset) +int via_driver_load(struct drm_device *dev, unsigned long chipset) { drm_via_private_t *dev_priv; int ret = 0; @@ -133,7 +133,7 @@ int via_driver_load(drm_device_t *dev, unsigned long chipset) return ret; } -int via_driver_unload(drm_device_t *dev) +int via_driver_unload(struct drm_device *dev) { drm_via_private_t *dev_priv = dev->dev_private; diff --git a/shared-core/via_verifier.c b/shared-core/via_verifier.c index 4b844af0..038bea2f 100644 --- a/shared-core/via_verifier.c +++ b/shared-core/via_verifier.c @@ -252,10 +252,10 @@ eat_words(const uint32_t ** buf, const uint32_t * buf_end, unsigned num_words) static __inline__ drm_local_map_t *via_drm_lookup_agp_map(drm_via_state_t * seq, unsigned long offset, unsigned long size, - drm_device_t * dev) + struct drm_device * dev) { #ifdef __linux__ - drm_map_list_t *r_list; + struct drm_map_list *r_list; #endif drm_local_map_t *map = seq->map_cache; @@ -967,7 +967,7 @@ via_parse_vheader6(drm_via_private_t * dev_priv, uint32_t const **buffer, int via_verify_command_stream(const uint32_t * buf, unsigned int size, - drm_device_t * dev, int agp) + struct drm_device * dev, int agp) { drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; @@ -1042,7 +1042,7 @@ via_verify_command_stream(const uint32_t * buf, unsigned int size, } int -via_parse_command_stream(drm_device_t * dev, const uint32_t * buf, +via_parse_command_stream(struct drm_device * dev, const uint32_t * buf, unsigned int size) { diff --git a/shared-core/via_verifier.h b/shared-core/via_verifier.h index 84497c44..dac1db91 100644 --- a/shared-core/via_verifier.h +++ b/shared-core/via_verifier.h @@ -49,7 +49,7 @@ typedef struct { drm_via_sequence_t unfinished; int agp_texture; int multitex; - drm_device_t *dev; + struct drm_device *dev; drm_local_map_t *map_cache; uint32_t vertex_count; int agp; @@ -57,8 +57,8 @@ typedef struct { } drm_via_state_t; extern int via_verify_command_stream(const uint32_t * buf, unsigned int size, - drm_device_t *dev, int agp); -extern int via_parse_command_stream(drm_device_t *dev, const uint32_t * buf, + struct drm_device *dev, int agp); +extern int via_parse_command_stream(struct drm_device *dev, const uint32_t * buf, unsigned int size); #endif -- cgit v1.2.3 From 6dce9e07352e14d2e03d26b8a64a40e111ecab2b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 16 Jul 2007 12:48:44 +1000 Subject: drm: remove hashtab/sman and object typedefs --- shared-core/sis_drv.h | 2 +- shared-core/via_drv.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/sis_drv.h b/shared-core/sis_drv.h index c174e294..57d60133 100644 --- a/shared-core/sis_drv.h +++ b/shared-core/sis_drv.h @@ -58,7 +58,7 @@ enum sis_family { typedef struct drm_sis_private { drm_local_map_t *mmio; unsigned int idle_fault; - drm_sman_t sman; + struct drm_sman sman; unsigned int chipset; int vram_initialized; int agp_initialized; diff --git a/shared-core/via_drv.h b/shared-core/via_drv.h index 85ddc53a..9ffc7a51 100644 --- a/shared-core/via_drv.h +++ b/shared-core/via_drv.h @@ -116,7 +116,7 @@ typedef struct drm_via_private { /* Memory manager stuff */ #ifdef VIA_HAVE_CORE_MM unsigned int idle_fault; - drm_sman_t sman; + struct drm_sman sman; int vram_initialized; int agp_initialized; unsigned long vram_offset; -- cgit v1.2.3 From be85ad0333b0c28129c2e4635f92780816308aa6 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 16 Jul 2007 13:37:02 +1000 Subject: drm: detypedef ttm/bo/fence code --- shared-core/i915_drv.h | 12 ++++++------ shared-core/via_drv.c | 4 ++-- shared-core/via_drv.h | 12 ++++++------ 3 files changed, 14 insertions(+), 14 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 1ed37c63..ee2b474b 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -197,14 +197,14 @@ extern int i915_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t f #ifdef I915_HAVE_BUFFER /* i915_buffer.c */ -extern drm_ttm_backend_t *i915_create_ttm_backend_entry(struct drm_device *dev); -extern int i915_fence_types(drm_buffer_object_t *bo, uint32_t *type); +extern struct drm_ttm_backend *i915_create_ttm_backend_entry(struct drm_device *dev); +extern int i915_fence_types(struct drm_buffer_object *bo, uint32_t *type); extern int i915_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags); extern int i915_init_mem_type(struct drm_device *dev, uint32_t type, - drm_mem_type_manager_t *man); -extern uint32_t i915_evict_mask(drm_buffer_object_t *bo); -extern int i915_move(drm_buffer_object_t *bo, int evict, - int no_wait, drm_bo_mem_reg_t *new_mem); + struct drm_mem_type_manager *man); +extern uint32_t i915_evict_mask(struct drm_buffer_object *bo); +extern int i915_move(struct drm_buffer_object *bo, int evict, + int no_wait, struct drm_bo_mem_reg *new_mem); #endif diff --git a/shared-core/via_drv.c b/shared-core/via_drv.c index 0a478fef..9f099555 100644 --- a/shared-core/via_drv.c +++ b/shared-core/via_drv.c @@ -40,7 +40,7 @@ static struct pci_device_id pciidlist[] = { #ifdef VIA_HAVE_FENCE -static drm_fence_driver_t via_fence_driver = { +static struct drm_fence_driver via_fence_driver = { .num_classes = 1, .wrap_diff = (1 << 30), .flush_diff = (1 << 20), @@ -65,7 +65,7 @@ static uint32_t via_mem_prios[] = {DRM_BO_MEM_PRIV0, DRM_BO_MEM_VRAM, DRM_BO_MEM static uint32_t via_busy_prios[] = {DRM_BO_MEM_TT, DRM_BO_MEM_PRIV0, DRM_BO_MEM_VRAM, DRM_BO_MEM_LOCAL}; -static drm_bo_driver_t via_bo_driver = { +static struct drm_bo_driver via_bo_driver = { .mem_type_prio = via_mem_prios, .mem_busy_prio = via_busy_prios, .num_mem_type_prio = ARRAY_SIZE(via_mem_prios), diff --git a/shared-core/via_drv.h b/shared-core/via_drv.h index 9ffc7a51..05935c81 100644 --- a/shared-core/via_drv.h +++ b/shared-core/via_drv.h @@ -204,14 +204,14 @@ extern int via_fence_has_irq(struct drm_device * dev, uint32_t class, #endif #ifdef VIA_HAVE_BUFFER -extern drm_ttm_backend_t *via_create_ttm_backend_entry(struct drm_device *dev); -extern int via_fence_types(drm_buffer_object_t *bo, uint32_t *type); +extern struct drm_ttm_backend *via_create_ttm_backend_entry(struct drm_device *dev); +extern int via_fence_types(struct drm_buffer_object *bo, uint32_t *type); extern int via_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags); extern int via_init_mem_type(struct drm_device *dev, uint32_t type, - drm_mem_type_manager_t *man); -extern uint32_t via_evict_mask(drm_buffer_object_t *bo); -extern int via_move(drm_buffer_object_t *bo, int evict, - int no_wait, drm_bo_mem_reg_t *new_mem); + struct drm_mem_type_manager *man); +extern uint32_t via_evict_mask(struct drm_buffer_object *bo); +extern int via_move(struct drm_buffer_object *bo, int evict, + int no_wait, struct drm_bo_mem_reg *new_mem); #endif #endif -- cgit v1.2.3 From 24311d5d82b61a4729b15355088dd9c2898d1089 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 16 Jul 2007 13:42:11 +1000 Subject: drm: remove drm_buf_t --- shared-core/mach64_dma.c | 10 +++++----- shared-core/mach64_drv.h | 10 +++++----- shared-core/mach64_state.c | 4 ++-- shared-core/mga_dma.c | 8 ++++---- shared-core/mga_drv.h | 4 ++-- shared-core/mga_state.c | 8 ++++---- shared-core/r128_drv.h | 2 +- shared-core/r300_cmdbuf.c | 4 ++-- shared-core/radeon_cp.c | 12 ++++++------ shared-core/radeon_drv.h | 4 ++-- shared-core/savage_bci.c | 10 +++++----- shared-core/savage_drv.h | 4 ++-- shared-core/savage_state.c | 8 ++++---- 13 files changed, 44 insertions(+), 44 deletions(-) (limited to 'shared-core') diff --git a/shared-core/mach64_dma.c b/shared-core/mach64_dma.c index c787260a..d833475f 100644 --- a/shared-core/mach64_dma.c +++ b/shared-core/mach64_dma.c @@ -418,7 +418,7 @@ void mach64_dump_engine_info(drm_mach64_private_t * dev_priv) * pointed by the ring head. */ static void mach64_dump_buf_info(drm_mach64_private_t * dev_priv, - drm_buf_t * buf) + struct drm_buf * buf) { u32 addr = GETBUFADDR(buf); u32 used = buf->used >> 2; @@ -522,7 +522,7 @@ void mach64_dump_ring_info(drm_mach64_private_t * dev_priv) list_for_each(ptr, &dev_priv->pending) { drm_mach64_freelist_t *entry = list_entry(ptr, drm_mach64_freelist_t, list); - drm_buf_t *buf = entry->buf; + struct drm_buf *buf = entry->buf; u32 buf_addr = GETBUFADDR(buf); @@ -974,7 +974,7 @@ int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t * dev_priv) volatile u32 *ring_read; struct list_head *ptr; drm_mach64_freelist_t *entry; - drm_buf_t *buf = NULL; + struct drm_buf *buf = NULL; u32 *buf_ptr; u32 used, reg, target; int fifo, count, found, ret, no_idle_wait; @@ -1381,7 +1381,7 @@ static int mach64_do_reclaim_completed(drm_mach64_private_t * dev_priv) return 1; } -drm_buf_t *mach64_freelist_get(drm_mach64_private_t * dev_priv) +struct drm_buf *mach64_freelist_get(drm_mach64_private_t * dev_priv) { drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; drm_mach64_freelist_t *entry; @@ -1427,7 +1427,7 @@ drm_buf_t *mach64_freelist_get(drm_mach64_private_t * dev_priv) return entry->buf; } -int mach64_freelist_put(drm_mach64_private_t * dev_priv, drm_buf_t * copy_buf) +int mach64_freelist_put(drm_mach64_private_t * dev_priv, struct drm_buf * copy_buf) { struct list_head *ptr; drm_mach64_freelist_t *entry; diff --git a/shared-core/mach64_drv.h b/shared-core/mach64_drv.h index 31b8247a..a1b36751 100644 --- a/shared-core/mach64_drv.h +++ b/shared-core/mach64_drv.h @@ -55,7 +55,7 @@ typedef struct drm_mach64_freelist { struct list_head list; /* List pointers for free_list, placeholders, or pending list */ - drm_buf_t *buf; /* Pointer to the buffer */ + struct drm_buf *buf; /* Pointer to the buffer */ int discard; /* This flag is set when we're done (re)using a buffer */ u32 ring_ofs; /* dword offset in ring of last descriptor for this buffer */ } drm_mach64_freelist_t; @@ -121,9 +121,9 @@ extern void mach64_driver_lastclose(struct drm_device * dev); extern int mach64_init_freelist(struct drm_device * dev); extern void mach64_destroy_freelist(struct drm_device * dev); -extern drm_buf_t *mach64_freelist_get(drm_mach64_private_t * dev_priv); +extern struct drm_buf *mach64_freelist_get(drm_mach64_private_t * dev_priv); extern int mach64_freelist_put(drm_mach64_private_t * dev_priv, - drm_buf_t * copy_buf); + struct drm_buf * copy_buf); extern int mach64_do_wait_for_fifo(drm_mach64_private_t * dev_priv, int entries); @@ -798,7 +798,7 @@ do { \ #define DMALOCALS \ drm_mach64_freelist_t *_entry = NULL; \ - drm_buf_t *_buf = NULL; \ + struct drm_buf *_buf = NULL; \ u32 *_buf_wptr; int _outcount #define GETBUFPTR( __buf ) \ @@ -813,7 +813,7 @@ do { \ static __inline__ int mach64_find_pending_buf_entry(drm_mach64_private_t * dev_priv, drm_mach64_freelist_t ** - entry, drm_buf_t * buf) + entry, struct drm_buf * buf) { struct list_head *ptr; #if MACH64_EXTRA_CHECKING diff --git a/shared-core/mach64_state.c b/shared-core/mach64_state.c index 4e8291af..95ad1ec3 100644 --- a/shared-core/mach64_state.c +++ b/shared-core/mach64_state.c @@ -550,7 +550,7 @@ static int mach64_dma_dispatch_vertex(DRMFILE filp, struct drm_device * dev, { drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_buf_t *copy_buf; + struct drm_buf *copy_buf; void *buf = vertex->buf; unsigned long used = vertex->used; int ret = 0; @@ -646,7 +646,7 @@ static int mach64_dma_dispatch_blit(DRMFILE filp, struct drm_device * dev, drm_mach64_private_t *dev_priv = dev->dev_private; int dword_shift, dwords; unsigned long used; - drm_buf_t *copy_buf; + struct drm_buf *copy_buf; int verify_ret = 0; DMALOCALS; diff --git a/shared-core/mga_dma.c b/shared-core/mga_dma.c index 0a3c2729..9bed3b34 100644 --- a/shared-core/mga_dma.c +++ b/shared-core/mga_dma.c @@ -314,7 +314,7 @@ static void mga_freelist_cleanup(struct drm_device * dev) static void mga_freelist_reset(struct drm_device * dev) { drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; + struct drm_buf *buf; drm_mga_buf_priv_t *buf_priv; int i; @@ -326,7 +326,7 @@ static void mga_freelist_reset(struct drm_device * dev) } #endif -static drm_buf_t *mga_freelist_get(struct drm_device * dev) +static struct drm_buf *mga_freelist_get(struct drm_device * dev) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_freelist_t *next; @@ -359,7 +359,7 @@ static drm_buf_t *mga_freelist_get(struct drm_device * dev) return NULL; } -int mga_freelist_put(struct drm_device * dev, drm_buf_t * buf) +int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; @@ -1091,7 +1091,7 @@ int mga_dma_reset(DRM_IOCTL_ARGS) static int mga_dma_get_buffers(DRMFILE filp, struct drm_device * dev, struct drm_dma * d) { - drm_buf_t *buf; + struct drm_buf *buf; int i; for (i = d->granted_count; i < d->request_count; i++) { diff --git a/shared-core/mga_drv.h b/shared-core/mga_drv.h index e1fdf403..10096a95 100644 --- a/shared-core/mga_drv.h +++ b/shared-core/mga_drv.h @@ -65,7 +65,7 @@ typedef struct drm_mga_freelist { struct drm_mga_freelist *next; struct drm_mga_freelist *prev; drm_mga_age_t age; - drm_buf_t *buf; + struct drm_buf *buf; } drm_mga_freelist_t; typedef struct { @@ -168,7 +168,7 @@ extern void mga_do_dma_flush(drm_mga_private_t * dev_priv); extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv); extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv); -extern int mga_freelist_put(struct drm_device * dev, drm_buf_t * buf); +extern int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf); /* mga_warp.c */ extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv); diff --git a/shared-core/mga_state.c b/shared-core/mga_state.c index 72db0ced..6d93c9e4 100644 --- a/shared-core/mga_state.c +++ b/shared-core/mga_state.c @@ -651,7 +651,7 @@ static void mga_dma_dispatch_swap(struct drm_device * dev) DRM_DEBUG("%s... done.\n", __FUNCTION__); } -static void mga_dma_dispatch_vertex(struct drm_device * dev, drm_buf_t * buf) +static void mga_dma_dispatch_vertex(struct drm_device * dev, struct drm_buf * buf) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; @@ -698,7 +698,7 @@ static void mga_dma_dispatch_vertex(struct drm_device * dev, drm_buf_t * buf) FLUSH_DMA(); } -static void mga_dma_dispatch_indices(struct drm_device * dev, drm_buf_t * buf, +static void mga_dma_dispatch_indices(struct drm_device * dev, struct drm_buf * buf, unsigned int start, unsigned int end) { drm_mga_private_t *dev_priv = dev->dev_private; @@ -747,7 +747,7 @@ static void mga_dma_dispatch_indices(struct drm_device * dev, drm_buf_t * buf, /* This copies a 64 byte aligned agp region to the frambuffer with a * standard blit, the ioctl needs to do checking. */ -static void mga_dma_dispatch_iload(struct drm_device * dev, drm_buf_t * buf, +static void mga_dma_dispatch_iload(struct drm_device * dev, struct drm_buf * buf, unsigned int dstorg, unsigned int length) { drm_mga_private_t *dev_priv = dev->dev_private; @@ -998,7 +998,7 @@ static int mga_dma_iload(DRM_IOCTL_ARGS) DRM_DEVICE; struct drm_device_dma *dma = dev->dma; drm_mga_private_t *dev_priv = dev->dev_private; - drm_buf_t *buf; + struct drm_buf *buf; drm_mga_buf_priv_t *buf_priv; drm_mga_iload_t iload; DRM_DEBUG("\n"); diff --git a/shared-core/r128_drv.h b/shared-core/r128_drv.h index 0791713a..c9abd67b 100644 --- a/shared-core/r128_drv.h +++ b/shared-core/r128_drv.h @@ -57,7 +57,7 @@ typedef struct drm_r128_freelist { unsigned int age; - drm_buf_t *buf; + struct drm_buf *buf; struct drm_r128_freelist *next; struct drm_r128_freelist *prev; } drm_r128_freelist_t; diff --git a/shared-core/r300_cmdbuf.c b/shared-core/r300_cmdbuf.c index 08015ecf..9cf352ae 100644 --- a/shared-core/r300_cmdbuf.c +++ b/shared-core/r300_cmdbuf.c @@ -706,7 +706,7 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv) * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must * be careful about how this function is called. */ -static void r300_discard_buffer(struct drm_device * dev, drm_buf_t * buf) +static void r300_discard_buffer(struct drm_device * dev, struct drm_buf * buf) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_buf_priv_t *buf_priv = buf->dev_private; @@ -785,7 +785,7 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, { drm_radeon_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; - drm_buf_t *buf = NULL; + struct drm_buf *buf = NULL; int emit_dispatch_age = 0; int ret = 0; diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index cef47ca0..40a20e6c 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -2066,12 +2066,12 @@ int radeon_fullscreen(DRM_IOCTL_ARGS) * they can't get the lock. */ -drm_buf_t *radeon_freelist_get(struct drm_device * dev) +struct drm_buf *radeon_freelist_get(struct drm_device * dev) { struct drm_device_dma *dma = dev->dma; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_buf_priv_t *buf_priv; - drm_buf_t *buf; + struct drm_buf *buf; int i, t; int start; @@ -2106,12 +2106,12 @@ drm_buf_t *radeon_freelist_get(struct drm_device * dev) } #if 0 -drm_buf_t *radeon_freelist_get(struct drm_device * dev) +struct drm_buf *radeon_freelist_get(struct drm_device * dev) { struct drm_device_dma *dma = dev->dma; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_buf_priv_t *buf_priv; - drm_buf_t *buf; + struct drm_buf *buf; int i, t; int start; u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); @@ -2148,7 +2148,7 @@ void radeon_freelist_reset(struct drm_device * dev) dev_priv->last_buf = 0; for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[i]; + struct drm_buf *buf = dma->buflist[i]; drm_radeon_buf_priv_t *buf_priv = buf->dev_private; buf_priv->age = 0; } @@ -2194,7 +2194,7 @@ static int radeon_cp_get_buffers(DRMFILE filp, struct drm_device * dev, struct drm_dma * d) { int i; - drm_buf_t *buf; + struct drm_buf *buf; for (i = d->granted_count; i < d->request_count; i++) { buf = radeon_freelist_get(dev); diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index dfa811c2..2dca1e70 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -156,7 +156,7 @@ enum radeon_chip_flags { typedef struct drm_radeon_freelist { unsigned int age; - drm_buf_t *buf; + struct drm_buf *buf; struct drm_radeon_freelist *next; struct drm_radeon_freelist *prev; } drm_radeon_freelist_t; @@ -346,7 +346,7 @@ extern int radeon_fullscreen(DRM_IOCTL_ARGS); extern int radeon_cp_buffers(DRM_IOCTL_ARGS); extern void radeon_freelist_reset(struct drm_device * dev); -extern drm_buf_t *radeon_freelist_get(struct drm_device * dev); +extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); diff --git a/shared-core/savage_bci.c b/shared-core/savage_bci.c index 5a41b238..a3fd8994 100644 --- a/shared-core/savage_bci.c +++ b/shared-core/savage_bci.c @@ -207,7 +207,7 @@ static int savage_freelist_init(struct drm_device *dev) { drm_savage_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; - drm_buf_t *buf; + struct drm_buf *buf; drm_savage_buf_priv_t *entry; int i; DRM_DEBUG("count=%d\n", dma->buf_count); @@ -236,7 +236,7 @@ static int savage_freelist_init(struct drm_device *dev) return 0; } -static drm_buf_t *savage_freelist_get(struct drm_device *dev) +static struct drm_buf *savage_freelist_get(struct drm_device *dev) { drm_savage_private_t *dev_priv = dev->dev_private; drm_savage_buf_priv_t *tail = dev_priv->tail.prev; @@ -269,7 +269,7 @@ static drm_buf_t *savage_freelist_get(struct drm_device *dev) return NULL; } -void savage_freelist_put(struct drm_device *dev, drm_buf_t *buf) +void savage_freelist_put(struct drm_device *dev, struct drm_buf *buf) { drm_savage_private_t *dev_priv = dev->dev_private; drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next; @@ -1008,7 +1008,7 @@ static int savage_bci_event_wait(DRM_IOCTL_ARGS) static int savage_bci_get_buffers(DRMFILE filp, struct drm_device *dev, struct drm_dma *d) { - drm_buf_t *buf; + struct drm_buf *buf; int i; for (i = d->granted_count; i < d->request_count; i++) { @@ -1084,7 +1084,7 @@ void savage_reclaim_buffers(struct drm_device *dev, DRMFILE filp) /*i830_flush_queue(dev);*/ for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[i]; + struct drm_buf *buf = dma->buflist[i]; drm_savage_buf_priv_t *buf_priv = buf->dev_private; if (buf->filp == filp && buf_priv && diff --git a/shared-core/savage_drv.h b/shared-core/savage_drv.h index 39c2c751..e9e2231f 100644 --- a/shared-core/savage_drv.h +++ b/shared-core/savage_drv.h @@ -58,7 +58,7 @@ typedef struct drm_savage_buf_priv { struct drm_savage_buf_priv *next; struct drm_savage_buf_priv *prev; drm_savage_age_t age; - drm_buf_t *buf; + struct drm_buf *buf; } drm_savage_buf_priv_t; typedef struct drm_savage_dma_page { @@ -203,7 +203,7 @@ extern int savage_bci_buffers(DRM_IOCTL_ARGS); /* BCI functions */ extern uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, unsigned int flags); -extern void savage_freelist_put(struct drm_device *dev, drm_buf_t *buf); +extern void savage_freelist_put(struct drm_device *dev, struct drm_buf *buf); extern void savage_dma_reset(drm_savage_private_t *dev_priv); extern void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page); extern uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, diff --git a/shared-core/savage_state.c b/shared-core/savage_state.c index 93d2081b..290796ee 100644 --- a/shared-core/savage_state.c +++ b/shared-core/savage_state.c @@ -275,7 +275,7 @@ static int savage_dispatch_state(drm_savage_private_t *dev_priv, static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv, const drm_savage_cmd_header_t *cmd_header, - const drm_buf_t *dmabuf) + const struct drm_buf *dmabuf) { unsigned char reorder = 0; unsigned int prim = cmd_header->prim.prim; @@ -534,7 +534,7 @@ static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv, static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv, const drm_savage_cmd_header_t *cmd_header, const uint16_t *idx, - const drm_buf_t *dmabuf) + const struct drm_buf *dmabuf) { unsigned char reorder = 0; unsigned int prim = cmd_header->idx.prim; @@ -891,7 +891,7 @@ static int savage_dispatch_swap(drm_savage_private_t *dev_priv, static int savage_dispatch_draw(drm_savage_private_t *dev_priv, const drm_savage_cmd_header_t *start, const drm_savage_cmd_header_t *end, - const drm_buf_t *dmabuf, + const struct drm_buf *dmabuf, const unsigned int *vtxbuf, unsigned int vb_size, unsigned int vb_stride, unsigned int nbox, @@ -957,7 +957,7 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) DRM_DEVICE; drm_savage_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; - drm_buf_t *dmabuf; + struct drm_buf *dmabuf; drm_savage_cmdbuf_t cmdbuf; drm_savage_cmd_header_t *kcmd_addr = NULL; drm_savage_cmd_header_t *first_draw_cmd; -- cgit v1.2.3 From 3f04fe7890fe7728e7df37a6b65ad328a46699bf Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 16 Jul 2007 01:53:06 -0700 Subject: Fix FreeBSD build. --- shared-core/i915_dma.c | 14 +++++++++----- shared-core/i915_drv.h | 14 +++++++++----- 2 files changed, 18 insertions(+), 10 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index dbc5f959..535a061a 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -855,12 +855,14 @@ static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t); static int i915_mmio(DRM_IOCTL_ARGS) { - char buf[32]; + uint32_t buf[8]; DRM_DEVICE; drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_mmio_entry_t *e; drm_i915_mmio_t mmio; void __iomem *base; + int i; + if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); @@ -878,7 +880,8 @@ static int i915_mmio(DRM_IOCTL_ARGS) case I915_MMIO_READ: if (!(e->flag & I915_MMIO_MAY_READ)) return DRM_ERR(EINVAL); - memcpy_fromio(buf, base, e->size); + for (i = 0; i < e->size / 4; i++) + buf[i] = I915_READ(e->offset + i * 4); if (DRM_COPY_TO_USER(mmio.data, buf, e->size)) { DRM_ERROR("DRM_COPY_TO_USER failed\n"); return DRM_ERR(EFAULT); @@ -892,7 +895,8 @@ static int i915_mmio(DRM_IOCTL_ARGS) DRM_ERROR("DRM_COPY_TO_USER failed\n"); return DRM_ERR(EFAULT); } - memcpy_toio(base, buf, e->size); + for (i = 0; i < e->size / 4; i++) + I915_WRITE(e->offset + i * 4, buf[i]); break; } return 0; @@ -910,11 +914,11 @@ static int i915_set_status_page(DRM_IOCTL_ARGS) } DRM_COPY_FROM_USER_IOCTL(hws, (drm_i915_hws_addr_t __user *) data, sizeof(hws)); - printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws.addr); + DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws.addr); dev_priv->status_gfx_addr = hws.addr & (0x1ffff<<12); - dev_priv->hws_map.offset = dev->agp->agp_info.aper_base + hws.addr; + dev_priv->hws_map.offset = dev->agp->base + hws.addr; dev_priv->hws_map.size = 4*1024; dev_priv->hws_map.type = 0; dev_priv->hws_map.flags = 0; diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index e0432996..60b32b0d 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -39,6 +39,11 @@ #define DRIVER_DESC "Intel Graphics" #define DRIVER_DATE "20070209" +#if defined(__linux__) +#define I915_HAVE_FENCE +#define I915_HAVE_BUFFER +#endif + /* Interface history: * * 1.1: Original. @@ -52,13 +57,12 @@ * 1.9: Usable page flipping and triple buffering */ #define DRIVER_MAJOR 1 +#if defined(I915_HAVE_FENCE) && defined(I915_HAVE_BUFFER) #define DRIVER_MINOR 9 -#define DRIVER_PATCHLEVEL 0 - -#if defined(__linux__) -#define I915_HAVE_FENCE -#define I915_HAVE_BUFFER +#else +#define DRIVER_MINOR 6 #endif +#define DRIVER_PATCHLEVEL 0 typedef struct _drm_i915_ring_buffer { int tail_mask; -- cgit v1.2.3 From 70a8a60a3e81c18f9c6485102cb226c340c3cd73 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Mon, 16 Jul 2007 10:56:43 -0700 Subject: Correct errors in the usage of pci_map_page. With these changes the driver no longer instantly hard-locks a 6600LE on a PowerPC G5. I haven't tested any 3D apps yet. --- shared-core/nouveau_object.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 146c4f1c..ea0edb08 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -672,10 +672,10 @@ nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class, pci_map_page(dev->pdev, dev->sg->pagelist[idx], 0, - DMA_31BIT_MASK, + PAGE_SIZE, DMA_BIDIRECTIONAL); - if (dev->sg->busaddr[idx] == 0) { + if (dma_mapping_error(dev->sg->busaddr[idx])) { return DRM_ERR(ENOMEM); } } -- cgit v1.2.3 From ec67c2def9af16bf9252d6742aec815b817f135a Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 15 Jul 2007 17:18:15 +1000 Subject: nouveau: G8x PCIEGART Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART support for G8X using the current mm has been hacked on top of it. --- shared-core/nouveau_drv.h | 35 +++++++- shared-core/nouveau_fifo.c | 31 ++++--- shared-core/nouveau_mem.c | 187 +++++++++++++++++++++++------------------ shared-core/nouveau_notifier.c | 3 +- shared-core/nouveau_object.c | 136 ++++++++++++++++++++++-------- shared-core/nouveau_state.c | 9 +- shared-core/nv50_graph.c | 2 +- 7 files changed, 269 insertions(+), 134 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 4fa979e6..f68304c9 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -118,6 +118,10 @@ struct nouveau_fifo struct nouveau_gpuobj_ref *ramin_grctx; uint32_t pgraph_ctx [340]; /* XXX dynamic alloc ? */ + /* NV50 VM */ + struct nouveau_gpuobj *vm_pd; + struct nouveau_gpuobj_ref *vm_gart_pt; + /* Objects */ struct nouveau_gpuobj_ref *ramin; /* Private instmem */ struct mem_block *ramin_heap; /* Private PRAMIN heap */ @@ -220,8 +224,24 @@ struct drm_nouveau_private { /* base physical adresses */ uint64_t fb_phys; uint64_t fb_available_size; - uint64_t agp_phys; - uint64_t agp_available_size; + + struct { + enum { + NOUVEAU_GART_NONE = 0, + NOUVEAU_GART_AGP, + NOUVEAU_GART_SGDMA + } type; + uint64_t aper_base; + uint64_t aper_size; + + struct nouveau_gpuobj *sg_ctxdma; + struct page *sg_dummy_page; + dma_addr_t sg_dummy_bus; + + /* nottm hack */ + struct drm_ttm_backend *sg_be; + unsigned long sg_handle; + } gart_info; /* the mtrr covering the FB */ int fb_mtrr; @@ -307,6 +327,10 @@ extern int nouveau_gpuobj_dma_new(struct drm_device *, int channel, int class, uint64_t offset, uint64_t size, int access, int target, struct nouveau_gpuobj **); +extern int nouveau_gpuobj_gart_dma_new(struct drm_device *, int channel, + uint64_t offset, uint64_t size, + int access, struct nouveau_gpuobj **, + uint32_t *o_ret); extern int nouveau_gpuobj_gr_new(struct drm_device *, int channel, int class, struct nouveau_gpuobj **); extern int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS); @@ -317,6 +341,13 @@ extern void nouveau_irq_preinstall(struct drm_device*); extern void nouveau_irq_postinstall(struct drm_device*); extern void nouveau_irq_uninstall(struct drm_device*); +/* nouveau_sgdma.c */ +extern int nouveau_sgdma_init(struct drm_device *); +extern void nouveau_sgdma_takedown(struct drm_device *); +extern struct drm_ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); +extern int nouveau_sgdma_nottm_hack_init(struct drm_device *); +extern void nouveau_sgdma_nottm_hack_takedown(struct drm_device *); + /* nv04_fb.c */ extern int nv04_fb_init(struct drm_device *dev); extern void nv04_fb_takedown(struct drm_device *dev); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 56c25a6e..230c8298 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -211,24 +211,27 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) } if (cb->flags & NOUVEAU_MEM_AGP) { - DRM_DEBUG("Creating CB in AGP memory\n"); + ret = nouveau_gpuobj_gart_dma_new(dev, channel, + cb->start, cb->size, + NV_DMA_ACCESS_RO, + &pushbuf, + &chan->pushbuf_base); + } else + if (cb->flags & NOUVEAU_MEM_PCI) { ret = nouveau_gpuobj_dma_new(dev, channel, - NV_CLASS_DMA_IN_MEMORY, - cb->start, cb->size, - NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP, &pushbuf); - } else if ( cb->flags & NOUVEAU_MEM_PCI) { - DRM_DEBUG("Creating CB in PCI memory\n"); - ret = nouveau_gpuobj_dma_new(dev, channel, - NV_CLASS_DMA_IN_MEMORY, - cb->start, - cb->size, - NV_DMA_ACCESS_RO, NV_DMA_TARGET_PCI_NONLINEAR, &pushbuf); + NV_CLASS_DMA_IN_MEMORY, + cb->start, cb->size, + NV_DMA_ACCESS_RO, + NV_DMA_TARGET_PCI_NONLINEAR, + &pushbuf); + chan->pushbuf_base = 0; } else if (dev_priv->card_type != NV_04) { ret = nouveau_gpuobj_dma_new (dev, channel, NV_CLASS_DMA_IN_MEMORY, cb->start, cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM, &pushbuf); + chan->pushbuf_base = 0; } else { /* NV04 cmdbuf hack, from original ddx.. not sure of it's * exact reason for existing :) PCI access to cmdbuf in @@ -239,6 +242,7 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) cb->start + drm_get_resource_start(dev, 1), cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_PCI, &pushbuf); + chan->pushbuf_base = 0; } if (ret) { @@ -250,11 +254,12 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) if ((ret = nouveau_gpuobj_ref_add(dev, channel, 0, pushbuf, &chan->pushbuf))) { DRM_ERROR("Error referencing push buffer ctxdma: %d\n", ret); + if (pushbuf != dev_priv->gart_info.sg_ctxdma) + nouveau_gpuobj_del(dev, &pushbuf); return ret; } - dev_priv->fifos[channel]->pushbuf_base = 0; - dev_priv->fifos[channel]->pushbuf_mem = cb; + chan->pushbuf_mem = cb; return 0; } diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index e5906867..7a923e17 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -209,12 +209,11 @@ void nouveau_mem_takedown(struct mem_block **heap) void nouveau_mem_close(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; + nouveau_mem_takedown(&dev_priv->agp_heap); nouveau_mem_takedown(&dev_priv->fb_heap); - if ( dev_priv->pci_heap ) - { + if (dev_priv->pci_heap) nouveau_mem_takedown(&dev_priv->pci_heap); - } } /* returns the amount of FB ram in bytes */ @@ -282,93 +281,68 @@ uint64_t nouveau_mem_fb_amount(struct drm_device *dev) return 0; } - - -int nouveau_mem_init(struct drm_device *dev) +static int +nouveau_mem_init_agp(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t fb_size; - struct drm_scatter_gather sgreq; - dev_priv->agp_phys=0; - dev_priv->fb_phys=0; - sgreq . size = 4 << 20; //4MB of PCI scatter-gather zone - - /* init AGP */ - dev_priv->agp_heap=NULL; - if (drm_device_is_agp(dev)) - { - int err; - struct drm_agp_info info; - struct drm_agp_mode mode; - struct drm_agp_buffer agp_req; - struct drm_agp_binding bind_req; - - err = drm_agp_acquire(dev); - if (err) { - DRM_ERROR("Unable to acquire AGP: %d\n", err); - goto no_agp; - } - - err = drm_agp_info(dev, &info); - if (err) { - DRM_ERROR("Unable to get AGP info: %d\n", err); - goto no_agp; - } - - /* see agp.h for the AGPSTAT_* modes available */ - mode.mode = info.mode; - err = drm_agp_enable(dev, mode); - if (err) { - DRM_ERROR("Unable to enable AGP: %d\n", err); - goto no_agp; - } - - agp_req.size = info.aperture_size; - agp_req.type = 0; - err = drm_agp_alloc(dev, &agp_req); - if (err) { - DRM_ERROR("Unable to alloc AGP: %d\n", err); - goto no_agp; - } + struct drm_agp_info info; + struct drm_agp_mode mode; + struct drm_agp_buffer agp_req; + struct drm_agp_binding bind_req; + int ret; + + ret = drm_agp_acquire(dev); + if (ret) { + DRM_ERROR("Unable to acquire AGP: %d\n", ret); + return ret; + } - bind_req.handle = agp_req.handle; - bind_req.offset = 0; - err = drm_agp_bind(dev, &bind_req); - if (err) { - DRM_ERROR("Unable to bind AGP: %d\n", err); - goto no_agp; - } + ret = drm_agp_info(dev, &info); + if (ret) { + DRM_ERROR("Unable to get AGP info: %d\n", ret); + return ret; + } - if (nouveau_mem_init_heap(&dev_priv->agp_heap, - 0, info.aperture_size)) - goto no_agp; + /* see agp.h for the AGPSTAT_* modes available */ + mode.mode = info.mode; + ret = drm_agp_enable(dev, mode); + if (ret) { + DRM_ERROR("Unable to enable AGP: %d\n", ret); + return ret; + } - dev_priv->agp_phys = info.aperture_base; - dev_priv->agp_available_size = info.aperture_size; - goto have_agp; + agp_req.size = info.aperture_size; + agp_req.type = 0; + ret = drm_agp_alloc(dev, &agp_req); + if (ret) { + DRM_ERROR("Unable to alloc AGP: %d\n", ret); + return ret; } -no_agp: + bind_req.handle = agp_req.handle; + bind_req.offset = 0; + ret = drm_agp_bind(dev, &bind_req); + if (ret) { + DRM_ERROR("Unable to bind AGP: %d\n", ret); + return ret; + } - if ( dev_priv->card_type >= NV_50 ) goto no_pci; + dev_priv->gart_info.type = NOUVEAU_GART_AGP; + dev_priv->gart_info.aper_base = info.aperture_base; + dev_priv->gart_info.aper_size = info.aperture_size; + return 0; +} - dev_priv->pci_heap = NULL; - DRM_DEBUG("Allocating sg memory for PCI DMA\n"); - if ( drm_sg_alloc(dev, &sgreq) ) - { - DRM_ERROR("Unable to allocate 4MB of scatter-gather pages for PCI DMA!"); - goto no_pci; - } +int nouveau_mem_init(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + uint32_t fb_size; + int ret = 0; - if ( nouveau_mem_init_heap(&dev_priv->pci_heap, 0, - dev->sg->pages * PAGE_SIZE)) - { - DRM_ERROR("Unable to initialize pci_heap!"); - goto no_pci; - } + dev_priv->agp_heap = dev_priv->pci_heap = dev_priv->fb_heap = NULL; + dev_priv->fb_phys = 0; + dev_priv->gart_info.type = NOUVEAU_GART_NONE; -no_pci: -have_agp: /* setup a mtrr over the FB */ dev_priv->fb_mtrr = drm_mtrr_add(drm_get_resource_start(dev, 1), nouveau_mem_fb_amount(dev), @@ -399,6 +373,54 @@ have_agp: dev_priv->fb_nomap_heap=NULL; } + /* Init AGP / NV50 PCIEGART */ + if (drm_device_is_agp(dev) && dev->agp) { + if ((ret = nouveau_mem_init_agp(dev))) + DRM_ERROR("Error initialising AGP: %d\n", ret); + } + + /*Note: this is *not* just NV50 code, but only used on NV50 for now */ + if (dev_priv->gart_info.type == NOUVEAU_GART_NONE && + dev_priv->card_type >= NV_50) { + ret = nouveau_sgdma_init(dev); + if (!ret) { + ret = nouveau_sgdma_nottm_hack_init(dev); + if (ret) + nouveau_sgdma_takedown(dev); + } + + if (ret) + DRM_ERROR("Error initialising SG DMA: %d\n", ret); + } + + if (dev_priv->gart_info.type != NOUVEAU_GART_NONE) { + if (nouveau_mem_init_heap(&dev_priv->agp_heap, + 0, dev_priv->gart_info.aper_size)) { + if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA) { + nouveau_sgdma_nottm_hack_takedown(dev); + nouveau_sgdma_takedown(dev); + } + } + } + + /* NV04-NV40 PCIEGART */ + if (!dev_priv->agp_heap && dev_priv->card_type < NV_50) { + struct drm_scatter_gather sgreq; + + DRM_DEBUG("Allocating sg memory for PCI DMA\n"); + sgreq.size = 4 << 20; //4MB of PCI scatter-gather zone + + if (drm_sg_alloc(dev, &sgreq)) { + DRM_ERROR("Unable to allocate 4MB of scatter-gather" + " pages for PCI DMA!"); + } else { + if (nouveau_mem_init_heap(&dev_priv->pci_heap, 0, + dev->sg->pages * PAGE_SIZE)) { + DRM_ERROR("Unable to initialize pci_heap!"); + } + } + } + return 0; } @@ -473,9 +495,14 @@ alloc_ok: int ret = 0; block->flags|=NOUVEAU_MEM_MAPPED; - if (type == NOUVEAU_MEM_AGP) + if (type == NOUVEAU_MEM_AGP) { + if (dev_priv->gart_info.type != NOUVEAU_GART_SGDMA) ret = drm_addmap(dev, block->start, block->size, _DRM_AGP, 0, &block->map); + else + ret = drm_addmap(dev, block->start, block->size, + _DRM_SCATTER_GATHER, 0, &block->map); + } else if (type == NOUVEAU_MEM_FB) ret = drm_addmap(dev, block->start + dev_priv->fb_phys, block->size, _DRM_FRAME_BUFFER, diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index 36dba654..238e3c8b 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -37,7 +37,8 @@ nouveau_notifier_init_channel(struct drm_device *dev, int channel, DRMFILE filp) int flags, ret; /*TODO: PCI notifier blocks */ - if (dev_priv->agp_heap) + if (dev_priv->agp_heap && + dev_priv->gart_info.type != NOUVEAU_GART_SGDMA) flags = NOUVEAU_MEM_AGP | NOUVEAU_MEM_FB_ACCEPTABLE; else flags = NOUVEAU_MEM_FB; diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index ea0edb08..f0025d7a 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -596,7 +596,7 @@ nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class, switch (target) { case NV_DMA_TARGET_AGP: - offset += dev_priv->agp_phys; + offset += dev_priv->gart_info.aper_base; break; case NV_DMA_TARGET_PCI_NONLINEAR: /*assume the "offset" is a virtual memory address*/ @@ -689,10 +689,20 @@ nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class, } } } else { - INSTANCE_WR(*gpuobj, 0, 0x00190000 | class); + uint32_t flags0, flags5; + + if (target == NV_DMA_TARGET_VIDMEM) { + flags0 = 0x00190000; + flags5 = 0x00010000; + } else { + flags0 = 0x7fc00000; + flags5 = 0x00080000; + } + + INSTANCE_WR(*gpuobj, 0, flags0 | class); INSTANCE_WR(*gpuobj, 1, offset + size - 1); INSTANCE_WR(*gpuobj, 2, offset); - INSTANCE_WR(*gpuobj, 5, 0x00010000); + INSTANCE_WR(*gpuobj, 5, flags5); } (*gpuobj)->engine = NVOBJ_ENGINE_SW; @@ -700,6 +710,42 @@ nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class, return 0; } +int +nouveau_gpuobj_gart_dma_new(struct drm_device *dev, int channel, + uint64_t offset, uint64_t size, int access, + struct nouveau_gpuobj **gpuobj, + uint32_t *o_ret) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int ret; + + if (dev_priv->gart_info.type == NOUVEAU_GART_AGP || + (dev_priv->card_type >= NV_50 && + dev_priv->gart_info.type == NOUVEAU_GART_SGDMA)) { + ret = nouveau_gpuobj_dma_new(dev, channel, + NV_CLASS_DMA_IN_MEMORY, + offset, size, access, + NV_DMA_TARGET_AGP, gpuobj); + if (o_ret) + *o_ret = 0; + } else + if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA) { + *gpuobj = dev_priv->gart_info.sg_ctxdma; + if (offset & ~0xffffffffULL) { + DRM_ERROR("obj offset exceeds 32-bits\n"); + return DRM_ERR(EINVAL); + } + if (o_ret) + *o_ret = (uint32_t)offset; + ret = (*gpuobj != NULL) ? 0 : DRM_ERR(EINVAL); + } else { + DRM_ERROR("Invalid GART type %d\n", dev_priv->gart_info.type); + return DRM_ERR(EINVAL); + } + + return ret; +} + /* Context objects in the instance RAM have the following structure. * On NV40 they are 32 byte long, on NV30 and smaller 16 bytes. @@ -857,7 +903,7 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel, struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; struct nouveau_gpuobj *vram = NULL, *tt = NULL; - int ret; + int ret, i; DRM_DEBUG("ch%d vram=0x%08x tt=0x%08x\n", channel, vram_h, tt_h); @@ -870,6 +916,29 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel, return ret; } + /* NV50 VM, point offset 0-512MiB at shared PCIEGART table */ + if (dev_priv->card_type >= NV_50) { + uint32_t vm_offset; + + vm_offset = (dev_priv->chipset & 0xf0) == 0x50 ? 0x1400 : 0x200; + vm_offset += chan->ramin->gpuobj->im_pramin->start; + if ((ret = nouveau_gpuobj_new_fake(dev, vm_offset, 0x4000, + 0, &chan->vm_pd, NULL))) + return ret; + for (i=0; i<0x4000; i+=8) { + INSTANCE_WR(chan->vm_pd, (i+0)/4, 0x00000000); + INSTANCE_WR(chan->vm_pd, (i+4)/4, 0xdeadcafe); + } + + if ((ret = nouveau_gpuobj_ref_add(dev, -1, 0, + dev_priv->gart_info.sg_ctxdma, + &chan->vm_gart_pt))) + return ret; + INSTANCE_WR(chan->vm_pd, (0+0)/4, + chan->vm_gart_pt->instance | 0x03); + INSTANCE_WR(chan->vm_pd, (0+4)/4, 0x00000000); + } + /* RAMHT */ if (dev_priv->card_type < NV_50) { ret = nouveau_gpuobj_ref_add(dev, -1, 0, dev_priv->ramht, @@ -899,40 +968,34 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel, return ret; } - if (dev_priv->agp_heap) { - /* AGPGART ctxdma */ - if ((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, - 0, dev_priv->agp_available_size, - NV_DMA_ACCESS_RW, - NV_DMA_TARGET_AGP, &tt))) { - DRM_ERROR("Error creating AGP TT ctxdma: %d\n", DRM_ERR(ENOMEM)); - return DRM_ERR(ENOMEM); - } - - ret = nouveau_gpuobj_ref_add(dev, channel, tt_h, tt, NULL); - if (ret) { - DRM_ERROR("Error referencing AGP TT ctxdma: %d\n", ret); - return ret; - } + /* TT memory ctxdma */ + if (dev_priv->gart_info.type != NOUVEAU_GART_NONE) { + ret = nouveau_gpuobj_gart_dma_new(dev, channel, 0, + dev_priv->gart_info.aper_size, + NV_DMA_ACCESS_RW, &tt, NULL); + } else + if (dev_priv->pci_heap) { + ret = nouveau_gpuobj_dma_new(dev, channel, + NV_CLASS_DMA_IN_MEMORY, + 0, dev->sg->pages * PAGE_SIZE, + NV_DMA_ACCESS_RW, + NV_DMA_TARGET_PCI_NONLINEAR, &tt); + } else { + DRM_ERROR("Invalid GART type %d\n", dev_priv->gart_info.type); + ret = DRM_ERR(EINVAL); } - else if ( dev_priv->pci_heap) { - if (dev_priv -> card_type >= NV_50 ) return 0; /*no PCIGART for NV50*/ - /*PCI*/ - if((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, - 0, dev->sg->pages * PAGE_SIZE, - NV_DMA_ACCESS_RW, - NV_DMA_TARGET_PCI_NONLINEAR, &tt))) { - DRM_ERROR("Error creating PCI TT ctxdma: %d\n", DRM_ERR(ENOMEM)); - return 0; //this is noncritical - } - - ret = nouveau_gpuobj_ref_add(dev, channel, tt_h, tt, NULL); - if (ret) { - DRM_ERROR("Error referencing PCI TT ctxdma: %d\n", ret); - return ret; - } + if (ret) { + DRM_ERROR("Error creating TT ctxdma: %d\n", ret); + return ret; } + + ret = nouveau_gpuobj_ref_add(dev, channel, tt_h, tt, NULL); + if (ret) { + DRM_ERROR("Error referencing TT ctxdma: %d\n", ret); + return ret; + } + return 0; } @@ -951,6 +1014,9 @@ nouveau_gpuobj_channel_takedown(struct drm_device *dev, int channel) } nouveau_gpuobj_ref_del(dev, &chan->ramht); + nouveau_gpuobj_del(dev, &chan->vm_pd); + nouveau_gpuobj_ref_del(dev, &chan->vm_gart_pt); + if (chan->ramin_heap) nouveau_mem_takedown(&chan->ramin_heap); if (chan->ramin) diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 69e9c221..4e3b39dd 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -332,7 +332,12 @@ static void nouveau_card_takedown(struct drm_device *dev) engine->fb.takedown(dev); engine->timer.takedown(dev); engine->mc.takedown(dev); + + nouveau_sgdma_nottm_hack_takedown(dev); + nouveau_sgdma_takedown(dev); + nouveau_gpuobj_takedown(dev); + nouveau_mem_close(dev); engine->instmem.takedown(dev); @@ -442,7 +447,7 @@ int nouveau_ioctl_getparam(DRM_IOCTL_ARGS) getparam.value=dev_priv->fb_phys; break; case NOUVEAU_GETPARAM_AGP_PHYSICAL: - getparam.value=dev_priv->agp_phys; + getparam.value=dev_priv->gart_info.aper_base; break; case NOUVEAU_GETPARAM_PCI_PHYSICAL: if ( dev -> sg ) @@ -457,7 +462,7 @@ int nouveau_ioctl_getparam(DRM_IOCTL_ARGS) getparam.value=dev_priv->fb_available_size; break; case NOUVEAU_GETPARAM_AGP_SIZE: - getparam.value=dev_priv->agp_available_size; + getparam.value=dev_priv->gart_info.aper_size; break; default: DRM_ERROR("unknown parameter %lld\n", getparam.param); diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c index 54fe498b..6a04c158 100644 --- a/shared-core/nv50_graph.c +++ b/shared-core/nv50_graph.c @@ -271,7 +271,7 @@ nv50_graph_load_context(struct drm_device *dev, int channel) struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t inst = ((chan->ramin->instance >> 12) | (1<<31)); - int ret; + int ret; (void)ret; DRM_DEBUG("ch%d\n", channel); -- cgit v1.2.3 From 658ff2daf3d2a080da2d859f522a627aef841637 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Mon, 16 Jul 2007 20:58:43 -0700 Subject: Eliminate several useless ioctls and associated cruft. The ioctlss XGI_ESC_DEVICE_INFO, XGI_ESC_MEM_COLLECT, XGI_ESC_PCIE_CHECK, XGI_ESC_GET_SCREEN_INFO, XGI_ESC_PUT_SCREEN_INFO, XGI_ESC_MMIO_INFO, and XGI_ESC_SAREA_INFO, are completely unnecessary. The will be doubly useless when the driver is converted to the DRM infrastructure. --- shared-core/xgi_drm.h | 64 ++++++++++++++++----------------------------------- 1 file changed, 20 insertions(+), 44 deletions(-) (limited to 'shared-core') diff --git a/shared-core/xgi_drm.h b/shared-core/xgi_drm.h index 0abf390a..bc39cbf7 100644 --- a/shared-core/xgi_drm.h +++ b/shared-core/xgi_drm.h @@ -31,15 +31,17 @@ #include #include -struct xgi_chip_info { +struct drm_xgi_sarea { __u16 device_id; __u16 vendor_id; char device_name[32]; - unsigned int curr_display_mode; //Singe, DualView(Contained), MHS - unsigned int fb_size; - unsigned long sarea_bus_addr; - unsigned int sarea_size; + + unsigned int scrn_start; + unsigned int scrn_xres; + unsigned int scrn_yres; + unsigned int scrn_bpp; + unsigned int scrn_pitch; }; enum xgi_mem_location { @@ -65,14 +67,6 @@ struct xgi_mem_alloc { unsigned long bus_addr; }; -struct xgi_screen_info { - unsigned int scrn_start; - unsigned int scrn_xres; - unsigned int scrn_yres; - unsigned int scrn_bpp; - unsigned int scrn_pitch; -}; - struct xgi_sarea_info { unsigned long bus_addr; unsigned int size; @@ -114,53 +108,35 @@ struct xgi_mmio_info { #define XGI_IOCTL_MAGIC 'x' /* use 'x' as magic number */ #define XGI_IOCTL_BASE 0 -#define XGI_ESC_DEVICE_INFO (XGI_IOCTL_BASE + 0) -#define XGI_ESC_POST_VBIOS (XGI_IOCTL_BASE + 1) - -#define XGI_ESC_FB_INIT (XGI_IOCTL_BASE + 2) -#define XGI_ESC_FB_ALLOC (XGI_IOCTL_BASE + 3) -#define XGI_ESC_FB_FREE (XGI_IOCTL_BASE + 4) -#define XGI_ESC_PCIE_INIT (XGI_IOCTL_BASE + 5) -#define XGI_ESC_PCIE_ALLOC (XGI_IOCTL_BASE + 6) -#define XGI_ESC_PCIE_FREE (XGI_IOCTL_BASE + 7) -#define XGI_ESC_SUBMIT_CMDLIST (XGI_IOCTL_BASE + 8) -#define XGI_ESC_PUT_SCREEN_INFO (XGI_IOCTL_BASE + 9) -#define XGI_ESC_GET_SCREEN_INFO (XGI_IOCTL_BASE + 10) -#define XGI_ESC_GE_RESET (XGI_IOCTL_BASE + 11) -#define XGI_ESC_SAREA_INFO (XGI_IOCTL_BASE + 12) -#define XGI_ESC_DUMP_REGISTER (XGI_IOCTL_BASE + 13) -#define XGI_ESC_DEBUG_INFO (XGI_IOCTL_BASE + 14) -#define XGI_ESC_TEST_RWINKERNEL (XGI_IOCTL_BASE + 16) -#define XGI_ESC_STATE_CHANGE (XGI_IOCTL_BASE + 17) -#define XGI_ESC_MMIO_INFO (XGI_IOCTL_BASE + 18) -#define XGI_ESC_PCIE_CHECK (XGI_IOCTL_BASE + 19) -#define XGI_ESC_MEM_COLLECT (XGI_IOCTL_BASE + 20) - -#define XGI_IOCTL_DEVICE_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_DEVICE_INFO, struct xgi_chip_info) +#define XGI_ESC_POST_VBIOS (XGI_IOCTL_BASE + 0) + +#define XGI_ESC_FB_ALLOC (XGI_IOCTL_BASE + 1) +#define XGI_ESC_FB_FREE (XGI_IOCTL_BASE + 2) +#define XGI_ESC_PCIE_ALLOC (XGI_IOCTL_BASE + 3) +#define XGI_ESC_PCIE_FREE (XGI_IOCTL_BASE + 4) +#define XGI_ESC_SUBMIT_CMDLIST (XGI_IOCTL_BASE + 5) +#define XGI_ESC_GE_RESET (XGI_IOCTL_BASE + 6) +#define XGI_ESC_DUMP_REGISTER (XGI_IOCTL_BASE + 7) +#define XGI_ESC_DEBUG_INFO (XGI_IOCTL_BASE + 8) +#define XGI_ESC_TEST_RWINKERNEL (XGI_IOCTL_BASE + 9) +#define XGI_ESC_STATE_CHANGE (XGI_IOCTL_BASE + 10) + #define XGI_IOCTL_POST_VBIOS _IO(XGI_IOCTL_MAGIC, XGI_ESC_POST_VBIOS) -#define XGI_IOCTL_FB_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_FB_INIT) #define XGI_IOCTL_FB_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_FB_ALLOC, struct xgi_mem_alloc) #define XGI_IOCTL_FB_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_FB_FREE, unsigned long) -#define XGI_IOCTL_PCIE_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_INIT) #define XGI_IOCTL_PCIE_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_ALLOC, struct xgi_mem_alloc) #define XGI_IOCTL_PCIE_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_FREE, unsigned long) -#define XGI_IOCTL_PUT_SCREEN_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PUT_SCREEN_INFO, struct xgi_screen_info) -#define XGI_IOCTL_GET_SCREEN_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_GET_SCREEN_INFO, struct xgi_screen_info) - #define XGI_IOCTL_GE_RESET _IO(XGI_IOCTL_MAGIC, XGI_ESC_GE_RESET) -#define XGI_IOCTL_SAREA_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_SAREA_INFO, struct xgi_sarea_info) #define XGI_IOCTL_DUMP_REGISTER _IO(XGI_IOCTL_MAGIC, XGI_ESC_DUMP_REGISTER) #define XGI_IOCTL_DEBUG_INFO _IO(XGI_IOCTL_MAGIC, XGI_ESC_DEBUG_INFO) -#define XGI_IOCTL_MMIO_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_MMIO_INFO, struct xgi_mmio_info) #define XGI_IOCTL_SUBMIT_CMDLIST _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_SUBMIT_CMDLIST, struct xgi_cmd_info) #define XGI_IOCTL_TEST_RWINKERNEL _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_TEST_RWINKERNEL, unsigned long) #define XGI_IOCTL_STATE_CHANGE _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_STATE_CHANGE, struct xgi_state_info) -#define XGI_IOCTL_PCIE_CHECK _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_CHECK) #define XGI_IOCTL_MAXNR 30 /* -- cgit v1.2.3 From 875dd1e53852d231b60eb82bfed33c016f92f3b8 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 17 Jul 2007 14:06:05 +1000 Subject: nouveau: Destroy PGRAPH context table on PGRAPH takedown --- shared-core/nv20_graph.c | 3 +++ shared-core/nv30_graph.c | 3 +++ 2 files changed, 6 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index e6aa1e2a..8af3bd12 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -242,5 +242,8 @@ int nv20_graph_init(struct drm_device *dev) { void nv20_graph_takedown(struct drm_device *dev) { + struct drm_nouveau_private *dev_priv = dev->dev_private; + + nouveau_gpuobj_ref_del(dev, &dev_priv->ctx_table); } diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index 23e0f7f0..d7138772 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -281,5 +281,8 @@ int nv30_graph_init(struct drm_device *dev) void nv30_graph_takedown(struct drm_device *dev) { + struct drm_nouveau_private *dev_priv = dev->dev_private; + + nouveau_gpuobj_ref_del(dev, &dev_priv->ctx_table); } -- cgit v1.2.3 From 2b6ea465134e72fa6aa96df5e40fbc91b561ef00 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Mon, 16 Jul 2007 21:11:22 -0700 Subject: Eliminate unnecessary structures and defines. --- shared-core/xgi_drm.h | 20 -------------------- 1 file changed, 20 deletions(-) (limited to 'shared-core') diff --git a/shared-core/xgi_drm.h b/shared-core/xgi_drm.h index bc39cbf7..67118884 100644 --- a/shared-core/xgi_drm.h +++ b/shared-core/xgi_drm.h @@ -67,11 +67,6 @@ struct xgi_mem_alloc { unsigned long bus_addr; }; -struct xgi_sarea_info { - unsigned long bus_addr; - unsigned int size; -}; - enum xgi_batch_type { BTYPE_2D = 0, BTYPE_3D = 1, @@ -95,11 +90,6 @@ struct xgi_state_info { unsigned int _toState; }; -struct xgi_mmio_info { - unsigned long mmio_base; - unsigned int size; -}; - /* * Ioctl definitions @@ -139,14 +129,4 @@ struct xgi_mmio_info { #define XGI_IOCTL_MAXNR 30 -/* - * flags - */ -#define XGI_FLAG_OPEN 0x0001 -#define XGI_FLAG_NEEDS_POSTING 0x0002 -#define XGI_FLAG_WAS_POSTED 0x0004 -#define XGI_FLAG_CONTROL 0x0010 -#define XGI_FLAG_MAP_REGS_EARLY 0x0200 - - #endif /* _XGI_DRM_H_ */ -- cgit v1.2.3 From 8d60bf2f199d57ec45feaab836b31832b9bbabb9 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Mon, 16 Jul 2007 22:15:41 -0700 Subject: Add XP5 and XP10 PCI IDs. --- shared-core/drm_pciids.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'shared-core') diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index 126974d0..4504cf77 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -720,3 +720,6 @@ 0x12d2 0x002c NV_04 "VTNT2" 0x12d2 0x00a0 NV_04 "ITNT2" +[xgi] +0x18ca 0x2200 0 "XP5" +0x18ca 0x0047 0 "XP10 / XG47" -- cgit v1.2.3 From 6ad1df217647d112a21c2e004d4e3d74c7bb0e0e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 18 Jul 2007 09:42:06 +1000 Subject: drm: remove drm_u64_t, replace with uint64_t everwhere This might break something, stdint.h inclusion in drm.h maybe required but I'm not sure yet what platforms have it what ones don't. --- shared-core/drm.h | 39 ++++++++++++++++----------------------- 1 file changed, 16 insertions(+), 23 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index 3ab63d5d..de8967ad 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -127,16 +127,9 @@ #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) #if defined(__linux__) -#if defined(__KERNEL__) -typedef __u64 drm_u64_t; -#else -typedef unsigned long long drm_u64_t; -#endif - typedef unsigned int drm_handle_t; #else #include -typedef u_int64_t drm_u64_t; typedef unsigned long drm_handle_t; /**< To mapped regions */ #endif typedef unsigned int drm_context_t; /**< GLXContext handle */ @@ -677,7 +670,7 @@ struct drm_fence_arg { unsigned int flags; unsigned int signaled; unsigned int pad64; - drm_u64_t expand_pad[3]; /*Future expansion */ + uint64_t expand_pad[3]; /*Future expansion */ }; /* Buffer permissions, referring to how the GPU uses the buffers. @@ -792,8 +785,8 @@ enum drm_bo_type { }; struct drm_bo_info_req { - drm_u64_t mask; - drm_u64_t flags; + uint64_t mask; + uint64_t flags; unsigned int handle; unsigned int hint; unsigned int fence_class; @@ -801,9 +794,9 @@ struct drm_bo_info_req { }; struct drm_bo_create_req { - drm_u64_t mask; - drm_u64_t size; - drm_u64_t buffer_start; + uint64_t mask; + uint64_t size; + uint64_t buffer_start; unsigned int hint; unsigned int page_alignment; enum drm_bo_type type; @@ -827,12 +820,12 @@ struct drm_bo_op_req { #define DRM_BO_REP_BUSY 0x00000001 struct drm_bo_info_rep { - drm_u64_t flags; - drm_u64_t mask; - drm_u64_t size; - drm_u64_t offset; - drm_u64_t arg_handle; - drm_u64_t buffer_start; + uint64_t flags; + uint64_t mask; + uint64_t size; + uint64_t offset; + uint64_t arg_handle; + uint64_t buffer_start; unsigned int handle; unsigned int fence_flags; unsigned int rep_flags; @@ -841,7 +834,7 @@ struct drm_bo_info_rep { unsigned int hw_tile_stride; unsigned int tile_info; unsigned int pad64; - drm_u64_t expand_pad[4]; /*Future expansion */ + uint64_t expand_pad[4]; /*Future expansion */ }; struct drm_bo_arg_rep { @@ -876,7 +869,7 @@ struct drm_bo_map_wait_idle_arg { }; struct drm_bo_op_arg { - drm_u64_t next; + uint64_t next; union { struct drm_bo_op_req req; struct drm_bo_arg_rep rep; @@ -905,8 +898,8 @@ struct drm_mm_init_arg { unsigned int major; unsigned int minor; unsigned int mem_type; - drm_u64_t p_offset; - drm_u64_t p_size; + uint64_t p_offset; + uint64_t p_size; }; /** -- cgit v1.2.3 From a64b5d8d3763639fbb4098500ad5c86fb8590aa7 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 18 Jul 2007 15:49:45 +1000 Subject: fix some missing whitespace/tab --- shared-core/drm.h | 12 ++++++------ shared-core/i915_dma.c | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index de8967ad..db913b1f 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -786,15 +786,15 @@ enum drm_bo_type { struct drm_bo_info_req { uint64_t mask; - uint64_t flags; - unsigned int handle; + uint64_t flags; + unsigned int handle; unsigned int hint; unsigned int fence_class; unsigned int pad64; }; struct drm_bo_create_req { - uint64_t mask; + uint64_t mask; uint64_t size; uint64_t buffer_start; unsigned int hint; @@ -820,8 +820,8 @@ struct drm_bo_op_req { #define DRM_BO_REP_BUSY 0x00000001 struct drm_bo_info_rep { - uint64_t flags; - uint64_t mask; + uint64_t flags; + uint64_t mask; uint64_t size; uint64_t offset; uint64_t arg_handle; @@ -831,7 +831,7 @@ struct drm_bo_info_rep { unsigned int rep_flags; unsigned int page_alignment; unsigned int desired_tile_stride; - unsigned int hw_tile_stride; + unsigned int hw_tile_stride; unsigned int tile_info; unsigned int pad64; uint64_t expand_pad[4]; /*Future expansion */ diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index fbad27c0..c3a41bd5 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -874,7 +874,7 @@ static int i915_mmio(DRM_IOCTL_ARGS) e = &mmio_table[mmio.reg]; base = (u8 *) dev_priv->mmio_map->handle + e->offset; - switch (mmio.read_write) { + switch (mmio.read_write) { case I915_MMIO_READ: if (!(e->flag & I915_MMIO_MAY_READ)) return DRM_ERR(EINVAL); -- cgit v1.2.3 From 14ecf8d6c2ccecbe9841ad4a7eb3b301685f2351 Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Fri, 6 Jul 2007 12:47:53 +0300 Subject: nouveau: Replace 0x00400104 and 0x00400108 with names. NV03_PGRAPH_NSTATUS and NV03_PGRAPH_NSOURCE. The prefix NV03 is chosen because nv10reg.h had no versioned prefix, and the code using these registers does not check card_type. --- shared-core/nouveau_irq.c | 15 ++++++++------- shared-core/nouveau_reg.h | 2 ++ 2 files changed, 10 insertions(+), 7 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 84319219..ffc4bac6 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -266,7 +266,8 @@ nouveau_graph_dump_trap_info(struct drm_device *dev) } DRM_ERROR("NV: nSource: 0x%08x, nStatus: 0x%08x\n", - NV_READ(0x400108), NV_READ(0x400104)); + NV_READ(NV03_PGRAPH_NSOURCE), + NV_READ(NV03_PGRAPH_NSTATUS)); DRM_ERROR("NV: Channel %d/%d (class 0x%04x) -" "Method 0x%04x, Data 0x%08x\n", channel, subc, class, method, data @@ -286,8 +287,8 @@ static void nouveau_pgraph_irq_handler(struct drm_device *dev) uint32_t nsource, nstatus, instance, notify; DRM_DEBUG("NV: PGRAPH notify interrupt\n"); - nstatus = NV_READ(0x00400104); - nsource = NV_READ(0x00400108); + nstatus = NV_READ(NV03_PGRAPH_NSTATUS); + nsource = NV_READ(NV03_PGRAPH_NSOURCE); DRM_DEBUG("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus); /* if this wasn't NOTIFICATION_PENDING, dump extra trap info */ @@ -308,8 +309,8 @@ static void nouveau_pgraph_irq_handler(struct drm_device *dev) uint32_t nsource, nstatus, instance, notify; DRM_DEBUG("NV: PGRAPH buffer notify interrupt\n"); - nstatus = NV_READ(0x00400104); - nsource = NV_READ(0x00400108); + nstatus = NV_READ(NV03_PGRAPH_NSTATUS); + nsource = NV_READ(NV03_PGRAPH_NSOURCE); DRM_DEBUG("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus); instance = NV_READ(0x00400158); @@ -332,8 +333,8 @@ static void nouveau_pgraph_irq_handler(struct drm_device *dev) DRM_ERROR("NV: PGRAPH error interrupt\n"); - nstatus = NV_READ(0x00400104); - nsource = NV_READ(0x00400108); + nstatus = NV_READ(NV03_PGRAPH_NSTATUS); + nsource = NV_READ(NV03_PGRAPH_NSOURCE); DRM_ERROR("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus); instance = NV_READ(0x00400158); diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index a66d2d34..bcdb1a9f 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -110,6 +110,8 @@ #define NV04_PGRAPH_DEBUG_3 0x0040008c #define NV10_PGRAPH_DEBUG_4 0x00400090 #define NV03_PGRAPH_INTR 0x00400100 +#define NV03_PGRAPH_NSTATUS 0x00400104 +#define NV03_PGRAPH_NSOURCE 0x00400108 #define NV03_PGRAPH_INTR_EN 0x00400140 #define NV40_PGRAPH_INTR_EN 0x0040013C # define NV_PGRAPH_INTR_NOTIFY (1<< 0) -- cgit v1.2.3 From 0c77f5abeadcbb89643740889cc865ba0ae66538 Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Fri, 6 Jul 2007 13:57:31 +0300 Subject: nouveau: Add bitfield names for NSOURCE and NSTATUS. Name strings and pretty-printing in nouveau_graph_dump_trap_info(). --- shared-core/nouveau_irq.c | 71 ++++++++++++++++++++++++++++++++++++++++++++--- shared-core/nouveau_reg.h | 23 +++++++++++++++ 2 files changed, 90 insertions(+), 4 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index ffc4bac6..f7baf89e 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -246,6 +246,61 @@ static void nouveau_nv04_context_switch(struct drm_device *dev) } #endif + +struct nouveau_bitfield_names +{ + uint32_t mask; + const char * name; +}; + +static struct nouveau_bitfield_names nouveau_nstatus_names[] = +{ + { NV03_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" }, + { NV03_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" }, + { NV03_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" }, + { NV03_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" } +}; + +static struct nouveau_bitfield_names nouveau_nsource_names[] = +{ + { NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" }, + { NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" }, + { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" }, + { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" }, + { NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" }, + { NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" }, + { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" }, + { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" }, + { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" }, + { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" }, + { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" }, + { NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" }, + { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" }, + { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" }, + { NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" }, + { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" }, + { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" }, + { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" }, + { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" }, +}; + +static void +nouveau_print_bitfield_names(uint32_t value, + const struct nouveau_bitfield_names *namelist, + const int namelist_len) +{ + int i; + for(i=0; i> 20) & 0x1F; subc = (address >> 16) & 0x7; method = address & 0x1FFC; data = NV_READ(0x400708); + nsource = NV_READ(NV03_PGRAPH_NSOURCE); + nstatus = NV_READ(NV03_PGRAPH_NSTATUS); if (dev_priv->card_type < NV_50) { class = NV_READ(0x400160 + subc*4) & 0xFFFF; } else { class = NV_READ(0x400814); } - DRM_ERROR("NV: nSource: 0x%08x, nStatus: 0x%08x\n", - NV_READ(NV03_PGRAPH_NSOURCE), - NV_READ(NV03_PGRAPH_NSTATUS)); - DRM_ERROR("NV: Channel %d/%d (class 0x%04x) -" + DRM_ERROR("nSource:"); + nouveau_print_bitfield_names(nsource, nouveau_nsource_names, + ARRAY_SIZE(nouveau_nsource_names)); + printk(", nStatus:"); + nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names, + ARRAY_SIZE(nouveau_nstatus_names)); + printk("\n"); + + DRM_ERROR("NV: Channel %d/%d (class 0x%04x) - " "Method 0x%04x, Data 0x%08x\n", channel, subc, class, method, data ); diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index bcdb1a9f..47d54b2a 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -111,7 +111,30 @@ #define NV10_PGRAPH_DEBUG_4 0x00400090 #define NV03_PGRAPH_INTR 0x00400100 #define NV03_PGRAPH_NSTATUS 0x00400104 +# define NV03_PGRAPH_NSTATUS_STATE_IN_USE (1<<23) +# define NV03_PGRAPH_NSTATUS_INVALID_STATE (1<<24) +# define NV03_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<25) +# define NV03_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<26) #define NV03_PGRAPH_NSOURCE 0x00400108 +# define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<< 0) +# define NV03_PGRAPH_NSOURCE_DATA_ERROR (1<< 1) +# define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR (1<< 2) +# define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION (1<< 3) +# define NV03_PGRAPH_NSOURCE_LIMIT_COLOR (1<< 4) +# define NV03_PGRAPH_NSOURCE_LIMIT_ZETA (1<< 5) +# define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD (1<< 6) +# define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION (1<< 7) +# define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION (1<< 8) +# define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION (1<< 9) +# define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION (1<<10) +# define NV03_PGRAPH_NSOURCE_STATE_INVALID (1<<11) +# define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY (1<<12) +# define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE (1<<13) +# define NV03_PGRAPH_NSOURCE_METHOD_CNT (1<<14) +# define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION (1<<15) +# define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION (1<<16) +# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A (1<<17) +# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B (1<<18) #define NV03_PGRAPH_INTR_EN 0x00400140 #define NV40_PGRAPH_INTR_EN 0x0040013C # define NV_PGRAPH_INTR_NOTIFY (1<< 0) -- cgit v1.2.3 From 696bee093f6f75dbb48699ff32bbebe2d3a1e307 Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Fri, 6 Jul 2007 19:34:15 +0300 Subject: nouveau: Add read() method to Engine.timer. This is not called from anywhere, yet. --- shared-core/nouveau_drv.h | 2 ++ shared-core/nouveau_state.c | 8 ++++++++ shared-core/nv04_timer.c | 21 +++++++++++++++++++++ 3 files changed, 31 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index f68304c9..9e11f9b7 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -157,6 +157,7 @@ struct nouveau_engine_func { struct { int (*init)(struct drm_device *dev); + uint64_t (*read)(struct drm_device *dev); void (*takedown)(struct drm_device *dev); } timer; @@ -469,6 +470,7 @@ extern void nv50_mc_takedown(struct drm_device *dev); /* nv04_timer.c */ extern int nv04_timer_init(struct drm_device *dev); +extern uint64_t nv04_timer_read(struct drm_device *dev); extern void nv04_timer_takedown(struct drm_device *dev); extern long nouveau_compat_ioctl(struct file *filp, unsigned int cmd, diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 4e3b39dd..5b67aea1 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -88,6 +88,8 @@ static int nouveau_init_card_mappings(struct drm_device *dev) static int nouveau_stub_init(struct drm_device *dev) { return 0; } static void nouveau_stub_takedown(struct drm_device *dev) {} +static uint64_t nouveau_stub_timer_read(struct drm_device *dev) { return 0; } + static int nouveau_init_engine_ptrs(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -104,6 +106,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) engine->mc.init = nv04_mc_init; engine->mc.takedown = nv04_mc_takedown; engine->timer.init = nv04_timer_init; + engine->timer.read = nv04_timer_read; engine->timer.takedown = nv04_timer_takedown; engine->fb.init = nv04_fb_init; engine->fb.takedown = nv04_fb_takedown; @@ -130,6 +133,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) engine->mc.init = nv04_mc_init; engine->mc.takedown = nv04_mc_takedown; engine->timer.init = nv04_timer_init; + engine->timer.read = nv04_timer_read; engine->timer.takedown = nv04_timer_takedown; engine->fb.init = nv10_fb_init; engine->fb.takedown = nv10_fb_takedown; @@ -156,6 +160,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) engine->mc.init = nv04_mc_init; engine->mc.takedown = nv04_mc_takedown; engine->timer.init = nv04_timer_init; + engine->timer.read = nv04_timer_read; engine->timer.takedown = nv04_timer_takedown; engine->fb.init = nv10_fb_init; engine->fb.takedown = nv10_fb_takedown; @@ -182,6 +187,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) engine->mc.init = nv04_mc_init; engine->mc.takedown = nv04_mc_takedown; engine->timer.init = nv04_timer_init; + engine->timer.read = nv04_timer_read; engine->timer.takedown = nv04_timer_takedown; engine->fb.init = nv10_fb_init; engine->fb.takedown = nv10_fb_takedown; @@ -208,6 +214,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) engine->mc.init = nv40_mc_init; engine->mc.takedown = nv40_mc_takedown; engine->timer.init = nv04_timer_init; + engine->timer.read = nv04_timer_read; engine->timer.takedown = nv04_timer_takedown; engine->fb.init = nv40_fb_init; engine->fb.takedown = nv40_fb_takedown; @@ -235,6 +242,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) engine->mc.init = nv50_mc_init; engine->mc.takedown = nv50_mc_takedown; engine->timer.init = nouveau_stub_init; + engine->timer.read = nouveau_stub_timer_read; engine->timer.takedown = nouveau_stub_takedown; engine->fb.init = nouveau_stub_init; engine->fb.takedown = nouveau_stub_takedown; diff --git a/shared-core/nv04_timer.c b/shared-core/nv04_timer.c index efe78da7..08a27f4f 100644 --- a/shared-core/nv04_timer.c +++ b/shared-core/nv04_timer.c @@ -17,6 +17,27 @@ nv04_timer_init(struct drm_device *dev) return 0; } +uint64_t +nv04_timer_read(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + uint32_t low; + /* From kmmio dumps on nv28 this looks like how the blob does this. + * It reads the high dword twice, before and after. + * The only explanation seems to be that the 64-bit timer counter + * advances between high and low dword reads and may corrupt the + * result. Not confirmed. + */ + uint32_t high2 = NV_READ(NV04_PTIMER_TIME_1); + uint32_t high1; + do { + high1 = high2; + low = NV_READ(NV04_PTIMER_TIME_0); + high2 = NV_READ(NV04_PTIMER_TIME_1); + } while(high1 != high2); + return (((uint64_t)high2) << 32) | (uint64_t)low; +} + void nv04_timer_takedown(struct drm_device *dev) { -- cgit v1.2.3 From af4cfa624a005f7105db89f6f076c41adbe44bd3 Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Fri, 6 Jul 2007 20:33:32 +0300 Subject: nouveau: Make nouveau_wait_for_idle() read PTIMER. Following my nv28 kmmio dumps, nouveau_wait_for_idle() is modified to read PTIMER and NV03_PMC_ENABLE. Also a timeout based on PTIMER value is added, so wait_for_idle() cannot stall indefinitely (unless PTIMER is halted). The timeout was selected as 1 giga-ticks, which for me is 1s. --- shared-core/nouveau_state.c | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 5b67aea1..a26ecea3 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -522,16 +522,31 @@ int nouveau_ioctl_setparam(DRM_IOCTL_ARGS) void nouveau_wait_for_idle(struct drm_device *dev) { struct drm_nouveau_private *dev_priv=dev->dev_private; - switch(dev_priv->card_type) - { - case NV_03: - while(NV_READ(NV03_PGRAPH_STATUS)); - break; - case NV_50: - break; - default: - while(NV_READ(NV04_PGRAPH_STATUS)); - break; + switch(dev_priv->card_type) { + case NV_03: + while (NV_READ(NV03_PGRAPH_STATUS)); + break; + case NV_50: + break; + default: { + /* This stuff is more or less a copy of what is seen + * in nv28 kmmio dump. + */ + uint64_t started = dev_priv->Engine.timer.read(dev); + uint64_t stopped = started; + uint32_t status; + do { + uint32_t pmc_e = NV_READ(NV03_PMC_ENABLE); + status = NV_READ(NV04_PGRAPH_STATUS); + if (!status) + break; + stopped = dev_priv->Engine.timer.read(dev); + /* It'll never wrap anyway... */ + } while (stopped - started < 1000000000ULL); + if (status) + DRM_ERROR("timed out with status 0x%08x\n", + status); + } } } -- cgit v1.2.3 From 33a50412c21229610dbb75dee83f145e2f1ec128 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 18 Jul 2007 14:22:40 -0700 Subject: Add dry-coded DRM drawable private information storage for FreeBSD. With this, all modules build again. --- shared-core/i915_drv.h | 4 +-- shared-core/i915_irq.c | 70 ++++++++++++++++++++++++-------------------------- 2 files changed, 35 insertions(+), 39 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 60b32b0d..e9447f2b 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -118,7 +118,7 @@ typedef struct drm_i915_private { struct mem_block *agp_heap; unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; int vblank_pipe; - spinlock_t user_irq_lock; + DRM_SPINTYPE user_irq_lock; int user_irq_refcount; int fence_irq_on; uint32_t irq_enable_reg; @@ -133,7 +133,7 @@ typedef struct drm_i915_private { #ifdef I915_HAVE_BUFFER void *agp_iomap; #endif - spinlock_t swaps_lock; + DRM_SPINTYPE swaps_lock; drm_i915_vbl_swap_t vbl_swaps; unsigned int swaps_pending; } drm_i915_private_t; diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c index 2f6a6b95..40724fae 100644 --- a/shared-core/i915_irq.c +++ b/shared-core/i915_irq.c @@ -50,6 +50,8 @@ i915_dispatch_vsync_flip(drm_device_t *dev, drm_drawable_info_t *drw, int pipe) u16 x1, y1, x2, y2; int pf_pipes = 1 << pipe; + DRM_SPINLOCK_ASSERT(&dev->drw_lock); + /* If the window is visible on the other pipe, we have to flip on that * pipe as well. */ @@ -89,7 +91,6 @@ i915_dispatch_vsync_flip(drm_device_t *dev, drm_drawable_info_t *drw, int pipe) static void i915_vblank_tasklet(drm_device_t *dev) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - unsigned long irqflags; struct list_head *list, *tmp, hits, *hit; int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages; unsigned counter[2] = { atomic_read(&dev->vbl_received), @@ -111,7 +112,12 @@ static void i915_vblank_tasklet(drm_device_t *dev) nhits = nrects = 0; - spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); + /* No irqsave/restore necessary. This tasklet may be run in an + * interrupt context or normal context, but we don't have to worry + * about getting interrupted by something acquiring the lock, because + * we are the interrupt context thing that acquires the lock. + */ + DRM_SPINLOCK(&dev_priv->swaps_lock); /* Find buffer swaps scheduled for this vertical blank */ list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) { @@ -124,15 +130,15 @@ static void i915_vblank_tasklet(drm_device_t *dev) list_del(list); dev_priv->swaps_pending--; - spin_unlock(&dev_priv->swaps_lock); - spin_lock(&dev->drw_lock); + DRM_SPINUNLOCK(&dev_priv->swaps_lock); + DRM_SPINLOCK(&dev->drw_lock); drw = drm_get_drawable_info(dev, vbl_swap->drw_id); if (!drw) { - spin_unlock(&dev->drw_lock); + DRM_SPINUNLOCK(&dev->drw_lock); drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER); - spin_lock(&dev_priv->swaps_lock); + DRM_SPINLOCK(&dev_priv->swaps_lock); continue; } @@ -149,7 +155,7 @@ static void i915_vblank_tasklet(drm_device_t *dev) } } - spin_unlock(&dev->drw_lock); + DRM_SPINUNLOCK(&dev->drw_lock); /* List of hits was empty, or we reached the end of it */ if (hit == &hits) @@ -157,16 +163,15 @@ static void i915_vblank_tasklet(drm_device_t *dev) nhits++; - spin_lock(&dev_priv->swaps_lock); + DRM_SPINLOCK(&dev_priv->swaps_lock); } + DRM_SPINUNLOCK(&dev->drw_lock); + if (nhits == 0) { - spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); return; } - spin_unlock(&dev_priv->swaps_lock); - i915_kernel_lost_context(dev); upper[0] = upper[1] = 0; @@ -180,7 +185,7 @@ static void i915_vblank_tasklet(drm_device_t *dev) offsets[2] = sarea_priv->third_offset; num_pages = sarea_priv->third_handle ? 3 : 2; - spin_lock(&dev->drw_lock); + DRM_SPINLOCK(&dev->drw_lock); /* Emit blits for buffer swaps, partitioning both outputs into as many * slices as there are buffer swaps scheduled in order to avoid tearing @@ -262,7 +267,7 @@ static void i915_vblank_tasklet(drm_device_t *dev) } } - spin_unlock_irqrestore(&dev->drw_lock, irqflags); + DRM_SPINUNLOCK(&dev->drw_lock); list_for_each_safe(hit, tmp, &hits) { drm_i915_vbl_swap_t *swap_hit = @@ -362,23 +367,23 @@ int i915_emit_irq(drm_device_t * dev) void i915_user_irq_on(drm_i915_private_t *dev_priv) { - spin_lock(&dev_priv->user_irq_lock); + DRM_SPINLOCK(&dev_priv->user_irq_lock); if (dev_priv->irq_enabled && (++dev_priv->user_irq_refcount == 1)){ dev_priv->irq_enable_reg |= USER_INT_FLAG; I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg); } - spin_unlock(&dev_priv->user_irq_lock); + DRM_SPINUNLOCK(&dev_priv->user_irq_lock); } void i915_user_irq_off(drm_i915_private_t *dev_priv) { - spin_lock(&dev_priv->user_irq_lock); + DRM_SPINLOCK(&dev_priv->user_irq_lock); if (dev_priv->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { // dev_priv->irq_enable_reg &= ~USER_INT_FLAG; // I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg); } - spin_unlock(&dev_priv->user_irq_lock); + DRM_SPINUNLOCK(&dev_priv->user_irq_lock); } @@ -597,16 +602,6 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) return DRM_ERR(EINVAL); } - spin_lock_irqsave(&dev->drw_lock, irqflags); - - if (!drm_get_drawable_info(dev, swap.drawable)) { - spin_unlock_irqrestore(&dev->drw_lock, irqflags); - DRM_DEBUG("Invalid drawable ID %d\n", swap.drawable); - return DRM_ERR(EINVAL); - } - - spin_unlock_irqrestore(&dev->drw_lock, irqflags); - curseq = atomic_read(pipe ? &dev->vbl_received2 : &dev->vbl_received); if (seqtype == _DRM_VBLANK_RELATIVE) @@ -629,12 +624,13 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) LOCK_TEST_WITH_RETURN(dev, filp); - spin_lock_irqsave(&dev->drw_lock, irqflags); + DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags); drw = drm_get_drawable_info(dev, swap.drawable); if (!drw) { - spin_unlock_irqrestore(&dev->drw_lock, irqflags); + DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, + irqflags); DRM_DEBUG("Invalid drawable ID %d\n", swap.drawable); return DRM_ERR(EINVAL); @@ -642,13 +638,13 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) i915_dispatch_vsync_flip(dev, drw, pipe); - spin_unlock_irqrestore(&dev->drw_lock, irqflags); + DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags); return 0; } } - spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); + DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags); list_for_each(list, &dev_priv->vbl_swaps.head) { vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head); @@ -657,13 +653,13 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) vbl_swap->pipe == pipe && vbl_swap->sequence == swap.sequence) { vbl_swap->flip = (swap.seqtype & _DRM_VBLANK_FLIP); - spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); + DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags); DRM_DEBUG("Already scheduled\n"); return 0; } } - spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); + DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags); if (dev_priv->swaps_pending >= 100) { DRM_DEBUG("Too many swaps queued\n"); @@ -687,12 +683,12 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) if (vbl_swap->flip) swap.sequence++; - spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); + DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags); list_add_tail((struct list_head *)vbl_swap, &dev_priv->vbl_swaps.head); dev_priv->swaps_pending++; - spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); + DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags); DRM_COPY_TO_USER_IOCTL((drm_i915_vblank_swap_t __user *) data, swap, sizeof(swap)); @@ -715,11 +711,11 @@ void i915_driver_irq_postinstall(drm_device_t * dev) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - spin_lock_init(&dev_priv->swaps_lock); + DRM_SPININIT(&dev_priv->swaps_lock, "swap"); INIT_LIST_HEAD(&dev_priv->vbl_swaps.head); dev_priv->swaps_pending = 0; - spin_lock_init(&dev_priv->user_irq_lock); + DRM_SPININIT(&dev_priv->user_irq_lock, "userirq"); dev_priv->user_irq_refcount = 0; i915_enable_interrupt(dev); -- cgit v1.2.3 From 0c95d489abd19efd2ba017e78a4b28cea0854e77 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 19 Jul 2007 16:42:58 +1000 Subject: nouveau/nv50: get non-default push buffer sizes working. --- shared-core/nv50_fifo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index feab24c4..4933bbf3 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -263,7 +263,7 @@ nv50_fifo_create_context(struct drm_device *dev, int channel) INSTANCE_WR(ramfc, 0x54/4, 0x000f0000); INSTANCE_WR(ramfc, 0x7c/4, 0x30000001); INSTANCE_WR(ramfc, 0x78/4, 0x00000000); - INSTANCE_WR(ramfc, 0x4c/4, 0x00007fff); + INSTANCE_WR(ramfc, 0x4c/4, chan->pushbuf_mem->size - 1); if (!IS_G80) { INSTANCE_WR(chan->ramin->gpuobj, 0, channel); -- cgit v1.2.3 From f4e1c1d05cfbd43ac429ab6dc78345ffa3599b7a Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 19 Jul 2007 06:46:13 -0700 Subject: FreeBSD warnings cleanup. --- shared-core/radeon_irq.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/radeon_irq.c b/shared-core/radeon_irq.c index ad8a0ac7..b973b968 100644 --- a/shared-core/radeon_irq.c +++ b/shared-core/radeon_irq.c @@ -144,8 +144,9 @@ static int radeon_wait_irq(struct drm_device * dev, int swi_nr) return ret; } -int radeon_driver_vblank_do_wait(struct drm_device * dev, unsigned int *sequence, - int crtc) +static int radeon_driver_vblank_do_wait(struct drm_device * dev, + unsigned int *sequence, + int crtc) { drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; -- cgit v1.2.3 From 5ba94c2ab8be350fee495e5cfe94afb8f663956a Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Thu, 19 Jul 2007 10:29:18 -0700 Subject: Initial pass at converting driver to DRM infrastructure. --- shared-core/xgi_drm.h | 72 ++++++++++++++++++++++++++------------------------- 1 file changed, 37 insertions(+), 35 deletions(-) (limited to 'shared-core') diff --git a/shared-core/xgi_drm.h b/shared-core/xgi_drm.h index 67118884..66cb4efb 100644 --- a/shared-core/xgi_drm.h +++ b/shared-core/xgi_drm.h @@ -44,6 +44,15 @@ struct drm_xgi_sarea { unsigned int scrn_pitch; }; + +struct xgi_bootstrap { + /** + * Size of PCI-e GART range in megabytes. + */ + unsigned int gart_size; +}; + + enum xgi_mem_location { XGI_MEMLOC_NON_LOCAL = 0, XGI_MEMLOC_LOCAL = 1, @@ -62,9 +71,9 @@ struct xgi_mem_alloc { __u32 hw_addr; /** - * Physical address of the memory from the processor's point of view. + * Offset of the allocation in the mapping. */ - unsigned long bus_addr; + unsigned long offset; }; enum xgi_batch_type { @@ -95,38 +104,31 @@ struct xgi_state_info { * Ioctl definitions */ -#define XGI_IOCTL_MAGIC 'x' /* use 'x' as magic number */ - -#define XGI_IOCTL_BASE 0 -#define XGI_ESC_POST_VBIOS (XGI_IOCTL_BASE + 0) - -#define XGI_ESC_FB_ALLOC (XGI_IOCTL_BASE + 1) -#define XGI_ESC_FB_FREE (XGI_IOCTL_BASE + 2) -#define XGI_ESC_PCIE_ALLOC (XGI_IOCTL_BASE + 3) -#define XGI_ESC_PCIE_FREE (XGI_IOCTL_BASE + 4) -#define XGI_ESC_SUBMIT_CMDLIST (XGI_IOCTL_BASE + 5) -#define XGI_ESC_GE_RESET (XGI_IOCTL_BASE + 6) -#define XGI_ESC_DUMP_REGISTER (XGI_IOCTL_BASE + 7) -#define XGI_ESC_DEBUG_INFO (XGI_IOCTL_BASE + 8) -#define XGI_ESC_TEST_RWINKERNEL (XGI_IOCTL_BASE + 9) -#define XGI_ESC_STATE_CHANGE (XGI_IOCTL_BASE + 10) - -#define XGI_IOCTL_POST_VBIOS _IO(XGI_IOCTL_MAGIC, XGI_ESC_POST_VBIOS) - -#define XGI_IOCTL_FB_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_FB_ALLOC, struct xgi_mem_alloc) -#define XGI_IOCTL_FB_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_FB_FREE, unsigned long) - -#define XGI_IOCTL_PCIE_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_ALLOC, struct xgi_mem_alloc) -#define XGI_IOCTL_PCIE_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_FREE, unsigned long) - -#define XGI_IOCTL_GE_RESET _IO(XGI_IOCTL_MAGIC, XGI_ESC_GE_RESET) -#define XGI_IOCTL_DUMP_REGISTER _IO(XGI_IOCTL_MAGIC, XGI_ESC_DUMP_REGISTER) -#define XGI_IOCTL_DEBUG_INFO _IO(XGI_IOCTL_MAGIC, XGI_ESC_DEBUG_INFO) - -#define XGI_IOCTL_SUBMIT_CMDLIST _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_SUBMIT_CMDLIST, struct xgi_cmd_info) -#define XGI_IOCTL_TEST_RWINKERNEL _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_TEST_RWINKERNEL, unsigned long) -#define XGI_IOCTL_STATE_CHANGE _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_STATE_CHANGE, struct xgi_state_info) - -#define XGI_IOCTL_MAXNR 30 +#define DRM_XGI_BOOTSTRAP 0 +#define DRM_XGI_FB_ALLOC 1 +#define DRM_XGI_FB_FREE 2 +#define DRM_XGI_PCIE_ALLOC 3 +#define DRM_XGI_PCIE_FREE 4 +#define DRM_XGI_SUBMIT_CMDLIST 5 +#define DRM_XGI_GE_RESET 6 +#define DRM_XGI_DUMP_REGISTER 7 +#define DRM_XGI_DEBUG_INFO 8 +#define DRM_XGI_TEST_RWINKERNEL 9 +#define DRM_XGI_STATE_CHANGE 10 + +#define XGI_IOCTL_BOOTSTRAP DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_BOOTSTRAP, struct xgi_bootstrap) + +#define XGI_IOCTL_FB_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_XGI_FB_ALLOC, struct xgi_mem_alloc) +#define XGI_IOCTL_FB_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_FB_FREE, __u32) + +#define XGI_IOCTL_PCIE_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_XGI_PCIE_ALLOC, struct xgi_mem_alloc) +#define XGI_IOCTL_PCIE_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_PCIE_FREE, __u32) + +#define XGI_IOCTL_GE_RESET DRM_IO(DRM_COMMAND_BASE + DRM_XGI_GE_RESET) +#define XGI_IOCTL_DUMP_REGISTER DRM_IO(DRM_COMMAND_BASE + DRM_XGI_DUMP_REGISTER) +#define XGI_IOCTL_DEBUG_INFO DRM_IO(DRM_COMMAND_BASE + DRM_XGI_DEBUG_INFO) +#define XGI_IOCTL_SUBMIT_CMDLIST DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_SUBMIT_CMDLIST, struct xgi_cmd_info) +#define XGI_IOCTL_TEST_RWINKERNEL DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_TEST_RWINKERNEL, __u32) +#define XGI_IOCTL_STATE_CHANGE DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_STATE_CHANGE, struct xgi_state_info) #endif /* _XGI_DRM_H_ */ -- cgit v1.2.3 From e39286eb5eab8846a228863abf8f1b8b07a9e29d Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 19 Jul 2007 17:00:17 -0700 Subject: Remove DRM_ERR OS macro. This was used to make all ioctl handlers return -errno on linux and errno on *BSD. Instead, just return -errno in shared code, and flip sign on return from shared code to *BSD code. --- shared-core/i915_dma.c | 72 ++++++++--------- shared-core/i915_irq.c | 32 ++++---- shared-core/i915_mem.c | 28 +++---- shared-core/mach64_dma.c | 50 ++++++------ shared-core/mach64_drv.h | 18 ++--- shared-core/mach64_state.c | 36 ++++----- shared-core/mga_dma.c | 42 +++++----- shared-core/mga_drv.h | 4 +- shared-core/mga_state.c | 36 ++++----- shared-core/mga_warp.c | 8 +- shared-core/nouveau_fifo.c | 10 +-- shared-core/nouveau_mem.c | 18 ++--- shared-core/nouveau_notifier.c | 10 +-- shared-core/nouveau_object.c | 58 +++++++------- shared-core/nouveau_state.c | 12 +-- shared-core/nv04_instmem.c | 6 +- shared-core/nv20_graph.c | 4 +- shared-core/nv30_graph.c | 6 +- shared-core/nv40_graph.c | 6 +- shared-core/nv50_fifo.c | 6 +- shared-core/nv50_graph.c | 2 +- shared-core/nv50_instmem.c | 16 ++-- shared-core/r128_cce.c | 54 ++++++------- shared-core/r128_drv.h | 2 +- shared-core/r128_state.c | 100 ++++++++++++------------ shared-core/r300_cmdbuf.c | 60 +++++++------- shared-core/radeon_cp.c | 50 ++++++------ shared-core/radeon_irq.c | 12 +-- shared-core/radeon_mem.c | 26 +++---- shared-core/radeon_state.c | 172 ++++++++++++++++++++--------------------- shared-core/savage_bci.c | 60 +++++++------- shared-core/savage_state.c | 96 +++++++++++------------ shared-core/sis_mm.c | 28 +++---- shared-core/via_dma.c | 44 +++++------ shared-core/via_irq.c | 14 ++-- shared-core/via_map.c | 2 +- shared-core/via_verifier.c | 8 +- 37 files changed, 604 insertions(+), 604 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 5fb9fcff..81e6981d 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -71,7 +71,7 @@ int i915_wait_ring(struct drm_device * dev, int n, const char *caller) DRM_UDELAY(1); } - return DRM_ERR(EBUSY); + return -EBUSY; } void i915_kernel_lost_context(struct drm_device * dev) @@ -136,7 +136,7 @@ static int i915_initialize(struct drm_device * dev, DRM_ERROR("can not find sarea!\n"); dev->dev_private = (void *)dev_priv; i915_dma_cleanup(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); @@ -144,7 +144,7 @@ static int i915_initialize(struct drm_device * dev, dev->dev_private = (void *)dev_priv; i915_dma_cleanup(dev); DRM_ERROR("can not find mmio map!\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->sarea_priv = (drm_i915_sarea_t *) @@ -168,7 +168,7 @@ static int i915_initialize(struct drm_device * dev, i915_dma_cleanup(dev); DRM_ERROR("can not ioremap virtual address for" " ring buffer\n"); - return DRM_ERR(ENOMEM); + return -ENOMEM; } dev_priv->ring.virtual_start = dev_priv->ring.map.handle; @@ -198,7 +198,7 @@ static int i915_initialize(struct drm_device * dev, dev->dev_private = (void *)dev_priv; i915_dma_cleanup(dev); DRM_ERROR("Can not allocate hardware status page\n"); - return DRM_ERR(ENOMEM); + return -ENOMEM; } dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr; dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; @@ -220,24 +220,24 @@ static int i915_dma_resume(struct drm_device * dev) if (!dev_priv->sarea) { DRM_ERROR("can not find sarea!\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } if (!dev_priv->mmio_map) { DRM_ERROR("can not find mmio map!\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } if (dev_priv->ring.map.handle == NULL) { DRM_ERROR("can not ioremap virtual address for" " ring buffer\n"); - return DRM_ERR(ENOMEM); + return -ENOMEM; } /* Program Hardware Status Page */ if (!dev_priv->hw_status_page) { DRM_ERROR("Can not find hardware status page\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); @@ -265,7 +265,7 @@ static int i915_dma_init(DRM_IOCTL_ARGS) dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER); if (dev_priv == NULL) - return DRM_ERR(ENOMEM); + return -ENOMEM; retcode = i915_initialize(dev, dev_priv, &init); break; case I915_CLEANUP_DMA: @@ -275,7 +275,7 @@ static int i915_dma_init(DRM_IOCTL_ARGS) retcode = i915_dma_resume(dev); break; default: - retcode = DRM_ERR(EINVAL); + retcode = -EINVAL; break; } @@ -365,7 +365,7 @@ static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwor RING_LOCALS; if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) - return DRM_ERR(EINVAL); + return -EINVAL; BEGIN_LP_RING((dwords+1)&~1); @@ -373,17 +373,17 @@ static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwor int cmd, sz; if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) - return DRM_ERR(EINVAL); + return -EINVAL; if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) - return DRM_ERR(EINVAL); + return -EINVAL; OUT_RING(cmd); while (++i, --sz) { if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) { - return DRM_ERR(EINVAL); + return -EINVAL; } OUT_RING(cmd); } @@ -406,13 +406,13 @@ static int i915_emit_box(struct drm_device * dev, RING_LOCALS; if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) { - return DRM_ERR(EFAULT); + return -EFAULT; } if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { DRM_ERROR("Bad box %d,%d..%d,%d\n", box.x1, box.y1, box.x2, box.y2); - return DRM_ERR(EINVAL); + return -EINVAL; } if (IS_I965G(dev)) { @@ -493,7 +493,7 @@ static int i915_dispatch_cmdbuffer(struct drm_device * dev, if (cmd->sz & 0x3) { DRM_ERROR("alignment"); - return DRM_ERR(EINVAL); + return -EINVAL; } i915_kernel_lost_context(dev); @@ -531,7 +531,7 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev, if ((batch->start | batch->used) & 0x7) { DRM_ERROR("alignment"); - return DRM_ERR(EINVAL); + return -EINVAL; } i915_kernel_lost_context(dev); @@ -670,7 +670,7 @@ static int i915_batchbuffer(DRM_IOCTL_ARGS) if (!dev_priv->allow_batchbuffer) { DRM_ERROR("Batchbuffer ioctl disabled\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data, @@ -684,7 +684,7 @@ static int i915_batchbuffer(DRM_IOCTL_ARGS) if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects, batch.num_cliprects * sizeof(struct drm_clip_rect))) - return DRM_ERR(EFAULT); + return -EFAULT; ret = i915_dispatch_batchbuffer(dev, &batch); @@ -714,7 +714,7 @@ static int i915_cmdbuffer(DRM_IOCTL_ARGS) cmdbuf.num_cliprects * sizeof(struct drm_clip_rect))) { DRM_ERROR("Fault accessing cliprects\n"); - return DRM_ERR(EFAULT); + return -EFAULT; } ret = i915_dispatch_cmdbuffer(dev, &cmdbuf); @@ -764,7 +764,7 @@ static int i915_flip_bufs(DRM_IOCTL_ARGS) if (param.pipes & ~0x3) { DRM_ERROR("Invalid pipes 0x%x, only <= 0x3 is valid\n", param.pipes); - return DRM_ERR(EINVAL); + return -EINVAL; } i915_dispatch_flip(dev, param.pipes, 0); @@ -782,7 +782,7 @@ static int i915_getparam(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data, @@ -800,12 +800,12 @@ static int i915_getparam(DRM_IOCTL_ARGS) break; default: DRM_ERROR("Unknown parameter %d\n", param.param); - return DRM_ERR(EINVAL); + return -EINVAL; } if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { DRM_ERROR("DRM_COPY_TO_USER failed\n"); - return DRM_ERR(EFAULT); + return -EFAULT; } return 0; @@ -819,7 +819,7 @@ static int i915_setparam(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data, @@ -837,7 +837,7 @@ static int i915_setparam(DRM_IOCTL_ARGS) break; default: DRM_ERROR("unknown parameter %d\n", param.param); - return DRM_ERR(EINVAL); + return -EINVAL; } return 0; @@ -865,13 +865,13 @@ static int i915_mmio(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(mmio, (drm_i915_mmio_t __user *) data, sizeof(mmio)); if (mmio.reg >= mmio_table_size) - return DRM_ERR(EINVAL); + return -EINVAL; e = &mmio_table[mmio.reg]; base = (u8 *) dev_priv->mmio_map->handle + e->offset; @@ -879,21 +879,21 @@ static int i915_mmio(DRM_IOCTL_ARGS) switch (mmio.read_write) { case I915_MMIO_READ: if (!(e->flag & I915_MMIO_MAY_READ)) - return DRM_ERR(EINVAL); + return -EINVAL; for (i = 0; i < e->size / 4; i++) buf[i] = I915_READ(e->offset + i * 4); if (DRM_COPY_TO_USER(mmio.data, buf, e->size)) { DRM_ERROR("DRM_COPY_TO_USER failed\n"); - return DRM_ERR(EFAULT); + return -EFAULT; } break; case I915_MMIO_WRITE: if (!(e->flag & I915_MMIO_MAY_WRITE)) - return DRM_ERR(EINVAL); + return -EINVAL; if(DRM_COPY_FROM_USER(buf, mmio.data, e->size)) { DRM_ERROR("DRM_COPY_TO_USER failed\n"); - return DRM_ERR(EFAULT); + return -EFAULT; } for (i = 0; i < e->size / 4; i++) I915_WRITE(e->offset + i * 4, buf[i]); @@ -910,7 +910,7 @@ static int i915_set_status_page(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(hws, (drm_i915_hws_addr_t __user *) data, sizeof(hws)); @@ -931,7 +931,7 @@ static int i915_set_status_page(DRM_IOCTL_ARGS) dev_priv->status_gfx_addr = 0; DRM_ERROR("can not ioremap virtual address for" " G33 hw status page\n"); - return DRM_ERR(ENOMEM); + return -ENOMEM; } dev_priv->hw_status_page = dev_priv->hws_map.handle; diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c index 698ecced..f4775b75 100644 --- a/shared-core/i915_irq.c +++ b/shared-core/i915_irq.c @@ -406,7 +406,7 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr) READ_BREADCRUMB(dev_priv) >= irq_nr); i915_user_irq_off(dev_priv); - if (ret == DRM_ERR(EBUSY)) { + if (ret == -EBUSY) { DRM_ERROR("%s: EBUSY -- rec: %d emitted: %d\n", __FUNCTION__, READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); @@ -425,7 +425,7 @@ static int i915_driver_vblank_do_wait(struct drm_device *dev, unsigned int *sequ if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ, @@ -460,7 +460,7 @@ int i915_irq_emit(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(emit, (drm_i915_irq_emit_t __user *) data, @@ -470,7 +470,7 @@ int i915_irq_emit(DRM_IOCTL_ARGS) if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) { DRM_ERROR("copy_to_user\n"); - return DRM_ERR(EFAULT); + return -EFAULT; } return 0; @@ -486,7 +486,7 @@ int i915_irq_wait(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(irqwait, (drm_i915_irq_wait_t __user *) data, @@ -519,7 +519,7 @@ int i915_vblank_pipe_set(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(pipe, (drm_i915_vblank_pipe_t __user *) data, @@ -528,7 +528,7 @@ int i915_vblank_pipe_set(DRM_IOCTL_ARGS) if (pipe.pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) { DRM_ERROR("%s called with invalid pipe 0x%x\n", __FUNCTION__, pipe.pipe); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->vblank_pipe = pipe.pipe; @@ -547,7 +547,7 @@ int i915_vblank_pipe_get(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } flag = I915_READ(I915REG_INT_ENABLE_R); @@ -576,12 +576,12 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __func__); - return DRM_ERR(EINVAL); + return -EINVAL; } if (dev_priv->sarea_priv->rotation) { DRM_DEBUG("Rotation not supported\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(swap, (drm_i915_vblank_swap_t __user *) data, @@ -591,7 +591,7 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS | _DRM_VBLANK_FLIP)) { DRM_ERROR("Invalid sequence type 0x%x\n", swap.seqtype); - return DRM_ERR(EINVAL); + return -EINVAL; } pipe = (swap.seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0; @@ -600,7 +600,7 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) if (!(dev_priv->vblank_pipe & (1 << pipe))) { DRM_ERROR("Invalid pipe %d\n", pipe); - return DRM_ERR(EINVAL); + return -EINVAL; } curseq = atomic_read(pipe ? &dev->vbl_received2 : &dev->vbl_received); @@ -613,7 +613,7 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) swap.sequence = curseq + 1; } else { DRM_DEBUG("Missed target sequence\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } } @@ -634,7 +634,7 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) irqflags); DRM_DEBUG("Invalid drawable ID %d\n", swap.drawable); - return DRM_ERR(EINVAL); + return -EINVAL; } i915_dispatch_vsync_flip(dev, drw, pipe); @@ -664,14 +664,14 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) if (dev_priv->swaps_pending >= 100) { DRM_DEBUG("Too many swaps queued\n"); - return DRM_ERR(EBUSY); + return -EBUSY; } vbl_swap = drm_calloc(1, sizeof(vbl_swap), DRM_MEM_DRIVER); if (!vbl_swap) { DRM_ERROR("Failed to allocate memory to queue swap\n"); - return DRM_ERR(ENOMEM); + return -ENOMEM; } DRM_DEBUG("\n"); diff --git a/shared-core/i915_mem.c b/shared-core/i915_mem.c index 582687ad..381562d8 100644 --- a/shared-core/i915_mem.c +++ b/shared-core/i915_mem.c @@ -276,7 +276,7 @@ int i915_mem_alloc(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(alloc, (drm_i915_mem_alloc_t __user *) data, @@ -284,7 +284,7 @@ int i915_mem_alloc(DRM_IOCTL_ARGS) heap = get_heap(dev_priv, alloc.region); if (!heap || !*heap) - return DRM_ERR(EFAULT); + return -EFAULT; /* Make things easier on ourselves: all allocations at least * 4k aligned. @@ -295,13 +295,13 @@ int i915_mem_alloc(DRM_IOCTL_ARGS) block = alloc_block(*heap, alloc.size, alloc.alignment, filp); if (!block) - return DRM_ERR(ENOMEM); + return -ENOMEM; mark_block(dev, block, 1); if (DRM_COPY_TO_USER(alloc.region_offset, &block->start, sizeof(int))) { DRM_ERROR("copy_to_user\n"); - return DRM_ERR(EFAULT); + return -EFAULT; } return 0; @@ -316,7 +316,7 @@ int i915_mem_free(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(memfree, (drm_i915_mem_free_t __user *) data, @@ -324,14 +324,14 @@ int i915_mem_free(DRM_IOCTL_ARGS) heap = get_heap(dev_priv, memfree.region); if (!heap || !*heap) - return DRM_ERR(EFAULT); + return -EFAULT; block = find_block(*heap, memfree.region_offset); if (!block) - return DRM_ERR(EFAULT); + return -EFAULT; if (block->filp != filp) - return DRM_ERR(EPERM); + return -EPERM; mark_block(dev, block, 0); free_block(block); @@ -347,7 +347,7 @@ int i915_mem_init_heap(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(initheap, @@ -356,11 +356,11 @@ int i915_mem_init_heap(DRM_IOCTL_ARGS) heap = get_heap(dev_priv, initheap.region); if (!heap) - return DRM_ERR(EFAULT); + return -EFAULT; if (*heap) { DRM_ERROR("heap already initialized?"); - return DRM_ERR(EFAULT); + return -EFAULT; } return init_heap(heap, initheap.start, initheap.size); @@ -375,7 +375,7 @@ int i915_mem_destroy_heap( DRM_IOCTL_ARGS ) if ( !dev_priv ) { DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL( destroyheap, (drm_i915_mem_destroy_heap_t *)data, @@ -384,12 +384,12 @@ int i915_mem_destroy_heap( DRM_IOCTL_ARGS ) heap = get_heap( dev_priv, destroyheap.region ); if (!heap) { DRM_ERROR("get_heap failed"); - return DRM_ERR(EFAULT); + return -EFAULT; } if (!*heap) { DRM_ERROR("heap not initialized?"); - return DRM_ERR(EFAULT); + return -EFAULT; } i915_mem_takedown( heap ); diff --git a/shared-core/mach64_dma.c b/shared-core/mach64_dma.c index d833475f..fec73076 100644 --- a/shared-core/mach64_dma.c +++ b/shared-core/mach64_dma.c @@ -70,7 +70,7 @@ int mach64_do_wait_for_fifo(drm_mach64_private_t * dev_priv, int entries) DRM_INFO("%s failed! slots=%d entries=%d\n", __FUNCTION__, slots, entries); - return DRM_ERR(EBUSY); + return -EBUSY; } /** @@ -94,7 +94,7 @@ int mach64_do_wait_for_idle(drm_mach64_private_t * dev_priv) DRM_INFO("%s failed! GUI_STAT=0x%08x\n", __FUNCTION__, MACH64_READ(MACH64_GUI_STAT)); mach64_dump_ring_info(dev_priv); - return DRM_ERR(EBUSY); + return -EBUSY; } /** @@ -135,7 +135,7 @@ int mach64_wait_ring(drm_mach64_private_t * dev_priv, int n) /* FIXME: This is being ignored... */ DRM_ERROR("failed!\n"); mach64_dump_ring_info(dev_priv); - return DRM_ERR(EBUSY); + return -EBUSY; } /** @@ -172,7 +172,7 @@ static int mach64_ring_idle(drm_mach64_private_t * dev_priv) DRM_INFO("%s failed! GUI_STAT=0x%08x\n", __FUNCTION__, MACH64_READ(MACH64_GUI_STAT)); mach64_dump_ring_info(dev_priv); - return DRM_ERR(EBUSY); + return -EBUSY; } /** @@ -592,7 +592,7 @@ static int mach64_bm_dma_test(struct drm_device * dev) drm_pci_alloc(dev, 0x1000, 0x1000, 0xfffffffful); if (!cpu_addr_dmah) { DRM_INFO("data-memory allocation failed!\n"); - return DRM_ERR(ENOMEM); + return -ENOMEM; } else { data = (u32 *) cpu_addr_dmah->vaddr; data_addr = (u32) cpu_addr_dmah->busaddr; @@ -624,7 +624,7 @@ static int mach64_bm_dma_test(struct drm_device * dev) mach64_do_engine_reset(dev_priv); DRM_INFO("freeing data buffer memory.\n"); drm_pci_free(dev, cpu_addr_dmah); - return DRM_ERR(EIO); + return -EIO; } } @@ -762,7 +762,7 @@ static int mach64_do_dma_init(struct drm_device * dev, drm_mach64_init_t * init) dev_priv = drm_alloc(sizeof(drm_mach64_private_t), DRM_MEM_DRIVER); if (dev_priv == NULL) - return DRM_ERR(ENOMEM); + return -ENOMEM; memset(dev_priv, 0, sizeof(drm_mach64_private_t)); @@ -797,21 +797,21 @@ static int mach64_do_dma_init(struct drm_device * dev, drm_mach64_init_t * init) DRM_ERROR("can not find sarea!\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->fb = drm_core_findmap(dev, init->fb_offset); if (!dev_priv->fb) { DRM_ERROR("can not find frame buffer map!\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); if (!dev_priv->mmio) { DRM_ERROR("can not find mmio map!\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->ring_map = drm_core_findmap(dev, init->ring_offset); @@ -819,7 +819,7 @@ static int mach64_do_dma_init(struct drm_device * dev, drm_mach64_init_t * init) DRM_ERROR("can not find ring map!\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->sarea_priv = (drm_mach64_sarea_t *) @@ -832,7 +832,7 @@ static int mach64_do_dma_init(struct drm_device * dev, drm_mach64_init_t * init) " descriptor ring\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); - return DRM_ERR(ENOMEM); + return -ENOMEM; } dev->agp_buffer_token = init->buffers_offset; dev->agp_buffer_map = @@ -841,7 +841,7 @@ static int mach64_do_dma_init(struct drm_device * dev, drm_mach64_init_t * init) DRM_ERROR("can not find dma buffer map!\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } /* there might be a nicer way to do this - dev isn't passed all the way though the mach64 - DA */ @@ -853,7 +853,7 @@ static int mach64_do_dma_init(struct drm_device * dev, drm_mach64_init_t * init) " dma buffer\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); - return DRM_ERR(ENOMEM); + return -ENOMEM; } dev_priv->agp_textures = drm_core_findmap(dev, init->agp_textures_offset); @@ -861,7 +861,7 @@ static int mach64_do_dma_init(struct drm_device * dev, drm_mach64_init_t * init) DRM_ERROR("can not find agp texture region!\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } } @@ -1035,7 +1035,7 @@ int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t * dev_priv) head, ring->tail, buf_addr, (eol ? "eol" : "")); mach64_dump_ring_info(dev_priv); mach64_do_engine_reset(dev_priv); - return DRM_ERR(EINVAL); + return -EINVAL; } /* Hand feed the buffer to the card via MMIO, waiting for the fifo @@ -1177,7 +1177,7 @@ int mach64_dma_init(DRM_IOCTL_ARGS) return mach64_do_cleanup_dma(dev); } - return DRM_ERR(EINVAL); + return -EINVAL; } int mach64_dma_idle(DRM_IOCTL_ARGS) @@ -1239,7 +1239,7 @@ int mach64_init_freelist(struct drm_device * dev) (drm_mach64_freelist_t *) drm_alloc(sizeof(drm_mach64_freelist_t), DRM_MEM_BUFLISTS)) == NULL) - return DRM_ERR(ENOMEM); + return -ENOMEM; memset(entry, 0, sizeof(drm_mach64_freelist_t)); entry->buf = dma->buflist[i]; ptr = &entry->list; @@ -1438,7 +1438,7 @@ int mach64_freelist_put(drm_mach64_private_t * dev_priv, struct drm_buf * copy_b if (copy_buf == entry->buf) { DRM_ERROR("%s: Trying to release a pending buf\n", __FUNCTION__); - return DRM_ERR(EFAULT); + return -EFAULT; } } #endif @@ -1472,20 +1472,20 @@ static int mach64_dma_get_buffers(DRMFILE filp, struct drm_device * dev, buf = mach64_freelist_get(dev_priv); #if MACH64_EXTRA_CHECKING if (!buf) - return DRM_ERR(EFAULT); + return -EFAULT; #else if (!buf) - return DRM_ERR(EAGAIN); + return -EAGAIN; #endif buf->filp = filp; if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, sizeof(buf->idx))) - return DRM_ERR(EFAULT); + return -EFAULT; if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, sizeof(buf->total))) - return DRM_ERR(EFAULT); + return -EFAULT; d->granted_count++; } @@ -1508,7 +1508,7 @@ int mach64_dma_buffers(DRM_IOCTL_ARGS) if (d.send_count != 0) { DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", DRM_CURRENTPID, d.send_count); - return DRM_ERR(EINVAL); + return -EINVAL; } /* We'll send you buffers. @@ -1516,7 +1516,7 @@ int mach64_dma_buffers(DRM_IOCTL_ARGS) if (d.request_count < 0 || d.request_count > dma->buf_count) { DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", DRM_CURRENTPID, d.request_count, dma->buf_count); - ret = DRM_ERR(EINVAL); + ret = -EINVAL; } d.granted_count = 0; diff --git a/shared-core/mach64_drv.h b/shared-core/mach64_drv.h index a1b36751..5d83c861 100644 --- a/shared-core/mach64_drv.h +++ b/shared-core/mach64_drv.h @@ -819,14 +819,14 @@ static __inline__ int mach64_find_pending_buf_entry(drm_mach64_private_t * #if MACH64_EXTRA_CHECKING if (list_empty(&dev_priv->pending)) { DRM_ERROR("Empty pending list in %s\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } #endif ptr = dev_priv->pending.prev; *entry = list_entry(ptr, drm_mach64_freelist_t, list); while ((*entry)->buf != buf) { if (ptr == &dev_priv->pending) { - return DRM_ERR(EFAULT); + return -EFAULT; } ptr = ptr->prev; *entry = list_entry(ptr, drm_mach64_freelist_t, list); @@ -852,12 +852,12 @@ do { \ if (_buf == NULL) { \ DRM_ERROR("%s: couldn't get buffer in DMAGETPTR\n", \ __FUNCTION__ ); \ - return DRM_ERR(EAGAIN); \ + return -EAGAIN; \ } \ if (_buf->pending) { \ DRM_ERROR("%s: pending buf in DMAGETPTR\n", \ __FUNCTION__ ); \ - return DRM_ERR(EFAULT); \ + return -EFAULT; \ } \ _buf->filp = filp; \ _outcount = 0; \ @@ -888,7 +888,7 @@ do { \ if (_buf->used <= 0) { \ DRM_ERROR( "DMAADVANCE() in %s: sending empty buf %d\n", \ __FUNCTION__, _buf->idx ); \ - return DRM_ERR(EFAULT); \ + return -EFAULT; \ } \ if (_buf->pending) { \ /* This is a resued buffer, so we need to find it in the pending list */ \ @@ -901,13 +901,13 @@ do { \ if (_entry->discard) { \ DRM_ERROR( "DMAADVANCE() in %s: sending discarded pending buf %d\n", \ __FUNCTION__, _buf->idx ); \ - return DRM_ERR(EFAULT); \ + return -EFAULT; \ } \ } else { \ if (list_empty(&dev_priv->placeholders)) { \ DRM_ERROR( "DMAADVANCE() in %s: empty placeholder list\n", \ __FUNCTION__ ); \ - return DRM_ERR(EFAULT); \ + return -EFAULT; \ } \ ptr = dev_priv->placeholders.next; \ list_del(ptr); \ @@ -983,12 +983,12 @@ do { \ if (_buf->used <= 0) { \ DRM_ERROR( "DMAADVANCEHOSTDATA() in %s: sending empty buf %d\n", \ __FUNCTION__, _buf->idx ); \ - return DRM_ERR(EFAULT); \ + return -EFAULT; \ } \ if (list_empty(&dev_priv->placeholders)) { \ DRM_ERROR( "%s: empty placeholder list in DMAADVANCEHOSTDATA()\n", \ __FUNCTION__ ); \ - return DRM_ERR(EFAULT); \ + return -EFAULT; \ } \ \ ptr = dev_priv->placeholders.next; \ diff --git a/shared-core/mach64_state.c b/shared-core/mach64_state.c index 95ad1ec3..397faaaa 100644 --- a/shared-core/mach64_state.c +++ b/shared-core/mach64_state.c @@ -237,7 +237,7 @@ static int mach64_dma_dispatch_clear(DRMFILE filp, struct drm_device * dev, fb_bpp = MACH64_DATATYPE_ARGB8888; break; default: - return DRM_ERR(EINVAL); + return -EINVAL; } switch (dev_priv->depth_bpp) { case 16: @@ -248,7 +248,7 @@ static int mach64_dma_dispatch_clear(DRMFILE filp, struct drm_device * dev, depth_bpp = MACH64_DATATYPE_ARGB8888; break; default: - return DRM_ERR(EINVAL); + return -EINVAL; } if (!nbox) @@ -489,11 +489,11 @@ static __inline__ int copy_from_user_vertex(u32 *to, from = drm_alloc(bytes, DRM_MEM_DRIVER); if (from == NULL) - return DRM_ERR(ENOMEM); + return -ENOMEM; if (DRM_COPY_FROM_USER(from, ufrom, bytes)) { drm_free(from, bytes, DRM_MEM_DRIVER); - return DRM_ERR(EFAULT); + return -EFAULT; } orig_from = from; /* we'll be modifying the "from" ptr, so save it */ @@ -525,14 +525,14 @@ static __inline__ int copy_from_user_vertex(u32 *to, DRM_ERROR("%s: Got bad command: 0x%04x\n", __FUNCTION__, reg); drm_free(orig_from, bytes, DRM_MEM_DRIVER); - return DRM_ERR(EACCES); + return -EACCES; } } else { DRM_ERROR ("%s: Got bad command count(=%u) dwords remaining=%lu\n", __FUNCTION__, count, n); drm_free(orig_from, bytes, DRM_MEM_DRIVER); - return DRM_ERR(EINVAL); + return -EINVAL; } } @@ -541,7 +541,7 @@ static __inline__ int copy_from_user_vertex(u32 *to, return 0; else { DRM_ERROR("%s: Bad buf->used(=%lu)\n", __FUNCTION__, bytes); - return DRM_ERR(EINVAL); + return -EINVAL; } } @@ -568,7 +568,7 @@ static int mach64_dma_dispatch_vertex(DRMFILE filp, struct drm_device * dev, copy_buf = mach64_freelist_get(dev_priv); if (copy_buf == NULL) { DRM_ERROR("%s: couldn't get buffer\n", __FUNCTION__); - return DRM_ERR(EAGAIN); + return -EAGAIN; } verify_ret = copy_from_user_vertex(GETBUFPTR(copy_buf), buf, used); @@ -634,7 +634,7 @@ static __inline__ int copy_from_user_blit(u32 *to, to = (u32 *)((char *)to + MACH64_HOSTDATA_BLIT_OFFSET); if (DRM_COPY_FROM_USER(to, ufrom, bytes)) { - return DRM_ERR(EFAULT); + return -EFAULT; } return 0; @@ -671,7 +671,7 @@ static int mach64_dma_dispatch_blit(DRMFILE filp, struct drm_device * dev, break; default: DRM_ERROR("invalid blit format %d\n", blit->format); - return DRM_ERR(EINVAL); + return -EINVAL; } /* Set buf->used to the bytes of blit data based on the blit dimensions @@ -684,13 +684,13 @@ static int mach64_dma_dispatch_blit(DRMFILE filp, struct drm_device * dev, if (used <= 0 || used > MACH64_BUFFER_SIZE - MACH64_HOSTDATA_BLIT_OFFSET) { DRM_ERROR("Invalid blit size: %lu bytes\n", used); - return DRM_ERR(EINVAL); + return -EINVAL; } copy_buf = mach64_freelist_get(dev_priv); if (copy_buf == NULL) { DRM_ERROR("%s: couldn't get buffer\n", __FUNCTION__); - return DRM_ERR(EAGAIN); + return -EAGAIN; } verify_ret = copy_from_user_blit(GETBUFPTR(copy_buf), blit->buf, used); @@ -814,7 +814,7 @@ int mach64_dma_vertex(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(vertex, (drm_mach64_vertex_t *) data, @@ -826,13 +826,13 @@ int mach64_dma_vertex(DRM_IOCTL_ARGS) if (vertex.prim < 0 || vertex.prim > MACH64_PRIM_POLYGON) { DRM_ERROR("buffer prim %d\n", vertex.prim); - return DRM_ERR(EINVAL); + return -EINVAL; } if (vertex.used > MACH64_BUFFER_SIZE || (vertex.used & 3) != 0) { DRM_ERROR("Invalid vertex buffer size: %lu bytes\n", vertex.used); - return DRM_ERR(EINVAL); + return -EINVAL; } if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS) @@ -875,7 +875,7 @@ int mach64_get_param(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(param, (drm_mach64_getparam_t *) data, @@ -891,12 +891,12 @@ int mach64_get_param(DRM_IOCTL_ARGS) value = dev->irq; break; default: - return DRM_ERR(EINVAL); + return -EINVAL; } if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { DRM_ERROR("copy_to_user\n"); - return DRM_ERR(EFAULT); + return -EFAULT; } return 0; diff --git a/shared-core/mga_dma.c b/shared-core/mga_dma.c index 9bed3b34..cbcb6380 100644 --- a/shared-core/mga_dma.c +++ b/shared-core/mga_dma.c @@ -71,7 +71,7 @@ int mga_do_wait_for_idle(drm_mga_private_t * dev_priv) DRM_ERROR("failed!\n"); DRM_INFO(" status=0x%08x\n", status); #endif - return DRM_ERR(EBUSY); + return -EBUSY; } static int mga_do_dma_reset(drm_mga_private_t * dev_priv) @@ -256,7 +256,7 @@ static int mga_freelist_init(struct drm_device * dev, drm_mga_private_t * dev_pr dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); if (dev_priv->head == NULL) - return DRM_ERR(ENOMEM); + return -ENOMEM; memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t)); SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0); @@ -267,7 +267,7 @@ static int mga_freelist_init(struct drm_device * dev, drm_mga_private_t * dev_pr entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); if (entry == NULL) - return DRM_ERR(ENOMEM); + return -ENOMEM; memset(entry, 0, sizeof(drm_mga_freelist_t)); @@ -399,7 +399,7 @@ int mga_driver_load(struct drm_device *dev, unsigned long flags) dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER); if (!dev_priv) - return DRM_ERR(ENOMEM); + return -ENOMEM; dev->dev_private = (void *)dev_priv; memset(dev_priv, 0, sizeof(drm_mga_private_t)); @@ -579,7 +579,7 @@ static int mga_do_agp_dma_bootstrap(struct drm_device *dev, DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n", dev_priv->warp->handle, dev_priv->primary->handle, dev->agp_buffer_map->handle); - return DRM_ERR(ENOMEM); + return -ENOMEM; } dev_priv->dma_access = MGA_PAGPXFER; @@ -616,7 +616,7 @@ static int mga_do_pci_dma_bootstrap(struct drm_device * dev, if (dev->dma == NULL) { DRM_ERROR("dev->dma is NULL\n"); - return DRM_ERR(EFAULT); + return -EFAULT; } /* Make drm_addbufs happy by not trying to create a mapping for less @@ -651,7 +651,7 @@ static int mga_do_pci_dma_bootstrap(struct drm_device * dev, if (err != 0) { DRM_ERROR("Unable to allocate primary DMA region: %d\n", err); - return DRM_ERR(ENOMEM); + return -ENOMEM; } if (dev_priv->primary->size != dma_bs->primary_size) { @@ -833,7 +833,7 @@ static int mga_do_init_dma(struct drm_device * dev, drm_mga_init_t * init) dev_priv->sarea = drm_getsarea(dev); if (!dev_priv->sarea) { DRM_ERROR("failed to find sarea!\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } if (! dev_priv->used_new_dma_init) { @@ -844,28 +844,28 @@ static int mga_do_init_dma(struct drm_device * dev, drm_mga_init_t * init) dev_priv->status = drm_core_findmap(dev, init->status_offset); if (!dev_priv->status) { DRM_ERROR("failed to find status page!\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); if (!dev_priv->mmio) { DRM_ERROR("failed to find mmio region!\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->warp = drm_core_findmap(dev, init->warp_offset); if (!dev_priv->warp) { DRM_ERROR("failed to find warp microcode region!\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->primary = drm_core_findmap(dev, init->primary_offset); if (!dev_priv->primary) { DRM_ERROR("failed to find primary dma region!\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } dev->agp_buffer_token = init->buffers_offset; dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); if (!dev->agp_buffer_map) { DRM_ERROR("failed to find dma buffer region!\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } drm_core_ioremap(dev_priv->warp, dev); @@ -883,7 +883,7 @@ static int mga_do_init_dma(struct drm_device * dev, drm_mga_init_t * init) ((dev->agp_buffer_map == NULL) || (dev->agp_buffer_map->handle == NULL)))) { DRM_ERROR("failed to ioremap agp regions!\n"); - return DRM_ERR(ENOMEM); + return -ENOMEM; } ret = mga_warp_install_microcode(dev_priv); @@ -933,7 +933,7 @@ static int mga_do_init_dma(struct drm_device * dev, drm_mga_init_t * init) if (mga_freelist_init(dev, dev_priv) < 0) { DRM_ERROR("could not initialize freelist\n"); - return DRM_ERR(ENOMEM); + return -ENOMEM; } return 0; @@ -1032,7 +1032,7 @@ int mga_dma_init(DRM_IOCTL_ARGS) return mga_do_cleanup_dma(dev, FULL_CLEANUP); } - return DRM_ERR(EINVAL); + return -EINVAL; } /* ================================================================ @@ -1097,16 +1097,16 @@ static int mga_dma_get_buffers(DRMFILE filp, struct drm_device * dev, struct drm for (i = d->granted_count; i < d->request_count; i++) { buf = mga_freelist_get(dev); if (!buf) - return DRM_ERR(EAGAIN); + return -EAGAIN; buf->filp = filp; if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, sizeof(buf->idx))) - return DRM_ERR(EFAULT); + return -EFAULT; if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, sizeof(buf->total))) - return DRM_ERR(EFAULT); + return -EFAULT; d->granted_count++; } @@ -1131,7 +1131,7 @@ int mga_dma_buffers(DRM_IOCTL_ARGS) if (d.send_count != 0) { DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", DRM_CURRENTPID, d.send_count); - return DRM_ERR(EINVAL); + return -EINVAL; } /* We'll send you buffers. @@ -1139,7 +1139,7 @@ int mga_dma_buffers(DRM_IOCTL_ARGS) if (d.request_count < 0 || d.request_count > dma->buf_count) { DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", DRM_CURRENTPID, d.request_count, dma->buf_count); - return DRM_ERR(EINVAL); + return -EINVAL; } WRAP_TEST_WITH_RETURN(dev_priv); diff --git a/shared-core/mga_drv.h b/shared-core/mga_drv.h index 10096a95..2da31194 100644 --- a/shared-core/mga_drv.h +++ b/shared-core/mga_drv.h @@ -245,7 +245,7 @@ do { \ dev_priv->prim.high_mark ) { \ if ( MGA_DMA_DEBUG ) \ DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ - return DRM_ERR(EBUSY); \ + return -EBUSY; \ } \ } \ } while (0) @@ -256,7 +256,7 @@ do { \ if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \ if ( MGA_DMA_DEBUG ) \ DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ - return DRM_ERR(EBUSY); \ + return -EBUSY; \ } \ mga_do_dma_wrap_end( dev_priv ); \ } \ diff --git a/shared-core/mga_state.c b/shared-core/mga_state.c index 6d93c9e4..f77883db 100644 --- a/shared-core/mga_state.c +++ b/shared-core/mga_state.c @@ -416,7 +416,7 @@ static int mga_verify_context(drm_mga_private_t * dev_priv) ctx->dstorg, dev_priv->front_offset, dev_priv->back_offset); ctx->dstorg = 0; - return DRM_ERR(EINVAL); + return -EINVAL; } return 0; @@ -435,7 +435,7 @@ static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit) if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) { DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit); tex->texorg = 0; - return DRM_ERR(EINVAL); + return -EINVAL; } return 0; @@ -477,13 +477,13 @@ static int mga_verify_iload(drm_mga_private_t * dev_priv, dstorg + length > (dev_priv->texture_offset + dev_priv->texture_size)) { DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg); - return DRM_ERR(EINVAL); + return -EINVAL; } if (length & MGA_ILOAD_MASK) { DRM_ERROR("*** bad iload length: 0x%x\n", length & MGA_ILOAD_MASK); - return DRM_ERR(EINVAL); + return -EINVAL; } return 0; @@ -495,7 +495,7 @@ static int mga_verify_blit(drm_mga_private_t * dev_priv, if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) || (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) { DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg); - return DRM_ERR(EINVAL); + return -EINVAL; } return 0; } @@ -929,7 +929,7 @@ static int mga_dma_vertex(DRM_IOCTL_ARGS) sizeof(vertex)); if (vertex.idx < 0 || vertex.idx > dma->buf_count) - return DRM_ERR(EINVAL); + return -EINVAL; buf = dma->buflist[vertex.idx]; buf_priv = buf->dev_private; @@ -943,7 +943,7 @@ static int mga_dma_vertex(DRM_IOCTL_ARGS) buf_priv->dispatched = 0; mga_freelist_put(dev, buf); } - return DRM_ERR(EINVAL); + return -EINVAL; } WRAP_TEST_WITH_RETURN(dev_priv); @@ -969,7 +969,7 @@ static int mga_dma_indices(DRM_IOCTL_ARGS) sizeof(indices)); if (indices.idx < 0 || indices.idx > dma->buf_count) - return DRM_ERR(EINVAL); + return -EINVAL; buf = dma->buflist[indices.idx]; buf_priv = buf->dev_private; @@ -983,7 +983,7 @@ static int mga_dma_indices(DRM_IOCTL_ARGS) buf_priv->dispatched = 0; mga_freelist_put(dev, buf); } - return DRM_ERR(EINVAL); + return -EINVAL; } WRAP_TEST_WITH_RETURN(dev_priv); @@ -1012,18 +1012,18 @@ static int mga_dma_iload(DRM_IOCTL_ARGS) if (mga_do_wait_for_idle(dev_priv) < 0) { if (MGA_DMA_DEBUG) DRM_INFO("%s: -EBUSY\n", __FUNCTION__); - return DRM_ERR(EBUSY); + return -EBUSY; } #endif if (iload.idx < 0 || iload.idx > dma->buf_count) - return DRM_ERR(EINVAL); + return -EINVAL; buf = dma->buflist[iload.idx]; buf_priv = buf->dev_private; if (mga_verify_iload(dev_priv, iload.dstorg, iload.length)) { mga_freelist_put(dev, buf); - return DRM_ERR(EINVAL); + return -EINVAL; } WRAP_TEST_WITH_RETURN(dev_priv); @@ -1054,7 +1054,7 @@ static int mga_dma_blit(DRM_IOCTL_ARGS) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; if (mga_verify_blit(dev_priv, blit.srcorg, blit.dstorg)) - return DRM_ERR(EINVAL); + return -EINVAL; WRAP_TEST_WITH_RETURN(dev_priv); @@ -1076,7 +1076,7 @@ static int mga_getparam(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(param, (drm_mga_getparam_t __user *) data, @@ -1092,12 +1092,12 @@ static int mga_getparam(DRM_IOCTL_ARGS) value = dev_priv->chipset; break; default: - return DRM_ERR(EINVAL); + return -EINVAL; } if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { DRM_ERROR("copy_to_user\n"); - return DRM_ERR(EFAULT); + return -EFAULT; } return 0; @@ -1112,7 +1112,7 @@ static int mga_set_fence(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); @@ -1144,7 +1144,7 @@ static int mga_wait_fence(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(fence, (u32 __user *) data, sizeof(u32)); diff --git a/shared-core/mga_warp.c b/shared-core/mga_warp.c index 05ed8058..9a44bddb 100644 --- a/shared-core/mga_warp.c +++ b/shared-core/mga_warp.c @@ -146,7 +146,7 @@ int mga_warp_install_microcode(drm_mga_private_t * dev_priv) if (size > dev_priv->warp->size) { DRM_ERROR("microcode too large! (%u > %lu)\n", size, dev_priv->warp->size); - return DRM_ERR(ENOMEM); + return -ENOMEM; } switch (dev_priv->chipset) { @@ -156,7 +156,7 @@ int mga_warp_install_microcode(drm_mga_private_t * dev_priv) case MGA_CARD_TYPE_G200: return mga_warp_install_g200_microcode(dev_priv); default: - return DRM_ERR(EINVAL); + return -EINVAL; } } @@ -182,7 +182,7 @@ int mga_warp_init(drm_mga_private_t * dev_priv) MGA_WRITE(MGA_WVRTXSZ, 7); break; default: - return DRM_ERR(EINVAL); + return -EINVAL; } MGA_WRITE(MGA_WMISC, (MGA_WUCODECACHE_ENABLE | @@ -191,7 +191,7 @@ int mga_warp_init(drm_mga_private_t * dev_priv) if (wmisc != WMISC_EXPECTED) { DRM_ERROR("WARP engine config failed! 0x%x != 0x%x\n", wmisc, WMISC_EXPECTED); - return DRM_ERR(EINVAL); + return -EINVAL; } return 0; diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 230c8298..e3a6674d 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -207,7 +207,7 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) (DRMFILE)-2); if (!cb) { DRM_ERROR("Couldn't allocate DMA command buffer.\n"); - return DRM_ERR(ENOMEM); + return -ENOMEM; } if (cb->flags & NOUVEAU_MEM_AGP) { @@ -289,13 +289,13 @@ int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret, DRMFILE filp, } /* no more fifos. you lost. */ if (channel==nouveau_fifo_number(dev)) - return DRM_ERR(EINVAL); + return -EINVAL; (*chan_ret) = channel; dev_priv->fifos[channel] = drm_calloc(1, sizeof(struct nouveau_fifo), DRM_MEM_DRIVER); if (!dev_priv->fifos[channel]) - return DRM_ERR(ENOMEM); + return -ENOMEM; dev_priv->fifo_alloc_count++; chan = dev_priv->fifos[channel]; chan->filp = filp; @@ -483,7 +483,7 @@ static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) sizeof(init)); if (init.fb_ctxdma_handle == ~0 || init.tt_ctxdma_handle == ~0) - return DRM_ERR(EINVAL); + return -EINVAL; res = nouveau_fifo_alloc(dev, &init.channel, filp, init.fb_ctxdma_handle, @@ -511,7 +511,7 @@ static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) entry = drm_find_matching_map(dev, chan->regs); if (!entry) - return DRM_ERR(EINVAL); + return -EINVAL; init.ctrl = entry->user_token; /* pass back FIFO map info to the caller */ diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 7a923e17..143378ff 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -138,12 +138,12 @@ int nouveau_mem_init_heap(struct mem_block **heap, uint64_t start, struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFS); if (!blocks) - return DRM_ERR(ENOMEM); + return -ENOMEM; *heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFS); if (!*heap) { drm_free(blocks, sizeof(*blocks), DRM_MEM_BUFS); - return DRM_ERR(ENOMEM); + return -ENOMEM; } blocks->start = start; @@ -363,13 +363,13 @@ int nouveau_mem_init(struct drm_device *dev) * So we create a second FB heap for that type of memory */ if (nouveau_mem_init_heap(&dev_priv->fb_heap, 0, 256*1024*1024)) - return DRM_ERR(ENOMEM); + return -ENOMEM; if (nouveau_mem_init_heap(&dev_priv->fb_nomap_heap, 256*1024*1024, fb_size-256*1024*1024)) - return DRM_ERR(ENOMEM); + return -ENOMEM; } else { if (nouveau_mem_init_heap(&dev_priv->fb_heap, 0, fb_size)) - return DRM_ERR(ENOMEM); + return -ENOMEM; dev_priv->fb_nomap_heap=NULL; } @@ -549,7 +549,7 @@ int nouveau_ioctl_mem_alloc(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(alloc, @@ -558,7 +558,7 @@ int nouveau_ioctl_mem_alloc(DRM_IOCTL_ARGS) block=nouveau_mem_alloc(dev, alloc.alignment, alloc.size, alloc.flags, filp); if (!block) - return DRM_ERR(ENOMEM); + return -ENOMEM; alloc.map_handle=block->map_handle; alloc.offset=block->start; alloc.flags=block->flags; @@ -588,9 +588,9 @@ int nouveau_ioctl_mem_free(DRM_IOCTL_ARGS) else if (memfree.flags&NOUVEAU_MEM_PCI) block = find_block(dev_priv->pci_heap, memfree.offset); if (!block) - return DRM_ERR(EFAULT); + return -EFAULT; if (block->filp != filp) - return DRM_ERR(EPERM); + return -EPERM; nouveau_mem_free(dev, block); return 0; diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index 238e3c8b..425e471c 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -46,7 +46,7 @@ nouveau_notifier_init_channel(struct drm_device *dev, int channel, DRMFILE filp) chan->notifier_block = nouveau_mem_alloc(dev, 0, PAGE_SIZE, flags,filp); if (!chan->notifier_block) - return DRM_ERR(ENOMEM); + return -ENOMEM; ret = nouveau_mem_init_heap(&chan->notifier_heap, 0, chan->notifier_block->size); @@ -84,13 +84,13 @@ nouveau_notifier_alloc(struct drm_device *dev, int channel, uint32_t handle, if (!chan->notifier_heap) { DRM_ERROR("Channel %d doesn't have a notifier heap!\n", channel); - return DRM_ERR(EINVAL); + return -EINVAL; } mem = nouveau_mem_alloc_block(chan->notifier_heap, 32, 0, chan->filp); if (!mem) { DRM_ERROR("Channel %d notifier block full\n", channel); - return DRM_ERR(ENOMEM); + return -ENOMEM; } mem->flags = NOUVEAU_MEM_NOTIFIER; @@ -102,7 +102,7 @@ nouveau_notifier_alloc(struct drm_device *dev, int channel, uint32_t handle, } else { DRM_ERROR("Bad DMA target, flags 0x%08x!\n", chan->notifier_block->flags); - return DRM_ERR(EINVAL); + return -EINVAL; } if ((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, @@ -138,7 +138,7 @@ nouveau_ioctl_notifier_alloc(DRM_IOCTL_ARGS) if (!nouveau_fifo_owner(dev, filp, na.channel)) { DRM_ERROR("pid %d doesn't own channel %d\n", DRM_CURRENTPID, na.channel); - return DRM_ERR(EPERM); + return -EPERM; } ret = nouveau_notifier_alloc(dev, na.channel, na.handle, diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index f0025d7a..30d515f0 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -107,7 +107,7 @@ nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) if (!ramht) { DRM_ERROR("No hash table!\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } if (dev_priv->card_type < NV_40) { @@ -142,7 +142,7 @@ nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) } while (co != ho); DRM_ERROR("RAMHT space exhausted. ch=%d\n", ref->channel); - return DRM_ERR(ENOMEM); + return -ENOMEM; } static void @@ -194,17 +194,17 @@ nouveau_gpuobj_new(struct drm_device *dev, int channel, int size, int align, channel, size, align, flags); if (!dev_priv || !gpuobj_ret || *gpuobj_ret != NULL) - return DRM_ERR(EINVAL); + return -EINVAL; if (channel >= 0) { if (channel > nouveau_fifo_number(dev)) - return DRM_ERR(EINVAL); + return -EINVAL; chan = dev_priv->fifos[channel]; } gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER); if (!gpuobj) - return DRM_ERR(ENOMEM); + return -ENOMEM; DRM_DEBUG("gpuobj %p\n", gpuobj); gpuobj->flags = flags; gpuobj->im_channel = channel; @@ -230,7 +230,7 @@ nouveau_gpuobj_new(struct drm_device *dev, int channel, int size, int align, if (!pramin) { DRM_ERROR("No PRAMIN heap!\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } if (!chan && (ret = engine->instmem.populate(dev, gpuobj, &size))) { @@ -244,7 +244,7 @@ nouveau_gpuobj_new(struct drm_device *dev, int channel, int size, int align, (DRMFILE)-2); if (!gpuobj->im_pramin) { nouveau_gpuobj_del(dev, &gpuobj); - return DRM_ERR(ENOMEM); + return -ENOMEM; } gpuobj->im_pramin->flags = NOUVEAU_MEM_INSTANCE; @@ -294,12 +294,12 @@ int nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj) DRM_DEBUG("gpuobj %p\n", pgpuobj ? *pgpuobj : NULL); if (!dev_priv || !pgpuobj || !(*pgpuobj)) - return DRM_ERR(EINVAL); + return -EINVAL; gpuobj = *pgpuobj; if (gpuobj->refcount != 0) { DRM_ERROR("gpuobj refcount is %d\n", gpuobj->refcount); - return DRM_ERR(EINVAL); + return -EINVAL; } engine->instmem.clear(dev, gpuobj); @@ -340,7 +340,7 @@ nouveau_gpuobj_instance_get(struct drm_device *dev, int channel, if ((channel > 0) && gpuobj->im_channel != channel) { DRM_ERROR("Channel mismatch: obj %d, ref %d\n", gpuobj->im_channel, channel); - return DRM_ERR(EINVAL); + return -EINVAL; } /* NV50 channel-local instance */ @@ -355,7 +355,7 @@ nouveau_gpuobj_instance_get(struct drm_device *dev, int channel, /* ...from global heap */ if (!gpuobj->im_backing) { DRM_ERROR("AII, no VRAM backing gpuobj\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } *inst = gpuobj->im_backing->start; return 0; @@ -367,7 +367,7 @@ nouveau_gpuobj_instance_get(struct drm_device *dev, int channel, return 0; } - return DRM_ERR(EINVAL); + return -EINVAL; } int @@ -383,15 +383,15 @@ nouveau_gpuobj_ref_add(struct drm_device *dev, int channel, uint32_t handle, DRM_DEBUG("ch%d h=0x%08x gpuobj=%p\n", channel, handle, gpuobj); if (!dev_priv || !gpuobj || (ref_ret && *ref_ret != NULL)) - return DRM_ERR(EINVAL); + return -EINVAL; if (channel >= 0) { if (channel > nouveau_fifo_number(dev)) - return DRM_ERR(EINVAL); + return -EINVAL; chan = dev_priv->fifos[channel]; } else if (!ref_ret) - return DRM_ERR(EINVAL); + return -EINVAL; ret = nouveau_gpuobj_instance_get(dev, channel, gpuobj, &instance); if (ret) @@ -399,7 +399,7 @@ nouveau_gpuobj_ref_add(struct drm_device *dev, int channel, uint32_t handle, ref = drm_calloc(1, sizeof(*ref), DRM_MEM_DRIVER); if (!ref) - return DRM_ERR(ENOMEM); + return -ENOMEM; ref->gpuobj = gpuobj; ref->channel = channel; ref->instance = instance; @@ -431,7 +431,7 @@ int nouveau_gpuobj_ref_del(struct drm_device *dev, struct nouveau_gpuobj_ref **p DRM_DEBUG("ref %p\n", pref ? *pref : NULL); if (!dev || !pref || *pref == NULL) - return DRM_ERR(EINVAL); + return -EINVAL; ref = *pref; if (ref->handle != ~0) @@ -487,7 +487,7 @@ nouveau_gpuobj_ref_find(struct drm_device *dev, int channel, uint32_t handle, ref = ref->next; } - return DRM_ERR(EINVAL); + return -EINVAL; } int @@ -504,7 +504,7 @@ nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t offset, uint32_t size, gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER); if (!gpuobj) - return DRM_ERR(ENOMEM); + return -ENOMEM; DRM_DEBUG("gpuobj %p\n", gpuobj); gpuobj->im_channel = -1; gpuobj->flags = flags | NVOBJ_FLAG_FAKE; @@ -513,7 +513,7 @@ nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t offset, uint32_t size, DRM_MEM_DRIVER); if (!gpuobj->im_pramin) { nouveau_gpuobj_del(dev, &gpuobj); - return DRM_ERR(ENOMEM); + return -ENOMEM; } gpuobj->im_pramin->start = offset; gpuobj->im_pramin->size = size; @@ -650,7 +650,7 @@ nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class, if ((idx + page_count) > dev->sg->pages) { DRM_ERROR("Requested page range exceedes " "allocated scatter-gather range!"); - return DRM_ERR(E2BIG); + return -E2BIG; } DRM_DEBUG("Creating PCI DMA object using virtual zone starting at %#llx, size %d\n", offset, (uint32_t)size); @@ -676,7 +676,7 @@ nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class, DMA_BIDIRECTIONAL); if (dma_mapping_error(dev->sg->busaddr[idx])) { - return DRM_ERR(ENOMEM); + return -ENOMEM; } } @@ -733,14 +733,14 @@ nouveau_gpuobj_gart_dma_new(struct drm_device *dev, int channel, *gpuobj = dev_priv->gart_info.sg_ctxdma; if (offset & ~0xffffffffULL) { DRM_ERROR("obj offset exceeds 32-bits\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } if (o_ret) *o_ret = (uint32_t)offset; - ret = (*gpuobj != NULL) ? 0 : DRM_ERR(EINVAL); + ret = (*gpuobj != NULL) ? 0 : -EINVAL; } else { DRM_ERROR("Invalid GART type %d\n", dev_priv->gart_info.type); - return DRM_ERR(EINVAL); + return -EINVAL; } return ret; @@ -982,7 +982,7 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel, NV_DMA_TARGET_PCI_NONLINEAR, &tt); } else { DRM_ERROR("Invalid GART type %d\n", dev_priv->gart_info.type); - ret = DRM_ERR(EINVAL); + ret = -EINVAL; } if (ret) { @@ -1038,15 +1038,15 @@ int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS) if (!nouveau_fifo_owner(dev, filp, init.channel)) { DRM_ERROR("pid %d doesn't own channel %d\n", DRM_CURRENTPID, init.channel); - return DRM_ERR(EINVAL); + return -EINVAL; } //FIXME: check args, only allow trusted objects to be created if (init.handle == ~0) - return DRM_ERR(EINVAL); + return -EINVAL; if (nouveau_gpuobj_ref_find(dev, init.channel, init.handle, NULL) == 0) - return DRM_ERR(EEXIST); + return -EEXIST; if ((ret = nouveau_gpuobj_gr_new(dev, init.channel, init.class, &gr))) { DRM_ERROR("Error creating gr object: %d (%d/0x%08x)\n", diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index a26ecea3..b6459957 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -383,11 +383,11 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) struct drm_nouveau_private *dev_priv; if (flags==NV_UNKNOWN) - return DRM_ERR(EINVAL); + return -EINVAL; dev_priv = drm_calloc(1, sizeof(*dev_priv), DRM_MEM_DRIVER); if (!dev_priv) - return DRM_ERR(ENOMEM); + return -ENOMEM; dev_priv->card_type=flags&NOUVEAU_FAMILY; dev_priv->flags=flags&NOUVEAU_FLAGS; @@ -463,7 +463,7 @@ int nouveau_ioctl_getparam(DRM_IOCTL_ARGS) else { DRM_ERROR("Requested PCIGART address, while no PCIGART was created\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } break; case NOUVEAU_GETPARAM_FB_SIZE: @@ -474,7 +474,7 @@ int nouveau_ioctl_getparam(DRM_IOCTL_ARGS) break; default: DRM_ERROR("unknown parameter %lld\n", getparam.param); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_TO_USER_IOCTL((struct drm_nouveau_getparam __user *)data, @@ -503,7 +503,7 @@ int nouveau_ioctl_setparam(DRM_IOCTL_ARGS) default: DRM_ERROR("invalid CMDBUF_LOCATION value=%lld\n", setparam.value); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->config.cmdbuf.location = setparam.value; break; @@ -512,7 +512,7 @@ int nouveau_ioctl_setparam(DRM_IOCTL_ARGS) break; default: DRM_ERROR("unknown parameter %lld\n", setparam.param); - return DRM_ERR(EINVAL); + return -EINVAL; } return 0; diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index 7cf06269..35b20abd 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -126,7 +126,7 @@ int nv04_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz) { if (gpuobj->im_backing) - return DRM_ERR(EINVAL); + return -EINVAL; return 0; } @@ -148,7 +148,7 @@ int nv04_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { if (!gpuobj->im_pramin || gpuobj->im_bound) - return DRM_ERR(EINVAL); + return -EINVAL; gpuobj->im_bound = 1; return 0; @@ -158,7 +158,7 @@ int nv04_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { if (gpuobj->im_bound == 0) - return DRM_ERR(EINVAL); + return -EINVAL; gpuobj->im_bound = 0; return 0; diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 8af3bd12..1670c527 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -81,7 +81,7 @@ int nv20_graph_save_context(struct drm_device *dev, int channel) { instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel); if (!instance) { - return DRM_ERR(EINVAL); + return -EINVAL; } if (instance != (chan->ramin_grctx->instance >> 4)) DRM_ERROR("nv20_graph_save_context : bad instance\n"); @@ -102,7 +102,7 @@ int nv20_graph_load_context(struct drm_device *dev, int channel) { instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel); if (!instance) { - return DRM_ERR(EINVAL); + return -EINVAL; } if (instance != (chan->ramin_grctx->instance >> 4)) DRM_ERROR("nv20_graph_load_context_current : bad instance\n"); diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index d7138772..4ed2e2ba 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -156,7 +156,7 @@ nouveau_graph_wait_idle(struct drm_device *dev) if (NV_READ(0x400700)) { DRM_ERROR("timeout!\n"); - return DRM_ERR(EBUSY); + return -EBUSY; } return 0; } @@ -168,7 +168,7 @@ int nv30_graph_load_context(struct drm_device *dev, int channel) uint32_t inst; if (!chan->ramin_grctx) - return DRM_ERR(EINVAL); + return -EINVAL; inst = chan->ramin_grctx->instance >> 4; NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); @@ -185,7 +185,7 @@ int nv30_graph_save_context(struct drm_device *dev, int channel) uint32_t inst; if (!chan->ramin_grctx) - return DRM_ERR(EINVAL); + return -EINVAL; inst = chan->ramin_grctx->instance >> 4; NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index d8fccb7e..441dbae7 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -1317,7 +1317,7 @@ nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save) DRM_ERROR("failed: inst=0x%08x save=%d\n", inst, save); DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(NV40_PGRAPH_CTXCTL_030C)); - return DRM_ERR(EBUSY); + return -EBUSY; } return 0; @@ -1334,7 +1334,7 @@ nv40_graph_save_context(struct drm_device *dev, int channel) uint32_t inst; if (!chan->ramin_grctx) - return DRM_ERR(EINVAL); + return -EINVAL; inst = chan->ramin_grctx->instance >> 4; return nv40_graph_transfer_context(dev, inst, 1); @@ -1352,7 +1352,7 @@ nv40_graph_load_context(struct drm_device *dev, int channel) int ret; if (!chan->ramin_grctx) - return DRM_ERR(EINVAL); + return -EINVAL; inst = chan->ramin_grctx->instance >> 4; ret = nv40_graph_transfer_context(dev, inst, 0); diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index 4933bbf3..f7b98220 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -69,14 +69,14 @@ nv50_fifo_channel_enable(struct drm_device *dev, int channel) if (IS_G80) { if (!chan->ramin) - return DRM_ERR(EINVAL); + return -EINVAL; NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), (chan->ramin->instance >> 12) | NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); } else { if (!chan->ramfc) - return DRM_ERR(EINVAL); + return -EINVAL; NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), (chan->ramfc->instance >> 8) | @@ -186,7 +186,7 @@ nv50_fifo_init(struct drm_device *dev) priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER); if (!priv) - return DRM_ERR(ENOMEM); + return -ENOMEM; dev_priv->Engine.fifo.priv = priv; nv50_fifo_init_reset(dev); diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c index 6a04c158..8df5df25 100644 --- a/shared-core/nv50_graph.c +++ b/shared-core/nv50_graph.c @@ -259,7 +259,7 @@ nv50_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save) DRM_ERROR("failed: inst=0x%08x save=%d\n", inst, save); DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(NV40_PGRAPH_CTXCTL_030C)); - return DRM_ERR(EBUSY); + return -EBUSY; } return 0; diff --git a/shared-core/nv50_instmem.c b/shared-core/nv50_instmem.c index 027d3ffb..ad77f441 100644 --- a/shared-core/nv50_instmem.c +++ b/shared-core/nv50_instmem.c @@ -49,7 +49,7 @@ nv50_instmem_init(struct drm_device *dev) priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER); if (!priv) - return DRM_ERR(ENOMEM); + return -ENOMEM; dev_priv->Engine.instmem.priv = priv; /* Save current state */ @@ -126,14 +126,14 @@ nv50_instmem_init(struct drm_device *dev) NV_WRITE(0x1700, pt >> 16); if (NV_READ(0x700000) != NV_RI32(0)) { DRM_ERROR("Failed to init PRAMIN page table\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } /* Create a heap to manage PRAMIN aperture allocations */ ret = nouveau_mem_init_heap(&dev_priv->ramin_heap, pts, as-pts); if (ret) { DRM_ERROR("Failed to init PRAMIN heap\n"); - return DRM_ERR(ENOMEM); + return -ENOMEM; } DRM_DEBUG("NV50: PRAMIN setup ok\n"); @@ -171,18 +171,18 @@ int nv50_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz) { if (gpuobj->im_backing) - return DRM_ERR(EINVAL); + return -EINVAL; *sz = (*sz + (NV50_INSTMEM_PAGE_SIZE-1)) & ~(NV50_INSTMEM_PAGE_SIZE-1); if (*sz == 0) - return DRM_ERR(EINVAL); + return -EINVAL; gpuobj->im_backing = nouveau_mem_alloc(dev, NV50_INSTMEM_PAGE_SIZE, *sz, NOUVEAU_MEM_FB, (DRMFILE)-2); if (!gpuobj->im_backing) { DRM_ERROR("Couldn't allocate vram to back PRAMIN pages\n"); - return DRM_ERR(ENOMEM); + return -ENOMEM; } return 0; @@ -208,7 +208,7 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) uint32_t pte, pte_end, vram; if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound) - return DRM_ERR(EINVAL); + return -EINVAL; DRM_DEBUG("st=0x%0llx sz=0x%0llx\n", gpuobj->im_pramin->start, gpuobj->im_pramin->size); @@ -246,7 +246,7 @@ nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) uint32_t pte, pte_end; if (gpuobj->im_bound == 0) - return DRM_ERR(EINVAL); + return -EINVAL; pte = (gpuobj->im_pramin->start >> 12) << 3; pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte; diff --git a/shared-core/r128_cce.c b/shared-core/r128_cce.c index 167fc070..51b290b4 100644 --- a/shared-core/r128_cce.c +++ b/shared-core/r128_cce.c @@ -129,7 +129,7 @@ static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv) #if R128_FIFO_DEBUG DRM_ERROR("failed!\n"); #endif - return DRM_ERR(EBUSY); + return -EBUSY; } static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries) @@ -146,7 +146,7 @@ static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries) #if R128_FIFO_DEBUG DRM_ERROR("failed!\n"); #endif - return DRM_ERR(EBUSY); + return -EBUSY; } static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv) @@ -168,7 +168,7 @@ static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv) #if R128_FIFO_DEBUG DRM_ERROR("failed!\n"); #endif - return DRM_ERR(EBUSY); + return -EBUSY; } /* ================================================================ @@ -227,7 +227,7 @@ int r128_do_cce_idle(drm_r128_private_t * dev_priv) DRM_ERROR("failed!\n"); r128_status(dev_priv); #endif - return DRM_ERR(EBUSY); + return -EBUSY; } /* Start the Concurrent Command Engine. @@ -355,7 +355,7 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER); if (dev_priv == NULL) - return DRM_ERR(ENOMEM); + return -ENOMEM; memset(dev_priv, 0, sizeof(drm_r128_private_t)); @@ -365,7 +365,7 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) DRM_ERROR("PCI GART memory not allocated!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->usec_timeout = init->usec_timeout; @@ -374,7 +374,7 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) DRM_DEBUG("TIMEOUT problem!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->cce_mode = init->cce_mode; @@ -394,7 +394,7 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) DRM_DEBUG("Bad cce_mode!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } switch (init->cce_mode) { @@ -461,7 +461,7 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) DRM_ERROR("could not find sarea!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); @@ -469,21 +469,21 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) DRM_ERROR("could not find mmio region!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset); if (!dev_priv->cce_ring) { DRM_ERROR("could not find cce ring region!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); if (!dev_priv->ring_rptr) { DRM_ERROR("could not find ring read pointer!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } dev->agp_buffer_token = init->buffers_offset; dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); @@ -491,7 +491,7 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) DRM_ERROR("could not find dma buffer region!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } if (!dev_priv->is_pci) { @@ -501,7 +501,7 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) DRM_ERROR("could not find agp texture region!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } } @@ -520,7 +520,7 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) DRM_ERROR("Could not ioremap agp regions!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce(dev); - return DRM_ERR(ENOMEM); + return -ENOMEM; } } else #endif @@ -567,7 +567,7 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) DRM_ERROR("failed to init PCI GART!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce(dev); - return DRM_ERR(ENOMEM); + return -ENOMEM; } R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr); #if __OS_HAS_AGP @@ -642,7 +642,7 @@ int r128_cce_init(DRM_IOCTL_ARGS) return r128_do_cleanup_cce(dev); } - return DRM_ERR(EINVAL); + return -EINVAL; } int r128_cce_start(DRM_IOCTL_ARGS) @@ -719,7 +719,7 @@ int r128_cce_reset(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_DEBUG("%s called before init done\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } r128_do_cce_reset(dev_priv); @@ -757,7 +757,7 @@ int r128_engine_reset(DRM_IOCTL_ARGS) int r128_fullscreen(DRM_IOCTL_ARGS) { - return DRM_ERR(EINVAL); + return -EINVAL; } /* ================================================================ @@ -778,7 +778,7 @@ static int r128_freelist_init(struct drm_device * dev) dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER); if (dev_priv->head == NULL) - return DRM_ERR(ENOMEM); + return -ENOMEM; memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t)); dev_priv->head->age = R128_BUFFER_USED; @@ -789,7 +789,7 @@ static int r128_freelist_init(struct drm_device * dev) entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER); if (!entry) - return DRM_ERR(ENOMEM); + return -ENOMEM; entry->age = R128_BUFFER_FREE; entry->buf = buf; @@ -881,7 +881,7 @@ int r128_wait_ring(drm_r128_private_t * dev_priv, int n) /* FIXME: This is being ignored... */ DRM_ERROR("failed!\n"); - return DRM_ERR(EBUSY); + return -EBUSY; } static int r128_cce_get_buffers(DRMFILE filp, struct drm_device * dev, struct drm_dma * d) @@ -892,16 +892,16 @@ static int r128_cce_get_buffers(DRMFILE filp, struct drm_device * dev, struct dr for (i = d->granted_count; i < d->request_count; i++) { buf = r128_freelist_get(dev); if (!buf) - return DRM_ERR(EAGAIN); + return -EAGAIN; buf->filp = filp; if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, sizeof(buf->idx))) - return DRM_ERR(EFAULT); + return -EFAULT; if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, sizeof(buf->total))) - return DRM_ERR(EFAULT); + return -EFAULT; d->granted_count++; } @@ -925,7 +925,7 @@ int r128_cce_buffers(DRM_IOCTL_ARGS) if (d.send_count != 0) { DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", DRM_CURRENTPID, d.send_count); - return DRM_ERR(EINVAL); + return -EINVAL; } /* We'll send you buffers. @@ -933,7 +933,7 @@ int r128_cce_buffers(DRM_IOCTL_ARGS) if (d.request_count < 0 || d.request_count > dma->buf_count) { DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", DRM_CURRENTPID, d.request_count, dma->buf_count); - return DRM_ERR(EINVAL); + return -EINVAL; } d.granted_count = 0; diff --git a/shared-core/r128_drv.h b/shared-core/r128_drv.h index c9abd67b..077b2763 100644 --- a/shared-core/r128_drv.h +++ b/shared-core/r128_drv.h @@ -428,7 +428,7 @@ do { \ DRM_UDELAY(1); \ } \ DRM_ERROR( "ring space check failed!\n" ); \ - return DRM_ERR(EBUSY); \ + return -EBUSY; \ } \ __ring_space_done: \ ; \ diff --git a/shared-core/r128_state.c b/shared-core/r128_state.c index b793d94b..6b19c4d3 100644 --- a/shared-core/r128_state.c +++ b/shared-core/r128_state.c @@ -809,7 +809,7 @@ static int r128_cce_dispatch_blit(DRMFILE filp, break; default: DRM_ERROR("invalid blit format %d\n", blit->format); - return DRM_ERR(EINVAL); + return -EINVAL; } /* Flush the pixel cache, and mark the contents as Read Invalid. @@ -832,11 +832,11 @@ static int r128_cce_dispatch_blit(DRMFILE filp, if (buf->filp != filp) { DRM_ERROR("process %d using buffer owned by %p\n", DRM_CURRENTPID, buf->filp); - return DRM_ERR(EINVAL); + return -EINVAL; } if (buf->pending) { DRM_ERROR("sending pending buffer %d\n", blit->idx); - return DRM_ERR(EINVAL); + return -EINVAL; } buf_priv->discard = 1; @@ -900,22 +900,22 @@ static int r128_cce_dispatch_write_span(struct drm_device * dev, count = depth->n; if (count > 4096 || count <= 0) - return DRM_ERR(EMSGSIZE); + return -EMSGSIZE; if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) { - return DRM_ERR(EFAULT); + return -EFAULT; } if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) { - return DRM_ERR(EFAULT); + return -EFAULT; } buffer_size = depth->n * sizeof(u32); buffer = drm_alloc(buffer_size, DRM_MEM_BUFS); if (buffer == NULL) - return DRM_ERR(ENOMEM); + return -ENOMEM; if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) { drm_free(buffer, buffer_size, DRM_MEM_BUFS); - return DRM_ERR(EFAULT); + return -EFAULT; } mask_size = depth->n * sizeof(u8); @@ -923,12 +923,12 @@ static int r128_cce_dispatch_write_span(struct drm_device * dev, mask = drm_alloc(mask_size, DRM_MEM_BUFS); if (mask == NULL) { drm_free(buffer, buffer_size, DRM_MEM_BUFS); - return DRM_ERR(ENOMEM); + return -ENOMEM; } if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) { drm_free(buffer, buffer_size, DRM_MEM_BUFS); drm_free(mask, mask_size, DRM_MEM_BUFS); - return DRM_ERR(EFAULT); + return -EFAULT; } for (i = 0; i < count; i++, x++) { @@ -996,28 +996,28 @@ static int r128_cce_dispatch_write_pixels(struct drm_device * dev, count = depth->n; if (count > 4096 || count <= 0) - return DRM_ERR(EMSGSIZE); + return -EMSGSIZE; xbuf_size = count * sizeof(*x); ybuf_size = count * sizeof(*y); x = drm_alloc(xbuf_size, DRM_MEM_BUFS); if (x == NULL) { - return DRM_ERR(ENOMEM); + return -ENOMEM; } y = drm_alloc(ybuf_size, DRM_MEM_BUFS); if (y == NULL) { drm_free(x, xbuf_size, DRM_MEM_BUFS); - return DRM_ERR(ENOMEM); + return -ENOMEM; } if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) { drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); - return DRM_ERR(EFAULT); + return -EFAULT; } if (DRM_COPY_FROM_USER(y, depth->y, xbuf_size)) { drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); - return DRM_ERR(EFAULT); + return -EFAULT; } buffer_size = depth->n * sizeof(u32); @@ -1025,13 +1025,13 @@ static int r128_cce_dispatch_write_pixels(struct drm_device * dev, if (buffer == NULL) { drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); - return DRM_ERR(ENOMEM); + return -ENOMEM; } if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) { drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); drm_free(buffer, buffer_size, DRM_MEM_BUFS); - return DRM_ERR(EFAULT); + return -EFAULT; } if (depth->mask) { @@ -1041,14 +1041,14 @@ static int r128_cce_dispatch_write_pixels(struct drm_device * dev, drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); drm_free(buffer, buffer_size, DRM_MEM_BUFS); - return DRM_ERR(ENOMEM); + return -ENOMEM; } if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) { drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); drm_free(buffer, buffer_size, DRM_MEM_BUFS); drm_free(mask, mask_size, DRM_MEM_BUFS); - return DRM_ERR(EFAULT); + return -EFAULT; } for (i = 0; i < count; i++) { @@ -1115,13 +1115,13 @@ static int r128_cce_dispatch_read_span(struct drm_device * dev, count = depth->n; if (count > 4096 || count <= 0) - return DRM_ERR(EMSGSIZE); + return -EMSGSIZE; if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) { - return DRM_ERR(EFAULT); + return -EFAULT; } if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) { - return DRM_ERR(EFAULT); + return -EFAULT; } BEGIN_RING(7); @@ -1159,7 +1159,7 @@ static int r128_cce_dispatch_read_pixels(struct drm_device * dev, count = depth->n; if (count > 4096 || count <= 0) - return DRM_ERR(EMSGSIZE); + return -EMSGSIZE; if (count > dev_priv->depth_pitch) { count = dev_priv->depth_pitch; @@ -1169,22 +1169,22 @@ static int r128_cce_dispatch_read_pixels(struct drm_device * dev, ybuf_size = count * sizeof(*y); x = drm_alloc(xbuf_size, DRM_MEM_BUFS); if (x == NULL) { - return DRM_ERR(ENOMEM); + return -ENOMEM; } y = drm_alloc(ybuf_size, DRM_MEM_BUFS); if (y == NULL) { drm_free(x, xbuf_size, DRM_MEM_BUFS); - return DRM_ERR(ENOMEM); + return -ENOMEM; } if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) { drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); - return DRM_ERR(EFAULT); + return -EFAULT; } if (DRM_COPY_FROM_USER(y, depth->y, ybuf_size)) { drm_free(x, xbuf_size, DRM_MEM_BUFS); drm_free(y, ybuf_size, DRM_MEM_BUFS); - return DRM_ERR(EFAULT); + return -EFAULT; } for (i = 0; i < count; i++) { @@ -1363,7 +1363,7 @@ static int r128_cce_vertex(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(vertex, (drm_r128_vertex_t __user *) data, @@ -1375,12 +1375,12 @@ static int r128_cce_vertex(DRM_IOCTL_ARGS) if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", vertex.idx, dma->buf_count - 1); - return DRM_ERR(EINVAL); + return -EINVAL; } if (vertex.prim < 0 || vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { DRM_ERROR("buffer prim %d\n", vertex.prim); - return DRM_ERR(EINVAL); + return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); @@ -1392,11 +1392,11 @@ static int r128_cce_vertex(DRM_IOCTL_ARGS) if (buf->filp != filp) { DRM_ERROR("process %d using buffer owned by %p\n", DRM_CURRENTPID, buf->filp); - return DRM_ERR(EINVAL); + return -EINVAL; } if (buf->pending) { DRM_ERROR("sending pending buffer %d\n", vertex.idx); - return DRM_ERR(EINVAL); + return -EINVAL; } buf->used = vertex.count; @@ -1423,7 +1423,7 @@ static int r128_cce_indices(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(elts, (drm_r128_indices_t __user *) data, @@ -1435,11 +1435,11 @@ static int r128_cce_indices(DRM_IOCTL_ARGS) if (elts.idx < 0 || elts.idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", elts.idx, dma->buf_count - 1); - return DRM_ERR(EINVAL); + return -EINVAL; } if (elts.prim < 0 || elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { DRM_ERROR("buffer prim %d\n", elts.prim); - return DRM_ERR(EINVAL); + return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); @@ -1451,11 +1451,11 @@ static int r128_cce_indices(DRM_IOCTL_ARGS) if (buf->filp != filp) { DRM_ERROR("process %d using buffer owned by %p\n", DRM_CURRENTPID, buf->filp); - return DRM_ERR(EINVAL); + return -EINVAL; } if (buf->pending) { DRM_ERROR("sending pending buffer %d\n", elts.idx); - return DRM_ERR(EINVAL); + return -EINVAL; } count = (elts.end - elts.start) / sizeof(u16); @@ -1463,11 +1463,11 @@ static int r128_cce_indices(DRM_IOCTL_ARGS) if (elts.start & 0x7) { DRM_ERROR("misaligned buffer 0x%x\n", elts.start); - return DRM_ERR(EINVAL); + return -EINVAL; } if (elts.start < buf->used) { DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used); - return DRM_ERR(EINVAL); + return -EINVAL; } buf->used = elts.end; @@ -1498,7 +1498,7 @@ static int r128_cce_blit(DRM_IOCTL_ARGS) if (blit.idx < 0 || blit.idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", blit.idx, dma->buf_count - 1); - return DRM_ERR(EINVAL); + return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); @@ -1524,7 +1524,7 @@ static int r128_cce_depth(DRM_IOCTL_ARGS) RING_SPACE_TEST_WITH_RETURN(dev_priv); - ret = DRM_ERR(EINVAL); + ret = -EINVAL; switch (depth.func) { case R128_WRITE_SPAN: ret = r128_cce_dispatch_write_span(dev, &depth); @@ -1557,7 +1557,7 @@ static int r128_cce_stipple(DRM_IOCTL_ARGS) sizeof(stipple)); if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32))) - return DRM_ERR(EFAULT); + return -EFAULT; RING_SPACE_TEST_WITH_RETURN(dev_priv); @@ -1583,7 +1583,7 @@ static int r128_cce_indirect(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(indirect, (drm_r128_indirect_t __user *) data, @@ -1595,7 +1595,7 @@ static int r128_cce_indirect(DRM_IOCTL_ARGS) if (indirect.idx < 0 || indirect.idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", indirect.idx, dma->buf_count - 1); - return DRM_ERR(EINVAL); + return -EINVAL; } buf = dma->buflist[indirect.idx]; @@ -1604,17 +1604,17 @@ static int r128_cce_indirect(DRM_IOCTL_ARGS) if (buf->filp != filp) { DRM_ERROR("process %d using buffer owned by %p\n", DRM_CURRENTPID, buf->filp); - return DRM_ERR(EINVAL); + return -EINVAL; } if (buf->pending) { DRM_ERROR("sending pending buffer %d\n", indirect.idx); - return DRM_ERR(EINVAL); + return -EINVAL; } if (indirect.start < buf->used) { DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", indirect.start, buf->used); - return DRM_ERR(EINVAL); + return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); @@ -1651,7 +1651,7 @@ static int r128_getparam(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(param, (drm_r128_getparam_t __user *) data, @@ -1664,12 +1664,12 @@ static int r128_getparam(DRM_IOCTL_ARGS) value = dev->irq; break; default: - return DRM_ERR(EINVAL); + return -EINVAL; } if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { DRM_ERROR("copy_to_user\n"); - return DRM_ERR(EFAULT); + return -EFAULT; } return 0; diff --git a/shared-core/r300_cmdbuf.c b/shared-core/r300_cmdbuf.c index 9cf352ae..8fee22e9 100644 --- a/shared-core/r300_cmdbuf.c +++ b/shared-core/r300_cmdbuf.c @@ -74,7 +74,7 @@ static int r300_emit_cliprects(drm_radeon_private_t *dev_priv, if (DRM_COPY_FROM_USER_UNCHECKED (&box, &cmdbuf->boxes[n + i], sizeof(box))) { DRM_ERROR("copy cliprect faulted\n"); - return DRM_ERR(EFAULT); + return -EFAULT; } box.x1 = @@ -263,7 +263,7 @@ static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t * DRM_ERROR ("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n", reg, sz); - return DRM_ERR(EINVAL); + return -EINVAL; } for (i = 0; i < sz; i++) { values[i] = ((int *)cmdbuf->buf)[i]; @@ -275,13 +275,13 @@ static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t * DRM_ERROR ("Offset failed range check (reg=%04x sz=%d)\n", reg, sz); - return DRM_ERR(EINVAL); + return -EINVAL; } break; default: DRM_ERROR("Register %04x failed check as flag=%02x\n", reg + i * 4, r300_reg_flags[(reg >> 2) + i]); - return DRM_ERR(EINVAL); + return -EINVAL; } } @@ -317,12 +317,12 @@ static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv, return 0; if (sz * 4 > cmdbuf->bufsz) - return DRM_ERR(EINVAL); + return -EINVAL; if (reg + sz * 4 >= 0x10000) { DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg, sz); - return DRM_ERR(EINVAL); + return -EINVAL; } if (r300_check_range(reg, sz)) { @@ -362,7 +362,7 @@ static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv, if (!sz) return 0; if (sz * 16 > cmdbuf->bufsz) - return DRM_ERR(EINVAL); + return -EINVAL; BEGIN_RING(5 + sz * 4); /* Wait for VAP to come to senses.. */ @@ -391,7 +391,7 @@ static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv, RING_LOCALS; if (8 * 4 > cmdbuf->bufsz) - return DRM_ERR(EINVAL); + return -EINVAL; BEGIN_RING(10); OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); @@ -421,7 +421,7 @@ static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv, if ((count + 1) > MAX_ARRAY_PACKET) { DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", count); - return DRM_ERR(EINVAL); + return -EINVAL; } memset(payload, 0, MAX_ARRAY_PACKET * 4); memcpy(payload, cmdbuf->buf + 4, (count + 1) * 4); @@ -437,7 +437,7 @@ static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv, DRM_ERROR ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", k, i); - return DRM_ERR(EINVAL); + return -EINVAL; } k++; i++; @@ -448,7 +448,7 @@ static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv, DRM_ERROR ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", k, i); - return DRM_ERR(EINVAL); + return -EINVAL; } k++; i++; @@ -458,7 +458,7 @@ static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv, DRM_ERROR ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n", k, i, narrays, count + 1); - return DRM_ERR(EINVAL); + return -EINVAL; } /* all clear, output packet */ @@ -492,7 +492,7 @@ static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv, ret = !radeon_check_offset(dev_priv, offset); if (ret) { DRM_ERROR("Invalid bitblt first offset is %08X\n", offset); - return DRM_ERR(EINVAL); + return -EINVAL; } } @@ -502,7 +502,7 @@ static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv, ret = !radeon_check_offset(dev_priv, offset); if (ret) { DRM_ERROR("Invalid bitblt second offset is %08X\n", offset); - return DRM_ERR(EINVAL); + return -EINVAL; } } @@ -530,12 +530,12 @@ static __inline__ int r300_emit_indx_buffer(drm_radeon_private_t *dev_priv, if ((cmd[1] & 0x8000ffff) != 0x80000810) { DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]); - return DRM_ERR(EINVAL); + return -EINVAL; } ret = !radeon_check_offset(dev_priv, cmd[2]); if (ret) { DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]); - return DRM_ERR(EINVAL); + return -EINVAL; } BEGIN_RING(count+2); @@ -557,7 +557,7 @@ static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv, RING_LOCALS; if (4 > cmdbuf->bufsz) - return DRM_ERR(EINVAL); + return -EINVAL; /* Fixme !! This simply emits a packet without much checking. We need to be smarter. */ @@ -568,7 +568,7 @@ static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv, /* Is it packet 3 ? */ if ((header >> 30) != 0x3) { DRM_ERROR("Not a packet3 header (0x%08x)\n", header); - return DRM_ERR(EINVAL); + return -EINVAL; } count = (header >> 16) & 0x3fff; @@ -578,7 +578,7 @@ static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv, DRM_ERROR ("Expected packet3 of length %d but have only %d bytes left\n", (count + 2) * 4, cmdbuf->bufsz); - return DRM_ERR(EINVAL); + return -EINVAL; } /* Is it a packet type we know about ? */ @@ -600,7 +600,7 @@ static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv, break; default: DRM_ERROR("Unknown packet3 header (0x%08x)\n", header); - return DRM_ERR(EINVAL); + return -EINVAL; } BEGIN_RING(count + 2); @@ -664,7 +664,7 @@ static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv, DRM_ERROR("bad packet3 type %i at %p\n", header.packet3.packet, cmdbuf->buf - sizeof(header)); - return DRM_ERR(EINVAL); + return -EINVAL; } n += R300_SIMULTANEOUS_CLIPRECTS; @@ -725,11 +725,11 @@ static int r300_scratch(drm_radeon_private_t *dev_priv, RING_LOCALS; if (cmdbuf->bufsz < sizeof(uint64_t) + header.scratch.n_bufs * sizeof(buf_idx) ) { - return DRM_ERR(EINVAL); + return -EINVAL; } if (header.scratch.reg >= 5) { - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->scratch_ages[header.scratch.reg] ++; @@ -744,21 +744,21 @@ static int r300_scratch(drm_radeon_private_t *dev_priv, buf_idx *= 2; /* 8 bytes per buf */ if (DRM_COPY_TO_USER(ref_age_base + buf_idx, &dev_priv->scratch_ages[header.scratch.reg], sizeof(u32))) { - return DRM_ERR(EINVAL); + return -EINVAL; } if (DRM_COPY_FROM_USER(&h_pending, ref_age_base + buf_idx + 1, sizeof(u32))) { - return DRM_ERR(EINVAL); + return -EINVAL; } if (h_pending == 0) { - return DRM_ERR(EINVAL); + return -EINVAL; } h_pending--; if (DRM_COPY_TO_USER(ref_age_base + buf_idx + 1, &h_pending, sizeof(u32))) { - return DRM_ERR(EINVAL); + return -EINVAL; } cmdbuf->buf += sizeof(buf_idx); @@ -878,7 +878,7 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, if (idx < 0 || idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", idx, dma->buf_count - 1); - ret = DRM_ERR(EINVAL); + ret = -EINVAL; goto cleanup; } @@ -886,7 +886,7 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, if (buf->filp != filp || buf->pending) { DRM_ERROR("bad buffer %p %p %d\n", buf->filp, filp, buf->pending); - ret = DRM_ERR(EINVAL); + ret = -EINVAL; goto cleanup; } @@ -923,7 +923,7 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, DRM_ERROR("bad cmd_type %i at %p\n", header.header.cmd_type, cmdbuf->buf - sizeof(header)); - ret = DRM_ERR(EINVAL); + ret = -EINVAL; goto cleanup; } } diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 40a20e6c..723d41c3 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -889,7 +889,7 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) DRM_ERROR("failed!\n"); radeon_status(dev_priv); #endif - return DRM_ERR(EBUSY); + return -EBUSY; } static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) @@ -910,7 +910,7 @@ static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) DRM_ERROR("failed!\n"); radeon_status(dev_priv); #endif - return DRM_ERR(EBUSY); + return -EBUSY; } static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) @@ -936,7 +936,7 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) DRM_ERROR("failed!\n"); radeon_status(dev_priv); #endif - return DRM_ERR(EBUSY); + return -EBUSY; } /* ================================================================ @@ -1400,7 +1400,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) @@ -1418,7 +1418,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) { DRM_ERROR("PCI GART memory not allocated!\n"); radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->usec_timeout = init->usec_timeout; @@ -1426,7 +1426,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { DRM_DEBUG("TIMEOUT problem!\n"); radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } /* Enable vblank on CRTC1 for older X servers @@ -1455,7 +1455,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } switch (init->fb_bpp) { @@ -1524,27 +1524,27 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) if (!dev_priv->sarea) { DRM_ERROR("could not find sarea!\n"); radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); if (!dev_priv->cp_ring) { DRM_ERROR("could not find cp ring region!\n"); radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); if (!dev_priv->ring_rptr) { DRM_ERROR("could not find ring read pointer!\n"); radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } dev->agp_buffer_token = init->buffers_offset; dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); if (!dev->agp_buffer_map) { DRM_ERROR("could not find dma buffer region!\n"); radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } if (init->gart_textures_offset) { @@ -1553,7 +1553,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) if (!dev_priv->gart_textures) { DRM_ERROR("could not find GART texture region!\n"); radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } } @@ -1571,7 +1571,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) !dev->agp_buffer_map->handle) { DRM_ERROR("could not find ioremap agp regions!\n"); radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } } else #endif @@ -1725,14 +1725,14 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) DRM_ERROR ("Cannot use PCI Express without GART in FB memory\n"); radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } } if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { DRM_ERROR("failed to init PCI GART!\n"); radeon_do_cleanup_cp(dev); - return DRM_ERR(ENOMEM); + return -ENOMEM; } /* Turn on PCI GART */ @@ -1812,7 +1812,7 @@ static int radeon_do_resume_cp(struct drm_device * dev) if (!dev_priv) { DRM_ERROR("Called with no initialization\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_DEBUG("Starting radeon_do_resume_cp()\n"); @@ -1860,7 +1860,7 @@ int radeon_cp_init(DRM_IOCTL_ARGS) return radeon_do_cleanup_cp(dev); } - return DRM_ERR(EINVAL); + return -EINVAL; } int radeon_cp_start(DRM_IOCTL_ARGS) @@ -1993,7 +1993,7 @@ int radeon_cp_reset(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_DEBUG("%s called before init done\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } radeon_do_cp_reset(dev_priv); @@ -2187,7 +2187,7 @@ int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) radeon_status(dev_priv); DRM_ERROR("failed!\n"); #endif - return DRM_ERR(EBUSY); + return -EBUSY; } static int radeon_cp_get_buffers(DRMFILE filp, struct drm_device * dev, @@ -2199,16 +2199,16 @@ static int radeon_cp_get_buffers(DRMFILE filp, struct drm_device * dev, for (i = d->granted_count; i < d->request_count; i++) { buf = radeon_freelist_get(dev); if (!buf) - return DRM_ERR(EBUSY); /* NOTE: broken client */ + return -EBUSY; /* NOTE: broken client */ buf->filp = filp; if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, sizeof(buf->idx))) - return DRM_ERR(EFAULT); + return -EFAULT; if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, sizeof(buf->total))) - return DRM_ERR(EFAULT); + return -EFAULT; d->granted_count++; } @@ -2232,7 +2232,7 @@ int radeon_cp_buffers(DRM_IOCTL_ARGS) if (d.send_count != 0) { DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", DRM_CURRENTPID, d.send_count); - return DRM_ERR(EINVAL); + return -EINVAL; } /* We'll send you buffers. @@ -2240,7 +2240,7 @@ int radeon_cp_buffers(DRM_IOCTL_ARGS) if (d.request_count < 0 || d.request_count > dma->buf_count) { DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", DRM_CURRENTPID, d.request_count, dma->buf_count); - return DRM_ERR(EINVAL); + return -EINVAL; } d.granted_count = 0; @@ -2261,7 +2261,7 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags) dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); if (dev_priv == NULL) - return DRM_ERR(ENOMEM); + return -ENOMEM; memset(dev_priv, 0, sizeof(drm_radeon_private_t)); dev->dev_private = (void *)dev_priv; diff --git a/shared-core/radeon_irq.c b/shared-core/radeon_irq.c index b973b968..8266d11a 100644 --- a/shared-core/radeon_irq.c +++ b/shared-core/radeon_irq.c @@ -156,7 +156,7 @@ static int radeon_driver_vblank_do_wait(struct drm_device * dev, atomic_t *counter; if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } if (crtc == DRM_RADEON_VBLANK_CRTC1) { @@ -166,7 +166,7 @@ static int radeon_driver_vblank_do_wait(struct drm_device * dev, counter = &dev->vbl_received2; ack |= RADEON_CRTC2_VBLANK_STAT; } else - return DRM_ERR(EINVAL); + return -EINVAL; radeon_acknowledge_irqs(dev_priv, ack); @@ -208,7 +208,7 @@ int radeon_irq_emit(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(emit, (drm_radeon_irq_emit_t __user *) data, @@ -218,7 +218,7 @@ int radeon_irq_emit(DRM_IOCTL_ARGS) if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) { DRM_ERROR("copy_to_user\n"); - return DRM_ERR(EFAULT); + return -EFAULT; } return 0; @@ -234,7 +234,7 @@ int radeon_irq_wait(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(irqwait, (drm_radeon_irq_wait_t __user *) data, @@ -321,7 +321,7 @@ int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value) drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) { DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->vblank_crtc = (unsigned int)value; radeon_enable_interrupt(dev); diff --git a/shared-core/radeon_mem.c b/shared-core/radeon_mem.c index dbc91c9f..63d4b8c9 100644 --- a/shared-core/radeon_mem.c +++ b/shared-core/radeon_mem.c @@ -137,12 +137,12 @@ static int init_heap(struct mem_block **heap, int start, int size) struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFS); if (!blocks) - return DRM_ERR(ENOMEM); + return -ENOMEM; *heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFS); if (!*heap) { drm_free(blocks, sizeof(*blocks), DRM_MEM_BUFS); - return DRM_ERR(ENOMEM); + return -ENOMEM; } blocks->start = start; @@ -226,7 +226,7 @@ int radeon_mem_alloc(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(alloc, (drm_radeon_mem_alloc_t __user *) data, @@ -234,7 +234,7 @@ int radeon_mem_alloc(DRM_IOCTL_ARGS) heap = get_heap(dev_priv, alloc.region); if (!heap || !*heap) - return DRM_ERR(EFAULT); + return -EFAULT; /* Make things easier on ourselves: all allocations at least * 4k aligned. @@ -245,11 +245,11 @@ int radeon_mem_alloc(DRM_IOCTL_ARGS) block = alloc_block(*heap, alloc.size, alloc.alignment, filp); if (!block) - return DRM_ERR(ENOMEM); + return -ENOMEM; if (DRM_COPY_TO_USER(alloc.region_offset, &block->start, sizeof(int))) { DRM_ERROR("copy_to_user\n"); - return DRM_ERR(EFAULT); + return -EFAULT; } return 0; @@ -264,7 +264,7 @@ int radeon_mem_free(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_mem_free_t __user *) data, @@ -272,14 +272,14 @@ int radeon_mem_free(DRM_IOCTL_ARGS) heap = get_heap(dev_priv, memfree.region); if (!heap || !*heap) - return DRM_ERR(EFAULT); + return -EFAULT; block = find_block(*heap, memfree.region_offset); if (!block) - return DRM_ERR(EFAULT); + return -EFAULT; if (block->filp != filp) - return DRM_ERR(EPERM); + return -EPERM; free_block(block); return 0; @@ -294,7 +294,7 @@ int radeon_mem_init_heap(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(initheap, @@ -303,11 +303,11 @@ int radeon_mem_init_heap(DRM_IOCTL_ARGS) heap = get_heap(dev_priv, initheap.region); if (!heap) - return DRM_ERR(EFAULT); + return -EFAULT; if (*heap) { DRM_ERROR("heap already initialized?"); - return DRM_ERR(EFAULT); + return -EFAULT; } return init_heap(heap, initheap.start, initheap.size); diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c index 13b09d44..e351656d 100644 --- a/shared-core/radeon_state.c +++ b/shared-core/radeon_state.c @@ -85,7 +85,7 @@ static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t * *offset = off; return 0; } - return DRM_ERR(EINVAL); + return -EINVAL; } static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * @@ -99,7 +99,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) { DRM_ERROR("Invalid depth buffer offset\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } break; @@ -107,7 +107,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) { DRM_ERROR("Invalid colour buffer offset\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } break; @@ -120,7 +120,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &data[0])) { DRM_ERROR("Invalid R200 texture offset\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } break; @@ -130,7 +130,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) { DRM_ERROR("Invalid R100 texture offset\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } break; @@ -147,7 +147,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * &data[i])) { DRM_ERROR ("Invalid R200 cubic texture offset\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } } break; @@ -163,7 +163,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * &data[i])) { DRM_ERROR ("Invalid R100 cubic texture offset\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } } } @@ -256,7 +256,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * default: DRM_ERROR("Unknown state packet ID %d\n", id); - return DRM_ERR(EINVAL); + return -EINVAL; } return 0; @@ -277,12 +277,12 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) { DRM_ERROR("Not a type 3 packet\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } if (4 * *cmdsz > cmdbuf->bufsz) { DRM_ERROR("Packet size larger than size of data provided\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } switch(cmd[0] & 0xff00) { @@ -307,7 +307,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * /* safe but r200 only */ if (dev_priv->microcode_version != UCODE_R200) { DRM_ERROR("Invalid 3d packet for r100-class chip\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } break; @@ -317,7 +317,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * if (count > 18) { /* 12 arrays max */ DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", count); - return DRM_ERR(EINVAL); + return -EINVAL; } /* carefully check packet contents */ @@ -330,7 +330,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * DRM_ERROR ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n", k, i); - return DRM_ERR(EINVAL); + return -EINVAL; } k++; i++; @@ -341,7 +341,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * DRM_ERROR ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n", k, i); - return DRM_ERR(EINVAL); + return -EINVAL; } k++; i++; @@ -351,33 +351,33 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * DRM_ERROR ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n", k, i, narrays, count + 1); - return DRM_ERR(EINVAL); + return -EINVAL; } break; case RADEON_3D_RNDR_GEN_INDX_PRIM: if (dev_priv->microcode_version != UCODE_R100) { DRM_ERROR("Invalid 3d packet for r200-class chip\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[1])) { DRM_ERROR("Invalid rndr_gen_indx offset\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } break; case RADEON_CP_INDX_BUFFER: if (dev_priv->microcode_version != UCODE_R200) { DRM_ERROR("Invalid 3d packet for r100-class chip\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } if ((cmd[1] & 0x8000ffff) != 0x80000810) { DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]); - return DRM_ERR(EINVAL); + return -EINVAL; } if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[2])) { DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]); - return DRM_ERR(EINVAL); + return -EINVAL; } break; @@ -391,7 +391,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * if (radeon_check_and_fixup_offset (dev_priv, filp_priv, &offset)) { DRM_ERROR("Invalid first packet offset\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } cmd[2] = (cmd[2] & 0xffc00000) | offset >> 10; } @@ -402,7 +402,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * if (radeon_check_and_fixup_offset (dev_priv, filp_priv, &offset)) { DRM_ERROR("Invalid second packet offset\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } cmd[3] = (cmd[3] & 0xffc00000) | offset >> 10; } @@ -410,7 +410,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * default: DRM_ERROR("Invalid packet type %x\n", cmd[0] & 0xff00); - return DRM_ERR(EINVAL); + return -EINVAL; } return 0; @@ -451,13 +451,13 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv, if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &ctx->rb3d_depthoffset)) { DRM_ERROR("Invalid depth buffer offset\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &ctx->rb3d_coloroffset)) { DRM_ERROR("Invalid depth buffer offset\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } BEGIN_RING(14); @@ -546,7 +546,7 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv, if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex[0].pp_txoffset)) { DRM_ERROR("Invalid texture offset for unit 0\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } BEGIN_RING(9); @@ -566,7 +566,7 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv, if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex[1].pp_txoffset)) { DRM_ERROR("Invalid texture offset for unit 1\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } BEGIN_RING(9); @@ -586,7 +586,7 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv, if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex[2].pp_txoffset)) { DRM_ERROR("Invalid texture offset for unit 2\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } BEGIN_RING(9); @@ -1668,7 +1668,7 @@ static int radeon_cp_dispatch_texture(DRMFILE filp, if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex->offset)) { DRM_ERROR("Invalid destination offset\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD; @@ -1711,11 +1711,11 @@ static int radeon_cp_dispatch_texture(DRMFILE filp, break; default: DRM_ERROR("invalid texture format %d\n", tex->format); - return DRM_ERR(EINVAL); + return -EINVAL; } spitch = blit_width >> 6; if (spitch == 0 && image->height > 1) - return DRM_ERR(EINVAL); + return -EINVAL; texpitch = tex->pitch; if ((texpitch << 22) & RADEON_DST_TILE_MICRO) { @@ -1760,8 +1760,8 @@ static int radeon_cp_dispatch_texture(DRMFILE filp, if (!buf) { DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n"); if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) - return DRM_ERR(EFAULT); - return DRM_ERR(EAGAIN); + return -EFAULT; + return -EAGAIN; } /* Dispatch the indirect buffer. @@ -1774,7 +1774,7 @@ static int radeon_cp_dispatch_texture(DRMFILE filp, do { \ if (DRM_COPY_FROM_USER(_buf, _data, (_width))) {\ DRM_ERROR("EFAULT on pad, %d bytes\n", (_width)); \ - return DRM_ERR(EFAULT); \ + return -EFAULT; \ } \ } while(0) @@ -2080,7 +2080,7 @@ static int radeon_surface_alloc(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(alloc, @@ -2088,7 +2088,7 @@ static int radeon_surface_alloc(DRM_IOCTL_ARGS) sizeof(alloc)); if (alloc_surface(&alloc, dev_priv, filp) == -1) - return DRM_ERR(EINVAL); + return -EINVAL; else return 0; } @@ -2101,14 +2101,14 @@ static int radeon_surface_free(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_surface_free_t __user *) data, sizeof(memfree)); if (free_surface(filp, dev_priv, memfree.address)) - return DRM_ERR(EINVAL); + return -EINVAL; else return 0; } @@ -2134,7 +2134,7 @@ static int radeon_cp_clear(DRM_IOCTL_ARGS) if (DRM_COPY_FROM_USER(&depth_boxes, clear.depth_boxes, sarea_priv->nbox * sizeof(depth_boxes[0]))) - return DRM_ERR(EFAULT); + return -EFAULT; radeon_cp_dispatch_clear(dev, &clear, depth_boxes); @@ -2227,7 +2227,7 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } sarea_priv = dev_priv->sarea_priv; @@ -2243,11 +2243,11 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", vertex.idx, dma->buf_count - 1); - return DRM_ERR(EINVAL); + return -EINVAL; } if (vertex.prim < 0 || vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { DRM_ERROR("buffer prim %d\n", vertex.prim); - return DRM_ERR(EINVAL); + return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); @@ -2258,11 +2258,11 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) if (buf->filp != filp) { DRM_ERROR("process %d using buffer owned by %p\n", DRM_CURRENTPID, buf->filp); - return DRM_ERR(EINVAL); + return -EINVAL; } if (buf->pending) { DRM_ERROR("sending pending buffer %d\n", vertex.idx); - return DRM_ERR(EINVAL); + return -EINVAL; } /* Build up a prim_t record: @@ -2276,7 +2276,7 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) sarea_priv->tex_state, sarea_priv->dirty)) { DRM_ERROR("radeon_emit_state failed\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | @@ -2318,7 +2318,7 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } sarea_priv = dev_priv->sarea_priv; @@ -2333,11 +2333,11 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) if (elts.idx < 0 || elts.idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", elts.idx, dma->buf_count - 1); - return DRM_ERR(EINVAL); + return -EINVAL; } if (elts.prim < 0 || elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { DRM_ERROR("buffer prim %d\n", elts.prim); - return DRM_ERR(EINVAL); + return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); @@ -2348,11 +2348,11 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) if (buf->filp != filp) { DRM_ERROR("process %d using buffer owned by %p\n", DRM_CURRENTPID, buf->filp); - return DRM_ERR(EINVAL); + return -EINVAL; } if (buf->pending) { DRM_ERROR("sending pending buffer %d\n", elts.idx); - return DRM_ERR(EINVAL); + return -EINVAL; } count = (elts.end - elts.start) / sizeof(u16); @@ -2360,11 +2360,11 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) if (elts.start & 0x7) { DRM_ERROR("misaligned buffer 0x%x\n", elts.start); - return DRM_ERR(EINVAL); + return -EINVAL; } if (elts.start < buf->used) { DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used); - return DRM_ERR(EINVAL); + return -EINVAL; } buf->used = elts.end; @@ -2375,7 +2375,7 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) sarea_priv->tex_state, sarea_priv->dirty)) { DRM_ERROR("radeon_emit_state failed\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | @@ -2417,13 +2417,13 @@ static int radeon_cp_texture(DRM_IOCTL_ARGS) if (tex.image == NULL) { DRM_ERROR("null texture image!\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } if (DRM_COPY_FROM_USER(&image, (drm_radeon_tex_image_t __user *) tex.image, sizeof(image))) - return DRM_ERR(EFAULT); + return -EFAULT; RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); @@ -2447,7 +2447,7 @@ static int radeon_cp_stipple(DRM_IOCTL_ARGS) sizeof(stipple)); if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32))) - return DRM_ERR(EFAULT); + return -EFAULT; RING_SPACE_TEST_WITH_RETURN(dev_priv); @@ -2470,7 +2470,7 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(indirect, @@ -2483,7 +2483,7 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS) if (indirect.idx < 0 || indirect.idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", indirect.idx, dma->buf_count - 1); - return DRM_ERR(EINVAL); + return -EINVAL; } buf = dma->buflist[indirect.idx]; @@ -2491,17 +2491,17 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS) if (buf->filp != filp) { DRM_ERROR("process %d using buffer owned by %p\n", DRM_CURRENTPID, buf->filp); - return DRM_ERR(EINVAL); + return -EINVAL; } if (buf->pending) { DRM_ERROR("sending pending buffer %d\n", indirect.idx); - return DRM_ERR(EINVAL); + return -EINVAL; } if (indirect.start < buf->used) { DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", indirect.start, buf->used); - return DRM_ERR(EINVAL); + return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); @@ -2547,7 +2547,7 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } sarea_priv = dev_priv->sarea_priv; @@ -2563,7 +2563,7 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", vertex.idx, dma->buf_count - 1); - return DRM_ERR(EINVAL); + return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); @@ -2574,23 +2574,23 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) if (buf->filp != filp) { DRM_ERROR("process %d using buffer owned by %p\n", DRM_CURRENTPID, buf->filp); - return DRM_ERR(EINVAL); + return -EINVAL; } if (buf->pending) { DRM_ERROR("sending pending buffer %d\n", vertex.idx); - return DRM_ERR(EINVAL); + return -EINVAL; } if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) - return DRM_ERR(EINVAL); + return -EINVAL; for (laststate = 0xff, i = 0; i < vertex.nr_prims; i++) { drm_radeon_prim_t prim; drm_radeon_tcl_prim_t tclprim; if (DRM_COPY_FROM_USER(&prim, &vertex.prim[i], sizeof(prim))) - return DRM_ERR(EFAULT); + return -EFAULT; if (prim.stateidx != laststate) { drm_radeon_state_t state; @@ -2598,11 +2598,11 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) if (DRM_COPY_FROM_USER(&state, &vertex.state[prim.stateidx], sizeof(state))) - return DRM_ERR(EFAULT); + return -EFAULT; if (radeon_emit_state2(dev_priv, filp_priv, &state)) { DRM_ERROR("radeon_emit_state2 failed\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } laststate = prim.stateidx; @@ -2648,19 +2648,19 @@ static int radeon_emit_packets(drm_radeon_private_t * dev_priv, RING_LOCALS; if (id >= RADEON_MAX_STATE_PACKETS) - return DRM_ERR(EINVAL); + return -EINVAL; sz = packet[id].len; reg = packet[id].start; if (sz * sizeof(int) > cmdbuf->bufsz) { DRM_ERROR("Packet size provided larger than data provided\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } if (radeon_check_and_fixup_packets(dev_priv, filp_priv, id, data)) { DRM_ERROR("Packet verification failed\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } BEGIN_RING(sz + 1); @@ -2748,7 +2748,7 @@ static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv, if (!sz) return 0; if (sz * 4 > cmdbuf->bufsz) - return DRM_ERR(EINVAL); + return -EINVAL; BEGIN_RING(5 + sz); OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0); @@ -2816,7 +2816,7 @@ static int radeon_emit_packet3_cliprect(struct drm_device *dev, do { if (i < cmdbuf->nbox) { if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box))) - return DRM_ERR(EFAULT); + return -EFAULT; /* FIXME The second and subsequent times round * this loop, send a WAIT_UNTIL_3D_IDLE before * calling emit_clip_rect(). This fixes a @@ -2874,7 +2874,7 @@ static int radeon_emit_wait(struct drm_device * dev, int flags) ADVANCE_RING(); break; default: - return DRM_ERR(EINVAL); + return -EINVAL; } return 0; @@ -2897,7 +2897,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); @@ -2910,7 +2910,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) VB_AGE_TEST_WITH_RETURN(dev_priv); if (cmdbuf.bufsz > 64 * 1024 || cmdbuf.bufsz < 0) { - return DRM_ERR(EINVAL); + return -EINVAL; } /* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid @@ -2921,11 +2921,11 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) if (orig_bufsz != 0) { kbuf = drm_alloc(cmdbuf.bufsz, DRM_MEM_DRIVER); if (kbuf == NULL) - return DRM_ERR(ENOMEM); + return -ENOMEM; if (DRM_COPY_FROM_USER(kbuf, (void __user *)cmdbuf.buf, cmdbuf.bufsz)) { drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); - return DRM_ERR(EFAULT); + return -EFAULT; } cmdbuf.buf = kbuf; } @@ -3052,7 +3052,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) err: if (orig_bufsz != 0) drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); - return DRM_ERR(EINVAL); + return -EINVAL; } static int radeon_cp_getparam(DRM_IOCTL_ARGS) @@ -3064,7 +3064,7 @@ static int radeon_cp_getparam(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_COPY_FROM_USER_IOCTL(param, (drm_radeon_getparam_t __user *) data, @@ -3119,7 +3119,7 @@ static int radeon_cp_getparam(DRM_IOCTL_ARGS) break; case RADEON_PARAM_SCRATCH_OFFSET: if (!dev_priv->writeback_works) - return DRM_ERR(EINVAL); + return -EINVAL; value = RADEON_SCRATCH_REG_OFFSET; break; @@ -3136,12 +3136,12 @@ static int radeon_cp_getparam(DRM_IOCTL_ARGS) break; default: DRM_DEBUG( "Invalid parameter %d\n", param.param ); - return DRM_ERR(EINVAL); + return -EINVAL; } if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { DRM_ERROR("copy_to_user\n"); - return DRM_ERR(EFAULT); + return -EFAULT; } return 0; @@ -3157,7 +3157,7 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS) if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); @@ -3200,7 +3200,7 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS) break; default: DRM_DEBUG("Invalid parameter %d\n", sp.param); - return DRM_ERR(EINVAL); + return -EINVAL; } return 0; diff --git a/shared-core/savage_bci.c b/shared-core/savage_bci.c index a3fd8994..1835d758 100644 --- a/shared-core/savage_bci.c +++ b/shared-core/savage_bci.c @@ -60,7 +60,7 @@ savage_bci_wait_fifo_shadow(drm_savage_private_t *dev_priv, unsigned int n) DRM_ERROR("failed!\n"); DRM_INFO(" status=0x%08x, threshold=0x%08x\n", status, threshold); #endif - return DRM_ERR(EBUSY); + return -EBUSY; } static int @@ -81,7 +81,7 @@ savage_bci_wait_fifo_s3d(drm_savage_private_t *dev_priv, unsigned int n) DRM_ERROR("failed!\n"); DRM_INFO(" status=0x%08x\n", status); #endif - return DRM_ERR(EBUSY); + return -EBUSY; } static int @@ -102,7 +102,7 @@ savage_bci_wait_fifo_s4(drm_savage_private_t *dev_priv, unsigned int n) DRM_ERROR("failed!\n"); DRM_INFO(" status=0x%08x\n", status); #endif - return DRM_ERR(EBUSY); + return -EBUSY; } /* @@ -136,7 +136,7 @@ savage_bci_wait_event_shadow(drm_savage_private_t *dev_priv, uint16_t e) DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e); #endif - return DRM_ERR(EBUSY); + return -EBUSY; } static int @@ -158,7 +158,7 @@ savage_bci_wait_event_reg(drm_savage_private_t *dev_priv, uint16_t e) DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e); #endif - return DRM_ERR(EBUSY); + return -EBUSY; } uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, @@ -301,7 +301,7 @@ static int savage_dma_init(drm_savage_private_t *dev_priv) dev_priv->dma_pages = drm_alloc(sizeof(drm_savage_dma_page_t) * dev_priv->nr_dma_pages, DRM_MEM_DRIVER); if (dev_priv->dma_pages == NULL) - return DRM_ERR(ENOMEM); + return -ENOMEM; for (i = 0; i < dev_priv->nr_dma_pages; ++i) { SET_AGE(&dev_priv->dma_pages[i].age, 0, 0); @@ -541,7 +541,7 @@ int savage_driver_load(struct drm_device *dev, unsigned long chipset) dev_priv = drm_alloc(sizeof(drm_savage_private_t), DRM_MEM_DRIVER); if (dev_priv == NULL) - return DRM_ERR(ENOMEM); + return -ENOMEM; memset(dev_priv, 0, sizeof(drm_savage_private_t)); dev->dev_private = (void *)dev_priv; @@ -681,16 +681,16 @@ static int savage_do_init_bci(struct drm_device *dev, drm_savage_init_t *init) if (init->fb_bpp != 16 && init->fb_bpp != 32) { DRM_ERROR("invalid frame buffer bpp %d!\n", init->fb_bpp); - return DRM_ERR(EINVAL); + return -EINVAL; } if (init->depth_bpp != 16 && init->depth_bpp != 32) { DRM_ERROR("invalid depth buffer bpp %d!\n", init->fb_bpp); - return DRM_ERR(EINVAL); + return -EINVAL; } if (init->dma_type != SAVAGE_DMA_AGP && init->dma_type != SAVAGE_DMA_PCI) { DRM_ERROR("invalid dma memory type %d!\n", init->dma_type); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->cob_size = init->cob_size; @@ -714,14 +714,14 @@ static int savage_do_init_bci(struct drm_device *dev, drm_savage_init_t *init) if (!dev_priv->sarea) { DRM_ERROR("could not find sarea!\n"); savage_do_cleanup_bci(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } if (init->status_offset != 0) { dev_priv->status = drm_core_findmap(dev, init->status_offset); if (!dev_priv->status) { DRM_ERROR("could not find shadow status region!\n"); savage_do_cleanup_bci(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } } else { dev_priv->status = NULL; @@ -733,13 +733,13 @@ static int savage_do_init_bci(struct drm_device *dev, drm_savage_init_t *init) if (!dev->agp_buffer_map) { DRM_ERROR("could not find DMA buffer region!\n"); savage_do_cleanup_bci(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } drm_core_ioremap(dev->agp_buffer_map, dev); if (!dev->agp_buffer_map) { DRM_ERROR("failed to ioremap DMA buffer region!\n"); savage_do_cleanup_bci(dev); - return DRM_ERR(ENOMEM); + return -ENOMEM; } } if (init->agp_textures_offset) { @@ -748,7 +748,7 @@ static int savage_do_init_bci(struct drm_device *dev, drm_savage_init_t *init) if (!dev_priv->agp_textures) { DRM_ERROR("could not find agp texture region!\n"); savage_do_cleanup_bci(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } } else { dev_priv->agp_textures = NULL; @@ -759,39 +759,39 @@ static int savage_do_init_bci(struct drm_device *dev, drm_savage_init_t *init) DRM_ERROR("command DMA not supported on " "Savage3D/MX/IX.\n"); savage_do_cleanup_bci(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } if (dev->dma && dev->dma->buflist) { DRM_ERROR("command and vertex DMA not supported " "at the same time.\n"); savage_do_cleanup_bci(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->cmd_dma = drm_core_findmap(dev, init->cmd_dma_offset); if (!dev_priv->cmd_dma) { DRM_ERROR("could not find command DMA region!\n"); savage_do_cleanup_bci(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } if (dev_priv->dma_type == SAVAGE_DMA_AGP) { if (dev_priv->cmd_dma->type != _DRM_AGP) { DRM_ERROR("AGP command DMA region is not a " "_DRM_AGP map!\n"); savage_do_cleanup_bci(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } drm_core_ioremap(dev_priv->cmd_dma, dev); if (!dev_priv->cmd_dma->handle) { DRM_ERROR("failed to ioremap command " "DMA region!\n"); savage_do_cleanup_bci(dev); - return DRM_ERR(ENOMEM); + return -ENOMEM; } } else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) { DRM_ERROR("PCI command DMA region is not a " "_DRM_CONSISTENT map!\n"); savage_do_cleanup_bci(dev); - return DRM_ERR(EINVAL); + return -EINVAL; } } else { dev_priv->cmd_dma = NULL; @@ -808,7 +808,7 @@ static int savage_do_init_bci(struct drm_device *dev, drm_savage_init_t *init) if (!dev_priv->fake_dma.handle) { DRM_ERROR("could not allocate faked DMA buffer!\n"); savage_do_cleanup_bci(dev); - return DRM_ERR(ENOMEM); + return -ENOMEM; } dev_priv->cmd_dma = &dev_priv->fake_dma; dev_priv->dma_flush = savage_fake_dma_flush; @@ -885,13 +885,13 @@ static int savage_do_init_bci(struct drm_device *dev, drm_savage_init_t *init) if (savage_freelist_init(dev) < 0) { DRM_ERROR("could not initialize freelist\n"); savage_do_cleanup_bci(dev); - return DRM_ERR(ENOMEM); + return -ENOMEM; } if (savage_dma_init(dev_priv) < 0) { DRM_ERROR("could not initialize command DMA\n"); savage_do_cleanup_bci(dev); - return DRM_ERR(ENOMEM); + return -ENOMEM; } return 0; @@ -944,7 +944,7 @@ static int savage_bci_init(DRM_IOCTL_ARGS) return savage_do_cleanup_bci(dev); } - return DRM_ERR(EINVAL); + return -EINVAL; } static int savage_bci_event_emit(DRM_IOCTL_ARGS) @@ -1014,16 +1014,16 @@ static int savage_bci_get_buffers(DRMFILE filp, struct drm_device *dev, struct d for (i = d->granted_count; i < d->request_count; i++) { buf = savage_freelist_get(dev); if (!buf) - return DRM_ERR(EAGAIN); + return -EAGAIN; buf->filp = filp; if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, sizeof(buf->idx))) - return DRM_ERR(EFAULT); + return -EFAULT; if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, sizeof(buf->total))) - return DRM_ERR(EFAULT); + return -EFAULT; d->granted_count++; } @@ -1046,7 +1046,7 @@ int savage_bci_buffers(DRM_IOCTL_ARGS) if (d.send_count != 0) { DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", DRM_CURRENTPID, d.send_count); - return DRM_ERR(EINVAL); + return -EINVAL; } /* We'll send you buffers. @@ -1054,7 +1054,7 @@ int savage_bci_buffers(DRM_IOCTL_ARGS) if (d.request_count < 0 || d.request_count > dma->buf_count) { DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", DRM_CURRENTPID, d.request_count, dma->buf_count); - return DRM_ERR(EINVAL); + return -EINVAL; } d.granted_count = 0; diff --git a/shared-core/savage_state.c b/shared-core/savage_state.c index 290796ee..753fe7d3 100644 --- a/shared-core/savage_state.c +++ b/shared-core/savage_state.c @@ -83,7 +83,7 @@ static int savage_verify_texaddr(drm_savage_private_t *dev_priv, int unit, { if ((addr & 6) != 2) { /* reserved bits */ DRM_ERROR("bad texAddr%d %08x (reserved bits)\n", unit, addr); - return DRM_ERR(EINVAL); + return -EINVAL; } if (!(addr & 1)) { /* local */ addr &= ~7; @@ -92,13 +92,13 @@ static int savage_verify_texaddr(drm_savage_private_t *dev_priv, int unit, DRM_ERROR ("bad texAddr%d %08x (local addr out of range)\n", unit, addr); - return DRM_ERR(EINVAL); + return -EINVAL; } } else { /* AGP */ if (!dev_priv->agp_textures) { DRM_ERROR("bad texAddr%d %08x (AGP not available)\n", unit, addr); - return DRM_ERR(EINVAL); + return -EINVAL; } addr &= ~7; if (addr < dev_priv->agp_textures->offset || @@ -107,7 +107,7 @@ static int savage_verify_texaddr(drm_savage_private_t *dev_priv, int unit, DRM_ERROR ("bad texAddr%d %08x (AGP addr out of range)\n", unit, addr); - return DRM_ERR(EINVAL); + return -EINVAL; } } return 0; @@ -132,7 +132,7 @@ static int savage_verify_state_s3d(drm_savage_private_t *dev_priv, start+count-1 > SAVAGE_DESTTEXRWWATERMARK_S3D) { DRM_ERROR("invalid register range (0x%04x-0x%04x)\n", start, start+count-1); - return DRM_ERR(EINVAL); + return -EINVAL; } SAVE_STATE_MASK(SAVAGE_SCSTART_S3D, s3d.new_scstart, @@ -164,7 +164,7 @@ static int savage_verify_state_s4(drm_savage_private_t *dev_priv, start+count-1 > SAVAGE_TEXBLENDCOLOR_S4) { DRM_ERROR("invalid register range (0x%04x-0x%04x)\n", start, start+count-1); - return DRM_ERR(EINVAL); + return -EINVAL; } SAVE_STATE_MASK(SAVAGE_DRAWCTRL0_S4, s4.new_drawctrl0, @@ -287,7 +287,7 @@ static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv, if (!dmabuf) { DRM_ERROR("called without dma buffers!\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } if (!n) @@ -301,7 +301,7 @@ static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv, if (n % 3 != 0) { DRM_ERROR("wrong number of vertices %u in TRILIST\n", n); - return DRM_ERR(EINVAL); + return -EINVAL; } break; case SAVAGE_PRIM_TRISTRIP: @@ -310,18 +310,18 @@ static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv, DRM_ERROR ("wrong number of vertices %u in TRIFAN/STRIP\n", n); - return DRM_ERR(EINVAL); + return -EINVAL; } break; default: DRM_ERROR("invalid primitive type %u\n", prim); - return DRM_ERR(EINVAL); + return -EINVAL; } if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { if (skip != 0) { DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip); - return DRM_ERR(EINVAL); + return -EINVAL; } } else { unsigned int size = 10 - (skip & 1) - (skip >> 1 & 1) - @@ -329,18 +329,18 @@ static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv, (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1); if (skip > SAVAGE_SKIP_ALL_S4 || size != 8) { DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip); - return DRM_ERR(EINVAL); + return -EINVAL; } if (reorder) { DRM_ERROR("TRILIST_201 used on Savage4 hardware\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } } if (start + n > dmabuf->total/32) { DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n", start, start + n - 1, dmabuf->total/32); - return DRM_ERR(EINVAL); + return -EINVAL; } /* Vertex DMA doesn't work with command DMA at the same time, @@ -438,7 +438,7 @@ static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv, if (n % 3 != 0) { DRM_ERROR("wrong number of vertices %u in TRILIST\n", n); - return DRM_ERR(EINVAL); + return -EINVAL; } break; case SAVAGE_PRIM_TRISTRIP: @@ -447,24 +447,24 @@ static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv, DRM_ERROR ("wrong number of vertices %u in TRIFAN/STRIP\n", n); - return DRM_ERR(EINVAL); + return -EINVAL; } break; default: DRM_ERROR("invalid primitive type %u\n", prim); - return DRM_ERR(EINVAL); + return -EINVAL; } if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { if (skip > SAVAGE_SKIP_ALL_S3D) { DRM_ERROR("invalid skip flags 0x%04x\n", skip); - return DRM_ERR(EINVAL); + return -EINVAL; } vtx_size = 8; /* full vertex */ } else { if (skip > SAVAGE_SKIP_ALL_S4) { DRM_ERROR("invalid skip flags 0x%04x\n", skip); - return DRM_ERR(EINVAL); + return -EINVAL; } vtx_size = 10; /* full vertex */ } @@ -476,13 +476,13 @@ static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv, if (vtx_size > vb_stride) { DRM_ERROR("vertex size greater than vb stride (%u > %u)\n", vtx_size, vb_stride); - return DRM_ERR(EINVAL); + return -EINVAL; } if (start + n > vb_size / (vb_stride*4)) { DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n", start, start + n - 1, vb_size / (vb_stride*4)); - return DRM_ERR(EINVAL); + return -EINVAL; } prim <<= 25; @@ -545,7 +545,7 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv, if (!dmabuf) { DRM_ERROR("called without dma buffers!\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } if (!n) @@ -558,7 +558,7 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv, case SAVAGE_PRIM_TRILIST: if (n % 3 != 0) { DRM_ERROR("wrong number of indices %u in TRILIST\n", n); - return DRM_ERR(EINVAL); + return -EINVAL; } break; case SAVAGE_PRIM_TRISTRIP: @@ -566,18 +566,18 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv, if (n < 3) { DRM_ERROR ("wrong number of indices %u in TRIFAN/STRIP\n", n); - return DRM_ERR(EINVAL); + return -EINVAL; } break; default: DRM_ERROR("invalid primitive type %u\n", prim); - return DRM_ERR(EINVAL); + return -EINVAL; } if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { if (skip != 0) { DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip); - return DRM_ERR(EINVAL); + return -EINVAL; } } else { unsigned int size = 10 - (skip & 1) - (skip >> 1 & 1) - @@ -585,11 +585,11 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv, (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1); if (skip > SAVAGE_SKIP_ALL_S4 || size != 8) { DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip); - return DRM_ERR(EINVAL); + return -EINVAL; } if (reorder) { DRM_ERROR("TRILIST_201 used on Savage4 hardware\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } } @@ -626,7 +626,7 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv, if (idx[i] > dmabuf->total/32) { DRM_ERROR("idx[%u]=%u out of range (0-%u)\n", i, idx[i], dmabuf->total/32); - return DRM_ERR(EINVAL); + return -EINVAL; } } @@ -696,7 +696,7 @@ static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv, case SAVAGE_PRIM_TRILIST: if (n % 3 != 0) { DRM_ERROR("wrong number of indices %u in TRILIST\n", n); - return DRM_ERR(EINVAL); + return -EINVAL; } break; case SAVAGE_PRIM_TRISTRIP: @@ -704,24 +704,24 @@ static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv, if (n < 3) { DRM_ERROR ("wrong number of indices %u in TRIFAN/STRIP\n", n); - return DRM_ERR(EINVAL); + return -EINVAL; } break; default: DRM_ERROR("invalid primitive type %u\n", prim); - return DRM_ERR(EINVAL); + return -EINVAL; } if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { if (skip > SAVAGE_SKIP_ALL_S3D) { DRM_ERROR("invalid skip flags 0x%04x\n", skip); - return DRM_ERR(EINVAL); + return -EINVAL; } vtx_size = 8; /* full vertex */ } else { if (skip > SAVAGE_SKIP_ALL_S4) { DRM_ERROR("invalid skip flags 0x%04x\n", skip); - return DRM_ERR(EINVAL); + return -EINVAL; } vtx_size = 10; /* full vertex */ } @@ -733,7 +733,7 @@ static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv, if (vtx_size > vb_stride) { DRM_ERROR("vertex size greater than vb stride (%u > %u)\n", vtx_size, vb_stride); - return DRM_ERR(EINVAL); + return -EINVAL; } prim <<= 25; @@ -746,7 +746,7 @@ static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv, if (idx[i] > vb_size / (vb_stride*4)) { DRM_ERROR("idx[%u]=%u out of range (0-%u)\n", i, idx[i], vb_size / (vb_stride*4)); - return DRM_ERR(EINVAL); + return -EINVAL; } } @@ -941,7 +941,7 @@ static int savage_dispatch_draw(drm_savage_private_t *dev_priv, DRM_ERROR("IMPLEMENTATION ERROR: " "non-drawing-command %d\n", cmd_header.cmd.cmd); - return DRM_ERR(EINVAL); + return -EINVAL; } if (ret != 0) @@ -978,7 +978,7 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) DRM_ERROR ("vertex buffer index %u out of range (0-%u)\n", cmdbuf.dma_idx, dma->buf_count-1); - return DRM_ERR(EINVAL); + return -EINVAL; } dmabuf = dma->buflist[cmdbuf.dma_idx]; } else { @@ -993,26 +993,26 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) if (cmdbuf.size) { kcmd_addr = drm_alloc(cmdbuf.size * 8, DRM_MEM_DRIVER); if (kcmd_addr == NULL) - return DRM_ERR(ENOMEM); + return -ENOMEM; if (DRM_COPY_FROM_USER(kcmd_addr, cmdbuf.cmd_addr, cmdbuf.size * 8)) { drm_free(kcmd_addr, cmdbuf.size * 8, DRM_MEM_DRIVER); - return DRM_ERR(EFAULT); + return -EFAULT; } cmdbuf.cmd_addr = kcmd_addr; } if (cmdbuf.vb_size) { kvb_addr = drm_alloc(cmdbuf.vb_size, DRM_MEM_DRIVER); if (kvb_addr == NULL) { - ret = DRM_ERR(ENOMEM); + ret = -ENOMEM; goto done; } if (DRM_COPY_FROM_USER(kvb_addr, cmdbuf.vb_addr, cmdbuf.vb_size)) { - ret = DRM_ERR(EFAULT); + ret = -EFAULT; goto done; } cmdbuf.vb_addr = kvb_addr; @@ -1021,13 +1021,13 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) kbox_addr = drm_alloc(cmdbuf.nbox * sizeof(struct drm_clip_rect), DRM_MEM_DRIVER); if (kbox_addr == NULL) { - ret = DRM_ERR(ENOMEM); + ret = -ENOMEM; goto done; } if (DRM_COPY_FROM_USER(kbox_addr, cmdbuf.box_addr, cmdbuf.nbox * sizeof(struct drm_clip_rect))) { - ret = DRM_ERR(EFAULT); + ret = -EFAULT; goto done; } cmdbuf.box_addr = kbox_addr; @@ -1060,7 +1060,7 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) DRM_ERROR("indexed drawing command extends " "beyond end of command buffer\n"); DMA_FLUSH(); - return DRM_ERR(EINVAL); + return -EINVAL; } /* fall through */ case SAVAGE_CMD_DMA_PRIM: @@ -1093,7 +1093,7 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) DRM_ERROR("command SAVAGE_CMD_STATE extends " "beyond end of command buffer\n"); DMA_FLUSH(); - ret = DRM_ERR(EINVAL); + ret = -EINVAL; goto done; } ret = savage_dispatch_state(dev_priv, &cmd_header, @@ -1106,7 +1106,7 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) DRM_ERROR("command SAVAGE_CMD_CLEAR extends " "beyond end of command buffer\n"); DMA_FLUSH(); - ret = DRM_ERR(EINVAL); + ret = -EINVAL; goto done; } ret = savage_dispatch_clear(dev_priv, &cmd_header, @@ -1122,7 +1122,7 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) default: DRM_ERROR("invalid command 0x%x\n", cmd_header.cmd.cmd); DMA_FLUSH(); - ret = DRM_ERR(EINVAL); + ret = -EINVAL; goto done; } diff --git a/shared-core/sis_mm.c b/shared-core/sis_mm.c index 6d074d6f..b62e3e27 100644 --- a/shared-core/sis_mm.c +++ b/shared-core/sis_mm.c @@ -104,7 +104,7 @@ static int sis_fb_alloc(DRM_IOCTL_ARGS) if (!add_alloc_set(fb.context, VIDEO_TYPE, fb.free)) { DRM_DEBUG("adding to allocation set fails\n"); sis_free(req.offset); - retval = DRM_ERR(EINVAL); + retval = -EINVAL; } } else { fb.offset = 0; @@ -127,10 +127,10 @@ static int sis_fb_free(DRM_IOCTL_ARGS) DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_mem_t __user *) data, sizeof(fb)); if (!fb.free) - return DRM_ERR(EINVAL); + return -EINVAL; if (!del_alloc_set(fb.context, VIDEO_TYPE, fb.free)) - retval = DRM_ERR(EINVAL); + retval = -EINVAL; sis_free(fb.free); DRM_DEBUG("free fb, offset = 0x%lx\n", fb.free); @@ -167,7 +167,7 @@ static int sis_fb_init(DRM_IOCTL_ARGS) } if (dev_priv->FBHeap != NULL) - return DRM_ERR(EINVAL); + return -EINVAL; dev_priv->FBHeap = mmInit(fb.offset, fb.size); @@ -186,7 +186,7 @@ static int sis_fb_alloc(DRM_IOCTL_ARGS) int retval = 0; if (dev_priv == NULL || dev_priv->FBHeap == NULL) - return DRM_ERR(EINVAL); + return -EINVAL; DRM_COPY_FROM_USER_IOCTL(fb, argp, sizeof(fb)); @@ -198,7 +198,7 @@ static int sis_fb_alloc(DRM_IOCTL_ARGS) if (!add_alloc_set(fb.context, VIDEO_TYPE, fb.free)) { DRM_DEBUG("adding to allocation set fails\n"); mmFreeMem((PMemBlock) fb.free); - retval = DRM_ERR(EINVAL); + retval = -EINVAL; } } else { fb.offset = 0; @@ -220,15 +220,15 @@ static int sis_fb_free(DRM_IOCTL_ARGS) drm_sis_mem_t fb; if (dev_priv == NULL || dev_priv->FBHeap == NULL) - return DRM_ERR(EINVAL); + return -EINVAL; DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_mem_t __user *) data, sizeof(fb)); if (!mmBlockInHeap(dev_priv->FBHeap, (PMemBlock) fb.free)) - return DRM_ERR(EINVAL); + return -EINVAL; if (!del_alloc_set(fb.context, VIDEO_TYPE, fb.free)) - return DRM_ERR(EINVAL); + return -EINVAL; mmFreeMem((PMemBlock) fb.free); DRM_DEBUG("free fb, free = 0x%lx\n", fb.free); @@ -255,7 +255,7 @@ static int sis_ioctl_agp_init(DRM_IOCTL_ARGS) } if (dev_priv->AGPHeap != NULL) - return DRM_ERR(EINVAL); + return -EINVAL; DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_agp_t __user *) data, sizeof(agp)); @@ -277,7 +277,7 @@ static int sis_ioctl_agp_alloc(DRM_IOCTL_ARGS) int retval = 0; if (dev_priv == NULL || dev_priv->AGPHeap == NULL) - return DRM_ERR(EINVAL); + return -EINVAL; DRM_COPY_FROM_USER_IOCTL(agp, argp, sizeof(agp)); @@ -311,17 +311,17 @@ static int sis_ioctl_agp_free(DRM_IOCTL_ARGS) drm_sis_mem_t agp; if (dev_priv == NULL || dev_priv->AGPHeap == NULL) - return DRM_ERR(EINVAL); + return -EINVAL; DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_mem_t __user *) data, sizeof(agp)); if (!mmBlockInHeap(dev_priv->AGPHeap, (PMemBlock) agp.free)) - return DRM_ERR(EINVAL); + return -EINVAL; mmFreeMem((PMemBlock) agp.free); if (!del_alloc_set(agp.context, AGP_TYPE, agp.free)) - return DRM_ERR(EINVAL); + return -EINVAL; DRM_DEBUG("free agp, free = 0x%lx\n", agp.free); diff --git a/shared-core/via_dma.c b/shared-core/via_dma.c index 48f46938..895c78bf 100644 --- a/shared-core/via_dma.c +++ b/shared-core/via_dma.c @@ -163,24 +163,24 @@ static int via_initialize(struct drm_device * dev, { if (!dev_priv || !dev_priv->mmio) { DRM_ERROR("via_dma_init called before via_map_init\n"); - return DRM_ERR(EFAULT); + return -EFAULT; } if (dev_priv->ring.virtual_start != NULL) { DRM_ERROR("%s called again without calling cleanup\n", __FUNCTION__); - return DRM_ERR(EFAULT); + return -EFAULT; } if (!dev->agp || !dev->agp->base) { DRM_ERROR("%s called with no agp memory available\n", __FUNCTION__); - return DRM_ERR(EFAULT); + return -EFAULT; } if (dev_priv->chipset == VIA_DX9_0) { DRM_ERROR("AGP DMA is not supported on this chip\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } dev_priv->ring.map.offset = dev->agp->base + init->offset; @@ -195,7 +195,7 @@ static int via_initialize(struct drm_device * dev, via_dma_cleanup(dev); DRM_ERROR("can not ioremap virtual address for" " ring buffer\n"); - return DRM_ERR(ENOMEM); + return -ENOMEM; } dev_priv->ring.virtual_start = dev_priv->ring.map.handle; @@ -228,22 +228,22 @@ static int via_dma_init(DRM_IOCTL_ARGS) switch (init.func) { case VIA_INIT_DMA: if (!DRM_SUSER(DRM_CURPROC)) - retcode = DRM_ERR(EPERM); + retcode = -EPERM; else retcode = via_initialize(dev, dev_priv, &init); break; case VIA_CLEANUP_DMA: if (!DRM_SUSER(DRM_CURPROC)) - retcode = DRM_ERR(EPERM); + retcode = -EPERM; else retcode = via_dma_cleanup(dev); break; case VIA_DMA_INITIALIZED: retcode = (dev_priv->ring.virtual_start != NULL) ? - 0 : DRM_ERR(EFAULT); + 0 : -EFAULT; break; default: - retcode = DRM_ERR(EINVAL); + retcode = -EINVAL; break; } @@ -263,15 +263,15 @@ static int via_dispatch_cmdbuffer(struct drm_device * dev, drm_via_cmdbuffer_t * if (dev_priv->ring.virtual_start == NULL) { DRM_ERROR("%s called without initializing AGP ring buffer.\n", __FUNCTION__); - return DRM_ERR(EFAULT); + return -EFAULT; } if (cmd->size > VIA_PCI_BUF_SIZE) { - return DRM_ERR(ENOMEM); + return -ENOMEM; } if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size)) - return DRM_ERR(EFAULT); + return -EFAULT; /* * Running this function on AGP memory is dead slow. Therefore @@ -287,7 +287,7 @@ static int via_dispatch_cmdbuffer(struct drm_device * dev, drm_via_cmdbuffer_t * vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size); if (vb == NULL) { - return DRM_ERR(EAGAIN); + return -EAGAIN; } memcpy(vb, dev_priv->pci_buf, cmd->size); @@ -311,7 +311,7 @@ int via_driver_dma_quiescent(struct drm_device * dev) drm_via_private_t *dev_priv = dev->dev_private; if (!via_wait_idle(dev_priv)) { - return DRM_ERR(EBUSY); + return -EBUSY; } return 0; } @@ -353,10 +353,10 @@ static int via_dispatch_pci_cmdbuffer(struct drm_device * dev, int ret; if (cmd->size > VIA_PCI_BUF_SIZE) { - return DRM_ERR(ENOMEM); + return -ENOMEM; } if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size)) - return DRM_ERR(EFAULT); + return -EFAULT; if ((ret = via_verify_command_stream((uint32_t *) dev_priv->pci_buf, @@ -661,7 +661,7 @@ static int via_cmdbuf_size(DRM_IOCTL_ARGS) if (dev_priv->ring.virtual_start == NULL) { DRM_ERROR("%s called without initializing AGP ring buffer.\n", __FUNCTION__); - return DRM_ERR(EFAULT); + return -EFAULT; } DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t __user *) data, @@ -680,7 +680,7 @@ static int via_cmdbuf_size(DRM_IOCTL_ARGS) } if (!count) { DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n"); - ret = DRM_ERR(EAGAIN); + ret = -EAGAIN; } break; case VIA_CMDBUF_LAG: @@ -692,11 +692,11 @@ static int via_cmdbuf_size(DRM_IOCTL_ARGS) } if (!count) { DRM_ERROR("VIA_CMDBUF_LAG timed out.\n"); - ret = DRM_ERR(EAGAIN); + ret = -EAGAIN; } break; default: - ret = DRM_ERR(EFAULT); + ret = -EFAULT; } d_siz.size = tmp_size; @@ -709,12 +709,12 @@ static int via_cmdbuf_size(DRM_IOCTL_ARGS) int via_dma_blit_sync( DRM_IOCTL_ARGS ) { DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } int via_dma_blit( DRM_IOCTL_ARGS ) { DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n"); - return DRM_ERR(EINVAL); + return -EINVAL; } #endif diff --git a/shared-core/via_irq.c b/shared-core/via_irq.c index 040df548..68ee5226 100644 --- a/shared-core/via_irq.c +++ b/shared-core/via_irq.c @@ -213,13 +213,13 @@ via_driver_irq_wait(struct drm_device * dev, unsigned int irq, int force_sequenc if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } if (irq >= drm_via_irq_num ) { DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__, irq); - return DRM_ERR(EINVAL); + return -EINVAL; } real_irq = dev_priv->irq_map[irq]; @@ -227,7 +227,7 @@ via_driver_irq_wait(struct drm_device * dev, unsigned int irq, int force_sequenc if (real_irq < 0) { DRM_ERROR("%s Video IRQ %d not available on this hardware.\n", __FUNCTION__, irq); - return DRM_ERR(EINVAL); + return -EINVAL; } masks = dev_priv->irq_masks; @@ -352,13 +352,13 @@ int via_wait_irq(DRM_IOCTL_ARGS) int force_sequence; if (!dev->irq) - return DRM_ERR(EINVAL); + return -EINVAL; DRM_COPY_FROM_USER_IOCTL(irqwait, argp, sizeof(irqwait)); if (irqwait.request.irq >= dev_priv->num_irqs) { DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__, irqwait.request.irq); - return DRM_ERR(EINVAL); + return -EINVAL; } cur_irq += irqwait.request.irq; @@ -370,13 +370,13 @@ int via_wait_irq(DRM_IOCTL_ARGS) case VIA_IRQ_ABSOLUTE: break; default: - return DRM_ERR(EINVAL); + return -EINVAL; } if (irqwait.request.type & VIA_IRQ_SIGNAL) { DRM_ERROR("%s Signals on Via IRQs not implemented yet.\n", __FUNCTION__); - return DRM_ERR(EINVAL); + return -EINVAL; } force_sequence = (irqwait.request.type & VIA_IRQ_FORCE_SEQUENCE); diff --git a/shared-core/via_map.c b/shared-core/via_map.c index 2381eaa9..1aed10f5 100644 --- a/shared-core/via_map.c +++ b/shared-core/via_map.c @@ -118,7 +118,7 @@ int via_driver_load(struct drm_device *dev, unsigned long chipset) dev_priv = drm_calloc(1, sizeof(drm_via_private_t), DRM_MEM_DRIVER); if (dev_priv == NULL) - return DRM_ERR(ENOMEM); + return -ENOMEM; dev->dev_private = (void *)dev_priv; diff --git a/shared-core/via_verifier.c b/shared-core/via_verifier.c index 038bea2f..ded5c4e1 100644 --- a/shared-core/via_verifier.c +++ b/shared-core/via_verifier.c @@ -1031,12 +1031,12 @@ via_verify_command_stream(const uint32_t * buf, unsigned int size, case state_error: default: *hc_state = saved_state; - return DRM_ERR(EINVAL); + return -EINVAL; } } if (state == state_error) { *hc_state = saved_state; - return DRM_ERR(EINVAL); + return -EINVAL; } return 0; } @@ -1087,11 +1087,11 @@ via_parse_command_stream(struct drm_device * dev, const uint32_t * buf, break; case state_error: default: - return DRM_ERR(EINVAL); + return -EINVAL; } } if (state == state_error) { - return DRM_ERR(EINVAL); + return -EINVAL; } return 0; } -- cgit v1.2.3 From c1119b1b092527fbb6950d0b5e51e076ddb00f29 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 20 Jul 2007 06:39:25 -0700 Subject: Replace filp in ioctl arguments with drm_file *file_priv. As a fallout, replace filp storage with file_priv storage for "unique identifier of a client" all over the DRM. There is a 1:1 mapping, so this should be a noop. This could be a minor performance improvement, as everything on Linux dereferenced filp to get file_priv anyway, while only the mmap ioctls went the other direction. --- shared-core/i915_dma.c | 12 +-- shared-core/i915_drv.h | 8 +- shared-core/i915_irq.c | 4 +- shared-core/i915_mem.c | 41 ++++----- shared-core/mach64_dma.c | 17 ++-- shared-core/mach64_drv.h | 4 +- shared-core/mach64_state.c | 47 +++++----- shared-core/mga_dma.c | 15 ++-- shared-core/mga_state.c | 12 +-- shared-core/nouveau_drv.h | 28 +++--- shared-core/nouveau_fifo.c | 25 +++--- shared-core/nouveau_mem.c | 62 +++++++------ shared-core/nouveau_notifier.c | 11 ++- shared-core/nouveau_object.c | 4 +- shared-core/nouveau_state.c | 13 +-- shared-core/nv50_instmem.c | 2 +- shared-core/r128_cce.c | 24 ++--- shared-core/r128_drv.h | 3 +- shared-core/r128_state.c | 43 ++++----- shared-core/r300_cmdbuf.c | 8 +- shared-core/radeon_cp.c | 31 ++++--- shared-core/radeon_drv.h | 20 +++-- shared-core/radeon_irq.c | 2 +- shared-core/radeon_mem.c | 40 ++++----- shared-core/radeon_state.c | 196 +++++++++++++++++++---------------------- shared-core/savage_bci.c | 20 +++-- shared-core/savage_drv.h | 3 +- shared-core/savage_state.c | 2 +- shared-core/sis_drv.h | 3 +- shared-core/via_dma.c | 8 +- shared-core/via_drv.h | 3 +- 31 files changed, 375 insertions(+), 336 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 81e6981d..05336d35 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -654,7 +654,7 @@ static int i915_flush_ioctl(DRM_IOCTL_ARGS) { DRM_DEVICE; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); return i915_quiescent(dev); } @@ -679,7 +679,7 @@ static int i915_batchbuffer(DRM_IOCTL_ARGS) DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n", batch.start, batch.used, batch.num_cliprects); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects, batch.num_cliprects * @@ -707,7 +707,7 @@ static int i915_cmdbuffer(DRM_IOCTL_ARGS) DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n", cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (cmdbuf.num_cliprects && DRM_VERIFYAREA_READ(cmdbuf.cliprects, @@ -756,7 +756,7 @@ static int i915_flip_bufs(DRM_IOCTL_ARGS) DRM_DEBUG("%s\n", __FUNCTION__); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_flip_t __user *) data, sizeof(param)); @@ -965,11 +965,11 @@ void i915_driver_lastclose(struct drm_device * dev) i915_dma_cleanup(dev); } -void i915_driver_preclose(struct drm_device * dev, DRMFILE filp) +void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) { if (dev->dev_private) { drm_i915_private_t *dev_priv = dev->dev_private; - i915_mem_release(dev, filp, dev_priv->agp_heap); + i915_mem_release(dev, file_priv, dev_priv->agp_heap); } } diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 1a2220a5..73b3d187 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -81,7 +81,7 @@ struct mem_block { struct mem_block *prev; int start; int size; - DRMFILE filp; /* 0: free, -1: heap, other: real files */ + struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ }; typedef struct _drm_i915_vbl_swap { @@ -152,7 +152,8 @@ extern int i915_max_ioctl; extern void i915_kernel_lost_context(struct drm_device * dev); extern int i915_driver_load(struct drm_device *, unsigned long flags); extern void i915_driver_lastclose(struct drm_device * dev); -extern void i915_driver_preclose(struct drm_device * dev, DRMFILE filp); +extern void i915_driver_preclose(struct drm_device *dev, + struct drm_file *file_priv); extern int i915_driver_device_is_agp(struct drm_device * dev); extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); @@ -185,7 +186,8 @@ extern int i915_mem_init_heap(DRM_IOCTL_ARGS); extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS); extern void i915_mem_takedown(struct mem_block **heap); extern void i915_mem_release(struct drm_device * dev, - DRMFILE filp, struct mem_block *heap); + struct drm_file *file_priv, + struct mem_block *heap); #ifdef I915_HAVE_FENCE /* i915_fence.c */ diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c index f4775b75..da61997e 100644 --- a/shared-core/i915_irq.c +++ b/shared-core/i915_irq.c @@ -456,7 +456,7 @@ int i915_irq_emit(DRM_IOCTL_ARGS) drm_i915_irq_emit_t emit; int result; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); @@ -623,7 +623,7 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) if ((curseq - swap.sequence) <= (1<<23)) { struct drm_drawable_info *drw; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags); diff --git a/shared-core/i915_mem.c b/shared-core/i915_mem.c index 381562d8..e2e7018d 100644 --- a/shared-core/i915_mem.c +++ b/shared-core/i915_mem.c @@ -89,7 +89,7 @@ static void mark_block(struct drm_device * dev, struct mem_block *p, int in_use) */ static struct mem_block *split_block(struct mem_block *p, int start, int size, - DRMFILE filp) + struct drm_file *file_priv) { /* Maybe cut off the start of an existing block */ if (start > p->start) { @@ -99,7 +99,7 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size, goto out; newblock->start = start; newblock->size = p->size - (start - p->start); - newblock->filp = NULL; + newblock->file_priv = NULL; newblock->next = p->next; newblock->prev = p; p->next->prev = newblock; @@ -116,7 +116,7 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size, goto out; newblock->start = start + size; newblock->size = p->size - size; - newblock->filp = NULL; + newblock->file_priv = NULL; newblock->next = p->next; newblock->prev = p; p->next->prev = newblock; @@ -126,20 +126,20 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size, out: /* Our block is in the middle */ - p->filp = filp; + p->file_priv = file_priv; return p; } static struct mem_block *alloc_block(struct mem_block *heap, int size, - int align2, DRMFILE filp) + int align2, struct drm_file *file_priv) { struct mem_block *p; int mask = (1 << align2) - 1; for (p = heap->next; p != heap; p = p->next) { int start = (p->start + mask) & ~mask; - if (p->filp == NULL && start + size <= p->start + p->size) - return split_block(p, start, size, filp); + if (p->file_priv == NULL && start + size <= p->start + p->size) + return split_block(p, start, size, file_priv); } return NULL; @@ -158,12 +158,12 @@ static struct mem_block *find_block(struct mem_block *heap, int start) static void free_block(struct mem_block *p) { - p->filp = NULL; + p->file_priv = NULL; - /* Assumes a single contiguous range. Needs a special filp in + /* Assumes a single contiguous range. Needs a special file_priv in * 'heap' to stop it being subsumed. */ - if (p->next->filp == NULL) { + if (p->next->file_priv == NULL) { struct mem_block *q = p->next; p->size += q->size; p->next = q->next; @@ -171,7 +171,7 @@ static void free_block(struct mem_block *p) drm_free(q, sizeof(*q), DRM_MEM_BUFLISTS); } - if (p->prev->filp == NULL) { + if (p->prev->file_priv == NULL) { struct mem_block *q = p->prev; q->size += p->size; q->next = p->next; @@ -197,18 +197,19 @@ static int init_heap(struct mem_block **heap, int start, int size) blocks->start = start; blocks->size = size; - blocks->filp = NULL; + blocks->file_priv = NULL; blocks->next = blocks->prev = *heap; memset(*heap, 0, sizeof(**heap)); - (*heap)->filp = (DRMFILE) - 1; + (*heap)->file_priv = (struct drm_file *) - 1; (*heap)->next = (*heap)->prev = blocks; return 0; } /* Free all blocks associated with the releasing file. */ -void i915_mem_release(struct drm_device * dev, DRMFILE filp, struct mem_block *heap) +void i915_mem_release(struct drm_device * dev, struct drm_file *file_priv, + struct mem_block *heap) { struct mem_block *p; @@ -216,17 +217,17 @@ void i915_mem_release(struct drm_device * dev, DRMFILE filp, struct mem_block *h return; for (p = heap->next; p != heap; p = p->next) { - if (p->filp == filp) { - p->filp = NULL; + if (p->file_priv == file_priv) { + p->file_priv = NULL; mark_block(dev, p, 0); } } - /* Assumes a single contiguous range. Needs a special filp in + /* Assumes a single contiguous range. Needs a special file_priv in * 'heap' to stop it being subsumed. */ for (p = heap->next; p != heap; p = p->next) { - while (p->filp == NULL && p->next->filp == NULL) { + while (p->file_priv == NULL && p->next->file_priv == NULL) { struct mem_block *q = p->next; p->size += q->size; p->next = q->next; @@ -292,7 +293,7 @@ int i915_mem_alloc(DRM_IOCTL_ARGS) if (alloc.alignment < 12) alloc.alignment = 12; - block = alloc_block(*heap, alloc.size, alloc.alignment, filp); + block = alloc_block(*heap, alloc.size, alloc.alignment, file_priv); if (!block) return -ENOMEM; @@ -330,7 +331,7 @@ int i915_mem_free(DRM_IOCTL_ARGS) if (!block) return -EFAULT; - if (block->filp != filp) + if (block->file_priv != file_priv) return -EPERM; mark_block(dev, block, 0); diff --git a/shared-core/mach64_dma.c b/shared-core/mach64_dma.c index fec73076..25877824 100644 --- a/shared-core/mach64_dma.c +++ b/shared-core/mach64_dma.c @@ -1165,7 +1165,7 @@ int mach64_dma_init(DRM_IOCTL_ARGS) DRM_DEBUG("%s\n", __FUNCTION__); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(init, (drm_mach64_init_t *) data, sizeof(init)); @@ -1187,7 +1187,7 @@ int mach64_dma_idle(DRM_IOCTL_ARGS) DRM_DEBUG("%s\n", __FUNCTION__); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); return mach64_do_dma_idle(dev_priv); } @@ -1199,7 +1199,7 @@ int mach64_dma_flush(DRM_IOCTL_ARGS) DRM_DEBUG("%s\n", __FUNCTION__); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); return mach64_do_dma_flush(dev_priv); } @@ -1211,7 +1211,7 @@ int mach64_engine_reset(DRM_IOCTL_ARGS) DRM_DEBUG("%s\n", __FUNCTION__); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); return mach64_do_engine_reset(dev_priv); } @@ -1461,7 +1461,8 @@ int mach64_freelist_put(drm_mach64_private_t * dev_priv, struct drm_buf * copy_b /** \name DMA buffer request and submission IOCTL handler */ /*@{*/ -static int mach64_dma_get_buffers(DRMFILE filp, struct drm_device * dev, +static int mach64_dma_get_buffers(struct drm_device * dev, + struct drm_file *file_priv, struct drm_dma * d) { int i; @@ -1478,7 +1479,7 @@ static int mach64_dma_get_buffers(DRMFILE filp, struct drm_device * dev, return -EAGAIN; #endif - buf->filp = filp; + buf->file_priv = file_priv; if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, sizeof(buf->idx))) @@ -1499,7 +1500,7 @@ int mach64_dma_buffers(DRM_IOCTL_ARGS) struct drm_dma d; int ret = 0; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(d, (struct drm_dma *) data, sizeof(d)); @@ -1522,7 +1523,7 @@ int mach64_dma_buffers(DRM_IOCTL_ARGS) d.granted_count = 0; if (d.request_count) { - ret = mach64_dma_get_buffers(filp, dev, &d); + ret = mach64_dma_get_buffers(dev, file_priv, &d); } DRM_COPY_TO_USER_IOCTL((struct drm_dma *) data, d, sizeof(d)); diff --git a/shared-core/mach64_drv.h b/shared-core/mach64_drv.h index 5d83c861..aa9afcab 100644 --- a/shared-core/mach64_drv.h +++ b/shared-core/mach64_drv.h @@ -842,7 +842,7 @@ do { \ } while(0) /* FIXME: use a private set of smaller buffers for state emits, clears, and swaps? */ -#define DMAGETPTR( filp, dev_priv, n ) \ +#define DMAGETPTR( file_priv, dev_priv, n ) \ do { \ if ( MACH64_VERBOSE ) { \ DRM_INFO( "DMAGETPTR( %d ) in %s\n", \ @@ -859,7 +859,7 @@ do { \ __FUNCTION__ ); \ return -EFAULT; \ } \ - _buf->filp = filp; \ + _buf->file_priv = file_priv; \ _outcount = 0; \ \ _buf_wptr = GETBUFPTR( _buf ); \ diff --git a/shared-core/mach64_state.c b/shared-core/mach64_state.c index 397faaaa..c89573e7 100644 --- a/shared-core/mach64_state.c +++ b/shared-core/mach64_state.c @@ -85,7 +85,8 @@ static void mach64_print_dirty(const char *msg, unsigned int flags) /* This function returns 0 on success, 1 for no intersection, and * negative for an error */ -static int mach64_emit_cliprect(DRMFILE filp, drm_mach64_private_t * dev_priv, +static int mach64_emit_cliprect(struct drm_file *file_priv, + drm_mach64_private_t * dev_priv, struct drm_clip_rect * box) { u32 sc_left_right, sc_top_bottom; @@ -120,7 +121,7 @@ static int mach64_emit_cliprect(DRMFILE filp, drm_mach64_private_t * dev_priv, if (scissor.y1 >= scissor.y2) return 1; - DMAGETPTR(filp, dev_priv, 2); /* returns on failure to get buffer */ + DMAGETPTR(file_priv, dev_priv, 2); /* returns on failure to get buffer */ sc_left_right = ((scissor.x1 << 0) | (scissor.x2 << 16)); sc_top_bottom = ((scissor.y1 << 0) | (scissor.y2 << 16)); @@ -133,7 +134,7 @@ static int mach64_emit_cliprect(DRMFILE filp, drm_mach64_private_t * dev_priv, return 0; } -static __inline__ int mach64_emit_state(DRMFILE filp, +static __inline__ int mach64_emit_state(struct drm_file *file_priv, drm_mach64_private_t * dev_priv) { drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -148,7 +149,7 @@ static __inline__ int mach64_emit_state(DRMFILE filp, DRM_DEBUG("%s: dirty=0x%08x\n", __FUNCTION__, dirty); } - DMAGETPTR(filp, dev_priv, 17); /* returns on failure to get buffer */ + DMAGETPTR(file_priv, dev_priv, 17); /* returns on failure to get buffer */ if (dirty & MACH64_UPLOAD_MISC) { DMAOUTREG(MACH64_DP_MIX, regs->dp_mix); @@ -212,7 +213,8 @@ static __inline__ int mach64_emit_state(DRMFILE filp, * DMA command dispatch functions */ -static int mach64_dma_dispatch_clear(DRMFILE filp, struct drm_device * dev, +static int mach64_dma_dispatch_clear(struct drm_device * dev, + struct drm_file *file_priv, unsigned int flags, int cx, int cy, int cw, int ch, unsigned int clear_color, @@ -254,7 +256,7 @@ static int mach64_dma_dispatch_clear(DRMFILE filp, struct drm_device * dev, if (!nbox) return 0; - DMAGETPTR(filp, dev_priv, nbox * 31); /* returns on failure to get buffer */ + DMAGETPTR(file_priv, dev_priv, nbox * 31); /* returns on failure to get buffer */ for (i = 0; i < nbox; i++) { int x = pbox[i].x1; @@ -355,7 +357,8 @@ static int mach64_dma_dispatch_clear(DRMFILE filp, struct drm_device * dev, return 0; } -static int mach64_dma_dispatch_swap(DRMFILE filp, struct drm_device * dev) +static int mach64_dma_dispatch_swap(struct drm_device * dev, + struct drm_file *file_priv) { drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -380,7 +383,7 @@ static int mach64_dma_dispatch_swap(DRMFILE filp, struct drm_device * dev) if (!nbox) return 0; - DMAGETPTR(filp, dev_priv, 13 + nbox * 4); /* returns on failure to get buffer */ + DMAGETPTR(file_priv, dev_priv, 13 + nbox * 4); /* returns on failure to get buffer */ DMAOUTREG(MACH64_Z_CNTL, 0); DMAOUTREG(MACH64_SCALE_3D_CNTL, 0); @@ -545,7 +548,8 @@ static __inline__ int copy_from_user_vertex(u32 *to, } } -static int mach64_dma_dispatch_vertex(DRMFILE filp, struct drm_device * dev, +static int mach64_dma_dispatch_vertex(struct drm_device * dev, + struct drm_file *file_priv, drm_mach64_vertex_t * vertex) { drm_mach64_private_t *dev_priv = dev->dev_private; @@ -583,7 +587,7 @@ static int mach64_dma_dispatch_vertex(DRMFILE filp, struct drm_device * dev, DMASETPTR(copy_buf); if (sarea_priv->dirty & ~MACH64_UPLOAD_CLIPRECTS) { - ret = mach64_emit_state(filp, dev_priv); + ret = mach64_emit_state(file_priv, dev_priv); if (ret < 0) return ret; } @@ -591,7 +595,7 @@ static int mach64_dma_dispatch_vertex(DRMFILE filp, struct drm_device * dev, do { /* Emit the next cliprect */ if (i < sarea_priv->nbox) { - ret = mach64_emit_cliprect(filp, dev_priv, + ret = mach64_emit_cliprect(file_priv, dev_priv, &sarea_priv->boxes[i]); if (ret < 0) { /* failed to get buffer */ @@ -640,7 +644,8 @@ static __inline__ int copy_from_user_blit(u32 *to, return 0; } -static int mach64_dma_dispatch_blit(DRMFILE filp, struct drm_device * dev, +static int mach64_dma_dispatch_blit(struct drm_device * dev, + struct drm_file *file_priv, drm_mach64_blit_t * blit) { drm_mach64_private_t *dev_priv = dev->dev_private; @@ -763,7 +768,7 @@ int mach64_dma_clear(DRM_IOCTL_ARGS) DRM_DEBUG("%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(clear, (drm_mach64_clear_t *) data, sizeof(clear)); @@ -771,7 +776,7 @@ int mach64_dma_clear(DRM_IOCTL_ARGS) if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS; - ret = mach64_dma_dispatch_clear(filp, dev, clear.flags, + ret = mach64_dma_dispatch_clear(dev, file_priv, clear.flags, clear.x, clear.y, clear.w, clear.h, clear.clear_color, clear.clear_depth); @@ -790,12 +795,12 @@ int mach64_dma_swap(DRM_IOCTL_ARGS) DRM_DEBUG("%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS; - ret = mach64_dma_dispatch_swap(filp, dev); + ret = mach64_dma_dispatch_swap(dev, file_priv); /* Make sure we restore the 3D state next time. */ @@ -810,7 +815,7 @@ int mach64_dma_vertex(DRM_IOCTL_ARGS) drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mach64_vertex_t vertex; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); @@ -838,7 +843,7 @@ int mach64_dma_vertex(DRM_IOCTL_ARGS) if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS; - return mach64_dma_dispatch_vertex(filp, dev, &vertex); + return mach64_dma_dispatch_vertex(dev, file_priv, &vertex); } int mach64_dma_blit(DRM_IOCTL_ARGS) @@ -849,12 +854,12 @@ int mach64_dma_blit(DRM_IOCTL_ARGS) drm_mach64_blit_t blit; int ret; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(blit, (drm_mach64_blit_t *) data, sizeof(blit)); - ret = mach64_dma_dispatch_blit(filp, dev, &blit); + ret = mach64_dma_dispatch_blit(dev, file_priv, &blit); /* Make sure we restore the 3D state next time. */ @@ -884,7 +889,7 @@ int mach64_get_param(DRM_IOCTL_ARGS) switch (param.param) { case MACH64_PARAM_FRAMES_QUEUED: /* Needs lock since it calls mach64_ring_tick() */ - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); value = mach64_do_get_frames_queued(dev_priv); break; case MACH64_PARAM_IRQ_NR: diff --git a/shared-core/mga_dma.c b/shared-core/mga_dma.c index cbcb6380..429ffa54 100644 --- a/shared-core/mga_dma.c +++ b/shared-core/mga_dma.c @@ -1016,7 +1016,7 @@ int mga_dma_init(DRM_IOCTL_ARGS) drm_mga_init_t init; int err; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data, sizeof(init)); @@ -1045,7 +1045,7 @@ int mga_dma_flush(DRM_IOCTL_ARGS) drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; struct drm_lock lock; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(lock, (struct drm_lock __user *) data, sizeof(lock)); @@ -1080,7 +1080,7 @@ int mga_dma_reset(DRM_IOCTL_ARGS) DRM_DEVICE; drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); return mga_do_dma_reset(dev_priv); } @@ -1089,7 +1089,8 @@ int mga_dma_reset(DRM_IOCTL_ARGS) * DMA buffer management */ -static int mga_dma_get_buffers(DRMFILE filp, struct drm_device * dev, struct drm_dma * d) +static int mga_dma_get_buffers(struct drm_device * dev, + struct drm_file *file_priv, struct drm_dma * d) { struct drm_buf *buf; int i; @@ -1099,7 +1100,7 @@ static int mga_dma_get_buffers(DRMFILE filp, struct drm_device * dev, struct drm if (!buf) return -EAGAIN; - buf->filp = filp; + buf->file_priv = file_priv; if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, sizeof(buf->idx))) @@ -1122,7 +1123,7 @@ int mga_dma_buffers(DRM_IOCTL_ARGS) struct drm_dma d; int ret = 0; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); @@ -1147,7 +1148,7 @@ int mga_dma_buffers(DRM_IOCTL_ARGS) d.granted_count = 0; if (d.request_count) { - ret = mga_dma_get_buffers(filp, dev, &d); + ret = mga_dma_get_buffers(dev, file_priv, &d); } DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); diff --git a/shared-core/mga_state.c b/shared-core/mga_state.c index f77883db..196d7d16 100644 --- a/shared-core/mga_state.c +++ b/shared-core/mga_state.c @@ -872,7 +872,7 @@ static int mga_dma_clear(DRM_IOCTL_ARGS) drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_clear_t clear; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(clear, (drm_mga_clear_t __user *) data, sizeof(clear)); @@ -897,7 +897,7 @@ static int mga_dma_swap(DRM_IOCTL_ARGS) drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; @@ -922,7 +922,7 @@ static int mga_dma_vertex(DRM_IOCTL_ARGS) drm_mga_buf_priv_t *buf_priv; drm_mga_vertex_t vertex; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(vertex, (drm_mga_vertex_t __user *) data, @@ -962,7 +962,7 @@ static int mga_dma_indices(DRM_IOCTL_ARGS) drm_mga_buf_priv_t *buf_priv; drm_mga_indices_t indices; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(indices, (drm_mga_indices_t __user *) data, @@ -1003,7 +1003,7 @@ static int mga_dma_iload(DRM_IOCTL_ARGS) drm_mga_iload_t iload; DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(iload, (drm_mga_iload_t __user *) data, sizeof(iload)); @@ -1045,7 +1045,7 @@ static int mga_dma_blit(DRM_IOCTL_ARGS) drm_mga_blit_t blit; DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(blit, (drm_mga_blit_t __user *) data, sizeof(blit)); diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 9e11f9b7..7ecfadd2 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -47,7 +47,7 @@ struct mem_block { struct mem_block *prev; uint64_t start; uint64_t size; - DRMFILE filp; /* 0: free, -1: heap, other: real files */ + struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ int flags; drm_local_map_t *map; drm_handle_t map_handle; @@ -95,7 +95,7 @@ struct nouveau_gpuobj_ref { struct nouveau_fifo { /* owner of this fifo */ - DRMFILE filp; + struct drm_file *file_priv; /* mapping of the fifo itself */ drm_local_map_t *map; /* mapping of the regs controling the fifo */ @@ -263,7 +263,8 @@ struct drm_nouveau_private { }; /* nouveau_state.c */ -extern void nouveau_preclose(struct drm_device * dev, DRMFILE filp); +extern void nouveau_preclose(struct drm_device * dev, + struct drm_file *file_priv); extern int nouveau_load(struct drm_device *dev, unsigned long flags); extern int nouveau_firstopen(struct drm_device *dev); extern void nouveau_lastclose(struct drm_device *dev); @@ -278,20 +279,25 @@ extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start, uint64_t size); extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *, uint64_t size, int align2, - DRMFILE); + struct drm_file *file_priv); extern void nouveau_mem_takedown(struct mem_block **heap); extern void nouveau_mem_free_block(struct mem_block *); extern uint64_t nouveau_mem_fb_amount(struct drm_device *dev); -extern void nouveau_mem_release(DRMFILE filp, struct mem_block *heap); +extern void nouveau_mem_release(struct drm_file *file_priv, + struct mem_block *heap); extern int nouveau_ioctl_mem_alloc(DRM_IOCTL_ARGS); extern int nouveau_ioctl_mem_free(DRM_IOCTL_ARGS); -extern struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment, uint64_t size, int flags, DRMFILE filp); +extern struct mem_block* nouveau_mem_alloc(struct drm_device *dev, + int alignment, uint64_t size, + int flags, + struct drm_file *file_priv); extern void nouveau_mem_free(struct drm_device* dev, struct mem_block*); extern int nouveau_mem_init(struct drm_device *dev); extern void nouveau_mem_close(struct drm_device *dev); /* nouveau_notifier.c */ -extern int nouveau_notifier_init_channel(struct drm_device *, int channel, DRMFILE); +extern int nouveau_notifier_init_channel(struct drm_device *, int channel, + struct drm_file *file_priv); extern void nouveau_notifier_takedown_channel(struct drm_device *, int channel); extern int nouveau_notifier_alloc(struct drm_device *, int channel, uint32_t handle, int cout, uint32_t *offset); @@ -301,8 +307,10 @@ extern int nouveau_ioctl_notifier_alloc(DRM_IOCTL_ARGS); extern int nouveau_fifo_init(struct drm_device *dev); extern int nouveau_fifo_number(struct drm_device *dev); extern int nouveau_fifo_ctx_size(struct drm_device *dev); -extern void nouveau_fifo_cleanup(struct drm_device *dev, DRMFILE filp); -extern int nouveau_fifo_owner(struct drm_device *dev, DRMFILE filp, int channel); +extern void nouveau_fifo_cleanup(struct drm_device *dev, + struct drm_file *file_priv); +extern int nouveau_fifo_owner(struct drm_device *dev, + struct drm_file *file_priv, int channel); extern void nouveau_fifo_free(struct drm_device *dev, int channel); /* nouveau_object.c */ @@ -473,7 +481,7 @@ extern int nv04_timer_init(struct drm_device *dev); extern uint64_t nv04_timer_read(struct drm_device *dev); extern void nv04_timer_takedown(struct drm_device *dev); -extern long nouveau_compat_ioctl(struct file *filp, unsigned int cmd, +extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg); #if defined(__powerpc__) diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index e3a6674d..8731c6a1 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -204,7 +204,7 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) cb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size, config->cmdbuf.location | NOUVEAU_MEM_MAPPED, - (DRMFILE)-2); + (struct drm_file *)-2); if (!cb) { DRM_ERROR("Couldn't allocate DMA command buffer.\n"); return -ENOMEM; @@ -264,7 +264,8 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) } /* allocates and initializes a fifo for user space consumption */ -int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret, DRMFILE filp, +int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret, + struct drm_file *file_priv, uint32_t vram_handle, uint32_t tt_handle) { int ret; @@ -298,7 +299,7 @@ int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret, DRMFILE filp, return -ENOMEM; dev_priv->fifo_alloc_count++; chan = dev_priv->fifos[channel]; - chan->filp = filp; + chan->file_priv = file_priv; DRM_INFO("Allocating FIFO number %d\n", channel); @@ -317,7 +318,7 @@ int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret, DRMFILE filp, } /* Allocate space for per-channel fixed notifier memory */ - ret = nouveau_notifier_init_channel(dev, channel, filp); + ret = nouveau_notifier_init_channel(dev, channel, file_priv); if (ret) { nouveau_fifo_free(dev, channel); return ret; @@ -441,20 +442,22 @@ void nouveau_fifo_free(struct drm_device *dev, int channel) drm_free(chan, sizeof(*chan), DRM_MEM_DRIVER); } -/* cleanups all the fifos from filp */ -void nouveau_fifo_cleanup(struct drm_device *dev, DRMFILE filp) +/* cleanups all the fifos from file_priv */ +void nouveau_fifo_cleanup(struct drm_device *dev, struct drm_file *file_priv) { int i; struct drm_nouveau_private *dev_priv = dev->dev_private; - DRM_DEBUG("clearing FIFO enables from filp\n"); + DRM_DEBUG("clearing FIFO enables from file_priv\n"); for(i=0;ififos[i] && dev_priv->fifos[i]->filp==filp) + if (dev_priv->fifos[i] && + dev_priv->fifos[i]->file_priv==file_priv) nouveau_fifo_free(dev,i); } int -nouveau_fifo_owner(struct drm_device *dev, DRMFILE filp, int channel) +nouveau_fifo_owner(struct drm_device *dev, struct drm_file *file_priv, + int channel) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -462,7 +465,7 @@ nouveau_fifo_owner(struct drm_device *dev, DRMFILE filp, int channel) return 0; if (dev_priv->fifos[channel] == NULL) return 0; - return (dev_priv->fifos[channel]->filp == filp); + return (dev_priv->fifos[channel]->file_priv == file_priv); } /*********************************** @@ -485,7 +488,7 @@ static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) if (init.fb_ctxdma_handle == ~0 || init.tt_ctxdma_handle == ~0) return -EINVAL; - res = nouveau_fifo_alloc(dev, &init.channel, filp, + res = nouveau_fifo_alloc(dev, &init.channel, file_priv, init.fb_ctxdma_handle, init.tt_ctxdma_handle); if (res) diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 143378ff..6a4818c5 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -36,7 +36,7 @@ #include "nouveau_drv.h" static struct mem_block *split_block(struct mem_block *p, uint64_t start, uint64_t size, - DRMFILE filp) + struct drm_file *file_priv) { /* Maybe cut off the start of an existing block */ if (start > p->start) { @@ -46,7 +46,7 @@ static struct mem_block *split_block(struct mem_block *p, uint64_t start, uint64 goto out; newblock->start = start; newblock->size = p->size - (start - p->start); - newblock->filp = NULL; + newblock->file_priv = NULL; newblock->next = p->next; newblock->prev = p; p->next->prev = newblock; @@ -63,7 +63,7 @@ static struct mem_block *split_block(struct mem_block *p, uint64_t start, uint64 goto out; newblock->start = start + size; newblock->size = p->size - size; - newblock->filp = NULL; + newblock->file_priv = NULL; newblock->next = p->next; newblock->prev = p; p->next->prev = newblock; @@ -73,12 +73,14 @@ static struct mem_block *split_block(struct mem_block *p, uint64_t start, uint64 out: /* Our block is in the middle */ - p->filp = filp; + p->file_priv = file_priv; return p; } -struct mem_block *nouveau_mem_alloc_block(struct mem_block *heap, uint64_t size, - int align2, DRMFILE filp) +struct mem_block *nouveau_mem_alloc_block(struct mem_block *heap, + uint64_t size, + int align2, + struct drm_file *file_priv) { struct mem_block *p; uint64_t mask = (1 << align2) - 1; @@ -88,8 +90,8 @@ struct mem_block *nouveau_mem_alloc_block(struct mem_block *heap, uint64_t size, list_for_each(p, heap) { uint64_t start = (p->start + mask) & ~mask; - if (p->filp == 0 && start + size <= p->start + p->size) - return split_block(p, start, size, filp); + if (p->file_priv == 0 && start + size <= p->start + p->size) + return split_block(p, start, size, file_priv); } return NULL; @@ -108,12 +110,12 @@ static struct mem_block *find_block(struct mem_block *heap, uint64_t start) void nouveau_mem_free_block(struct mem_block *p) { - p->filp = NULL; + p->file_priv = NULL; - /* Assumes a single contiguous range. Needs a special filp in + /* Assumes a single contiguous range. Needs a special file_priv in * 'heap' to stop it being subsumed. */ - if (p->next->filp == 0) { + if (p->next->file_priv == 0) { struct mem_block *q = p->next; p->size += q->size; p->next = q->next; @@ -121,7 +123,7 @@ void nouveau_mem_free_block(struct mem_block *p) drm_free(q, sizeof(*q), DRM_MEM_BUFS); } - if (p->prev->filp == 0) { + if (p->prev->file_priv == 0) { struct mem_block *q = p->prev; q->size += p->size; q->next = p->next; @@ -148,19 +150,19 @@ int nouveau_mem_init_heap(struct mem_block **heap, uint64_t start, blocks->start = start; blocks->size = size; - blocks->filp = NULL; + blocks->file_priv = NULL; blocks->next = blocks->prev = *heap; memset(*heap, 0, sizeof(**heap)); - (*heap)->filp = (DRMFILE) - 1; + (*heap)->file_priv = (struct drm_file *) - 1; (*heap)->next = (*heap)->prev = blocks; return 0; } /* - * Free all blocks associated with the releasing filp + * Free all blocks associated with the releasing file_priv */ -void nouveau_mem_release(DRMFILE filp, struct mem_block *heap) +void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap) { struct mem_block *p; @@ -168,15 +170,16 @@ void nouveau_mem_release(DRMFILE filp, struct mem_block *heap) return; list_for_each(p, heap) { - if (p->filp == filp) - p->filp = NULL; + if (p->file_priv == file_priv) + p->file_priv = NULL; } - /* Assumes a single contiguous range. Needs a special filp in + /* Assumes a single contiguous range. Needs a special file_priv in * 'heap' to stop it being subsumed. */ list_for_each(p, heap) { - while ((p->filp == 0) && (p->next->filp == 0) && (p->next!=heap)) { + while ((p->file_priv == 0) && (p->next->file_priv == 0) && + (p->next!=heap)) { struct mem_block *q = p->next; p->size += q->size; p->next = q->next; @@ -424,7 +427,9 @@ int nouveau_mem_init(struct drm_device *dev) return 0; } -struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment, uint64_t size, int flags, DRMFILE filp) +struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment, + uint64_t size, int flags, + struct drm_file *file_priv) { struct mem_block *block; int type; @@ -453,13 +458,14 @@ struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment, uint6 #define NOUVEAU_MEM_ALLOC_AGP {\ type=NOUVEAU_MEM_AGP;\ block = nouveau_mem_alloc_block(dev_priv->agp_heap, size,\ - alignment, filp);\ + alignment, file_priv); \ if (block) goto alloc_ok;\ } #define NOUVEAU_MEM_ALLOC_PCI {\ type = NOUVEAU_MEM_PCI;\ - block = nouveau_mem_alloc_block(dev_priv->pci_heap, size, alignment, filp);\ + block = nouveau_mem_alloc_block(dev_priv->pci_heap, size, \ + alignment, file_priv); \ if ( block ) goto alloc_ok;\ } @@ -467,11 +473,12 @@ struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment, uint6 type=NOUVEAU_MEM_FB;\ if (!(flags&NOUVEAU_MEM_MAPPED)) {\ block = nouveau_mem_alloc_block(dev_priv->fb_nomap_heap,\ - size, alignment, filp); \ + size, alignment, \ + file_priv); \ if (block) goto alloc_ok;\ }\ block = nouveau_mem_alloc_block(dev_priv->fb_heap, size,\ - alignment, filp);\ + alignment, file_priv);\ if (block) goto alloc_ok;\ } @@ -556,7 +563,8 @@ int nouveau_ioctl_mem_alloc(DRM_IOCTL_ARGS) (struct drm_nouveau_mem_alloc_t __user *) data, sizeof(alloc)); - block=nouveau_mem_alloc(dev, alloc.alignment, alloc.size, alloc.flags, filp); + block=nouveau_mem_alloc(dev, alloc.alignment, alloc.size, alloc.flags, + file_priv); if (!block) return -ENOMEM; alloc.map_handle=block->map_handle; @@ -589,7 +597,7 @@ int nouveau_ioctl_mem_free(DRM_IOCTL_ARGS) block = find_block(dev_priv->pci_heap, memfree.offset); if (!block) return -EFAULT; - if (block->filp != filp) + if (block->file_priv != file_priv) return -EPERM; nouveau_mem_free(dev, block); diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index 425e471c..6a78bb23 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -30,7 +30,8 @@ #include "nouveau_drv.h" int -nouveau_notifier_init_channel(struct drm_device *dev, int channel, DRMFILE filp) +nouveau_notifier_init_channel(struct drm_device *dev, int channel, + struct drm_file *file_priv) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; @@ -44,7 +45,8 @@ nouveau_notifier_init_channel(struct drm_device *dev, int channel, DRMFILE filp) flags = NOUVEAU_MEM_FB; flags |= NOUVEAU_MEM_MAPPED; - chan->notifier_block = nouveau_mem_alloc(dev, 0, PAGE_SIZE, flags,filp); + chan->notifier_block = nouveau_mem_alloc(dev, 0, PAGE_SIZE, flags, + file_priv); if (!chan->notifier_block) return -ENOMEM; @@ -87,7 +89,8 @@ nouveau_notifier_alloc(struct drm_device *dev, int channel, uint32_t handle, return -EINVAL; } - mem = nouveau_mem_alloc_block(chan->notifier_heap, 32, 0, chan->filp); + mem = nouveau_mem_alloc_block(chan->notifier_heap, 32, 0, + chan->file_priv); if (!mem) { DRM_ERROR("Channel %d notifier block full\n", channel); return -ENOMEM; @@ -135,7 +138,7 @@ nouveau_ioctl_notifier_alloc(DRM_IOCTL_ARGS) (struct drm_nouveau_notifier_alloc __user*)data, sizeof(na)); - if (!nouveau_fifo_owner(dev, filp, na.channel)) { + if (!nouveau_fifo_owner(dev, file_priv, na.channel)) { DRM_ERROR("pid %d doesn't own channel %d\n", DRM_CURRENTPID, na.channel); return -EPERM; diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 30d515f0..f11cc115 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -241,7 +241,7 @@ nouveau_gpuobj_new(struct drm_device *dev, int channel, int size, int align, /* Allocate a chunk of the PRAMIN aperture */ gpuobj->im_pramin = nouveau_mem_alloc_block(pramin, size, drm_order(align), - (DRMFILE)-2); + (struct drm_file *)-2); if (!gpuobj->im_pramin) { nouveau_gpuobj_del(dev, &gpuobj); return -ENOMEM; @@ -1035,7 +1035,7 @@ int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS) (struct drm_nouveau_grobj_alloc_t __user*)data, sizeof(init)); - if (!nouveau_fifo_owner(dev, filp, init.channel)) { + if (!nouveau_fifo_owner(dev, file_priv, init.channel)) { DRM_ERROR("pid %d doesn't own channel %d\n", DRM_CURRENTPID, init.channel); return -EINVAL; diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index b6459957..aea6bcf5 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -353,15 +353,16 @@ static void nouveau_card_takedown(struct drm_device *dev) } } -/* here a client dies, release the stuff that was allocated for its filp */ -void nouveau_preclose(struct drm_device *dev, DRMFILE filp) +/* here a client dies, release the stuff that was allocated for its + * file_priv */ +void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv) { struct drm_nouveau_private *dev_priv = dev->dev_private; - nouveau_fifo_cleanup(dev, filp); - nouveau_mem_release(filp,dev_priv->fb_heap); - nouveau_mem_release(filp,dev_priv->agp_heap); - nouveau_mem_release(filp,dev_priv->pci_heap); + nouveau_fifo_cleanup(dev, file_priv); + nouveau_mem_release(file_priv,dev_priv->fb_heap); + nouveau_mem_release(file_priv,dev_priv->agp_heap); + nouveau_mem_release(file_priv,dev_priv->pci_heap); } /* first module load, setup the mmio/fb mapping */ diff --git a/shared-core/nv50_instmem.c b/shared-core/nv50_instmem.c index ad77f441..c26b1db5 100644 --- a/shared-core/nv50_instmem.c +++ b/shared-core/nv50_instmem.c @@ -179,7 +179,7 @@ nv50_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uin gpuobj->im_backing = nouveau_mem_alloc(dev, NV50_INSTMEM_PAGE_SIZE, *sz, NOUVEAU_MEM_FB, - (DRMFILE)-2); + (struct drm_file *)-2); if (!gpuobj->im_backing) { DRM_ERROR("Couldn't allocate vram to back PRAMIN pages\n"); return -ENOMEM; diff --git a/shared-core/r128_cce.c b/shared-core/r128_cce.c index 51b290b4..f91e9031 100644 --- a/shared-core/r128_cce.c +++ b/shared-core/r128_cce.c @@ -630,7 +630,7 @@ int r128_cce_init(DRM_IOCTL_ARGS) DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(init, (drm_r128_init_t __user *) data, sizeof(init)); @@ -651,7 +651,7 @@ int r128_cce_start(DRM_IOCTL_ARGS) drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) { DRM_DEBUG("%s while CCE running\n", __FUNCTION__); @@ -674,7 +674,7 @@ int r128_cce_stop(DRM_IOCTL_ARGS) int ret; DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *) data, sizeof(stop)); @@ -715,7 +715,7 @@ int r128_cce_reset(DRM_IOCTL_ARGS) drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { DRM_DEBUG("%s called before init done\n", __FUNCTION__); @@ -736,7 +736,7 @@ int r128_cce_idle(DRM_IOCTL_ARGS) drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (dev_priv->cce_running) { r128_do_cce_flush(dev_priv); @@ -750,7 +750,7 @@ int r128_engine_reset(DRM_IOCTL_ARGS) DRM_DEVICE; DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); return r128_do_engine_reset(dev); } @@ -826,7 +826,7 @@ static struct drm_buf *r128_freelist_get(struct drm_device * dev) for (i = 0; i < dma->buf_count; i++) { buf = dma->buflist[i]; buf_priv = buf->dev_private; - if (buf->filp == 0) + if (buf->file_priv == 0) return buf; } @@ -884,7 +884,9 @@ int r128_wait_ring(drm_r128_private_t * dev_priv, int n) return -EBUSY; } -static int r128_cce_get_buffers(DRMFILE filp, struct drm_device * dev, struct drm_dma * d) +static int r128_cce_get_buffers(struct drm_device * dev, + struct drm_file *file_priv, + struct drm_dma * d) { int i; struct drm_buf *buf; @@ -894,7 +896,7 @@ static int r128_cce_get_buffers(DRMFILE filp, struct drm_device * dev, struct dr if (!buf) return -EAGAIN; - buf->filp = filp; + buf->file_priv = file_priv; if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, sizeof(buf->idx))) @@ -916,7 +918,7 @@ int r128_cce_buffers(DRM_IOCTL_ARGS) struct drm_dma __user *argp = (void __user *)data; struct drm_dma d; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); @@ -939,7 +941,7 @@ int r128_cce_buffers(DRM_IOCTL_ARGS) d.granted_count = 0; if (d.request_count) { - ret = r128_cce_get_buffers(filp, dev, &d); + ret = r128_cce_get_buffers(dev, file_priv, &d); } DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); diff --git a/shared-core/r128_drv.h b/shared-core/r128_drv.h index 077b2763..6eb59e33 100644 --- a/shared-core/r128_drv.h +++ b/shared-core/r128_drv.h @@ -156,7 +156,8 @@ extern void r128_driver_irq_preinstall(struct drm_device * dev); extern void r128_driver_irq_postinstall(struct drm_device * dev); extern void r128_driver_irq_uninstall(struct drm_device * dev); extern void r128_driver_lastclose(struct drm_device * dev); -extern void r128_driver_preclose(struct drm_device * dev, DRMFILE filp); +extern void r128_driver_preclose(struct drm_device * dev, + struct drm_file *file_priv); extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); diff --git a/shared-core/r128_state.c b/shared-core/r128_state.c index 6b19c4d3..4c244377 100644 --- a/shared-core/r128_state.c +++ b/shared-core/r128_state.c @@ -776,8 +776,9 @@ static void r128_cce_dispatch_indices(struct drm_device * dev, sarea_priv->nbox = 0; } -static int r128_cce_dispatch_blit(DRMFILE filp, - struct drm_device * dev, drm_r128_blit_t * blit) +static int r128_cce_dispatch_blit(struct drm_device * dev, + struct drm_file *file_priv, + drm_r128_blit_t * blit) { drm_r128_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; @@ -829,9 +830,9 @@ static int r128_cce_dispatch_blit(DRMFILE filp, buf = dma->buflist[blit->idx]; buf_priv = buf->dev_private; - if (buf->filp != filp) { + if (buf->file_priv != file_priv) { DRM_ERROR("process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp); + DRM_CURRENTPID, buf->file_priv); return -EINVAL; } if (buf->pending) { @@ -1249,7 +1250,7 @@ static int r128_cce_clear(DRM_IOCTL_ARGS) drm_r128_clear_t clear; DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(clear, (drm_r128_clear_t __user *) data, sizeof(clear)); @@ -1315,7 +1316,7 @@ static int r128_cce_flip(DRM_IOCTL_ARGS) drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG("%s\n", __FUNCTION__); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); RING_SPACE_TEST_WITH_RETURN(dev_priv); @@ -1335,7 +1336,7 @@ static int r128_cce_swap(DRM_IOCTL_ARGS) drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; DRM_DEBUG("%s\n", __FUNCTION__); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); RING_SPACE_TEST_WITH_RETURN(dev_priv); @@ -1359,7 +1360,7 @@ static int r128_cce_vertex(DRM_IOCTL_ARGS) drm_r128_buf_priv_t *buf_priv; drm_r128_vertex_t vertex; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); @@ -1389,9 +1390,9 @@ static int r128_cce_vertex(DRM_IOCTL_ARGS) buf = dma->buflist[vertex.idx]; buf_priv = buf->dev_private; - if (buf->filp != filp) { + if (buf->file_priv != file_priv) { DRM_ERROR("process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp); + DRM_CURRENTPID, buf->file_priv); return -EINVAL; } if (buf->pending) { @@ -1419,7 +1420,7 @@ static int r128_cce_indices(DRM_IOCTL_ARGS) drm_r128_indices_t elts; int count; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); @@ -1448,9 +1449,9 @@ static int r128_cce_indices(DRM_IOCTL_ARGS) buf = dma->buflist[elts.idx]; buf_priv = buf->dev_private; - if (buf->filp != filp) { + if (buf->file_priv != file_priv) { DRM_ERROR("process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp); + DRM_CURRENTPID, buf->file_priv); return -EINVAL; } if (buf->pending) { @@ -1488,7 +1489,7 @@ static int r128_cce_blit(DRM_IOCTL_ARGS) drm_r128_blit_t blit; int ret; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(blit, (drm_r128_blit_t __user *) data, sizeof(blit)); @@ -1504,7 +1505,7 @@ static int r128_cce_blit(DRM_IOCTL_ARGS) RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); - ret = r128_cce_dispatch_blit(filp, dev, &blit); + ret = r128_cce_dispatch_blit(dev, file_priv, &blit); COMMIT_RING(); return ret; @@ -1517,7 +1518,7 @@ static int r128_cce_depth(DRM_IOCTL_ARGS) drm_r128_depth_t depth; int ret; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(depth, (drm_r128_depth_t __user *) data, sizeof(depth)); @@ -1551,7 +1552,7 @@ static int r128_cce_stipple(DRM_IOCTL_ARGS) drm_r128_stipple_t stipple; u32 mask[32]; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(stipple, (drm_r128_stipple_t __user *) data, sizeof(stipple)); @@ -1579,7 +1580,7 @@ static int r128_cce_indirect(DRM_IOCTL_ARGS) RING_LOCALS; #endif - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); @@ -1601,9 +1602,9 @@ static int r128_cce_indirect(DRM_IOCTL_ARGS) buf = dma->buflist[indirect.idx]; buf_priv = buf->dev_private; - if (buf->filp != filp) { + if (buf->file_priv != file_priv) { DRM_ERROR("process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp); + DRM_CURRENTPID, buf->file_priv); return -EINVAL; } if (buf->pending) { @@ -1675,7 +1676,7 @@ static int r128_getparam(DRM_IOCTL_ARGS) return 0; } -void r128_driver_preclose(struct drm_device * dev, DRMFILE filp) +void r128_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) { if (dev->dev_private) { drm_r128_private_t *dev_priv = dev->dev_private; diff --git a/shared-core/r300_cmdbuf.c b/shared-core/r300_cmdbuf.c index 8fee22e9..fe46c2d2 100644 --- a/shared-core/r300_cmdbuf.c +++ b/shared-core/r300_cmdbuf.c @@ -779,8 +779,7 @@ static int r300_scratch(drm_radeon_private_t *dev_priv, * Called by the ioctl handler function radeon_cp_cmdbuf. */ int r300_do_cp_cmdbuf(struct drm_device *dev, - DRMFILE filp, - struct drm_file *filp_priv, + struct drm_file *file_priv, drm_radeon_kcmd_buffer_t *cmdbuf) { drm_radeon_private_t *dev_priv = dev->dev_private; @@ -883,9 +882,10 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, } buf = dma->buflist[idx]; - if (buf->filp != filp || buf->pending) { + if (buf->file_priv != file_priv || buf->pending) { DRM_ERROR("bad buffer %p %p %d\n", - buf->filp, filp, buf->pending); + buf->file_priv, file_priv, + buf->pending); ret = -EINVAL; goto cleanup; } diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 723d41c3..dd87f009 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -1843,7 +1843,7 @@ int radeon_cp_init(DRM_IOCTL_ARGS) DRM_DEVICE; drm_radeon_init_t init; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data, sizeof(init)); @@ -1869,7 +1869,7 @@ int radeon_cp_start(DRM_IOCTL_ARGS) drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (dev_priv->cp_running) { DRM_DEBUG("%s while CP running\n", __FUNCTION__); @@ -1897,7 +1897,7 @@ int radeon_cp_stop(DRM_IOCTL_ARGS) int ret; DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data, sizeof(stop)); @@ -1989,7 +1989,7 @@ int radeon_cp_reset(DRM_IOCTL_ARGS) drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { DRM_DEBUG("%s called before init done\n", __FUNCTION__); @@ -2010,7 +2010,7 @@ int radeon_cp_idle(DRM_IOCTL_ARGS) drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); return radeon_do_cp_idle(dev_priv); } @@ -2029,7 +2029,7 @@ int radeon_engine_reset(DRM_IOCTL_ARGS) DRM_DEVICE; DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); return radeon_do_engine_reset(dev); } @@ -2086,8 +2086,9 @@ struct drm_buf *radeon_freelist_get(struct drm_device * dev) for (i = start; i < dma->buf_count; i++) { buf = dma->buflist[i]; buf_priv = buf->dev_private; - if (buf->filp == 0 || (buf->pending && - buf_priv->age <= done_age)) { + if (buf->file_priv == NULL || (buf->pending && + buf_priv->age <= + done_age)) { dev_priv->stats.requested_bufs++; buf->pending = 0; return buf; @@ -2126,8 +2127,9 @@ struct drm_buf *radeon_freelist_get(struct drm_device * dev) for (i = start; i < dma->buf_count; i++) { buf = dma->buflist[i]; buf_priv = buf->dev_private; - if (buf->filp == 0 || (buf->pending && - buf_priv->age <= done_age)) { + if (buf->file_priv == 0 || (buf->pending && + buf_priv->age <= + done_age)) { dev_priv->stats.requested_bufs++; buf->pending = 0; return buf; @@ -2190,7 +2192,8 @@ int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) return -EBUSY; } -static int radeon_cp_get_buffers(DRMFILE filp, struct drm_device * dev, +static int radeon_cp_get_buffers(struct drm_device *dev, + struct drm_file *file_priv, struct drm_dma * d) { int i; @@ -2201,7 +2204,7 @@ static int radeon_cp_get_buffers(DRMFILE filp, struct drm_device * dev, if (!buf) return -EBUSY; /* NOTE: broken client */ - buf->filp = filp; + buf->file_priv = file_priv; if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, sizeof(buf->idx))) @@ -2223,7 +2226,7 @@ int radeon_cp_buffers(DRM_IOCTL_ARGS) struct drm_dma __user *argp = (void __user *)data; struct drm_dma d; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); @@ -2246,7 +2249,7 @@ int radeon_cp_buffers(DRM_IOCTL_ARGS) d.granted_count = 0; if (d.request_count) { - ret = radeon_cp_get_buffers(filp, dev, &d); + ret = radeon_cp_get_buffers(dev, file_priv, &d); } DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 2dca1e70..631fe007 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -195,7 +195,7 @@ struct mem_block { struct mem_block *prev; int start; int size; - DRMFILE filp; /* 0: free, -1: heap, other: real files */ + struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ }; struct radeon_surface { @@ -210,7 +210,7 @@ struct radeon_virt_surface { u32 lower; u32 upper; u32 flags; - DRMFILE filp; + struct drm_file *file_priv; }; typedef struct drm_radeon_private { @@ -356,7 +356,8 @@ extern int radeon_mem_alloc(DRM_IOCTL_ARGS); extern int radeon_mem_free(DRM_IOCTL_ARGS); extern int radeon_mem_init_heap(DRM_IOCTL_ARGS); extern void radeon_mem_takedown(struct mem_block **heap); -extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap); +extern void radeon_mem_release(struct drm_file *file_priv, + struct mem_block *heap); /* radeon_irq.c */ extern int radeon_irq_emit(DRM_IOCTL_ARGS); @@ -377,18 +378,21 @@ extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); extern int radeon_driver_unload(struct drm_device *dev); extern int radeon_driver_firstopen(struct drm_device *dev); -extern void radeon_driver_preclose(struct drm_device * dev, DRMFILE filp); -extern void radeon_driver_postclose(struct drm_device * dev, struct drm_file * filp); +extern void radeon_driver_preclose(struct drm_device * dev, + struct drm_file *file_priv); +extern void radeon_driver_postclose(struct drm_device * dev, + struct drm_file *file_priv); extern void radeon_driver_lastclose(struct drm_device * dev); -extern int radeon_driver_open(struct drm_device * dev, struct drm_file * filp_priv); +extern int radeon_driver_open(struct drm_device * dev, + struct drm_file * file_priv); extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); /* r300_cmdbuf.c */ extern void r300_init_reg_flags(void); -extern int r300_do_cp_cmdbuf(struct drm_device *dev, DRMFILE filp, - struct drm_file* filp_priv, +extern int r300_do_cp_cmdbuf(struct drm_device *dev, + struct drm_file *file_priv, drm_radeon_kcmd_buffer_t* cmdbuf); /* Flags for stats.boxes diff --git a/shared-core/radeon_irq.c b/shared-core/radeon_irq.c index 8266d11a..140f9668 100644 --- a/shared-core/radeon_irq.c +++ b/shared-core/radeon_irq.c @@ -204,7 +204,7 @@ int radeon_irq_emit(DRM_IOCTL_ARGS) drm_radeon_irq_emit_t emit; int result; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); diff --git a/shared-core/radeon_mem.c b/shared-core/radeon_mem.c index 63d4b8c9..82d454ff 100644 --- a/shared-core/radeon_mem.c +++ b/shared-core/radeon_mem.c @@ -39,7 +39,7 @@ */ static struct mem_block *split_block(struct mem_block *p, int start, int size, - DRMFILE filp) + struct drm_file *file_priv) { /* Maybe cut off the start of an existing block */ if (start > p->start) { @@ -49,7 +49,7 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size, goto out; newblock->start = start; newblock->size = p->size - (start - p->start); - newblock->filp = NULL; + newblock->file_priv = NULL; newblock->next = p->next; newblock->prev = p; p->next->prev = newblock; @@ -66,7 +66,7 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size, goto out; newblock->start = start + size; newblock->size = p->size - size; - newblock->filp = NULL; + newblock->file_priv = NULL; newblock->next = p->next; newblock->prev = p; p->next->prev = newblock; @@ -76,20 +76,20 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size, out: /* Our block is in the middle */ - p->filp = filp; + p->file_priv = file_priv; return p; } static struct mem_block *alloc_block(struct mem_block *heap, int size, - int align2, DRMFILE filp) + int align2, struct drm_file *file_priv) { struct mem_block *p; int mask = (1 << align2) - 1; list_for_each(p, heap) { int start = (p->start + mask) & ~mask; - if (p->filp == 0 && start + size <= p->start + p->size) - return split_block(p, start, size, filp); + if (p->file_priv == 0 && start + size <= p->start + p->size) + return split_block(p, start, size, file_priv); } return NULL; @@ -108,12 +108,12 @@ static struct mem_block *find_block(struct mem_block *heap, int start) static void free_block(struct mem_block *p) { - p->filp = NULL; + p->file_priv = NULL; - /* Assumes a single contiguous range. Needs a special filp in + /* Assumes a single contiguous range. Needs a special file_priv in * 'heap' to stop it being subsumed. */ - if (p->next->filp == 0) { + if (p->next->file_priv == 0) { struct mem_block *q = p->next; p->size += q->size; p->next = q->next; @@ -121,7 +121,7 @@ static void free_block(struct mem_block *p) drm_free(q, sizeof(*q), DRM_MEM_BUFS); } - if (p->prev->filp == 0) { + if (p->prev->file_priv == 0) { struct mem_block *q = p->prev; q->size += p->size; q->next = p->next; @@ -147,18 +147,18 @@ static int init_heap(struct mem_block **heap, int start, int size) blocks->start = start; blocks->size = size; - blocks->filp = NULL; + blocks->file_priv = NULL; blocks->next = blocks->prev = *heap; memset(*heap, 0, sizeof(**heap)); - (*heap)->filp = (DRMFILE) - 1; + (*heap)->file_priv = (struct drm_file *) - 1; (*heap)->next = (*heap)->prev = blocks; return 0; } /* Free all blocks associated with the releasing file. */ -void radeon_mem_release(DRMFILE filp, struct mem_block *heap) +void radeon_mem_release(struct drm_file *file_priv, struct mem_block *heap) { struct mem_block *p; @@ -166,15 +166,15 @@ void radeon_mem_release(DRMFILE filp, struct mem_block *heap) return; list_for_each(p, heap) { - if (p->filp == filp) - p->filp = NULL; + if (p->file_priv == file_priv) + p->file_priv = NULL; } - /* Assumes a single contiguous range. Needs a special filp in + /* Assumes a single contiguous range. Needs a special file_priv in * 'heap' to stop it being subsumed. */ list_for_each(p, heap) { - while (p->filp == 0 && p->next->filp == 0) { + while (p->file_priv == 0 && p->next->file_priv == 0) { struct mem_block *q = p->next; p->size += q->size; p->next = q->next; @@ -242,7 +242,7 @@ int radeon_mem_alloc(DRM_IOCTL_ARGS) if (alloc.alignment < 12) alloc.alignment = 12; - block = alloc_block(*heap, alloc.size, alloc.alignment, filp); + block = alloc_block(*heap, alloc.size, alloc.alignment, file_priv); if (!block) return -ENOMEM; @@ -278,7 +278,7 @@ int radeon_mem_free(DRM_IOCTL_ARGS) if (!block) return -EFAULT; - if (block->filp != filp) + if (block->file_priv != file_priv) return -EPERM; free_block(block); diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c index e351656d..3ca49d6a 100644 --- a/shared-core/radeon_state.c +++ b/shared-core/radeon_state.c @@ -39,7 +39,7 @@ static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t * dev_priv, - struct drm_file * filp_priv, + struct drm_file *file_priv, u32 * offset) { u64 off = *offset; @@ -71,7 +71,7 @@ static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t * * magic offset we get from SETPARAM or calculated from fb_location */ if (off < (dev_priv->fb_size + dev_priv->gart_size)) { - radeon_priv = filp_priv->driver_priv; + radeon_priv = file_priv->driver_priv; off += radeon_priv->radeon_fb_delta; } @@ -90,13 +90,13 @@ static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t * static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * dev_priv, - struct drm_file * filp_priv, + struct drm_file *file_priv, int id, u32 *data) { switch (id) { case RADEON_EMIT_PP_MISC: - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + if (radeon_check_and_fixup_offset(dev_priv, file_priv, &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) { DRM_ERROR("Invalid depth buffer offset\n"); return -EINVAL; @@ -104,7 +104,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * break; case RADEON_EMIT_PP_CNTL: - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + if (radeon_check_and_fixup_offset(dev_priv, file_priv, &data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) { DRM_ERROR("Invalid colour buffer offset\n"); return -EINVAL; @@ -117,7 +117,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * case R200_EMIT_PP_TXOFFSET_3: case R200_EMIT_PP_TXOFFSET_4: case R200_EMIT_PP_TXOFFSET_5: - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + if (radeon_check_and_fixup_offset(dev_priv, file_priv, &data[0])) { DRM_ERROR("Invalid R200 texture offset\n"); return -EINVAL; @@ -127,7 +127,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * case RADEON_EMIT_PP_TXFILTER_0: case RADEON_EMIT_PP_TXFILTER_1: case RADEON_EMIT_PP_TXFILTER_2: - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + if (radeon_check_and_fixup_offset(dev_priv, file_priv, &data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) { DRM_ERROR("Invalid R100 texture offset\n"); return -EINVAL; @@ -143,7 +143,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * int i; for (i = 0; i < 5; i++) { if (radeon_check_and_fixup_offset(dev_priv, - filp_priv, + file_priv, &data[i])) { DRM_ERROR ("Invalid R200 cubic texture offset\n"); @@ -159,7 +159,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * int i; for (i = 0; i < 5; i++) { if (radeon_check_and_fixup_offset(dev_priv, - filp_priv, + file_priv, &data[i])) { DRM_ERROR ("Invalid R100 cubic texture offset\n"); @@ -264,7 +264,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * dev_priv, - struct drm_file *filp_priv, + struct drm_file *file_priv, drm_radeon_kcmd_buffer_t * cmdbuf, unsigned int *cmdsz) @@ -326,7 +326,8 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * i = 2; while ((k < narrays) && (i < (count + 2))) { i++; /* skip attribute field */ - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[i])) { + if (radeon_check_and_fixup_offset(dev_priv, file_priv, + &cmd[i])) { DRM_ERROR ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n", k, i); @@ -337,7 +338,9 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * if (k == narrays) break; /* have one more to process, they come in pairs */ - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[i])) { + if (radeon_check_and_fixup_offset(dev_priv, + file_priv, &cmd[i])) + { DRM_ERROR ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n", k, i); @@ -360,7 +363,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * DRM_ERROR("Invalid 3d packet for r200-class chip\n"); return -EINVAL; } - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[1])) { + if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[1])) { DRM_ERROR("Invalid rndr_gen_indx offset\n"); return -EINVAL; } @@ -375,7 +378,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]); return -EINVAL; } - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[2])) { + if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[2])) { DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]); return -EINVAL; } @@ -389,7 +392,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { offset = cmd[2] << 10; if (radeon_check_and_fixup_offset - (dev_priv, filp_priv, &offset)) { + (dev_priv, file_priv, &offset)) { DRM_ERROR("Invalid first packet offset\n"); return -EINVAL; } @@ -400,7 +403,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { offset = cmd[3] << 10; if (radeon_check_and_fixup_offset - (dev_priv, filp_priv, &offset)) { + (dev_priv, file_priv, &offset)) { DRM_ERROR("Invalid second packet offset\n"); return -EINVAL; } @@ -439,7 +442,7 @@ static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv, /* Emit 1.1 state */ static int radeon_emit_state(drm_radeon_private_t * dev_priv, - struct drm_file * filp_priv, + struct drm_file *file_priv, drm_radeon_context_regs_t * ctx, drm_radeon_texture_regs_t * tex, unsigned int dirty) @@ -448,13 +451,13 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv, DRM_DEBUG("dirty=0x%08x\n", dirty); if (dirty & RADEON_UPLOAD_CONTEXT) { - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + if (radeon_check_and_fixup_offset(dev_priv, file_priv, &ctx->rb3d_depthoffset)) { DRM_ERROR("Invalid depth buffer offset\n"); return -EINVAL; } - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + if (radeon_check_and_fixup_offset(dev_priv, file_priv, &ctx->rb3d_coloroffset)) { DRM_ERROR("Invalid depth buffer offset\n"); return -EINVAL; @@ -543,7 +546,7 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv, } if (dirty & RADEON_UPLOAD_TEX0) { - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex[0].pp_txoffset)) { DRM_ERROR("Invalid texture offset for unit 0\n"); return -EINVAL; @@ -563,7 +566,7 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv, } if (dirty & RADEON_UPLOAD_TEX1) { - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex[1].pp_txoffset)) { DRM_ERROR("Invalid texture offset for unit 1\n"); return -EINVAL; @@ -583,7 +586,7 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv, } if (dirty & RADEON_UPLOAD_TEX2) { - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex[2].pp_txoffset)) { DRM_ERROR("Invalid texture offset for unit 2\n"); return -EINVAL; @@ -608,7 +611,7 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv, /* Emit 1.2 state */ static int radeon_emit_state2(drm_radeon_private_t * dev_priv, - struct drm_file * filp_priv, + struct drm_file *file_priv, drm_radeon_state_t * state) { RING_LOCALS; @@ -621,7 +624,7 @@ static int radeon_emit_state2(drm_radeon_private_t * dev_priv, ADVANCE_RING(); } - return radeon_emit_state(dev_priv, filp_priv, &state->context, + return radeon_emit_state(dev_priv, file_priv, &state->context, state->tex, state->dirty); } @@ -1646,13 +1649,12 @@ static void radeon_cp_dispatch_indices(struct drm_device * dev, #define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE -static int radeon_cp_dispatch_texture(DRMFILE filp, - struct drm_device * dev, +static int radeon_cp_dispatch_texture(struct drm_device * dev, + struct drm_file *file_priv, drm_radeon_texture_t * tex, drm_radeon_tex_image_t * image) { drm_radeon_private_t *dev_priv = dev->dev_private; - struct drm_file *filp_priv; struct drm_buf *buf; u32 format; u32 *buffer; @@ -1664,9 +1666,7 @@ static int radeon_cp_dispatch_texture(DRMFILE filp, u32 offset; RING_LOCALS; - DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex->offset)) { + if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) { DRM_ERROR("Invalid destination offset\n"); return -EINVAL; } @@ -1841,7 +1841,7 @@ static int radeon_cp_dispatch_texture(DRMFILE filp, } #undef RADEON_COPY_MT - buf->filp = filp; + buf->file_priv = file_priv; buf->used = size; offset = dev_priv->gart_buffers_offset + buf->offset; BEGIN_RING(9); @@ -1929,7 +1929,8 @@ static void radeon_apply_surface_regs(int surf_index, * not always be available. */ static int alloc_surface(drm_radeon_surface_alloc_t *new, - drm_radeon_private_t *dev_priv, DRMFILE filp) + drm_radeon_private_t *dev_priv, + struct drm_file *file_priv) { struct radeon_virt_surface *s; int i; @@ -1959,7 +1960,7 @@ static int alloc_surface(drm_radeon_surface_alloc_t *new, /* find a virtual surface */ for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) - if (dev_priv->virt_surfaces[i].filp == 0) + if (dev_priv->virt_surfaces[i].file_priv == 0) break; if (i == 2 * RADEON_MAX_SURFACES) { return -1; @@ -1977,7 +1978,7 @@ static int alloc_surface(drm_radeon_surface_alloc_t *new, s->lower = new_lower; s->upper = new_upper; s->flags = new->flags; - s->filp = filp; + s->file_priv = file_priv; dev_priv->surfaces[i].refcount++; dev_priv->surfaces[i].lower = s->lower; radeon_apply_surface_regs(s->surface_index, dev_priv); @@ -1993,7 +1994,7 @@ static int alloc_surface(drm_radeon_surface_alloc_t *new, s->lower = new_lower; s->upper = new_upper; s->flags = new->flags; - s->filp = filp; + s->file_priv = file_priv; dev_priv->surfaces[i].refcount++; dev_priv->surfaces[i].upper = s->upper; radeon_apply_surface_regs(s->surface_index, dev_priv); @@ -2009,7 +2010,7 @@ static int alloc_surface(drm_radeon_surface_alloc_t *new, s->lower = new_lower; s->upper = new_upper; s->flags = new->flags; - s->filp = filp; + s->file_priv = file_priv; dev_priv->surfaces[i].refcount = 1; dev_priv->surfaces[i].lower = s->lower; dev_priv->surfaces[i].upper = s->upper; @@ -2023,7 +2024,8 @@ static int alloc_surface(drm_radeon_surface_alloc_t *new, return -1; } -static int free_surface(DRMFILE filp, drm_radeon_private_t * dev_priv, +static int free_surface(struct drm_file *file_priv, + drm_radeon_private_t * dev_priv, int lower) { struct radeon_virt_surface *s; @@ -2031,8 +2033,9 @@ static int free_surface(DRMFILE filp, drm_radeon_private_t * dev_priv, /* find the virtual surface */ for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) { s = &(dev_priv->virt_surfaces[i]); - if (s->filp) { - if ((lower == s->lower) && (filp == s->filp)) { + if (s->file_priv) { + if ((lower == s->lower) && (file_priv == s->file_priv)) + { if (dev_priv->surfaces[s->surface_index]. lower == s->lower) dev_priv->surfaces[s->surface_index]. @@ -2048,7 +2051,7 @@ static int free_surface(DRMFILE filp, drm_radeon_private_t * dev_priv, refcount == 0) dev_priv->surfaces[s->surface_index]. flags = 0; - s->filp = NULL; + s->file_priv = NULL; radeon_apply_surface_regs(s->surface_index, dev_priv); return 0; @@ -2058,13 +2061,13 @@ static int free_surface(DRMFILE filp, drm_radeon_private_t * dev_priv, return 1; } -static void radeon_surfaces_release(DRMFILE filp, +static void radeon_surfaces_release(struct drm_file *file_priv, drm_radeon_private_t * dev_priv) { int i; for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) { - if (dev_priv->virt_surfaces[i].filp == filp) - free_surface(filp, dev_priv, + if (dev_priv->virt_surfaces[i].file_priv == file_priv) + free_surface(file_priv, dev_priv, dev_priv->virt_surfaces[i].lower); } } @@ -2087,7 +2090,7 @@ static int radeon_surface_alloc(DRM_IOCTL_ARGS) (drm_radeon_surface_alloc_t __user *) data, sizeof(alloc)); - if (alloc_surface(&alloc, dev_priv, filp) == -1) + if (alloc_surface(&alloc, dev_priv, file_priv) == -1) return -EINVAL; else return 0; @@ -2107,7 +2110,7 @@ static int radeon_surface_free(DRM_IOCTL_ARGS) DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_surface_free_t __user *) data, sizeof(memfree)); - if (free_surface(filp, dev_priv, memfree.address)) + if (free_surface(file_priv, dev_priv, memfree.address)) return -EINVAL; else return 0; @@ -2122,7 +2125,7 @@ static int radeon_cp_clear(DRM_IOCTL_ARGS) drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(clear, (drm_radeon_clear_t __user *) data, sizeof(clear)); @@ -2178,7 +2181,7 @@ static int radeon_cp_flip(DRM_IOCTL_ARGS) drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); RING_SPACE_TEST_WITH_RETURN(dev_priv); @@ -2198,7 +2201,7 @@ static int radeon_cp_swap(DRM_IOCTL_ARGS) drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); RING_SPACE_TEST_WITH_RETURN(dev_priv); @@ -2216,14 +2219,13 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - struct drm_file *filp_priv; drm_radeon_sarea_t *sarea_priv; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; drm_radeon_vertex_t vertex; drm_radeon_tcl_prim_t prim; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); @@ -2232,8 +2234,6 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) sarea_priv = dev_priv->sarea_priv; - DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex_t __user *) data, sizeof(vertex)); @@ -2255,9 +2255,9 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) buf = dma->buflist[vertex.idx]; - if (buf->filp != filp) { + if (buf->file_priv != file_priv) { DRM_ERROR("process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp); + DRM_CURRENTPID, buf->file_priv); return -EINVAL; } if (buf->pending) { @@ -2271,7 +2271,7 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) buf->used = vertex.count; /* not used? */ if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { - if (radeon_emit_state(dev_priv, filp_priv, + if (radeon_emit_state(dev_priv, file_priv, &sarea_priv->context_state, sarea_priv->tex_state, sarea_priv->dirty)) { @@ -2306,7 +2306,6 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - struct drm_file *filp_priv; drm_radeon_sarea_t *sarea_priv; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; @@ -2314,7 +2313,7 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) drm_radeon_tcl_prim_t prim; int count; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); @@ -2322,8 +2321,6 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) } sarea_priv = dev_priv->sarea_priv; - DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - DRM_COPY_FROM_USER_IOCTL(elts, (drm_radeon_indices_t __user *) data, sizeof(elts)); @@ -2345,9 +2342,9 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) buf = dma->buflist[elts.idx]; - if (buf->filp != filp) { + if (buf->file_priv != file_priv) { DRM_ERROR("process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp); + DRM_CURRENTPID, buf->file_priv); return -EINVAL; } if (buf->pending) { @@ -2370,7 +2367,7 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) buf->used = elts.end; if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { - if (radeon_emit_state(dev_priv, filp_priv, + if (radeon_emit_state(dev_priv, file_priv, &sarea_priv->context_state, sarea_priv->tex_state, sarea_priv->dirty)) { @@ -2410,7 +2407,7 @@ static int radeon_cp_texture(DRM_IOCTL_ARGS) drm_radeon_tex_image_t image; int ret; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(tex, (drm_radeon_texture_t __user *) data, sizeof(tex)); @@ -2428,7 +2425,7 @@ static int radeon_cp_texture(DRM_IOCTL_ARGS) RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); - ret = radeon_cp_dispatch_texture(filp, dev, &tex, &image); + ret = radeon_cp_dispatch_texture(dev, file_priv, &tex, &image); COMMIT_RING(); return ret; @@ -2441,7 +2438,7 @@ static int radeon_cp_stipple(DRM_IOCTL_ARGS) drm_radeon_stipple_t stipple; u32 mask[32]; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(stipple, (drm_radeon_stipple_t __user *) data, sizeof(stipple)); @@ -2466,7 +2463,7 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS) drm_radeon_indirect_t indirect; RING_LOCALS; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); @@ -2488,9 +2485,9 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS) buf = dma->buflist[indirect.idx]; - if (buf->filp != filp) { + if (buf->file_priv != file_priv) { DRM_ERROR("process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp); + DRM_CURRENTPID, buf->file_priv); return -EINVAL; } if (buf->pending) { @@ -2535,7 +2532,6 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - struct drm_file *filp_priv; drm_radeon_sarea_t *sarea_priv; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; @@ -2543,7 +2539,7 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) int i; unsigned char laststate; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); @@ -2552,8 +2548,6 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) sarea_priv = dev_priv->sarea_priv; - DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex2_t __user *) data, sizeof(vertex)); @@ -2571,9 +2565,9 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) buf = dma->buflist[vertex.idx]; - if (buf->filp != filp) { + if (buf->file_priv != file_priv) { DRM_ERROR("process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp); + DRM_CURRENTPID, buf->file_priv); return -EINVAL; } @@ -2600,7 +2594,7 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) sizeof(state))) return -EFAULT; - if (radeon_emit_state2(dev_priv, filp_priv, &state)) { + if (radeon_emit_state2(dev_priv, file_priv, &state)) { DRM_ERROR("radeon_emit_state2 failed\n"); return -EINVAL; } @@ -2638,7 +2632,7 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) } static int radeon_emit_packets(drm_radeon_private_t * dev_priv, - struct drm_file * filp_priv, + struct drm_file *file_priv, drm_radeon_cmd_header_t header, drm_radeon_kcmd_buffer_t *cmdbuf) { @@ -2658,7 +2652,7 @@ static int radeon_emit_packets(drm_radeon_private_t * dev_priv, return -EINVAL; } - if (radeon_check_and_fixup_packets(dev_priv, filp_priv, id, data)) { + if (radeon_check_and_fixup_packets(dev_priv, file_priv, id, data)) { DRM_ERROR("Packet verification failed\n"); return -EINVAL; } @@ -2764,7 +2758,7 @@ static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv, } static int radeon_emit_packet3(struct drm_device * dev, - struct drm_file * filp_priv, + struct drm_file *file_priv, drm_radeon_kcmd_buffer_t *cmdbuf) { drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2774,7 +2768,7 @@ static int radeon_emit_packet3(struct drm_device * dev, DRM_DEBUG("\n"); - if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv, + if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv, cmdbuf, &cmdsz))) { DRM_ERROR("Packet verification failed\n"); return ret; @@ -2790,7 +2784,7 @@ static int radeon_emit_packet3(struct drm_device * dev, } static int radeon_emit_packet3_cliprect(struct drm_device *dev, - struct drm_file *filp_priv, + struct drm_file *file_priv, drm_radeon_kcmd_buffer_t *cmdbuf, int orig_nbox) { @@ -2804,7 +2798,7 @@ static int radeon_emit_packet3_cliprect(struct drm_device *dev, DRM_DEBUG("\n"); - if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv, + if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv, cmdbuf, &cmdsz))) { DRM_ERROR("Packet verification failed\n"); return ret; @@ -2884,7 +2878,6 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - struct drm_file *filp_priv; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf = NULL; int idx; @@ -2893,15 +2886,13 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) int orig_nbox, orig_bufsz; char *kbuf = NULL; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_radeon_kcmd_buffer_t __user *) data, sizeof(cmdbuf)); @@ -2934,7 +2925,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) if (dev_priv->microcode_version == UCODE_R300) { int temp; - temp = r300_do_cp_cmdbuf(dev, filp, filp_priv, &cmdbuf); + temp = r300_do_cp_cmdbuf(dev, file_priv, &cmdbuf); if (orig_bufsz != 0) drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); @@ -2953,7 +2944,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) case RADEON_CMD_PACKET: DRM_DEBUG("RADEON_CMD_PACKET\n"); if (radeon_emit_packets - (dev_priv, filp_priv, header, &cmdbuf)) { + (dev_priv, file_priv, header, &cmdbuf)) { DRM_ERROR("radeon_emit_packets failed\n"); goto err; } @@ -2985,9 +2976,10 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) } buf = dma->buflist[idx]; - if (buf->filp != filp || buf->pending) { + if (buf->file_priv != file_priv || buf->pending) { DRM_ERROR("bad buffer %p %p %d\n", - buf->filp, filp, buf->pending); + buf->file_priv, file_priv, + buf->pending); goto err; } @@ -2996,7 +2988,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) case RADEON_CMD_PACKET3: DRM_DEBUG("RADEON_CMD_PACKET3\n"); - if (radeon_emit_packet3(dev, filp_priv, &cmdbuf)) { + if (radeon_emit_packet3(dev, file_priv, &cmdbuf)) { DRM_ERROR("radeon_emit_packet3 failed\n"); goto err; } @@ -3005,7 +2997,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) case RADEON_CMD_PACKET3_CLIP: DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n"); if (radeon_emit_packet3_cliprect - (dev, filp_priv, &cmdbuf, orig_nbox)) { + (dev, file_priv, &cmdbuf, orig_nbox)) { DRM_ERROR("radeon_emit_packet3_clip failed\n"); goto err; } @@ -3151,7 +3143,6 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - struct drm_file *filp_priv; drm_radeon_setparam_t sp; struct drm_radeon_driver_file_fields *radeon_priv; @@ -3160,14 +3151,12 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - DRM_COPY_FROM_USER_IOCTL(sp, (drm_radeon_setparam_t __user *) data, sizeof(sp)); switch (sp.param) { case RADEON_SETPARAM_FB_LOCATION: - radeon_priv = filp_priv->driver_priv; + radeon_priv = file_priv->driver_priv; radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value; break; case RADEON_SETPARAM_SWITCH_TILING: @@ -3213,14 +3202,15 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS) * * DRM infrastructure takes care of reclaiming dma buffers. */ -void radeon_driver_preclose(struct drm_device * dev, DRMFILE filp) +void radeon_driver_preclose(struct drm_device * dev, + struct drm_file *file_priv) { if (dev->dev_private) { drm_radeon_private_t *dev_priv = dev->dev_private; dev_priv->page_flipping = 0; - radeon_mem_release(filp, dev_priv->gart_heap); - radeon_mem_release(filp, dev_priv->fb_heap); - radeon_surfaces_release(filp, dev_priv); + radeon_mem_release(file_priv, dev_priv->gart_heap); + radeon_mem_release(file_priv, dev_priv->fb_heap); + radeon_surfaces_release(file_priv, dev_priv); } } @@ -3237,7 +3227,7 @@ void radeon_driver_lastclose(struct drm_device * dev) radeon_do_release(dev); } -int radeon_driver_open(struct drm_device * dev, struct drm_file * filp_priv) +int radeon_driver_open(struct drm_device * dev, struct drm_file *file_priv) { drm_radeon_private_t *dev_priv = dev->dev_private; struct drm_radeon_driver_file_fields *radeon_priv; @@ -3250,7 +3240,7 @@ int radeon_driver_open(struct drm_device * dev, struct drm_file * filp_priv) if (!radeon_priv) return -ENOMEM; - filp_priv->driver_priv = radeon_priv; + file_priv->driver_priv = radeon_priv; if (dev_priv) radeon_priv->radeon_fb_delta = dev_priv->fb_location; @@ -3259,10 +3249,10 @@ int radeon_driver_open(struct drm_device * dev, struct drm_file * filp_priv) return 0; } -void radeon_driver_postclose(struct drm_device * dev, struct drm_file * filp_priv) +void radeon_driver_postclose(struct drm_device * dev, struct drm_file *file_priv) { struct drm_radeon_driver_file_fields *radeon_priv = - filp_priv->driver_priv; + file_priv->driver_priv; drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); } diff --git a/shared-core/savage_bci.c b/shared-core/savage_bci.c index 1835d758..c2dee6f9 100644 --- a/shared-core/savage_bci.c +++ b/shared-core/savage_bci.c @@ -932,7 +932,7 @@ static int savage_bci_init(DRM_IOCTL_ARGS) DRM_DEVICE; drm_savage_init_t init; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(init, (drm_savage_init_t __user *)data, sizeof(init)); @@ -955,7 +955,7 @@ static int savage_bci_event_emit(DRM_IOCTL_ARGS) DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_emit_t __user *)data, sizeof(event)); @@ -1006,7 +1006,9 @@ static int savage_bci_event_wait(DRM_IOCTL_ARGS) * DMA buffer management */ -static int savage_bci_get_buffers(DRMFILE filp, struct drm_device *dev, struct drm_dma *d) +static int savage_bci_get_buffers(struct drm_device *dev, + struct drm_file *file_priv, + struct drm_dma *d) { struct drm_buf *buf; int i; @@ -1016,7 +1018,7 @@ static int savage_bci_get_buffers(DRMFILE filp, struct drm_device *dev, struct d if (!buf) return -EAGAIN; - buf->filp = filp; + buf->file_priv = file_priv; if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, sizeof(buf->idx))) @@ -1037,7 +1039,7 @@ int savage_bci_buffers(DRM_IOCTL_ARGS) struct drm_dma d; int ret = 0; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(d, (struct drm_dma __user *)data, sizeof(d)); @@ -1060,7 +1062,7 @@ int savage_bci_buffers(DRM_IOCTL_ARGS) d.granted_count = 0; if (d.request_count) { - ret = savage_bci_get_buffers(filp, dev, &d); + ret = savage_bci_get_buffers(dev, file_priv, &d); } DRM_COPY_TO_USER_IOCTL((struct drm_dma __user *)data, d, sizeof(d)); @@ -1068,7 +1070,7 @@ int savage_bci_buffers(DRM_IOCTL_ARGS) return ret; } -void savage_reclaim_buffers(struct drm_device *dev, DRMFILE filp) +void savage_reclaim_buffers(struct drm_device *dev, struct drm_file *file_priv) { struct drm_device_dma *dma = dev->dma; drm_savage_private_t *dev_priv = dev->dev_private; @@ -1087,7 +1089,7 @@ void savage_reclaim_buffers(struct drm_device *dev, DRMFILE filp) struct drm_buf *buf = dma->buflist[i]; drm_savage_buf_priv_t *buf_priv = buf->dev_private; - if (buf->filp == filp && buf_priv && + if (buf->file_priv == file_priv && buf_priv && buf_priv->next == NULL && buf_priv->prev == NULL) { uint16_t event; DRM_DEBUG("reclaimed from client\n"); @@ -1097,7 +1099,7 @@ void savage_reclaim_buffers(struct drm_device *dev, DRMFILE filp) } } - drm_core_reclaim_buffers(dev, filp); + drm_core_reclaim_buffers(dev, file_priv); } struct drm_ioctl_desc savage_ioctls[] = { diff --git a/shared-core/savage_drv.h b/shared-core/savage_drv.h index e9e2231f..3208cfcc 100644 --- a/shared-core/savage_drv.h +++ b/shared-core/savage_drv.h @@ -212,7 +212,8 @@ extern int savage_driver_load(struct drm_device *dev, unsigned long chipset); extern int savage_driver_firstopen(struct drm_device *dev); extern void savage_driver_lastclose(struct drm_device *dev); extern int savage_driver_unload(struct drm_device *dev); -extern void savage_reclaim_buffers(struct drm_device *dev, DRMFILE filp); +extern void savage_reclaim_buffers(struct drm_device *dev, + struct drm_file *file_priv); /* state functions */ extern void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv, diff --git a/shared-core/savage_state.c b/shared-core/savage_state.c index 753fe7d3..f5b9888c 100644 --- a/shared-core/savage_state.c +++ b/shared-core/savage_state.c @@ -968,7 +968,7 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_savage_cmdbuf_t __user *)data, sizeof(cmdbuf)); diff --git a/shared-core/sis_drv.h b/shared-core/sis_drv.h index 57d60133..a4a88fe1 100644 --- a/shared-core/sis_drv.h +++ b/shared-core/sis_drv.h @@ -67,7 +67,8 @@ typedef struct drm_sis_private { } drm_sis_private_t; extern int sis_idle(struct drm_device *dev); -extern void sis_reclaim_buffers_locked(struct drm_device *dev, struct file *filp); +extern void sis_reclaim_buffers_locked(struct drm_device *dev, + struct drm_file *file_priv); extern void sis_lastclose(struct drm_device *dev); #else diff --git a/shared-core/via_dma.c b/shared-core/via_dma.c index 895c78bf..7fe6d019 100644 --- a/shared-core/via_dma.c +++ b/shared-core/via_dma.c @@ -320,7 +320,7 @@ static int via_flush_ioctl(DRM_IOCTL_ARGS) { DRM_DEVICE; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); return via_driver_dma_quiescent(dev); } @@ -331,7 +331,7 @@ static int via_cmdbuffer(DRM_IOCTL_ARGS) drm_via_cmdbuffer_t cmdbuf; int ret; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data, sizeof(cmdbuf)); @@ -376,7 +376,7 @@ static int via_pci_cmdbuffer(DRM_IOCTL_ARGS) drm_via_cmdbuffer_t cmdbuf; int ret; - LOCK_TEST_WITH_RETURN(dev, filp); + LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data, sizeof(cmdbuf)); @@ -654,7 +654,7 @@ static int via_cmdbuf_size(DRM_IOCTL_ARGS) drm_via_private_t *dev_priv; DRM_DEBUG("via cmdbuf_size\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, file_priv); dev_priv = (drm_via_private_t *) dev->dev_private; diff --git a/shared-core/via_drv.h b/shared-core/via_drv.h index 05935c81..b7997942 100644 --- a/shared-core/via_drv.h +++ b/shared-core/via_drv.h @@ -181,7 +181,8 @@ extern void via_cleanup_futex(drm_via_private_t *dev_priv); extern void via_release_futex(drm_via_private_t *dev_priv, int context); #ifdef VIA_HAVE_CORE_MM -extern void via_reclaim_buffers_locked(struct drm_device *dev, struct file *filp); +extern void via_reclaim_buffers_locked(struct drm_device *dev, + struct drm_file *file_priv); extern void via_lastclose(struct drm_device *dev); #else extern int via_init_context(struct drm_device * dev, int context); -- cgit v1.2.3 From 5b38e134163cc375e91424c4688cc9328c6e9082 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 19 Jul 2007 17:11:11 -0700 Subject: Replace DRM_IOCTL_ARGS with (dev, data, file_priv) and remove DRM_DEVICE. The data is now in kernel space, copied in/out as appropriate according to the This results in DRM_COPY_{TO,FROM}_USER going away, and error paths to deal with those failures. This also means that XFree86 4.2.0 support for i810 DRM is lost. --- shared-core/i915_dma.c | 174 +++++++++------------ shared-core/i915_drv.h | 27 ++-- shared-core/i915_irq.c | 106 ++++++------- shared-core/i915_mem.c | 58 +++---- shared-core/mach64_dma.c | 51 +++--- shared-core/mach64_drv.h | 30 ++-- shared-core/mach64_state.c | 83 +++++----- shared-core/mga_dma.c | 86 ++++------- shared-core/mga_drv.h | 15 +- shared-core/mga_state.c | 139 +++++++---------- shared-core/nouveau_drv.h | 14 +- shared-core/nouveau_fifo.c | 59 ++++--- shared-core/nouveau_mem.c | 43 ++---- shared-core/nouveau_notifier.c | 19 +-- shared-core/nouveau_object.c | 27 ++-- shared-core/nouveau_state.c | 56 +++---- shared-core/r128_cce.c | 62 +++----- shared-core/r128_drv.h | 16 +- shared-core/r128_state.c | 208 +++++++++++-------------- shared-core/radeon_cp.c | 67 +++----- shared-core/radeon_drv.h | 28 ++-- shared-core/radeon_irq.c | 20 +-- shared-core/radeon_mem.c | 44 ++---- shared-core/radeon_state.c | 342 ++++++++++++++++++----------------------- shared-core/savage_bci.c | 68 +++----- shared-core/savage_drv.h | 4 +- shared-core/savage_state.c | 107 ++++++------- shared-core/sis_mm.c | 162 ++++++++----------- shared-core/via_dma.c | 99 +++++------- shared-core/via_drv.h | 18 +-- shared-core/via_irq.c | 34 ++-- shared-core/via_map.c | 12 +- shared-core/via_mm.c | 49 ++---- shared-core/via_video.c | 20 +-- 34 files changed, 987 insertions(+), 1360 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 05336d35..5d227d8b 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -250,23 +250,20 @@ static int i915_dma_resume(struct drm_device * dev) return 0; } -static int i915_dma_init(DRM_IOCTL_ARGS) +static int i915_dma_init(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_i915_private_t *dev_priv; - drm_i915_init_t init; + drm_i915_init_t *init = data; int retcode = 0; - DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data, - sizeof(init)); - - switch (init.func) { + switch (init->func) { case I915_INIT_DMA: dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER); if (dev_priv == NULL) return -ENOMEM; - retcode = i915_initialize(dev, dev_priv, &init); + retcode = i915_initialize(dev, dev_priv, init); break; case I915_CLEANUP_DMA: retcode = i915_dma_cleanup(dev); @@ -358,7 +355,8 @@ static int validate_cmd(int cmd) return ret; } -static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords) +static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, + int dwords) { drm_i915_private_t *dev_priv = dev->dev_private; int i; @@ -650,22 +648,22 @@ static int i915_quiescent(struct drm_device * dev) return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__); } -static int i915_flush_ioctl(DRM_IOCTL_ARGS) +static int i915_flush_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; LOCK_TEST_WITH_RETURN(dev, file_priv); return i915_quiescent(dev); } -static int i915_batchbuffer(DRM_IOCTL_ARGS) +static int i915_batchbuffer(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) dev_priv->sarea_priv; - drm_i915_batchbuffer_t batch; + drm_i915_batchbuffer_t *batch = data; int ret; if (!dev_priv->allow_batchbuffer) { @@ -673,51 +671,45 @@ static int i915_batchbuffer(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data, - sizeof(batch)); - DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n", - batch.start, batch.used, batch.num_cliprects); + batch->start, batch->used, batch->num_cliprects); LOCK_TEST_WITH_RETURN(dev, file_priv); - if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects, - batch.num_cliprects * - sizeof(struct drm_clip_rect))) + if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects, + batch->num_cliprects * + sizeof(struct drm_clip_rect))) return -EFAULT; - ret = i915_dispatch_batchbuffer(dev, &batch); + ret = i915_dispatch_batchbuffer(dev, batch); sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); return ret; } -static int i915_cmdbuffer(DRM_IOCTL_ARGS) +static int i915_cmdbuffer(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) dev_priv->sarea_priv; - drm_i915_cmdbuffer_t cmdbuf; + drm_i915_cmdbuffer_t *cmdbuf = data; int ret; - DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data, - sizeof(cmdbuf)); - DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n", - cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects); + cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); LOCK_TEST_WITH_RETURN(dev, file_priv); - if (cmdbuf.num_cliprects && - DRM_VERIFYAREA_READ(cmdbuf.cliprects, - cmdbuf.num_cliprects * + if (cmdbuf->num_cliprects && + DRM_VERIFYAREA_READ(cmdbuf->cliprects, + cmdbuf->num_cliprects * sizeof(struct drm_clip_rect))) { DRM_ERROR("Fault accessing cliprects\n"); return -EFAULT; } - ret = i915_dispatch_cmdbuffer(dev, &cmdbuf); + ret = i915_dispatch_cmdbuffer(dev, cmdbuf); if (ret) { DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); return ret; @@ -749,35 +741,31 @@ static int i915_do_cleanup_pageflip(struct drm_device * dev) return 0; } -static int i915_flip_bufs(DRM_IOCTL_ARGS) +static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; - drm_i915_flip_t param; + drm_i915_flip_t *param = data; DRM_DEBUG("%s\n", __FUNCTION__); LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_flip_t __user *) data, - sizeof(param)); - - if (param.pipes & ~0x3) { + if (param->pipes & ~0x3) { DRM_ERROR("Invalid pipes 0x%x, only <= 0x3 is valid\n", - param.pipes); + param->pipes); return -EINVAL; } - i915_dispatch_flip(dev, param.pipes, 0); + i915_dispatch_flip(dev, param->pipes, 0); return 0; } -static int i915_getparam(DRM_IOCTL_ARGS) +static int i915_getparam(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_getparam_t param; + drm_i915_getparam_t *param = data; int value; if (!dev_priv) { @@ -785,10 +773,7 @@ static int i915_getparam(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data, - sizeof(param)); - - switch (param.param) { + switch (param->param) { case I915_PARAM_IRQ_ACTIVE: value = dev->irq ? 1 : 0; break; @@ -799,11 +784,11 @@ static int i915_getparam(DRM_IOCTL_ARGS) value = READ_BREADCRUMB(dev_priv); break; default: - DRM_ERROR("Unknown parameter %d\n", param.param); + DRM_ERROR("Unknown parameter %d\n", param->param); return -EINVAL; } - if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { + if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { DRM_ERROR("DRM_COPY_TO_USER failed\n"); return -EFAULT; } @@ -811,32 +796,29 @@ static int i915_getparam(DRM_IOCTL_ARGS) return 0; } -static int i915_setparam(DRM_IOCTL_ARGS) +static int i915_setparam(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_setparam_t param; + drm_i915_setparam_t *param = data; if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data, - sizeof(param)); - - switch (param.param) { + switch (param->param) { case I915_SETPARAM_USE_MI_BATCHBUFFER_START: - dev_priv->use_mi_batchbuffer_start = param.value; + dev_priv->use_mi_batchbuffer_start = param->value; break; case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: - dev_priv->tex_lru_log_granularity = param.value; + dev_priv->tex_lru_log_granularity = param->value; break; case I915_SETPARAM_ALLOW_BATCHBUFFER: - dev_priv->allow_batchbuffer = param.value; + dev_priv->allow_batchbuffer = param->value; break; default: - DRM_ERROR("unknown parameter %d\n", param.param); + DRM_ERROR("unknown parameter %d\n", param->param); return -EINVAL; } @@ -853,13 +835,13 @@ drm_i915_mmio_entry_t mmio_table[] = { static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t); -static int i915_mmio(DRM_IOCTL_ARGS) +static int i915_mmio(struct drm_device *dev, void *data, + struct drm_file *file_priv) { uint32_t buf[8]; - DRM_DEVICE; drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_mmio_entry_t *e; - drm_i915_mmio_t mmio; + drm_i915_mmio_t *mmio = data; void __iomem *base; int i; @@ -867,22 +849,20 @@ static int i915_mmio(DRM_IOCTL_ARGS) DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(mmio, (drm_i915_mmio_t __user *) data, - sizeof(mmio)); - if (mmio.reg >= mmio_table_size) + if (mmio->reg >= mmio_table_size) return -EINVAL; - e = &mmio_table[mmio.reg]; + e = &mmio_table[mmio->reg]; base = (u8 *) dev_priv->mmio_map->handle + e->offset; - switch (mmio.read_write) { + switch (mmio->read_write) { case I915_MMIO_READ: if (!(e->flag & I915_MMIO_MAY_READ)) return -EINVAL; for (i = 0; i < e->size / 4; i++) buf[i] = I915_READ(e->offset + i * 4); - if (DRM_COPY_TO_USER(mmio.data, buf, e->size)) { + if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) { DRM_ERROR("DRM_COPY_TO_USER failed\n"); return -EFAULT; } @@ -891,7 +871,7 @@ static int i915_mmio(DRM_IOCTL_ARGS) case I915_MMIO_WRITE: if (!(e->flag & I915_MMIO_MAY_WRITE)) return -EINVAL; - if(DRM_COPY_FROM_USER(buf, mmio.data, e->size)) { + if(DRM_COPY_FROM_USER(buf, mmio->data, e->size)) { DRM_ERROR("DRM_COPY_TO_USER failed\n"); return -EFAULT; } @@ -902,23 +882,21 @@ static int i915_mmio(DRM_IOCTL_ARGS) return 0; } -static int i915_set_status_page(DRM_IOCTL_ARGS) +static int i915_set_status_page(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_hws_addr_t hws; + drm_i915_hws_addr_t *hws = data; if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(hws, (drm_i915_hws_addr_t __user *) data, - sizeof(hws)); - DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws.addr); + DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr); - dev_priv->status_gfx_addr = hws.addr & (0x1ffff<<12); + dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); - dev_priv->hws_map.offset = dev->agp->base + hws.addr; + dev_priv->hws_map.offset = dev->agp->base + hws->addr; dev_priv->hws_map.size = 4*1024; dev_priv->hws_map.type = 0; dev_priv->hws_map.flags = 0; @@ -974,24 +952,24 @@ void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) } struct drm_ioctl_desc i915_ioctls[] = { - [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY }, - [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY }, - [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH }, - [DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_I915_MMIO)] = {i915_mmio, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_I915_HWS_ADDR)] = {i915_set_status_page, DRM_AUTH}, + DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), + DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), + DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), + DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), + DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), + DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), + DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH), + DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH), + DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), + DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), + DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), + DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), + DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), + DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH), + DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH), }; int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 73b3d187..e641fdc6 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -163,8 +163,10 @@ extern int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush); extern int i915_driver_firstopen(struct drm_device *dev); /* i915_irq.c */ -extern int i915_irq_emit(DRM_IOCTL_ARGS); -extern int i915_irq_wait(DRM_IOCTL_ARGS); +extern int i915_irq_emit(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int i915_irq_wait(struct drm_device *dev, void *data, + struct drm_file *file_priv); extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence); extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence); @@ -172,18 +174,25 @@ extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); extern void i915_driver_irq_preinstall(struct drm_device * dev); extern void i915_driver_irq_postinstall(struct drm_device * dev); extern void i915_driver_irq_uninstall(struct drm_device * dev); -extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS); -extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS); +extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, + struct drm_file *file_priv); extern int i915_emit_irq(struct drm_device * dev); extern void i915_user_irq_on(drm_i915_private_t *dev_priv); extern void i915_user_irq_off(drm_i915_private_t *dev_priv); -extern int i915_vblank_swap(DRM_IOCTL_ARGS); +extern int i915_vblank_swap(struct drm_device *dev, void *data, + struct drm_file *file_priv); /* i915_mem.c */ -extern int i915_mem_alloc(DRM_IOCTL_ARGS); -extern int i915_mem_free(DRM_IOCTL_ARGS); -extern int i915_mem_init_heap(DRM_IOCTL_ARGS); -extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS); +extern int i915_mem_alloc(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int i915_mem_free(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int i915_mem_init_heap(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, + struct drm_file *file_priv); extern void i915_mem_takedown(struct mem_block **heap); extern void i915_mem_release(struct drm_device * dev, struct drm_file *file_priv, diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c index da61997e..1056b3e6 100644 --- a/shared-core/i915_irq.c +++ b/shared-core/i915_irq.c @@ -416,7 +416,8 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr) return ret; } -static int i915_driver_vblank_do_wait(struct drm_device *dev, unsigned int *sequence, +static int i915_driver_vblank_do_wait(struct drm_device *dev, + unsigned int *sequence, atomic_t *counter) { drm_i915_private_t *dev_priv = dev->dev_private; @@ -449,11 +450,10 @@ int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence) /* Needs the lock as it touches the ring. */ -int i915_irq_emit(DRM_IOCTL_ARGS) +int i915_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_irq_emit_t emit; + drm_i915_irq_emit_t *emit = data; int result; LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -463,12 +463,9 @@ int i915_irq_emit(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(emit, (drm_i915_irq_emit_t __user *) data, - sizeof(emit)); - result = i915_emit_irq(dev); - if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) { + if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { DRM_ERROR("copy_to_user\n"); return -EFAULT; } @@ -478,21 +475,18 @@ int i915_irq_emit(DRM_IOCTL_ARGS) /* Doesn't need the hardware lock. */ -int i915_irq_wait(DRM_IOCTL_ARGS) +int i915_irq_wait(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_irq_wait_t irqwait; + drm_i915_irq_wait_t *irqwait = data; if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(irqwait, (drm_i915_irq_wait_t __user *) data, - sizeof(irqwait)); - - return i915_wait_irq(dev, irqwait.irq_seq); + return i915_wait_irq(dev, irqwait->irq_seq); } static void i915_enable_interrupt (struct drm_device *dev) @@ -511,38 +505,35 @@ static void i915_enable_interrupt (struct drm_device *dev) /* Set the vblank monitor pipe */ -int i915_vblank_pipe_set(DRM_IOCTL_ARGS) +int i915_vblank_pipe_set(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_vblank_pipe_t pipe; + drm_i915_vblank_pipe_t *pipe = data; if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(pipe, (drm_i915_vblank_pipe_t __user *) data, - sizeof(pipe)); - - if (pipe.pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) { + if (pipe->pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) { DRM_ERROR("%s called with invalid pipe 0x%x\n", - __FUNCTION__, pipe.pipe); + __FUNCTION__, pipe->pipe); return -EINVAL; } - dev_priv->vblank_pipe = pipe.pipe; + dev_priv->vblank_pipe = pipe->pipe; i915_enable_interrupt (dev); return 0; } -int i915_vblank_pipe_get(DRM_IOCTL_ARGS) +int i915_vblank_pipe_get(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_vblank_pipe_t pipe; + drm_i915_vblank_pipe_t *pipe = data; u16 flag; if (!dev_priv) { @@ -551,24 +542,23 @@ int i915_vblank_pipe_get(DRM_IOCTL_ARGS) } flag = I915_READ(I915REG_INT_ENABLE_R); - pipe.pipe = 0; + pipe->pipe = 0; if (flag & VSYNC_PIPEA_FLAG) - pipe.pipe |= DRM_I915_VBLANK_PIPE_A; + pipe->pipe |= DRM_I915_VBLANK_PIPE_A; if (flag & VSYNC_PIPEB_FLAG) - pipe.pipe |= DRM_I915_VBLANK_PIPE_B; - DRM_COPY_TO_USER_IOCTL((drm_i915_vblank_pipe_t __user *) data, pipe, - sizeof(pipe)); + pipe->pipe |= DRM_I915_VBLANK_PIPE_B; + return 0; } /** * Schedule buffer swap at given vertical blank. */ -int i915_vblank_swap(DRM_IOCTL_ARGS) +int i915_vblank_swap(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_vblank_swap_t swap; + drm_i915_vblank_swap_t *swap = data; drm_i915_vbl_swap_t *vbl_swap; unsigned int pipe, seqtype, curseq; unsigned long irqflags; @@ -584,19 +574,16 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(swap, (drm_i915_vblank_swap_t __user *) data, - sizeof(swap)); - - if (swap.seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE | + if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS | _DRM_VBLANK_FLIP)) { - DRM_ERROR("Invalid sequence type 0x%x\n", swap.seqtype); + DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype); return -EINVAL; } - pipe = (swap.seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0; + pipe = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0; - seqtype = swap.seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE); + seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE); if (!(dev_priv->vblank_pipe & (1 << pipe))) { DRM_ERROR("Invalid pipe %d\n", pipe); @@ -606,34 +593,34 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) curseq = atomic_read(pipe ? &dev->vbl_received2 : &dev->vbl_received); if (seqtype == _DRM_VBLANK_RELATIVE) - swap.sequence += curseq; + swap->sequence += curseq; - if ((curseq - swap.sequence) <= (1<<23)) { - if (swap.seqtype & _DRM_VBLANK_NEXTONMISS) { - swap.sequence = curseq + 1; + if ((curseq - swap->sequence) <= (1<<23)) { + if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) { + swap->sequence = curseq + 1; } else { DRM_DEBUG("Missed target sequence\n"); return -EINVAL; } } - if (swap.seqtype & _DRM_VBLANK_FLIP) { - swap.sequence--; + if (swap->seqtype & _DRM_VBLANK_FLIP) { + swap->sequence--; - if ((curseq - swap.sequence) <= (1<<23)) { + if ((curseq - swap->sequence) <= (1<<23)) { struct drm_drawable_info *drw; LOCK_TEST_WITH_RETURN(dev, file_priv); DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags); - drw = drm_get_drawable_info(dev, swap.drawable); + drw = drm_get_drawable_info(dev, swap->drawable); if (!drw) { DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags); DRM_DEBUG("Invalid drawable ID %d\n", - swap.drawable); + swap->drawable); return -EINVAL; } @@ -650,10 +637,10 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) list_for_each(list, &dev_priv->vbl_swaps.head) { vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head); - if (vbl_swap->drw_id == swap.drawable && + if (vbl_swap->drw_id == swap->drawable && vbl_swap->pipe == pipe && - vbl_swap->sequence == swap.sequence) { - vbl_swap->flip = (swap.seqtype & _DRM_VBLANK_FLIP); + vbl_swap->sequence == swap->sequence) { + vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP); DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags); DRM_DEBUG("Already scheduled\n"); return 0; @@ -676,13 +663,13 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) DRM_DEBUG("\n"); - vbl_swap->drw_id = swap.drawable; + vbl_swap->drw_id = swap->drawable; vbl_swap->pipe = pipe; - vbl_swap->sequence = swap.sequence; - vbl_swap->flip = (swap.seqtype & _DRM_VBLANK_FLIP); + vbl_swap->sequence = swap->sequence; + vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP); if (vbl_swap->flip) - swap.sequence++; + swap->sequence++; DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags); @@ -691,9 +678,6 @@ int i915_vblank_swap(DRM_IOCTL_ARGS) DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags); - DRM_COPY_TO_USER_IOCTL((drm_i915_vblank_swap_t __user *) data, swap, - sizeof(swap)); - return 0; } diff --git a/shared-core/i915_mem.c b/shared-core/i915_mem.c index e2e7018d..5bf29a1e 100644 --- a/shared-core/i915_mem.c +++ b/shared-core/i915_mem.c @@ -268,11 +268,11 @@ static struct mem_block **get_heap(drm_i915_private_t * dev_priv, int region) /* IOCTL HANDLERS */ -int i915_mem_alloc(DRM_IOCTL_ARGS) +int i915_mem_alloc(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_mem_alloc_t alloc; + drm_i915_mem_alloc_t *alloc = data; struct mem_block *block, **heap; if (!dev_priv) { @@ -280,27 +280,25 @@ int i915_mem_alloc(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(alloc, (drm_i915_mem_alloc_t __user *) data, - sizeof(alloc)); - - heap = get_heap(dev_priv, alloc.region); + heap = get_heap(dev_priv, alloc->region); if (!heap || !*heap) return -EFAULT; /* Make things easier on ourselves: all allocations at least * 4k aligned. */ - if (alloc.alignment < 12) - alloc.alignment = 12; + if (alloc->alignment < 12) + alloc->alignment = 12; - block = alloc_block(*heap, alloc.size, alloc.alignment, file_priv); + block = alloc_block(*heap, alloc->size, alloc->alignment, file_priv); if (!block) return -ENOMEM; mark_block(dev, block, 1); - if (DRM_COPY_TO_USER(alloc.region_offset, &block->start, sizeof(int))) { + if (DRM_COPY_TO_USER(alloc->region_offset, &block->start, + sizeof(int))) { DRM_ERROR("copy_to_user\n"); return -EFAULT; } @@ -308,11 +306,11 @@ int i915_mem_alloc(DRM_IOCTL_ARGS) return 0; } -int i915_mem_free(DRM_IOCTL_ARGS) +int i915_mem_free(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_mem_free_t memfree; + drm_i915_mem_free_t *memfree = data; struct mem_block *block, **heap; if (!dev_priv) { @@ -320,14 +318,11 @@ int i915_mem_free(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(memfree, (drm_i915_mem_free_t __user *) data, - sizeof(memfree)); - - heap = get_heap(dev_priv, memfree.region); + heap = get_heap(dev_priv, memfree->region); if (!heap || !*heap) return -EFAULT; - block = find_block(*heap, memfree.region_offset); + block = find_block(*heap, memfree->region_offset); if (!block) return -EFAULT; @@ -339,11 +334,11 @@ int i915_mem_free(DRM_IOCTL_ARGS) return 0; } -int i915_mem_init_heap(DRM_IOCTL_ARGS) +int i915_mem_init_heap(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_mem_init_heap_t initheap; + drm_i915_mem_init_heap_t *initheap = data; struct mem_block **heap; if (!dev_priv) { @@ -351,11 +346,7 @@ int i915_mem_init_heap(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(initheap, - (drm_i915_mem_init_heap_t __user *) data, - sizeof(initheap)); - - heap = get_heap(dev_priv, initheap.region); + heap = get_heap(dev_priv, initheap->region); if (!heap) return -EFAULT; @@ -364,14 +355,14 @@ int i915_mem_init_heap(DRM_IOCTL_ARGS) return -EFAULT; } - return init_heap(heap, initheap.start, initheap.size); + return init_heap(heap, initheap->start, initheap->size); } -int i915_mem_destroy_heap( DRM_IOCTL_ARGS ) +int i915_mem_destroy_heap( struct drm_device *dev, void *data, + struct drm_file *file_priv ) { - DRM_DEVICE; drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_mem_destroy_heap_t destroyheap; + drm_i915_mem_destroy_heap_t *destroyheap = data; struct mem_block **heap; if ( !dev_priv ) { @@ -379,10 +370,7 @@ int i915_mem_destroy_heap( DRM_IOCTL_ARGS ) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL( destroyheap, (drm_i915_mem_destroy_heap_t *)data, - sizeof(destroyheap) ); - - heap = get_heap( dev_priv, destroyheap.region ); + heap = get_heap( dev_priv, destroyheap->region ); if (!heap) { DRM_ERROR("get_heap failed"); return -EFAULT; diff --git a/shared-core/mach64_dma.c b/shared-core/mach64_dma.c index 25877824..e0a67458 100644 --- a/shared-core/mach64_dma.c +++ b/shared-core/mach64_dma.c @@ -1158,21 +1158,18 @@ int mach64_do_cleanup_dma(struct drm_device * dev) /** \name IOCTL handlers */ /*@{*/ -int mach64_dma_init(DRM_IOCTL_ARGS) +int mach64_dma_init(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; - drm_mach64_init_t init; + drm_mach64_init_t *init = data; DRM_DEBUG("%s\n", __FUNCTION__); LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(init, (drm_mach64_init_t *) data, - sizeof(init)); - - switch (init.func) { + switch (init->func) { case DRM_MACH64_INIT_DMA: - return mach64_do_dma_init(dev, &init); + return mach64_do_dma_init(dev, init); case DRM_MACH64_CLEANUP_DMA: return mach64_do_cleanup_dma(dev); } @@ -1180,9 +1177,9 @@ int mach64_dma_init(DRM_IOCTL_ARGS) return -EINVAL; } -int mach64_dma_idle(DRM_IOCTL_ARGS) +int mach64_dma_idle(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_mach64_private_t *dev_priv = dev->dev_private; DRM_DEBUG("%s\n", __FUNCTION__); @@ -1192,9 +1189,9 @@ int mach64_dma_idle(DRM_IOCTL_ARGS) return mach64_do_dma_idle(dev_priv); } -int mach64_dma_flush(DRM_IOCTL_ARGS) +int mach64_dma_flush(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_mach64_private_t *dev_priv = dev->dev_private; DRM_DEBUG("%s\n", __FUNCTION__); @@ -1204,9 +1201,9 @@ int mach64_dma_flush(DRM_IOCTL_ARGS) return mach64_do_dma_flush(dev_priv); } -int mach64_engine_reset(DRM_IOCTL_ARGS) +int mach64_engine_reset(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_mach64_private_t *dev_priv = dev->dev_private; DRM_DEBUG("%s\n", __FUNCTION__); @@ -1461,7 +1458,7 @@ int mach64_freelist_put(drm_mach64_private_t * dev_priv, struct drm_buf * copy_b /** \name DMA buffer request and submission IOCTL handler */ /*@{*/ -static int mach64_dma_get_buffers(struct drm_device * dev, +static int mach64_dma_get_buffers(struct drm_device *dev, struct drm_file *file_priv, struct drm_dma * d) { @@ -1493,41 +1490,37 @@ static int mach64_dma_get_buffers(struct drm_device * dev, return 0; } -int mach64_dma_buffers(DRM_IOCTL_ARGS) +int mach64_dma_buffers(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; struct drm_device_dma *dma = dev->dma; - struct drm_dma d; + struct drm_dma *d = data; int ret = 0; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(d, (struct drm_dma *) data, sizeof(d)); - /* Please don't send us buffers. */ - if (d.send_count != 0) { + if (d->send_count != 0) { DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d.send_count); + DRM_CURRENTPID, d->send_count); return -EINVAL; } /* We'll send you buffers. */ - if (d.request_count < 0 || d.request_count > dma->buf_count) { + if (d->request_count < 0 || d->request_count > dma->buf_count) { DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d.request_count, dma->buf_count); + DRM_CURRENTPID, d->request_count, dma->buf_count); ret = -EINVAL; } - d.granted_count = 0; + d->granted_count = 0; - if (d.request_count) { - ret = mach64_dma_get_buffers(dev, file_priv, &d); + if (d->request_count) { + ret = mach64_dma_get_buffers(dev, file_priv, d); } - DRM_COPY_TO_USER_IOCTL((struct drm_dma *) data, d, sizeof(d)); - return ret; } diff --git a/shared-core/mach64_drv.h b/shared-core/mach64_drv.h index aa9afcab..cebd4c6e 100644 --- a/shared-core/mach64_drv.h +++ b/shared-core/mach64_drv.h @@ -112,11 +112,16 @@ extern struct drm_ioctl_desc mach64_ioctls[]; extern int mach64_max_ioctl; /* mach64_dma.c */ -extern int mach64_dma_init(DRM_IOCTL_ARGS); -extern int mach64_dma_idle(DRM_IOCTL_ARGS); -extern int mach64_dma_flush(DRM_IOCTL_ARGS); -extern int mach64_engine_reset(DRM_IOCTL_ARGS); -extern int mach64_dma_buffers(DRM_IOCTL_ARGS); +extern int mach64_dma_init(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int mach64_dma_idle(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int mach64_dma_flush(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int mach64_engine_reset(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int mach64_dma_buffers(struct drm_device *dev, void *data, + struct drm_file *file_priv); extern void mach64_driver_lastclose(struct drm_device * dev); extern int mach64_init_freelist(struct drm_device * dev); @@ -140,11 +145,16 @@ extern int mach64_do_dma_flush(drm_mach64_private_t * dev_priv); extern int mach64_do_cleanup_dma(struct drm_device * dev); /* mach64_state.c */ -extern int mach64_dma_clear(DRM_IOCTL_ARGS); -extern int mach64_dma_swap(DRM_IOCTL_ARGS); -extern int mach64_dma_vertex(DRM_IOCTL_ARGS); -extern int mach64_dma_blit(DRM_IOCTL_ARGS); -extern int mach64_get_param(DRM_IOCTL_ARGS); +extern int mach64_dma_clear(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int mach64_dma_swap(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int mach64_dma_vertex(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int mach64_dma_blit(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int mach64_get_param(struct drm_device *dev, void *data, + struct drm_file *file_priv); extern int mach64_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence); diff --git a/shared-core/mach64_state.c b/shared-core/mach64_state.c index c89573e7..89b6c6ce 100644 --- a/shared-core/mach64_state.c +++ b/shared-core/mach64_state.c @@ -41,15 +41,15 @@ * */ struct drm_ioctl_desc mach64_ioctls[] = { - [DRM_IOCTL_NR(DRM_MACH64_INIT)] = {mach64_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_MACH64_CLEAR)] = {mach64_dma_clear, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MACH64_SWAP)] = {mach64_dma_swap, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MACH64_IDLE)] = {mach64_dma_idle, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MACH64_RESET)] = {mach64_engine_reset, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MACH64_VERTEX)] = {mach64_dma_vertex, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MACH64_BLIT)] = {mach64_dma_blit, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MACH64_FLUSH)] = {mach64_dma_flush, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MACH64_GETPARAM)] = {mach64_get_param, DRM_AUTH}, + DRM_IOCTL_DEF(DRM_MACH64_INIT, mach64_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_MACH64_CLEAR, mach64_dma_clear, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MACH64_SWAP, mach64_dma_swap, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MACH64_IDLE, mach64_dma_idle, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MACH64_RESET, mach64_engine_reset, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MACH64_VERTEX, mach64_dma_vertex, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MACH64_BLIT, mach64_dma_blit, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MACH64_FLUSH, mach64_dma_flush, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MACH64_GETPARAM, mach64_get_param, DRM_AUTH), }; int mach64_max_ioctl = DRM_ARRAY_SIZE(mach64_ioctls); @@ -758,27 +758,25 @@ _blit_done: * IOCTL functions */ -int mach64_dma_clear(DRM_IOCTL_ARGS) +int mach64_dma_clear(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mach64_clear_t clear; + drm_mach64_clear_t *clear = data; int ret; DRM_DEBUG("%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID); LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(clear, (drm_mach64_clear_t *) data, - sizeof(clear)); - if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS; - ret = mach64_dma_dispatch_clear(dev, file_priv, clear.flags, - clear.x, clear.y, clear.w, clear.h, - clear.clear_color, clear.clear_depth); + ret = mach64_dma_dispatch_clear(dev, file_priv, clear->flags, + clear->x, clear->y, clear->w, clear->h, + clear->clear_color, + clear->clear_depth); /* Make sure we restore the 3D state next time. */ @@ -786,9 +784,9 @@ int mach64_dma_clear(DRM_IOCTL_ARGS) return ret; } -int mach64_dma_swap(DRM_IOCTL_ARGS) +int mach64_dma_swap(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; int ret; @@ -808,12 +806,12 @@ int mach64_dma_swap(DRM_IOCTL_ARGS) return ret; } -int mach64_dma_vertex(DRM_IOCTL_ARGS) +int mach64_dma_vertex(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mach64_vertex_t vertex; + drm_mach64_vertex_t *vertex = data; LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -822,44 +820,38 @@ int mach64_dma_vertex(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(vertex, (drm_mach64_vertex_t *) data, - sizeof(vertex)); - DRM_DEBUG("%s: pid=%d buf=%p used=%lu discard=%d\n", __FUNCTION__, DRM_CURRENTPID, - vertex.buf, vertex.used, vertex.discard); + vertex->buf, vertex->used, vertex->discard); - if (vertex.prim < 0 || vertex.prim > MACH64_PRIM_POLYGON) { - DRM_ERROR("buffer prim %d\n", vertex.prim); + if (vertex->prim < 0 || vertex->prim > MACH64_PRIM_POLYGON) { + DRM_ERROR("buffer prim %d\n", vertex->prim); return -EINVAL; } - if (vertex.used > MACH64_BUFFER_SIZE || (vertex.used & 3) != 0) { + if (vertex->used > MACH64_BUFFER_SIZE || (vertex->used & 3) != 0) { DRM_ERROR("Invalid vertex buffer size: %lu bytes\n", - vertex.used); + vertex->used); return -EINVAL; } if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS; - return mach64_dma_dispatch_vertex(dev, file_priv, &vertex); + return mach64_dma_dispatch_vertex(dev, file_priv, vertex); } -int mach64_dma_blit(DRM_IOCTL_ARGS) +int mach64_dma_blit(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mach64_blit_t blit; + drm_mach64_blit_t *blit = data; int ret; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(blit, (drm_mach64_blit_t *) data, - sizeof(blit)); - - ret = mach64_dma_dispatch_blit(dev, file_priv, &blit); + ret = mach64_dma_dispatch_blit(dev, file_priv, blit); /* Make sure we restore the 3D state next time. */ @@ -869,11 +861,11 @@ int mach64_dma_blit(DRM_IOCTL_ARGS) return ret; } -int mach64_get_param(DRM_IOCTL_ARGS) +int mach64_get_param(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_getparam_t param; + drm_mach64_getparam_t *param = data; int value; DRM_DEBUG("%s\n", __FUNCTION__); @@ -883,10 +875,7 @@ int mach64_get_param(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(param, (drm_mach64_getparam_t *) data, - sizeof(param)); - - switch (param.param) { + switch (param->param) { case MACH64_PARAM_FRAMES_QUEUED: /* Needs lock since it calls mach64_ring_tick() */ LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -899,7 +888,7 @@ int mach64_get_param(DRM_IOCTL_ARGS) return -EINVAL; } - if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { + if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { DRM_ERROR("copy_to_user\n"); return -EFAULT; } diff --git a/shared-core/mga_dma.c b/shared-core/mga_dma.c index 429ffa54..a86dd31c 100644 --- a/shared-core/mga_dma.c +++ b/shared-core/mga_dma.c @@ -762,38 +762,31 @@ static int mga_do_dma_bootstrap(struct drm_device * dev, return err; } -int mga_dma_bootstrap(DRM_IOCTL_ARGS) +int mga_dma_bootstrap(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; - drm_mga_dma_bootstrap_t bootstrap; + drm_mga_dma_bootstrap_t *bootstrap = data; int err; static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 }; const drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private; - DRM_COPY_FROM_USER_IOCTL(bootstrap, - (drm_mga_dma_bootstrap_t __user *) data, - sizeof(bootstrap)); - - err = mga_do_dma_bootstrap(dev, & bootstrap); + err = mga_do_dma_bootstrap(dev, bootstrap); if (err) { mga_do_cleanup_dma(dev, FULL_CLEANUP); return err; } if (dev_priv->agp_textures != NULL) { - bootstrap.texture_handle = dev_priv->agp_textures->offset; - bootstrap.texture_size = dev_priv->agp_textures->size; + bootstrap->texture_handle = dev_priv->agp_textures->offset; + bootstrap->texture_size = dev_priv->agp_textures->size; } else { - bootstrap.texture_handle = 0; - bootstrap.texture_size = 0; + bootstrap->texture_handle = 0; + bootstrap->texture_size = 0; } - bootstrap.agp_mode = modes[bootstrap.agp_mode & 0x07]; - - DRM_COPY_TO_USER_IOCTL((drm_mga_dma_bootstrap_t __user *)data, - bootstrap, sizeof(bootstrap)); + bootstrap->agp_mode = modes[bootstrap->agp_mode & 0x07]; return 0; } @@ -1010,20 +1003,17 @@ static int mga_do_cleanup_dma(struct drm_device * dev, int full_cleanup) return 0; } -int mga_dma_init(DRM_IOCTL_ARGS) +int mga_dma_init(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; - drm_mga_init_t init; + drm_mga_init_t *init = data; int err; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data, - sizeof(init)); - - switch (init.func) { + switch (init->func) { case MGA_INIT_DMA: - err = mga_do_init_dma(dev, &init); + err = mga_do_init_dma(dev, init); if (err) { (void) mga_do_cleanup_dma(dev, FULL_CLEANUP); } @@ -1039,29 +1029,26 @@ int mga_dma_init(DRM_IOCTL_ARGS) * Primary DMA stream management */ -int mga_dma_flush(DRM_IOCTL_ARGS) +int mga_dma_flush(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - struct drm_lock lock; + struct drm_lock *lock = data; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(lock, (struct drm_lock __user *) data, - sizeof(lock)); - DRM_DEBUG("%s%s%s\n", - (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "", - (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", - (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : ""); + (lock->flags & _DRM_LOCK_FLUSH) ? "flush, " : "", + (lock->flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", + (lock->flags & _DRM_LOCK_QUIESCENT) ? "idle, " : ""); WRAP_WAIT_WITH_RETURN(dev_priv); - if (lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) { + if (lock->flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) { mga_do_dma_flush(dev_priv); } - if (lock.flags & _DRM_LOCK_QUIESCENT) { + if (lock->flags & _DRM_LOCK_QUIESCENT) { #if MGA_DMA_DEBUG int ret = mga_do_wait_for_idle(dev_priv); if (ret < 0) @@ -1075,9 +1062,9 @@ int mga_dma_flush(DRM_IOCTL_ARGS) } } -int mga_dma_reset(DRM_IOCTL_ARGS) +int mga_dma_reset(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -1114,45 +1101,40 @@ static int mga_dma_get_buffers(struct drm_device * dev, return 0; } -int mga_dma_buffers(DRM_IOCTL_ARGS) +int mga_dma_buffers(struct drm_device *dev, void *data, + struct drm_file *file_priv) { - DRM_DEVICE; struct drm_device_dma *dma = dev->dma; drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - struct drm_dma __user *argp = (void __user *)data; - struct drm_dma d; + struct drm_dma *d = data; int ret = 0; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); - /* Please don't send us buffers. */ - if (d.send_count != 0) { + if (d->send_count != 0) { DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d.send_count); + DRM_CURRENTPID, d->send_count); return -EINVAL; } /* We'll send you buffers. */ - if (d.request_count < 0 || d.request_count > dma->buf_count) { + if (d->request_count < 0 || d->request_count > dma->buf_count) { DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d.request_count, dma->buf_count); + DRM_CURRENTPID, d->request_count, dma->buf_count); return -EINVAL; } WRAP_TEST_WITH_RETURN(dev_priv); - d.granted_count = 0; + d->granted_count = 0; - if (d.request_count) { - ret = mga_dma_get_buffers(dev, file_priv, &d); + if (d->request_count) { + ret = mga_dma_get_buffers(dev, file_priv, d); } - DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); - return ret; } diff --git a/shared-core/mga_drv.h b/shared-core/mga_drv.h index 2da31194..8254c3f1 100644 --- a/shared-core/mga_drv.h +++ b/shared-core/mga_drv.h @@ -152,11 +152,16 @@ extern struct drm_ioctl_desc mga_ioctls[]; extern int mga_max_ioctl; /* mga_dma.c */ -extern int mga_dma_bootstrap(DRM_IOCTL_ARGS); -extern int mga_dma_init(DRM_IOCTL_ARGS); -extern int mga_dma_flush(DRM_IOCTL_ARGS); -extern int mga_dma_reset(DRM_IOCTL_ARGS); -extern int mga_dma_buffers(DRM_IOCTL_ARGS); +extern int mga_dma_bootstrap(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int mga_dma_init(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int mga_dma_flush(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int mga_dma_reset(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int mga_dma_buffers(struct drm_device *dev, void *data, + struct drm_file *file_priv); extern int mga_driver_load(struct drm_device *dev, unsigned long flags); extern int mga_driver_unload(struct drm_device * dev); extern void mga_driver_lastclose(struct drm_device * dev); diff --git a/shared-core/mga_state.c b/shared-core/mga_state.c index 196d7d16..70b7caa0 100644 --- a/shared-core/mga_state.c +++ b/shared-core/mga_state.c @@ -865,24 +865,20 @@ static void mga_dma_dispatch_blit(struct drm_device * dev, drm_mga_blit_t * blit * */ -static int mga_dma_clear(DRM_IOCTL_ARGS) +static int mga_dma_clear(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_clear_t clear; + drm_mga_clear_t *clear = data; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(clear, (drm_mga_clear_t __user *) data, - sizeof(clear)); - if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; WRAP_TEST_WITH_RETURN(dev_priv); - mga_dma_dispatch_clear(dev, &clear); + mga_dma_dispatch_clear(dev, clear); /* Make sure we restore the 3D state next time. */ @@ -891,9 +887,8 @@ static int mga_dma_clear(DRM_IOCTL_ARGS) return 0; } -static int mga_dma_swap(DRM_IOCTL_ARGS) +static int mga_dma_swap(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -913,31 +908,26 @@ static int mga_dma_swap(DRM_IOCTL_ARGS) return 0; } -static int mga_dma_vertex(DRM_IOCTL_ARGS) +static int mga_dma_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; drm_mga_buf_priv_t *buf_priv; - drm_mga_vertex_t vertex; + drm_mga_vertex_t *vertex = data; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(vertex, - (drm_mga_vertex_t __user *) data, - sizeof(vertex)); - - if (vertex.idx < 0 || vertex.idx > dma->buf_count) + if (vertex->idx < 0 || vertex->idx > dma->buf_count) return -EINVAL; - buf = dma->buflist[vertex.idx]; + buf = dma->buflist[vertex->idx]; buf_priv = buf->dev_private; - buf->used = vertex.used; - buf_priv->discard = vertex.discard; + buf->used = vertex->used; + buf_priv->discard = vertex->discard; if (!mga_verify_state(dev_priv)) { - if (vertex.discard) { + if (vertex->discard) { if (buf_priv->dispatched == 1) AGE_BUFFER(buf_priv); buf_priv->dispatched = 0; @@ -953,31 +943,26 @@ static int mga_dma_vertex(DRM_IOCTL_ARGS) return 0; } -static int mga_dma_indices(DRM_IOCTL_ARGS) +static int mga_dma_indices(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; drm_mga_buf_priv_t *buf_priv; - drm_mga_indices_t indices; + drm_mga_indices_t *indices = data; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(indices, - (drm_mga_indices_t __user *) data, - sizeof(indices)); - - if (indices.idx < 0 || indices.idx > dma->buf_count) + if (indices->idx < 0 || indices->idx > dma->buf_count) return -EINVAL; - buf = dma->buflist[indices.idx]; + buf = dma->buflist[indices->idx]; buf_priv = buf->dev_private; - buf_priv->discard = indices.discard; + buf_priv->discard = indices->discard; if (!mga_verify_state(dev_priv)) { - if (indices.discard) { + if (indices->discard) { if (buf_priv->dispatched == 1) AGE_BUFFER(buf_priv); buf_priv->dispatched = 0; @@ -988,26 +973,22 @@ static int mga_dma_indices(DRM_IOCTL_ARGS) WRAP_TEST_WITH_RETURN(dev_priv); - mga_dma_dispatch_indices(dev, buf, indices.start, indices.end); + mga_dma_dispatch_indices(dev, buf, indices->start, indices->end); return 0; } -static int mga_dma_iload(DRM_IOCTL_ARGS) +static int mga_dma_iload(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; struct drm_device_dma *dma = dev->dma; drm_mga_private_t *dev_priv = dev->dev_private; struct drm_buf *buf; drm_mga_buf_priv_t *buf_priv; - drm_mga_iload_t iload; + drm_mga_iload_t *iload = data; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(iload, (drm_mga_iload_t __user *) data, - sizeof(iload)); - #if 0 if (mga_do_wait_for_idle(dev_priv) < 0) { if (MGA_DMA_DEBUG) @@ -1015,20 +996,20 @@ static int mga_dma_iload(DRM_IOCTL_ARGS) return -EBUSY; } #endif - if (iload.idx < 0 || iload.idx > dma->buf_count) + if (iload->idx < 0 || iload->idx > dma->buf_count) return -EINVAL; - buf = dma->buflist[iload.idx]; + buf = dma->buflist[iload->idx]; buf_priv = buf->dev_private; - if (mga_verify_iload(dev_priv, iload.dstorg, iload.length)) { + if (mga_verify_iload(dev_priv, iload->dstorg, iload->length)) { mga_freelist_put(dev, buf); return -EINVAL; } WRAP_TEST_WITH_RETURN(dev_priv); - mga_dma_dispatch_iload(dev, buf, iload.dstorg, iload.length); + mga_dma_dispatch_iload(dev, buf, iload->dstorg, iload->length); /* Make sure we restore the 3D state next time. */ @@ -1037,28 +1018,24 @@ static int mga_dma_iload(DRM_IOCTL_ARGS) return 0; } -static int mga_dma_blit(DRM_IOCTL_ARGS) +static int mga_dma_blit(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_blit_t blit; + drm_mga_blit_t *blit = data; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(blit, (drm_mga_blit_t __user *) data, - sizeof(blit)); - if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - if (mga_verify_blit(dev_priv, blit.srcorg, blit.dstorg)) + if (mga_verify_blit(dev_priv, blit->srcorg, blit->dstorg)) return -EINVAL; WRAP_TEST_WITH_RETURN(dev_priv); - mga_dma_dispatch_blit(dev, &blit); + mga_dma_dispatch_blit(dev, blit); /* Make sure we restore the 3D state next time. */ @@ -1067,11 +1044,10 @@ static int mga_dma_blit(DRM_IOCTL_ARGS) return 0; } -static int mga_getparam(DRM_IOCTL_ARGS) +static int mga_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_getparam_t param; + drm_mga_getparam_t *param = data; int value; if (!dev_priv) { @@ -1079,12 +1055,9 @@ static int mga_getparam(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(param, (drm_mga_getparam_t __user *) data, - sizeof(param)); - DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - switch (param.param) { + switch (param->param) { case MGA_PARAM_IRQ_NR: value = dev->irq; break; @@ -1095,7 +1068,7 @@ static int mga_getparam(DRM_IOCTL_ARGS) return -EINVAL; } - if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { + if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { DRM_ERROR("copy_to_user\n"); return -EFAULT; } @@ -1103,11 +1076,10 @@ static int mga_getparam(DRM_IOCTL_ARGS) return 0; } -static int mga_set_fence(DRM_IOCTL_ARGS) +static int mga_set_fence(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; - u32 temp; + u32 *fence = data; DMA_LOCALS; if (!dev_priv) { @@ -1117,11 +1089,11 @@ static int mga_set_fence(DRM_IOCTL_ARGS) DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - /* I would normal do this assignment in the declaration of temp, + /* I would normal do this assignment in the declaration of fence, * but dev_priv may be NULL. */ - temp = dev_priv->next_fence_to_post; + *fence = dev_priv->next_fence_to_post; dev_priv->next_fence_to_post++; BEGIN_DMA(1); @@ -1131,47 +1103,40 @@ static int mga_set_fence(DRM_IOCTL_ARGS) MGA_SOFTRAP, 0x00000000); ADVANCE_DMA(); - DRM_COPY_TO_USER_IOCTL((u32 __user *)data, temp, sizeof(u32)); - return 0; } -static int mga_wait_fence(DRM_IOCTL_ARGS) +static int mga_wait_fence(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; - u32 fence; + u32 *fence = data; if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(fence, (u32 __user *) data, sizeof(u32)); - DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - mga_driver_fence_wait(dev, & fence); - - DRM_COPY_TO_USER_IOCTL((u32 __user *)data, fence, sizeof(u32)); + mga_driver_fence_wait(dev, fence); return 0; } struct drm_ioctl_desc mga_ioctls[] = { - [DRM_IOCTL_NR(DRM_MGA_INIT)] = {mga_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = {mga_dma_flush, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MGA_RESET)] = {mga_dma_reset, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MGA_SWAP)] = {mga_dma_swap, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = {mga_dma_clear, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = {mga_dma_vertex, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MGA_INDICES)] = {mga_dma_indices, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = {mga_dma_iload, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MGA_BLIT)] = {mga_dma_blit, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MGA_GETPARAM)] = {mga_getparam, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MGA_SET_FENCE)] = {mga_set_fence, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MGA_WAIT_FENCE)] = {mga_wait_fence, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_MGA_DMA_BOOTSTRAP)] = {mga_dma_bootstrap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, + DRM_IOCTL_DEF(DRM_MGA_INIT, mga_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_MGA_FLUSH, mga_dma_flush, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MGA_RESET, mga_dma_reset, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MGA_SWAP, mga_dma_swap, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MGA_CLEAR, mga_dma_clear, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MGA_VERTEX, mga_dma_vertex, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MGA_INDICES, mga_dma_indices, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MGA_ILOAD, mga_dma_iload, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MGA_BLIT, mga_dma_blit, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MGA_GETPARAM, mga_getparam, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MGA_SET_FENCE, mga_set_fence, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MGA_WAIT_FENCE, mga_wait_fence, DRM_AUTH), + DRM_IOCTL_DEF(DRM_MGA_DMA_BOOTSTRAP, mga_dma_bootstrap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), }; diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 7ecfadd2..dd323a0b 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -269,10 +269,10 @@ extern int nouveau_load(struct drm_device *dev, unsigned long flags); extern int nouveau_firstopen(struct drm_device *dev); extern void nouveau_lastclose(struct drm_device *dev); extern int nouveau_unload(struct drm_device *dev); -extern int nouveau_ioctl_getparam(DRM_IOCTL_ARGS); -extern int nouveau_ioctl_setparam(DRM_IOCTL_ARGS); +extern int nouveau_ioctl_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int nouveau_ioctl_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv); extern void nouveau_wait_for_idle(struct drm_device *dev); -extern int nouveau_ioctl_card_init(DRM_IOCTL_ARGS); +extern int nouveau_ioctl_card_init(struct drm_device *dev, void *data, struct drm_file *file_priv); /* nouveau_mem.c */ extern int nouveau_mem_init_heap(struct mem_block **, @@ -285,8 +285,8 @@ extern void nouveau_mem_free_block(struct mem_block *); extern uint64_t nouveau_mem_fb_amount(struct drm_device *dev); extern void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap); -extern int nouveau_ioctl_mem_alloc(DRM_IOCTL_ARGS); -extern int nouveau_ioctl_mem_free(DRM_IOCTL_ARGS); +extern int nouveau_ioctl_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int nouveau_ioctl_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); extern struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment, uint64_t size, int flags, @@ -301,7 +301,7 @@ extern int nouveau_notifier_init_channel(struct drm_device *, int channel, extern void nouveau_notifier_takedown_channel(struct drm_device *, int channel); extern int nouveau_notifier_alloc(struct drm_device *, int channel, uint32_t handle, int cout, uint32_t *offset); -extern int nouveau_ioctl_notifier_alloc(DRM_IOCTL_ARGS); +extern int nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); /* nouveau_fifo.c */ extern int nouveau_fifo_init(struct drm_device *dev); @@ -342,7 +342,7 @@ extern int nouveau_gpuobj_gart_dma_new(struct drm_device *, int channel, uint32_t *o_ret); extern int nouveau_gpuobj_gr_new(struct drm_device *, int channel, int class, struct nouveau_gpuobj **); -extern int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS); +extern int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); /* nouveau_irq.c */ extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 8731c6a1..e5d3ab3c 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -472,42 +472,37 @@ nouveau_fifo_owner(struct drm_device *dev, struct drm_file *file_priv, * ioctls wrapping the functions ***********************************/ -static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) +static int nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct drm_nouveau_fifo_alloc init; + struct drm_nouveau_fifo_alloc *init = data; struct drm_map_list *entry; struct nouveau_fifo *chan; int res; - DRM_COPY_FROM_USER_IOCTL(init, - (struct drm_nouveau_fifo_alloc __user *) data, - sizeof(init)); - - if (init.fb_ctxdma_handle == ~0 || init.tt_ctxdma_handle == ~0) + if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0) return -EINVAL; - res = nouveau_fifo_alloc(dev, &init.channel, file_priv, - init.fb_ctxdma_handle, - init.tt_ctxdma_handle); + res = nouveau_fifo_alloc(dev, &init->channel, file_priv, + init->fb_ctxdma_handle, + init->tt_ctxdma_handle); if (res) return res; - chan = dev_priv->fifos[init.channel]; + chan = dev_priv->fifos[init->channel]; - init.put_base = chan->pushbuf_base; + init->put_base = chan->pushbuf_base; /* make the fifo available to user space */ /* first, the fifo control regs */ - init.ctrl = dev_priv->mmio->offset; + init->ctrl = dev_priv->mmio->offset; if (dev_priv->card_type < NV_50) { - init.ctrl += NV03_FIFO_REGS(init.channel); - init.ctrl_size = NV03_FIFO_REGS_SIZE; + init->ctrl += NV03_FIFO_REGS(init->channel); + init->ctrl_size = NV03_FIFO_REGS_SIZE; } else { - init.ctrl += NV50_FIFO_REGS(init.channel); - init.ctrl_size = NV50_FIFO_REGS_SIZE; + init->ctrl += NV50_FIFO_REGS(init->channel); + init->ctrl_size = NV50_FIFO_REGS_SIZE; } - res = drm_addmap(dev, init.ctrl, init.ctrl_size, _DRM_REGISTERS, + res = drm_addmap(dev, init->ctrl, init->ctrl_size, _DRM_REGISTERS, 0, &chan->regs); if (res != 0) return res; @@ -515,18 +510,16 @@ static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) entry = drm_find_matching_map(dev, chan->regs); if (!entry) return -EINVAL; - init.ctrl = entry->user_token; + init->ctrl = entry->user_token; /* pass back FIFO map info to the caller */ - init.cmdbuf = chan->pushbuf_mem->map_handle; - init.cmdbuf_size = chan->pushbuf_mem->size; + init->cmdbuf = chan->pushbuf_mem->map_handle; + init->cmdbuf_size = chan->pushbuf_mem->size; /* and the notifier block */ - init.notifier = chan->notifier_block->map_handle; - init.notifier_size = chan->notifier_block->size; + init->notifier = chan->notifier_block->map_handle; + init->notifier_size = chan->notifier_block->size; - DRM_COPY_TO_USER_IOCTL((struct drm_nouveau_fifo_alloc __user *)data, - init, sizeof(init)); return 0; } @@ -535,13 +528,13 @@ static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) ***********************************/ struct drm_ioctl_desc nouveau_ioctls[] = { - [DRM_IOCTL_NR(DRM_NOUVEAU_FIFO_ALLOC)] = {nouveau_ioctl_fifo_alloc, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_NOUVEAU_GROBJ_ALLOC)] = {nouveau_ioctl_grobj_alloc, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_NOUVEAU_NOTIFIER_ALLOC)] = {nouveau_ioctl_notifier_alloc, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_NOUVEAU_MEM_ALLOC)] = {nouveau_ioctl_mem_alloc, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_NOUVEAU_MEM_FREE)] = {nouveau_ioctl_mem_free, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_NOUVEAU_GETPARAM)] = {nouveau_ioctl_getparam, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_NOUVEAU_SETPARAM)] = {nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, + DRM_IOCTL_DEF(DRM_NOUVEAU_FIFO_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH), + DRM_IOCTL_DEF(DRM_NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_AUTH), + DRM_IOCTL_DEF(DRM_NOUVEAU_NOTIFIER_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH), + DRM_IOCTL_DEF(DRM_NOUVEAU_MEM_ALLOC, nouveau_ioctl_mem_alloc, DRM_AUTH), + DRM_IOCTL_DEF(DRM_NOUVEAU_MEM_FREE, nouveau_ioctl_mem_free, DRM_AUTH), + DRM_IOCTL_DEF(DRM_NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH), + DRM_IOCTL_DEF(DRM_NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), }; int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls); diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 6a4818c5..a7044c94 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -547,11 +547,10 @@ void nouveau_mem_free(struct drm_device* dev, struct mem_block* block) * Ioctls */ -int nouveau_ioctl_mem_alloc(DRM_IOCTL_ARGS) +int nouveau_ioctl_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct drm_nouveau_mem_alloc alloc; + struct drm_nouveau_mem_alloc *alloc = data; struct mem_block *block; if (!dev_priv) { @@ -559,42 +558,30 @@ int nouveau_ioctl_mem_alloc(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(alloc, - (struct drm_nouveau_mem_alloc_t __user *) data, - sizeof(alloc)); - - block=nouveau_mem_alloc(dev, alloc.alignment, alloc.size, alloc.flags, - file_priv); + block=nouveau_mem_alloc(dev, alloc->alignment, alloc->size, + alloc->flags, file_priv); if (!block) return -ENOMEM; - alloc.map_handle=block->map_handle; - alloc.offset=block->start; - alloc.flags=block->flags; - - DRM_COPY_TO_USER_IOCTL((struct drm_nouveau_mem_alloc __user *)data, - alloc, sizeof(alloc)); + alloc->map_handle=block->map_handle; + alloc->offset=block->start; + alloc->flags=block->flags; return 0; } -int nouveau_ioctl_mem_free(DRM_IOCTL_ARGS) +int nouveau_ioctl_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct drm_nouveau_mem_free memfree; + struct drm_nouveau_mem_free *memfree = data; struct mem_block *block; - DRM_COPY_FROM_USER_IOCTL(memfree, - (struct drm_nouveau_mem_free_t __user *)data, - sizeof(memfree)); - block=NULL; - if (memfree.flags&NOUVEAU_MEM_FB) - block = find_block(dev_priv->fb_heap, memfree.offset); - else if (memfree.flags&NOUVEAU_MEM_AGP) - block = find_block(dev_priv->agp_heap, memfree.offset); - else if (memfree.flags&NOUVEAU_MEM_PCI) - block = find_block(dev_priv->pci_heap, memfree.offset); + if (memfree->flags & NOUVEAU_MEM_FB) + block = find_block(dev_priv->fb_heap, memfree->offset); + else if (memfree->flags & NOUVEAU_MEM_AGP) + block = find_block(dev_priv->agp_heap, memfree->offset); + else if (memfree->flags & NOUVEAU_MEM_PCI) + block = find_block(dev_priv->pci_heap, memfree->offset); if (!block) return -EFAULT; if (block->file_priv != file_priv) diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index 6a78bb23..24a306e8 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -128,29 +128,22 @@ nouveau_notifier_alloc(struct drm_device *dev, int channel, uint32_t handle, } int -nouveau_ioctl_notifier_alloc(DRM_IOCTL_ARGS) +nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; - struct drm_nouveau_notifier_alloc na; + struct drm_nouveau_notifier_alloc *na = data; int ret; - DRM_COPY_FROM_USER_IOCTL(na, - (struct drm_nouveau_notifier_alloc __user*)data, - sizeof(na)); - - if (!nouveau_fifo_owner(dev, file_priv, na.channel)) { + if (!nouveau_fifo_owner(dev, file_priv, na->channel)) { DRM_ERROR("pid %d doesn't own channel %d\n", - DRM_CURRENTPID, na.channel); + DRM_CURRENTPID, na->channel); return -EPERM; } - ret = nouveau_notifier_alloc(dev, na.channel, na.handle, - na.count, &na.offset); + ret = nouveau_notifier_alloc(dev, na->channel, na->handle, + na->count, &na->offset); if (ret) return ret; - DRM_COPY_TO_USER_IOCTL((struct drm_nouveau_notifier_alloc __user*)data, - na, sizeof(na)); return 0; } diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index f11cc115..e8b12bb7 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -1024,40 +1024,37 @@ nouveau_gpuobj_channel_takedown(struct drm_device *dev, int channel) } -int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS) +int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; - struct drm_nouveau_grobj_alloc init; + struct drm_nouveau_grobj_alloc *init = data; struct nouveau_gpuobj *gr = NULL; int ret; - DRM_COPY_FROM_USER_IOCTL(init, - (struct drm_nouveau_grobj_alloc_t __user*)data, - sizeof(init)); - - if (!nouveau_fifo_owner(dev, file_priv, init.channel)) { + if (!nouveau_fifo_owner(dev, file_priv, init->channel)) { DRM_ERROR("pid %d doesn't own channel %d\n", - DRM_CURRENTPID, init.channel); + DRM_CURRENTPID, init->channel); return -EINVAL; } //FIXME: check args, only allow trusted objects to be created - if (init.handle == ~0) + if (init->handle == ~0) return -EINVAL; - if (nouveau_gpuobj_ref_find(dev, init.channel, init.handle, NULL) == 0) + if (nouveau_gpuobj_ref_find(dev, init->channel, init->handle, NULL) == + 0) return -EEXIST; - if ((ret = nouveau_gpuobj_gr_new(dev, init.channel, init.class, &gr))) { + ret = nouveau_gpuobj_gr_new(dev, init->channel, init->class, &gr); + if (ret) { DRM_ERROR("Error creating gr object: %d (%d/0x%08x)\n", - ret, init.channel, init.handle); + ret, init->channel, init->handle); return ret; } - if ((ret = nouveau_gpuobj_ref_add(dev, init.channel, init.handle, + if ((ret = nouveau_gpuobj_ref_add(dev, init->channel, init->handle, gr, NULL))) { DRM_ERROR("Error referencing gr object: %d (%d/0x%08x\n)", - ret, init.channel, init.handle); + ret, init->channel, init->handle); nouveau_gpuobj_del(dev, &gr); return ret; } diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index aea6bcf5..f45f2783 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -427,40 +427,35 @@ int nouveau_unload(struct drm_device *dev) return 0; } -int nouveau_ioctl_getparam(DRM_IOCTL_ARGS) +int nouveau_ioctl_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct drm_nouveau_getparam getparam; + struct drm_nouveau_getparam *getparam = data; - DRM_COPY_FROM_USER_IOCTL(getparam, - (struct drm_nouveau_getparam __user *)data, - sizeof(getparam)); - - switch (getparam.param) { + switch (getparam->param) { case NOUVEAU_GETPARAM_PCI_VENDOR: - getparam.value=dev->pci_vendor; + getparam->value=dev->pci_vendor; break; case NOUVEAU_GETPARAM_PCI_DEVICE: - getparam.value=dev->pci_device; + getparam->value=dev->pci_device; break; case NOUVEAU_GETPARAM_BUS_TYPE: if (drm_device_is_agp(dev)) - getparam.value=NV_AGP; + getparam->value=NV_AGP; else if (drm_device_is_pcie(dev)) - getparam.value=NV_PCIE; + getparam->value=NV_PCIE; else - getparam.value=NV_PCI; + getparam->value=NV_PCI; break; case NOUVEAU_GETPARAM_FB_PHYSICAL: - getparam.value=dev_priv->fb_phys; + getparam->value=dev_priv->fb_phys; break; case NOUVEAU_GETPARAM_AGP_PHYSICAL: - getparam.value=dev_priv->gart_info.aper_base; + getparam->value=dev_priv->gart_info.aper_base; break; case NOUVEAU_GETPARAM_PCI_PHYSICAL: if ( dev -> sg ) - getparam.value=(uint64_t) dev->sg->virtual; + getparam->value=(uint64_t) dev->sg->virtual; else { DRM_ERROR("Requested PCIGART address, while no PCIGART was created\n"); @@ -468,34 +463,27 @@ int nouveau_ioctl_getparam(DRM_IOCTL_ARGS) } break; case NOUVEAU_GETPARAM_FB_SIZE: - getparam.value=dev_priv->fb_available_size; + getparam->value=dev_priv->fb_available_size; break; case NOUVEAU_GETPARAM_AGP_SIZE: - getparam.value=dev_priv->gart_info.aper_size; + getparam->value=dev_priv->gart_info.aper_size; break; default: - DRM_ERROR("unknown parameter %lld\n", getparam.param); + DRM_ERROR("unknown parameter %lld\n", getparam->param); return -EINVAL; } - DRM_COPY_TO_USER_IOCTL((struct drm_nouveau_getparam __user *)data, - getparam, sizeof(getparam)); return 0; } -int nouveau_ioctl_setparam(DRM_IOCTL_ARGS) +int nouveau_ioctl_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct drm_nouveau_setparam setparam; - - DRM_COPY_FROM_USER_IOCTL(setparam, - (struct drm_nouveau_setparam __user *)data, - sizeof(setparam)); + struct drm_nouveau_setparam *setparam = data; - switch (setparam.param) { + switch (setparam->param) { case NOUVEAU_SETPARAM_CMDBUF_LOCATION: - switch (setparam.value) { + switch (setparam->value) { case NOUVEAU_MEM_AGP: case NOUVEAU_MEM_FB: case NOUVEAU_MEM_PCI: @@ -503,16 +491,16 @@ int nouveau_ioctl_setparam(DRM_IOCTL_ARGS) break; default: DRM_ERROR("invalid CMDBUF_LOCATION value=%lld\n", - setparam.value); + setparam->value); return -EINVAL; } - dev_priv->config.cmdbuf.location = setparam.value; + dev_priv->config.cmdbuf.location = setparam->value; break; case NOUVEAU_SETPARAM_CMDBUF_SIZE: - dev_priv->config.cmdbuf.size = setparam.value; + dev_priv->config.cmdbuf.size = setparam->value; break; default: - DRM_ERROR("unknown parameter %lld\n", setparam.param); + DRM_ERROR("unknown parameter %lld\n", setparam->param); return -EINVAL; } diff --git a/shared-core/r128_cce.c b/shared-core/r128_cce.c index f91e9031..5bed45bc 100644 --- a/shared-core/r128_cce.c +++ b/shared-core/r128_cce.c @@ -623,21 +623,17 @@ int r128_do_cleanup_cce(struct drm_device * dev) return 0; } -int r128_cce_init(DRM_IOCTL_ARGS) +int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; - drm_r128_init_t init; + drm_r128_init_t *init = data; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(init, (drm_r128_init_t __user *) data, - sizeof(init)); - - switch (init.func) { + switch (init->func) { case R128_INIT_CCE: - return r128_do_init_cce(dev, &init); + return r128_do_init_cce(dev, init); case R128_CLEANUP_CCE: return r128_do_cleanup_cce(dev); } @@ -645,9 +641,8 @@ int r128_cce_init(DRM_IOCTL_ARGS) return -EINVAL; } -int r128_cce_start(DRM_IOCTL_ARGS) +int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); @@ -666,30 +661,26 @@ int r128_cce_start(DRM_IOCTL_ARGS) /* Stop the CCE. The engine must have been idled before calling this * routine. */ -int r128_cce_stop(DRM_IOCTL_ARGS) +int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_cce_stop_t stop; + drm_r128_cce_stop_t *stop = data; int ret; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *) data, - sizeof(stop)); - /* Flush any pending CCE commands. This ensures any outstanding * commands are exectuted by the engine before we turn it off. */ - if (stop.flush) { + if (stop->flush) { r128_do_cce_flush(dev_priv); } /* If we fail to make the engine go idle, we return an error * code so that the DRM ioctl wrapper can try again. */ - if (stop.idle) { + if (stop->idle) { ret = r128_do_cce_idle(dev_priv); if (ret) return ret; @@ -709,9 +700,8 @@ int r128_cce_stop(DRM_IOCTL_ARGS) /* Just reset the CCE ring. Called as part of an X Server engine reset. */ -int r128_cce_reset(DRM_IOCTL_ARGS) +int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); @@ -730,9 +720,8 @@ int r128_cce_reset(DRM_IOCTL_ARGS) return 0; } -int r128_cce_idle(DRM_IOCTL_ARGS) +int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); @@ -745,9 +734,8 @@ int r128_cce_idle(DRM_IOCTL_ARGS) return r128_do_cce_idle(dev_priv); } -int r128_engine_reset(DRM_IOCTL_ARGS) +int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -755,7 +743,7 @@ int r128_engine_reset(DRM_IOCTL_ARGS) return r128_do_engine_reset(dev); } -int r128_fullscreen(DRM_IOCTL_ARGS) +int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv) { return -EINVAL; } @@ -910,41 +898,35 @@ static int r128_cce_get_buffers(struct drm_device * dev, return 0; } -int r128_cce_buffers(DRM_IOCTL_ARGS) +int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; struct drm_device_dma *dma = dev->dma; int ret = 0; - struct drm_dma __user *argp = (void __user *)data; - struct drm_dma d; + struct drm_dma *d = data; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); - /* Please don't send us buffers. */ - if (d.send_count != 0) { + if (d->send_count != 0) { DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d.send_count); + DRM_CURRENTPID, d->send_count); return -EINVAL; } /* We'll send you buffers. */ - if (d.request_count < 0 || d.request_count > dma->buf_count) { + if (d->request_count < 0 || d->request_count > dma->buf_count) { DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d.request_count, dma->buf_count); + DRM_CURRENTPID, d->request_count, dma->buf_count); return -EINVAL; } - d.granted_count = 0; + d->granted_count = 0; - if (d.request_count) { - ret = r128_cce_get_buffers(dev, file_priv, &d); + if (d->request_count) { + ret = r128_cce_get_buffers(dev, file_priv, d); } - DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); - return ret; } diff --git a/shared-core/r128_drv.h b/shared-core/r128_drv.h index 6eb59e33..abb99898 100644 --- a/shared-core/r128_drv.h +++ b/shared-core/r128_drv.h @@ -133,14 +133,14 @@ extern struct drm_ioctl_desc r128_ioctls[]; extern int r128_max_ioctl; /* r128_cce.c */ -extern int r128_cce_init(DRM_IOCTL_ARGS); -extern int r128_cce_start(DRM_IOCTL_ARGS); -extern int r128_cce_stop(DRM_IOCTL_ARGS); -extern int r128_cce_reset(DRM_IOCTL_ARGS); -extern int r128_cce_idle(DRM_IOCTL_ARGS); -extern int r128_engine_reset(DRM_IOCTL_ARGS); -extern int r128_fullscreen(DRM_IOCTL_ARGS); -extern int r128_cce_buffers(DRM_IOCTL_ARGS); +extern int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); extern void r128_freelist_reset(struct drm_device * dev); diff --git a/shared-core/r128_state.c b/shared-core/r128_state.c index 4c244377..b7f483ca 100644 --- a/shared-core/r128_state.c +++ b/shared-core/r128_state.c @@ -1242,25 +1242,21 @@ static void r128_cce_dispatch_stipple(struct drm_device * dev, u32 * stipple) * IOCTL functions */ -static int r128_cce_clear(DRM_IOCTL_ARGS) +static int r128_cce_clear(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_clear_t clear; + drm_r128_clear_t *clear = data; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(clear, (drm_r128_clear_t __user *) data, - sizeof(clear)); - RING_SPACE_TEST_WITH_RETURN(dev_priv); if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; - r128_cce_dispatch_clear(dev, &clear); + r128_cce_dispatch_clear(dev, clear); COMMIT_RING(); /* Make sure we restore the 3D state next time. @@ -1310,9 +1306,8 @@ static int r128_do_cleanup_pageflip(struct drm_device * dev) * They can & should be intermixed to support multiple 3d windows. */ -static int r128_cce_flip(DRM_IOCTL_ARGS) +static int r128_cce_flip(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG("%s\n", __FUNCTION__); @@ -1329,9 +1324,8 @@ static int r128_cce_flip(DRM_IOCTL_ARGS) return 0; } -static int r128_cce_swap(DRM_IOCTL_ARGS) +static int r128_cce_swap(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; DRM_DEBUG("%s\n", __FUNCTION__); @@ -1351,14 +1345,13 @@ static int r128_cce_swap(DRM_IOCTL_ARGS) return 0; } -static int r128_cce_vertex(DRM_IOCTL_ARGS) +static int r128_cce_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; drm_r128_buf_priv_t *buf_priv; - drm_r128_vertex_t vertex; + drm_r128_vertex_t *vertex = data; LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -1367,27 +1360,24 @@ static int r128_cce_vertex(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(vertex, (drm_r128_vertex_t __user *) data, - sizeof(vertex)); - DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", - DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard); + DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard); - if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { + if (vertex->idx < 0 || vertex->idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", - vertex.idx, dma->buf_count - 1); + vertex->idx, dma->buf_count - 1); return -EINVAL; } - if (vertex.prim < 0 || - vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { - DRM_ERROR("buffer prim %d\n", vertex.prim); + if (vertex->prim < 0 || + vertex->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { + DRM_ERROR("buffer prim %d\n", vertex->prim); return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); - buf = dma->buflist[vertex.idx]; + buf = dma->buflist[vertex->idx]; buf_priv = buf->dev_private; if (buf->file_priv != file_priv) { @@ -1396,13 +1386,13 @@ static int r128_cce_vertex(DRM_IOCTL_ARGS) return -EINVAL; } if (buf->pending) { - DRM_ERROR("sending pending buffer %d\n", vertex.idx); + DRM_ERROR("sending pending buffer %d\n", vertex->idx); return -EINVAL; } - buf->used = vertex.count; - buf_priv->prim = vertex.prim; - buf_priv->discard = vertex.discard; + buf->used = vertex->count; + buf_priv->prim = vertex->prim; + buf_priv->discard = vertex->discard; r128_cce_dispatch_vertex(dev, buf); @@ -1410,14 +1400,13 @@ static int r128_cce_vertex(DRM_IOCTL_ARGS) return 0; } -static int r128_cce_indices(DRM_IOCTL_ARGS) +static int r128_cce_indices(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; drm_r128_buf_priv_t *buf_priv; - drm_r128_indices_t elts; + drm_r128_indices_t *elts = data; int count; LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -1427,26 +1416,24 @@ static int r128_cce_indices(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(elts, (drm_r128_indices_t __user *) data, - sizeof(elts)); - DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, - elts.idx, elts.start, elts.end, elts.discard); + elts->idx, elts->start, elts->end, elts->discard); - if (elts.idx < 0 || elts.idx >= dma->buf_count) { + if (elts->idx < 0 || elts->idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", - elts.idx, dma->buf_count - 1); + elts->idx, dma->buf_count - 1); return -EINVAL; } - if (elts.prim < 0 || elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { - DRM_ERROR("buffer prim %d\n", elts.prim); + if (elts->prim < 0 || + elts->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { + DRM_ERROR("buffer prim %d\n", elts->prim); return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); - buf = dma->buflist[elts.idx]; + buf = dma->buflist[elts->idx]; buf_priv = buf->dev_private; if (buf->file_priv != file_priv) { @@ -1455,89 +1442,81 @@ static int r128_cce_indices(DRM_IOCTL_ARGS) return -EINVAL; } if (buf->pending) { - DRM_ERROR("sending pending buffer %d\n", elts.idx); + DRM_ERROR("sending pending buffer %d\n", elts->idx); return -EINVAL; } - count = (elts.end - elts.start) / sizeof(u16); - elts.start -= R128_INDEX_PRIM_OFFSET; + count = (elts->end - elts->start) / sizeof(u16); + elts->start -= R128_INDEX_PRIM_OFFSET; - if (elts.start & 0x7) { - DRM_ERROR("misaligned buffer 0x%x\n", elts.start); + if (elts->start & 0x7) { + DRM_ERROR("misaligned buffer 0x%x\n", elts->start); return -EINVAL; } - if (elts.start < buf->used) { - DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used); + if (elts->start < buf->used) { + DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used); return -EINVAL; } - buf->used = elts.end; - buf_priv->prim = elts.prim; - buf_priv->discard = elts.discard; + buf->used = elts->end; + buf_priv->prim = elts->prim; + buf_priv->discard = elts->discard; - r128_cce_dispatch_indices(dev, buf, elts.start, elts.end, count); + r128_cce_dispatch_indices(dev, buf, elts->start, elts->end, count); COMMIT_RING(); return 0; } -static int r128_cce_blit(DRM_IOCTL_ARGS) +static int r128_cce_blit(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; struct drm_device_dma *dma = dev->dma; drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_blit_t blit; + drm_r128_blit_t *blit = data; int ret; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(blit, (drm_r128_blit_t __user *) data, - sizeof(blit)); - - DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit.idx); + DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit->idx); - if (blit.idx < 0 || blit.idx >= dma->buf_count) { + if (blit->idx < 0 || blit->idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", - blit.idx, dma->buf_count - 1); + blit->idx, dma->buf_count - 1); return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); - ret = r128_cce_dispatch_blit(dev, file_priv, &blit); + ret = r128_cce_dispatch_blit(dev, file_priv, blit); COMMIT_RING(); return ret; } -static int r128_cce_depth(DRM_IOCTL_ARGS) +static int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_depth_t depth; + drm_r128_depth_t *depth = data; int ret; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(depth, (drm_r128_depth_t __user *) data, - sizeof(depth)); - RING_SPACE_TEST_WITH_RETURN(dev_priv); ret = -EINVAL; - switch (depth.func) { + switch (depth->func) { case R128_WRITE_SPAN: - ret = r128_cce_dispatch_write_span(dev, &depth); + ret = r128_cce_dispatch_write_span(dev, depth); break; case R128_WRITE_PIXELS: - ret = r128_cce_dispatch_write_pixels(dev, &depth); + ret = r128_cce_dispatch_write_pixels(dev, depth); break; case R128_READ_SPAN: - ret = r128_cce_dispatch_read_span(dev, &depth); + ret = r128_cce_dispatch_read_span(dev, depth); break; case R128_READ_PIXELS: - ret = r128_cce_dispatch_read_pixels(dev, &depth); + ret = r128_cce_dispatch_read_pixels(dev, depth); break; } @@ -1545,19 +1524,15 @@ static int r128_cce_depth(DRM_IOCTL_ARGS) return ret; } -static int r128_cce_stipple(DRM_IOCTL_ARGS) +static int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_stipple_t stipple; + drm_r128_stipple_t *stipple = data; u32 mask[32]; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(stipple, (drm_r128_stipple_t __user *) data, - sizeof(stipple)); - - if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32))) + if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32))) return -EFAULT; RING_SPACE_TEST_WITH_RETURN(dev_priv); @@ -1568,14 +1543,13 @@ static int r128_cce_stipple(DRM_IOCTL_ARGS) return 0; } -static int r128_cce_indirect(DRM_IOCTL_ARGS) +static int r128_cce_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; drm_r128_buf_priv_t *buf_priv; - drm_r128_indirect_t indirect; + drm_r128_indirect_t *indirect = data; #if 0 RING_LOCALS; #endif @@ -1587,19 +1561,17 @@ static int r128_cce_indirect(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(indirect, (drm_r128_indirect_t __user *) data, - sizeof(indirect)); - DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n", - indirect.idx, indirect.start, indirect.end, indirect.discard); + indirect->idx, indirect->start, indirect->end, + indirect->discard); - if (indirect.idx < 0 || indirect.idx >= dma->buf_count) { + if (indirect->idx < 0 || indirect->idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", - indirect.idx, dma->buf_count - 1); + indirect->idx, dma->buf_count - 1); return -EINVAL; } - buf = dma->buflist[indirect.idx]; + buf = dma->buflist[indirect->idx]; buf_priv = buf->dev_private; if (buf->file_priv != file_priv) { @@ -1608,21 +1580,21 @@ static int r128_cce_indirect(DRM_IOCTL_ARGS) return -EINVAL; } if (buf->pending) { - DRM_ERROR("sending pending buffer %d\n", indirect.idx); + DRM_ERROR("sending pending buffer %d\n", indirect->idx); return -EINVAL; } - if (indirect.start < buf->used) { + if (indirect->start < buf->used) { DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", - indirect.start, buf->used); + indirect->start, buf->used); return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); - buf->used = indirect.end; - buf_priv->discard = indirect.discard; + buf->used = indirect->end; + buf_priv->discard = indirect->discard; #if 0 /* Wait for the 3D stream to idle before the indirect buffer @@ -1637,17 +1609,16 @@ static int r128_cce_indirect(DRM_IOCTL_ARGS) * X server. This is insecure and is thus only available to * privileged clients. */ - r128_cce_dispatch_indirect(dev, buf, indirect.start, indirect.end); + r128_cce_dispatch_indirect(dev, buf, indirect->start, indirect->end); COMMIT_RING(); return 0; } -static int r128_getparam(DRM_IOCTL_ARGS) +static int r128_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_getparam_t param; + drm_r128_getparam_t *param = data; int value; if (!dev_priv) { @@ -1655,12 +1626,9 @@ static int r128_getparam(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(param, (drm_r128_getparam_t __user *) data, - sizeof(param)); - DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - switch (param.param) { + switch (param->param) { case R128_PARAM_IRQ_NR: value = dev->irq; break; @@ -1668,7 +1636,7 @@ static int r128_getparam(DRM_IOCTL_ARGS) return -EINVAL; } - if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { + if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { DRM_ERROR("copy_to_user\n"); return -EFAULT; } @@ -1692,23 +1660,23 @@ void r128_driver_lastclose(struct drm_device * dev) } struct drm_ioctl_desc r128_ioctls[] = { - [DRM_IOCTL_NR(DRM_R128_INIT)] = {r128_cce_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_R128_CCE_START)] = {r128_cce_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_R128_CCE_STOP)] = {r128_cce_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_R128_CCE_RESET)] = {r128_cce_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_R128_CCE_IDLE)] = {r128_cce_idle, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_R128_RESET)] = {r128_engine_reset, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_R128_FULLSCREEN)] = {r128_fullscreen, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_R128_SWAP)] = {r128_cce_swap, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_R128_FLIP)] = {r128_cce_flip, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_R128_CLEAR)] = {r128_cce_clear, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_R128_VERTEX)] = {r128_cce_vertex, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_R128_INDICES)] = {r128_cce_indices, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_R128_BLIT)] = {r128_cce_blit, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_R128_DEPTH)] = {r128_cce_depth, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_R128_STIPPLE)] = {r128_cce_stipple, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_R128_INDIRECT)] = {r128_cce_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_R128_GETPARAM)] = {r128_getparam, DRM_AUTH}, + DRM_IOCTL_DEF(DRM_R128_INIT, r128_cce_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_R128_CCE_START, r128_cce_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_R128_CCE_STOP, r128_cce_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_R128_CCE_RESET, r128_cce_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_R128_CCE_IDLE, r128_cce_idle, DRM_AUTH), + DRM_IOCTL_DEF(DRM_R128_RESET, r128_engine_reset, DRM_AUTH), + DRM_IOCTL_DEF(DRM_R128_FULLSCREEN, r128_fullscreen, DRM_AUTH), + DRM_IOCTL_DEF(DRM_R128_SWAP, r128_cce_swap, DRM_AUTH), + DRM_IOCTL_DEF(DRM_R128_FLIP, r128_cce_flip, DRM_AUTH), + DRM_IOCTL_DEF(DRM_R128_CLEAR, r128_cce_clear, DRM_AUTH), + DRM_IOCTL_DEF(DRM_R128_VERTEX, r128_cce_vertex, DRM_AUTH), + DRM_IOCTL_DEF(DRM_R128_INDICES, r128_cce_indices, DRM_AUTH), + DRM_IOCTL_DEF(DRM_R128_BLIT, r128_cce_blit, DRM_AUTH), + DRM_IOCTL_DEF(DRM_R128_DEPTH, r128_cce_depth, DRM_AUTH), + DRM_IOCTL_DEF(DRM_R128_STIPPLE, r128_cce_stipple, DRM_AUTH), + DRM_IOCTL_DEF(DRM_R128_INDIRECT, r128_cce_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_R128_GETPARAM, r128_getparam, DRM_AUTH), }; int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls); diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index dd87f009..06861381 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -1838,24 +1838,20 @@ static int radeon_do_resume_cp(struct drm_device * dev) return 0; } -int radeon_cp_init(DRM_IOCTL_ARGS) +int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; - drm_radeon_init_t init; + drm_radeon_init_t *init = data; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data, - sizeof(init)); - - if (init.func == RADEON_INIT_R300_CP) + if (init->func == RADEON_INIT_R300_CP) r300_init_reg_flags(); - switch (init.func) { + switch (init->func) { case RADEON_INIT_CP: case RADEON_INIT_R200_CP: case RADEON_INIT_R300_CP: - return radeon_do_init_cp(dev, &init); + return radeon_do_init_cp(dev, init); case RADEON_CLEANUP_CP: return radeon_do_cleanup_cp(dev); } @@ -1863,9 +1859,8 @@ int radeon_cp_init(DRM_IOCTL_ARGS) return -EINVAL; } -int radeon_cp_start(DRM_IOCTL_ARGS) +int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); @@ -1889,33 +1884,29 @@ int radeon_cp_start(DRM_IOCTL_ARGS) /* Stop the CP. The engine must have been idled before calling this * routine. */ -int radeon_cp_stop(DRM_IOCTL_ARGS) +int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_cp_stop_t stop; + drm_radeon_cp_stop_t *stop = data; int ret; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data, - sizeof(stop)); - if (!dev_priv->cp_running) return 0; /* Flush any pending CP commands. This ensures any outstanding * commands are exectuted by the engine before we turn it off. */ - if (stop.flush) { + if (stop->flush) { radeon_do_cp_flush(dev_priv); } /* If we fail to make the engine go idle, we return an error * code so that the DRM ioctl wrapper can try again. */ - if (stop.idle) { + if (stop->idle) { ret = radeon_do_cp_idle(dev_priv); if (ret) return ret; @@ -1983,9 +1974,8 @@ void radeon_do_release(struct drm_device * dev) /* Just reset the CP ring. Called as part of an X Server engine reset. */ -int radeon_cp_reset(DRM_IOCTL_ARGS) +int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); @@ -2004,9 +1994,8 @@ int radeon_cp_reset(DRM_IOCTL_ARGS) return 0; } -int radeon_cp_idle(DRM_IOCTL_ARGS) +int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); @@ -2017,16 +2006,14 @@ int radeon_cp_idle(DRM_IOCTL_ARGS) /* Added by Charl P. Botha to call radeon_do_resume_cp(). */ -int radeon_cp_resume(DRM_IOCTL_ARGS) +int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; return radeon_do_resume_cp(dev); } -int radeon_engine_reset(DRM_IOCTL_ARGS) +int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -2040,7 +2027,7 @@ int radeon_engine_reset(DRM_IOCTL_ARGS) /* KW: Deprecated to say the least: */ -int radeon_fullscreen(DRM_IOCTL_ARGS) +int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv) { return 0; } @@ -2218,42 +2205,36 @@ static int radeon_cp_get_buffers(struct drm_device *dev, return 0; } -int radeon_cp_buffers(DRM_IOCTL_ARGS) +int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; struct drm_device_dma *dma = dev->dma; int ret = 0; - struct drm_dma __user *argp = (void __user *)data; - struct drm_dma d; + struct drm_dma *d = data; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); - /* Please don't send us buffers. */ - if (d.send_count != 0) { + if (d->send_count != 0) { DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d.send_count); + DRM_CURRENTPID, d->send_count); return -EINVAL; } /* We'll send you buffers. */ - if (d.request_count < 0 || d.request_count > dma->buf_count) { + if (d->request_count < 0 || d->request_count > dma->buf_count) { DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d.request_count, dma->buf_count); + DRM_CURRENTPID, d->request_count, dma->buf_count); return -EINVAL; } - d.granted_count = 0; + d->granted_count = 0; - if (d.request_count) { - ret = radeon_cp_get_buffers(dev, file_priv, &d); + if (d->request_count) { + ret = radeon_cp_get_buffers(dev, file_priv, d); } - DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); - return ret; } diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 631fe007..006559df 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -335,15 +335,15 @@ static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, } /* radeon_cp.c */ -extern int radeon_cp_init(DRM_IOCTL_ARGS); -extern int radeon_cp_start(DRM_IOCTL_ARGS); -extern int radeon_cp_stop(DRM_IOCTL_ARGS); -extern int radeon_cp_reset(DRM_IOCTL_ARGS); -extern int radeon_cp_idle(DRM_IOCTL_ARGS); -extern int radeon_cp_resume(DRM_IOCTL_ARGS); -extern int radeon_engine_reset(DRM_IOCTL_ARGS); -extern int radeon_fullscreen(DRM_IOCTL_ARGS); -extern int radeon_cp_buffers(DRM_IOCTL_ARGS); +extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); extern void radeon_freelist_reset(struct drm_device * dev); extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); @@ -352,16 +352,16 @@ extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); -extern int radeon_mem_alloc(DRM_IOCTL_ARGS); -extern int radeon_mem_free(DRM_IOCTL_ARGS); -extern int radeon_mem_init_heap(DRM_IOCTL_ARGS); +extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); extern void radeon_mem_takedown(struct mem_block **heap); extern void radeon_mem_release(struct drm_file *file_priv, struct mem_block *heap); /* radeon_irq.c */ -extern int radeon_irq_emit(DRM_IOCTL_ARGS); -extern int radeon_irq_wait(DRM_IOCTL_ARGS); +extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); extern void radeon_do_release(struct drm_device * dev); extern int radeon_driver_vblank_wait(struct drm_device * dev, diff --git a/shared-core/radeon_irq.c b/shared-core/radeon_irq.c index 140f9668..1ece6399 100644 --- a/shared-core/radeon_irq.c +++ b/shared-core/radeon_irq.c @@ -197,11 +197,10 @@ int radeon_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence) /* Needs the lock as it touches the ring. */ -int radeon_irq_emit(DRM_IOCTL_ARGS) +int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_irq_emit_t emit; + drm_radeon_irq_emit_t *emit = data; int result; LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -211,12 +210,9 @@ int radeon_irq_emit(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(emit, (drm_radeon_irq_emit_t __user *) data, - sizeof(emit)); - result = radeon_emit_irq(dev); - if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) { + if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { DRM_ERROR("copy_to_user\n"); return -EFAULT; } @@ -226,21 +222,17 @@ int radeon_irq_emit(DRM_IOCTL_ARGS) /* Doesn't need the hardware lock. */ -int radeon_irq_wait(DRM_IOCTL_ARGS) +int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_irq_wait_t irqwait; + drm_radeon_irq_wait_t *irqwait = data; if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(irqwait, (drm_radeon_irq_wait_t __user *) data, - sizeof(irqwait)); - - return radeon_wait_irq(dev, irqwait.irq_seq); + return radeon_wait_irq(dev, irqwait->irq_seq); } static void radeon_enable_interrupt(struct drm_device *dev) diff --git a/shared-core/radeon_mem.c b/shared-core/radeon_mem.c index 82d454ff..9947e940 100644 --- a/shared-core/radeon_mem.c +++ b/shared-core/radeon_mem.c @@ -217,11 +217,10 @@ static struct mem_block **get_heap(drm_radeon_private_t * dev_priv, int region) } } -int radeon_mem_alloc(DRM_IOCTL_ARGS) +int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_mem_alloc_t alloc; + drm_radeon_mem_alloc_t *alloc = data; struct mem_block *block, **heap; if (!dev_priv) { @@ -229,25 +228,23 @@ int radeon_mem_alloc(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(alloc, (drm_radeon_mem_alloc_t __user *) data, - sizeof(alloc)); - - heap = get_heap(dev_priv, alloc.region); + heap = get_heap(dev_priv, alloc->region); if (!heap || !*heap) return -EFAULT; /* Make things easier on ourselves: all allocations at least * 4k aligned. */ - if (alloc.alignment < 12) - alloc.alignment = 12; + if (alloc->alignment < 12) + alloc->alignment = 12; - block = alloc_block(*heap, alloc.size, alloc.alignment, file_priv); + block = alloc_block(*heap, alloc->size, alloc->alignment, file_priv); if (!block) return -ENOMEM; - if (DRM_COPY_TO_USER(alloc.region_offset, &block->start, sizeof(int))) { + if (DRM_COPY_TO_USER(alloc->region_offset, &block->start, + sizeof(int))) { DRM_ERROR("copy_to_user\n"); return -EFAULT; } @@ -255,11 +252,10 @@ int radeon_mem_alloc(DRM_IOCTL_ARGS) return 0; } -int radeon_mem_free(DRM_IOCTL_ARGS) +int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_mem_free_t memfree; + drm_radeon_mem_free_t *memfree = data; struct mem_block *block, **heap; if (!dev_priv) { @@ -267,14 +263,11 @@ int radeon_mem_free(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_mem_free_t __user *) data, - sizeof(memfree)); - - heap = get_heap(dev_priv, memfree.region); + heap = get_heap(dev_priv, memfree->region); if (!heap || !*heap) return -EFAULT; - block = find_block(*heap, memfree.region_offset); + block = find_block(*heap, memfree->region_offset); if (!block) return -EFAULT; @@ -285,11 +278,10 @@ int radeon_mem_free(DRM_IOCTL_ARGS) return 0; } -int radeon_mem_init_heap(DRM_IOCTL_ARGS) +int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_mem_init_heap_t initheap; + drm_radeon_mem_init_heap_t *initheap = data; struct mem_block **heap; if (!dev_priv) { @@ -297,11 +289,7 @@ int radeon_mem_init_heap(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(initheap, - (drm_radeon_mem_init_heap_t __user *) data, - sizeof(initheap)); - - heap = get_heap(dev_priv, initheap.region); + heap = get_heap(dev_priv, initheap->region); if (!heap) return -EFAULT; @@ -310,5 +298,5 @@ int radeon_mem_init_heap(DRM_IOCTL_ARGS) return -EFAULT; } - return init_heap(heap, initheap.start, initheap.size); + return init_heap(heap, initheap->start, initheap->size); } diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c index 3ca49d6a..ac7f6011 100644 --- a/shared-core/radeon_state.c +++ b/shared-core/radeon_state.c @@ -2075,71 +2075,58 @@ static void radeon_surfaces_release(struct drm_file *file_priv, /* ================================================================ * IOCTL functions */ -static int radeon_surface_alloc(DRM_IOCTL_ARGS) +static int radeon_surface_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_surface_alloc_t alloc; + drm_radeon_surface_alloc_t *alloc = data; if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(alloc, - (drm_radeon_surface_alloc_t __user *) data, - sizeof(alloc)); - - if (alloc_surface(&alloc, dev_priv, file_priv) == -1) + if (alloc_surface(alloc, dev_priv, file_priv) == -1) return -EINVAL; else return 0; } -static int radeon_surface_free(DRM_IOCTL_ARGS) +static int radeon_surface_free(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_surface_free_t memfree; + drm_radeon_surface_free_t *memfree = data; if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_surface_free_t __user *) data, - sizeof(memfree)); - - if (free_surface(file_priv, dev_priv, memfree.address)) + if (free_surface(file_priv, dev_priv, memfree->address)) return -EINVAL; else return 0; } -static int radeon_cp_clear(DRM_IOCTL_ARGS) +static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_radeon_clear_t clear; + drm_radeon_clear_t *clear = data; drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(clear, (drm_radeon_clear_t __user *) data, - sizeof(clear)); - RING_SPACE_TEST_WITH_RETURN(dev_priv); if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; - if (DRM_COPY_FROM_USER(&depth_boxes, clear.depth_boxes, + if (DRM_COPY_FROM_USER(&depth_boxes, clear->depth_boxes, sarea_priv->nbox * sizeof(depth_boxes[0]))) return -EFAULT; - radeon_cp_dispatch_clear(dev, &clear, depth_boxes); + radeon_cp_dispatch_clear(dev, clear, depth_boxes); COMMIT_RING(); return 0; @@ -2175,9 +2162,8 @@ static int radeon_do_init_pageflip(struct drm_device * dev) /* Swapping and flipping are different operations, need different ioctls. * They can & should be intermixed to support multiple 3d windows. */ -static int radeon_cp_flip(DRM_IOCTL_ARGS) +static int radeon_cp_flip(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); @@ -2194,9 +2180,8 @@ static int radeon_cp_flip(DRM_IOCTL_ARGS) return 0; } -static int radeon_cp_swap(DRM_IOCTL_ARGS) +static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; DRM_DEBUG("\n"); @@ -2215,14 +2200,13 @@ static int radeon_cp_swap(DRM_IOCTL_ARGS) return 0; } -static int radeon_cp_vertex(DRM_IOCTL_ARGS) +static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; - drm_radeon_vertex_t vertex; + drm_radeon_vertex_t *vertex = data; drm_radeon_tcl_prim_t prim; LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -2234,26 +2218,23 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) sarea_priv = dev_priv->sarea_priv; - DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex_t __user *) data, - sizeof(vertex)); - DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", - DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard); + DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard); - if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { + if (vertex->idx < 0 || vertex->idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", - vertex.idx, dma->buf_count - 1); + vertex->idx, dma->buf_count - 1); return -EINVAL; } - if (vertex.prim < 0 || vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { - DRM_ERROR("buffer prim %d\n", vertex.prim); + if (vertex->prim < 0 || vertex->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { + DRM_ERROR("buffer prim %d\n", vertex->prim); return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); - buf = dma->buflist[vertex.idx]; + buf = dma->buflist[vertex->idx]; if (buf->file_priv != file_priv) { DRM_ERROR("process %d using buffer owned by %p\n", @@ -2261,14 +2242,14 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) return -EINVAL; } if (buf->pending) { - DRM_ERROR("sending pending buffer %d\n", vertex.idx); + DRM_ERROR("sending pending buffer %d\n", vertex->idx); return -EINVAL; } /* Build up a prim_t record: */ - if (vertex.count) { - buf->used = vertex.count; /* not used? */ + if (vertex->count) { + buf->used = vertex->count; /* not used? */ if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { if (radeon_emit_state(dev_priv, file_priv, @@ -2286,15 +2267,15 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) } prim.start = 0; - prim.finish = vertex.count; /* unused */ - prim.prim = vertex.prim; - prim.numverts = vertex.count; + prim.finish = vertex->count; /* unused */ + prim.prim = vertex->prim; + prim.numverts = vertex->count; prim.vc_format = dev_priv->sarea_priv->vc_format; radeon_cp_dispatch_vertex(dev, buf, &prim); } - if (vertex.discard) { + if (vertex->discard) { radeon_cp_discard_buffer(dev, buf); } @@ -2302,14 +2283,13 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) return 0; } -static int radeon_cp_indices(DRM_IOCTL_ARGS) +static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; - drm_radeon_indices_t elts; + drm_radeon_indices_t *elts = data; drm_radeon_tcl_prim_t prim; int count; @@ -2321,26 +2301,24 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) } sarea_priv = dev_priv->sarea_priv; - DRM_COPY_FROM_USER_IOCTL(elts, (drm_radeon_indices_t __user *) data, - sizeof(elts)); - DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n", - DRM_CURRENTPID, elts.idx, elts.start, elts.end, elts.discard); + DRM_CURRENTPID, elts->idx, elts->start, elts->end, + elts->discard); - if (elts.idx < 0 || elts.idx >= dma->buf_count) { + if (elts->idx < 0 || elts->idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", - elts.idx, dma->buf_count - 1); + elts->idx, dma->buf_count - 1); return -EINVAL; } - if (elts.prim < 0 || elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { - DRM_ERROR("buffer prim %d\n", elts.prim); + if (elts->prim < 0 || elts->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { + DRM_ERROR("buffer prim %d\n", elts->prim); return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); - buf = dma->buflist[elts.idx]; + buf = dma->buflist[elts->idx]; if (buf->file_priv != file_priv) { DRM_ERROR("process %d using buffer owned by %p\n", @@ -2348,23 +2326,23 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) return -EINVAL; } if (buf->pending) { - DRM_ERROR("sending pending buffer %d\n", elts.idx); + DRM_ERROR("sending pending buffer %d\n", elts->idx); return -EINVAL; } - count = (elts.end - elts.start) / sizeof(u16); - elts.start -= RADEON_INDEX_PRIM_OFFSET; + count = (elts->end - elts->start) / sizeof(u16); + elts->start -= RADEON_INDEX_PRIM_OFFSET; - if (elts.start & 0x7) { - DRM_ERROR("misaligned buffer 0x%x\n", elts.start); + if (elts->start & 0x7) { + DRM_ERROR("misaligned buffer 0x%x\n", elts->start); return -EINVAL; } - if (elts.start < buf->used) { - DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used); + if (elts->start < buf->used) { + DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used); return -EINVAL; } - buf->used = elts.end; + buf->used = elts->end; if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { if (radeon_emit_state(dev_priv, file_priv, @@ -2383,15 +2361,15 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) /* Build up a prim_t record: */ - prim.start = elts.start; - prim.finish = elts.end; - prim.prim = elts.prim; + prim.start = elts->start; + prim.finish = elts->end; + prim.prim = elts->prim; prim.offset = 0; /* offset from start of dma buffers */ prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ prim.vc_format = dev_priv->sarea_priv->vc_format; radeon_cp_dispatch_indices(dev, buf, &prim); - if (elts.discard) { + if (elts->discard) { radeon_cp_discard_buffer(dev, buf); } @@ -2399,51 +2377,43 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) return 0; } -static int radeon_cp_texture(DRM_IOCTL_ARGS) +static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_texture_t tex; + drm_radeon_texture_t *tex = data; drm_radeon_tex_image_t image; int ret; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(tex, (drm_radeon_texture_t __user *) data, - sizeof(tex)); - - if (tex.image == NULL) { + if (tex->image == NULL) { DRM_ERROR("null texture image!\n"); return -EINVAL; } if (DRM_COPY_FROM_USER(&image, - (drm_radeon_tex_image_t __user *) tex.image, + (drm_radeon_tex_image_t __user *) tex->image, sizeof(image))) return -EFAULT; RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); - ret = radeon_cp_dispatch_texture(dev, file_priv, &tex, &image); + ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image); COMMIT_RING(); return ret; } -static int radeon_cp_stipple(DRM_IOCTL_ARGS) +static int radeon_cp_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_stipple_t stipple; + drm_radeon_stipple_t *stipple = data; u32 mask[32]; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(stipple, (drm_radeon_stipple_t __user *) data, - sizeof(stipple)); - - if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32))) + if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32))) return -EFAULT; RING_SPACE_TEST_WITH_RETURN(dev_priv); @@ -2454,13 +2424,12 @@ static int radeon_cp_stipple(DRM_IOCTL_ARGS) return 0; } -static int radeon_cp_indirect(DRM_IOCTL_ARGS) +static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; - drm_radeon_indirect_t indirect; + drm_radeon_indirect_t *indirect = data; RING_LOCALS; LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -2470,20 +2439,17 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(indirect, - (drm_radeon_indirect_t __user *) data, - sizeof(indirect)); - DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n", - indirect.idx, indirect.start, indirect.end, indirect.discard); + indirect->idx, indirect->start, indirect->end, + indirect->discard); - if (indirect.idx < 0 || indirect.idx >= dma->buf_count) { + if (indirect->idx < 0 || indirect->idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", - indirect.idx, dma->buf_count - 1); + indirect->idx, dma->buf_count - 1); return -EINVAL; } - buf = dma->buflist[indirect.idx]; + buf = dma->buflist[indirect->idx]; if (buf->file_priv != file_priv) { DRM_ERROR("process %d using buffer owned by %p\n", @@ -2491,20 +2457,20 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS) return -EINVAL; } if (buf->pending) { - DRM_ERROR("sending pending buffer %d\n", indirect.idx); + DRM_ERROR("sending pending buffer %d\n", indirect->idx); return -EINVAL; } - if (indirect.start < buf->used) { + if (indirect->start < buf->used) { DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", - indirect.start, buf->used); + indirect->start, buf->used); return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); - buf->used = indirect.end; + buf->used = indirect->end; /* Wait for the 3D stream to idle before the indirect buffer * containing 2D acceleration commands is processed. @@ -2519,8 +2485,8 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS) * X server. This is insecure and is thus only available to * privileged clients. */ - radeon_cp_dispatch_indirect(dev, buf, indirect.start, indirect.end); - if (indirect.discard) { + radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end); + if (indirect->discard) { radeon_cp_discard_buffer(dev, buf); } @@ -2528,14 +2494,13 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS) return 0; } -static int radeon_cp_vertex2(DRM_IOCTL_ARGS) +static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; - drm_radeon_vertex2_t vertex; + drm_radeon_vertex2_t *vertex = data; int i; unsigned char laststate; @@ -2548,22 +2513,19 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) sarea_priv = dev_priv->sarea_priv; - DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex2_t __user *) data, - sizeof(vertex)); - DRM_DEBUG("pid=%d index=%d discard=%d\n", - DRM_CURRENTPID, vertex.idx, vertex.discard); + DRM_CURRENTPID, vertex->idx, vertex->discard); - if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { + if (vertex->idx < 0 || vertex->idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", - vertex.idx, dma->buf_count - 1); + vertex->idx, dma->buf_count - 1); return -EINVAL; } RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); - buf = dma->buflist[vertex.idx]; + buf = dma->buflist[vertex->idx]; if (buf->file_priv != file_priv) { DRM_ERROR("process %d using buffer owned by %p\n", @@ -2572,25 +2534,25 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) } if (buf->pending) { - DRM_ERROR("sending pending buffer %d\n", vertex.idx); + DRM_ERROR("sending pending buffer %d\n", vertex->idx); return -EINVAL; } if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) return -EINVAL; - for (laststate = 0xff, i = 0; i < vertex.nr_prims; i++) { + for (laststate = 0xff, i = 0; i < vertex->nr_prims; i++) { drm_radeon_prim_t prim; drm_radeon_tcl_prim_t tclprim; - if (DRM_COPY_FROM_USER(&prim, &vertex.prim[i], sizeof(prim))) + if (DRM_COPY_FROM_USER(&prim, &vertex->prim[i], sizeof(prim))) return -EFAULT; if (prim.stateidx != laststate) { drm_radeon_state_t state; if (DRM_COPY_FROM_USER(&state, - &vertex.state[prim.stateidx], + &vertex->state[prim.stateidx], sizeof(state))) return -EFAULT; @@ -2623,7 +2585,7 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) sarea_priv->nbox = 0; } - if (vertex.discard) { + if (vertex->discard) { radeon_cp_discard_buffer(dev, buf); } @@ -2874,14 +2836,13 @@ static int radeon_emit_wait(struct drm_device * dev, int flags) return 0; } -static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) +static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf = NULL; int idx; - drm_radeon_kcmd_buffer_t cmdbuf; + drm_radeon_kcmd_buffer_t *cmdbuf = data; drm_radeon_cmd_header_t header; int orig_nbox, orig_bufsz; char *kbuf = NULL; @@ -2893,14 +2854,10 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(cmdbuf, - (drm_radeon_kcmd_buffer_t __user *) data, - sizeof(cmdbuf)); - RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); - if (cmdbuf.bufsz > 64 * 1024 || cmdbuf.bufsz < 0) { + if (cmdbuf->bufsz > 64 * 1024 || cmdbuf->bufsz < 0) { return -EINVAL; } @@ -2908,24 +2865,24 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) * races between checking values and using those values in other code, * and simply to avoid a lot of function calls to copy in data. */ - orig_bufsz = cmdbuf.bufsz; + orig_bufsz = cmdbuf->bufsz; if (orig_bufsz != 0) { - kbuf = drm_alloc(cmdbuf.bufsz, DRM_MEM_DRIVER); + kbuf = drm_alloc(cmdbuf->bufsz, DRM_MEM_DRIVER); if (kbuf == NULL) return -ENOMEM; - if (DRM_COPY_FROM_USER(kbuf, (void __user *)cmdbuf.buf, - cmdbuf.bufsz)) { + if (DRM_COPY_FROM_USER(kbuf, (void __user *)cmdbuf->buf, + cmdbuf->bufsz)) { drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); return -EFAULT; } - cmdbuf.buf = kbuf; + cmdbuf->buf = kbuf; } - orig_nbox = cmdbuf.nbox; + orig_nbox = cmdbuf->nbox; if (dev_priv->microcode_version == UCODE_R300) { int temp; - temp = r300_do_cp_cmdbuf(dev, file_priv, &cmdbuf); + temp = r300_do_cp_cmdbuf(dev, file_priv, cmdbuf); if (orig_bufsz != 0) drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); @@ -2934,17 +2891,17 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) } /* microcode_version != r300 */ - while (cmdbuf.bufsz >= sizeof(header)) { + while (cmdbuf->bufsz >= sizeof(header)) { - header.i = *(int *)cmdbuf.buf; - cmdbuf.buf += sizeof(header); - cmdbuf.bufsz -= sizeof(header); + header.i = *(int *)cmdbuf->buf; + cmdbuf->buf += sizeof(header); + cmdbuf->bufsz -= sizeof(header); switch (header.header.cmd_type) { case RADEON_CMD_PACKET: DRM_DEBUG("RADEON_CMD_PACKET\n"); if (radeon_emit_packets - (dev_priv, file_priv, header, &cmdbuf)) { + (dev_priv, file_priv, header, cmdbuf)) { DRM_ERROR("radeon_emit_packets failed\n"); goto err; } @@ -2952,7 +2909,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) case RADEON_CMD_SCALARS: DRM_DEBUG("RADEON_CMD_SCALARS\n"); - if (radeon_emit_scalars(dev_priv, header, &cmdbuf)) { + if (radeon_emit_scalars(dev_priv, header, cmdbuf)) { DRM_ERROR("radeon_emit_scalars failed\n"); goto err; } @@ -2960,7 +2917,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) case RADEON_CMD_VECTORS: DRM_DEBUG("RADEON_CMD_VECTORS\n"); - if (radeon_emit_vectors(dev_priv, header, &cmdbuf)) { + if (radeon_emit_vectors(dev_priv, header, cmdbuf)) { DRM_ERROR("radeon_emit_vectors failed\n"); goto err; } @@ -2988,7 +2945,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) case RADEON_CMD_PACKET3: DRM_DEBUG("RADEON_CMD_PACKET3\n"); - if (radeon_emit_packet3(dev, file_priv, &cmdbuf)) { + if (radeon_emit_packet3(dev, file_priv, cmdbuf)) { DRM_ERROR("radeon_emit_packet3 failed\n"); goto err; } @@ -2997,7 +2954,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) case RADEON_CMD_PACKET3_CLIP: DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n"); if (radeon_emit_packet3_cliprect - (dev, file_priv, &cmdbuf, orig_nbox)) { + (dev, file_priv, cmdbuf, orig_nbox)) { DRM_ERROR("radeon_emit_packet3_clip failed\n"); goto err; } @@ -3005,7 +2962,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) case RADEON_CMD_SCALARS2: DRM_DEBUG("RADEON_CMD_SCALARS2\n"); - if (radeon_emit_scalars2(dev_priv, header, &cmdbuf)) { + if (radeon_emit_scalars2(dev_priv, header, cmdbuf)) { DRM_ERROR("radeon_emit_scalars2 failed\n"); goto err; } @@ -3020,7 +2977,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) break; case RADEON_CMD_VECLINEAR: DRM_DEBUG("RADEON_CMD_VECLINEAR\n"); - if (radeon_emit_veclinear(dev_priv, header, &cmdbuf)) { + if (radeon_emit_veclinear(dev_priv, header, cmdbuf)) { DRM_ERROR("radeon_emit_veclinear failed\n"); goto err; } @@ -3029,7 +2986,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) default: DRM_ERROR("bad cmd_type %d at %p\n", header.header.cmd_type, - cmdbuf.buf - sizeof(header)); + cmdbuf->buf - sizeof(header)); goto err; } } @@ -3047,11 +3004,10 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) return -EINVAL; } -static int radeon_cp_getparam(DRM_IOCTL_ARGS) +static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_getparam_t param; + drm_radeon_getparam_t *param = data; int value; if (!dev_priv) { @@ -3059,12 +3015,9 @@ static int radeon_cp_getparam(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(param, (drm_radeon_getparam_t __user *) data, - sizeof(param)); - DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - switch (param.param) { + switch (param->param) { case RADEON_PARAM_GART_BUFFER_OFFSET: value = dev_priv->gart_buffers_offset; break; @@ -3127,11 +3080,11 @@ static int radeon_cp_getparam(DRM_IOCTL_ARGS) value = radeon_vblank_crtc_get(dev); break; default: - DRM_DEBUG( "Invalid parameter %d\n", param.param ); + DRM_DEBUG( "Invalid parameter %d\n", param->param ); return -EINVAL; } - if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { + if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { DRM_ERROR("copy_to_user\n"); return -EFAULT; } @@ -3139,11 +3092,10 @@ static int radeon_cp_getparam(DRM_IOCTL_ARGS) return 0; } -static int radeon_cp_setparam(DRM_IOCTL_ARGS) +static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_setparam_t sp; + drm_radeon_setparam_t *sp = data; struct drm_radeon_driver_file_fields *radeon_priv; if (!dev_priv) { @@ -3151,21 +3103,19 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS) return -EINVAL; } - DRM_COPY_FROM_USER_IOCTL(sp, (drm_radeon_setparam_t __user *) data, - sizeof(sp)); - - switch (sp.param) { + switch (sp->param) { case RADEON_SETPARAM_FB_LOCATION: radeon_priv = file_priv->driver_priv; - radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value; + radeon_priv->radeon_fb_delta = dev_priv->fb_location - + sp->value; break; case RADEON_SETPARAM_SWITCH_TILING: - if (sp.value == 0) { + if (sp->value == 0) { DRM_DEBUG("color tiling disabled\n"); dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO; dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO; dev_priv->sarea_priv->tiling_enabled = 0; - } else if (sp.value == 1) { + } else if (sp->value == 1) { DRM_DEBUG("color tiling enabled\n"); dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO; dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO; @@ -3173,22 +3123,22 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS) } break; case RADEON_SETPARAM_PCIGART_LOCATION: - dev_priv->pcigart_offset = sp.value; + dev_priv->pcigart_offset = sp->value; dev_priv->pcigart_offset_set = 1; break; case RADEON_SETPARAM_NEW_MEMMAP: - dev_priv->new_memmap = sp.value; + dev_priv->new_memmap = sp->value; break; case RADEON_SETPARAM_PCIGART_TABLE_SIZE: - dev_priv->gart_info.table_size = sp.value; + dev_priv->gart_info.table_size = sp->value; if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE) dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; break; case RADEON_SETPARAM_VBLANK_CRTC: - return radeon_vblank_crtc_set(dev, sp.value); + return radeon_vblank_crtc_set(dev, sp->value); break; default: - DRM_DEBUG("Invalid parameter %d\n", sp.param); + DRM_DEBUG("Invalid parameter %d\n", sp->param); return -EINVAL; } @@ -3258,33 +3208,33 @@ void radeon_driver_postclose(struct drm_device * dev, struct drm_file *file_priv } struct drm_ioctl_desc radeon_ioctls[] = { - [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = {radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = {radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = {radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = {radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = {radeon_cp_idle, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = {radeon_cp_resume, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_RESET)] = {radeon_engine_reset, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = {radeon_fullscreen, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = {radeon_cp_swap, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = {radeon_cp_clear, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = {radeon_cp_vertex, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = {radeon_cp_indices, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = {radeon_cp_texture, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = {radeon_cp_stipple, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = {radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = {radeon_cp_vertex2, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = {radeon_cp_cmdbuf, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = {radeon_cp_getparam, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = {radeon_cp_flip, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = {radeon_mem_alloc, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_FREE)] = {radeon_mem_free, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = {radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = {radeon_irq_emit, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = {radeon_irq_wait, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = {radeon_cp_setparam, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = {radeon_surface_alloc, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_RADEON_SURF_FREE)] = {radeon_surface_free, DRM_AUTH} + DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH) }; int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); diff --git a/shared-core/savage_bci.c b/shared-core/savage_bci.c index c2dee6f9..32ac5ac2 100644 --- a/shared-core/savage_bci.c +++ b/shared-core/savage_bci.c @@ -927,19 +927,15 @@ static int savage_do_cleanup_bci(struct drm_device *dev) return 0; } -static int savage_bci_init(DRM_IOCTL_ARGS) +static int savage_bci_init(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; - drm_savage_init_t init; + drm_savage_init_t *init = data; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(init, (drm_savage_init_t __user *)data, - sizeof(init)); - - switch (init.func) { + switch (init->func) { case SAVAGE_INIT_BCI: - return savage_do_init_bci(dev, &init); + return savage_do_init_bci(dev, init); case SAVAGE_CLEANUP_BCI: return savage_do_cleanup_bci(dev); } @@ -947,39 +943,30 @@ static int savage_bci_init(DRM_IOCTL_ARGS) return -EINVAL; } -static int savage_bci_event_emit(DRM_IOCTL_ARGS) +static int savage_bci_event_emit(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_savage_private_t *dev_priv = dev->dev_private; - drm_savage_event_emit_t event; + drm_savage_event_emit_t *event = data; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_emit_t __user *)data, - sizeof(event)); + event->count = savage_bci_emit_event(dev_priv, event->flags); + event->count |= dev_priv->event_wrap << 16; - event.count = savage_bci_emit_event(dev_priv, event.flags); - event.count |= dev_priv->event_wrap << 16; - DRM_COPY_TO_USER_IOCTL((drm_savage_event_emit_t __user *)data, - event, sizeof(event)); return 0; } -static int savage_bci_event_wait(DRM_IOCTL_ARGS) +static int savage_bci_event_wait(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_savage_private_t *dev_priv = dev->dev_private; - drm_savage_event_wait_t event; + drm_savage_event_wait_t *event = data; unsigned int event_e, hw_e; unsigned int event_w, hw_w; DRM_DEBUG("\n"); - DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_wait_t __user *)data, - sizeof(event)); - UPDATE_EVENT_COUNTER(); if (dev_priv->status_ptr) hw_e = dev_priv->status_ptr[1] & 0xffff; @@ -989,8 +976,8 @@ static int savage_bci_event_wait(DRM_IOCTL_ARGS) if (hw_e > dev_priv->event_counter) hw_w--; /* hardware hasn't passed the last wrap yet */ - event_e = event.count & 0xffff; - event_w = event.count >> 16; + event_e = event->count & 0xffff; + event_w = event->count >> 16; /* Don't need to wait if * - event counter wrapped since the event was emitted or @@ -1032,41 +1019,36 @@ static int savage_bci_get_buffers(struct drm_device *dev, return 0; } -int savage_bci_buffers(DRM_IOCTL_ARGS) +int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; struct drm_device_dma *dma = dev->dma; - struct drm_dma d; + struct drm_dma *d = data; int ret = 0; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(d, (struct drm_dma __user *)data, sizeof(d)); - /* Please don't send us buffers. */ - if (d.send_count != 0) { + if (d->send_count != 0) { DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d.send_count); + DRM_CURRENTPID, d->send_count); return -EINVAL; } /* We'll send you buffers. */ - if (d.request_count < 0 || d.request_count > dma->buf_count) { + if (d->request_count < 0 || d->request_count > dma->buf_count) { DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d.request_count, dma->buf_count); + DRM_CURRENTPID, d->request_count, dma->buf_count); return -EINVAL; } - d.granted_count = 0; + d->granted_count = 0; - if (d.request_count) { - ret = savage_bci_get_buffers(dev, file_priv, &d); + if (d->request_count) { + ret = savage_bci_get_buffers(dev, file_priv, d); } - DRM_COPY_TO_USER_IOCTL((struct drm_dma __user *)data, d, sizeof(d)); - return ret; } @@ -1103,10 +1085,10 @@ void savage_reclaim_buffers(struct drm_device *dev, struct drm_file *file_priv) } struct drm_ioctl_desc savage_ioctls[] = { - [DRM_IOCTL_NR(DRM_SAVAGE_BCI_INIT)] = {savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_SAVAGE_BCI_CMDBUF)] = {savage_bci_cmdbuf, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_EMIT)] = {savage_bci_event_emit, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_WAIT)] = {savage_bci_event_wait, DRM_AUTH}, + DRM_IOCTL_DEF(DRM_SAVAGE_BCI_INIT, savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_SAVAGE_BCI_CMDBUF, savage_bci_cmdbuf, DRM_AUTH), + DRM_IOCTL_DEF(DRM_SAVAGE_BCI_EVENT_EMIT, savage_bci_event_emit, DRM_AUTH), + DRM_IOCTL_DEF(DRM_SAVAGE_BCI_EVENT_WAIT, savage_bci_event_wait, DRM_AUTH), }; int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls); diff --git a/shared-core/savage_drv.h b/shared-core/savage_drv.h index 3208cfcc..d86bac04 100644 --- a/shared-core/savage_drv.h +++ b/shared-core/savage_drv.h @@ -197,8 +197,8 @@ typedef struct drm_savage_private { } drm_savage_private_t; /* ioctls */ -extern int savage_bci_cmdbuf(DRM_IOCTL_ARGS); -extern int savage_bci_buffers(DRM_IOCTL_ARGS); +extern int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); /* BCI functions */ extern uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, diff --git a/shared-core/savage_state.c b/shared-core/savage_state.c index f5b9888c..dd593340 100644 --- a/shared-core/savage_state.c +++ b/shared-core/savage_state.c @@ -952,13 +952,12 @@ static int savage_dispatch_draw(drm_savage_private_t *dev_priv, return 0; } -int savage_bci_cmdbuf(DRM_IOCTL_ARGS) +int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_savage_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; struct drm_buf *dmabuf; - drm_savage_cmdbuf_t cmdbuf; + drm_savage_cmdbuf_t *cmdbuf = data; drm_savage_cmd_header_t *kcmd_addr = NULL; drm_savage_cmd_header_t *first_draw_cmd; unsigned int *kvb_addr = NULL; @@ -970,17 +969,14 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_savage_cmdbuf_t __user *)data, - sizeof(cmdbuf)); - if (dma && dma->buflist) { - if (cmdbuf.dma_idx > dma->buf_count) { + if (cmdbuf->dma_idx > dma->buf_count) { DRM_ERROR ("vertex buffer index %u out of range (0-%u)\n", - cmdbuf.dma_idx, dma->buf_count-1); + cmdbuf->dma_idx, dma->buf_count-1); return -EINVAL; } - dmabuf = dma->buflist[cmdbuf.dma_idx]; + dmabuf = dma->buflist[cmdbuf->dma_idx]; } else { dmabuf = NULL; } @@ -990,47 +986,49 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) * COPY_FROM_USER_UNCHECKED when done in other drivers, and is correct * for locking on FreeBSD. */ - if (cmdbuf.size) { - kcmd_addr = drm_alloc(cmdbuf.size * 8, DRM_MEM_DRIVER); + if (cmdbuf->size) { + kcmd_addr = drm_alloc(cmdbuf->size * 8, DRM_MEM_DRIVER); if (kcmd_addr == NULL) return -ENOMEM; - if (DRM_COPY_FROM_USER(kcmd_addr, cmdbuf.cmd_addr, - cmdbuf.size * 8)) + if (DRM_COPY_FROM_USER(kcmd_addr, cmdbuf->cmd_addr, + cmdbuf->size * 8)) { - drm_free(kcmd_addr, cmdbuf.size * 8, DRM_MEM_DRIVER); + drm_free(kcmd_addr, cmdbuf->size * 8, DRM_MEM_DRIVER); return -EFAULT; } - cmdbuf.cmd_addr = kcmd_addr; + cmdbuf->cmd_addr = kcmd_addr; } - if (cmdbuf.vb_size) { - kvb_addr = drm_alloc(cmdbuf.vb_size, DRM_MEM_DRIVER); + if (cmdbuf->vb_size) { + kvb_addr = drm_alloc(cmdbuf->vb_size, DRM_MEM_DRIVER); if (kvb_addr == NULL) { ret = -ENOMEM; goto done; } - if (DRM_COPY_FROM_USER(kvb_addr, cmdbuf.vb_addr, - cmdbuf.vb_size)) { + if (DRM_COPY_FROM_USER(kvb_addr, cmdbuf->vb_addr, + cmdbuf->vb_size)) { ret = -EFAULT; goto done; } - cmdbuf.vb_addr = kvb_addr; + cmdbuf->vb_addr = kvb_addr; } - if (cmdbuf.nbox) { - kbox_addr = drm_alloc(cmdbuf.nbox * sizeof(struct drm_clip_rect), - DRM_MEM_DRIVER); + if (cmdbuf->nbox) { + kbox_addr = drm_alloc(cmdbuf->nbox * + sizeof(struct drm_clip_rect), + DRM_MEM_DRIVER); if (kbox_addr == NULL) { ret = -ENOMEM; goto done; } - if (DRM_COPY_FROM_USER(kbox_addr, cmdbuf.box_addr, - cmdbuf.nbox * sizeof(struct drm_clip_rect))) { + if (DRM_COPY_FROM_USER(kbox_addr, cmdbuf->box_addr, + cmdbuf->nbox * + sizeof(struct drm_clip_rect))) { ret = -EFAULT; goto done; } - cmdbuf.box_addr = kbox_addr; + cmdbuf->box_addr = kbox_addr; } /* Make sure writes to DMA buffers are finished before sending @@ -1043,10 +1041,10 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) i = 0; first_draw_cmd = NULL; - while (i < cmdbuf.size) { + while (i < cmdbuf->size) { drm_savage_cmd_header_t cmd_header; - cmd_header = *(drm_savage_cmd_header_t *)cmdbuf.cmd_addr; - cmdbuf.cmd_addr++; + cmd_header = *(drm_savage_cmd_header_t *)cmdbuf->cmd_addr; + cmdbuf->cmd_addr++; i++; /* Group drawing commands with same state to minimize @@ -1056,7 +1054,7 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) case SAVAGE_CMD_DMA_IDX: case SAVAGE_CMD_VB_IDX: j = (cmd_header.idx.count + 3) / 4; - if (i + j > cmdbuf.size) { + if (i + j > cmdbuf->size) { DRM_ERROR("indexed drawing command extends " "beyond end of command buffer\n"); DMA_FLUSH(); @@ -1066,18 +1064,19 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) case SAVAGE_CMD_DMA_PRIM: case SAVAGE_CMD_VB_PRIM: if (!first_draw_cmd) - first_draw_cmd = cmdbuf.cmd_addr-1; - cmdbuf.cmd_addr += j; + first_draw_cmd = cmdbuf->cmd_addr-1; + cmdbuf->cmd_addr += j; i += j; break; default: if (first_draw_cmd) { ret = savage_dispatch_draw ( dev_priv, first_draw_cmd, - cmdbuf.cmd_addr-1, - dmabuf, cmdbuf.vb_addr, cmdbuf.vb_size, - cmdbuf.vb_stride, - cmdbuf.nbox, cmdbuf.box_addr); + cmdbuf->cmd_addr-1, + dmabuf, cmdbuf->vb_addr, + cmdbuf->vb_size, + cmdbuf->vb_stride, + cmdbuf->nbox, cmdbuf->box_addr); if (ret != 0) return ret; first_draw_cmd = NULL; @@ -1089,7 +1088,7 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) switch (cmd_header.cmd.cmd) { case SAVAGE_CMD_STATE: j = (cmd_header.state.count + 1) / 2; - if (i + j > cmdbuf.size) { + if (i + j > cmdbuf->size) { DRM_ERROR("command SAVAGE_CMD_STATE extends " "beyond end of command buffer\n"); DMA_FLUSH(); @@ -1097,12 +1096,12 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) goto done; } ret = savage_dispatch_state(dev_priv, &cmd_header, - (const uint32_t *)cmdbuf.cmd_addr); - cmdbuf.cmd_addr += j; + (const uint32_t *)cmdbuf->cmd_addr); + cmdbuf->cmd_addr += j; i += j; break; case SAVAGE_CMD_CLEAR: - if (i + 1 > cmdbuf.size) { + if (i + 1 > cmdbuf->size) { DRM_ERROR("command SAVAGE_CMD_CLEAR extends " "beyond end of command buffer\n"); DMA_FLUSH(); @@ -1110,17 +1109,19 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) goto done; } ret = savage_dispatch_clear(dev_priv, &cmd_header, - cmdbuf.cmd_addr, - cmdbuf.nbox, cmdbuf.box_addr); - cmdbuf.cmd_addr++; + cmdbuf->cmd_addr, + cmdbuf->nbox, + cmdbuf->box_addr); + cmdbuf->cmd_addr++; i++; break; case SAVAGE_CMD_SWAP: - ret = savage_dispatch_swap(dev_priv, cmdbuf.nbox, - cmdbuf.box_addr); + ret = savage_dispatch_swap(dev_priv, cmdbuf->nbox, + cmdbuf->box_addr); break; default: - DRM_ERROR("invalid command 0x%x\n", cmd_header.cmd.cmd); + DRM_ERROR("invalid command 0x%x\n", + cmd_header.cmd.cmd); DMA_FLUSH(); ret = -EINVAL; goto done; @@ -1134,9 +1135,9 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) if (first_draw_cmd) { ret = savage_dispatch_draw ( - dev_priv, first_draw_cmd, cmdbuf.cmd_addr, dmabuf, - cmdbuf.vb_addr, cmdbuf.vb_size, cmdbuf.vb_stride, - cmdbuf.nbox, cmdbuf.box_addr); + dev_priv, first_draw_cmd, cmdbuf->cmd_addr, dmabuf, + cmdbuf->vb_addr, cmdbuf->vb_size, cmdbuf->vb_stride, + cmdbuf->nbox, cmdbuf->box_addr); if (ret != 0) { DMA_FLUSH(); goto done; @@ -1145,7 +1146,7 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) DMA_FLUSH(); - if (dmabuf && cmdbuf.discard) { + if (dmabuf && cmdbuf->discard) { drm_savage_buf_priv_t *buf_priv = dmabuf->dev_private; uint16_t event; event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D); @@ -1155,9 +1156,9 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) done: /* If we didn't need to allocate them, these'll be NULL */ - drm_free(kcmd_addr, cmdbuf.size * 8, DRM_MEM_DRIVER); - drm_free(kvb_addr, cmdbuf.vb_size, DRM_MEM_DRIVER); - drm_free(kbox_addr, cmdbuf.nbox * sizeof(struct drm_clip_rect), + drm_free(kcmd_addr, cmdbuf->size * 8, DRM_MEM_DRIVER); + drm_free(kvb_addr, cmdbuf->vb_size, DRM_MEM_DRIVER); + drm_free(kbox_addr, cmdbuf->nbox * sizeof(struct drm_clip_rect), DRM_MEM_DRIVER); return ret; diff --git a/shared-core/sis_mm.c b/shared-core/sis_mm.c index b62e3e27..e11939fa 100644 --- a/shared-core/sis_mm.c +++ b/shared-core/sis_mm.c @@ -81,59 +81,52 @@ static int del_alloc_set(int context, int type, unsigned int val) /* fb management via fb device */ #if defined(__linux__) && defined(CONFIG_FB_SIS) -static int sis_fb_init(DRM_IOCTL_ARGS) +static int sis_fb_init(struct drm_device *dev, void *data, struct drm_file *file_priv) { return 0; } -static int sis_fb_alloc(DRM_IOCTL_ARGS) +static int sis_fb_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) { - drm_sis_mem_t fb; + drm_sis_mem_t *fb = data; struct sis_memreq req; - drm_sis_mem_t __user *argp = (drm_sis_mem_t __user *)data; int retval = 0; - DRM_COPY_FROM_USER_IOCTL(fb, argp, sizeof(fb)); - - req.size = fb.size; + req.size = fb->size; sis_malloc(&req); if (req.offset) { /* TODO */ - fb.offset = req.offset; - fb.free = req.offset; - if (!add_alloc_set(fb.context, VIDEO_TYPE, fb.free)) { + fb->offset = req.offset; + fb->free = req.offset; + if (!add_alloc_set(fb->context, VIDEO_TYPE, fb->free)) { DRM_DEBUG("adding to allocation set fails\n"); sis_free(req.offset); retval = -EINVAL; } } else { - fb.offset = 0; - fb.size = 0; - fb.free = 0; + fb->offset = 0; + fb->size = 0; + fb->free = 0; } - DRM_COPY_TO_USER_IOCTL(argp, fb, sizeof(fb)); - - DRM_DEBUG("alloc fb, size = %d, offset = %ld\n", fb.size, req.offset); + DRM_DEBUG("alloc fb, size = %d, offset = %ld\n", fb->size, req.offset); return retval; } -static int sis_fb_free(DRM_IOCTL_ARGS) +static int sis_fb_free(struct drm_device *dev, void *data, struct drm_file *file_priv) { drm_sis_mem_t fb; int retval = 0; - DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_mem_t __user *) data, sizeof(fb)); - - if (!fb.free) + if (!fb->free) return -EINVAL; - if (!del_alloc_set(fb.context, VIDEO_TYPE, fb.free)) + if (!del_alloc_set(fb->context, VIDEO_TYPE, fb->free)) retval = -EINVAL; - sis_free(fb.free); + sis_free(fb->free); - DRM_DEBUG("free fb, offset = 0x%lx\n", fb.free); + DRM_DEBUG("free fb, offset = 0x%lx\n", fb->free); return retval; } @@ -150,13 +143,10 @@ static int sis_fb_free(DRM_IOCTL_ARGS) * X driver/sisfb HW- Command- * framebuffer memory DRI heap Cursor queue */ -static int sis_fb_init(DRM_IOCTL_ARGS) +static int sis_fb_init(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_sis_private_t *dev_priv = dev->dev_private; - drm_sis_fb_t fb; - - DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_fb_t __user *) data, sizeof(fb)); + drm_sis_fb_t *fb = data; if (dev_priv == NULL) { dev->dev_private = drm_calloc(1, sizeof(drm_sis_private_t), @@ -169,69 +159,60 @@ static int sis_fb_init(DRM_IOCTL_ARGS) if (dev_priv->FBHeap != NULL) return -EINVAL; - dev_priv->FBHeap = mmInit(fb.offset, fb.size); + dev_priv->FBHeap = mmInit(fb->offset, fb->size); - DRM_DEBUG("offset = %u, size = %u", fb.offset, fb.size); + DRM_DEBUG("offset = %u, size = %u", fb->offset, fb->size); return 0; } -static int sis_fb_alloc(DRM_IOCTL_ARGS) +static int sis_fb_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_sis_private_t *dev_priv = dev->dev_private; - drm_sis_mem_t __user *argp = (drm_sis_mem_t __user *)data; - drm_sis_mem_t fb; + drm_sis_mem_t *fb = data; PMemBlock block; int retval = 0; if (dev_priv == NULL || dev_priv->FBHeap == NULL) return -EINVAL; - DRM_COPY_FROM_USER_IOCTL(fb, argp, sizeof(fb)); - - block = mmAllocMem(dev_priv->FBHeap, fb.size, 0, 0); + block = mmAllocMem(dev_priv->FBHeap, fb->size, 0, 0); if (block) { /* TODO */ - fb.offset = block->ofs; - fb.free = (unsigned long)block; - if (!add_alloc_set(fb.context, VIDEO_TYPE, fb.free)) { + fb->offset = block->ofs; + fb->free = (unsigned long)block; + if (!add_alloc_set(fb->context, VIDEO_TYPE, fb->free)) { DRM_DEBUG("adding to allocation set fails\n"); - mmFreeMem((PMemBlock) fb.free); + mmFreeMem((PMemBlock) fb->free); retval = -EINVAL; } } else { - fb.offset = 0; - fb.size = 0; - fb.free = 0; + fb->offset = 0; + fb->size = 0; + fb->free = 0; } - DRM_COPY_TO_USER_IOCTL(argp, fb, sizeof(fb)); - - DRM_DEBUG("alloc fb, size = %d, offset = %d\n", fb.size, fb.offset); + DRM_DEBUG("alloc fb, size = %d, offset = %d\n", fb->size, fb->offset); return retval; } -static int sis_fb_free(DRM_IOCTL_ARGS) +static int sis_fb_free(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_sis_private_t *dev_priv = dev->dev_private; - drm_sis_mem_t fb; + drm_sis_mem_t *fb = data; if (dev_priv == NULL || dev_priv->FBHeap == NULL) return -EINVAL; - DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_mem_t __user *) data, sizeof(fb)); - - if (!mmBlockInHeap(dev_priv->FBHeap, (PMemBlock) fb.free)) + if (!mmBlockInHeap(dev_priv->FBHeap, (PMemBlock) fb->free)) return -EINVAL; - if (!del_alloc_set(fb.context, VIDEO_TYPE, fb.free)) + if (!del_alloc_set(fb->context, VIDEO_TYPE, fb->free)) return -EINVAL; - mmFreeMem((PMemBlock) fb.free); + mmFreeMem((PMemBlock) fb->free); - DRM_DEBUG("free fb, free = 0x%lx\n", fb.free); + DRM_DEBUG("free fb, free = 0x%lx\n", fb->free); return 0; } @@ -240,11 +221,10 @@ static int sis_fb_free(DRM_IOCTL_ARGS) /* agp memory management */ -static int sis_ioctl_agp_init(DRM_IOCTL_ARGS) +static int sis_ioctl_agp_init(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_sis_private_t *dev_priv = dev->dev_private; - drm_sis_agp_t agp; + drm_sis_agp_t *agp = data; if (dev_priv == NULL) { dev->dev_private = drm_calloc(1, sizeof(drm_sis_private_t), @@ -257,73 +237,61 @@ static int sis_ioctl_agp_init(DRM_IOCTL_ARGS) if (dev_priv->AGPHeap != NULL) return -EINVAL; - DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_agp_t __user *) data, - sizeof(agp)); - - dev_priv->AGPHeap = mmInit(agp.offset, agp.size); + dev_priv->AGPHeap = mmInit(agp->offset, agp->size); - DRM_DEBUG("offset = %u, size = %u", agp.offset, agp.size); + DRM_DEBUG("offset = %u, size = %u", agp->offset, agp->size); return 0; } -static int sis_ioctl_agp_alloc(DRM_IOCTL_ARGS) +static int sis_ioctl_agp_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_sis_private_t *dev_priv = dev->dev_private; - drm_sis_mem_t __user *argp = (drm_sis_mem_t __user *)data; - drm_sis_mem_t agp; + drm_sis_mem_t *agp = data; PMemBlock block; int retval = 0; if (dev_priv == NULL || dev_priv->AGPHeap == NULL) return -EINVAL; - DRM_COPY_FROM_USER_IOCTL(agp, argp, sizeof(agp)); - - block = mmAllocMem(dev_priv->AGPHeap, agp.size, 0, 0); + block = mmAllocMem(dev_priv->AGPHeap, agp->size, 0, 0); if (block) { /* TODO */ - agp.offset = block->ofs; - agp.free = (unsigned long)block; - if (!add_alloc_set(agp.context, AGP_TYPE, agp.free)) { + agp->offset = block->ofs; + agp->free = (unsigned long)block; + if (!add_alloc_set(agp->context, AGP_TYPE, agp->free)) { DRM_DEBUG("adding to allocation set fails\n"); - mmFreeMem((PMemBlock) agp.free); + mmFreeMem((PMemBlock) agp->free); retval = -1; } } else { - agp.offset = 0; - agp.size = 0; - agp.free = 0; + agp->offset = 0; + agp->size = 0; + agp->free = 0; } - DRM_COPY_TO_USER_IOCTL(argp, agp, sizeof(agp)); - - DRM_DEBUG("alloc agp, size = %d, offset = %d\n", agp.size, agp.offset); + DRM_DEBUG("alloc agp, size = %d, offset = %d\n", agp->size, + agp->offset); return retval; } -static int sis_ioctl_agp_free(DRM_IOCTL_ARGS) +static int sis_ioctl_agp_free(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_sis_private_t *dev_priv = dev->dev_private; - drm_sis_mem_t agp; + drm_sis_mem_t *agp = data; if (dev_priv == NULL || dev_priv->AGPHeap == NULL) return -EINVAL; - DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_mem_t __user *) data, - sizeof(agp)); - - if (!mmBlockInHeap(dev_priv->AGPHeap, (PMemBlock) agp.free)) + if (!mmBlockInHeap(dev_priv->AGPHeap, (PMemBlock) agp->free)) return -EINVAL; - mmFreeMem((PMemBlock) agp.free); - if (!del_alloc_set(agp.context, AGP_TYPE, agp.free)) + mmFreeMem((PMemBlock) agp->free); + if (!del_alloc_set(agp->context, AGP_TYPE, agp->free)) return -EINVAL; - DRM_DEBUG("free agp, free = 0x%lx\n", agp.free); + DRM_DEBUG("free agp, free = 0x%lx\n", agp->free); return 0; } @@ -407,12 +375,12 @@ int sis_final_context(struct drm_device *dev, int context) } drm_ioctl_desc_t sis_ioctls[] = { - [DRM_IOCTL_NR(DRM_SIS_FB_ALLOC)] = {sis_fb_alloc, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_SIS_FB_FREE)] = {sis_fb_free, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_SIS_AGP_INIT)] = {sis_ioctl_agp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, - [DRM_IOCTL_NR(DRM_SIS_AGP_ALLOC)] = {sis_ioctl_agp_alloc, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_SIS_AGP_FREE)] = {sis_ioctl_agp_free, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_SIS_FB_INIT)] = {sis_fb_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY} + DRM_IOCTL_DEF(DRM_SIS_FB_ALLOC, sis_fb_alloc, DRM_AUTH), + DRM_IOCTL_DEF(DRM_SIS_FB_FREE, sis_fb_free, DRM_AUTH), + DRM_IOCTL_DEF(DRM_SIS_AGP_INIT, sis_ioctl_agp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_SIS_AGP_ALLOC, sis_ioctl_agp_alloc, DRM_AUTH), + DRM_IOCTL_DEF(DRM_SIS_AGP_FREE, sis_ioctl_agp_free, DRM_AUTH), + DRM_IOCTL_DEF(DRM_SIS_FB_INIT, sis_fb_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY) }; int sis_max_ioctl = DRM_ARRAY_SIZE(sis_ioctls); diff --git a/shared-core/via_dma.c b/shared-core/via_dma.c index 7fe6d019..bd737a7e 100644 --- a/shared-core/via_dma.c +++ b/shared-core/via_dma.c @@ -215,22 +215,18 @@ static int via_initialize(struct drm_device * dev, return 0; } -static int via_dma_init(DRM_IOCTL_ARGS) +static int via_dma_init(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; - drm_via_dma_init_t init; + drm_via_dma_init_t *init = data; int retcode = 0; - DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t __user *) data, - sizeof(init)); - - switch (init.func) { + switch (init->func) { case VIA_INIT_DMA: if (!DRM_SUSER(DRM_CURPROC)) retcode = -EPERM; else - retcode = via_initialize(dev, dev_priv, &init); + retcode = via_initialize(dev, dev_priv, init); break; case VIA_CLEANUP_DMA: if (!DRM_SUSER(DRM_CURPROC)) @@ -316,29 +312,25 @@ int via_driver_dma_quiescent(struct drm_device * dev) return 0; } -static int via_flush_ioctl(DRM_IOCTL_ARGS) +static int via_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; LOCK_TEST_WITH_RETURN(dev, file_priv); return via_driver_dma_quiescent(dev); } -static int via_cmdbuffer(DRM_IOCTL_ARGS) +static int via_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; - drm_via_cmdbuffer_t cmdbuf; + drm_via_cmdbuffer_t *cmdbuf = data; int ret; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data, - sizeof(cmdbuf)); - - DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf.buf, cmdbuf.size); + DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf->buf, + cmdbuf->size); - ret = via_dispatch_cmdbuffer(dev, &cmdbuf); + ret = via_dispatch_cmdbuffer(dev, cmdbuf); if (ret) { return ret; } @@ -370,21 +362,17 @@ static int via_dispatch_pci_cmdbuffer(struct drm_device * dev, return ret; } -static int via_pci_cmdbuffer(DRM_IOCTL_ARGS) +static int via_pci_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; - drm_via_cmdbuffer_t cmdbuf; + drm_via_cmdbuffer_t *cmdbuf = data; int ret; LOCK_TEST_WITH_RETURN(dev, file_priv); - DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data, - sizeof(cmdbuf)); - - DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf.buf, - cmdbuf.size); + DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf->buf, + cmdbuf->size); - ret = via_dispatch_pci_cmdbuffer(dev, &cmdbuf); + ret = via_dispatch_pci_cmdbuffer(dev, cmdbuf); if (ret) { return ret; } @@ -645,10 +633,9 @@ static void via_cmdbuf_reset(drm_via_private_t * dev_priv) * User interface to the space and lag functions. */ -static int via_cmdbuf_size(DRM_IOCTL_ARGS) +static int via_cmdbuf_size(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; - drm_via_cmdbuf_size_t d_siz; + drm_via_cmdbuf_size_t *d_siz = data; int ret = 0; uint32_t tmp_size, count; drm_via_private_t *dev_priv; @@ -664,17 +651,13 @@ static int via_cmdbuf_size(DRM_IOCTL_ARGS) return -EFAULT; } - DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t __user *) data, - sizeof(d_siz)); - - count = 1000000; - tmp_size = d_siz.size; - switch(d_siz.func) { + tmp_size = d_siz->size; + switch(d_siz->func) { case VIA_CMDBUF_SPACE: - while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz.size) + while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz->size) && count--) { - if (!d_siz.wait) { + if (!d_siz->wait) { break; } } @@ -684,9 +667,9 @@ static int via_cmdbuf_size(DRM_IOCTL_ARGS) } break; case VIA_CMDBUF_LAG: - while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz.size) + while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz->size) && count--) { - if (!d_siz.wait) { + if (!d_siz->wait) { break; } } @@ -698,41 +681,39 @@ static int via_cmdbuf_size(DRM_IOCTL_ARGS) default: ret = -EFAULT; } - d_siz.size = tmp_size; + d_siz->size = tmp_size; - DRM_COPY_TO_USER_IOCTL((drm_via_cmdbuf_size_t __user *) data, d_siz, - sizeof(d_siz)); return ret; } #ifndef VIA_HAVE_DMABLIT int -via_dma_blit_sync( DRM_IOCTL_ARGS ) { +via_dma_blit_sync( struct drm_device *dev, void *data, struct drm_file *file_priv ) { DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n"); return -EINVAL; } int -via_dma_blit( DRM_IOCTL_ARGS ) { +via_dma_blit( struct drm_device *dev, void *data, struct drm_file *file_priv ) { DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n"); return -EINVAL; } #endif struct drm_ioctl_desc via_ioctls[] = { - [DRM_IOCTL_NR(DRM_VIA_ALLOCMEM)] = {via_mem_alloc, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_VIA_FREEMEM)] = {via_mem_free, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_VIA_AGP_INIT)] = {via_agp_init, DRM_AUTH|DRM_MASTER}, - [DRM_IOCTL_NR(DRM_VIA_FB_INIT)] = {via_fb_init, DRM_AUTH|DRM_MASTER}, - [DRM_IOCTL_NR(DRM_VIA_MAP_INIT)] = {via_map_init, DRM_AUTH|DRM_MASTER}, - [DRM_IOCTL_NR(DRM_VIA_DEC_FUTEX)] = {via_decoder_futex, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_VIA_DMA_INIT)] = {via_dma_init, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_VIA_CMDBUFFER)] = {via_cmdbuffer, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_VIA_FLUSH)] = {via_flush_ioctl, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_VIA_PCICMD)] = {via_pci_cmdbuffer, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_VIA_CMDBUF_SIZE)] = {via_cmdbuf_size, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_VIA_WAIT_IRQ)] = {via_wait_irq, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_VIA_DMA_BLIT)] = {via_dma_blit, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_VIA_BLIT_SYNC)] = {via_dma_blit_sync, DRM_AUTH} + DRM_IOCTL_DEF(DRM_VIA_ALLOCMEM, via_mem_alloc, DRM_AUTH), + DRM_IOCTL_DEF(DRM_VIA_FREEMEM, via_mem_free, DRM_AUTH), + DRM_IOCTL_DEF(DRM_VIA_AGP_INIT, via_agp_init, DRM_AUTH|DRM_MASTER), + DRM_IOCTL_DEF(DRM_VIA_FB_INIT, via_fb_init, DRM_AUTH|DRM_MASTER), + DRM_IOCTL_DEF(DRM_VIA_MAP_INIT, via_map_init, DRM_AUTH|DRM_MASTER), + DRM_IOCTL_DEF(DRM_VIA_DEC_FUTEX, via_decoder_futex, DRM_AUTH), + DRM_IOCTL_DEF(DRM_VIA_DMA_INIT, via_dma_init, DRM_AUTH), + DRM_IOCTL_DEF(DRM_VIA_CMDBUFFER, via_cmdbuffer, DRM_AUTH), + DRM_IOCTL_DEF(DRM_VIA_FLUSH, via_flush_ioctl, DRM_AUTH), + DRM_IOCTL_DEF(DRM_VIA_PCICMD, via_pci_cmdbuffer, DRM_AUTH), + DRM_IOCTL_DEF(DRM_VIA_CMDBUF_SIZE, via_cmdbuf_size, DRM_AUTH), + DRM_IOCTL_DEF(DRM_VIA_WAIT_IRQ, via_wait_irq, DRM_AUTH), + DRM_IOCTL_DEF(DRM_VIA_DMA_BLIT, via_dma_blit, DRM_AUTH), + DRM_IOCTL_DEF(DRM_VIA_BLIT_SYNC, via_dma_blit_sync, DRM_AUTH) }; int via_max_ioctl = DRM_ARRAY_SIZE(via_ioctls); diff --git a/shared-core/via_drv.h b/shared-core/via_drv.h index b7997942..15e65950 100644 --- a/shared-core/via_drv.h +++ b/shared-core/via_drv.h @@ -151,15 +151,15 @@ enum via_family { extern struct drm_ioctl_desc via_ioctls[]; extern int via_max_ioctl; -extern int via_fb_init(DRM_IOCTL_ARGS); -extern int via_mem_alloc(DRM_IOCTL_ARGS); -extern int via_mem_free(DRM_IOCTL_ARGS); -extern int via_agp_init(DRM_IOCTL_ARGS); -extern int via_map_init(DRM_IOCTL_ARGS); -extern int via_decoder_futex(DRM_IOCTL_ARGS); -extern int via_wait_irq(DRM_IOCTL_ARGS); -extern int via_dma_blit_sync( DRM_IOCTL_ARGS ); -extern int via_dma_blit( DRM_IOCTL_ARGS ); +extern int via_fb_init(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int via_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int via_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int via_agp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int via_map_init(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int via_decoder_futex(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int via_dma_blit_sync( struct drm_device *dev, void *data, struct drm_file *file_priv ); +extern int via_dma_blit( struct drm_device *dev, void *data, struct drm_file *file_priv ); extern int via_driver_load(struct drm_device *dev, unsigned long chipset); extern int via_driver_unload(struct drm_device *dev); diff --git a/shared-core/via_irq.c b/shared-core/via_irq.c index 68ee5226..475b6461 100644 --- a/shared-core/via_irq.c +++ b/shared-core/via_irq.c @@ -340,11 +340,9 @@ void via_driver_irq_uninstall(struct drm_device * dev) } } -int via_wait_irq(DRM_IOCTL_ARGS) +int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; - drm_via_irqwait_t __user *argp = (void __user *)data; - drm_via_irqwait_t irqwait; + drm_via_irqwait_t *irqwait = data; struct timeval now; int ret = 0; drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; @@ -354,44 +352,42 @@ int via_wait_irq(DRM_IOCTL_ARGS) if (!dev->irq) return -EINVAL; - DRM_COPY_FROM_USER_IOCTL(irqwait, argp, sizeof(irqwait)); - if (irqwait.request.irq >= dev_priv->num_irqs) { + if (irqwait->request.irq >= dev_priv->num_irqs) { DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__, - irqwait.request.irq); + irqwait->request.irq); return -EINVAL; } - cur_irq += irqwait.request.irq; + cur_irq += irqwait->request.irq; - switch (irqwait.request.type & ~VIA_IRQ_FLAGS_MASK) { + switch (irqwait->request.type & ~VIA_IRQ_FLAGS_MASK) { case VIA_IRQ_RELATIVE: - irqwait.request.sequence += atomic_read(&cur_irq->irq_received); - irqwait.request.type &= ~_DRM_VBLANK_RELATIVE; + irqwait->request.sequence += + atomic_read(&cur_irq->irq_received); + irqwait->request.type &= ~_DRM_VBLANK_RELATIVE; case VIA_IRQ_ABSOLUTE: break; default: return -EINVAL; } - if (irqwait.request.type & VIA_IRQ_SIGNAL) { + if (irqwait->request.type & VIA_IRQ_SIGNAL) { DRM_ERROR("%s Signals on Via IRQs not implemented yet.\n", __FUNCTION__); return -EINVAL; } - force_sequence = (irqwait.request.type & VIA_IRQ_FORCE_SEQUENCE); + force_sequence = (irqwait->request.type & VIA_IRQ_FORCE_SEQUENCE); - ret = via_driver_irq_wait(dev, irqwait.request.irq, force_sequence, - &irqwait.request.sequence); + ret = via_driver_irq_wait(dev, irqwait->request.irq, force_sequence, + &irqwait->request.sequence); #ifdef __linux__ do_gettimeofday(&now); #else microtime(&now); #endif - irqwait.reply.tval_sec = now.tv_sec; - irqwait.reply.tval_usec = now.tv_usec; - - DRM_COPY_TO_USER_IOCTL(argp, irqwait, sizeof(irqwait)); + irqwait->reply.tval_sec = now.tv_sec; + irqwait->reply.tval_usec = now.tv_usec; return ret; } diff --git a/shared-core/via_map.c b/shared-core/via_map.c index 1aed10f5..1623df68 100644 --- a/shared-core/via_map.c +++ b/shared-core/via_map.c @@ -91,19 +91,15 @@ int via_do_cleanup_map(struct drm_device * dev) } -int via_map_init(DRM_IOCTL_ARGS) +int via_map_init(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; - drm_via_init_t init; + drm_via_init_t *init = data; DRM_DEBUG("%s\n", __FUNCTION__); - DRM_COPY_FROM_USER_IOCTL(init, (drm_via_init_t __user *) data, - sizeof(init)); - - switch (init.func) { + switch (init->func) { case VIA_INIT_MAP: - return via_do_init_map(dev, &init); + return via_do_init_map(dev, init); case VIA_CLEANUP_MAP: return via_do_cleanup_map(dev); } diff --git a/shared-core/via_mm.c b/shared-core/via_mm.c index 8f175a7d..45790dc2 100644 --- a/shared-core/via_mm.c +++ b/shared-core/via_mm.c @@ -72,17 +72,14 @@ static int del_alloc_set(int context, int type, unsigned long val) /* agp memory management */ static memHeap_t *AgpHeap = NULL; -int via_agp_init(DRM_IOCTL_ARGS) +int via_agp_init(struct drm_device *dev, void *data, struct drm_file *file_priv) { - drm_via_agp_t agp; + drm_via_agp_t *agp = data; - DRM_COPY_FROM_USER_IOCTL(agp, (drm_via_agp_t __user *) data, - sizeof(agp)); + AgpHeap = via_mmInit(agp->offset, agp->size); - AgpHeap = via_mmInit(agp.offset, agp.size); - - DRM_DEBUG("offset = %lu, size = %lu", (unsigned long)agp.offset, - (unsigned long)agp.size); + DRM_DEBUG("offset = %lu, size = %lu", (unsigned long)agp->offset, + (unsigned long)agp->size); return 0; } @@ -90,11 +87,9 @@ int via_agp_init(DRM_IOCTL_ARGS) /* fb memory management */ static memHeap_t *FBHeap = NULL; -int via_fb_init(DRM_IOCTL_ARGS) +int via_fb_init(struct drm_device *dev, void *data, struct drm_file *file_priv) { - drm_via_fb_t fb; - - DRM_COPY_FROM_USER_IOCTL(fb, (drm_via_fb_t __user *) data, sizeof(fb)); + drm_via_fb_t *fb = data; FBHeap = via_mmInit(fb.offset, fb.size); @@ -191,25 +186,18 @@ int via_final_context(struct drm_device *dev, int context) return 1; } -int via_mem_alloc(DRM_IOCTL_ARGS) +int via_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) { - drm_via_mem_t mem; - - DRM_COPY_FROM_USER_IOCTL(mem, (drm_via_mem_t __user *) data, - sizeof(mem)); + drm_via_mem_t *mem = data; switch (mem.type) { case VIA_MEM_VIDEO: - if (via_fb_alloc(&mem) < 0) + if (via_fb_alloc(mem) < 0) return -EFAULT; - DRM_COPY_TO_USER_IOCTL((drm_via_mem_t __user *) data, mem, - sizeof(mem)); return 0; case VIA_MEM_AGP: - if (via_agp_alloc(&mem) < 0) + if (via_agp_alloc(mem) < 0) return -EFAULT; - DRM_COPY_TO_USER_IOCTL((drm_via_mem_t __user *) data, mem, - sizeof(mem)); return 0; } @@ -288,21 +276,18 @@ static int via_agp_alloc(drm_via_mem_t * mem) return retval; } -int via_mem_free(DRM_IOCTL_ARGS) +int via_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv) { - drm_via_mem_t mem; + drm_via_mem_t *mem = data; - DRM_COPY_FROM_USER_IOCTL(mem, (drm_via_mem_t __user *) data, - sizeof(mem)); - - switch (mem.type) { + switch (mem->type) { case VIA_MEM_VIDEO: - if (via_fb_free(&mem) == 0) + if (via_fb_free(mem) == 0) return 0; break; case VIA_MEM_AGP: - if (via_agp_free(&mem) == 0) + if (via_agp_free(mem) == 0) return 0; break; } @@ -356,7 +341,7 @@ static int via_agp_free(drm_via_mem_t * mem) retval = -1; } - DRM_DEBUG("free agp, free = %ld\n", agp.free); + DRM_DEBUG("free agp, free = %ld\n", agp.nfree); return retval; } diff --git a/shared-core/via_video.c b/shared-core/via_video.c index 300ac61b..c15e75b5 100644 --- a/shared-core/via_video.c +++ b/shared-core/via_video.c @@ -65,10 +65,9 @@ void via_release_futex(drm_via_private_t * dev_priv, int context) } } -int via_decoder_futex(DRM_IOCTL_ARGS) +int via_decoder_futex(struct drm_device *dev, void *data, struct drm_file *file_priv) { - DRM_DEVICE; - drm_via_futex_t fx; + drm_via_futex_t *fx = data; volatile int *lock; drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; drm_via_sarea_t *sAPriv = dev_priv->sarea_priv; @@ -76,21 +75,18 @@ int via_decoder_futex(DRM_IOCTL_ARGS) DRM_DEBUG("%s\n", __FUNCTION__); - DRM_COPY_FROM_USER_IOCTL(fx, (drm_via_futex_t __user *) data, - sizeof(fx)); - - if (fx.lock > VIA_NR_XVMC_LOCKS) + if (fx->lock > VIA_NR_XVMC_LOCKS) return -EFAULT; - lock = (volatile int *)XVMCLOCKPTR(sAPriv, fx.lock); + lock = (volatile int *)XVMCLOCKPTR(sAPriv, fx->lock); - switch (fx.func) { + switch (fx->func) { case VIA_FUTEX_WAIT: - DRM_WAIT_ON(ret, dev_priv->decoder_queue[fx.lock], - (fx.ms / 10) * (DRM_HZ / 100), *lock != fx.val); + DRM_WAIT_ON(ret, dev_priv->decoder_queue[fx->lock], + (fx->ms / 10) * (DRM_HZ / 100), *lock != fx->val); return ret; case VIA_FUTEX_WAKE: - DRM_WAKEUP(&(dev_priv->decoder_queue[fx.lock])); + DRM_WAKEUP(&(dev_priv->decoder_queue[fx->lock])); return 0; } return 0; -- cgit v1.2.3 From 5d6fdd9d7924fde8ce62631e6bdce8d5fe33fc3d Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Sat, 21 Jul 2007 20:34:56 -0700 Subject: Clean up xgi_cmd_info and associated code. There were numerous unnecessary fields in xgi_cmd_info. The remaining fields had pretty crummy names. Cut out the cruft, and rename the rest. As a result, the unused parameter "triggerCounter" to triggerHWCommandList can be removed. --- shared-core/xgi_drm.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'shared-core') diff --git a/shared-core/xgi_drm.h b/shared-core/xgi_drm.h index 66cb4efb..6f50d4e1 100644 --- a/shared-core/xgi_drm.h +++ b/shared-core/xgi_drm.h @@ -85,13 +85,10 @@ enum xgi_batch_type { }; struct xgi_cmd_info { - unsigned int _firstBeginType; - __u32 _firstBeginAddr; - __u32 _firstSize; - __u32 _curDebugID; - __u32 _lastBeginAddr; - unsigned int _beginCount; - + __u32 type; + __u32 hw_addr; + __u32 size; + __u32 id; }; struct xgi_state_info { -- cgit v1.2.3 From 877296ade051cd45c0c2e0354b9f6765f8030413 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Sat, 21 Jul 2007 21:36:11 -0700 Subject: xgi_mem_alloc::offset is a hardware offset, so it should be u32, not long. --- shared-core/xgi_drm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/xgi_drm.h b/shared-core/xgi_drm.h index 6f50d4e1..da2ea8b9 100644 --- a/shared-core/xgi_drm.h +++ b/shared-core/xgi_drm.h @@ -73,7 +73,7 @@ struct xgi_mem_alloc { /** * Offset of the allocation in the mapping. */ - unsigned long offset; + __u32 offset; }; enum xgi_batch_type { -- cgit v1.2.3 From 887cb31ee9ec04e45829500f095aa4a3bc1095ea Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 24 Jul 2007 13:27:44 -0700 Subject: Fix bug preventing X server from restarting. The core DRM lastclose routine automatically destroys all mappings and releases SG memory. XP10 DRM and DDX assumed this data stayed around until module unload. xgi_bootstrap was reworked to recreate all these mappings. In addition, the drm_addmap for the GART backing store was moved into the kernel. This causes a change to the ioctl protocol and a version bump. --- shared-core/xgi_drm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/xgi_drm.h b/shared-core/xgi_drm.h index da2ea8b9..adce7066 100644 --- a/shared-core/xgi_drm.h +++ b/shared-core/xgi_drm.h @@ -49,7 +49,7 @@ struct xgi_bootstrap { /** * Size of PCI-e GART range in megabytes. */ - unsigned int gart_size; + struct drm_map gart; }; @@ -113,7 +113,7 @@ struct xgi_state_info { #define DRM_XGI_TEST_RWINKERNEL 9 #define DRM_XGI_STATE_CHANGE 10 -#define XGI_IOCTL_BOOTSTRAP DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_BOOTSTRAP, struct xgi_bootstrap) +#define XGI_IOCTL_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_XGI_BOOTSTRAP, struct xgi_bootstrap) #define XGI_IOCTL_FB_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_XGI_FB_ALLOC, struct xgi_mem_alloc) #define XGI_IOCTL_FB_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_FB_FREE, __u32) -- cgit v1.2.3 From cf2d569daca6954d11a796f4d110148ae2e0c827 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 26 Jul 2007 10:14:17 -0700 Subject: Replace NO_MOVE/NO_EVICT flags to buffer objects with an ioctl to set pinning. This cleans up the create/validate interfaces for this very uncommon path, and makes pinned object creation much easier to use for the X Server. --- shared-core/drm.h | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index db913b1f..57d1dbec 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -688,14 +688,6 @@ struct drm_fence_arg { * Can also be set in the buffer mask before validation. */ -/* - * Mask: Never evict this buffer. Not even with force. This type of buffer is only - * available to root and must be manually removed before buffer manager shutdown - * or lock. - * Flags: Acknowledge - */ -#define DRM_BO_FLAG_NO_EVICT (1ULL << 4) - /* * Mask: Require that the buffer is placed in mappable memory when validated. * If not set the buffer may or may not be in mappable memory when validated. @@ -813,6 +805,16 @@ struct drm_bo_op_req { struct drm_bo_info_req bo_req; }; +struct drm_bo_set_pin_req { + /** Buffer object ID */ + unsigned int handle; + /** + * - 0: Unpin the given buffer object. + * - 1: Pin the given buffer object. + */ + unsigned int pin; +}; + /* * Reply flags */ @@ -878,6 +880,13 @@ struct drm_bo_op_arg { unsigned int pad64; }; +struct drm_bo_set_pin_arg { + union { + struct drm_bo_set_pin_req req; + struct drm_bo_info_rep rep; + } d; +}; + #define DRM_BO_MEM_LOCAL 0 #define DRM_BO_MEM_TT 1 #define DRM_BO_MEM_VRAM 2 @@ -993,7 +1002,7 @@ struct drm_mm_init_arg { #define DRM_IOCTL_BO_OP DRM_IOWR(0xd3, struct drm_bo_op_arg) #define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg) #define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg) - +#define DRM_IOCTL_BO_SET_PIN DRM_IOWR(0xd6, struct drm_bo_set_pin_arg) /*@}*/ -- cgit v1.2.3 From f01026eae69e81ae16a69a014ba3bcfb286fc7a4 Mon Sep 17 00:00:00 2001 From: Arthur Huillet Date: Fri, 27 Jul 2007 15:48:04 +0200 Subject: nouveau: creating notifier in PCI memory for PCIGART --- shared-core/nouveau_notifier.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index 24a306e8..7a982ba4 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -41,10 +41,13 @@ nouveau_notifier_init_channel(struct drm_device *dev, int channel, if (dev_priv->agp_heap && dev_priv->gart_info.type != NOUVEAU_GART_SGDMA) flags = NOUVEAU_MEM_AGP | NOUVEAU_MEM_FB_ACCEPTABLE; + else if ( dev_priv->pci_heap ) + flags = NOUVEAU_MEM_PCI; else flags = NOUVEAU_MEM_FB; flags |= NOUVEAU_MEM_MAPPED; +DRM_DEBUG("Allocating notifier block in %d\n", flags); chan->notifier_block = nouveau_mem_alloc(dev, 0, PAGE_SIZE, flags, file_priv); if (!chan->notifier_block) @@ -102,6 +105,8 @@ nouveau_notifier_alloc(struct drm_device *dev, int channel, uint32_t handle, target = NV_DMA_TARGET_VIDMEM; } else if (chan->notifier_block->flags & NOUVEAU_MEM_AGP) { target = NV_DMA_TARGET_AGP; + } else if (chan->notifier_block->flags & NOUVEAU_MEM_PCI) { + target = NV_DMA_TARGET_PCI_NONLINEAR; } else { DRM_ERROR("Bad DMA target, flags 0x%08x!\n", chan->notifier_block->flags); -- cgit v1.2.3 From 2453ba19b6f9956ea5d412a66d5d33c8a8b301b2 Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Fri, 3 Aug 2007 23:06:39 +0200 Subject: nouveau:nv10: fill and use load,save graph context functions --- shared-core/nv10_graph.c | 55 +++++++++++++++++++++++------------------------- 1 file changed, 26 insertions(+), 29 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 930fcbdf..ce1cbfa7 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -544,24 +544,42 @@ static int nv10_graph_ctx_regs_find_offset(struct drm_device *dev, int reg) return -1; } -static void restore_ctx_regs(struct drm_device *dev, int channel) +int nv10_graph_load_context(struct drm_device *dev, int channel) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *fifo = dev_priv->fifos[channel]; int i, j; + for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) NV_WRITE(nv10_graph_ctx_regs[i], fifo->pgraph_ctx[i]); if (dev_priv->chipset>=0x17) { for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) NV_WRITE(nv17_graph_ctx_regs[j], fifo->pgraph_ctx[i]); } - nouveau_wait_for_idle(dev); + + return 0; +} + +int nv10_graph_save_context(struct drm_device *dev, int channel) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_fifo *fifo = dev_priv->fifos[channel]; + int i, j; + + for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) + fifo->pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); + if (dev_priv->chipset>=0x17) { + for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) + fifo->pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); + } + + return 0; } void nouveau_nv10_context_switch(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - int channel, channel_old, i, j; + int channel, channel_old; channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); @@ -574,14 +592,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev) NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000); NV_WRITE(NV_PFIFO_CACHES, 0x00000000); #endif - - // save PGRAPH context - for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) - dev_priv->fifos[channel_old]->pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); - if (dev_priv->chipset>=0x17) { - for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) - dev_priv->fifos[channel_old]->pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); - } + nv10_graph_save_context(dev, channel_old); nouveau_wait_for_idle(dev); @@ -589,15 +600,12 @@ void nouveau_nv10_context_switch(struct drm_device *dev) NV_WRITE(NV10_PGRAPH_CTX_USER, (NV_READ(NV10_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24)); nouveau_wait_for_idle(dev); - // restore PGRAPH context -#if 1 - restore_ctx_regs(dev, channel); -#endif + + nv10_graph_load_context(dev, channel); NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100); NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24); NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); - #if 0 NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); @@ -611,6 +619,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev) if (offset > 0) \ fifo->pgraph_ctx[offset] = val; \ } while (0) + int nv10_graph_create_context(struct drm_device *dev, int channel) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *fifo = dev_priv->fifos[channel]; @@ -654,7 +663,7 @@ int nv10_graph_create_context(struct drm_device *dev, int channel) { /* for the first channel init the regs */ if (dev_priv->fifo_alloc_count == 0) - restore_ctx_regs(dev, channel); + nv10_graph_load_context(dev, channel); //XXX should be saved/restored for each fifo @@ -667,18 +676,6 @@ void nv10_graph_destroy_context(struct drm_device *dev, int channel) { } -int nv10_graph_load_context(struct drm_device *dev, int channel) -{ - DRM_ERROR("stub!\n"); - return 0; -} - -int nv10_graph_save_context(struct drm_device *dev, int channel) -{ - DRM_ERROR("stub!\n"); - return 0; -} - int nv10_graph_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; int i; -- cgit v1.2.3 From beaa0c9a28b30a6ba3292184d04875b6a597e433 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 6 Aug 2007 03:40:43 +1000 Subject: nouveau: Pass channel struct around instead of channel id. --- shared-core/nouveau_drv.h | 391 ++++++++++++++++++++++------------------- shared-core/nouveau_fifo.c | 104 ++++++----- shared-core/nouveau_notifier.c | 42 ++--- shared-core/nouveau_object.c | 150 ++++++++-------- shared-core/nouveau_state.c | 7 +- shared-core/nv04_fifo.c | 29 ++- shared-core/nv04_graph.c | 15 +- shared-core/nv10_fifo.c | 27 ++- shared-core/nv10_graph.c | 49 +++--- shared-core/nv20_graph.c | 68 +++---- shared-core/nv30_graph.c | 35 ++-- shared-core/nv40_fifo.c | 24 +-- shared-core/nv40_graph.c | 26 ++- shared-core/nv50_fifo.c | 41 +++-- shared-core/nv50_graph.c | 27 ++- 15 files changed, 515 insertions(+), 520 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index dd323a0b..8ec91898 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -92,8 +92,11 @@ struct nouveau_gpuobj_ref { int handle; }; -struct nouveau_fifo +struct nouveau_channel { + struct drm_device *dev; + int id; + /* owner of this fifo */ struct drm_file *file_priv; /* mapping of the fifo itself */ @@ -136,57 +139,64 @@ struct nouveau_config { } cmdbuf; }; -struct nouveau_engine_func { - struct { - void *priv; +struct nouveau_instmem_engine { + void *priv; - int (*init)(struct drm_device *dev); - void (*takedown)(struct drm_device *dev); + int (*init)(struct drm_device *dev); + void (*takedown)(struct drm_device *dev); - int (*populate)(struct drm_device *, struct nouveau_gpuobj *, - uint32_t *size); - void (*clear)(struct drm_device *, struct nouveau_gpuobj *); - int (*bind)(struct drm_device *, struct nouveau_gpuobj *); - int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); - } instmem; + int (*populate)(struct drm_device *, struct nouveau_gpuobj *, + uint32_t *size); + void (*clear)(struct drm_device *, struct nouveau_gpuobj *); + int (*bind)(struct drm_device *, struct nouveau_gpuobj *); + int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); +}; - struct { - int (*init)(struct drm_device *dev); - void (*takedown)(struct drm_device *dev); - } mc; +struct nouveau_mc_engine { + int (*init)(struct drm_device *dev); + void (*takedown)(struct drm_device *dev); +}; - struct { - int (*init)(struct drm_device *dev); - uint64_t (*read)(struct drm_device *dev); - void (*takedown)(struct drm_device *dev); - } timer; +struct nouveau_timer_engine { + int (*init)(struct drm_device *dev); + void (*takedown)(struct drm_device *dev); + uint64_t (*read)(struct drm_device *dev); +}; - struct { - int (*init)(struct drm_device *dev); - void (*takedown)(struct drm_device *dev); - } fb; +struct nouveau_fb_engine { + int (*init)(struct drm_device *dev); + void (*takedown)(struct drm_device *dev); +}; - struct { - int (*init)(struct drm_device *); - void (*takedown)(struct drm_device *); +struct nouveau_fifo_engine { + void *priv; - int (*create_context)(struct drm_device *, int channel); - void (*destroy_context)(struct drm_device *, int channel); - int (*load_context)(struct drm_device *, int channel); - int (*save_context)(struct drm_device *, int channel); - } graph; + int (*init)(struct drm_device *); + void (*takedown)(struct drm_device *); - struct { - void *priv; + int (*create_context)(struct nouveau_channel *); + void (*destroy_context)(struct nouveau_channel *); + int (*load_context)(struct nouveau_channel *); + int (*save_context)(struct nouveau_channel *); +}; - int (*init)(struct drm_device *); - void (*takedown)(struct drm_device *); +struct nouveau_pgraph_engine { + int (*init)(struct drm_device *); + void (*takedown)(struct drm_device *); - int (*create_context)(struct drm_device *, int channel); - void (*destroy_context)(struct drm_device *, int channel); - int (*load_context)(struct drm_device *, int channel); - int (*save_context)(struct drm_device *, int channel); - } fifo; + int (*create_context)(struct nouveau_channel *); + void (*destroy_context)(struct nouveau_channel *); + int (*load_context)(struct nouveau_channel *); + int (*save_context)(struct nouveau_channel *); +}; + +struct nouveau_engine { + struct nouveau_instmem_engine instmem; + struct nouveau_mc_engine mc; + struct nouveau_timer_engine timer; + struct nouveau_fb_engine fb; + struct nouveau_pgraph_engine graph; + struct nouveau_fifo_engine fifo; }; struct drm_nouveau_private { @@ -207,9 +217,9 @@ struct drm_nouveau_private { drm_local_map_t *ramin; /* NV40 onwards */ int fifo_alloc_count; - struct nouveau_fifo *fifos[NV_MAX_FIFO_NUMBER]; + struct nouveau_channel *fifos[NV_MAX_FIFO_NUMBER]; - struct nouveau_engine_func Engine; + struct nouveau_engine Engine; /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ struct nouveau_gpuobj *ramht; @@ -262,93 +272,108 @@ struct drm_nouveau_private { struct nouveau_gpuobj *gpuobj_all; }; +#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id,cl,ch) do { \ + struct drm_nouveau_private *nv = dev->dev_private; \ + if (!nouveau_fifo_owner(dev, (cl), (id))) { \ + DRM_ERROR("pid %d doesn't own channel %d\n", \ + DRM_CURRENTPID, (id)); \ + return -EPERM; \ + } \ + (ch) = nv->fifos[(id)]; \ +} while(0) + /* nouveau_state.c */ -extern void nouveau_preclose(struct drm_device * dev, - struct drm_file *file_priv); -extern int nouveau_load(struct drm_device *dev, unsigned long flags); -extern int nouveau_firstopen(struct drm_device *dev); -extern void nouveau_lastclose(struct drm_device *dev); -extern int nouveau_unload(struct drm_device *dev); -extern int nouveau_ioctl_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int nouveau_ioctl_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern void nouveau_wait_for_idle(struct drm_device *dev); -extern int nouveau_ioctl_card_init(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); +extern int nouveau_load(struct drm_device *, unsigned long flags); +extern int nouveau_firstopen(struct drm_device *); +extern void nouveau_lastclose(struct drm_device *); +extern int nouveau_unload(struct drm_device *); +extern int nouveau_ioctl_getparam(struct drm_device *, void *data, + struct drm_file *); +extern int nouveau_ioctl_setparam(struct drm_device *, void *data, + struct drm_file *); +extern void nouveau_wait_for_idle(struct drm_device *); +extern int nouveau_ioctl_card_init(struct drm_device *, void *data, + struct drm_file *); /* nouveau_mem.c */ -extern int nouveau_mem_init_heap(struct mem_block **, - uint64_t start, uint64_t size); +extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start, + uint64_t size); extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *, uint64_t size, int align2, - struct drm_file *file_priv); -extern void nouveau_mem_takedown(struct mem_block **heap); -extern void nouveau_mem_free_block(struct mem_block *); -extern uint64_t nouveau_mem_fb_amount(struct drm_device *dev); -extern void nouveau_mem_release(struct drm_file *file_priv, - struct mem_block *heap); -extern int nouveau_ioctl_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern int nouveau_ioctl_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); -extern struct mem_block* nouveau_mem_alloc(struct drm_device *dev, + struct drm_file *); +extern void nouveau_mem_takedown(struct mem_block **heap); +extern void nouveau_mem_free_block(struct mem_block *); +extern uint64_t nouveau_mem_fb_amount(struct drm_device *); +extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap); +extern int nouveau_ioctl_mem_alloc(struct drm_device *, void *data, + struct drm_file *); +extern int nouveau_ioctl_mem_free(struct drm_device *, void *data, + struct drm_file *); +extern struct mem_block* nouveau_mem_alloc(struct drm_device *, int alignment, uint64_t size, - int flags, - struct drm_file *file_priv); -extern void nouveau_mem_free(struct drm_device* dev, struct mem_block*); -extern int nouveau_mem_init(struct drm_device *dev); -extern void nouveau_mem_close(struct drm_device *dev); + int flags, struct drm_file *); +extern void nouveau_mem_free(struct drm_device *dev, struct mem_block*); +extern int nouveau_mem_init(struct drm_device *); +extern void nouveau_mem_close(struct drm_device *); /* nouveau_notifier.c */ -extern int nouveau_notifier_init_channel(struct drm_device *, int channel, - struct drm_file *file_priv); -extern void nouveau_notifier_takedown_channel(struct drm_device *, int channel); -extern int nouveau_notifier_alloc(struct drm_device *, int channel, - uint32_t handle, int cout, uint32_t *offset); -extern int nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int nouveau_notifier_init_channel(struct nouveau_channel *); +extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); +extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, + int cout, uint32_t *offset); +extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, + struct drm_file *); /* nouveau_fifo.c */ -extern int nouveau_fifo_init(struct drm_device *dev); -extern int nouveau_fifo_number(struct drm_device *dev); -extern int nouveau_fifo_ctx_size(struct drm_device *dev); -extern void nouveau_fifo_cleanup(struct drm_device *dev, - struct drm_file *file_priv); -extern int nouveau_fifo_owner(struct drm_device *dev, - struct drm_file *file_priv, int channel); -extern void nouveau_fifo_free(struct drm_device *dev, int channel); +extern int nouveau_fifo_init(struct drm_device *); +extern int nouveau_fifo_number(struct drm_device *); +extern int nouveau_fifo_ctx_size(struct drm_device *); +extern void nouveau_fifo_cleanup(struct drm_device *, struct drm_file *); +extern int nouveau_fifo_owner(struct drm_device *, struct drm_file *, + int channel); +extern void nouveau_fifo_free(struct nouveau_channel *); /* nouveau_object.c */ -extern void nouveau_gpuobj_takedown(struct drm_device *dev); -extern int nouveau_gpuobj_channel_init(struct drm_device *, int channel, +extern void nouveau_gpuobj_takedown(struct drm_device *); +extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, uint32_t vram_h, uint32_t tt_h); -extern void nouveau_gpuobj_channel_takedown(struct drm_device *, int channel); -extern int nouveau_gpuobj_new(struct drm_device *, int channel, int size, int align, - uint32_t flags, struct nouveau_gpuobj **); +extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); +extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, + int size, int align, uint32_t flags, + struct nouveau_gpuobj **); extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **); -extern int nouveau_gpuobj_ref_add(struct drm_device *, int channel, uint32_t handle, - struct nouveau_gpuobj *, +extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *, + uint32_t handle, struct nouveau_gpuobj *, + struct nouveau_gpuobj_ref **); +extern int nouveau_gpuobj_ref_del(struct drm_device *, struct nouveau_gpuobj_ref **); -extern int nouveau_gpuobj_ref_del(struct drm_device *, struct nouveau_gpuobj_ref **); -extern int nouveau_gpuobj_new_ref(struct drm_device *, int chan_obj, int chan_ref, +extern int nouveau_gpuobj_new_ref(struct drm_device *, + struct nouveau_channel *alloc_chan, + struct nouveau_channel *ref_chan, uint32_t handle, int size, int align, uint32_t flags, struct nouveau_gpuobj_ref **); extern int nouveau_gpuobj_new_fake(struct drm_device *, uint32_t offset, uint32_t size, uint32_t flags, - struct nouveau_gpuobj**, + struct nouveau_gpuobj **, struct nouveau_gpuobj_ref**); -extern int nouveau_gpuobj_dma_new(struct drm_device *, int channel, int class, - uint64_t offset, uint64_t size, - int access, int target, - struct nouveau_gpuobj **); -extern int nouveau_gpuobj_gart_dma_new(struct drm_device *, int channel, +extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, + uint64_t offset, uint64_t size, int access, + int target, struct nouveau_gpuobj **); +extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, uint64_t offset, uint64_t size, int access, struct nouveau_gpuobj **, uint32_t *o_ret); -extern int nouveau_gpuobj_gr_new(struct drm_device *, int channel, int class, +extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, struct nouveau_gpuobj **); -extern int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, + struct drm_file *); /* nouveau_irq.c */ extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); -extern void nouveau_irq_preinstall(struct drm_device*); -extern void nouveau_irq_postinstall(struct drm_device*); -extern void nouveau_irq_uninstall(struct drm_device*); +extern void nouveau_irq_preinstall(struct drm_device *); +extern void nouveau_irq_postinstall(struct drm_device *); +extern void nouveau_irq_uninstall(struct drm_device *); /* nouveau_sgdma.c */ extern int nouveau_sgdma_init(struct drm_device *); @@ -358,131 +383,131 @@ extern int nouveau_sgdma_nottm_hack_init(struct drm_device *); extern void nouveau_sgdma_nottm_hack_takedown(struct drm_device *); /* nv04_fb.c */ -extern int nv04_fb_init(struct drm_device *dev); -extern void nv04_fb_takedown(struct drm_device *dev); +extern int nv04_fb_init(struct drm_device *); +extern void nv04_fb_takedown(struct drm_device *); /* nv10_fb.c */ -extern int nv10_fb_init(struct drm_device *dev); -extern void nv10_fb_takedown(struct drm_device *dev); +extern int nv10_fb_init(struct drm_device *); +extern void nv10_fb_takedown(struct drm_device *); /* nv40_fb.c */ -extern int nv40_fb_init(struct drm_device *dev); -extern void nv40_fb_takedown(struct drm_device *dev); +extern int nv40_fb_init(struct drm_device *); +extern void nv40_fb_takedown(struct drm_device *); /* nv04_fifo.c */ -extern int nv04_fifo_create_context(struct drm_device *dev, int channel); -extern void nv04_fifo_destroy_context(struct drm_device *dev, int channel); -extern int nv04_fifo_load_context(struct drm_device *dev, int channel); -extern int nv04_fifo_save_context(struct drm_device *dev, int channel); +extern int nv04_fifo_create_context(struct nouveau_channel *); +extern void nv04_fifo_destroy_context(struct nouveau_channel *); +extern int nv04_fifo_load_context(struct nouveau_channel *); +extern int nv04_fifo_save_context(struct nouveau_channel *); /* nv10_fifo.c */ -extern int nv10_fifo_create_context(struct drm_device *dev, int channel); -extern void nv10_fifo_destroy_context(struct drm_device *dev, int channel); -extern int nv10_fifo_load_context(struct drm_device *dev, int channel); -extern int nv10_fifo_save_context(struct drm_device *dev, int channel); +extern int nv10_fifo_create_context(struct nouveau_channel *); +extern void nv10_fifo_destroy_context(struct nouveau_channel *); +extern int nv10_fifo_load_context(struct nouveau_channel *); +extern int nv10_fifo_save_context(struct nouveau_channel *); /* nv40_fifo.c */ -extern int nv40_fifo_create_context(struct drm_device *, int channel); -extern void nv40_fifo_destroy_context(struct drm_device *, int channel); -extern int nv40_fifo_load_context(struct drm_device *, int channel); -extern int nv40_fifo_save_context(struct drm_device *, int channel); +extern int nv40_fifo_create_context(struct nouveau_channel *); +extern void nv40_fifo_destroy_context(struct nouveau_channel *); +extern int nv40_fifo_load_context(struct nouveau_channel *); +extern int nv40_fifo_save_context(struct nouveau_channel *); /* nv50_fifo.c */ extern int nv50_fifo_init(struct drm_device *); extern void nv50_fifo_takedown(struct drm_device *); -extern int nv50_fifo_create_context(struct drm_device *, int channel); -extern void nv50_fifo_destroy_context(struct drm_device *, int channel); -extern int nv50_fifo_load_context(struct drm_device *, int channel); -extern int nv50_fifo_save_context(struct drm_device *, int channel); +extern int nv50_fifo_create_context(struct nouveau_channel *); +extern void nv50_fifo_destroy_context(struct nouveau_channel *); +extern int nv50_fifo_load_context(struct nouveau_channel *); +extern int nv50_fifo_save_context(struct nouveau_channel *); /* nv04_graph.c */ -extern void nouveau_nv04_context_switch(struct drm_device *dev); -extern int nv04_graph_init(struct drm_device *dev); -extern void nv04_graph_takedown(struct drm_device *dev); -extern int nv04_graph_create_context(struct drm_device *dev, int channel); -extern void nv04_graph_destroy_context(struct drm_device *dev, int channel); -extern int nv04_graph_load_context(struct drm_device *dev, int channel); -extern int nv04_graph_save_context(struct drm_device *dev, int channel); +extern void nouveau_nv04_context_switch(struct drm_device *); +extern int nv04_graph_init(struct drm_device *); +extern void nv04_graph_takedown(struct drm_device *); +extern int nv04_graph_create_context(struct nouveau_channel *); +extern void nv04_graph_destroy_context(struct nouveau_channel *); +extern int nv04_graph_load_context(struct nouveau_channel *); +extern int nv04_graph_save_context(struct nouveau_channel *); /* nv10_graph.c */ -extern void nouveau_nv10_context_switch(struct drm_device *dev); -extern int nv10_graph_init(struct drm_device *dev); -extern void nv10_graph_takedown(struct drm_device *dev); -extern int nv10_graph_create_context(struct drm_device *dev, int channel); -extern void nv10_graph_destroy_context(struct drm_device *dev, int channel); -extern int nv10_graph_load_context(struct drm_device *dev, int channel); -extern int nv10_graph_save_context(struct drm_device *dev, int channel); +extern void nouveau_nv10_context_switch(struct drm_device *); +extern int nv10_graph_init(struct drm_device *); +extern void nv10_graph_takedown(struct drm_device *); +extern int nv10_graph_create_context(struct nouveau_channel *); +extern void nv10_graph_destroy_context(struct nouveau_channel *); +extern int nv10_graph_load_context(struct nouveau_channel *); +extern int nv10_graph_save_context(struct nouveau_channel *); /* nv20_graph.c */ -extern void nouveau_nv20_context_switch(struct drm_device *dev); -extern int nv20_graph_init(struct drm_device *dev); -extern void nv20_graph_takedown(struct drm_device *dev); -extern int nv20_graph_create_context(struct drm_device *dev, int channel); -extern void nv20_graph_destroy_context(struct drm_device *dev, int channel); -extern int nv20_graph_load_context(struct drm_device *dev, int channel); -extern int nv20_graph_save_context(struct drm_device *dev, int channel); +extern void nouveau_nv20_context_switch(struct drm_device *); +extern int nv20_graph_init(struct drm_device *); +extern void nv20_graph_takedown(struct drm_device *); +extern int nv20_graph_create_context(struct nouveau_channel *); +extern void nv20_graph_destroy_context(struct nouveau_channel *); +extern int nv20_graph_load_context(struct nouveau_channel *); +extern int nv20_graph_save_context(struct nouveau_channel *); /* nv30_graph.c */ -extern int nv30_graph_init(struct drm_device *dev); -extern void nv30_graph_takedown(struct drm_device *dev); -extern int nv30_graph_create_context(struct drm_device *, int channel); -extern void nv30_graph_destroy_context(struct drm_device *, int channel); -extern int nv30_graph_load_context(struct drm_device *, int channel); -extern int nv30_graph_save_context(struct drm_device *, int channel); +extern int nv30_graph_init(struct drm_device *); +extern void nv30_graph_takedown(struct drm_device *); +extern int nv30_graph_create_context(struct nouveau_channel *); +extern void nv30_graph_destroy_context(struct nouveau_channel *); +extern int nv30_graph_load_context(struct nouveau_channel *); +extern int nv30_graph_save_context(struct nouveau_channel *); /* nv40_graph.c */ extern int nv40_graph_init(struct drm_device *); extern void nv40_graph_takedown(struct drm_device *); -extern int nv40_graph_create_context(struct drm_device *, int channel); -extern void nv40_graph_destroy_context(struct drm_device *, int channel); -extern int nv40_graph_load_context(struct drm_device *, int channel); -extern int nv40_graph_save_context(struct drm_device *, int channel); +extern int nv40_graph_create_context(struct nouveau_channel *); +extern void nv40_graph_destroy_context(struct nouveau_channel *); +extern int nv40_graph_load_context(struct nouveau_channel *); +extern int nv40_graph_save_context(struct nouveau_channel *); /* nv50_graph.c */ extern int nv50_graph_init(struct drm_device *); extern void nv50_graph_takedown(struct drm_device *); -extern int nv50_graph_create_context(struct drm_device *, int channel); -extern void nv50_graph_destroy_context(struct drm_device *, int channel); -extern int nv50_graph_load_context(struct drm_device *, int channel); -extern int nv50_graph_save_context(struct drm_device *, int channel); +extern int nv50_graph_create_context(struct nouveau_channel *); +extern void nv50_graph_destroy_context(struct nouveau_channel *); +extern int nv50_graph_load_context(struct nouveau_channel *); +extern int nv50_graph_save_context(struct nouveau_channel *); /* nv04_instmem.c */ -extern int nv04_instmem_init(struct drm_device *dev); -extern void nv04_instmem_takedown(struct drm_device *dev); -extern int nv04_instmem_populate(struct drm_device*, struct nouveau_gpuobj*, +extern int nv04_instmem_init(struct drm_device *); +extern void nv04_instmem_takedown(struct drm_device *); +extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, uint32_t *size); -extern void nv04_instmem_clear(struct drm_device*, struct nouveau_gpuobj*); -extern int nv04_instmem_bind(struct drm_device*, struct nouveau_gpuobj*); -extern int nv04_instmem_unbind(struct drm_device*, struct nouveau_gpuobj*); +extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); +extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); +extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); /* nv50_instmem.c */ -extern int nv50_instmem_init(struct drm_device *dev); -extern void nv50_instmem_takedown(struct drm_device *dev); -extern int nv50_instmem_populate(struct drm_device*, struct nouveau_gpuobj*, +extern int nv50_instmem_init(struct drm_device *); +extern void nv50_instmem_takedown(struct drm_device *); +extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, uint32_t *size); -extern void nv50_instmem_clear(struct drm_device*, struct nouveau_gpuobj*); -extern int nv50_instmem_bind(struct drm_device*, struct nouveau_gpuobj*); -extern int nv50_instmem_unbind(struct drm_device*, struct nouveau_gpuobj*); +extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); +extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); +extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); /* nv04_mc.c */ -extern int nv04_mc_init(struct drm_device *dev); -extern void nv04_mc_takedown(struct drm_device *dev); +extern int nv04_mc_init(struct drm_device *); +extern void nv04_mc_takedown(struct drm_device *); /* nv40_mc.c */ -extern int nv40_mc_init(struct drm_device *dev); -extern void nv40_mc_takedown(struct drm_device *dev); +extern int nv40_mc_init(struct drm_device *); +extern void nv40_mc_takedown(struct drm_device *); /* nv50_mc.c */ -extern int nv50_mc_init(struct drm_device *dev); -extern void nv50_mc_takedown(struct drm_device *dev); +extern int nv50_mc_init(struct drm_device *); +extern void nv50_mc_takedown(struct drm_device *); /* nv04_timer.c */ -extern int nv04_timer_init(struct drm_device *dev); -extern uint64_t nv04_timer_read(struct drm_device *dev); -extern void nv04_timer_takedown(struct drm_device *dev); +extern int nv04_timer_init(struct drm_device *); +extern uint64_t nv04_timer_read(struct drm_device *); +extern void nv04_timer_takedown(struct drm_device *); extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, - unsigned long arg); + unsigned long arg); #if defined(__powerpc__) #define NV_READ(reg) in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) ) diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index e5d3ab3c..c7ce1d8d 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -186,10 +186,10 @@ int nouveau_fifo_init(struct drm_device *dev) } static int -nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) +nouveau_fifo_cmdbuf_alloc(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; struct nouveau_config *config = &dev_priv->config; struct mem_block *cb; int cb_min_size = max(NV03_FIFO_SIZE,PAGE_SIZE); @@ -211,37 +211,34 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) } if (cb->flags & NOUVEAU_MEM_AGP) { - ret = nouveau_gpuobj_gart_dma_new(dev, channel, - cb->start, cb->size, + ret = nouveau_gpuobj_gart_dma_new(chan, cb->start, cb->size, NV_DMA_ACCESS_RO, &pushbuf, &chan->pushbuf_base); } else if (cb->flags & NOUVEAU_MEM_PCI) { - ret = nouveau_gpuobj_dma_new(dev, channel, - NV_CLASS_DMA_IN_MEMORY, + ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, cb->start, cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_PCI_NONLINEAR, &pushbuf); chan->pushbuf_base = 0; } else if (dev_priv->card_type != NV_04) { - ret = nouveau_gpuobj_dma_new - (dev, channel, NV_CLASS_DMA_IN_MEMORY, - cb->start, - cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM, - &pushbuf); + ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, + cb->start, cb->size, + NV_DMA_ACCESS_RO, + NV_DMA_TARGET_VIDMEM, &pushbuf); chan->pushbuf_base = 0; } else { /* NV04 cmdbuf hack, from original ddx.. not sure of it's * exact reason for existing :) PCI access to cmdbuf in * VRAM. */ - ret = nouveau_gpuobj_dma_new - (dev, channel, NV_CLASS_DMA_IN_MEMORY, - cb->start + drm_get_resource_start(dev, 1), - cb->size, NV_DMA_ACCESS_RO, - NV_DMA_TARGET_PCI, &pushbuf); + ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, + cb->start + + drm_get_resource_start(dev, 1), + cb->size, NV_DMA_ACCESS_RO, + NV_DMA_TARGET_PCI, &pushbuf); chan->pushbuf_base = 0; } @@ -251,7 +248,7 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel) return ret; } - if ((ret = nouveau_gpuobj_ref_add(dev, channel, 0, pushbuf, + if ((ret = nouveau_gpuobj_ref_add(dev, chan, 0, pushbuf, &chan->pushbuf))) { DRM_ERROR("Error referencing push buffer ctxdma: %d\n", ret); if (pushbuf != dev_priv->gart_info.sg_ctxdma) @@ -270,8 +267,8 @@ int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret, { int ret; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine_func *engine = &dev_priv->Engine; - struct nouveau_fifo *chan; + struct nouveau_engine *engine = &dev_priv->Engine; + struct nouveau_channel *chan; int channel; /* @@ -293,34 +290,36 @@ int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret, return -EINVAL; (*chan_ret) = channel; - dev_priv->fifos[channel] = drm_calloc(1, sizeof(struct nouveau_fifo), + dev_priv->fifos[channel] = drm_calloc(1, sizeof(struct nouveau_channel), DRM_MEM_DRIVER); if (!dev_priv->fifos[channel]) return -ENOMEM; dev_priv->fifo_alloc_count++; chan = dev_priv->fifos[channel]; + chan->dev = dev; + chan->id = channel; chan->file_priv = file_priv; DRM_INFO("Allocating FIFO number %d\n", channel); /* Setup channel's default objects */ - ret = nouveau_gpuobj_channel_init(dev, channel, vram_handle, tt_handle); + ret = nouveau_gpuobj_channel_init(chan, vram_handle, tt_handle); if (ret) { - nouveau_fifo_free(dev, channel); + nouveau_fifo_free(chan); return ret; } /* allocate a command buffer, and create a dma object for the gpu */ - ret = nouveau_fifo_cmdbuf_alloc(dev, channel); + ret = nouveau_fifo_cmdbuf_alloc(chan); if (ret) { - nouveau_fifo_free(dev, channel); + nouveau_fifo_free(chan); return ret; } /* Allocate space for per-channel fixed notifier memory */ - ret = nouveau_notifier_init_channel(dev, channel, file_priv); + ret = nouveau_notifier_init_channel(chan); if (ret) { - nouveau_fifo_free(dev, channel); + nouveau_fifo_free(chan); return ret; } @@ -333,16 +332,16 @@ int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret, NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000); /* Create a graphics context for new channel */ - ret = engine->graph.create_context(dev, channel); + ret = engine->graph.create_context(chan); if (ret) { - nouveau_fifo_free(dev, channel); + nouveau_fifo_free(chan); return ret; } /* Construct inital RAMFC for new channel */ - ret = engine->fifo.create_context(dev, channel); + ret = engine->fifo.create_context(chan); if (ret) { - nouveau_fifo_free(dev, channel); + nouveau_fifo_free(chan); return ret; } @@ -359,15 +358,15 @@ int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret, * other case, the GPU will handle this when it switches contexts. */ if (dev_priv->fifo_alloc_count == 1) { - ret = engine->fifo.load_context(dev, channel); + ret = engine->fifo.load_context(chan); if (ret) { - nouveau_fifo_free(dev, channel); + nouveau_fifo_free(chan); return ret; } - ret = engine->graph.load_context(dev, channel); + ret = engine->graph.load_context(chan); if (ret) { - nouveau_fifo_free(dev, channel); + nouveau_fifo_free(chan); return ret; } @@ -399,28 +398,23 @@ int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret, } /* stops a fifo */ -void nouveau_fifo_free(struct drm_device *dev, int channel) +void nouveau_fifo_free(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine_func *engine = &dev_priv->Engine; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; - - if (!chan) { - DRM_ERROR("Freeing non-existant channel %d\n", channel); - return; - } + struct nouveau_engine *engine = &dev_priv->Engine; - DRM_INFO("%s: freeing fifo %d\n", __func__, channel); + DRM_INFO("%s: freeing fifo %d\n", __func__, chan->id); /* disable the fifo caches */ NV_WRITE(NV03_PFIFO_CACHES, 0x00000000); // FIXME XXX needs more code - engine->fifo.destroy_context(dev, channel); + engine->fifo.destroy_context(chan); /* Cleanup PGRAPH state */ - engine->graph.destroy_context(dev, channel); + engine->graph.destroy_context(chan); /* reenable the fifo caches */ NV_WRITE(NV03_PFIFO_CACHES, 0x00000001); @@ -432,12 +426,12 @@ void nouveau_fifo_free(struct drm_device *dev, int channel) chan->pushbuf_mem = NULL; } - nouveau_notifier_takedown_channel(dev, channel); + nouveau_notifier_takedown_channel(chan); /* Destroy objects belonging to the channel */ - nouveau_gpuobj_channel_takedown(dev, channel); + nouveau_gpuobj_channel_takedown(chan); - dev_priv->fifos[channel] = NULL; + dev_priv->fifos[chan->id] = NULL; dev_priv->fifo_alloc_count--; drm_free(chan, sizeof(*chan), DRM_MEM_DRIVER); } @@ -445,14 +439,16 @@ void nouveau_fifo_free(struct drm_device *dev, int channel) /* cleanups all the fifos from file_priv */ void nouveau_fifo_cleanup(struct drm_device *dev, struct drm_file *file_priv) { - int i; struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; DRM_DEBUG("clearing FIFO enables from file_priv\n"); - for(i=0;ififos[i] && - dev_priv->fifos[i]->file_priv==file_priv) - nouveau_fifo_free(dev,i); + for(i = 0; i < nouveau_fifo_number(dev); i++) { + struct nouveau_channel *chan = dev_priv->fifos[i]; + + if (chan && chan->file_priv == file_priv) + nouveau_fifo_free(chan); + } } int @@ -477,7 +473,7 @@ static int nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, struct d struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_fifo_alloc *init = data; struct drm_map_list *entry; - struct nouveau_fifo *chan; + struct nouveau_channel *chan; int res; if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0) diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index 7a982ba4..b1090587 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -30,11 +30,10 @@ #include "nouveau_drv.h" int -nouveau_notifier_init_channel(struct drm_device *dev, int channel, - struct drm_file *file_priv) +nouveau_notifier_init_channel(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; int flags, ret; /*TODO: PCI notifier blocks */ @@ -47,9 +46,9 @@ nouveau_notifier_init_channel(struct drm_device *dev, int channel, flags = NOUVEAU_MEM_FB; flags |= NOUVEAU_MEM_MAPPED; -DRM_DEBUG("Allocating notifier block in %d\n", flags); + DRM_DEBUG("Allocating notifier block in %d\n", flags); chan->notifier_block = nouveau_mem_alloc(dev, 0, PAGE_SIZE, flags, - file_priv); + (struct drm_file *)-2); if (!chan->notifier_block) return -ENOMEM; @@ -62,25 +61,23 @@ DRM_DEBUG("Allocating notifier block in %d\n", flags); } void -nouveau_notifier_takedown_channel(struct drm_device *dev, int channel) +nouveau_notifier_takedown_channel(struct nouveau_channel *chan) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; + struct drm_device *dev = chan->dev; if (chan->notifier_block) { nouveau_mem_free(dev, chan->notifier_block); chan->notifier_block = NULL; } - /*XXX: heap destroy */ + nouveau_mem_takedown(&chan->notifier_heap); } int -nouveau_notifier_alloc(struct drm_device *dev, int channel, uint32_t handle, +nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle, int count, uint32_t *b_offset) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; + struct drm_device *dev = chan->dev; struct nouveau_gpuobj *nobj = NULL; struct mem_block *mem; uint32_t offset; @@ -88,14 +85,14 @@ nouveau_notifier_alloc(struct drm_device *dev, int channel, uint32_t handle, if (!chan->notifier_heap) { DRM_ERROR("Channel %d doesn't have a notifier heap!\n", - channel); + chan->id); return -EINVAL; } mem = nouveau_mem_alloc_block(chan->notifier_heap, 32, 0, chan->file_priv); if (!mem) { - DRM_ERROR("Channel %d notifier block full\n", channel); + DRM_ERROR("Channel %d notifier block full\n", chan->id); return -ENOMEM; } mem->flags = NOUVEAU_MEM_NOTIFIER; @@ -113,7 +110,7 @@ nouveau_notifier_alloc(struct drm_device *dev, int channel, uint32_t handle, return -EINVAL; } - if ((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, + if ((ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, offset, mem->size, NV_DMA_ACCESS_RW, target, &nobj))) { nouveau_mem_free_block(mem); @@ -121,7 +118,7 @@ nouveau_notifier_alloc(struct drm_device *dev, int channel, uint32_t handle, return ret; } - if ((ret = nouveau_gpuobj_ref_add(dev, channel, handle, nobj, NULL))) { + if ((ret = nouveau_gpuobj_ref_add(dev, chan, handle, nobj, NULL))) { nouveau_gpuobj_del(dev, &nobj); nouveau_mem_free_block(mem); DRM_ERROR("Error referencing notifier ctxdma: %d\n", ret); @@ -133,19 +130,16 @@ nouveau_notifier_alloc(struct drm_device *dev, int channel, uint32_t handle, } int -nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) +nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data, + struct drm_file *file_priv) { struct drm_nouveau_notifier_alloc *na = data; + struct nouveau_channel *chan; int ret; - if (!nouveau_fifo_owner(dev, file_priv, na->channel)) { - DRM_ERROR("pid %d doesn't own channel %d\n", - DRM_CURRENTPID, na->channel); - return -EPERM; - } + NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(na->channel, file_priv, chan); - ret = nouveau_notifier_alloc(dev, na->channel, na->handle, - na->count, &na->offset); + ret = nouveau_notifier_alloc(chan, na->handle, na->count, &na->offset); if (ret) return ret; diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index e8b12bb7..274bb2a7 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -100,7 +100,7 @@ static int nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) { struct drm_nouveau_private *dev_priv=dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[ref->channel]; + struct nouveau_channel *chan = dev_priv->fifos[ref->channel]; struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL; struct nouveau_gpuobj *gpuobj = ref->gpuobj; uint32_t ctx, co, ho; @@ -149,7 +149,7 @@ static void nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[ref->channel]; + struct nouveau_channel *chan = dev_priv->fifos[ref->channel]; struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL; uint32_t co, ho; @@ -180,34 +180,28 @@ nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) } int -nouveau_gpuobj_new(struct drm_device *dev, int channel, int size, int align, - uint32_t flags, struct nouveau_gpuobj **gpuobj_ret) +nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan, + int size, int align, uint32_t flags, + struct nouveau_gpuobj **gpuobj_ret) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine_func *engine = &dev_priv->Engine; - struct nouveau_fifo *chan = NULL; + struct nouveau_engine *engine = &dev_priv->Engine; struct nouveau_gpuobj *gpuobj; struct mem_block *pramin = NULL; int ret; DRM_DEBUG("ch%d size=%d align=%d flags=0x%08x\n", - channel, size, align, flags); + chan ? chan->id : -1, size, align, flags); if (!dev_priv || !gpuobj_ret || *gpuobj_ret != NULL) return -EINVAL; - if (channel >= 0) { - if (channel > nouveau_fifo_number(dev)) - return -EINVAL; - chan = dev_priv->fifos[channel]; - } - gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER); if (!gpuobj) return -ENOMEM; DRM_DEBUG("gpuobj %p\n", gpuobj); gpuobj->flags = flags; - gpuobj->im_channel = channel; + gpuobj->im_channel = chan ? chan->id : -1; /* Choose between global instmem heap, and per-channel private * instmem heap. On dev_private; - struct nouveau_engine_func *engine = &dev_priv->Engine; + struct nouveau_engine *engine = &dev_priv->Engine; struct nouveau_gpuobj *gpuobj; DRM_DEBUG("gpuobj %p\n", pgpuobj ? *pgpuobj : NULL); @@ -325,7 +319,8 @@ int nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj) } static int -nouveau_gpuobj_instance_get(struct drm_device *dev, int channel, +nouveau_gpuobj_instance_get(struct drm_device *dev, + struct nouveau_channel *chan, struct nouveau_gpuobj *gpuobj, uint32_t *inst) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -337,15 +332,15 @@ nouveau_gpuobj_instance_get(struct drm_device *dev, int channel, return 0; } - if ((channel > 0) && gpuobj->im_channel != channel) { + if (chan && gpuobj->im_channel != chan->id) { DRM_ERROR("Channel mismatch: obj %d, ref %d\n", - gpuobj->im_channel, channel); + gpuobj->im_channel, chan->id); return -EINVAL; } /* NV50 channel-local instance */ - if (channel > 0) { - cpramin = dev_priv->fifos[channel]->ramin->gpuobj; + if (chan > 0) { + cpramin = chan->ramin->gpuobj; *inst = gpuobj->im_pramin->start - cpramin->im_pramin->start; return 0; } @@ -371,29 +366,25 @@ nouveau_gpuobj_instance_get(struct drm_device *dev, int channel, } int -nouveau_gpuobj_ref_add(struct drm_device *dev, int channel, uint32_t handle, - struct nouveau_gpuobj *gpuobj, struct nouveau_gpuobj_ref **ref_ret) +nouveau_gpuobj_ref_add(struct drm_device *dev, struct nouveau_channel *chan, + uint32_t handle, struct nouveau_gpuobj *gpuobj, + struct nouveau_gpuobj_ref **ref_ret) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = NULL; struct nouveau_gpuobj_ref *ref; uint32_t instance; int ret; - DRM_DEBUG("ch%d h=0x%08x gpuobj=%p\n", channel, handle, gpuobj); + DRM_DEBUG("ch%d h=0x%08x gpuobj=%p\n", + chan ? chan->id : -1, handle, gpuobj); if (!dev_priv || !gpuobj || (ref_ret && *ref_ret != NULL)) return -EINVAL; - if (channel >= 0) { - if (channel > nouveau_fifo_number(dev)) - return -EINVAL; - chan = dev_priv->fifos[channel]; - } else - if (!ref_ret) + if (!chan && !ref_ret) return -EINVAL; - ret = nouveau_gpuobj_instance_get(dev, channel, gpuobj, &instance); + ret = nouveau_gpuobj_instance_get(dev, chan, gpuobj, &instance); if (ret) return ret; @@ -401,7 +392,7 @@ nouveau_gpuobj_ref_add(struct drm_device *dev, int channel, uint32_t handle, if (!ref) return -ENOMEM; ref->gpuobj = gpuobj; - ref->channel = channel; + ref->channel = chan ? chan->id : -1; ref->instance = instance; if (!ref_ret) { @@ -452,8 +443,9 @@ int nouveau_gpuobj_ref_del(struct drm_device *dev, struct nouveau_gpuobj_ref **p } int -nouveau_gpuobj_new_ref(struct drm_device *dev, int oc, int rc, uint32_t handle, - int size, int align, uint32_t flags, +nouveau_gpuobj_new_ref(struct drm_device *dev, + struct nouveau_channel *oc, struct nouveau_channel *rc, + uint32_t handle, int size, int align, uint32_t flags, struct nouveau_gpuobj_ref **ref) { struct nouveau_gpuobj *gpuobj = NULL; @@ -471,11 +463,9 @@ nouveau_gpuobj_new_ref(struct drm_device *dev, int oc, int rc, uint32_t handle, } static int -nouveau_gpuobj_ref_find(struct drm_device *dev, int channel, uint32_t handle, +nouveau_gpuobj_ref_find(struct nouveau_channel *chan, uint32_t handle, struct nouveau_gpuobj_ref **ref_ret) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; struct nouveau_gpuobj_ref *ref = chan->ramht_refs; while (ref) { @@ -524,7 +514,7 @@ nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t offset, uint32_t size, } if (pref) { - if ((i = nouveau_gpuobj_ref_add(dev, -1, 0, gpuobj, pref))) { + if ((i = nouveau_gpuobj_ref_add(dev, NULL, 0, gpuobj, pref))) { nouveau_gpuobj_del(dev, &gpuobj); return i; } @@ -577,10 +567,11 @@ nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class) to it that can be used to set up context objects. */ int -nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class, - uint64_t offset, uint64_t size, int access, int target, - struct nouveau_gpuobj **gpuobj) +nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, + uint64_t offset, uint64_t size, int access, + int target, struct nouveau_gpuobj **gpuobj) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; uint32_t is_scatter_gather = 0; @@ -591,7 +582,7 @@ nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class, DRM_DEBUG("ch%d class=0x%04x offset=0x%llx size=0x%llx\n", - channel, class, offset, size); + chan->id, class, offset, size); DRM_DEBUG("access=%d target=%d\n", access, target); switch (target) { @@ -608,7 +599,7 @@ nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class, break; } - ret = nouveau_gpuobj_new(dev, channel, + ret = nouveau_gpuobj_new(dev, chan, is_scatter_gather ? ((page_count << 2) + 12) : nouveau_gpuobj_class_instmem_size(dev, class), 16, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, @@ -711,19 +702,19 @@ nouveau_gpuobj_dma_new(struct drm_device *dev, int channel, int class, } int -nouveau_gpuobj_gart_dma_new(struct drm_device *dev, int channel, +nouveau_gpuobj_gart_dma_new(struct nouveau_channel *chan, uint64_t offset, uint64_t size, int access, struct nouveau_gpuobj **gpuobj, uint32_t *o_ret) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; if (dev_priv->gart_info.type == NOUVEAU_GART_AGP || (dev_priv->card_type >= NV_50 && dev_priv->gart_info.type == NOUVEAU_GART_SGDMA)) { - ret = nouveau_gpuobj_dma_new(dev, channel, - NV_CLASS_DMA_IN_MEMORY, + ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, offset, size, access, NV_DMA_TARGET_AGP, gpuobj); if (o_ret) @@ -798,15 +789,16 @@ nouveau_gpuobj_gart_dma_new(struct drm_device *dev, int channel, set to 0? */ int -nouveau_gpuobj_gr_new(struct drm_device *dev, int channel, int class, +nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class, struct nouveau_gpuobj **gpuobj) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; - DRM_DEBUG("ch%d class=0x%04x\n", channel, class); + DRM_DEBUG("ch%d class=0x%04x\n", chan->id, class); - ret = nouveau_gpuobj_new(dev, channel, + ret = nouveau_gpuobj_new(dev, chan, nouveau_gpuobj_class_instmem_size(dev, class), 16, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, @@ -847,14 +839,14 @@ nouveau_gpuobj_gr_new(struct drm_device *dev, int channel, int class, } static int -nouveau_gpuobj_channel_init_pramin(struct drm_device *dev, int channel) +nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; struct nouveau_gpuobj *pramin = NULL; int size, base, ret; - DRM_DEBUG("ch%d\n", channel); + DRM_DEBUG("ch%d\n", chan->id); /* Base amount for object storage (4KiB enough?) */ size = 0x1000; @@ -876,8 +868,8 @@ nouveau_gpuobj_channel_init_pramin(struct drm_device *dev, int channel) } DRM_DEBUG("ch%d PRAMIN size: 0x%08x bytes, base alloc=0x%08x\n", - channel, size, base); - ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, size, 0x1000, 0, + chan->id, size, base); + ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, size, 0x1000, 0, &chan->ramin); if (ret) { DRM_ERROR("Error allocating channel PRAMIN: %d\n", ret); @@ -897,21 +889,21 @@ nouveau_gpuobj_channel_init_pramin(struct drm_device *dev, int channel) } int -nouveau_gpuobj_channel_init(struct drm_device *dev, int channel, +nouveau_gpuobj_channel_init(struct nouveau_channel *chan, uint32_t vram_h, uint32_t tt_h) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; struct nouveau_gpuobj *vram = NULL, *tt = NULL; int ret, i; - DRM_DEBUG("ch%d vram=0x%08x tt=0x%08x\n", channel, vram_h, tt_h); + DRM_DEBUG("ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h); /* Reserve a block of PRAMIN for the channel *XXX: maybe on card_type == NV_50) { - ret = nouveau_gpuobj_channel_init_pramin(dev, channel); + ret = nouveau_gpuobj_channel_init_pramin(chan); if (ret) return ret; } @@ -930,7 +922,7 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel, INSTANCE_WR(chan->vm_pd, (i+4)/4, 0xdeadcafe); } - if ((ret = nouveau_gpuobj_ref_add(dev, -1, 0, + if ((ret = nouveau_gpuobj_ref_add(dev, NULL, 0, dev_priv->gart_info.sg_ctxdma, &chan->vm_gart_pt))) return ret; @@ -941,12 +933,12 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel, /* RAMHT */ if (dev_priv->card_type < NV_50) { - ret = nouveau_gpuobj_ref_add(dev, -1, 0, dev_priv->ramht, + ret = nouveau_gpuobj_ref_add(dev, NULL, 0, dev_priv->ramht, &chan->ramht); if (ret) return ret; } else { - ret = nouveau_gpuobj_new_ref(dev, channel, channel, 0, + ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 0x8000, 16, NVOBJ_FLAG_ZERO_ALLOC, &chan->ramht); @@ -955,7 +947,7 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel, } /* VRAM ctxdma */ - if ((ret = nouveau_gpuobj_dma_new(dev, channel, NV_CLASS_DMA_IN_MEMORY, + if ((ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0, dev_priv->fb_available_size, NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM, &vram))) { @@ -963,20 +955,19 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel, return ret; } - if ((ret = nouveau_gpuobj_ref_add(dev, channel, vram_h, vram, NULL))) { + if ((ret = nouveau_gpuobj_ref_add(dev, chan, vram_h, vram, NULL))) { DRM_ERROR("Error referencing VRAM ctxdma: %d\n", ret); return ret; } /* TT memory ctxdma */ if (dev_priv->gart_info.type != NOUVEAU_GART_NONE) { - ret = nouveau_gpuobj_gart_dma_new(dev, channel, 0, + ret = nouveau_gpuobj_gart_dma_new(chan, 0, dev_priv->gart_info.aper_size, NV_DMA_ACCESS_RW, &tt, NULL); } else if (dev_priv->pci_heap) { - ret = nouveau_gpuobj_dma_new(dev, channel, - NV_CLASS_DMA_IN_MEMORY, + ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0, dev->sg->pages * PAGE_SIZE, NV_DMA_ACCESS_RW, NV_DMA_TARGET_PCI_NONLINEAR, &tt); @@ -990,7 +981,7 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel, return ret; } - ret = nouveau_gpuobj_ref_add(dev, channel, tt_h, tt, NULL); + ret = nouveau_gpuobj_ref_add(dev, chan, tt_h, tt, NULL); if (ret) { DRM_ERROR("Error referencing TT ctxdma: %d\n", ret); return ret; @@ -1000,13 +991,12 @@ nouveau_gpuobj_channel_init(struct drm_device *dev, int channel, } void -nouveau_gpuobj_channel_takedown(struct drm_device *dev, int channel) +nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; + struct drm_device *dev = chan->dev; struct nouveau_gpuobj_ref *ref; - DRM_DEBUG("ch%d\n", channel); + DRM_DEBUG("ch%d\n", chan->id); while ((ref = chan->ramht_refs)) { chan->ramht_refs = ref->next; @@ -1024,35 +1014,33 @@ nouveau_gpuobj_channel_takedown(struct drm_device *dev, int channel) } -int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) +int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data, + struct drm_file *file_priv) { + struct nouveau_channel *chan; struct drm_nouveau_grobj_alloc *init = data; struct nouveau_gpuobj *gr = NULL; int ret; - if (!nouveau_fifo_owner(dev, file_priv, init->channel)) { - DRM_ERROR("pid %d doesn't own channel %d\n", - DRM_CURRENTPID, init->channel); - return -EINVAL; - } + NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(init->channel, file_priv, chan); //FIXME: check args, only allow trusted objects to be created if (init->handle == ~0) return -EINVAL; - if (nouveau_gpuobj_ref_find(dev, init->channel, init->handle, NULL) == + + if (nouveau_gpuobj_ref_find(chan, init->handle, NULL) == 0) return -EEXIST; - ret = nouveau_gpuobj_gr_new(dev, init->channel, init->class, &gr); + ret = nouveau_gpuobj_gr_new(chan, init->class, &gr); if (ret) { DRM_ERROR("Error creating gr object: %d (%d/0x%08x)\n", ret, init->channel, init->handle); return ret; } - if ((ret = nouveau_gpuobj_ref_add(dev, init->channel, init->handle, - gr, NULL))) { + if ((ret = nouveau_gpuobj_ref_add(dev, chan, init->handle, gr, NULL))) { DRM_ERROR("Error referencing gr object: %d (%d/0x%08x\n)", ret, init->channel, init->handle); nouveau_gpuobj_del(dev, &gr); diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index f45f2783..26ba8fbf 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -93,7 +93,7 @@ static uint64_t nouveau_stub_timer_read(struct drm_device *dev) { return 0; } static int nouveau_init_engine_ptrs(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine_func *engine = &dev_priv->Engine; + struct nouveau_engine *engine = &dev_priv->Engine; switch (dev_priv->chipset & 0xf0) { case 0x00: @@ -270,7 +270,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) static int nouveau_card_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine_func *engine; + struct nouveau_engine *engine; int ret; /* Map any PCI resources we need on the card */ @@ -332,7 +332,7 @@ static int nouveau_card_init(struct drm_device *dev) static void nouveau_card_takedown(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_engine_func *engine = &dev_priv->Engine; + struct nouveau_engine *engine = &dev_priv->Engine; if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) { engine->fifo.takedown(dev); @@ -526,6 +526,7 @@ void nouveau_wait_for_idle(struct drm_device *dev) uint32_t status; do { uint32_t pmc_e = NV_READ(NV03_PMC_ENABLE); + (void)pmc_e; status = NV_READ(NV04_PGRAPH_STATUS); if (!status) break; diff --git a/shared-core/nv04_fifo.c b/shared-core/nv04_fifo.c index 564efd0b..4d61f4fe 100644 --- a/shared-core/nv04_fifo.c +++ b/shared-core/nv04_fifo.c @@ -36,13 +36,13 @@ #define NV04_RAMFC__SIZE 32 int -nv04_fifo_create_context(struct drm_device *dev, int channel) +nv04_fifo_create_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; int ret; - if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(channel), + if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), NV04_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, @@ -62,30 +62,29 @@ nv04_fifo_create_context(struct drm_device *dev, int channel) 0)); /* enable the fifo dma operation */ - NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<id)); return 0; } void -nv04_fifo_destroy_context(struct drm_device *dev, int channel) +nv04_fifo_destroy_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; - - NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<id)); - if (chan->ramfc) - nouveau_gpuobj_ref_del(dev, &chan->ramfc); + nouveau_gpuobj_ref_del(dev, &chan->ramfc); } int -nv04_fifo_load_context(struct drm_device *dev, int channel) +nv04_fifo_load_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; - NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, (1<<8) | channel); + NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, (1<<8) | chan->id); NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET)); NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT)); @@ -107,10 +106,10 @@ nv04_fifo_load_context(struct drm_device *dev, int channel) } int -nv04_fifo_save_context(struct drm_device *dev, int channel) +nv04_fifo_save_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; RAMFC_WR(DMA_PUT, NV04_PFIFO_CACHE1_DMA_PUT); diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c index e35e3071..b2ea7804 100644 --- a/shared-core/nv04_graph.c +++ b/shared-core/nv04_graph.c @@ -336,14 +336,13 @@ void nouveau_nv04_context_switch(struct drm_device *dev) NV_WRITE(NV04_PGRAPH_FIFO,0x1); } -int nv04_graph_create_context(struct drm_device *dev, int channel) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - DRM_DEBUG("nv04_graph_context_create %d\n", channel); +int nv04_graph_create_context(struct nouveau_channel *chan) { + DRM_DEBUG("nv04_graph_context_create %d\n", chan->id); - memset(dev_priv->fifos[channel]->pgraph_ctx, 0, sizeof(dev_priv->fifos[channel]->pgraph_ctx)); + memset(chan->pgraph_ctx, 0, sizeof(chan->pgraph_ctx)); //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; - dev_priv->fifos[channel]->pgraph_ctx[0] = 0x0001ffff; + chan->pgraph_ctx[0] = 0x0001ffff; /* is it really needed ??? */ //dev_priv->fifos[channel].pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4); //dev_priv->fifos[channel].pgraph_ctx[2] = NV_READ(0x004006b0); @@ -351,17 +350,17 @@ int nv04_graph_create_context(struct drm_device *dev, int channel) { return 0; } -void nv04_graph_destroy_context(struct drm_device *dev, int channel) +void nv04_graph_destroy_context(struct nouveau_channel *chan) { } -int nv04_graph_load_context(struct drm_device *dev, int channel) +int nv04_graph_load_context(struct nouveau_channel *chan) { DRM_ERROR("stub!\n"); return 0; } -int nv04_graph_save_context(struct drm_device *dev, int channel) +int nv04_graph_save_context(struct nouveau_channel *chan) { DRM_ERROR("stub!\n"); return 0; diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c index 7b9c665b..47af0ff0 100644 --- a/shared-core/nv10_fifo.c +++ b/shared-core/nv10_fifo.c @@ -37,13 +37,13 @@ #define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32) int -nv10_fifo_create_context(struct drm_device *dev, int channel) +nv10_fifo_create_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; int ret; - if ((ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(channel), + if ((ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id), NV10_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, @@ -65,30 +65,29 @@ nv10_fifo_create_context(struct drm_device *dev, int channel) 0); /* enable the fifo dma operation */ - NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<id)); return 0; } void -nv10_fifo_destroy_context(struct drm_device *dev, int channel) +nv10_fifo_destroy_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; - NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<id)); - if (chan->ramfc) - nouveau_gpuobj_ref_del(dev, &chan->ramfc); + nouveau_gpuobj_ref_del(dev, &chan->ramfc); } int -nv10_fifo_load_context(struct drm_device *dev, int channel) +nv10_fifo_load_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; - NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00000100 | channel); + NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00000100 | chan->id); NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET)); NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT , RAMFC_RD(DMA_PUT)); @@ -124,10 +123,10 @@ nv10_fifo_load_context(struct drm_device *dev, int channel) } int -nv10_fifo_save_context(struct drm_device *dev, int channel) +nv10_fifo_save_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index ce1cbfa7..a2df2d71 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -544,33 +544,33 @@ static int nv10_graph_ctx_regs_find_offset(struct drm_device *dev, int reg) return -1; } -int nv10_graph_load_context(struct drm_device *dev, int channel) +int nv10_graph_load_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *fifo = dev_priv->fifos[channel]; int i, j; for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) - NV_WRITE(nv10_graph_ctx_regs[i], fifo->pgraph_ctx[i]); + NV_WRITE(nv10_graph_ctx_regs[i], chan->pgraph_ctx[i]); if (dev_priv->chipset>=0x17) { for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) - NV_WRITE(nv17_graph_ctx_regs[j], fifo->pgraph_ctx[i]); + NV_WRITE(nv17_graph_ctx_regs[j], chan->pgraph_ctx[i]); } return 0; } -int nv10_graph_save_context(struct drm_device *dev, int channel) +int nv10_graph_save_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *fifo = dev_priv->fifos[channel]; int i, j; for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) - fifo->pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); + chan->pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); if (dev_priv->chipset>=0x17) { for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) - fifo->pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); + chan->pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); } return 0; @@ -579,12 +579,17 @@ int nv10_graph_save_context(struct drm_device *dev, int channel) void nouveau_nv10_context_switch(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - int channel, channel_old; + struct nouveau_channel *next, *last; + int chid; - channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); - channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); + next = dev_priv->fifos[chid]; - DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel); + chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + last = dev_priv->fifos[chid]; + + DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n", + last->id, next->id); NV_WRITE(NV04_PGRAPH_FIFO,0x0); #if 0 @@ -592,7 +597,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev) NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000); NV_WRITE(NV_PFIFO_CACHES, 0x00000000); #endif - nv10_graph_save_context(dev, channel_old); + nv10_graph_save_context(last); nouveau_wait_for_idle(dev); @@ -601,10 +606,10 @@ void nouveau_nv10_context_switch(struct drm_device *dev) nouveau_wait_for_idle(dev); - nv10_graph_load_context(dev, channel); + nv10_graph_load_context(next); NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100); - NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24); + NV_WRITE(NV10_PGRAPH_CTX_USER, next->id << 24); NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); #if 0 NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); @@ -617,17 +622,17 @@ void nouveau_nv10_context_switch(struct drm_device *dev) #define NV_WRITE_CTX(reg, val) do { \ int offset = nv10_graph_ctx_regs_find_offset(dev, reg); \ if (offset > 0) \ - fifo->pgraph_ctx[offset] = val; \ + chan->pgraph_ctx[offset] = val; \ } while (0) -int nv10_graph_create_context(struct drm_device *dev, int channel) { +int nv10_graph_create_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *fifo = dev_priv->fifos[channel]; uint32_t tmp, vramsz; - DRM_DEBUG("nv10_graph_context_create %d\n", channel); + DRM_DEBUG("nv10_graph_context_create %d\n", chan->id); - memset(fifo->pgraph_ctx, 0, sizeof(fifo->pgraph_ctx)); + memset(chan->pgraph_ctx, 0, sizeof(chan->pgraph_ctx)); /* per channel init from ddx */ tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; @@ -663,7 +668,7 @@ int nv10_graph_create_context(struct drm_device *dev, int channel) { /* for the first channel init the regs */ if (dev_priv->fifo_alloc_count == 0) - nv10_graph_load_context(dev, channel); + nv10_graph_load_context(chan); //XXX should be saved/restored for each fifo @@ -672,7 +677,7 @@ int nv10_graph_create_context(struct drm_device *dev, int channel) { return 0; } -void nv10_graph_destroy_context(struct drm_device *dev, int channel) +void nv10_graph_destroy_context(struct nouveau_channel *chan) { } diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 1670c527..d397390f 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -29,39 +29,36 @@ #define NV20_GRCTX_SIZE (3529*4) -int nv20_graph_create_context(struct drm_device *dev, int channel) { - struct drm_nouveau_private *dev_priv = - (struct drm_nouveau_private *)dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; +int nv20_graph_create_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; unsigned int ctx_size = NV20_GRCTX_SIZE; int ret; - if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, ctx_size, 16, + if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16, NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx))) return ret; /* Initialise default context values */ - INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, channel<<24); /* CTX_USER */ + INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); /* CTX_USER */ - INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, + INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, chan->ramin_grctx->instance >> 4); return 0; } -void nv20_graph_destroy_context(struct drm_device *dev, int channel) { +void nv20_graph_destroy_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; - if (chan->ramin_grctx) - nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); + nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); - INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, 0); + INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0); } static void nv20_graph_rdi(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = - (struct drm_nouveau_private *)dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int i; NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000); @@ -73,13 +70,12 @@ static void nv20_graph_rdi(struct drm_device *dev) { /* Save current context (from PGRAPH) into the channel's context */ -int nv20_graph_save_context(struct drm_device *dev, int channel) { - struct drm_nouveau_private *dev_priv = - (struct drm_nouveau_private *)dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; +int nv20_graph_save_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t instance; - instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel); + instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, chan->id); if (!instance) { return -EINVAL; } @@ -94,20 +90,19 @@ int nv20_graph_save_context(struct drm_device *dev, int channel) { /* Restore the context for a specific channel into PGRAPH */ -int nv20_graph_load_context(struct drm_device *dev, int channel) { - struct drm_nouveau_private *dev_priv = - (struct drm_nouveau_private *)dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; +int nv20_graph_load_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t instance; - instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel); + instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, chan->id); if (!instance) { return -EINVAL; } if (instance != (chan->ramin_grctx->instance >> 4)) DRM_ERROR("nv20_graph_load_context_current : bad instance\n"); - NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24); + NV_WRITE(NV10_PGRAPH_CTX_USER, chan->id << 24); NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance); NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 1 /* restore ctx */); return 0; @@ -116,27 +111,32 @@ int nv20_graph_load_context(struct drm_device *dev, int channel) { void nouveau_nv20_context_switch(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - int channel, channel_old; + struct nouveau_channel *next, *last; + int chid; + + chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); + next = dev_priv->fifos[chid]; - channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); - channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + last = dev_priv->fifos[chid]; - DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel); + DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n", + last->id, next->id); NV_WRITE(NV04_PGRAPH_FIFO,0x0); - nv20_graph_save_context(dev, channel_old); + nv20_graph_save_context(last); nouveau_wait_for_idle(dev); NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000000); - nv20_graph_load_context(dev, channel); + nv20_graph_load_context(next); nouveau_wait_for_idle(dev); - if ((NV_READ(NV10_PGRAPH_CTX_USER) >> 24) != channel) - DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", channel, NV_READ(NV10_PGRAPH_CTX_USER) >> 24); + if ((NV_READ(NV10_PGRAPH_CTX_USER) >> 24) != next->id) + DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", next->id, NV_READ(NV10_PGRAPH_CTX_USER) >> 24); NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100); NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); @@ -157,7 +157,7 @@ int nv20_graph_init(struct drm_device *dev) { /* Create Context Pointer Table */ dev_priv->ctx_table_size = 32 * 4; - if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, + if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, dev_priv->ctx_table_size, 16, NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ctx_table))) diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index 4ed2e2ba..c605c84e 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -100,11 +100,10 @@ static void nv30_graph_context_init(struct drm_device *dev, struct nouveau_gpuob } -int nv30_graph_create_context(struct drm_device *dev, int channel) +int nv30_graph_create_context(struct nouveau_channel *chan) { - struct drm_nouveau_private *dev_priv = - (struct drm_nouveau_private *)dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *); unsigned int ctx_size; int ret; @@ -116,7 +115,7 @@ int nv30_graph_create_context(struct drm_device *dev, int channel) break; } - if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, ctx_size, 16, + if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16, NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx))) return ret; @@ -124,23 +123,22 @@ int nv30_graph_create_context(struct drm_device *dev, int channel) /* Initialise default context values */ ctx_init(dev, chan->ramin_grctx->gpuobj); - INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, channel<<24); /* CTX_USER */ - INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, + INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); /* CTX_USER */ + INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, chan->ramin_grctx->instance >> 4); return 0; } -void nv30_graph_destroy_context(struct drm_device *dev, int channel) +void nv30_graph_destroy_context(struct nouveau_channel *chan) { - struct drm_nouveau_private *dev_priv = - (struct drm_nouveau_private *)dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; if (chan->ramin_grctx) nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); - INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, 0); + INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0); } static int @@ -161,10 +159,10 @@ nouveau_graph_wait_idle(struct drm_device *dev) return 0; } -int nv30_graph_load_context(struct drm_device *dev, int channel) +int nv30_graph_load_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t inst; if (!chan->ramin_grctx) @@ -178,10 +176,10 @@ int nv30_graph_load_context(struct drm_device *dev, int channel) return nouveau_graph_wait_idle(dev); } -int nv30_graph_save_context(struct drm_device *dev, int channel) +int nv30_graph_save_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t inst; if (!chan->ramin_grctx) @@ -197,8 +195,7 @@ int nv30_graph_save_context(struct drm_device *dev, int channel) int nv30_graph_init(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = - (struct drm_nouveau_private *)dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t vramsz, tmp; int ret, i; @@ -209,7 +206,7 @@ int nv30_graph_init(struct drm_device *dev) /* Create Context Pointer Table */ dev_priv->ctx_table_size = 32 * 4; - if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, + if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, dev_priv->ctx_table_size, 16, NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ctx_table))) diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c index ecb1d21e..f04c2882 100644 --- a/shared-core/nv40_fifo.c +++ b/shared-core/nv40_fifo.c @@ -37,13 +37,13 @@ #define NV40_RAMFC__SIZE 128 int -nv40_fifo_create_context(struct drm_device *dev, int channel) +nv40_fifo_create_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; int ret; - if ((ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(channel), + if ((ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), NV40_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, @@ -68,27 +68,27 @@ nv40_fifo_create_context(struct drm_device *dev, int channel) RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF); /* enable the fifo dma operation */ - NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<id)); return 0; } void -nv40_fifo_destroy_context(struct drm_device *dev, int channel) +nv40_fifo_destroy_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; - NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<id)); if (chan->ramfc) nouveau_gpuobj_ref_del(dev, &chan->ramfc); } int -nv40_fifo_load_context(struct drm_device *dev, int channel) +nv40_fifo_load_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp, tmp2; NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET)); @@ -135,7 +135,7 @@ nv40_fifo_load_context(struct drm_device *dev, int channel) NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, tmp); /* Set channel active, and in DMA mode */ - NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00010000 | channel); + NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00010000 | chan->id); /* Reset DMA_CTL_AT_INFO to INVALID */ tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31); NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp); @@ -144,10 +144,10 @@ nv40_fifo_load_context(struct drm_device *dev, int channel) } int -nv40_fifo_save_context(struct drm_device *dev, int channel) +nv40_fifo_save_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index 441dbae7..c79b63cc 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -1224,11 +1224,10 @@ nv4e_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) } int -nv40_graph_create_context(struct drm_device *dev, int channel) +nv40_graph_create_context(struct nouveau_channel *chan) { - struct drm_nouveau_private *dev_priv = - (struct drm_nouveau_private *)dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *); unsigned int ctx_size; int ret; @@ -1272,7 +1271,7 @@ nv40_graph_create_context(struct drm_device *dev, int channel) break; } - if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, ctx_size, 16, + if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16, NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx))) return ret; @@ -1284,13 +1283,9 @@ nv40_graph_create_context(struct drm_device *dev, int channel) } void -nv40_graph_destroy_context(struct drm_device *dev, int channel) +nv40_graph_destroy_context(struct nouveau_channel *chan) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; - - if (chan->ramin_grctx) - nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); + nouveau_gpuobj_ref_del(chan->dev, &chan->ramin_grctx); } static int @@ -1327,10 +1322,9 @@ nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save) *XXX: fails sometimes, not sure why.. */ int -nv40_graph_save_context(struct drm_device *dev, int channel) +nv40_graph_save_context(struct nouveau_channel *chan) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; + struct drm_device *dev = chan->dev; uint32_t inst; if (!chan->ramin_grctx) @@ -1344,10 +1338,10 @@ nv40_graph_save_context(struct drm_device *dev, int channel) * XXX: fails sometimes.. not sure why */ int -nv40_graph_load_context(struct drm_device *dev, int channel) +nv40_graph_load_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t inst; int ret; diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index f7b98220..a5e79260 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -63,7 +63,7 @@ static int nv50_fifo_channel_enable(struct drm_device *dev, int channel) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; + struct nouveau_channel *chan = dev_priv->fifos[channel]; DRM_DEBUG("ch%d\n", channel); @@ -150,7 +150,7 @@ nv50_fifo_init_regs(struct drm_device *dev) DRM_DEBUG("\n"); - if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, 0x1000, + if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 0x1000, 0x1000, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, @@ -191,7 +191,7 @@ nv50_fifo_init(struct drm_device *dev) nv50_fifo_init_reset(dev); - if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, (128+2)*4, 0x1000, + if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, (128+2)*4, 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->thingo))) { DRM_ERROR("error creating thingo: %d\n", ret); @@ -225,14 +225,14 @@ nv50_fifo_takedown(struct drm_device *dev) } int -nv50_fifo_create_context(struct drm_device *dev, int channel) +nv50_fifo_create_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; struct nouveau_gpuobj *ramfc = NULL; int ret; - DRM_DEBUG("ch%d\n", channel); + DRM_DEBUG("ch%d\n", chan->id); if (IS_G80) { uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start; @@ -242,7 +242,7 @@ nv50_fifo_create_context(struct drm_device *dev, int channel) &ramfc, &chan->ramfc))) return ret; } else { - if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, 0x100, + if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 0x100, 256, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, @@ -266,15 +266,15 @@ nv50_fifo_create_context(struct drm_device *dev, int channel) INSTANCE_WR(ramfc, 0x4c/4, chan->pushbuf_mem->size - 1); if (!IS_G80) { - INSTANCE_WR(chan->ramin->gpuobj, 0, channel); + INSTANCE_WR(chan->ramin->gpuobj, 0, chan->id); INSTANCE_WR(chan->ramin->gpuobj, 1, chan->ramfc->instance); INSTANCE_WR(ramfc, 0x88/4, 0x3d520); /* some vram addy >> 10 */ INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12); } - if ((ret = nv50_fifo_channel_enable(dev, channel))) { - DRM_ERROR("error enabling ch%d: %d\n", channel, ret); + if ((ret = nv50_fifo_channel_enable(dev, chan->id))) { + DRM_ERROR("error enabling ch%d: %d\n", chan->id, ret); nouveau_gpuobj_ref_del(dev, &chan->ramfc); return ret; } @@ -283,25 +283,24 @@ nv50_fifo_create_context(struct drm_device *dev, int channel) } void -nv50_fifo_destroy_context(struct drm_device *dev, int channel) +nv50_fifo_destroy_context(struct nouveau_channel *chan) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; + struct drm_device *dev = chan->dev; - DRM_DEBUG("ch%d\n", channel); + DRM_DEBUG("ch%d\n", chan->id); - nv50_fifo_channel_disable(dev, channel, 0); + nv50_fifo_channel_disable(dev, chan->id, 0); nouveau_gpuobj_ref_del(dev, &chan->ramfc); } int -nv50_fifo_load_context(struct drm_device *dev, int channel) +nv50_fifo_load_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; struct nouveau_gpuobj *ramfc = chan->ramfc->gpuobj; - DRM_DEBUG("ch%d\n", channel); + DRM_DEBUG("ch%d\n", chan->id); /*XXX: incomplete, only touches the regs that NV does */ @@ -319,14 +318,14 @@ nv50_fifo_load_context(struct drm_device *dev, int channel) NV_WRITE(0x3410, INSTANCE_RD(ramfc, 0x98/4)); } - NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, channel | (1<<16)); + NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16)); return 0; } int -nv50_fifo_save_context(struct drm_device *dev, int channel) +nv50_fifo_save_context(struct nouveau_channel *chan) { - DRM_DEBUG("ch%d\n", channel); + DRM_DEBUG("ch%d\n", chan->id); DRM_ERROR("stub!\n"); return 0; } diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c index 8df5df25..59c8cfeb 100644 --- a/shared-core/nv50_graph.c +++ b/shared-core/nv50_graph.c @@ -188,17 +188,17 @@ nv50_graph_takedown(struct drm_device *dev) } int -nv50_graph_create_context(struct drm_device *dev, int channel) +nv50_graph_create_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; struct nouveau_gpuobj *ramin = chan->ramin->gpuobj; int grctx_size = 0x60000, hdr; int ret; - DRM_DEBUG("ch%d\n", channel); + DRM_DEBUG("ch%d\n", chan->id); - if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, + if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, grctx_size, 0x1000, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, @@ -218,13 +218,13 @@ nv50_graph_create_context(struct drm_device *dev, int channel) } void -nv50_graph_destroy_context(struct drm_device *dev, int channel) +nv50_graph_destroy_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; int i, hdr; - DRM_DEBUG("ch%d\n", channel); + DRM_DEBUG("ch%d\n", chan->id); hdr = IS_G80 ? 0x200 : 0x20; for (i=hdr; idev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t inst = ((chan->ramin->instance >> 12) | (1<<31)); int ret; (void)ret; - DRM_DEBUG("ch%d\n", channel); + DRM_DEBUG("ch%d\n", chan->id); #if 0 if ((ret = nv50_graph_transfer_context(dev, inst, 0))) @@ -288,13 +288,12 @@ nv50_graph_load_context(struct drm_device *dev, int channel) } int -nv50_graph_save_context(struct drm_device *dev, int channel) +nv50_graph_save_context(struct nouveau_channel *chan) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; + struct drm_device *dev = chan->dev; uint32_t inst = ((chan->ramin->instance >> 12) | (1<<31)); - DRM_DEBUG("ch%d\n", channel); + DRM_DEBUG("ch%d\n", chan->id); return nv50_graph_transfer_context(dev, inst, 1); } -- cgit v1.2.3 From 97770db72040dc032130413e0cdabc1777560a75 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 6 Aug 2007 21:45:18 +1000 Subject: nouveau: Various internal and external API changes 1. DRM_NOUVEAU_GPUOBJ_FREE Used to free GPU objects. The obvious usage case is for Gr objects, but notifiers can also be destroyed in the same way. GPU objects gain a destructor method and private data fields with this change, so other specialised cases (like notifiers) can be implemented on top of gpuobjs. 2. DRM_NOUVEAU_CHANNEL_FREE 3. DRM_NOUVEAU_CARD_INIT Ideally we'd do init during module load, but this isn't currently possible. Doing init during firstopen() is bad as X has a love of opening/closing the DRM many times during startup. Once the modesetting-101 branch is merged this can go away. IRQs are enabled in nouveau_card_init() now, rather than having the X server call drmCtlInstHandler(). We'll need this for when we give the kernel module its own channel. 4. DRM_NOUVEAU_GETPARAM Add CHIPSET_ID value, which will return the chipset id derived from NV_PMC_BOOT_0. 4. Use list_* in a few places, rather than home-brewed stuff. --- shared-core/nouveau_drm.h | 33 +++++++++----- shared-core/nouveau_drv.h | 30 ++++++++++--- shared-core/nouveau_fifo.c | 47 ++++++++++++++------ shared-core/nouveau_mem.c | 8 ++-- shared-core/nouveau_notifier.c | 17 +++++++- shared-core/nouveau_object.c | 99 +++++++++++++++++++++++++++++++----------- shared-core/nouveau_state.c | 45 +++++++++++-------- shared-core/nv04_instmem.c | 10 ----- 8 files changed, 199 insertions(+), 90 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h index 4016f004..bfc9bd4b 100644 --- a/shared-core/nouveau_drm.h +++ b/shared-core/nouveau_drm.h @@ -25,9 +25,9 @@ #ifndef __NOUVEAU_DRM_H__ #define __NOUVEAU_DRM_H__ -#define NOUVEAU_DRM_HEADER_PATCHLEVEL 9 +#define NOUVEAU_DRM_HEADER_PATCHLEVEL 10 -struct drm_nouveau_fifo_alloc { +struct drm_nouveau_channel_alloc { uint32_t fb_ctxdma_handle; uint32_t tt_ctxdma_handle; @@ -44,6 +44,10 @@ struct drm_nouveau_fifo_alloc { int notifier_size; }; +struct drm_nouveau_channel_free { + int channel; +}; + struct drm_nouveau_grobj_alloc { int channel; uint32_t handle; @@ -53,7 +57,7 @@ struct drm_nouveau_grobj_alloc { #define NOUVEAU_MEM_ACCESS_RO 1 #define NOUVEAU_MEM_ACCESS_WO 2 #define NOUVEAU_MEM_ACCESS_RW 3 -struct drm_nouveau_notifier_alloc { +struct drm_nouveau_notifierobj_alloc { int channel; uint32_t handle; int count; @@ -61,6 +65,11 @@ struct drm_nouveau_notifier_alloc { uint32_t offset; }; +struct drm_nouveau_gpuobj_free { + int channel; + uint32_t handle; +}; + #define NOUVEAU_MEM_FB 0x00000001 #define NOUVEAU_MEM_AGP 0x00000002 #define NOUVEAU_MEM_FB_ACCEPTABLE 0x00000004 @@ -95,6 +104,7 @@ struct drm_nouveau_mem_free { #define NOUVEAU_GETPARAM_FB_SIZE 8 #define NOUVEAU_GETPARAM_AGP_SIZE 9 #define NOUVEAU_GETPARAM_PCI_PHYSICAL 10 +#define NOUVEAU_GETPARAM_CHIPSET_ID 11 struct drm_nouveau_getparam { uint64_t param; uint64_t value; @@ -141,13 +151,16 @@ struct drm_nouveau_sarea { unsigned int nbox; }; -#define DRM_NOUVEAU_FIFO_ALLOC 0x00 -#define DRM_NOUVEAU_GROBJ_ALLOC 0x01 -#define DRM_NOUVEAU_NOTIFIER_ALLOC 0x02 -#define DRM_NOUVEAU_MEM_ALLOC 0x03 -#define DRM_NOUVEAU_MEM_FREE 0x04 -#define DRM_NOUVEAU_GETPARAM 0x05 -#define DRM_NOUVEAU_SETPARAM 0x06 +#define DRM_NOUVEAU_CARD_INIT 0x00 +#define DRM_NOUVEAU_GETPARAM 0x01 +#define DRM_NOUVEAU_SETPARAM 0x02 +#define DRM_NOUVEAU_CHANNEL_ALLOC 0x03 +#define DRM_NOUVEAU_CHANNEL_FREE 0x04 +#define DRM_NOUVEAU_GROBJ_ALLOC 0x05 +#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x06 +#define DRM_NOUVEAU_GPUOBJ_FREE 0x07 +#define DRM_NOUVEAU_MEM_ALLOC 0x08 +#define DRM_NOUVEAU_MEM_FREE 0x09 #endif /* __NOUVEAU_DRM_H__ */ diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 8ec91898..0b173b76 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -34,7 +34,7 @@ #define DRIVER_MAJOR 0 #define DRIVER_MINOR 0 -#define DRIVER_PATCHLEVEL 9 +#define DRIVER_PATCHLEVEL 10 #define NOUVEAU_FAMILY 0x0000FFFF #define NOUVEAU_FLAGS 0xFFFF0000 @@ -67,8 +67,7 @@ enum nouveau_flags { #define NVOBJ_FLAG_ZERO_FREE (1 << 2) #define NVOBJ_FLAG_FAKE (1 << 3) struct nouveau_gpuobj { - struct nouveau_gpuobj *next; - struct nouveau_gpuobj *prev; + struct list_head list; int im_channel; struct mem_block *im_pramin; @@ -80,10 +79,13 @@ struct nouveau_gpuobj { uint32_t engine; uint32_t class; + + void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); + void *priv; }; struct nouveau_gpuobj_ref { - struct nouveau_gpuobj_ref *next; + struct list_head list; struct nouveau_gpuobj *gpuobj; uint32_t instance; @@ -129,7 +131,7 @@ struct nouveau_channel struct nouveau_gpuobj_ref *ramin; /* Private instmem */ struct mem_block *ramin_heap; /* Private PRAMIN heap */ struct nouveau_gpuobj_ref *ramht; /* Hash table */ - struct nouveau_gpuobj_ref *ramht_refs; /* Objects referenced by RAMHT */ + struct list_head ramht_refs; /* Objects referenced by RAMHT */ }; struct nouveau_config { @@ -269,9 +271,17 @@ struct drm_nouveau_private { struct nouveau_config config; - struct nouveau_gpuobj *gpuobj_all; + struct list_head gpuobj_list; }; +#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \ + struct drm_nouveau_private *nv = dev->dev_private; \ + if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \ + DRM_ERROR("called without init\n"); \ + return -EINVAL; \ + } \ +} while(0) + #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id,cl,ch) do { \ struct drm_nouveau_private *nv = dev->dev_private; \ if (!nouveau_fifo_owner(dev, (cl), (id))) { \ @@ -293,6 +303,7 @@ extern int nouveau_ioctl_getparam(struct drm_device *, void *data, extern int nouveau_ioctl_setparam(struct drm_device *, void *data, struct drm_file *); extern void nouveau_wait_for_idle(struct drm_device *); +extern int nouveau_card_init(struct drm_device *); extern int nouveau_ioctl_card_init(struct drm_device *, void *data, struct drm_file *); @@ -324,6 +335,8 @@ extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, int cout, uint32_t *offset); extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, struct drm_file *); +extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, + struct drm_file *); /* nouveau_fifo.c */ extern int nouveau_fifo_init(struct drm_device *); @@ -335,6 +348,7 @@ extern int nouveau_fifo_owner(struct drm_device *, struct drm_file *, extern void nouveau_fifo_free(struct nouveau_channel *); /* nouveau_object.c */ +extern int nouveau_gpuobj_init(struct drm_device *); extern void nouveau_gpuobj_takedown(struct drm_device *); extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, uint32_t vram_h, uint32_t tt_h); @@ -348,6 +362,8 @@ extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *, struct nouveau_gpuobj_ref **); extern int nouveau_gpuobj_ref_del(struct drm_device *, struct nouveau_gpuobj_ref **); +extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle, + struct nouveau_gpuobj_ref **ref_ret); extern int nouveau_gpuobj_new_ref(struct drm_device *, struct nouveau_channel *alloc_chan, struct nouveau_channel *ref_chan, @@ -368,6 +384,8 @@ extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, struct nouveau_gpuobj **); extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, struct drm_file *); +extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, + struct drm_file *); /* nouveau_irq.c */ extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index c7ce1d8d..152b669a 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -302,22 +302,22 @@ int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret, DRM_INFO("Allocating FIFO number %d\n", channel); - /* Setup channel's default objects */ - ret = nouveau_gpuobj_channel_init(chan, vram_handle, tt_handle); + /* Allocate space for per-channel fixed notifier memory */ + ret = nouveau_notifier_init_channel(chan); if (ret) { nouveau_fifo_free(chan); return ret; } - /* allocate a command buffer, and create a dma object for the gpu */ - ret = nouveau_fifo_cmdbuf_alloc(chan); + /* Setup channel's default objects */ + ret = nouveau_gpuobj_channel_init(chan, vram_handle, tt_handle); if (ret) { nouveau_fifo_free(chan); return ret; } - /* Allocate space for per-channel fixed notifier memory */ - ret = nouveau_notifier_init_channel(chan); + /* allocate a command buffer, and create a dma object for the gpu */ + ret = nouveau_fifo_cmdbuf_alloc(chan); if (ret) { nouveau_fifo_free(chan); return ret; @@ -426,11 +426,11 @@ void nouveau_fifo_free(struct nouveau_channel *chan) chan->pushbuf_mem = NULL; } - nouveau_notifier_takedown_channel(chan); - /* Destroy objects belonging to the channel */ nouveau_gpuobj_channel_takedown(chan); + nouveau_notifier_takedown_channel(chan); + dev_priv->fifos[chan->id] = NULL; dev_priv->fifo_alloc_count--; drm_free(chan, sizeof(*chan), DRM_MEM_DRIVER); @@ -468,14 +468,17 @@ nouveau_fifo_owner(struct drm_device *dev, struct drm_file *file_priv, * ioctls wrapping the functions ***********************************/ -static int nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) +static int nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, + struct drm_file *file_priv) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct drm_nouveau_fifo_alloc *init = data; + struct drm_nouveau_channel_alloc *init = data; struct drm_map_list *entry; struct nouveau_channel *chan; int res; + NOUVEAU_CHECK_INITIALISED_WITH_RETURN; + if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0) return -EINVAL; @@ -519,18 +522,34 @@ static int nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, struct d return 0; } +static int nouveau_ioctl_fifo_free(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + struct drm_nouveau_channel_free *cfree = data; + struct nouveau_channel *chan; + + NOUVEAU_CHECK_INITIALISED_WITH_RETURN; + NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(cfree->channel, file_priv, chan); + + nouveau_fifo_free(chan); + return 0; +} + /*********************************** * finally, the ioctl table ***********************************/ struct drm_ioctl_desc nouveau_ioctls[] = { - DRM_IOCTL_DEF(DRM_NOUVEAU_FIFO_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH), + DRM_IOCTL_DEF(DRM_NOUVEAU_CARD_INIT, nouveau_ioctl_card_init, DRM_AUTH), + DRM_IOCTL_DEF(DRM_NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH), + DRM_IOCTL_DEF(DRM_NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH), + DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_NOTIFIER_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH), + DRM_IOCTL_DEF(DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH), + DRM_IOCTL_DEF(DRM_NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_MEM_ALLOC, nouveau_ioctl_mem_alloc, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_MEM_FREE, nouveau_ioctl_mem_free, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), }; int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls); diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index a7044c94..981af8a6 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -549,14 +549,10 @@ void nouveau_mem_free(struct drm_device* dev, struct mem_block* block) int nouveau_ioctl_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) { - struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_mem_alloc *alloc = data; struct mem_block *block; - if (!dev_priv) { - DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return -EINVAL; - } + NOUVEAU_CHECK_INITIALISED_WITH_RETURN; block=nouveau_mem_alloc(dev, alloc->alignment, alloc->size, alloc->flags, file_priv); @@ -575,6 +571,8 @@ int nouveau_ioctl_mem_free(struct drm_device *dev, void *data, struct drm_file * struct drm_nouveau_mem_free *memfree = data; struct mem_block *block; + NOUVEAU_CHECK_INITIALISED_WITH_RETURN; + block=NULL; if (memfree->flags & NOUVEAU_MEM_FB) block = find_block(dev_priv->fb_heap, memfree->offset); diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index b1090587..31547aae 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -73,6 +73,16 @@ nouveau_notifier_takedown_channel(struct nouveau_channel *chan) nouveau_mem_takedown(&chan->notifier_heap); } +static void +nouveau_notifier_gpuobj_dtor(struct drm_device *dev, + struct nouveau_gpuobj *gpuobj) +{ + DRM_DEBUG("\n"); + + if (gpuobj->priv) + nouveau_mem_free_block(gpuobj->priv); +} + int nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle, int count, uint32_t *b_offset) @@ -90,7 +100,7 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle, } mem = nouveau_mem_alloc_block(chan->notifier_heap, 32, 0, - chan->file_priv); + (struct drm_file *)-2); if (!mem) { DRM_ERROR("Channel %d notifier block full\n", chan->id); return -ENOMEM; @@ -117,6 +127,8 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle, DRM_ERROR("Error creating notifier ctxdma: %d\n", ret); return ret; } + nobj->dtor = nouveau_notifier_gpuobj_dtor; + nobj->priv = mem; if ((ret = nouveau_gpuobj_ref_add(dev, chan, handle, nobj, NULL))) { nouveau_gpuobj_del(dev, &nobj); @@ -133,10 +145,11 @@ int nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) { - struct drm_nouveau_notifier_alloc *na = data; + struct drm_nouveau_notifierobj_alloc *na = data; struct nouveau_channel *chan; int ret; + NOUVEAU_CHECK_INITIALISED_WITH_RETURN; NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(na->channel, file_priv, chan); ret = nouveau_notifier_alloc(chan, na->handle, na->count, &na->offset); diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 274bb2a7..22ad23cd 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -131,6 +131,8 @@ nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) ref->channel, co, ref->handle, ctx); INSTANCE_WR(ramht, (co + 0)/4, ref->handle); INSTANCE_WR(ramht, (co + 4)/4, ctx); + + list_add_tail(&ref->list, &chan->ramht_refs); return 0; } DRM_DEBUG("collision ch%d 0x%08x: h=0x%08x\n", @@ -167,6 +169,8 @@ nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) INSTANCE_RD(ramht, (co + 4))); INSTANCE_WR(ramht, (co + 0)/4, 0x00000000); INSTANCE_WR(ramht, (co + 4)/4, 0x00000000); + + list_del(&ref->list); return; } @@ -203,6 +207,8 @@ nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan, gpuobj->flags = flags; gpuobj->im_channel = chan ? chan->id : -1; + list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list); + /* Choose between global instmem heap, and per-channel private * instmem heap. On gpuobj_all) { - gpuobj->next = dev_priv->gpuobj_all; - gpuobj->next->prev = gpuobj; + *gpuobj_ret = gpuobj; + return 0; +} + +int +nouveau_gpuobj_init(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int ret; + + INIT_LIST_HEAD(&dev_priv->gpuobj_list); + + if (dev_priv->card_type < NV_50) { + if ((ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramht_offset, + dev_priv->ramht_size, + NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_ALLOW_NO_REFS, + &dev_priv->ramht, NULL))) + return ret; } - dev_priv->gpuobj_all = gpuobj; - *gpuobj_ret = gpuobj; return 0; } -void nouveau_gpuobj_takedown(struct drm_device *dev) +void +nouveau_gpuobj_takedown(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_gpuobj *gpuobj = NULL; + struct list_head *entry, *tmp; DRM_DEBUG("\n"); - while ((gpuobj = dev_priv->gpuobj_all)) { + nouveau_gpuobj_del(dev, &dev_priv->ramht); + + list_for_each_safe(entry, tmp, &dev_priv->gpuobj_list) { + gpuobj = list_entry(entry, struct nouveau_gpuobj, list); + DRM_ERROR("gpuobj %p still exists at takedown, refs=%d\n", gpuobj, gpuobj->refcount); gpuobj->refcount = 0; @@ -279,7 +305,8 @@ void nouveau_gpuobj_takedown(struct drm_device *dev) } } -int nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj) +int +nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_engine *engine = &dev_priv->Engine; @@ -296,6 +323,9 @@ int nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj) return -EINVAL; } + if (gpuobj->dtor) + gpuobj->dtor(dev, gpuobj); + engine->instmem.clear(dev, gpuobj); if (gpuobj->im_pramin) { @@ -306,12 +336,7 @@ int nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj) nouveau_mem_free_block(gpuobj->im_pramin); } - if (gpuobj->next) - gpuobj->next->prev = gpuobj->prev; - if (gpuobj->prev) - gpuobj->prev->next = gpuobj->next; - else - dev_priv->gpuobj_all = gpuobj->next; + list_del(&gpuobj->list); *pgpuobj = NULL; drm_free(gpuobj, sizeof(*gpuobj), DRM_MEM_DRIVER); @@ -403,9 +428,6 @@ nouveau_gpuobj_ref_add(struct drm_device *dev, struct nouveau_channel *chan, drm_free(ref, sizeof(*ref), DRM_MEM_DRIVER); return ret; } - - ref->next = chan->ramht_refs; - chan->ramht_refs = ref; } else { ref->handle = ~0; *ref_ret = ref; @@ -462,19 +484,21 @@ nouveau_gpuobj_new_ref(struct drm_device *dev, return 0; } -static int +int nouveau_gpuobj_ref_find(struct nouveau_channel *chan, uint32_t handle, struct nouveau_gpuobj_ref **ref_ret) { - struct nouveau_gpuobj_ref *ref = chan->ramht_refs; + struct nouveau_gpuobj_ref *ref; + struct list_head *entry, *tmp; + + list_for_each_safe(entry, tmp, &chan->ramht_refs) { + ref = list_entry(entry, struct nouveau_gpuobj_ref, list); - while (ref) { if (ref->handle == handle) { if (ref_ret) *ref_ret = ref; return 0; } - ref = ref->next; } return -EINVAL; @@ -499,6 +523,8 @@ nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t offset, uint32_t size, gpuobj->im_channel = -1; gpuobj->flags = flags | NVOBJ_FLAG_FAKE; + list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list); + gpuobj->im_pramin = drm_calloc(1, sizeof(struct mem_block), DRM_MEM_DRIVER); if (!gpuobj->im_pramin) { @@ -897,6 +923,8 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, struct nouveau_gpuobj *vram = NULL, *tt = NULL; int ret, i; + INIT_LIST_HEAD(&chan->ramht_refs); + DRM_DEBUG("ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h); /* Reserve a block of PRAMIN for the channel @@ -994,14 +1022,17 @@ void nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; + struct list_head *entry, *tmp; struct nouveau_gpuobj_ref *ref; DRM_DEBUG("ch%d\n", chan->id); - while ((ref = chan->ramht_refs)) { - chan->ramht_refs = ref->next; + list_for_each_safe(entry, tmp, &chan->ramht_refs) { + ref = list_entry(entry, struct nouveau_gpuobj_ref, list); + nouveau_gpuobj_ref_del(dev, &ref); } + nouveau_gpuobj_ref_del(dev, &chan->ramht); nouveau_gpuobj_del(dev, &chan->vm_pd); @@ -1022,6 +1053,7 @@ int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data, struct nouveau_gpuobj *gr = NULL; int ret; + NOUVEAU_CHECK_INITIALISED_WITH_RETURN; NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(init->channel, file_priv, chan); //FIXME: check args, only allow trusted objects to be created @@ -1029,8 +1061,7 @@ int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data, if (init->handle == ~0) return -EINVAL; - if (nouveau_gpuobj_ref_find(chan, init->handle, NULL) == - 0) + if (nouveau_gpuobj_ref_find(chan, init->handle, NULL) == 0) return -EEXIST; ret = nouveau_gpuobj_gr_new(chan, init->class, &gr); @@ -1050,3 +1081,21 @@ int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data, return 0; } +int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + struct drm_nouveau_gpuobj_free *objfree = data; + struct nouveau_gpuobj_ref *ref; + struct nouveau_channel *chan; + int ret; + + NOUVEAU_CHECK_INITIALISED_WITH_RETURN; + NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(objfree->channel, file_priv, chan); + + if ((ret = nouveau_gpuobj_ref_find(chan, objfree->handle, &ref))) + return ret; + nouveau_gpuobj_ref_del(dev, &ref); + + return 0; +} + diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 26ba8fbf..4fb53291 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -267,12 +267,16 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) return 0; } -static int nouveau_card_init(struct drm_device *dev) +int +nouveau_card_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_engine *engine; int ret; + if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE) + return 0; + /* Map any PCI resources we need on the card */ ret = nouveau_init_card_mappings(dev); if (ret) return ret; @@ -290,6 +294,9 @@ static int nouveau_card_init(struct drm_device *dev) engine = &dev_priv->Engine; dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED; + ret = drm_irq_install(dev); + if (ret) return ret; + /* Initialise instance memory, must happen before mem_init so we * know exactly how much VRAM we're able to use for "normal" * purposes. @@ -301,6 +308,9 @@ static int nouveau_card_init(struct drm_device *dev) ret = nouveau_mem_init(dev); if (ret) return ret; + ret = nouveau_gpuobj_init(dev); + if (ret) return ret; + /* Parse BIOS tables / Run init tables? */ /* PMC */ @@ -349,6 +359,8 @@ static void nouveau_card_takedown(struct drm_device *dev) nouveau_mem_close(dev); engine->instmem.takedown(dev); + drm_irq_uninstall(dev); + dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN; } } @@ -368,14 +380,6 @@ void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv) /* first module load, setup the mmio/fb mapping */ int nouveau_firstopen(struct drm_device *dev) { - int ret; - - ret = nouveau_card_init(dev); - if (ret) { - DRM_ERROR("nouveau_card_init() failed! (%d)\n", ret); - return ret; - } - return 0; } @@ -395,15 +399,6 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN; dev->dev_private = (void *)dev_priv; - -#if 0 - ret = nouveau_card_init(dev); - if (ret) { - DRM_ERROR("nouveau_card_init() failed! (%d)\n", ret); - return ret; - } -#endif - return 0; } @@ -427,12 +422,24 @@ int nouveau_unload(struct drm_device *dev) return 0; } +int +nouveau_ioctl_card_init(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + return nouveau_card_init(dev); +} + int nouveau_ioctl_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_getparam *getparam = data; + NOUVEAU_CHECK_INITIALISED_WITH_RETURN; + switch (getparam->param) { + case NOUVEAU_GETPARAM_CHIPSET_ID: + getparam->value = dev_priv->chipset; + break; case NOUVEAU_GETPARAM_PCI_VENDOR: getparam->value=dev->pci_vendor; break; @@ -481,6 +488,8 @@ int nouveau_ioctl_setparam(struct drm_device *dev, void *data, struct drm_file * struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_setparam *setparam = data; + NOUVEAU_CHECK_INITIALISED_WITH_RETURN; + switch (setparam->param) { case NOUVEAU_SETPARAM_CMDBUF_LOCATION: switch (setparam->value) { diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index 35b20abd..36aa6200 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -93,13 +93,6 @@ int nv04_instmem_init(struct drm_device *dev) nv04_instmem_determine_amount(dev); nv04_instmem_configure_fixed_tables(dev); - if ((ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramht_offset, - dev_priv->ramht_size, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ALLOW_NO_REFS, - &dev_priv->ramht, NULL))) - return ret; - /* Create a heap to manage RAMIN allocations, we don't allocate * the space that was reserved for RAMHT/FC/RO. */ @@ -117,9 +110,6 @@ int nv04_instmem_init(struct drm_device *dev) void nv04_instmem_takedown(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - - nouveau_gpuobj_del(dev, &dev_priv->ramht); } int -- cgit v1.2.3 From 51f24be578025e3f1eae859288adf5232afc898d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 6 Aug 2007 21:46:55 +1000 Subject: nouveau: Determine trapped channel id from active grctx on >=NV40 --- shared-core/nouveau_irq.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index f7baf89e..2ee77d83 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -301,6 +301,61 @@ nouveau_print_bitfield_names(uint32_t value, printk(" (unknown bits 0x%08x)", value); } +static int +nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int channel; + + if (dev_priv->card_type < NV_40) { + channel = (NV_READ(0x400704) >> 20) & 0x1f; + } else + if (dev_priv->card_type < NV_50) { + uint32_t cur_grctx = (NV_READ(0x40032C) & 0xfffff) << 4; + + /* 0x400704 *sometimes* contains a sensible channel ID, but + * mostly not.. for now lookup which channel owns the active + * PGRAPH context. Probably a better way, but this'll do + * for now. + */ + for (channel = 0; channel < 32; channel++) { + if (dev_priv->fifos[channel] == NULL) + continue; + if (cur_grctx == + dev_priv->fifos[channel]->ramin_grctx->instance) + break; + } + if (channel == 32) { + DRM_ERROR("AIII, unable to determine active channel " + "from PGRAPH context 0x%08x\n", cur_grctx); + return -EINVAL; + } + } else { + uint32_t cur_grctx = (NV_READ(0x40032C) & 0xfffff) << 12; + + for (channel = 0; channel < 128; channel++) { + if (dev_priv->fifos[channel] == NULL) + continue; + if (cur_grctx == + dev_priv->fifos[channel]->ramin_grctx->instance) + break; + } + if (channel == 128) { + DRM_ERROR("AIII, unable to determine active channel " + "from PGRAPH context 0x%08x\n", cur_grctx); + return -EINVAL; + } + } + + if (channel > nouveau_fifo_number(dev) || + dev_priv->fifos[channel] == NULL) { + DRM_ERROR("AIII, invalid/inactive channel id %d\n", channel); + return -EINVAL; + } + + return 0; +} + static void nouveau_graph_dump_trap_info(struct drm_device *dev) { @@ -310,8 +365,10 @@ nouveau_graph_dump_trap_info(struct drm_device *dev) uint32_t method, subc, data; uint32_t nsource, nstatus; + if (nouveau_graph_trapped_channel(dev, &channel)) + channel = -1; + address = NV_READ(0x400704); - channel = (address >> 20) & 0x1F; subc = (address >> 16) & 0x7; method = address & 0x1FFC; data = NV_READ(0x400708); -- cgit v1.2.3 From cf04641bc61c8bc18101713a8d95ef98e6afae7f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 6 Aug 2007 22:05:31 +1000 Subject: nouveau: Give DRM its own gpu channel If your card doesn't have working context switching, it is now broken. --- shared-core/nouveau_drv.h | 26 ++++++++++++++++++++++++++ shared-core/nouveau_fifo.c | 14 +++++++------- shared-core/nouveau_state.c | 9 +++++++++ shared-core/nv04_instmem.c | 1 - 4 files changed, 42 insertions(+), 8 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 0b173b76..10f9149e 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -134,6 +134,22 @@ struct nouveau_channel struct list_head ramht_refs; /* Objects referenced by RAMHT */ }; +struct nouveau_drm_channel { + struct nouveau_channel *chan; + + /* DMA state */ + int max, put, cur, free; + int push_free; + volatile uint32_t *pushbuf; + + /* Notifiers */ + uint32_t notify0_offset; + + /* Buffer moves */ + uint32_t m2mf_dma_source; + uint32_t m2mf_dma_destin; +}; + struct nouveau_config { struct { int location; @@ -222,6 +238,7 @@ struct drm_nouveau_private { struct nouveau_channel *fifos[NV_MAX_FIFO_NUMBER]; struct nouveau_engine Engine; + struct nouveau_drm_channel channel; /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ struct nouveau_gpuobj *ramht; @@ -345,6 +362,10 @@ extern int nouveau_fifo_ctx_size(struct drm_device *); extern void nouveau_fifo_cleanup(struct drm_device *, struct drm_file *); extern int nouveau_fifo_owner(struct drm_device *, struct drm_file *, int channel); +extern int nouveau_fifo_alloc(struct drm_device *dev, + struct nouveau_channel **chan, + struct drm_file *file_priv, + uint32_t fb_ctxdma, uint32_t tt_ctxdma); extern void nouveau_fifo_free(struct nouveau_channel *); /* nouveau_object.c */ @@ -400,6 +421,11 @@ extern struct drm_ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); extern int nouveau_sgdma_nottm_hack_init(struct drm_device *); extern void nouveau_sgdma_nottm_hack_takedown(struct drm_device *); +/* nouveau_dma.c */ +extern int nouveau_dma_channel_init(struct drm_device *); +extern void nouveau_dma_channel_takedown(struct drm_device *); +extern int nouveau_dma_wait(struct drm_device *, int size); + /* nv04_fb.c */ extern int nv04_fb_init(struct drm_device *); extern void nv04_fb_takedown(struct drm_device *); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 152b669a..823801f9 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -261,9 +261,10 @@ nouveau_fifo_cmdbuf_alloc(struct nouveau_channel *chan) } /* allocates and initializes a fifo for user space consumption */ -int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret, - struct drm_file *file_priv, - uint32_t vram_handle, uint32_t tt_handle) +int +nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, + struct drm_file *file_priv, + uint32_t vram_handle, uint32_t tt_handle) { int ret; struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -288,7 +289,6 @@ int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret, /* no more fifos. you lost. */ if (channel==nouveau_fifo_number(dev)) return -EINVAL; - (*chan_ret) = channel; dev_priv->fifos[channel] = drm_calloc(1, sizeof(struct nouveau_channel), DRM_MEM_DRIVER); @@ -394,6 +394,7 @@ int nouveau_fifo_alloc(struct drm_device *dev, int *chan_ret, NV_WRITE(NV03_PFIFO_CACHES, 1); DRM_INFO("%s: initialised FIFO %d\n", __func__, channel); + *chan_ret = chan; return 0; } @@ -482,13 +483,12 @@ static int nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0) return -EINVAL; - res = nouveau_fifo_alloc(dev, &init->channel, file_priv, + res = nouveau_fifo_alloc(dev, &chan, file_priv, init->fb_ctxdma_handle, init->tt_ctxdma_handle); if (res) return res; - chan = dev_priv->fifos[init->channel]; - + init->channel = chan->id; init->put_base = chan->pushbuf_base; /* make the fifo available to user space */ diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 4fb53291..9dab34cc 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -274,6 +274,8 @@ nouveau_card_init(struct drm_device *dev) struct nouveau_engine *engine; int ret; + DRM_DEBUG("prev state = %d\n", dev_priv->init_state); + if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE) return 0; @@ -335,6 +337,9 @@ nouveau_card_init(struct drm_device *dev) /* what about PVIDEO/PCRTC/PRAMDAC etc? */ + ret = nouveau_dma_channel_init(dev); + if (ret) return ret; + dev_priv->init_state = NOUVEAU_CARD_INIT_DONE; return 0; } @@ -344,7 +349,11 @@ static void nouveau_card_takedown(struct drm_device *dev) struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_engine *engine = &dev_priv->Engine; + DRM_DEBUG("prev state = %d\n", dev_priv->init_state); + if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) { + nouveau_dma_channel_takedown(dev); + engine->fifo.takedown(dev); engine->graph.takedown(dev); engine->fb.takedown(dev); diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index 36aa6200..5e0f6f4e 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -129,7 +129,6 @@ nv04_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) if (gpuobj && gpuobj->im_backing) { if (gpuobj->im_bound) dev_priv->Engine.instmem.unbind(dev, gpuobj); - nouveau_mem_free(dev, gpuobj->im_backing); gpuobj->im_backing = NULL; } } -- cgit v1.2.3 From 7a0a812ea42d80eed89b7b9993eae42c7c1b1613 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 6 Aug 2007 22:06:52 +1000 Subject: nouveau: Remove PGRAPH_SURFACE hack, it wont work now anyway. Need to find another way of doing this, ideally someone'd hunt down which object/method controls it! The Xv blit adaptor is likely now broken on cards that have pNv->WaitVSyncPossible enabled. --- shared-core/nouveau_fifo.c | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 823801f9..fd21d2f3 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -369,19 +369,6 @@ nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, nouveau_fifo_free(chan); return ret; } - - /* Temporary hack, to avoid breaking Xv on cards where the - * initial context value for 0x400710 doesn't have these bits - * set. Proper fix would be to find which object+method is - * responsible for modifying this state. - */ - if (dev_priv->chipset >= 0x10 && dev_priv->chipset < 0x50) { - uint32_t tmp; - tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; - NV_WRITE(NV10_PGRAPH_SURFACE, tmp); - tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100; - NV_WRITE(NV10_PGRAPH_SURFACE, tmp); - } } NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, -- cgit v1.2.3 From 8d5a8ebc316028f14666697cff33daddbe384bcd Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 6 Aug 2007 22:32:36 +1000 Subject: nouveau: ouch, add nouveau_dma.[ch] files.. --- shared-core/nouveau_dma.c | 168 ++++++++++++++++++++++++++++++++++++++++++++++ shared-core/nouveau_dma.h | 98 +++++++++++++++++++++++++++ 2 files changed, 266 insertions(+) create mode 100644 shared-core/nouveau_dma.c create mode 100644 shared-core/nouveau_dma.h (limited to 'shared-core') diff --git a/shared-core/nouveau_dma.c b/shared-core/nouveau_dma.c new file mode 100644 index 00000000..ce5b6299 --- /dev/null +++ b/shared-core/nouveau_dma.c @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2007 Ben Skeggs. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "drmP.h" +#include "drm.h" +#include "nouveau_drv.h" +#include "nouveau_dma.h" + +#define SKIPS 8 + +int +nouveau_dma_channel_init(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_drm_channel *dchan = &dev_priv->channel; + struct nouveau_gpuobj *gpuobj = NULL; + int grclass, ret, i; + + DRM_DEBUG("\n"); + + /* Allocate channel */ + ret = nouveau_fifo_alloc(dev, &dchan->chan, (struct drm_file *)-2, + NvDmaFB, NvDmaTT); + if (ret) { + DRM_ERROR("Error allocating GPU channel: %d\n", ret); + return ret; + } + DRM_DEBUG("Using FIFO channel %d\n", dchan->chan->id); + + /* Map push buffer */ + drm_core_ioremap(dchan->chan->pushbuf_mem->map, dev); + if (!dchan->chan->pushbuf_mem->map->handle) { + DRM_ERROR("Failed to ioremap push buffer\n"); + return -EINVAL; + } + dchan->pushbuf = (void*)dchan->chan->pushbuf_mem->map->handle; + + /* Initialise DMA vars */ + dchan->max = (dchan->chan->pushbuf_mem->size >> 2) - 2; + dchan->put = dchan->chan->pushbuf_base >> 2; + dchan->cur = dchan->put; + dchan->free = dchan->max - dchan->cur; + + /* Insert NOPS for SKIPS */ + dchan->free -= SKIPS; + dchan->push_free = SKIPS; + for (i=0; ichan, NvNotify0, 1, + &dchan->notify0_offset))) { + DRM_ERROR("Error allocating NvNotify0: %d\n", ret); + return ret; + } + + /* We use NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */ + if (dev_priv->card_type < NV_50) grclass = NV_MEMORY_TO_MEMORY_FORMAT; + else grclass = NV50_MEMORY_TO_MEMORY_FORMAT; + if ((ret = nouveau_gpuobj_gr_new(dchan->chan, grclass, &gpuobj))) { + DRM_ERROR("Error creating NvM2MF: %d\n", ret); + return ret; + } + + if ((ret = nouveau_gpuobj_ref_add(dev, dchan->chan, NvM2MF, + gpuobj, NULL))) { + DRM_ERROR("Error referencing NvM2MF: %d\n", ret); + return ret; + } + dchan->m2mf_dma_source = NvDmaFB; + dchan->m2mf_dma_destin = NvDmaFB; + + BEGIN_RING(NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1); + OUT_RING (NvM2MF); + BEGIN_RING(NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_SET_DMA_NOTIFY, 1); + OUT_RING (NvNotify0); + BEGIN_RING(NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_SET_DMA_SOURCE, 2); + OUT_RING (dchan->m2mf_dma_source); + OUT_RING (dchan->m2mf_dma_destin); + FIRE_RING(); + + return 0; +} + +void +nouveau_dma_channel_takedown(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_drm_channel *dchan = &dev_priv->channel; + + DRM_DEBUG("\n"); + + if (dchan->chan) { + nouveau_fifo_free(dchan->chan); + dchan->chan = NULL; + } +} + +#define RING_SKIPS 8 + +#define READ_GET() ((NV_READ(NV03_FIFO_REGS_DMAGET(dchan->chan->id)) - \ + dchan->chan->pushbuf_base) >> 2) +#define WRITE_PUT(val) do { \ + NV_WRITE(NV03_FIFO_REGS_DMAPUT(dchan->chan->id), \ + ((val) << 2) + dchan->chan->pushbuf_base); \ +} while(0) + +int +nouveau_dma_wait(struct drm_device *dev, int size) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_drm_channel *dchan = &dev_priv->channel; + uint32_t get; + + while (dchan->free < size) { + get = READ_GET(); + + if (dchan->put >= get) { + dchan->free = dchan->max - dchan->cur; + + if (dchan->free < size) { + dchan->push_free = 1; + OUT_RING(0x20000000|dchan->chan->pushbuf_base); + if (get <= RING_SKIPS) { + /*corner case - will be idle*/ + if (dchan->put <= RING_SKIPS) + WRITE_PUT(RING_SKIPS + 1); + + do { + get = READ_GET(); + } while (get <= RING_SKIPS); + } + + WRITE_PUT(RING_SKIPS); + dchan->cur = dchan->put = RING_SKIPS; + dchan->free = get - (RING_SKIPS + 1); + } + } else { + dchan->free = get - dchan->cur - 1; + } + } + + return 0; +} + diff --git a/shared-core/nouveau_dma.h b/shared-core/nouveau_dma.h new file mode 100644 index 00000000..5e51c1c4 --- /dev/null +++ b/shared-core/nouveau_dma.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2007 Ben Skeggs. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __NOUVEAU_DMA_H__ +#define __NOUVEAU_DMA_H__ + +typedef enum { + NvSubM2MF = 0, +} nouveau_subchannel_id_t; + +typedef enum { + NvM2MF = 0x80039001, + NvDmaFB = 0x8003d001, + NvDmaTT = 0x8003d002, + NvNotify0 = 0x8003d003 +} nouveau_object_handle_t; + +#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 +#define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000 +#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050 +#define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100 +#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 +#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000 +#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001 +#define NV_MEMORY_TO_MEMORY_FORMAT_SET_DMA_NOTIFY 0x00000180 +#define NV_MEMORY_TO_MEMORY_FORMAT_SET_DMA_SOURCE 0x00000184 +#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c + +#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 +#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200 +#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c +#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238 +#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c + +#define BEGIN_RING(subc, mthd, cnt) do { \ + int push_size = (cnt) + 1; \ + if (dchan->push_free) { \ + DRM_ERROR("prior packet incomplete: %d\n", dchan->push_free); \ + break; \ + } \ + if (dchan->free < push_size) { \ + if (nouveau_dma_wait(dev, push_size)) { \ + DRM_ERROR("FIFO timeout\n"); \ + break; \ + } \ + } \ + dchan->free -= push_size; \ + dchan->push_free = push_size; \ + OUT_RING(((cnt)<<18) | ((subc)<<15) | mthd); \ +} while(0) + +#define OUT_RING(data) do { \ + if (dchan->push_free == 0) { \ + DRM_ERROR("no space left in packet\n"); \ + break; \ + } \ + dchan->pushbuf[dchan->cur++] = (data); \ + dchan->push_free--; \ +} while(0) + +#define FIRE_RING() do { \ + if (dchan->push_free) { \ + DRM_ERROR("packet incomplete: %d\n", dchan->push_free); \ + break; \ + } \ + if (dchan->cur != dchan->put) { \ + DRM_MEMORYBARRIER(); \ + dchan->put = dchan->cur; \ + NV_WRITE(NV03_FIFO_REGS_DMAPUT(dchan->chan->id), \ + (dchan->put<<2)); \ + } \ +} while(0) + +#endif + -- cgit v1.2.3 From ac24f328ec8954f78b1025db716abdd5b25b3dd9 Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Mon, 6 Aug 2007 17:14:26 +0200 Subject: nouveau: Bump PCI GART to 16MB --- shared-core/nouveau_mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 981af8a6..419522f4 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -411,7 +411,7 @@ int nouveau_mem_init(struct drm_device *dev) struct drm_scatter_gather sgreq; DRM_DEBUG("Allocating sg memory for PCI DMA\n"); - sgreq.size = 4 << 20; //4MB of PCI scatter-gather zone + sgreq.size = 16 << 20; //4MB of PCI scatter-gather zone if (drm_sg_alloc(dev, &sgreq)) { DRM_ERROR("Unable to allocate 4MB of scatter-gather" -- cgit v1.2.3 From 66f5232d9393f6886d8fd1a60b2d75cd009b972c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 7 Aug 2007 01:51:46 +1000 Subject: nouveau: Init global gpuobj list early, unbreaks sgdma code. --- shared-core/nouveau_object.c | 2 -- shared-core/nouveau_state.c | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 22ad23cd..bb096531 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -270,8 +270,6 @@ nouveau_gpuobj_init(struct drm_device *dev) struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; - INIT_LIST_HEAD(&dev_priv->gpuobj_list); - if (dev_priv->card_type < NV_50) { if ((ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramht_offset, dev_priv->ramht_size, diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 9dab34cc..a23d6001 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -299,6 +299,8 @@ nouveau_card_init(struct drm_device *dev) ret = drm_irq_install(dev); if (ret) return ret; + INIT_LIST_HEAD(&dev_priv->gpuobj_list); + /* Initialise instance memory, must happen before mem_init so we * know exactly how much VRAM we're able to use for "normal" * purposes. -- cgit v1.2.3 From a4759b85139dd8d81de25e170777309b770f5316 Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Tue, 7 Aug 2007 23:09:44 +0200 Subject: nouveau : fix enable irq (in the previous code all irq were masked by engine init after irq_postinstall) --- shared-core/nouveau_irq.c | 3 +++ shared-core/nouveau_state.c | 9 ++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 2ee77d83..84a37040 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -39,6 +39,9 @@ void nouveau_irq_preinstall(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; + /* TODO this should be removed as this stuff is done in + * engine.*init + */ DRM_DEBUG("IRQ: preinst\n"); diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index a23d6001..e80e77a5 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -296,9 +296,6 @@ nouveau_card_init(struct drm_device *dev) engine = &dev_priv->Engine; dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED; - ret = drm_irq_install(dev); - if (ret) return ret; - INIT_LIST_HEAD(&dev_priv->gpuobj_list); /* Initialise instance memory, must happen before mem_init so we @@ -337,6 +334,12 @@ nouveau_card_init(struct drm_device *dev) ret = engine->fifo.init(dev); if (ret) return ret; + /* this call irq_preinstall, register irq handler and + * call irq_postinstall + */ + ret = drm_irq_install(dev); + if (ret) return ret; + /* what about PVIDEO/PCRTC/PRAMDAC etc? */ ret = nouveau_dma_channel_init(dev); -- cgit v1.2.3 From 4ad487190d5b79947c65e238330506db6b77e523 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 8 Aug 2007 10:42:12 +1000 Subject: nouveau: enable/disable engine-specific interrupts in _init()/_takedown() All interrupts are still masked by PMC until init is finished. --- shared-core/nouveau_fifo.c | 4 +++ shared-core/nouveau_irq.c | 81 ---------------------------------------------- shared-core/nv04_graph.c | 4 +++ shared-core/nv04_mc.c | 2 -- shared-core/nv10_graph.c | 2 +- shared-core/nv20_graph.c | 2 +- shared-core/nv30_graph.c | 2 +- shared-core/nv40_graph.c | 2 +- shared-core/nv40_mc.c | 2 -- shared-core/nv50_fifo.c | 12 +++++++ shared-core/nv50_graph.c | 12 ++++++- shared-core/nv50_mc.c | 1 + 12 files changed, 36 insertions(+), 90 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index fd21d2f3..f9677514 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -120,6 +120,10 @@ int nouveau_fifo_init(struct drm_device *dev) NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | NV_PMC_ENABLE_PFIFO); + /* Enable PFIFO error reporting */ + NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF); + NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF); + NV_WRITE(NV03_PFIFO_CACHES, 0x00000000); ret = nouveau_fifo_instmem_configure(dev); diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 84a37040..f110340b 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -39,37 +39,7 @@ void nouveau_irq_preinstall(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - /* TODO this should be removed as this stuff is done in - * engine.*init - */ - DRM_DEBUG("IRQ: preinst\n"); - - if (!dev_priv) { - DRM_ERROR("AIII, no dev_priv\n"); - return; - } - if (!dev_priv->mmio) { - DRM_ERROR("AIII, no dev_priv->mmio\n"); - return; - } - - /* Disable/Clear PFIFO interrupts */ - NV_WRITE(NV03_PFIFO_INTR_EN_0, 0); - NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF); - /* Disable/Clear PGRAPH interrupts */ - if (dev_priv->card_typedev_private; - if (!dev_priv) { - DRM_ERROR("AIII, no dev_priv\n"); - return; - } - if (!dev_priv->mmio) { - DRM_ERROR("AIII, no dev_priv->mmio\n"); - return; - } - - DRM_DEBUG("IRQ: postinst\n"); - - /* Enable PFIFO error reporting */ - NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF); - NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF); - - /* Enable PGRAPH interrupts */ - if (dev_priv->card_typedev_private; - if (!dev_priv) { - DRM_ERROR("AIII, no dev_priv\n"); - return; - } - if (!dev_priv->mmio) { - DRM_ERROR("AIII, no dev_priv->mmio\n"); - return; - } - - DRM_DEBUG("IRQ: uninst\n"); - - /* Disable PFIFO interrupts */ - NV_WRITE(NV03_PFIFO_INTR_EN_0, 0); - /* Disable PGRAPH interrupts */ - if (dev_priv->card_typectx_table->instance >> 4); - NV_WRITE(NV03_PGRAPH_INTR_EN, 0x00000000); NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); + NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index c79b63cc..c1464bc2 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -1636,8 +1636,8 @@ nv40_graph_init(struct drm_device *dev) /* No context present currently */ NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, 0x00000000); - NV_WRITE(NV03_PGRAPH_INTR_EN, 0x00000000); NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); + NV_WRITE(NV40_PGRAPH_INTR_EN, 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); diff --git a/shared-core/nv40_mc.c b/shared-core/nv40_mc.c index 8bb6b083..c7db9023 100644 --- a/shared-core/nv40_mc.c +++ b/shared-core/nv40_mc.c @@ -14,8 +14,6 @@ nv40_mc_init(struct drm_device *dev) */ NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF); - NV_WRITE(NV03_PMC_INTR_EN_0, 0); - switch (dev_priv->chipset) { case 0x44: case 0x46: /* G72 */ diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index a5e79260..f915d332 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -119,6 +119,17 @@ nv50_fifo_init_reset(struct drm_device *dev) NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PFIFO); } +static void +nv50_fifo_init_intr(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + + DRM_DEBUG("\n"); + + NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF); + NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF); +} + static void nv50_fifo_init_context_table(struct drm_device *dev) { @@ -190,6 +201,7 @@ nv50_fifo_init(struct drm_device *dev) dev_priv->Engine.fifo.priv = priv; nv50_fifo_init_reset(dev); + nv50_fifo_init_intr(dev); if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, (128+2)*4, 0x1000, NVOBJ_FLAG_ZERO_ALLOC, diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c index 59c8cfeb..f98fe601 100644 --- a/shared-core/nv50_graph.c +++ b/shared-core/nv50_graph.c @@ -44,6 +44,16 @@ nv50_graph_init_reset(struct drm_device *dev) NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PGRAPH); } +static void +nv50_graph_init_intr(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + + DRM_DEBUG("\n"); + NV_WRITE(NV03_PGRAPH_INTR, 0xffffffff); + NV_WRITE(NV40_PGRAPH_INTR_EN, 0xffffffff); +} + static void nv50_graph_init_regs__nv(struct drm_device *dev) { @@ -59,7 +69,6 @@ nv50_graph_init_regs__nv(struct drm_device *dev) NV_WRITE(0x402000, 0xc0000000); NV_WRITE(0x400108, 0xffffffff); - NV_WRITE(0x400100, 0xffffffff); NV_WRITE(0x400824, 0x00004000); NV_WRITE(0x400500, 0x00010001); @@ -174,6 +183,7 @@ nv50_graph_init(struct drm_device *dev) DRM_DEBUG("\n"); nv50_graph_init_reset(dev); + nv50_graph_init_intr(dev); nv50_graph_init_regs__nv(dev); nv50_graph_init_regs(dev); nv50_graph_init_ctxctl(dev); diff --git a/shared-core/nv50_mc.c b/shared-core/nv50_mc.c index 952dea9f..b111826b 100644 --- a/shared-core/nv50_mc.c +++ b/shared-core/nv50_mc.c @@ -34,6 +34,7 @@ nv50_mc_init(struct drm_device *dev) struct drm_nouveau_private *dev_priv = dev->dev_private; NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF); + return 0; } -- cgit v1.2.3 From 296050eee6ca7b496e8702ceca9628de803d79f8 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 8 Aug 2007 13:01:29 +1000 Subject: nouveau/nv50: hack up initial channel context from current state We really should be providing static values like the nv40 PGRAPH code does, however, this will do for now to keep X at least working. --- shared-core/nv50_graph.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c index f98fe601..e5bbf65e 100644 --- a/shared-core/nv50_graph.c +++ b/shared-core/nv50_graph.c @@ -202,6 +202,7 @@ nv50_graph_create_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_engine *engine = &dev_priv->Engine; struct nouveau_gpuobj *ramin = chan->ramin->gpuobj; int grctx_size = 0x60000, hdr; int ret; @@ -224,6 +225,11 @@ nv50_graph_create_context(struct nouveau_channel *chan) INSTANCE_WR(ramin, (hdr + 0x10)/4, 0); INSTANCE_WR(ramin, (hdr + 0x14)/4, 0x00010000); + if ((ret = engine->graph.load_context(chan))) { + DRM_ERROR("Error hacking up initial context: %d\n", ret); + return ret; + } + return 0; } -- cgit v1.2.3 From 40f21563564332786ca2b9ffc7d7ba9c7e6f7f1a Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 8 Aug 2007 16:11:28 +1000 Subject: nouveau: return channel id --- shared-core/nouveau_irq.c | 1 + 1 file changed, 1 insertion(+) (limited to 'shared-core') diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index f110340b..03c466de 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -275,6 +275,7 @@ nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret) return -EINVAL; } + *channel_ret = channel; return 0; } -- cgit v1.2.3 From 05633ca3708f48cfbbb77518da4e791d7e1613c2 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 8 Aug 2007 16:37:55 +1000 Subject: nouveau: Always allocate drm's push buffer in VRAM Fixes #11868 --- shared-core/nouveau_dma.c | 11 ++++++- shared-core/nouveau_drv.h | 1 + shared-core/nouveau_fifo.c | 78 +++++++++++++++++++++++++--------------------- 3 files changed, 53 insertions(+), 37 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_dma.c b/shared-core/nouveau_dma.c index ce5b6299..ab502e6a 100644 --- a/shared-core/nouveau_dma.c +++ b/shared-core/nouveau_dma.c @@ -37,13 +37,22 @@ nouveau_dma_channel_init(struct drm_device *dev) struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_drm_channel *dchan = &dev_priv->channel; struct nouveau_gpuobj *gpuobj = NULL; + struct mem_block *pushbuf; int grclass, ret, i; DRM_DEBUG("\n"); + pushbuf = nouveau_mem_alloc(dev, 0, 0x8000, + NOUVEAU_MEM_FB | NOUVEAU_MEM_MAPPED, + (struct drm_file *)-2); + if (!pushbuf) { + DRM_ERROR("Failed to allocate DMA push buffer\n"); + return -ENOMEM; + } + /* Allocate channel */ ret = nouveau_fifo_alloc(dev, &dchan->chan, (struct drm_file *)-2, - NvDmaFB, NvDmaTT); + pushbuf, NvDmaFB, NvDmaTT); if (ret) { DRM_ERROR("Error allocating GPU channel: %d\n", ret); return ret; diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 10f9149e..572df46e 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -365,6 +365,7 @@ extern int nouveau_fifo_owner(struct drm_device *, struct drm_file *, extern int nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan, struct drm_file *file_priv, + struct mem_block *pushbuf, uint32_t fb_ctxdma, uint32_t tt_ctxdma); extern void nouveau_fifo_free(struct nouveau_channel *); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index f9677514..22bced14 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -190,46 +190,30 @@ int nouveau_fifo_init(struct drm_device *dev) } static int -nouveau_fifo_cmdbuf_alloc(struct nouveau_channel *chan) +nouveau_fifo_pushbuf_ctxdma_init(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_config *config = &dev_priv->config; - struct mem_block *cb; - int cb_min_size = max(NV03_FIFO_SIZE,PAGE_SIZE); + struct mem_block *pb = chan->pushbuf_mem; struct nouveau_gpuobj *pushbuf = NULL; int ret; - /* Defaults for unconfigured values */ - if (!config->cmdbuf.location) - config->cmdbuf.location = NOUVEAU_MEM_FB; - if (!config->cmdbuf.size || config->cmdbuf.size < cb_min_size) - config->cmdbuf.size = cb_min_size; - - cb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size, - config->cmdbuf.location | NOUVEAU_MEM_MAPPED, - (struct drm_file *)-2); - if (!cb) { - DRM_ERROR("Couldn't allocate DMA command buffer.\n"); - return -ENOMEM; - } - - if (cb->flags & NOUVEAU_MEM_AGP) { - ret = nouveau_gpuobj_gart_dma_new(chan, cb->start, cb->size, + if (pb->flags & NOUVEAU_MEM_AGP) { + ret = nouveau_gpuobj_gart_dma_new(chan, pb->start, pb->size, NV_DMA_ACCESS_RO, &pushbuf, &chan->pushbuf_base); } else - if (cb->flags & NOUVEAU_MEM_PCI) { + if (pb->flags & NOUVEAU_MEM_PCI) { ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, - cb->start, cb->size, + pb->start, pb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_PCI_NONLINEAR, &pushbuf); chan->pushbuf_base = 0; } else if (dev_priv->card_type != NV_04) { ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, - cb->start, cb->size, + pb->start, pb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM, &pushbuf); chan->pushbuf_base = 0; @@ -239,19 +223,13 @@ nouveau_fifo_cmdbuf_alloc(struct nouveau_channel *chan) * VRAM. */ ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, - cb->start + + pb->start + drm_get_resource_start(dev, 1), - cb->size, NV_DMA_ACCESS_RO, + pb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_PCI, &pushbuf); chan->pushbuf_base = 0; } - if (ret) { - nouveau_mem_free(dev, cb); - DRM_ERROR("Error creating push buffer ctxdma: %d\n", ret); - return ret; - } - if ((ret = nouveau_gpuobj_ref_add(dev, chan, 0, pushbuf, &chan->pushbuf))) { DRM_ERROR("Error referencing push buffer ctxdma: %d\n", ret); @@ -260,14 +238,36 @@ nouveau_fifo_cmdbuf_alloc(struct nouveau_channel *chan) return ret; } - chan->pushbuf_mem = cb; return 0; } +static struct mem_block * +nouveau_fifo_user_pushbuf_alloc(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_config *config = &dev_priv->config; + struct mem_block *pb; + int pb_min_size = max(NV03_FIFO_SIZE,PAGE_SIZE); + + /* Defaults for unconfigured values */ + if (!config->cmdbuf.location) + config->cmdbuf.location = NOUVEAU_MEM_FB; + if (!config->cmdbuf.size || config->cmdbuf.size < pb_min_size) + config->cmdbuf.size = pb_min_size; + + pb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size, + config->cmdbuf.location | NOUVEAU_MEM_MAPPED, + (struct drm_file *)-2); + if (!pb) + DRM_ERROR("Couldn't allocate DMA push buffer.\n"); + + return pb; +} + /* allocates and initializes a fifo for user space consumption */ int nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, - struct drm_file *file_priv, + struct drm_file *file_priv, struct mem_block *pushbuf, uint32_t vram_handle, uint32_t tt_handle) { int ret; @@ -303,6 +303,7 @@ nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, chan->dev = dev; chan->id = channel; chan->file_priv = file_priv; + chan->pushbuf_mem = pushbuf; DRM_INFO("Allocating FIFO number %d\n", channel); @@ -320,8 +321,8 @@ nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, return ret; } - /* allocate a command buffer, and create a dma object for the gpu */ - ret = nouveau_fifo_cmdbuf_alloc(chan); + /* Create a dma object for the push buffer */ + ret = nouveau_fifo_pushbuf_ctxdma_init(chan); if (ret) { nouveau_fifo_free(chan); return ret; @@ -467,6 +468,7 @@ static int nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, struct drm_nouveau_channel_alloc *init = data; struct drm_map_list *entry; struct nouveau_channel *chan; + struct mem_block *pushbuf; int res; NOUVEAU_CHECK_INITIALISED_WITH_RETURN; @@ -474,7 +476,11 @@ static int nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0) return -EINVAL; - res = nouveau_fifo_alloc(dev, &chan, file_priv, + pushbuf = nouveau_fifo_user_pushbuf_alloc(dev); + if (!pushbuf) + return -ENOMEM; + + res = nouveau_fifo_alloc(dev, &chan, file_priv, pushbuf, init->fb_ctxdma_handle, init->tt_ctxdma_handle); if (res) -- cgit v1.2.3 From e326acf5493a7193954d3dd794855e2a11dc1782 Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Wed, 8 Aug 2007 22:55:32 +0200 Subject: nouveau : nv10, nv20, nv30 : don't save all channel in the same RAMFC entry This should improve multi fifo --- shared-core/nv10_fifo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c index 47af0ff0..a056460d 100644 --- a/shared-core/nv10_fifo.c +++ b/shared-core/nv10_fifo.c @@ -33,7 +33,7 @@ NV10_RAMFC_##offset/4, (val)) #define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \ NV10_RAMFC_##offset/4) -#define NV10_RAMFC(c) (dev_priv->ramfc_offset + NV10_RAMFC__SIZE) +#define NV10_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV10_RAMFC__SIZE)) #define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32) int -- cgit v1.2.3 From 7281463f8d5d45a26f4cdff3fb67d896e0e74f74 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 9 Aug 2007 10:23:36 +1000 Subject: nouveau/nv40: add some missing pciids. --- shared-core/drm_pciids.txt | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index 126974d0..4bd690b2 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -510,8 +510,9 @@ 0x10de 0x0091 NV_40 "GeForce 7800 GTX" 0x10de 0x0092 NV_40 "GeForce 7800 GT" 0x10de 0x0093 NV_40 "GeForce 7800 GS" +0x10de 0x0095 NV_40 "GeForce 7800 SLI" 0x10de 0x0098 NV_40 "GeForce Go 7800" -0x10de 0x0099 NV_40 "GE Force Go 7800 GTX" +0x10de 0x0099 NV_40 "GeForce Go 7800 GTX" 0x10de 0x009d NV_40 "Quadro FX4500" 0x10de 0x00a0 NV_04 "Aladdin TNT2" 0x10de 0x00c0 NV_40 "GeForce 6800 GS" @@ -547,13 +548,16 @@ 0x10de 0x0113 NV_11 "Quadro2 MXR/EX/Go" 0x10de 0x0140 NV_40 "GeForce 6600 GT" 0x10de 0x0141 NV_40 "GeForce 6600" -0x10de 0x0142 NV_40 "GeForce 6600 PCIe" +0x10de 0x0142 NV_40 "GeForce 6600 LE" +0x10de 0x0143 NV_40 "GeForce 6600 VE" 0x10de 0x0144 NV_40 "GeForce Go 6600" 0x10de 0x0145 NV_40 "GeForce 6610 XL" 0x10de 0x0146 NV_40 "Geforce Go 6600TE/6200TE" +0x10de 0x0147 NV_40 "GeForce 6700 XL" 0x10de 0x0148 NV_40 "GeForce Go 6600" 0x10de 0x0149 NV_40 "GeForce Go 6600 GT" 0x10de 0x014a NV_40 "Quadro NVS 440" +0x10de 0x014c NV_40 "Quadro FX 550" 0x10de 0x014d NV_17 "Quadro FX 550" 0x10de 0x014e NV_40 "Quadro FX 540" 0x10de 0x014f NV_40 "GeForce 6200" @@ -561,6 +565,7 @@ 0x10de 0x0151 NV_15 "GeForce2 Ti" 0x10de 0x0152 NV_15 "GeForce2 Ultra, Bladerunner" 0x10de 0x0153 NV_15 "Quadro2 Pro" +0x10de 0x0160 NV_44 "GeForce 6500" 0x10de 0x0161 NV_44 "GeForce 6200 TurboCache(TM)" 0x10de 0x0162 NV_44 "GeForce 6200 SE TurboCache (TM)" 0x10de 0x0163 NV_44 "GeForce 6200 LE" @@ -569,6 +574,7 @@ 0x10de 0x0166 NV_44 "GeForce Go 6400" 0x10de 0x0167 NV_44 "GeForce Go 6200 TurboCache" 0x10de 0x0168 NV_44 "GeForce Go 6200 TurboCache" +0x10de 0x0169 NV_44 "GeForce 6250" 0x10de 0x0170 NV_17 "GeForce4 MX 460" 0x10de 0x0171 NV_17 "GeForce4 MX 440" 0x10de 0x0172 NV_17 "GeForce4 MX 420" @@ -601,11 +607,16 @@ 0x10de 0x019e NV_50 "Quadro FX 4600" 0x10de 0x01a0 NV_11|NV_NFORCE "GeForce2 MX Integrated Graphics" 0x10de 0x01d1 NV_44 "GeForce 7300 LE" +0x10de 0x01d3 NV_44 "Geforce 7300 SE" 0x10de 0x01d6 NV_44 "GeForce Go 7200" 0x10de 0x01d7 NV_44 "Quadro NVS 110M / GeForce Go 7300" 0x10de 0x01d8 NV_44 "GeForce Go 7400" +0x10de 0x01d9 NV_44 "GeForce Go 7400 GS" 0x10de 0x01da NV_44 "Quadro NVS 110M" +0x10de 0x01db NV_44 "Quadro NVS 120M" 0x10de 0x01dc NV_44 "Quadro FX 350M" +0x10de 0x01dd NV_44 "GeForce 7500 LE" +0x10de 0x01de NV_44 "Quadro FX 350" 0x10de 0x01df NV_44 "GeForce 7300 GS" 0x10de 0x01f0 NV_17|NV_NFORCE2 "GeForce4 MX - nForce GPU" 0x10de 0x0200 NV_20 "GeForce3" @@ -617,9 +628,12 @@ 0x10de 0x0215 NV_40 "GeForce 6800 GT" 0x10de 0x0218 NV_40 "GeForce 6800 XT" 0x10de 0x0221 NV_44 "GeForce 6200" +0x10de 0x0222 NV_44 "GeForce 6200 A-LE" 0x10de 0x0240 NV_44 "GeForce 6150" +0x10de 0x0241 NV_44 "GeForce 6150 LE" 0x10de 0x0242 NV_44 "GeForce 6100" -0x10de 0x0244 NV_44 "GeForce 6150 Go" +0x10de 0x0244 NV_44 "GeForce Go 6150" +0x10de 0x0247 NV_44 "GeForce Go 6100" 0x10de 0x0250 NV_25 "GeForce4 Ti 4600" 0x10de 0x0251 NV_25 "GeForce4 Ti 4400" 0x10de 0x0252 NV_25 "GeForce4 Ti" @@ -700,7 +714,15 @@ 0x10de 0x0391 NV_40 "GeForce 7600 GT" 0x10de 0x0392 NV_40 "GeForce 7600 GS" 0x10de 0x0393 NV_40 "GeForce 7300 GT" +0x10de 0x0394 NV_40 "GeForce 7600 LE" +0x10de 0x0395 NV_40 "GeForce 7300 GT" +0x10de 0x0397 NV_40 "GeForce Go 7700" 0x10de 0x0398 NV_40 "GeForce Go 7600" +0x10de 0x0399 NV_40 "GeForce Go 7600 GT" +0x10de 0x039a NV_40 "Quadro NVS 300M" +0x10de 0x039b NV_40 "GeForce Go 7900 SE" +0x10de 0x039c NV_40 "Quadro FX 550M" +0x10de 0x039e NV_40 "Quadro FX 560" 0x10de 0x03d0 NV_44 "GeForce 6100 nForce 430" 0x10de 0x03d1 NV_44 "GeForce 6100 nForce 405" 0x10de 0x03d2 NV_44 "GeForce 6100 nForce 400" -- cgit v1.2.3 From 7784e8c6e74b93ffb39d82e3385bd3268a55507c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 9 Aug 2007 11:12:13 +1000 Subject: nouveau: silence irq handler a bit --- shared-core/nouveau_irq.c | 87 +++++++++++------------------------------------ 1 file changed, 20 insertions(+), 67 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 03c466de..d8a2c1b8 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -72,12 +72,10 @@ static void nouveau_fifo_irq_handler(struct drm_device *dev) chstat = NV_READ(NV04_PFIFO_DMA); channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); - DRM_DEBUG("NV: PFIFO interrupt! Channel=%d, INTSTAT=0x%08x/MODE=0x%08x/PEND=0x%08x\n", channel, status, chmode, chstat); - if (status & NV_PFIFO_INTR_CACHE_ERROR) { uint32_t c1get, c1method, c1data; - DRM_ERROR("NV: PFIFO error interrupt\n"); + DRM_ERROR("PFIFO error interrupt\n"); c1get = NV_READ(NV03_PFIFO_CACHE1_GET) >> 2; if (dev_priv->card_type < NV_40) { @@ -89,17 +87,17 @@ static void nouveau_fifo_irq_handler(struct drm_device *dev) c1data = NV_READ(NV40_PFIFO_CACHE1_DATA(c1get)); } - DRM_ERROR("NV: Channel %d/%d - Method 0x%04x, Data 0x%08x\n", - channel, (c1method >> 13) & 7, - c1method & 0x1ffc, c1data - ); + DRM_ERROR("Channel %d/%d - Method 0x%04x, Data 0x%08x\n", + channel, (c1method >> 13) & 7, c1method & 0x1ffc, + c1data); status &= ~NV_PFIFO_INTR_CACHE_ERROR; NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); } if (status & NV_PFIFO_INTR_DMA_PUSHER) { - DRM_INFO("NV: PFIFO DMA pusher interrupt\n"); + DRM_ERROR("PFIFO DMA pusher interrupt: ch%d, 0x%08x\n", + channel, NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); status &= ~NV_PFIFO_INTR_DMA_PUSHER; NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_DMA_PUSHER); @@ -113,7 +111,7 @@ static void nouveau_fifo_irq_handler(struct drm_device *dev) } if (status) { - DRM_INFO("NV: unknown PFIFO interrupt. status=0x%08x\n", status); + DRM_ERROR("Unhandled PFIFO interrupt: status=0x%08x\n", status); NV_WRITE(NV03_PFIFO_INTR_0, status); } @@ -311,77 +309,31 @@ nouveau_graph_dump_trap_info(struct drm_device *dev) ARRAY_SIZE(nouveau_nstatus_names)); printk("\n"); - DRM_ERROR("NV: Channel %d/%d (class 0x%04x) - " - "Method 0x%04x, Data 0x%08x\n", - channel, subc, class, method, data - ); + DRM_ERROR("Channel %d/%d (class 0x%04x) - Method 0x%04x, Data 0x%08x\n", + channel, subc, class, method, data); } static void nouveau_pgraph_irq_handler(struct drm_device *dev) { - uint32_t status; struct drm_nouveau_private *dev_priv = dev->dev_private; + uint32_t status, nsource; status = NV_READ(NV03_PGRAPH_INTR); if (!status) return; + nsource = NV_READ(NV03_PGRAPH_NSOURCE); if (status & NV_PGRAPH_INTR_NOTIFY) { - uint32_t nsource, nstatus, instance, notify; - DRM_DEBUG("NV: PGRAPH notify interrupt\n"); + DRM_DEBUG("PGRAPH notify interrupt\n"); - nstatus = NV_READ(NV03_PGRAPH_NSTATUS); - nsource = NV_READ(NV03_PGRAPH_NSOURCE); - DRM_DEBUG("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus); - - /* if this wasn't NOTIFICATION_PENDING, dump extra trap info */ - if (nsource & ~(1<<0)) { - nouveau_graph_dump_trap_info(dev); - } else { - instance = NV_READ(0x00400158); - notify = NV_READ(0x00400150) >> 16; - DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n", - instance, notify); - } + nouveau_graph_dump_trap_info(dev); status &= ~NV_PGRAPH_INTR_NOTIFY; NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY); } - if (status & NV_PGRAPH_INTR_BUFFER_NOTIFY) { - uint32_t nsource, nstatus, instance, notify; - DRM_DEBUG("NV: PGRAPH buffer notify interrupt\n"); - - nstatus = NV_READ(NV03_PGRAPH_NSTATUS); - nsource = NV_READ(NV03_PGRAPH_NSOURCE); - DRM_DEBUG("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus); - - instance = NV_READ(0x00400158); - notify = NV_READ(0x00400150) >> 16; - DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n", instance, notify); - - status &= ~NV_PGRAPH_INTR_BUFFER_NOTIFY; - NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_BUFFER_NOTIFY); - } - - if (status & NV_PGRAPH_INTR_MISSING_HW) { - DRM_ERROR("NV: PGRAPH missing hw interrupt\n"); - - status &= ~NV_PGRAPH_INTR_MISSING_HW; - NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_MISSING_HW); - } - if (status & NV_PGRAPH_INTR_ERROR) { - uint32_t nsource, nstatus, instance; - - DRM_ERROR("NV: PGRAPH error interrupt\n"); - - nstatus = NV_READ(NV03_PGRAPH_NSTATUS); - nsource = NV_READ(NV03_PGRAPH_NSOURCE); - DRM_ERROR("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus); - - instance = NV_READ(0x00400158); - DRM_ERROR("instance:0x%08x\n", instance); + DRM_ERROR("PGRAPH error interrupt\n"); nouveau_graph_dump_trap_info(dev); @@ -391,7 +343,7 @@ static void nouveau_pgraph_irq_handler(struct drm_device *dev) if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) { uint32_t channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); - DRM_INFO("NV: PGRAPH context switch interrupt channel %x\n",channel); + DRM_DEBUG("PGRAPH context switch interrupt channel %x\n",channel); switch(dev_priv->card_type) { case NV_04: @@ -408,7 +360,7 @@ static void nouveau_pgraph_irq_handler(struct drm_device *dev) nouveau_nv20_context_switch(dev); break; default: - DRM_INFO("NV: Context switch not implemented\n"); + DRM_ERROR("Context switch not implemented\n"); break; } @@ -417,7 +369,7 @@ static void nouveau_pgraph_irq_handler(struct drm_device *dev) } if (status) { - DRM_INFO("NV: Unknown PGRAPH interrupt! STAT=0x%08x\n", status); + DRM_ERROR("Unhandled PGRAPH interrupt: STAT=0x%08x\n", status); NV_WRITE(NV03_PGRAPH_INTR, status); } @@ -427,6 +379,7 @@ static void nouveau_pgraph_irq_handler(struct drm_device *dev) static void nouveau_crtc_irq_handler(struct drm_device *dev, int crtc) { struct drm_nouveau_private *dev_priv = dev->dev_private; + if (crtc&1) { NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK); } @@ -446,16 +399,16 @@ irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS) if (!status) return IRQ_NONE; - DRM_DEBUG("PMC INTSTAT: 0x%08x\n", status); - if (status & NV_PMC_INTR_0_PFIFO_PENDING) { nouveau_fifo_irq_handler(dev); status &= ~NV_PMC_INTR_0_PFIFO_PENDING; } + if (status & NV_PMC_INTR_0_PGRAPH_PENDING) { nouveau_pgraph_irq_handler(dev); status &= ~NV_PMC_INTR_0_PGRAPH_PENDING; } + if (status & NV_PMC_INTR_0_CRTCn_PENDING) { nouveau_crtc_irq_handler(dev, (status>>24)&3); status &= ~NV_PMC_INTR_0_CRTCn_PENDING; -- cgit v1.2.3 From aea6b4dea9708f66f5fc2068fe84407682570aca Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Thu, 9 Aug 2007 15:30:36 -0700 Subject: Unify alloc and free ioctls. The DRM_XGI_PCIE_ALLOC and DRM_XGI_FB_ALLOC ioctls (and the matching free ioctls) are unified to DRM_XGI_ALLOC. The desired memory region is selected by xgi_mem_alloc::location. The region is magically encoded in xgi_mem_alloc::index, which is used to release the memory. Bump to version 0.11.0. This update requires a new DDX. --- shared-core/xgi_drm.h | 46 +++++++++++++++++++++++++++++----------------- 1 file changed, 29 insertions(+), 17 deletions(-) (limited to 'shared-core') diff --git a/shared-core/xgi_drm.h b/shared-core/xgi_drm.h index adce7066..c980a35a 100644 --- a/shared-core/xgi_drm.h +++ b/shared-core/xgi_drm.h @@ -60,10 +60,20 @@ enum xgi_mem_location { }; struct xgi_mem_alloc { + /** + * Memory region to be used for allocation. + * + * Must be one of XGI_MEMLOC_NON_LOCAL or XGI_MEMLOC_LOCAL. + */ unsigned int location; + + /** + * Number of bytes request. + * + * On successful allocation, set to the actual number of bytes + * allocated. + */ unsigned int size; - unsigned int is_front; - unsigned int owner; /** * Address of the memory from the graphics hardware's point of view. @@ -74,6 +84,13 @@ struct xgi_mem_alloc { * Offset of the allocation in the mapping. */ __u32 offset; + + /** + * Magic handle used to release memory. + * + * See also DRM_XGI_FREE ioctl. + */ + unsigned long index; }; enum xgi_batch_type { @@ -102,24 +119,19 @@ struct xgi_state_info { */ #define DRM_XGI_BOOTSTRAP 0 -#define DRM_XGI_FB_ALLOC 1 -#define DRM_XGI_FB_FREE 2 -#define DRM_XGI_PCIE_ALLOC 3 -#define DRM_XGI_PCIE_FREE 4 -#define DRM_XGI_SUBMIT_CMDLIST 5 -#define DRM_XGI_GE_RESET 6 -#define DRM_XGI_DUMP_REGISTER 7 -#define DRM_XGI_DEBUG_INFO 8 -#define DRM_XGI_TEST_RWINKERNEL 9 -#define DRM_XGI_STATE_CHANGE 10 +#define DRM_XGI_ALLOC 1 +#define DRM_XGI_FREE 2 +#define DRM_XGI_SUBMIT_CMDLIST 3 +#define DRM_XGI_GE_RESET 4 +#define DRM_XGI_DUMP_REGISTER 5 +#define DRM_XGI_DEBUG_INFO 6 +#define DRM_XGI_TEST_RWINKERNEL 7 +#define DRM_XGI_STATE_CHANGE 8 #define XGI_IOCTL_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_XGI_BOOTSTRAP, struct xgi_bootstrap) -#define XGI_IOCTL_FB_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_XGI_FB_ALLOC, struct xgi_mem_alloc) -#define XGI_IOCTL_FB_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_FB_FREE, __u32) - -#define XGI_IOCTL_PCIE_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_XGI_PCIE_ALLOC, struct xgi_mem_alloc) -#define XGI_IOCTL_PCIE_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_PCIE_FREE, __u32) +#define XGI_IOCTL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_XGI_ALLOC, struct xgi_mem_alloc) +#define XGI_IOCTL_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_FREE, __u32) #define XGI_IOCTL_GE_RESET DRM_IO(DRM_COMMAND_BASE + DRM_XGI_GE_RESET) #define XGI_IOCTL_DUMP_REGISTER DRM_IO(DRM_COMMAND_BASE + DRM_XGI_DUMP_REGISTER) -- cgit v1.2.3 From 39907f613b6c84499c34c9a6ece5f5dde64788c0 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 10 Aug 2007 13:53:10 +1000 Subject: nouveau: Allow creation of gpuobjs before any other init has taken place. --- shared-core/nouveau_drv.h | 2 ++ shared-core/nouveau_object.c | 26 ++++++++++++++++++++++++-- shared-core/nouveau_state.c | 5 ++++- 3 files changed, 30 insertions(+), 3 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 572df46e..4d5c7f7e 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -370,8 +370,10 @@ extern int nouveau_fifo_alloc(struct drm_device *dev, extern void nouveau_fifo_free(struct nouveau_channel *); /* nouveau_object.c */ +extern int nouveau_gpuobj_early_init(struct drm_device *); extern int nouveau_gpuobj_init(struct drm_device *); extern void nouveau_gpuobj_takedown(struct drm_device *); +extern void nouveau_gpuobj_late_takedown(struct drm_device *); extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, uint32_t vram_h, uint32_t tt_h); extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index bb096531..d4142e44 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -264,12 +264,26 @@ nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan, return 0; } +int +nouveau_gpuobj_early_init(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + + DRM_DEBUG("\n"); + + INIT_LIST_HEAD(&dev_priv->gpuobj_list); + + return 0; +} + int nouveau_gpuobj_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; + DRM_DEBUG("\n"); + if (dev_priv->card_type < NV_50) { if ((ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramht_offset, dev_priv->ramht_size, @@ -286,12 +300,20 @@ void nouveau_gpuobj_takedown(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_gpuobj *gpuobj = NULL; - struct list_head *entry, *tmp; DRM_DEBUG("\n"); nouveau_gpuobj_del(dev, &dev_priv->ramht); +} + +void +nouveau_gpuobj_late_takedown(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_gpuobj *gpuobj = NULL; + struct list_head *entry, *tmp; + + DRM_DEBUG("\n"); list_for_each_safe(entry, tmp, &dev_priv->gpuobj_list) { gpuobj = list_entry(entry, struct nouveau_gpuobj, list); diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index e80e77a5..eac38060 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -296,7 +296,8 @@ nouveau_card_init(struct drm_device *dev) engine = &dev_priv->Engine; dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED; - INIT_LIST_HEAD(&dev_priv->gpuobj_list); + ret = nouveau_gpuobj_early_init(dev); + if (ret) return ret; /* Initialise instance memory, must happen before mem_init so we * know exactly how much VRAM we're able to use for "normal" @@ -375,6 +376,8 @@ static void nouveau_card_takedown(struct drm_device *dev) drm_irq_uninstall(dev); + nouveau_gpuobj_late_takedown(dev); + dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN; } } -- cgit v1.2.3 From a46104674f129e873b8dfa29cf8aac9c67bd77be Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 10 Aug 2007 13:54:26 +1000 Subject: nouveau/nv50: demagic instmem setup. --- shared-core/nouveau_drv.h | 3 +- shared-core/nouveau_fifo.c | 2 - shared-core/nouveau_object.c | 50 ++++++--- shared-core/nouveau_reg.h | 10 ++ shared-core/nv04_fifo.c | 2 +- shared-core/nv10_fifo.c | 2 +- shared-core/nv40_fifo.c | 2 +- shared-core/nv50_fifo.c | 37 +++---- shared-core/nv50_instmem.c | 246 ++++++++++++++++++++++++++----------------- 9 files changed, 217 insertions(+), 137 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 4d5c7f7e..e3d0ff4c 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -393,7 +393,8 @@ extern int nouveau_gpuobj_new_ref(struct drm_device *, struct nouveau_channel *ref_chan, uint32_t handle, int size, int align, uint32_t flags, struct nouveau_gpuobj_ref **); -extern int nouveau_gpuobj_new_fake(struct drm_device *, uint32_t offset, +extern int nouveau_gpuobj_new_fake(struct drm_device *, + uint32_t p_offset, uint32_t b_offset, uint32_t size, uint32_t flags, struct nouveau_gpuobj **, struct nouveau_gpuobj_ref**); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 22bced14..f0c2a556 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -285,8 +285,6 @@ nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, * When there are no more contexts, you lost */ for(channel=0; channelcard_type == NV_50) && (channel == 0)) - continue; if (dev_priv->fifos[channel] == NULL) break; } diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index d4142e44..e0cb334f 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -72,6 +72,8 @@ nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle) uint32_t hash = 0; int i; + DRM_DEBUG("ch%d handle=0x%08x\n", channel, handle); + for (i=32;i>0;i-=dev_priv->ramht_bits) { hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1)); handle >>= dev_priv->ramht_bits; @@ -80,7 +82,7 @@ nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle) hash ^= channel << (dev_priv->ramht_bits - 4); hash <<= 3; - DRM_DEBUG("ch%d handle=0x%08x hash=0x%08x\n", channel, handle, hash); + DRM_DEBUG("hash=0x%08x\n", hash); return hash; } @@ -286,7 +288,7 @@ nouveau_gpuobj_init(struct drm_device *dev) if (dev_priv->card_type < NV_50) { if ((ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramht_offset, - dev_priv->ramht_size, + ~0, dev_priv->ramht_size, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ALLOW_NO_REFS, &dev_priv->ramht, NULL))) @@ -346,7 +348,13 @@ nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj) if (gpuobj->dtor) gpuobj->dtor(dev, gpuobj); - engine->instmem.clear(dev, gpuobj); + if (gpuobj->im_backing) { + if (gpuobj->flags & NVOBJ_FLAG_FAKE) + drm_free(gpuobj->im_backing, + sizeof(*gpuobj->im_backing), DRM_MEM_DRIVER); + else + engine->instmem.clear(dev, gpuobj); + } if (gpuobj->im_pramin) { if (gpuobj->flags & NVOBJ_FLAG_FAKE) @@ -525,7 +533,8 @@ nouveau_gpuobj_ref_find(struct nouveau_channel *chan, uint32_t handle, } int -nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t offset, uint32_t size, +nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t p_offset, + uint32_t b_offset, uint32_t size, uint32_t flags, struct nouveau_gpuobj **pgpuobj, struct nouveau_gpuobj_ref **pref) { @@ -533,8 +542,8 @@ nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t offset, uint32_t size, struct nouveau_gpuobj *gpuobj = NULL; int i; - DRM_DEBUG("offset=0x%08x size=0x%08x flags=0x%08x\n", - offset, size, flags); + DRM_DEBUG("p_offset=0x%08x b_offset=0x%08x size=0x%08x flags=0x%08x\n", + p_offset, b_offset, size, flags); gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER); if (!gpuobj) @@ -545,14 +554,27 @@ nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t offset, uint32_t size, list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list); - gpuobj->im_pramin = drm_calloc(1, sizeof(struct mem_block), - DRM_MEM_DRIVER); - if (!gpuobj->im_pramin) { - nouveau_gpuobj_del(dev, &gpuobj); - return -ENOMEM; + if (p_offset != ~0) { + gpuobj->im_pramin = drm_calloc(1, sizeof(struct mem_block), + DRM_MEM_DRIVER); + if (!gpuobj->im_pramin) { + nouveau_gpuobj_del(dev, &gpuobj); + return -ENOMEM; + } + gpuobj->im_pramin->start = p_offset; + gpuobj->im_pramin->size = size; + } + + if (b_offset != ~0) { + gpuobj->im_backing = drm_calloc(1, sizeof(struct mem_block), + DRM_MEM_DRIVER); + if (!gpuobj->im_backing) { + nouveau_gpuobj_del(dev, &gpuobj); + return -ENOMEM; + } + gpuobj->im_backing->start = b_offset; + gpuobj->im_backing->size = size; } - gpuobj->im_pramin->start = offset; - gpuobj->im_pramin->size = size; if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) { for (i = 0; i < gpuobj->im_pramin->size; i += 4) @@ -962,7 +984,7 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, vm_offset = (dev_priv->chipset & 0xf0) == 0x50 ? 0x1400 : 0x200; vm_offset += chan->ramin->gpuobj->im_pramin->start; - if ((ret = nouveau_gpuobj_new_fake(dev, vm_offset, 0x4000, + if ((ret = nouveau_gpuobj_new_fake(dev, vm_offset, ~0, 0x4000, 0, &chan->vm_pd, NULL))) return ret; for (i=0; i<0x4000; i+=8) { diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 47d54b2a..65614627 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -80,6 +80,16 @@ #define NV40_PMC_1708 0x00001708 #define NV40_PMC_170C 0x0000170C +/* probably PMC ? */ +#define NV50_PUNK_BAR0_PRAMIN 0x00001700 +#define NV50_PUNK_BAR_CFG_BASE 0x00001704 +#define NV50_PUNK_BAR_CFG_BASE_VALID (1<<30) +#define NV50_PUNK_BAR1_CTXDMA 0x00001708 +#define NV50_PUNK_BAR1_CTXDMA_VALID (1<<31) +#define NV50_PUNK_BAR3_CTXDMA 0x0000170C +#define NV50_PUNK_BAR3_CTXDMA_VALID (1<<31) +#define NV50_PUNK_UNK1710 0x00001710 + #define NV04_PTIMER_INTR_0 0x00009100 #define NV04_PTIMER_INTR_EN_0 0x00009140 #define NV04_PTIMER_NUMERATOR 0x00009200 diff --git a/shared-core/nv04_fifo.c b/shared-core/nv04_fifo.c index 4d61f4fe..d750ced8 100644 --- a/shared-core/nv04_fifo.c +++ b/shared-core/nv04_fifo.c @@ -42,7 +42,7 @@ nv04_fifo_create_context(struct nouveau_channel *chan) struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; - if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), + if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), ~0, NV04_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c index a056460d..c86725d2 100644 --- a/shared-core/nv10_fifo.c +++ b/shared-core/nv10_fifo.c @@ -43,7 +43,7 @@ nv10_fifo_create_context(struct nouveau_channel *chan) struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; - if ((ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id), + if ((ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id), ~0, NV10_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c index f04c2882..eb160ee2 100644 --- a/shared-core/nv40_fifo.c +++ b/shared-core/nv40_fifo.c @@ -43,7 +43,7 @@ nv40_fifo_create_context(struct nouveau_channel *chan) struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; - if ((ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), + if ((ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), ~0, NV40_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index f915d332..71b89d6d 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -30,7 +30,6 @@ typedef struct { struct nouveau_gpuobj_ref *thingo; - struct nouveau_gpuobj_ref *dummyctx; } nv50_fifo_priv; #define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50) @@ -47,7 +46,7 @@ nv50_fifo_init_thingo(struct drm_device *dev) INSTANCE_WR(thingo->gpuobj, 0, 0x7e); INSTANCE_WR(thingo->gpuobj, 1, 0x7e); - for (i = 0; i fifos[i]) { INSTANCE_WR(thingo->gpuobj, fi, i); fi++; @@ -60,7 +59,7 @@ nv50_fifo_init_thingo(struct drm_device *dev) } static int -nv50_fifo_channel_enable(struct drm_device *dev, int channel) +nv50_fifo_channel_enable(struct drm_device *dev, int channel, int nt) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_channel *chan = dev_priv->fifos[channel]; @@ -83,7 +82,7 @@ nv50_fifo_channel_enable(struct drm_device *dev, int channel) NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); } - nv50_fifo_init_thingo(dev); + if (!nt) nv50_fifo_init_thingo(dev); return 0; } @@ -156,18 +155,9 @@ static int nv50_fifo_init_regs(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; - int ret; DRM_DEBUG("\n"); - if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 0x1000, - 0x1000, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ZERO_FREE, - &priv->dummyctx))) - return ret; - NV_WRITE(0x2500, 0); NV_WRITE(0x3250, 0); NV_WRITE(0x3220, 0); @@ -175,13 +165,9 @@ nv50_fifo_init_regs(struct drm_device *dev) NV_WRITE(0x3210, 0); NV_WRITE(0x3270, 0); - if (IS_G80) { - NV_WRITE(0x2600, (priv->dummyctx->instance>>8) | (1<<31)); - NV_WRITE(0x27fc, (priv->dummyctx->instance>>8) | (1<<31)); - } else { - NV_WRITE(0x2600, (priv->dummyctx->instance>>12) | (1<<31)); - NV_WRITE(0x27fc, (priv->dummyctx->instance>>12) | (1<<31)); - } + /* Enable dummy channels setup by nv50_instmem.c */ + nv50_fifo_channel_enable(dev, 0, 1); + nv50_fifo_channel_enable(dev, 127, 1); return 0; } @@ -209,6 +195,7 @@ nv50_fifo_init(struct drm_device *dev) DRM_ERROR("error creating thingo: %d\n", ret); return ret; } + nv50_fifo_init_context_table(dev); nv50_fifo_init_regs__nv(dev); @@ -230,7 +217,6 @@ nv50_fifo_takedown(struct drm_device *dev) return; nouveau_gpuobj_ref_del(dev, &priv->thingo); - nouveau_gpuobj_ref_del(dev, &priv->dummyctx); dev_priv->Engine.fifo.priv = NULL; drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER); @@ -248,7 +234,7 @@ nv50_fifo_create_context(struct nouveau_channel *chan) if (IS_G80) { uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start; - if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, 0x100, + if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, ~0, 0x100, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, &ramfc, &chan->ramfc))) @@ -285,7 +271,7 @@ nv50_fifo_create_context(struct nouveau_channel *chan) INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12); } - if ((ret = nv50_fifo_channel_enable(dev, chan->id))) { + if ((ret = nv50_fifo_channel_enable(dev, chan->id, 0))) { DRM_ERROR("error enabling ch%d: %d\n", chan->id, ret); nouveau_gpuobj_ref_del(dev, &chan->ramfc); return ret; @@ -302,6 +288,11 @@ nv50_fifo_destroy_context(struct nouveau_channel *chan) DRM_DEBUG("ch%d\n", chan->id); nv50_fifo_channel_disable(dev, chan->id, 0); + + /* Dummy channel, also used on ch 127 */ + if (chan->id == 0) + nv50_fifo_channel_disable(dev, 127, 0); + nouveau_gpuobj_ref_del(dev, &chan->ramfc); } diff --git a/shared-core/nv50_instmem.c b/shared-core/nv50_instmem.c index c26b1db5..1eeb54df 100644 --- a/shared-core/nv50_instmem.c +++ b/shared-core/nv50_instmem.c @@ -31,118 +31,162 @@ typedef struct { uint32_t save1700[5]; /* 0x1700->0x1710 */ + + struct nouveau_gpuobj_ref *pramin_pt; + struct nouveau_gpuobj_ref *pramin_bar; } nv50_instmem_priv; #define NV50_INSTMEM_PAGE_SHIFT 12 #define NV50_INSTMEM_PAGE_SIZE (1 << NV50_INSTMEM_PAGE_SHIFT) -#define NV50_INSTMEM_RSVD_SIZE (64 * 1024) #define NV50_INSTMEM_PT_SIZE(a) (((a) >> 12) << 3) +/*NOTE: - Assumes 0x1700 already covers the correct MiB of PRAMIN + */ +#define BAR0_WI32(g,o,v) do { \ + uint32_t offset; \ + if ((g)->im_backing) { \ + offset = (g)->im_backing->start; \ + } else { \ + offset = chan->ramin->gpuobj->im_backing->start; \ + offset += (g)->im_pramin->start; \ + } \ + offset += (o); \ + NV_WRITE(NV_RAMIN + (offset & 0xfffff), (v)); \ +} while(0) + int nv50_instmem_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_channel *chan; + uint32_t c_offset, c_size, c_ramfc, c_vmpd, c_base, pt_size; nv50_instmem_priv *priv; - uint32_t rv, pt, pts, cb, cb0, cb1, unk, as; - uint32_t i, v; - int ret; + int ret, i; + uint32_t v; priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER); if (!priv) return -ENOMEM; dev_priv->Engine.instmem.priv = priv; - /* Save current state */ - for (i = 0x1700; i <= 0x1710; i+=4) - priv->save1700[(i-0x1700)/4] = NV_READ(i); - - as = dev_priv->ramin->size; - rv = nouveau_mem_fb_amount(dev) - (1*1024*1024); - pt = rv + 0xd0000; - pts = NV50_INSTMEM_PT_SIZE(as); - cb = rv + 0xc8000; - if ((dev_priv->chipset & 0xf0) != 0x50) { - unk = cb + 0x4200; - cb0 = cb + 0x4240; - cb1 = cb + 0x278; - } else { - unk = cb + 0x5400; - cb0 = cb + 0x5440; - cb1 = cb + 0x1478; - } - - DRM_DEBUG("PRAMIN config:\n"); - DRM_DEBUG(" Rsvd VRAM base: 0x%08x\n", rv); - DRM_DEBUG(" Aperture size: %i MiB\n", as >> 20); - DRM_DEBUG(" PT base: 0x%08x\n", pt); - DRM_DEBUG(" PT size: %d KiB\n", pts >> 10); - DRM_DEBUG(" BIOS image: 0x%08x\n", (NV_READ(0x619f04)&~0xff)<<8); - DRM_DEBUG(" Config base: 0x%08x\n", cb); - DRM_DEBUG(" ctxdma Config0: 0x%08x\n", cb0); - DRM_DEBUG(" Config1: 0x%08x\n", cb1); - - /* Map first MiB of reserved vram into BAR0 PRAMIN aperture */ - NV_WRITE(0x1700, (rv>>16)); - /* Poke some regs.. */ - NV_WRITE(0x1704, (cb>>12)); - NV_WRITE(0x1710, (((unk-cb)>>4))|(1<<31)); - NV_WRITE(0x1704, (cb>>12)|(1<<30)); - - /* CB0, some DMA object, NFI what it points at... Needed however, - * or the PRAMIN aperture doesn't operate as expected. + /* Reserve the last MiB of VRAM, we should probably try to avoid + * setting up the below tables over the top of the VBIOS image at + * some point. */ - NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x00, 0x7fc00000); - NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x04, 0xe1ffffff); - NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x08, 0xe0000000); - NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x0c, 0x01000001); - NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x10, 0x00000000); - NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x14, 0x00000000); - - /* CB1, points at PRAMIN PT */ - NV_WRITE(NV_RAMIN + (cb1 - rv) + 0, pt | 0x63); - NV_WRITE(NV_RAMIN + (cb1 - rv) + 4, 0x00000000); - - /* Zero PRAMIN page table */ - v = NV_RAMIN + (pt - rv); - for (i = v; i < v + pts; i += 8) { - NV_WRITE(i + 0x00, 0x00000009); - NV_WRITE(i + 0x04, 0x00000000); - } + dev_priv->ramin_rsvd_vram = 1 << 20; + c_offset = nouveau_mem_fb_amount(dev) - dev_priv->ramin_rsvd_vram; + c_size = 128 << 10; + c_vmpd = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x1400 : 0x200; + c_ramfc = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x0 : 0x20; + c_base = c_vmpd + 0x4000; + pt_size = NV50_INSTMEM_PT_SIZE(dev_priv->ramin->size); + + DRM_DEBUG(" Rsvd VRAM base: 0x%08x\n", c_offset); + DRM_DEBUG(" VBIOS image: 0x%08x\n", (NV_READ(0x619f04)&~0xff)<<8); + DRM_DEBUG(" Aperture size: %d MiB\n", + (uint32_t)dev_priv->ramin->size >> 20); + DRM_DEBUG(" PT size: %d KiB\n", pt_size >> 10); + + NV_WRITE(NV50_PUNK_BAR0_PRAMIN, (c_offset >> 16)); + + /* Create a fake channel, and use it as our "dummy" channels 0/127. + * The main reason for creating a channel is so we can use the gpuobj + * code. However, it's probably worth noting that NVIDIA also setup + * their channels 0/127 with the same values they configure here. + * So, there may be some other reason for doing this. + * + * Have to create the entire channel manually, as the real channel + * creation code assumes we have PRAMIN access, and we don't until + * we're done here. + */ + chan = drm_calloc(1, sizeof(*chan), DRM_MEM_DRIVER); + if (!chan) + return -ENOMEM; + chan->id = 0; + chan->dev = dev; + chan->file_priv = (struct drm_file *)-2; + dev_priv->fifos[0] = dev_priv->fifos[127] = chan; - /* Map page table into PRAMIN aperture */ - for (i = pt; i < pt + pts; i += 0x1000) { - uint32_t pte = NV_RAMIN + (pt-rv) + (((i-pt) >> 12) << 3); - DRM_DEBUG("PRAMIN PTE = 0x%08x @ 0x%08x\n", i, pte); - NV_WRITE(pte + 0x00, i | 1); - NV_WRITE(pte + 0x04, 0x00000000); - } + /* Channel's PRAMIN object + heap */ + if ((ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, 128<<10, 0, + NULL, &chan->ramin))) + return ret; - /* Points at CB0 */ - NV_WRITE(0x170c, (((cb0 - cb)>>4)|(1<<31))); + if (nouveau_mem_init_heap(&chan->ramin_heap, c_base, c_size - c_base)) + return -ENOMEM; + + /* RAMFC + zero channel's PRAMIN up to start of VM pagedir */ + if ((ret = nouveau_gpuobj_new_fake(dev, c_ramfc, c_offset + c_ramfc, + 0x4000, 0, NULL, &chan->ramfc))) + return ret; + + for (i = 0; i < c_vmpd; i += 4) + BAR0_WI32(chan->ramin->gpuobj, i, 0); + + /* VM page directory */ + if ((ret = nouveau_gpuobj_new_fake(dev, c_vmpd, c_offset + c_vmpd, + 0x4000, 0, &chan->vm_pd, NULL))) + return ret; + for (i = 0; i < 0x4000; i += 8) { + BAR0_WI32(chan->vm_pd, i + 0x00, 0x00000000); + BAR0_WI32(chan->vm_pd, i + 0x04, 0x00000000); + } - /* Confirm it all worked, should be able to read back the page table's - * PTEs from the PRAMIN BAR + /* PRAMIN page table, cheat and map into VM at 0x0000000000. + * We map the entire fake channel into the start of the PRAMIN BAR */ - NV_WRITE(0x1700, pt >> 16); - if (NV_READ(0x700000) != NV_RI32(0)) { - DRM_ERROR("Failed to init PRAMIN page table\n"); - return -EINVAL; + if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pt_size, 0x1000, + 0, &priv->pramin_pt))) + return ret; + + for (i = 0, v = c_offset; i < pt_size; i+=8, v+=0x1000) { + if (v < (c_offset + c_size)) + BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v | 1); + else + BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000009); + BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000); } - /* Create a heap to manage PRAMIN aperture allocations */ - ret = nouveau_mem_init_heap(&dev_priv->ramin_heap, pts, as-pts); - if (ret) { - DRM_ERROR("Failed to init PRAMIN heap\n"); - return -ENOMEM; + BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63); + BAR0_WI32(chan->vm_pd, 0x04, 0x00000000); + + /* DMA object for PRAMIN BAR */ + if ((ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 6*4, 16, 0, + &priv->pramin_bar))) + return ret; + BAR0_WI32(priv->pramin_bar->gpuobj, 0x00, 0x7fc00000); + BAR0_WI32(priv->pramin_bar->gpuobj, 0x04, dev_priv->ramin->size - 1); + BAR0_WI32(priv->pramin_bar->gpuobj, 0x08, 0x00000000); + BAR0_WI32(priv->pramin_bar->gpuobj, 0x0c, 0x00000000); + BAR0_WI32(priv->pramin_bar->gpuobj, 0x10, 0x00000000); + BAR0_WI32(priv->pramin_bar->gpuobj, 0x14, 0x00000000); + + /* Poke the relevant regs, and pray it works :) */ + NV_WRITE(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12)); + NV_WRITE(NV50_PUNK_UNK1710, 0); + NV_WRITE(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) | + NV50_PUNK_BAR_CFG_BASE_VALID); + NV_WRITE(NV50_PUNK_BAR1_CTXDMA, 0); + NV_WRITE(NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) | + NV50_PUNK_BAR3_CTXDMA_VALID); + + /* Assume that praying isn't enough, check that we can re-read the + * entire fake channel back from the PRAMIN BAR */ + for (i = 0; i < c_size; i+=4) { + if (NV_READ(NV_RAMIN + i) != NV_RI32(i)) { + DRM_ERROR("Error reading back PRAMIN at 0x%08x\n", i); + return -EINVAL; + } } - DRM_DEBUG("NV50: PRAMIN setup ok\n"); - /* Don't alloc the last MiB of VRAM, probably too much, but be safe - * at least for now. - */ - dev_priv->ramin_rsvd_vram = 1*1024*1024; + /* Global PRAMIN heap */ + if (nouveau_mem_init_heap(&dev_priv->ramin_heap, + c_size, dev_priv->ramin->size - c_size)) { + dev_priv->ramin_heap = NULL; + DRM_ERROR("Failed to init RAMIN heap\n"); + } - /*XXX: probably incorrect, but needed to make hash func "work" */ + /*XXX: incorrect, but needed to make hash func "work" */ dev_priv->ramht_offset = 0x10000; dev_priv->ramht_bits = 9; dev_priv->ramht_size = (1 << dev_priv->ramht_bits); @@ -154,8 +198,11 @@ nv50_instmem_takedown(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv; + struct nouveau_channel *chan = dev_priv->fifos[0]; int i; + DRM_DEBUG("\n"); + if (!priv) return; @@ -163,6 +210,20 @@ nv50_instmem_takedown(struct drm_device *dev) for (i = 0x1700; i <= 0x1710; i+=4) NV_WRITE(i, priv->save1700[(i-0x1700)/4]); + nouveau_gpuobj_ref_del(dev, &priv->pramin_bar); + nouveau_gpuobj_ref_del(dev, &priv->pramin_pt); + + /* Destroy dummy channel */ + if (chan) { + nouveau_gpuobj_del(dev, &chan->vm_pd); + nouveau_gpuobj_ref_del(dev, &chan->ramfc); + nouveau_gpuobj_ref_del(dev, &chan->ramin); + nouveau_mem_takedown(&chan->ramin_heap); + + dev_priv->fifos[0] = dev_priv->fifos[127] = NULL; + drm_free(chan, sizeof(*chan), DRM_MEM_DRIVER); + } + dev_priv->Engine.instmem.priv = NULL; drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER); } @@ -205,6 +266,7 @@ int nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { struct drm_nouveau_private *dev_priv = dev->dev_private; + nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv; uint32_t pte, pte_end, vram; if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound) @@ -217,19 +279,14 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte; vram = gpuobj->im_backing->start; - if (pte == pte_end) { - DRM_ERROR("WARNING: badness in bind() pte calc\n"); - pte_end++; - } - DRM_DEBUG("pramin=0x%llx, pte=%d, pte_end=%d\n", gpuobj->im_pramin->start, pte, pte_end); DRM_DEBUG("first vram page: 0x%llx\n", gpuobj->im_backing->start); while (pte < pte_end) { - NV_WI32(pte + 0, vram | 1); - NV_WI32(pte + 4, 0x00000000); + INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 0)/4, vram | 1); + INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000); pte += 8; vram += NV50_INSTMEM_PAGE_SIZE; @@ -243,6 +300,7 @@ int nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { struct drm_nouveau_private *dev_priv = dev->dev_private; + nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv; uint32_t pte, pte_end; if (gpuobj->im_bound == 0) @@ -251,8 +309,8 @@ nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) pte = (gpuobj->im_pramin->start >> 12) << 3; pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte; while (pte < pte_end) { - NV_WI32(pte + 0, 0x00000000); - NV_WI32(pte + 4, 0x00000000); + INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 0)/4, 0x00000009); + INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000); pte += 8; } -- cgit v1.2.3 From da279868706cc799bdf25cdd5523d11fda64d4cc Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 6 Aug 2007 18:33:29 +1000 Subject: i915: i965 non-secure batchbuffer bit has moved. --- shared-core/i915_dma.c | 10 ++++++++-- shared-core/i915_drv.h | 2 ++ 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 5d227d8b..9f18feee 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -546,9 +546,15 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev, if (dev_priv->use_mi_batchbuffer_start) { BEGIN_LP_RING(2); - OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); - OUT_RING(batch->start | MI_BATCH_NON_SECURE); + if (IS_I965G(dev)) { + OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); + OUT_RING(batch->start); + } else { + OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); + OUT_RING(batch->start | MI_BATCH_NON_SECURE); + } ADVANCE_LP_RING(); + } else { BEGIN_LP_RING(4); OUT_RING(MI_BATCH_BUFFER); diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index e641fdc6..528f7b3a 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -364,6 +364,8 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); #define MI_BATCH_BUFFER_END (0xA<<23) #define MI_BATCH_NON_SECURE (1) +#define MI_BATCH_NON_SECURE_I965 (1<<8) + #define MI_WAIT_FOR_EVENT ((0x3<<23)) #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) -- cgit v1.2.3 From 02c4e0e757b69cd6ae38b8ab2c078b3f06fea661 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 15 Aug 2007 00:56:24 +1000 Subject: nouveau/nv40: Fix channel scheduling. Ensure NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLE gets set, otherwise channels will appear to "freeze" in some circumstances. --- shared-core/nouveau_drv.h | 1 + shared-core/nouveau_state.c | 2 +- shared-core/nv40_fifo.c | 13 +++++++++++++ 3 files changed, 15 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index e3d0ff4c..b7459b1b 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -455,6 +455,7 @@ extern int nv10_fifo_load_context(struct nouveau_channel *); extern int nv10_fifo_save_context(struct nouveau_channel *); /* nv40_fifo.c */ +extern int nv40_fifo_init(struct drm_device *); extern int nv40_fifo_create_context(struct nouveau_channel *); extern void nv40_fifo_destroy_context(struct nouveau_channel *); extern int nv40_fifo_load_context(struct nouveau_channel *); diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index eac38060..d885f7c6 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -224,7 +224,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) engine->graph.destroy_context = nv40_graph_destroy_context; engine->graph.load_context = nv40_graph_load_context; engine->graph.save_context = nv40_graph_save_context; - engine->fifo.init = nouveau_fifo_init; + engine->fifo.init = nv40_fifo_init; engine->fifo.takedown = nouveau_stub_takedown; engine->fifo.create_context = nv40_fifo_create_context; engine->fifo.destroy_context = nv40_fifo_destroy_context; diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c index eb160ee2..ce3f8fdd 100644 --- a/shared-core/nv40_fifo.c +++ b/shared-core/nv40_fifo.c @@ -193,3 +193,16 @@ nv40_fifo_save_context(struct nouveau_channel *chan) return 0; } +int +nv40_fifo_init(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int ret; + + if ((ret = nouveau_fifo_init(dev))) + return ret; + + NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff); + return 0; +} + -- cgit v1.2.3 From a6ea60c77e8d4a266d696e0d99c11b1f39578dcc Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 15 Aug 2007 01:40:46 +1000 Subject: nouveau: Catch all NV4x chips instead of just NV_40. --- shared-core/nv04_instmem.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index 5e0f6f4e..b5569b55 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -9,21 +9,18 @@ nv04_instmem_determine_amount(struct drm_device *dev) int i; /* Figure out how much instance memory we need */ - switch (dev_priv->card_type) { - case NV_40: + if (dev_priv->card_type >= NV_40) { /* We'll want more instance memory than this on some NV4x cards. * There's a 16MB aperture to play with that maps onto the end * of vram. For now, only reserve a small piece until we know * more about what each chipset requires. */ dev_priv->ramin_rsvd_vram = (1*1024* 1024); - break; - default: + } else { /*XXX: what *are* the limits on ramin_rsvd_vram = (512*1024); - break; } DRM_DEBUG("RAMIN size: %dKiB\n", dev_priv->ramin_rsvd_vram>>10); -- cgit v1.2.3 From f563a50d145848ed296b63c63422caff80232ddf Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 14 Aug 2007 13:44:51 -0700 Subject: Eliminate unused / useless ioctls. --- shared-core/xgi_drm.h | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) (limited to 'shared-core') diff --git a/shared-core/xgi_drm.h b/shared-core/xgi_drm.h index c980a35a..d8715df5 100644 --- a/shared-core/xgi_drm.h +++ b/shared-core/xgi_drm.h @@ -122,22 +122,12 @@ struct xgi_state_info { #define DRM_XGI_ALLOC 1 #define DRM_XGI_FREE 2 #define DRM_XGI_SUBMIT_CMDLIST 3 -#define DRM_XGI_GE_RESET 4 -#define DRM_XGI_DUMP_REGISTER 5 -#define DRM_XGI_DEBUG_INFO 6 -#define DRM_XGI_TEST_RWINKERNEL 7 -#define DRM_XGI_STATE_CHANGE 8 +#define DRM_XGI_STATE_CHANGE 4 #define XGI_IOCTL_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_XGI_BOOTSTRAP, struct xgi_bootstrap) - #define XGI_IOCTL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_XGI_ALLOC, struct xgi_mem_alloc) #define XGI_IOCTL_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_FREE, __u32) - -#define XGI_IOCTL_GE_RESET DRM_IO(DRM_COMMAND_BASE + DRM_XGI_GE_RESET) -#define XGI_IOCTL_DUMP_REGISTER DRM_IO(DRM_COMMAND_BASE + DRM_XGI_DUMP_REGISTER) -#define XGI_IOCTL_DEBUG_INFO DRM_IO(DRM_COMMAND_BASE + DRM_XGI_DEBUG_INFO) #define XGI_IOCTL_SUBMIT_CMDLIST DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_SUBMIT_CMDLIST, struct xgi_cmd_info) -#define XGI_IOCTL_TEST_RWINKERNEL DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_TEST_RWINKERNEL, __u32) #define XGI_IOCTL_STATE_CHANGE DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_STATE_CHANGE, struct xgi_state_info) #endif /* _XGI_DRM_H_ */ -- cgit v1.2.3 From ee01d3755ac03f2c47e3b4d9bf084d68e6ee95bc Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 15 Aug 2007 13:34:57 +1000 Subject: nouveau: Workaround mysterious PRAMIN clobbering by the card. --- shared-core/nv04_instmem.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index b5569b55..fed6ff7e 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -94,6 +94,14 @@ int nv04_instmem_init(struct drm_device *dev) * the space that was reserved for RAMHT/FC/RO. */ offset = dev_priv->ramfc_offset + dev_priv->ramfc_size; + + /* On my NV4E, there's *something* clobbering the 16KiB just after + * where we setup these fixed tables. No idea what it is just yet, + * so reserve this space on all NV4X cards for now. + */ + if (dev_priv->card_type >= NV_40) + offset += 16*1024; + ret = nouveau_mem_init_heap(&dev_priv->ramin_heap, offset, dev_priv->ramin_rsvd_vram - offset); if (ret) { -- cgit v1.2.3 From c3faa589b09616acdfd827be1719f6c2706c49ab Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 15 Aug 2007 13:36:54 +1000 Subject: nouveau: Allow GART notifiers when using sgdma code. --- shared-core/nouveau_drv.h | 2 ++ shared-core/nouveau_notifier.c | 29 ++++++++++++++++++++--------- 2 files changed, 22 insertions(+), 9 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index b7459b1b..e96c8fad 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -421,6 +421,8 @@ extern void nouveau_irq_uninstall(struct drm_device *); /* nouveau_sgdma.c */ extern int nouveau_sgdma_init(struct drm_device *); extern void nouveau_sgdma_takedown(struct drm_device *); +extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, + uint32_t *page); extern struct drm_ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); extern int nouveau_sgdma_nottm_hack_init(struct drm_device *); extern void nouveau_sgdma_nottm_hack_takedown(struct drm_device *); diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index 31547aae..91f605ec 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -37,14 +37,13 @@ nouveau_notifier_init_channel(struct nouveau_channel *chan) int flags, ret; /*TODO: PCI notifier blocks */ - if (dev_priv->agp_heap && - dev_priv->gart_info.type != NOUVEAU_GART_SGDMA) - flags = NOUVEAU_MEM_AGP | NOUVEAU_MEM_FB_ACCEPTABLE; - else if ( dev_priv->pci_heap ) + if (dev_priv->agp_heap) + flags = NOUVEAU_MEM_AGP; + else if (dev_priv->pci_heap) flags = NOUVEAU_MEM_PCI; else flags = NOUVEAU_MEM_FB; - flags |= NOUVEAU_MEM_MAPPED; + flags |= (NOUVEAU_MEM_MAPPED | NOUVEAU_MEM_FB_ACCEPTABLE); DRM_DEBUG("Allocating notifier block in %d\n", flags); chan->notifier_block = nouveau_mem_alloc(dev, 0, PAGE_SIZE, flags, @@ -88,6 +87,7 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle, int count, uint32_t *b_offset) { struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_gpuobj *nobj = NULL; struct mem_block *mem; uint32_t offset; @@ -107,18 +107,29 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle, } mem->flags = NOUVEAU_MEM_NOTIFIER; - offset = chan->notifier_block->start + mem->start; + offset = chan->notifier_block->start; if (chan->notifier_block->flags & NOUVEAU_MEM_FB) { target = NV_DMA_TARGET_VIDMEM; - } else if (chan->notifier_block->flags & NOUVEAU_MEM_AGP) { - target = NV_DMA_TARGET_AGP; - } else if (chan->notifier_block->flags & NOUVEAU_MEM_PCI) { + } else + if (chan->notifier_block->flags & NOUVEAU_MEM_AGP) { + if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA && + dev_priv->card_type < NV_50) { + ret = nouveau_sgdma_get_page(dev, offset, &offset); + if (ret) + return ret; + target = NV_DMA_TARGET_PCI; + } else { + target = NV_DMA_TARGET_AGP; + } + } else + if (chan->notifier_block->flags & NOUVEAU_MEM_PCI) { target = NV_DMA_TARGET_PCI_NONLINEAR; } else { DRM_ERROR("Bad DMA target, flags 0x%08x!\n", chan->notifier_block->flags); return -EINVAL; } + offset += mem->start; if ((ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, offset, mem->size, -- cgit v1.2.3 From a615d2fde77092062f7e2bbfa39705b5f34547e8 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 15 Aug 2007 13:53:58 +1000 Subject: nouveau: Turn some messages into DRM_DEBUGs.. --- shared-core/nouveau_mem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 419522f4..92fa6b05 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -531,13 +531,13 @@ alloc_ok: block->map_handle = entry->user_token; } - DRM_INFO("allocated 0x%llx\n", block->start); + DRM_DEBUG("allocated 0x%llx type=0x%08x\n", block->start, block->flags); return block; } void nouveau_mem_free(struct drm_device* dev, struct mem_block* block) { - DRM_INFO("freeing 0x%llx\n", block->start); + DRM_DEBUG("freeing 0x%llx type=0x%08x\n", block->start, block->flags); if (block->flags&NOUVEAU_MEM_MAPPED) drm_rmmap(dev, block->map); nouveau_mem_free_block(block); -- cgit v1.2.3 From 10f9b7bd0b471487371813083bd3481629b2a56f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 15 Aug 2007 14:14:23 +1000 Subject: nouveau: Use count parameter in nouveau_notifier_alloc(). --- shared-core/nouveau_notifier.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index 91f605ec..71b8cbe1 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -45,11 +45,12 @@ nouveau_notifier_init_channel(struct nouveau_channel *chan) flags = NOUVEAU_MEM_FB; flags |= (NOUVEAU_MEM_MAPPED | NOUVEAU_MEM_FB_ACCEPTABLE); - DRM_DEBUG("Allocating notifier block in %d\n", flags); chan->notifier_block = nouveau_mem_alloc(dev, 0, PAGE_SIZE, flags, (struct drm_file *)-2); if (!chan->notifier_block) return -ENOMEM; + DRM_DEBUG("Allocated notifier block in 0x%08x\n", + chan->notifier_block->flags); ret = nouveau_mem_init_heap(&chan->notifier_heap, 0, chan->notifier_block->size); @@ -99,7 +100,7 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle, return -EINVAL; } - mem = nouveau_mem_alloc_block(chan->notifier_heap, 32, 0, + mem = nouveau_mem_alloc_block(chan->notifier_heap, count*32, 0, (struct drm_file *)-2); if (!mem) { DRM_ERROR("Channel %d notifier block full\n", chan->id); -- cgit v1.2.3 From 8a4d7f34d9c0182c466518c6f413d9a039db402d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 17 Aug 2007 01:12:46 +1000 Subject: nouveau: Detect memory on NFORCE/NFORCE2 correctly. --- shared-core/nouveau_mem.c | 43 +++++++++++++++++++++++++++++++++---------- 1 file changed, 33 insertions(+), 10 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 92fa6b05..30345797 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -219,6 +219,33 @@ void nouveau_mem_close(struct drm_device *dev) nouveau_mem_takedown(&dev_priv->pci_heap); } +/*XXX won't work on BSD because of pci_read_config_dword */ +static uint32_t +nouveau_mem_fb_amount_igp(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct pci_dev *bridge; + uint32_t mem; + + bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0,1)); + if (!bridge) { + DRM_ERROR("no bridge device\n"); + return 0; + } + + if (dev_priv->flags&NV_NFORCE) { + pci_read_config_dword(bridge, 0x7C, &mem); + return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024; + } else + if(dev_priv->flags&NV_NFORCE2) { + pci_read_config_dword(bridge, 0x84, &mem); + return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024; + } + + DRM_ERROR("impossible!\n"); + return 0; +} + /* returns the amount of FB ram in bytes */ uint64_t nouveau_mem_fb_amount(struct drm_device *dev) { @@ -263,18 +290,14 @@ uint64_t nouveau_mem_fb_amount(struct drm_device *dev) case NV_44: case NV_50: default: - // XXX won't work on BSD because of pci_read_config_dword - if (dev_priv->flags&NV_NFORCE) { - uint32_t mem; - pci_read_config_dword(dev->pdev, 0x7C, &mem); - return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024; - } else if(dev_priv->flags&NV_NFORCE2) { - uint32_t mem; - pci_read_config_dword(dev->pdev, 0x84, &mem); - return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024; + if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) { + return nouveau_mem_fb_amount_igp(dev); } else { uint64_t mem; - mem=(NV_READ(NV04_FIFO_DATA)&NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK) >> NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT; + + mem = (NV_READ(NV04_FIFO_DATA) & + NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK) >> + NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT; return mem*1024*1024; } break; -- cgit v1.2.3 From a122e7dabfaade751e8f6bb6d1488902fd36a40e Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Sun, 19 Aug 2007 18:41:18 +0200 Subject: Function pci_get_bus_and_slot needs 2.6.19 or later --- shared-core/nouveau_mem.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 30345797..3c294e4b 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -223,6 +223,7 @@ void nouveau_mem_close(struct drm_device *dev) static uint32_t nouveau_mem_fb_amount_igp(struct drm_device *dev) { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) struct drm_nouveau_private *dev_priv = dev->dev_private; struct pci_dev *bridge; uint32_t mem; @@ -243,6 +244,10 @@ nouveau_mem_fb_amount_igp(struct drm_device *dev) } DRM_ERROR("impossible!\n"); +#else + DRM_ERROR("Linux kernel >= 2.6.19 required to check for igp memory amount\n"); +#endif + return 0; } -- cgit v1.2.3 From c8760c7999b8aeb6d51b09c062331f518953a920 Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Sun, 19 Aug 2007 18:45:01 +0200 Subject: Check also for Linux, as it's not supported on different OS --- shared-core/nouveau_mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 3c294e4b..12d1ba75 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -223,7 +223,7 @@ void nouveau_mem_close(struct drm_device *dev) static uint32_t nouveau_mem_fb_amount_igp(struct drm_device *dev) { -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) +#if defined(LINUX) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)) struct drm_nouveau_private *dev_priv = dev->dev_private; struct pci_dev *bridge; uint32_t mem; -- cgit v1.2.3 From 216f1b0573b2c0e39ac82c7f56235c1003e9bd4d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 21 Aug 2007 02:18:27 +1000 Subject: nouveau: Poke 0x2230 on NV47 also. Makes 0x2220 work the same way as on NV40. --- shared-core/nouveau_fifo.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index f0c2a556..1aa724f1 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -84,9 +84,16 @@ static int nouveau_fifo_instmem_configure(struct drm_device *dev) { case NV_50: case NV_40: + switch (dev_priv->chipset) { + case 0x47: + case 0x49: + case 0x4b: + NV_WRITE(0x2230, 1); + break; + default: + break; + } NV_WRITE(NV40_PFIFO_RAMFC, 0x30002); - if((dev_priv->chipset == 0x49) || (dev_priv->chipset == 0x4b)) - NV_WRITE(0x2230,0x00000001); break; case NV_44: NV_WRITE(NV40_PFIFO_RAMFC, ((nouveau_mem_fb_amount(dev)-512*1024+dev_priv->ramfc_offset)>>16) | -- cgit v1.2.3 From 03c0490129816b5f5b40855438e948fdae572d06 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 21 Aug 2007 02:23:21 +1000 Subject: nouveau: Add NV44 ctx ucode. Patch from stillunknown. Microcode is similar enough to the NV4A one that it should be able to use the same initial PGRAPH context. One day this mess will go away, honest.. --- shared-core/nv40_graph.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index c1464bc2..0e6028af 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -1249,6 +1249,7 @@ nv40_graph_create_context(struct nouveau_channel *chan) ctx_size = NV49_GRCTX_SIZE; ctx_init = nv49_graph_context_init; break; + case 0x44: case 0x4a: ctx_size = NV4A_GRCTX_SIZE; ctx_init = nv4a_graph_context_init; @@ -1453,6 +1454,39 @@ static uint32_t nv43_ctx_voodoo[] = { ~0 }; +static uint32_t nv44_ctx_voodoo[] = { + 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, + 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409a65, 0x00409f06, + 0x0040ac68, 0x0040248f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042, + 0x001041c6, 0x00104040, 0x00200001, 0x0060000a, 0x00700000, 0x001040c5, + 0x00402320, 0x00402321, 0x00402322, 0x00402324, 0x00402326, 0x0040232b, + 0x001040c5, 0x00402328, 0x001040c5, 0x00402320, 0x00402468, 0x0060000d, + 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080, 0x00402be6, + 0x007000a0, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d, 0x00110158, + 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4, 0x001041c9, + 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e, 0x001242c0, + 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143, 0x0011415f, + 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10, 0x001046ec, + 0x00500060, 0x00404b87, 0x0060000d, 0x004084e6, 0x002000f1, 0x0060000a, + 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b, 0x00168691, + 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6, 0x001646cc, + 0x001186e6, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700, 0x0010c3d7, + 0x001043e1, 0x00500060, 0x00200232, 0x0060000a, 0x00104800, 0x00108901, + 0x00104910, 0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00148a00, + 0x00108a14, 0x00160b00, 0x00134b2c, 0x0010cd00, 0x0010cd04, 0x0010cd08, + 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06, 0x002002c8, + 0x0060000a, 0x00300000, 0x00200080, 0x00407d00, 0x00200084, 0x00800001, + 0x00200510, 0x0060000a, 0x002037e0, 0x0040838a, 0x00201320, 0x00800029, + 0x00409400, 0x00600006, 0x004090e6, 0x00700080, 0x0020007a, 0x0060000a, + 0x00104280, 0x002002c8, 0x0060000a, 0x00200004, 0x00800001, 0x00700000, + 0x00200000, 0x0060000a, 0x00106002, 0x0040ac68, 0x00700000, 0x00200000, + 0x0060000a, 0x00106002, 0x00700080, 0x00400a68, 0x00500060, 0x00600007, + 0x00409e88, 0x0060000f, 0x00000000, 0x00500060, 0x00200000, 0x0060000a, + 0x00700000, 0x00106001, 0x00910880, 0x00901ffe, 0x01940000, 0x00200020, + 0x0060000b, 0x00500069, 0x0060000c, 0x00402c68, 0x0040ae06, 0x0040af05, + 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0 +}; + static uint32_t nv46_ctx_voodoo[] = { 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00408f65, 0x00409306, @@ -1609,6 +1643,7 @@ nv40_graph_init(struct drm_device *dev) switch (dev_priv->chipset) { case 0x40: ctx_voodoo = nv40_ctx_voodoo; break; case 0x43: ctx_voodoo = nv43_ctx_voodoo; break; + case 0x44: ctx_voodoo = nv44_ctx_voodoo; break; case 0x46: ctx_voodoo = nv46_ctx_voodoo; break; case 0x49: ctx_voodoo = nv49_4b_ctx_voodoo; break; case 0x4a: ctx_voodoo = nv4a_ctx_voodoo; break; -- cgit v1.2.3 From 76337bdb19fb6a098fc6d6ceaafb58a4ed15f9b0 Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Mon, 6 Aug 2007 17:42:31 +0200 Subject: nouveau: fix the comment and debug message for PCIGART size --- shared-core/nouveau_mem.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 12d1ba75..2cc0ed77 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -439,11 +439,11 @@ int nouveau_mem_init(struct drm_device *dev) struct drm_scatter_gather sgreq; DRM_DEBUG("Allocating sg memory for PCI DMA\n"); - sgreq.size = 16 << 20; //4MB of PCI scatter-gather zone + sgreq.size = 16 << 20; //16MB of PCI scatter-gather zone if (drm_sg_alloc(dev, &sgreq)) { - DRM_ERROR("Unable to allocate 4MB of scatter-gather" - " pages for PCI DMA!"); + DRM_ERROR("Unable to allocate %dMB of scatter-gather" + " pages for PCI DMA!",sgreq.size>>20); } else { if (nouveau_mem_init_heap(&dev_priv->pci_heap, 0, dev->sg->pages * PAGE_SIZE)) { -- cgit v1.2.3 From c8ee6a6cabbd44c06e382f99c2691d3efe46b984 Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Wed, 22 Aug 2007 04:20:09 +0200 Subject: nouveau: redo nv30_graph.c. Should work better, but we still lack a couple of cards. --- shared-core/nv30_graph.c | 2824 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 2725 insertions(+), 99 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index 161f3154..ca43bb95 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -8,97 +8,2703 @@ #include "nouveau_drm.h" /* - * This is obviously not the correct size. + * There are 4 families : + * NV30 is 0x10de:0x030* (not working, no dump for that one) + * + * NV31 is 0x10de:0x031* + * + * NV34 is 0x10de:0x032* + * + * NV35 is 0x10de:0x033* (NV35 and NV36 are the same) + * NV36 is 0x10de:0x034* + * + * Not seen in the wild, no dumps (probably NV35) : + * NV37 is 0x10de:0x00fc, 0x10de:0x00fd + * NV38 is 0x10de:0x0333, 0x10de:0x00fe + * */ -#define NV30_GRCTX_SIZE (23840) -/*TODO: deciper what each offset in the context represents. The below - * contexts are taken from dumps just after the 3D object is - * created. - */ -static void nv30_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) + +#define NV31_GRCTX_SIZE (22392) +#define NV34_GRCTX_SIZE (18140) +#define NV35_GRCTX_SIZE (22396) + +static void nv31_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { struct drm_nouveau_private *dev_priv = dev->dev_private; int i; - - INSTANCE_WR(ctx, 0x28/4, 0x10000000); - INSTANCE_WR(ctx, 0x40c/4, 0x00000101); - INSTANCE_WR(ctx, 0x420/4, 0x00000111); - INSTANCE_WR(ctx, 0x424/4, 0x00000060); - INSTANCE_WR(ctx, 0x440/4, 0x00000080); - INSTANCE_WR(ctx, 0x444/4, 0xffff0000); - INSTANCE_WR(ctx, 0x448/4, 0x00000001); - INSTANCE_WR(ctx, 0x45c/4, 0x44400000); - INSTANCE_WR(ctx, 0x448/4, 0xffff0000); - INSTANCE_WR(ctx, 0x4dc/4, 0xfff00000); - INSTANCE_WR(ctx, 0x4e0/4, 0xfff00000); - INSTANCE_WR(ctx, 0x4e8/4, 0x00011100); - - for (i = 0x504; i <= 0x540; i += 4) - INSTANCE_WR(ctx, i/4, 0x7ff00000); - - INSTANCE_WR(ctx, 0x54c/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x588/4, 0x00000080); - INSTANCE_WR(ctx, 0x58c/4, 0x30201000); - INSTANCE_WR(ctx, 0x590/4, 0x70605040); - INSTANCE_WR(ctx, 0x594/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x598/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x5ac/4, 0xb0000000); - - for (i = 0x604; i <= 0x640; i += 4) - INSTANCE_WR(ctx, i/4, 0x00010588); - - for (i = 0x644; i <= 0x680; i += 4) - INSTANCE_WR(ctx, i/4, 0x00030303); - - for (i = 0x6c4; i <= 0x700; i += 4) - INSTANCE_WR(ctx, i/4, 0x0008aae4); - - for (i = 0x704; i <= 0x740; i += 4) - INSTANCE_WR(ctx, i/4, 0x1012000); - - for (i = 0x744; i <= 0x780; i += 4) - INSTANCE_WR(ctx, i/4, 0x0080008); - - INSTANCE_WR(ctx, 0x860/4, 0x00040000); - INSTANCE_WR(ctx, 0x864/4, 0x00010000); - INSTANCE_WR(ctx, 0x868/4, 0x00040000); - INSTANCE_WR(ctx, 0x86c/4, 0x00040000); - INSTANCE_WR(ctx, 0x870/4, 0x00040000); - INSTANCE_WR(ctx, 0x874/4, 0x00040000); - - for (i = 0x00; i <= 0x1170; i += 0x10) - { - INSTANCE_WR(ctx, (0x1f24 + i)/4, 0x000c001b); - INSTANCE_WR(ctx, (0x1f20 + i)/4, 0x0436086c); - INSTANCE_WR(ctx, (0x1f1c + i)/4, 0x10700ff9); - } - - INSTANCE_WR(ctx, 0x30bc/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x30c0/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x30c4/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x30c8/4, 0x0000ffff); - - INSTANCE_WR(ctx, 0x380c/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3450/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3820/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3854/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3850/4, 0x3f000000); - INSTANCE_WR(ctx, 0x384c/4, 0x40000000); - INSTANCE_WR(ctx, 0x3868/4, 0xbf800000); - INSTANCE_WR(ctx, 0x3860/4, 0x3f800000); - INSTANCE_WR(ctx, 0x386c/4, 0x40000000); - INSTANCE_WR(ctx, 0x3870/4, 0xbf800000); - - for (i = 0x4e0; i <= 0x4e1c; i += 4) - INSTANCE_WR(ctx, i/4, 0x001c527d); - INSTANCE_WR(ctx, 0x4e40, 0x001c527c); - - INSTANCE_WR(ctx, 0x5680/4, 0x000a0000); - INSTANCE_WR(ctx, 0x87c/4, 0x10000000); - INSTANCE_WR(ctx, 0x28/4, 0x10000011); + + INSTANCE_WR(ctx, 0x410/4, 0x00000101); + INSTANCE_WR(ctx, 0x424/4, 0x00000111); + INSTANCE_WR(ctx, 0x428/4, 0x00000060); + INSTANCE_WR(ctx, 0x444/4, 0x00000080); + INSTANCE_WR(ctx, 0x448/4, 0xffff0000); + INSTANCE_WR(ctx, 0x44c/4, 0x00000001); + INSTANCE_WR(ctx, 0x460/4, 0x44400000); + INSTANCE_WR(ctx, 0x48c/4, 0xffff0000); + for(i = 0x4e0; i< 0x4e8; i += 4) + INSTANCE_WR(ctx, i/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x4ec/4, 0x00011100); + for(i = 0x508; i< 0x548; i += 4) + INSTANCE_WR(ctx, i/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x550/4, 0x4b7fffff); + INSTANCE_WR(ctx, 0x58c/4, 0x00000080); + INSTANCE_WR(ctx, 0x590/4, 0x30201000); + INSTANCE_WR(ctx, 0x594/4, 0x70605040); + INSTANCE_WR(ctx, 0x598/4, 0xb8a89888); + INSTANCE_WR(ctx, 0x59c/4, 0xf8e8d8c8); + INSTANCE_WR(ctx, 0x5b0/4, 0xb0000000); + for(i = 0x600; i< 0x640; i += 4) + INSTANCE_WR(ctx, i/4, 0x00010588); + for(i = 0x640; i< 0x680; i += 4) + INSTANCE_WR(ctx, i/4, 0x00030303); + for(i = 0x6c0; i< 0x700; i += 4) + INSTANCE_WR(ctx, i/4, 0x0008aae4); + for(i = 0x700; i< 0x740; i += 4) + INSTANCE_WR(ctx, i/4, 0x01012000); + for(i = 0x740; i< 0x780; i += 4) + INSTANCE_WR(ctx, i/4, 0x00080008); + INSTANCE_WR(ctx, 0x85c/4, 0x00040000); + INSTANCE_WR(ctx, 0x860/4, 0x00010000); + for(i = 0x864; i< 0x874; i += 4) + INSTANCE_WR(ctx, i/4, 0x00040004); + INSTANCE_WR(ctx, 0x1f18/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f1c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f20/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f28/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f2c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f30/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f38/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f3c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f40/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f48/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f4c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f50/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f58/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f5c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f60/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f68/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f6c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f70/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f78/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f7c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f80/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f88/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f8c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f90/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f98/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f9c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fa0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fa8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fb0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fb8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fbc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fc0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fc8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fcc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fd0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fd8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fdc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fe0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fe8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ff0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1ff8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ffc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2000/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2008/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x200c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2010/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2018/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x201c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2020/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2028/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x202c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2030/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2038/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x203c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2040/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2048/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x204c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2050/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2058/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x205c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2060/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2068/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x206c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2070/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2078/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x207c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2080/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2088/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x208c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2090/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2098/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x209c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2100/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2108/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x210c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2110/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2118/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x211c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2120/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2128/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x212c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2130/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2138/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x213c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2140/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2148/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x214c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2150/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2158/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x215c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2160/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2168/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x216c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2170/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2178/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x217c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2180/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2188/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x218c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2190/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2198/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x219c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2200/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2208/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x220c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2210/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2218/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x221c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2220/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2228/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x222c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2230/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2238/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x223c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2240/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2248/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x224c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2250/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2258/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x225c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2260/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2268/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x226c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2270/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2278/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x227c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2280/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2288/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x228c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2290/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2298/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x229c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2300/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2308/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x230c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2310/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2318/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x231c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2320/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2328/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x232c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2330/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2338/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x233c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2340/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2348/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x234c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2350/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2358/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x235c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2360/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2368/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x236c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2370/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2378/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x237c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2380/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2388/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x238c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2390/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2398/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x239c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2400/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2408/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x240c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2410/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2418/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x241c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2420/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2428/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x242c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2430/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2438/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x243c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2440/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2448/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x244c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2450/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2458/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x245c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2460/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2468/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x246c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2470/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2478/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x247c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2480/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2488/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x248c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2490/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2498/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x249c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2500/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2508/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x250c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2510/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2518/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x251c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2520/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2528/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x252c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2530/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2538/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x253c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2540/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2548/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x254c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2550/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2558/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x255c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2560/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2568/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x256c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2570/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2578/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x257c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2580/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2588/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x258c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2590/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2598/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x259c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2600/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2608/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x260c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2610/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2618/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x261c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2620/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2628/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x262c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2630/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2638/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x263c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2640/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2648/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x264c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2650/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2658/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x265c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2660/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2668/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x266c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2670/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2678/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x267c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2680/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2688/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x268c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2690/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2698/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x269c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2700/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2708/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x270c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2710/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2718/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x271c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2720/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2728/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x272c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2730/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2738/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x273c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2740/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2748/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x274c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2750/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2758/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x275c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2760/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2768/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x276c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2770/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2778/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x277c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2780/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2788/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x278c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2790/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2798/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x279c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2800/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2808/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x280c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2810/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2818/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x281c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2820/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2828/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x282c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2830/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2838/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x283c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2840/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2848/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x284c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2850/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2858/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x285c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2860/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2868/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x286c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2870/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2878/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x287c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2880/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2888/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x288c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2890/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2898/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x289c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2900/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2908/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x290c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2910/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2918/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x291c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2920/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2928/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x292c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2930/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2938/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x293c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2940/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2948/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x294c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2950/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2958/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x295c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2960/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2968/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x296c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2970/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2978/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x297c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2980/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2988/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x298c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2990/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2998/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x299c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a00/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a08/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a0c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a10/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a18/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a1c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a20/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a28/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a2c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a30/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a38/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a3c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a40/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a48/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a4c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a50/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a58/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a5c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a60/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a68/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a6c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a70/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a78/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a7c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a80/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a88/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a8c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a90/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a98/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a9c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2aa0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2aa8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2aac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ab0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ab8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2abc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ac0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ac8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2acc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ad0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ad8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2adc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ae0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ae8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2aec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2af0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2af8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2afc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b00/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b08/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b0c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b10/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b18/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b1c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b20/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b28/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b2c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b30/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b38/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b3c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b40/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b48/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b4c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b50/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b58/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b5c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b60/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b68/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b6c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b70/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b78/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b7c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b80/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b88/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b8c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b90/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b98/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b9c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ba0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ba8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2bb0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bb8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bbc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2bc0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bc8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bcc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2bd0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bd8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bdc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2be0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2be8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2bf0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bf8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bfc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c00/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c08/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c0c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c10/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c18/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c1c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c20/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c28/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c2c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c30/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c38/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c3c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c40/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c48/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c4c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c50/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c58/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c5c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c60/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c68/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c6c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c70/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c78/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c7c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c80/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c88/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c8c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c90/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c98/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c9c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ca0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ca8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2cb0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cb8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cbc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2cc0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cc8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ccc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2cd0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cd8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cdc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ce0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ce8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2cf0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cf8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cfc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d00/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d08/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d0c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d10/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d18/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d1c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d20/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d28/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d2c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d30/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d38/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d3c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d40/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d48/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d4c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d50/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d58/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d5c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d60/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d68/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d6c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d70/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d78/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d7c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d80/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d88/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d8c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d90/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d98/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d9c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2da0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2da8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2dac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2db0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2db8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2dbc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2dc0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2dc8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2dcc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2dd0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2dd8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ddc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2de0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2de8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2dec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2df0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2df8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2dfc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e00/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e08/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e0c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e10/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e18/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e1c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e20/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e28/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e2c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e30/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e38/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e3c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e40/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e48/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e4c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e50/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e58/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e5c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e60/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e68/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e6c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e70/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e78/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e7c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e80/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e88/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e8c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e90/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e98/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e9c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ea0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ea8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2eac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2eb0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2eb8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ebc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ec0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ec8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ecc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ed0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ed8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2edc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ee0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ee8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2eec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ef0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ef8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2efc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f00/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f08/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f0c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f10/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f18/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f1c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f20/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f28/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f2c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f30/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f38/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f3c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f40/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f48/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f4c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f50/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f58/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f5c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f60/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f68/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f6c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f70/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f78/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f7c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f80/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f88/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f8c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f90/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f98/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f9c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fa0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fa8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fb0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fb8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fbc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fc0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fc8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fcc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fd0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fd8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fdc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fe0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fe8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ff0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ff8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ffc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3000/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3008/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x300c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3010/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3018/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x301c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3020/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3028/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x302c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3030/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3038/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x303c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3040/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3048/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x304c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3050/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3058/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x305c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3060/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3068/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x306c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3070/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3078/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x307c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3080/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3088/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x308c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3090/4, 0x000c001b); + for(i = 0x30b8; i< 0x30c8; i += 4) + INSTANCE_WR(ctx, i/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x344c/4, 0x3f800000); + INSTANCE_WR(ctx, 0x3808/4, 0x3f800000); + INSTANCE_WR(ctx, 0x381c/4, 0x3f800000); + INSTANCE_WR(ctx, 0x3848/4, 0x40000000); + INSTANCE_WR(ctx, 0x384c/4, 0x3f800000); + INSTANCE_WR(ctx, 0x3850/4, 0x3f000000); + INSTANCE_WR(ctx, 0x3858/4, 0x40000000); + INSTANCE_WR(ctx, 0x385c/4, 0x3f800000); + INSTANCE_WR(ctx, 0x3864/4, 0xbf800000); + INSTANCE_WR(ctx, 0x386c/4, 0xbf800000);} + +static void nv34_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; + + INSTANCE_WR(ctx, 0x40c/4, 0x01000101); + INSTANCE_WR(ctx, 0x420/4, 0x00000111); + INSTANCE_WR(ctx, 0x424/4, 0x00000060); + INSTANCE_WR(ctx, 0x440/4, 0x00000080); + INSTANCE_WR(ctx, 0x444/4, 0xffff0000); + INSTANCE_WR(ctx, 0x448/4, 0x00000001); + INSTANCE_WR(ctx, 0x45c/4, 0x44400000); + INSTANCE_WR(ctx, 0x480/4, 0xffff0000); + for(i = 0x4d4; i< 0x4dc; i += 4) + INSTANCE_WR(ctx, i/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x4e0/4, 0x00011100); + for(i = 0x4fc; i< 0x53c; i += 4) + INSTANCE_WR(ctx, i/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x544/4, 0x4b7fffff); + INSTANCE_WR(ctx, 0x57c/4, 0x00000080); + INSTANCE_WR(ctx, 0x580/4, 0x30201000); + INSTANCE_WR(ctx, 0x584/4, 0x70605040); + INSTANCE_WR(ctx, 0x588/4, 0xb8a89888); + INSTANCE_WR(ctx, 0x58c/4, 0xf8e8d8c8); + INSTANCE_WR(ctx, 0x5a0/4, 0xb0000000); + for(i = 0x5f0; i< 0x630; i += 4) + INSTANCE_WR(ctx, i/4, 0x00010588); + for(i = 0x630; i< 0x670; i += 4) + INSTANCE_WR(ctx, i/4, 0x00030303); + for(i = 0x6b0; i< 0x6f0; i += 4) + INSTANCE_WR(ctx, i/4, 0x0008aae4); + for(i = 0x6f0; i< 0x730; i += 4) + INSTANCE_WR(ctx, i/4, 0x01012000); + for(i = 0x730; i< 0x770; i += 4) + INSTANCE_WR(ctx, i/4, 0x00080008); + INSTANCE_WR(ctx, 0x850/4, 0x00040000); + INSTANCE_WR(ctx, 0x854/4, 0x00010000); + for(i = 0x858; i< 0x868; i += 4) + INSTANCE_WR(ctx, i/4, 0x00040004); + INSTANCE_WR(ctx, 0x15ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x15b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x15b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x15bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x15c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x15c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x15cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x15d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x15d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x15dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x15e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x15e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x15ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x15f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x15f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x15fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1600/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1604/4, 0x000c001b); + INSTANCE_WR(ctx, 0x160c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1610/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1614/4, 0x000c001b); + INSTANCE_WR(ctx, 0x161c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1620/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1624/4, 0x000c001b); + INSTANCE_WR(ctx, 0x162c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1630/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1634/4, 0x000c001b); + INSTANCE_WR(ctx, 0x163c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1640/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1644/4, 0x000c001b); + INSTANCE_WR(ctx, 0x164c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1650/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1654/4, 0x000c001b); + INSTANCE_WR(ctx, 0x165c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1660/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1664/4, 0x000c001b); + INSTANCE_WR(ctx, 0x166c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1670/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1674/4, 0x000c001b); + INSTANCE_WR(ctx, 0x167c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1680/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1684/4, 0x000c001b); + INSTANCE_WR(ctx, 0x168c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1690/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1694/4, 0x000c001b); + INSTANCE_WR(ctx, 0x169c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x16a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x16a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x16ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x16b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x16b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x16bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x16c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x16c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x16cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x16d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x16d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x16dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x16e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x16e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x16ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x16f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x16f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x16fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1700/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1704/4, 0x000c001b); + INSTANCE_WR(ctx, 0x170c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1710/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1714/4, 0x000c001b); + INSTANCE_WR(ctx, 0x171c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1720/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1724/4, 0x000c001b); + INSTANCE_WR(ctx, 0x172c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1730/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1734/4, 0x000c001b); + INSTANCE_WR(ctx, 0x173c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1740/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1744/4, 0x000c001b); + INSTANCE_WR(ctx, 0x174c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1750/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1754/4, 0x000c001b); + INSTANCE_WR(ctx, 0x175c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1760/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1764/4, 0x000c001b); + INSTANCE_WR(ctx, 0x176c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1770/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1774/4, 0x000c001b); + INSTANCE_WR(ctx, 0x177c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1780/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1784/4, 0x000c001b); + INSTANCE_WR(ctx, 0x178c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1790/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1794/4, 0x000c001b); + INSTANCE_WR(ctx, 0x179c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x17a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x17a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x17ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x17b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x17b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x17bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x17c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x17c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x17cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x17d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x17d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x17dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x17e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x17e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x17ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x17f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x17f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x17fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1800/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1804/4, 0x000c001b); + INSTANCE_WR(ctx, 0x180c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1810/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1814/4, 0x000c001b); + INSTANCE_WR(ctx, 0x181c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1820/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1824/4, 0x000c001b); + INSTANCE_WR(ctx, 0x182c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1830/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1834/4, 0x000c001b); + INSTANCE_WR(ctx, 0x183c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1840/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1844/4, 0x000c001b); + INSTANCE_WR(ctx, 0x184c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1850/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1854/4, 0x000c001b); + INSTANCE_WR(ctx, 0x185c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1860/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1864/4, 0x000c001b); + INSTANCE_WR(ctx, 0x186c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1870/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1874/4, 0x000c001b); + INSTANCE_WR(ctx, 0x187c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1880/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1884/4, 0x000c001b); + INSTANCE_WR(ctx, 0x188c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1890/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1894/4, 0x000c001b); + INSTANCE_WR(ctx, 0x189c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x18a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x18a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x18ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x18b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x18b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x18bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x18c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x18c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x18cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x18d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x18d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x18dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x18e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x18e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x18ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x18f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x18f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x18fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1900/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1904/4, 0x000c001b); + INSTANCE_WR(ctx, 0x190c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1910/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1914/4, 0x000c001b); + INSTANCE_WR(ctx, 0x191c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1920/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1924/4, 0x000c001b); + INSTANCE_WR(ctx, 0x192c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1930/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1934/4, 0x000c001b); + INSTANCE_WR(ctx, 0x193c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1940/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1944/4, 0x000c001b); + INSTANCE_WR(ctx, 0x194c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1950/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1954/4, 0x000c001b); + INSTANCE_WR(ctx, 0x195c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1960/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1964/4, 0x000c001b); + INSTANCE_WR(ctx, 0x196c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1970/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1974/4, 0x000c001b); + INSTANCE_WR(ctx, 0x197c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1980/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1984/4, 0x000c001b); + INSTANCE_WR(ctx, 0x198c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1990/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1994/4, 0x000c001b); + INSTANCE_WR(ctx, 0x199c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x19a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x19a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x19ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x19b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x19b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x19bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x19c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x19c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x19cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x19d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x19d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x19dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x19e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x19e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x19ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x19f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x19f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x19fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1aa0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1aa4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1aac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ab0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ab4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1abc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ac0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ac4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1acc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ad0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ad4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1adc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ae0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ae4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1aec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1af0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1af4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1afc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ba0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ba4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1bac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1bb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1bb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1bbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1bc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1bc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1bcc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1bd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1bd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1bdc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1be0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1be4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1bec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1bf0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1bf4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1bfc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ca0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ca4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1cac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1cb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1cb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1cbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1cc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1cc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1ccc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1cd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1cd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1cdc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ce0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ce4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1cec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1cf0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1cf4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1cfc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1da0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1da4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1dac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1db0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1db4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1dbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1dc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1dc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1dcc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1dd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1dd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1ddc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1de0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1de4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1dec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1df0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1df4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1dfc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ea0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ea4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1eac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1eb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1eb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1ebc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ec0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ec4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1ecc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ed0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ed4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1edc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ee0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ee4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1eec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ef0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ef4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1efc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fa0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fa4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fcc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fdc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fe0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fe4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ff0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ff4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1ffc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2000/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2004/4, 0x000c001b); + INSTANCE_WR(ctx, 0x200c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2010/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2014/4, 0x000c001b); + INSTANCE_WR(ctx, 0x201c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2020/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2024/4, 0x000c001b); + INSTANCE_WR(ctx, 0x202c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2030/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2034/4, 0x000c001b); + INSTANCE_WR(ctx, 0x203c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2040/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2044/4, 0x000c001b); + INSTANCE_WR(ctx, 0x204c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2050/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2054/4, 0x000c001b); + INSTANCE_WR(ctx, 0x205c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2060/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2064/4, 0x000c001b); + INSTANCE_WR(ctx, 0x206c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2070/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2074/4, 0x000c001b); + INSTANCE_WR(ctx, 0x207c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2080/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2084/4, 0x000c001b); + INSTANCE_WR(ctx, 0x208c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2090/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2094/4, 0x000c001b); + INSTANCE_WR(ctx, 0x209c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2100/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2104/4, 0x000c001b); + INSTANCE_WR(ctx, 0x210c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2110/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2114/4, 0x000c001b); + INSTANCE_WR(ctx, 0x211c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2120/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2124/4, 0x000c001b); + INSTANCE_WR(ctx, 0x212c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2130/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2134/4, 0x000c001b); + INSTANCE_WR(ctx, 0x213c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2140/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2144/4, 0x000c001b); + INSTANCE_WR(ctx, 0x214c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2150/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2154/4, 0x000c001b); + INSTANCE_WR(ctx, 0x215c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2160/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2164/4, 0x000c001b); + INSTANCE_WR(ctx, 0x216c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2170/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2174/4, 0x000c001b); + INSTANCE_WR(ctx, 0x217c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2180/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2184/4, 0x000c001b); + INSTANCE_WR(ctx, 0x218c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2190/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2194/4, 0x000c001b); + INSTANCE_WR(ctx, 0x219c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2200/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2204/4, 0x000c001b); + INSTANCE_WR(ctx, 0x220c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2210/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2214/4, 0x000c001b); + INSTANCE_WR(ctx, 0x221c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2220/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2224/4, 0x000c001b); + INSTANCE_WR(ctx, 0x222c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2230/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2234/4, 0x000c001b); + INSTANCE_WR(ctx, 0x223c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2240/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2244/4, 0x000c001b); + INSTANCE_WR(ctx, 0x224c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2250/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2254/4, 0x000c001b); + INSTANCE_WR(ctx, 0x225c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2260/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2264/4, 0x000c001b); + INSTANCE_WR(ctx, 0x226c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2270/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2274/4, 0x000c001b); + INSTANCE_WR(ctx, 0x227c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2280/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2284/4, 0x000c001b); + INSTANCE_WR(ctx, 0x228c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2290/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2294/4, 0x000c001b); + INSTANCE_WR(ctx, 0x229c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2300/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2304/4, 0x000c001b); + INSTANCE_WR(ctx, 0x230c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2310/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2314/4, 0x000c001b); + INSTANCE_WR(ctx, 0x231c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2320/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2324/4, 0x000c001b); + INSTANCE_WR(ctx, 0x232c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2330/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2334/4, 0x000c001b); + INSTANCE_WR(ctx, 0x233c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2340/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2344/4, 0x000c001b); + INSTANCE_WR(ctx, 0x234c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2350/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2354/4, 0x000c001b); + INSTANCE_WR(ctx, 0x235c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2360/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2364/4, 0x000c001b); + INSTANCE_WR(ctx, 0x236c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2370/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2374/4, 0x000c001b); + INSTANCE_WR(ctx, 0x237c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2380/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2384/4, 0x000c001b); + INSTANCE_WR(ctx, 0x238c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2390/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2394/4, 0x000c001b); + INSTANCE_WR(ctx, 0x239c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2400/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2404/4, 0x000c001b); + INSTANCE_WR(ctx, 0x240c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2410/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2414/4, 0x000c001b); + INSTANCE_WR(ctx, 0x241c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2420/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2424/4, 0x000c001b); + INSTANCE_WR(ctx, 0x242c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2430/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2434/4, 0x000c001b); + INSTANCE_WR(ctx, 0x243c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2440/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2444/4, 0x000c001b); + INSTANCE_WR(ctx, 0x244c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2450/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2454/4, 0x000c001b); + INSTANCE_WR(ctx, 0x245c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2460/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2464/4, 0x000c001b); + INSTANCE_WR(ctx, 0x246c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2470/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2474/4, 0x000c001b); + INSTANCE_WR(ctx, 0x247c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2480/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2484/4, 0x000c001b); + INSTANCE_WR(ctx, 0x248c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2490/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2494/4, 0x000c001b); + INSTANCE_WR(ctx, 0x249c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2500/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2504/4, 0x000c001b); + INSTANCE_WR(ctx, 0x250c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2510/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2514/4, 0x000c001b); + INSTANCE_WR(ctx, 0x251c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2520/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2524/4, 0x000c001b); + INSTANCE_WR(ctx, 0x252c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2530/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2534/4, 0x000c001b); + INSTANCE_WR(ctx, 0x253c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2540/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2544/4, 0x000c001b); + INSTANCE_WR(ctx, 0x254c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2550/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2554/4, 0x000c001b); + INSTANCE_WR(ctx, 0x255c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2560/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2564/4, 0x000c001b); + INSTANCE_WR(ctx, 0x256c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2570/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2574/4, 0x000c001b); + INSTANCE_WR(ctx, 0x257c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2580/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2584/4, 0x000c001b); + INSTANCE_WR(ctx, 0x258c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2590/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2594/4, 0x000c001b); + INSTANCE_WR(ctx, 0x259c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2600/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2604/4, 0x000c001b); + INSTANCE_WR(ctx, 0x260c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2610/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2614/4, 0x000c001b); + INSTANCE_WR(ctx, 0x261c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2620/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2624/4, 0x000c001b); + INSTANCE_WR(ctx, 0x262c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2630/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2634/4, 0x000c001b); + INSTANCE_WR(ctx, 0x263c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2640/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2644/4, 0x000c001b); + INSTANCE_WR(ctx, 0x264c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2650/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2654/4, 0x000c001b); + INSTANCE_WR(ctx, 0x265c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2660/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2664/4, 0x000c001b); + INSTANCE_WR(ctx, 0x266c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2670/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2674/4, 0x000c001b); + INSTANCE_WR(ctx, 0x267c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2680/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2684/4, 0x000c001b); + INSTANCE_WR(ctx, 0x268c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2690/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2694/4, 0x000c001b); + INSTANCE_WR(ctx, 0x269c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2700/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2704/4, 0x000c001b); + INSTANCE_WR(ctx, 0x270c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2710/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2714/4, 0x000c001b); + INSTANCE_WR(ctx, 0x271c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2720/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2724/4, 0x000c001b); + for(i = 0x274c; i< 0x275c; i += 4) + INSTANCE_WR(ctx, i/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x2ae0/4, 0x3f800000); + INSTANCE_WR(ctx, 0x2e9c/4, 0x3f800000); + INSTANCE_WR(ctx, 0x2eb0/4, 0x3f800000); + INSTANCE_WR(ctx, 0x2edc/4, 0x40000000); + INSTANCE_WR(ctx, 0x2ee0/4, 0x3f800000); + INSTANCE_WR(ctx, 0x2ee4/4, 0x3f000000); + INSTANCE_WR(ctx, 0x2eec/4, 0x40000000); + INSTANCE_WR(ctx, 0x2ef0/4, 0x3f800000); + INSTANCE_WR(ctx, 0x2ef8/4, 0xbf800000); + INSTANCE_WR(ctx, 0x2f00/4, 0xbf800000); } +static void nv35_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; + + INSTANCE_WR(ctx, 0x40c/4, 0x00000101); + INSTANCE_WR(ctx, 0x420/4, 0x00000111); + INSTANCE_WR(ctx, 0x424/4, 0x00000060); + INSTANCE_WR(ctx, 0x440/4, 0x00000080); + INSTANCE_WR(ctx, 0x444/4, 0xffff0000); + INSTANCE_WR(ctx, 0x448/4, 0x00000001); + INSTANCE_WR(ctx, 0x45c/4, 0x44400000); + INSTANCE_WR(ctx, 0x488/4, 0xffff0000); + for(i = 0x4dc; i< 0x4e4; i += 4) + INSTANCE_WR(ctx, i/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x4e8/4, 0x00011100); + for(i = 0x504; i< 0x544; i += 4) + INSTANCE_WR(ctx, i/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x54c/4, 0x4b7fffff); + INSTANCE_WR(ctx, 0x588/4, 0x00000080); + INSTANCE_WR(ctx, 0x58c/4, 0x30201000); + INSTANCE_WR(ctx, 0x590/4, 0x70605040); + INSTANCE_WR(ctx, 0x594/4, 0xb8a89888); + INSTANCE_WR(ctx, 0x598/4, 0xf8e8d8c8); + INSTANCE_WR(ctx, 0x5ac/4, 0xb0000000); + for(i = 0x604; i< 0x644; i += 4) + INSTANCE_WR(ctx, i/4, 0x00010588); + for(i = 0x644; i< 0x684; i += 4) + INSTANCE_WR(ctx, i/4, 0x00030303); + for(i = 0x6c4; i< 0x704; i += 4) + INSTANCE_WR(ctx, i/4, 0x0008aae4); + for(i = 0x704; i< 0x744; i += 4) + INSTANCE_WR(ctx, i/4, 0x01012000); + for(i = 0x744; i< 0x784; i += 4) + INSTANCE_WR(ctx, i/4, 0x00080008); + INSTANCE_WR(ctx, 0x860/4, 0x00040000); + INSTANCE_WR(ctx, 0x864/4, 0x00010000); + for(i = 0x868; i< 0x878; i += 4) + INSTANCE_WR(ctx, i/4, 0x00040004); + INSTANCE_WR(ctx, 0x1f1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fa0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fa4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fcc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fdc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fe0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fe4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ff0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ff4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1ffc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2000/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2004/4, 0x000c001b); + INSTANCE_WR(ctx, 0x200c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2010/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2014/4, 0x000c001b); + INSTANCE_WR(ctx, 0x201c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2020/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2024/4, 0x000c001b); + INSTANCE_WR(ctx, 0x202c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2030/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2034/4, 0x000c001b); + INSTANCE_WR(ctx, 0x203c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2040/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2044/4, 0x000c001b); + INSTANCE_WR(ctx, 0x204c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2050/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2054/4, 0x000c001b); + INSTANCE_WR(ctx, 0x205c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2060/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2064/4, 0x000c001b); + INSTANCE_WR(ctx, 0x206c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2070/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2074/4, 0x000c001b); + INSTANCE_WR(ctx, 0x207c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2080/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2084/4, 0x000c001b); + INSTANCE_WR(ctx, 0x208c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2090/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2094/4, 0x000c001b); + INSTANCE_WR(ctx, 0x209c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2100/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2104/4, 0x000c001b); + INSTANCE_WR(ctx, 0x210c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2110/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2114/4, 0x000c001b); + INSTANCE_WR(ctx, 0x211c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2120/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2124/4, 0x000c001b); + INSTANCE_WR(ctx, 0x212c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2130/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2134/4, 0x000c001b); + INSTANCE_WR(ctx, 0x213c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2140/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2144/4, 0x000c001b); + INSTANCE_WR(ctx, 0x214c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2150/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2154/4, 0x000c001b); + INSTANCE_WR(ctx, 0x215c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2160/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2164/4, 0x000c001b); + INSTANCE_WR(ctx, 0x216c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2170/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2174/4, 0x000c001b); + INSTANCE_WR(ctx, 0x217c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2180/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2184/4, 0x000c001b); + INSTANCE_WR(ctx, 0x218c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2190/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2194/4, 0x000c001b); + INSTANCE_WR(ctx, 0x219c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2200/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2204/4, 0x000c001b); + INSTANCE_WR(ctx, 0x220c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2210/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2214/4, 0x000c001b); + INSTANCE_WR(ctx, 0x221c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2220/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2224/4, 0x000c001b); + INSTANCE_WR(ctx, 0x222c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2230/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2234/4, 0x000c001b); + INSTANCE_WR(ctx, 0x223c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2240/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2244/4, 0x000c001b); + INSTANCE_WR(ctx, 0x224c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2250/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2254/4, 0x000c001b); + INSTANCE_WR(ctx, 0x225c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2260/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2264/4, 0x000c001b); + INSTANCE_WR(ctx, 0x226c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2270/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2274/4, 0x000c001b); + INSTANCE_WR(ctx, 0x227c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2280/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2284/4, 0x000c001b); + INSTANCE_WR(ctx, 0x228c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2290/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2294/4, 0x000c001b); + INSTANCE_WR(ctx, 0x229c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2300/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2304/4, 0x000c001b); + INSTANCE_WR(ctx, 0x230c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2310/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2314/4, 0x000c001b); + INSTANCE_WR(ctx, 0x231c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2320/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2324/4, 0x000c001b); + INSTANCE_WR(ctx, 0x232c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2330/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2334/4, 0x000c001b); + INSTANCE_WR(ctx, 0x233c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2340/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2344/4, 0x000c001b); + INSTANCE_WR(ctx, 0x234c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2350/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2354/4, 0x000c001b); + INSTANCE_WR(ctx, 0x235c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2360/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2364/4, 0x000c001b); + INSTANCE_WR(ctx, 0x236c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2370/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2374/4, 0x000c001b); + INSTANCE_WR(ctx, 0x237c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2380/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2384/4, 0x000c001b); + INSTANCE_WR(ctx, 0x238c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2390/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2394/4, 0x000c001b); + INSTANCE_WR(ctx, 0x239c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2400/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2404/4, 0x000c001b); + INSTANCE_WR(ctx, 0x240c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2410/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2414/4, 0x000c001b); + INSTANCE_WR(ctx, 0x241c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2420/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2424/4, 0x000c001b); + INSTANCE_WR(ctx, 0x242c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2430/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2434/4, 0x000c001b); + INSTANCE_WR(ctx, 0x243c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2440/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2444/4, 0x000c001b); + INSTANCE_WR(ctx, 0x244c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2450/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2454/4, 0x000c001b); + INSTANCE_WR(ctx, 0x245c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2460/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2464/4, 0x000c001b); + INSTANCE_WR(ctx, 0x246c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2470/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2474/4, 0x000c001b); + INSTANCE_WR(ctx, 0x247c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2480/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2484/4, 0x000c001b); + INSTANCE_WR(ctx, 0x248c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2490/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2494/4, 0x000c001b); + INSTANCE_WR(ctx, 0x249c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2500/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2504/4, 0x000c001b); + INSTANCE_WR(ctx, 0x250c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2510/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2514/4, 0x000c001b); + INSTANCE_WR(ctx, 0x251c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2520/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2524/4, 0x000c001b); + INSTANCE_WR(ctx, 0x252c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2530/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2534/4, 0x000c001b); + INSTANCE_WR(ctx, 0x253c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2540/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2544/4, 0x000c001b); + INSTANCE_WR(ctx, 0x254c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2550/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2554/4, 0x000c001b); + INSTANCE_WR(ctx, 0x255c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2560/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2564/4, 0x000c001b); + INSTANCE_WR(ctx, 0x256c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2570/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2574/4, 0x000c001b); + INSTANCE_WR(ctx, 0x257c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2580/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2584/4, 0x000c001b); + INSTANCE_WR(ctx, 0x258c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2590/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2594/4, 0x000c001b); + INSTANCE_WR(ctx, 0x259c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2600/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2604/4, 0x000c001b); + INSTANCE_WR(ctx, 0x260c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2610/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2614/4, 0x000c001b); + INSTANCE_WR(ctx, 0x261c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2620/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2624/4, 0x000c001b); + INSTANCE_WR(ctx, 0x262c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2630/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2634/4, 0x000c001b); + INSTANCE_WR(ctx, 0x263c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2640/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2644/4, 0x000c001b); + INSTANCE_WR(ctx, 0x264c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2650/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2654/4, 0x000c001b); + INSTANCE_WR(ctx, 0x265c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2660/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2664/4, 0x000c001b); + INSTANCE_WR(ctx, 0x266c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2670/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2674/4, 0x000c001b); + INSTANCE_WR(ctx, 0x267c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2680/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2684/4, 0x000c001b); + INSTANCE_WR(ctx, 0x268c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2690/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2694/4, 0x000c001b); + INSTANCE_WR(ctx, 0x269c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2700/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2704/4, 0x000c001b); + INSTANCE_WR(ctx, 0x270c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2710/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2714/4, 0x000c001b); + INSTANCE_WR(ctx, 0x271c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2720/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2724/4, 0x000c001b); + INSTANCE_WR(ctx, 0x272c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2730/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2734/4, 0x000c001b); + INSTANCE_WR(ctx, 0x273c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2740/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2744/4, 0x000c001b); + INSTANCE_WR(ctx, 0x274c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2750/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2754/4, 0x000c001b); + INSTANCE_WR(ctx, 0x275c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2760/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2764/4, 0x000c001b); + INSTANCE_WR(ctx, 0x276c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2770/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2774/4, 0x000c001b); + INSTANCE_WR(ctx, 0x277c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2780/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2784/4, 0x000c001b); + INSTANCE_WR(ctx, 0x278c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2790/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2794/4, 0x000c001b); + INSTANCE_WR(ctx, 0x279c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2800/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2804/4, 0x000c001b); + INSTANCE_WR(ctx, 0x280c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2810/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2814/4, 0x000c001b); + INSTANCE_WR(ctx, 0x281c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2820/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2824/4, 0x000c001b); + INSTANCE_WR(ctx, 0x282c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2830/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2834/4, 0x000c001b); + INSTANCE_WR(ctx, 0x283c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2840/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2844/4, 0x000c001b); + INSTANCE_WR(ctx, 0x284c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2850/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2854/4, 0x000c001b); + INSTANCE_WR(ctx, 0x285c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2860/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2864/4, 0x000c001b); + INSTANCE_WR(ctx, 0x286c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2870/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2874/4, 0x000c001b); + INSTANCE_WR(ctx, 0x287c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2880/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2884/4, 0x000c001b); + INSTANCE_WR(ctx, 0x288c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2890/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2894/4, 0x000c001b); + INSTANCE_WR(ctx, 0x289c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2900/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2904/4, 0x000c001b); + INSTANCE_WR(ctx, 0x290c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2910/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2914/4, 0x000c001b); + INSTANCE_WR(ctx, 0x291c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2920/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2924/4, 0x000c001b); + INSTANCE_WR(ctx, 0x292c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2930/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2934/4, 0x000c001b); + INSTANCE_WR(ctx, 0x293c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2940/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2944/4, 0x000c001b); + INSTANCE_WR(ctx, 0x294c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2950/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2954/4, 0x000c001b); + INSTANCE_WR(ctx, 0x295c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2960/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2964/4, 0x000c001b); + INSTANCE_WR(ctx, 0x296c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2970/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2974/4, 0x000c001b); + INSTANCE_WR(ctx, 0x297c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2980/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2984/4, 0x000c001b); + INSTANCE_WR(ctx, 0x298c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2990/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2994/4, 0x000c001b); + INSTANCE_WR(ctx, 0x299c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2aa0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2aa4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2aac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ab0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ab4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2abc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ac0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ac4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2acc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ad0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ad4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2adc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ae0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ae4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2aec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2af0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2af4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2afc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ba0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ba4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2bb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2bc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bcc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2bd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bdc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2be0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2be4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bf0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2bf4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bfc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ca0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ca4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2cb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2cc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ccc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2cd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cdc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ce0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ce4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cf0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2cf4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cfc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2da0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2da4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2dac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2db0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2db4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2dbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2dc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2dc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2dcc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2dd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2dd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ddc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2de0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2de4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2dec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2df0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2df4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2dfc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ea0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ea4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2eac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2eb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2eb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ebc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ec0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ec4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ecc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ed0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ed4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2edc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ee0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ee4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2eec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ef0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ef4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2efc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fa0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fa4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fcc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fdc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fe0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fe4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ff0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ff4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ffc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3000/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3004/4, 0x000c001b); + INSTANCE_WR(ctx, 0x300c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3010/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3014/4, 0x000c001b); + INSTANCE_WR(ctx, 0x301c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3020/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3024/4, 0x000c001b); + INSTANCE_WR(ctx, 0x302c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3030/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3034/4, 0x000c001b); + INSTANCE_WR(ctx, 0x303c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3040/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3044/4, 0x000c001b); + INSTANCE_WR(ctx, 0x304c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3050/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3054/4, 0x000c001b); + INSTANCE_WR(ctx, 0x305c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3060/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3064/4, 0x000c001b); + INSTANCE_WR(ctx, 0x306c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3070/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3074/4, 0x000c001b); + INSTANCE_WR(ctx, 0x307c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3080/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3084/4, 0x000c001b); + INSTANCE_WR(ctx, 0x308c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3090/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3094/4, 0x000c001b); + for(i = 0x30bc; i< 0x30cc; i += 4) + INSTANCE_WR(ctx, i/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x3450/4, 0x3f800000); + INSTANCE_WR(ctx, 0x380c/4, 0x3f800000); + INSTANCE_WR(ctx, 0x3820/4, 0x3f800000); + INSTANCE_WR(ctx, 0x384c/4, 0x40000000); + INSTANCE_WR(ctx, 0x3850/4, 0x3f800000); + INSTANCE_WR(ctx, 0x3854/4, 0x3f000000); + INSTANCE_WR(ctx, 0x385c/4, 0x40000000); + INSTANCE_WR(ctx, 0x3860/4, 0x3f800000); + INSTANCE_WR(ctx, 0x3868/4, 0xbf800000); + INSTANCE_WR(ctx, 0x3870/4, 0xbf800000);} int nv30_graph_create_context(struct nouveau_channel *chan) { @@ -109,9 +2715,23 @@ int nv30_graph_create_context(struct nouveau_channel *chan) int ret; switch (dev_priv->chipset) { + case 0x31: + ctx_size = NV31_GRCTX_SIZE; + ctx_init = nv31_graph_context_init; + break; + case 0x34: + ctx_size = NV34_GRCTX_SIZE; + ctx_init = nv34_graph_context_init; + break; + case 0x35: + case 0x36: + ctx_size = NV35_GRCTX_SIZE; + ctx_init = nv35_graph_context_init; + break; default: - ctx_size = NV30_GRCTX_SIZE; - ctx_init = nv30_graph_context_init; + ctx_size = 0; + ctx_init = nv35_graph_context_init; + DRM_ERROR("Please contact the devs if you want your NV%x card to work\n",dev_priv->chipset); break; } @@ -122,10 +2742,10 @@ int nv30_graph_create_context(struct nouveau_channel *chan) /* Initialise default context values */ ctx_init(dev, chan->ramin_grctx->gpuobj); - - INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); /* CTX_USER */ - INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, - chan->ramin_grctx->instance >> 4); + + INSTANCE_WR(chan->ramin_grctx->gpuobj, 0x28/4, (chan->id<<24)|0x1); /* CTX_USER */ + INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, + chan->ramin_grctx->instance >> 4); return 0; } @@ -221,18 +2841,24 @@ int nv30_graph_init(struct drm_device *dev) NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x401287c0); - NV_WRITE(0x400890, 0x00140000); - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xf0de0475); - NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x10008000); - NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04b1f36); + NV_WRITE(0x400890, 0x01b463ff); + NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xf3de0471); + NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000); + NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); NV_WRITE(0x400B80, 0x1003d888); - NV_WRITE(0x400B84, 0x0c000000); - NV_WRITE(0x400B88, 0x62ff0f7f); - NV_WRITE(0x400098, 0x000000c0); - NV_WRITE(0x40009C, 0x0005dc00); - NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x62ff0f7f); + NV_WRITE(0x400098, 0x00000000); + NV_WRITE(0x40009C, 0x0005ad00); + NV_WRITE(0x400B88, 0x62ff00ff); // suspiciously like PGRAPH_DEBUG_2 NV_WRITE(0x4000a0, 0x00000000); NV_WRITE(0x4000a4, 0x00000008); + NV_WRITE(0x4008a8, 0xb784a400); + NV_WRITE(0x400ba0, 0x002f8685); + NV_WRITE(0x400ba4, 0x00231f3f); + NV_WRITE(0x4008a4, 0x40000020); + NV_WRITE(0x400B84, 0x0c000000); + NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x62ff0f7f); + NV_WRITE(0x4000c0, 0x00000016); + NV_WRITE(0x400780, 0x000014e4); /* copy tile info from PFB */ for (i=0; i Date: Wed, 22 Aug 2007 12:54:26 +1000 Subject: nouveau/nv50: Correct thinko for 8800 chips + cleanup a bit. --- shared-core/nv50_fifo.c | 36 ++++++++++++++---------------------- 1 file changed, 14 insertions(+), 22 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index 71b89d6d..7859544a 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -63,24 +63,17 @@ nv50_fifo_channel_enable(struct drm_device *dev, int channel, int nt) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_channel *chan = dev_priv->fifos[channel]; + uint32_t inst; DRM_DEBUG("ch%d\n", channel); - if (IS_G80) { - if (!chan->ramin) - return -EINVAL; - - NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), - (chan->ramin->instance >> 12) | - NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); - } else { - if (!chan->ramfc) - return -EINVAL; + if (!chan->ramfc) + return -EINVAL; - NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), - (chan->ramfc->instance >> 8) | - NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); - } + if (IS_G80) inst = chan->ramfc->instance >> 12; + else inst = chan->ramfc->instance >> 8; + NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), + inst | NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); if (!nt) nv50_fifo_init_thingo(dev); return 0; @@ -90,16 +83,13 @@ static void nv50_fifo_channel_disable(struct drm_device *dev, int channel, int nt) { struct drm_nouveau_private *dev_priv = dev->dev_private; + uint32_t inst; DRM_DEBUG("ch%d, nt=%d\n", channel, nt); - if (IS_G80) { - NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), - NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80); - } else { - NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), - NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84); - } + if (IS_G80) inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80; + else inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84; + NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), inst); if (!nt) nv50_fifo_init_thingo(dev); } @@ -234,7 +224,9 @@ nv50_fifo_create_context(struct nouveau_channel *chan) if (IS_G80) { uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start; - if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, ~0, 0x100, + uint32_t vram_offset = chan->ramin->gpuobj->im_backing->start; + if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, + vram_offset, 0x100, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, &ramfc, &chan->ramfc))) -- cgit v1.2.3 From 81eaff44c47cfb23e96b1cb848df5fd7ea24f913 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 22 Aug 2007 13:09:27 +1000 Subject: nouveau: NV4c ctx ucode. Seems we already have a nv4c_ctx_init() somehow, a quick check shows the ucode matches it still. --- shared-core/nv40_graph.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index 0e6028af..8882e62b 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -1584,6 +1584,37 @@ static uint32_t nv4a_ctx_voodoo[] = { 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0 }; +static uint32_t nv4c_ctx_voodoo[] = { + 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, + 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409065, 0x00409406, + 0x0040a168, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042, + 0x00200001, 0x0060000a, 0x00700000, 0x001040c5, 0x00401826, 0x00401968, + 0x0060000d, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080, + 0x004020e6, 0x007000a0, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d, + 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4, + 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e, + 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143, + 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10, + 0x0010427e, 0x001046ec, 0x00500060, 0x00404187, 0x0060000d, 0x00407ae6, + 0x002000f2, 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, + 0x0011068b, 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, + 0x001146c6, 0x00200020, 0x001006cc, 0x001046ed, 0x001246f0, 0x002000c0, + 0x00100700, 0x0010c3d7, 0x001043e1, 0x00500060, 0x00200234, 0x0060000a, + 0x00104800, 0x00108901, 0x00104910, 0x00124920, 0x0020001f, 0x00100940, + 0x00140965, 0x00148a00, 0x00108a14, 0x00140b00, 0x00134b2c, 0x0010cd00, + 0x0010cd04, 0x00104d08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00, + 0x00104f06, 0x002002c0, 0x0060000a, 0x00300000, 0x00200080, 0x00407300, + 0x00200084, 0x00800001, 0x00200508, 0x0060000a, 0x00201320, 0x0040798a, + 0xfffffaf8, 0x00800029, 0x00408a00, 0x00600006, 0x004086e6, 0x00700080, + 0x0020007a, 0x0060000a, 0x00104280, 0x002002c0, 0x0060000a, 0x00200004, + 0x00800001, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a168, + 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x00700080, 0x00400a68, + 0x00500060, 0x00600007, 0x00409488, 0x0060000f, 0x00500060, 0x00200000, + 0x0060000a, 0x00700000, 0x00106001, 0x00910880, 0x00901ffe, 0x01940000, + 0x00200020, 0x0060000b, 0x00500069, 0x0060000c, 0x00402168, 0x0040a306, + 0x0040a405, 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0 +}; + static uint32_t nv4e_ctx_voodoo[] = { 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409565, 0x00409a06, @@ -1648,6 +1679,7 @@ nv40_graph_init(struct drm_device *dev) case 0x49: ctx_voodoo = nv49_4b_ctx_voodoo; break; case 0x4a: ctx_voodoo = nv4a_ctx_voodoo; break; case 0x4b: ctx_voodoo = nv49_4b_ctx_voodoo; break; + case 0x4c: ctx_voodoo = nv4c_ctx_voodoo; break; case 0x4e: ctx_voodoo = nv4e_ctx_voodoo; break; default: DRM_ERROR("Unknown ctx_voodoo for chipset 0x%02x\n", -- cgit v1.2.3 From a654c0341a7892307522ed6e7f4518cc7e28a99e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 22 Aug 2007 13:17:19 +1000 Subject: nouveau/nv40: Dump extra info on ucode state if ctx switch fails. --- shared-core/nouveau_reg.h | 4 ++++ shared-core/nv40_graph.c | 6 +++++- 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 65614627..1023e75e 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -178,6 +178,10 @@ #define NV10_PGRAPH_CTX_CACHE5 0x004001E0 #define NV40_PGRAPH_CTXCTL_0304 0x00400304 #define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001 +#define NV40_PGRAPH_CTXCTL_UCODE_STAT 0x00400308 +#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK 0xff000000 +#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT 24 +#define NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK 0x00ffffff #define NV40_PGRAPH_CTXCTL_0310 0x00400310 #define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE 0x00000020 #define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD 0x00000040 diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index 8882e62b..25ee5c77 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -1310,7 +1310,11 @@ nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save) NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp); if (i == tv) { - DRM_ERROR("failed: inst=0x%08x save=%d\n", inst, save); + uint32_t ucstat = NV_READ(NV40_PGRAPH_CTXCTL_UCODE_STAT); + DRM_ERROR("Failed: Instance=0x%08x Save=%d\n", inst, save); + DRM_ERROR("IP: 0x%02x, Opcode: 0x%08x\n", + ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT, + ucstat & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK); DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(NV40_PGRAPH_CTXCTL_030C)); return -EBUSY; -- cgit v1.2.3 From 11c46afe7599cf3cefd30a7e55325a1a1aa8e5ba Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 22 Aug 2007 13:23:49 +1000 Subject: nouveau/nv40: Preserve other bits in 0x400304/0x400310 like NVIDIA do. --- shared-core/nv40_graph.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index 25ee5c77..26237c7d 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -1293,20 +1293,26 @@ static int nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save) { struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t old_cp, tv = 1000; + uint32_t old_cp, tv = 1000, tmp; int i; old_cp = NV_READ(NV20_PGRAPH_CHANNEL_CTX_POINTER); NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); - NV_WRITE(NV40_PGRAPH_CTXCTL_0310, - save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE : - NV40_PGRAPH_CTXCTL_0310_XFER_LOAD); - NV_WRITE(NV40_PGRAPH_CTXCTL_0304, NV40_PGRAPH_CTXCTL_0304_XFER_CTX); + + tmp = NV_READ(NV40_PGRAPH_CTXCTL_0310); + tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE : + NV40_PGRAPH_CTXCTL_0310_XFER_LOAD; + NV_WRITE(NV40_PGRAPH_CTXCTL_0310, tmp); + + tmp = NV_READ(NV40_PGRAPH_CTXCTL_0304); + tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX; + NV_WRITE(NV40_PGRAPH_CTXCTL_0304, tmp); for (i = 0; i < tv; i++) { if (NV_READ(NV40_PGRAPH_CTXCTL_030C) == 0) break; } + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp); if (i == tv) { -- cgit v1.2.3 From 8645dac8952473dc3e09ba7a7a9db3fbdf75215f Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Wed, 22 Aug 2007 23:17:56 +0200 Subject: nouveau : fix some potential crashes with objects causing hash collision --- shared-core/nouveau_object.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index e0cb334f..fbce7702 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -141,8 +141,13 @@ nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) ref->channel, co, INSTANCE_RD(ramht, co/4)); co += 8; - if (co >= dev_priv->ramht_size) + if (co >= dev_priv->ramht_size) { + DRM_INFO("no space left after collision\n"); co = 0; + /* exit as it seems to cause crash with nouveau_demo and + * 0xdead0001 object */ + break; + } } while (co != ho); DRM_ERROR("RAMHT space exhausted. ch=%d\n", ref->channel); -- cgit v1.2.3 From 98750111961a5729eba9433b927f8c24548fbace Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Thu, 23 Aug 2007 10:18:34 +0200 Subject: nouveau: nv10: check some NULL pointers inside context switch --- shared-core/nv10_graph.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 53b93758..567ce6a4 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -578,16 +578,40 @@ int nv10_graph_save_context(struct nouveau_channel *chan) void nouveau_nv10_context_switch(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv; struct nouveau_channel *next, *last; int chid; + if (!dev) { + DRM_DEBUG("Invalid drm_device\n"); + return; + } + dev_priv = dev->dev_private; + if (!dev_priv) { + DRM_DEBUG("Invalid drm_nouveau_private\n"); + return; + } + if (!dev_priv->fifos) { + DRM_DEBUG("Invalid drm_nouveau_private->fifos\n"); + return; + } + chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); next = dev_priv->fifos[chid]; + if (!next) { + DRM_DEBUG("Invalid next channel\n"); + return; + } + chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); last = dev_priv->fifos[chid]; + if (!last) { + DRM_DEBUG("Invalid last channel\n"); + return; + } + DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n", last->id, next->id); @@ -607,7 +631,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev) nouveau_wait_for_idle(dev); nv10_graph_load_context(next); - + NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100); NV_WRITE(NV10_PGRAPH_CTX_USER, next->id << 24); NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); -- cgit v1.2.3 From 502bbdbe14fa458ed06c7fa4b1ccb63e4f126625 Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Sat, 25 Aug 2007 00:12:58 +0200 Subject: nouveau: nv10: output a warning if last channel invalid, and switch to next --- shared-core/nv10_graph.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 567ce6a4..18bab7eb 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -608,21 +608,23 @@ void nouveau_nv10_context_switch(struct drm_device *dev) last = dev_priv->fifos[chid]; if (!last) { - DRM_DEBUG("Invalid last channel\n"); - return; + DRM_DEBUG("WARNING: Invalid last channel, switch to %x\n", + next->id); + } else { + DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n", + last->id, next->id); } - DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n", - last->id, next->id); - NV_WRITE(NV04_PGRAPH_FIFO,0x0); #if 0 NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000); NV_WRITE(NV_PFIFO_CACHES, 0x00000000); #endif - nv10_graph_save_context(last); - + if (last) { + nv10_graph_save_context(last); + } + nouveau_wait_for_idle(dev); NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000000); -- cgit v1.2.3 From 4182fce4084f4d884a7435b8ad2acb5c209f4544 Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Sat, 25 Aug 2007 22:10:45 +0200 Subject: nouveau : nv1x graph reworks - add forgotten init value - use the same PGRAPH_DEBUG than the blob - remove init of ddx reg : it should be done with object - better handle of channel destruction hope I didn't break anything ;) --- shared-core/nv10_graph.c | 67 ++++++++++++++++++++++++++++++++++-------------- 1 file changed, 48 insertions(+), 19 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 18bab7eb..c604ff2e 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -181,11 +181,7 @@ static void nv10_praph_pipe(struct drm_device *dev) { nouveau_wait_for_idle(dev); } -/* TODO replace address with name - use loops */ static int nv10_graph_ctx_regs [] = { -NV03_PGRAPH_XY_LOGIC_MISC0, - NV10_PGRAPH_CTX_SWITCH1, NV10_PGRAPH_CTX_SWITCH2, NV10_PGRAPH_CTX_SWITCH3, @@ -455,6 +451,7 @@ NV03_PGRAPH_ABS_UCLIPA_YMIN, NV03_PGRAPH_ABS_UCLIPA_YMAX, NV03_PGRAPH_ABS_ICLIP_XMAX, NV03_PGRAPH_ABS_ICLIP_YMAX, +NV03_PGRAPH_XY_LOGIC_MISC0, NV03_PGRAPH_XY_LOGIC_MISC1, NV03_PGRAPH_XY_LOGIC_MISC2, NV03_PGRAPH_XY_LOGIC_MISC3, @@ -556,6 +553,7 @@ int nv10_graph_load_context(struct nouveau_channel *chan) for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) NV_WRITE(nv17_graph_ctx_regs[j], chan->pgraph_ctx[i]); } + NV_WRITE(NV10_PGRAPH_CTX_USER, chan->id << 24); return 0; } @@ -616,11 +614,6 @@ void nouveau_nv10_context_switch(struct drm_device *dev) } NV_WRITE(NV04_PGRAPH_FIFO,0x0); -#if 0 - NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); - NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000); - NV_WRITE(NV_PFIFO_CACHES, 0x00000000); -#endif if (last) { nv10_graph_save_context(last); } @@ -635,13 +628,8 @@ void nouveau_nv10_context_switch(struct drm_device *dev) nv10_graph_load_context(next); NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100); - NV_WRITE(NV10_PGRAPH_CTX_USER, next->id << 24); + //NV_WRITE(NV10_PGRAPH_CTX_USER, next->id << 24); NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); -#if 0 - NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); - NV_WRITE(NV_PFIFO_CACHES, 0x00000001); -#endif NV_WRITE(NV04_PGRAPH_FIFO,0x1); } @@ -654,12 +642,14 @@ void nouveau_nv10_context_switch(struct drm_device *dev) int nv10_graph_create_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t tmp, vramsz; DRM_DEBUG("nv10_graph_context_create %d\n", chan->id); memset(chan->pgraph_ctx, 0, sizeof(chan->pgraph_ctx)); + /* mmio trace suggest that should be done in ddx with methods/objects */ +#if 0 + uint32_t tmp, vramsz; /* per channel init from ddx */ tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; /*XXX the original ddx code, does this in 2 steps : @@ -684,12 +674,23 @@ int nv10_graph_create_context(struct nouveau_channel *chan) { NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_YMIN, 0); NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); +#endif + NV_WRITE_CTX(0x00400e88, 0x08000000); + NV_WRITE_CTX(0x00400e9c, 0x4b7fffff); NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff); - /* is it really needed ??? */ + NV_WRITE_CTX(0x00400e10, 0x00001000); + NV_WRITE_CTX(0x00400e14, 0x00001000); + NV_WRITE_CTX(0x00400e30, 0x00080008); + NV_WRITE_CTX(0x00400e34, 0x00080008); if (dev_priv->chipset>=0x17) { + /* is it really needed ??? */ NV_WRITE_CTX(NV10_PGRAPH_DEBUG_4, NV_READ(NV10_PGRAPH_DEBUG_4)); NV_WRITE_CTX(0x004006b0, NV_READ(0x004006b0)); + NV_WRITE_CTX(0x00400eac, 0x0fff0000); + NV_WRITE_CTX(0x00400eb0, 0x0fff0000); + NV_WRITE_CTX(0x00400ec0, 0x00000080); + NV_WRITE_CTX(0x00400ed0, 0x00000080); } /* for the first channel init the regs */ @@ -705,6 +706,23 @@ int nv10_graph_create_context(struct nouveau_channel *chan) { void nv10_graph_destroy_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + int chid; + chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + + /* does this avoid a potential context switch while we are written graph + * reg, or we should mask graph interrupt ??? + */ + NV_WRITE(NV04_PGRAPH_FIFO,0x0); + if (chid == chan->id) { + DRM_INFO("cleanning a channel with graph in current context\n"); + nouveau_wait_for_idle(dev); + DRM_INFO("reseting current graph context\n"); + nv10_graph_create_context(chan); + nv10_graph_load_context(chan); + } + NV_WRITE(NV04_PGRAPH_FIFO,0x1); } int nv10_graph_init(struct drm_device *dev) { @@ -722,10 +740,17 @@ int nv10_graph_init(struct drm_device *dev) { NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700); - NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x24E00810); - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x55DE0030 | + //NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x24E00810); /* 0x25f92ad9 */ + NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x25f92ad9); + NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1<<29) | (1<<31)); + if (dev_priv->chipset>=0x17) { + NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x1f000000); + NV_WRITE(0x004006b0, 0x40000020); + } + else + NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000); /* copy tile info from PFB */ for (i=0; i Date: Sun, 26 Aug 2007 20:48:32 +0200 Subject: nouveau : add NV04_PGRAPH_TRAPPED_ADDR definition - fix offset for nv04 - use it in nv10 graph ctx switch for getting next channel - dump NV10_PGRAPH_TRAPPED_DATA_HIGH on nv10+ --- shared-core/nouveau_irq.c | 24 ++++++++++++++++-------- shared-core/nouveau_reg.h | 8 +++++--- shared-core/nv10_graph.c | 2 +- 3 files changed, 22 insertions(+), 12 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index d8a2c1b8..e64677ed 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -227,8 +227,10 @@ nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret) struct drm_nouveau_private *dev_priv = dev->dev_private; int channel; - if (dev_priv->card_type < NV_40) { - channel = (NV_READ(0x400704) >> 20) & 0x1f; + if (dev_priv->card_type < NV_10) { + channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf; + } else if (dev_priv->card_type < NV_40) { + channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f; } else if (dev_priv->card_type < NV_50) { uint32_t cur_grctx = (NV_READ(0x40032C) & 0xfffff) << 4; @@ -283,16 +285,22 @@ nouveau_graph_dump_trap_info(struct drm_device *dev) struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t address; uint32_t channel, class; - uint32_t method, subc, data; + uint32_t method, subc, data, data2; uint32_t nsource, nstatus; if (nouveau_graph_trapped_channel(dev, &channel)) channel = -1; - address = NV_READ(0x400704); - subc = (address >> 16) & 0x7; + data = NV_READ(NV04_PGRAPH_TRAPPED_DATA); + address = NV_READ(NV04_PGRAPH_TRAPPED_ADDR); method = address & 0x1FFC; - data = NV_READ(0x400708); + if (dev_priv->card_type < NV_10) { + subc = (address >> 13) & 0x7; + data2= 0; + } else { + subc = (address >> 16) & 0x7; + data2= NV_READ(NV10_PGRAPH_TRAPPED_DATA_HIGH); + } nsource = NV_READ(NV03_PGRAPH_NSOURCE); nstatus = NV_READ(NV03_PGRAPH_NSTATUS); if (dev_priv->card_type < NV_50) { @@ -309,8 +317,8 @@ nouveau_graph_dump_trap_info(struct drm_device *dev) ARRAY_SIZE(nouveau_nstatus_names)); printk("\n"); - DRM_ERROR("Channel %d/%d (class 0x%04x) - Method 0x%04x, Data 0x%08x\n", - channel, subc, class, method, data); + DRM_ERROR("Channel %d/%d (class 0x%04x) - Method 0x%04x, Data 0x%08x:0x%08x\n", + channel, subc, class, method, data2, data); } static void nouveau_pgraph_irq_handler(struct drm_device *dev) diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 1023e75e..a1895c34 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -15,9 +15,6 @@ # define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000 # define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20 -#define NV03_PGRAPH_STATUS 0x004006b0 -#define NV04_PGRAPH_STATUS 0x00400700 - #define NV_RAMIN 0x00700000 #define NV_RAMHT_HANDLE_OFFSET 0 @@ -264,7 +261,12 @@ #define NV04_PGRAPH_BLIMIT5 0x00400698 #define NV04_PGRAPH_BSWIZZLE2 0x0040069C #define NV04_PGRAPH_BSWIZZLE5 0x004006A0 +#define NV03_PGRAPH_STATUS 0x004006B0 +#define NV04_PGRAPH_STATUS 0x00400700 +#define NV04_PGRAPH_TRAPPED_ADDR 0x00400704 +#define NV04_PGRAPH_TRAPPED_DATA 0x00400708 #define NV04_PGRAPH_SURFACE 0x0040070C +#define NV10_PGRAPH_TRAPPED_DATA_HIGH 0x0040070C #define NV04_PGRAPH_STATE 0x00400710 #define NV10_PGRAPH_SURFACE 0x00400710 #define NV04_PGRAPH_NOTIFY 0x00400714 diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index c604ff2e..e470ff06 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -594,7 +594,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev) return; } - chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); + chid = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20)&(nouveau_fifo_number(dev)-1); next = dev_priv->fifos[chid]; if (!next) { -- cgit v1.2.3 From 589707b765eee78cc278c10603e2c858bb819436 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 28 Aug 2007 15:17:11 +1000 Subject: drm: remove XFREE86_VERSION macros --- shared-core/drm.h | 20 +------------------- shared-core/r128_drm.h | 18 ------------------ 2 files changed, 1 insertion(+), 37 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index db913b1f..a9882d49 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -89,24 +89,6 @@ #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) #endif -#define XFREE86_VERSION(major,minor,patch,snap) \ - ((major << 16) | (minor << 8) | patch) - -#ifndef CONFIG_XFREE86_VERSION -#define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0) -#endif - -#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) -#define DRM_PROC_DEVICES "/proc/devices" -#define DRM_PROC_MISC "/proc/misc" -#define DRM_PROC_DRM "/proc/drm" -#define DRM_DEV_DRM "/dev/drm" -#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP) -#define DRM_DEV_UID 0 -#define DRM_DEV_GID 0 -#endif - -#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0) #ifdef __OpenBSD__ #define DRM_MAJOR 81 #endif @@ -114,7 +96,7 @@ #define DRM_MAJOR 226 #endif #define DRM_MAX_MINOR 15 -#endif + #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ diff --git a/shared-core/r128_drm.h b/shared-core/r128_drm.h index e94a39c6..8d8878b5 100644 --- a/shared-core/r128_drm.h +++ b/shared-core/r128_drm.h @@ -222,11 +222,7 @@ typedef struct drm_r128_init { R128_INIT_CCE = 0x01, R128_CLEANUP_CCE = 0x02 } func; -#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) - int sarea_priv_offset; -#else unsigned long sarea_priv_offset; -#endif int is_pci; int cce_mode; int cce_secure; @@ -240,21 +236,12 @@ typedef struct drm_r128_init { unsigned int depth_offset, depth_pitch; unsigned int span_offset; -#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) - unsigned int fb_offset; - unsigned int mmio_offset; - unsigned int ring_offset; - unsigned int ring_rptr_offset; - unsigned int buffers_offset; - unsigned int agp_textures_offset; -#else unsigned long fb_offset; unsigned long mmio_offset; unsigned long ring_offset; unsigned long ring_rptr_offset; unsigned long buffers_offset; unsigned long agp_textures_offset; -#endif } drm_r128_init_t; typedef struct drm_r128_cce_stop { @@ -264,15 +251,10 @@ typedef struct drm_r128_cce_stop { typedef struct drm_r128_clear { unsigned int flags; -#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) - int x, y, w, h; -#endif unsigned int clear_color; unsigned int clear_depth; -#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0) unsigned int color_mask; unsigned int depth_mask; -#endif } drm_r128_clear_t; typedef struct drm_r128_vertex { -- cgit v1.2.3 From c78e610fa42c8122ed6bc504222ef650f5693d22 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 28 Aug 2007 12:23:51 -0700 Subject: Add register defines for hw binning --- shared-core/i915_drv.h | 115 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) (limited to 'shared-core') diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 528f7b3a..aff03bee 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -272,12 +272,25 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); #define MI_NO_WRITE_FLUSH (1 << 2) #define MI_READ_FLUSH (1 << 0) #define MI_EXE_FLUSH (1 << 1) +#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ +#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ + +/* Packet to load a register value from the ring/batch command stream: + */ +#define CMD_MI_LOAD_REGISTER_IMM ((0x22 << 23)|0x1) #define BB1_START_ADDR_MASK (~0x7) #define BB1_PROTECTED (1<<0) #define BB1_UNPROTECTED (0<<0) #define BB2_END_ADDR_MASK (~0x7) +/* Interrupt bits: + */ +#define USER_INT_FLAG (1<<1) +#define VSYNC_PIPEB_FLAG (1<<5) +#define VSYNC_PIPEA_FLAG (1<<7) +#define HWB_OOM_FLAG (1<<13) /* binner out of memory */ + #define I915REG_HWSTAM 0x02098 #define I915REG_INT_IDENTITY_R 0x020a4 #define I915REG_INT_MASK_R 0x020a8 @@ -315,6 +328,10 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); #define NOPID 0x2094 #define LP_RING 0x2030 #define HP_RING 0x2040 +/* The binner has its own ring buffer: + */ +#define HWB_RING 0x2400 + #define RING_TAIL 0x00 #define TAIL_ADDR 0x001FFFF8 #define RING_HEAD 0x04 @@ -333,11 +350,105 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); #define RING_VALID 0x00000001 #define RING_INVALID 0x00000000 +/* Instruction parser error reg: + */ +#define IPEIR 0x2088 + +/* Scratch pad debug 0 reg: + */ +#define SCPD0 0x209c + +/* Error status reg: + */ +#define ESR 0x20b8 + +/* Secondary DMA fetch address debug reg: + */ +#define DMA_FADD_S 0x20d4 + +/* Cache mode 0 reg. + * - Manipulating render cache behaviour is central + * to the concept of zone rendering, tuning this reg can help avoid + * unnecessary render cache reads and even writes (for z/stencil) + * at beginning and end of scene. + * + * - To change a bit, write to this reg with a mask bit set and the + * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set. + */ +#define Cache_Mode_0 0x2120 +#define CM0_MASK_SHIFT 16 +#define CM0_IZ_OPT_DISABLE (1<<6) +#define CM0_ZR_OPT_DISABLE (1<<5) +#define CM0_DEPTH_EVICT_DISABLE (1<<4) +#define CM0_COLOR_EVICT_DISABLE (1<<3) +#define CM0_DEPTH_WRITE_DISABLE (1<<1) +#define CM0_RC_OP_FLUSH_DISABLE (1<<0) + + +/* Graphics flush control. A CPU write flushes the GWB of all writes. + * The data is discarded. + */ +#define GFX_FLSH_CNTL 0x2170 + +/* Binner control. Defines the location of the bin pointer list: + */ +#define BINCTL 0x2420 +#define BC_MASK (1 << 9) + +/* Binned scene info. + */ +#define BINSCENE 0x2428 +#define BS_OP_LOAD (1 << 8) +#define BS_MASK (1 << 22) + +/* Bin command parser debug reg: + */ +#define BCPD 0x2480 + +/* Bin memory control debug reg: + */ +#define BMCD 0x2484 + +/* Bin data cache debug reg: + */ +#define BDCD 0x2488 + +/* Binner pointer cache debug reg: + */ +#define BPCD 0x248c + +/* Binner scratch pad debug reg: + */ +#define BINSKPD 0x24f0 + +/* HWB scratch pad debug reg: + */ +#define HWBSKPD 0x24f4 + +/* Binner memory pool reg: + */ +#define BMP_BUFFER 0x2430 +#define BMP_PAGE_SIZE_4K (0 << 10) +#define BMP_BUFFER_SIZE_SHIFT 1 +#define BMP_ENABLE (1 << 0) + +/* Get/put memory from the binner memory pool: + */ +#define BMP_GET 0x2438 +#define BMP_PUT 0x2440 +#define BMP_OFFSET_SHIFT 5 + +/* 3D state packets: + */ +#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) + #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) #define SC_UPDATE_SCISSOR (0x1<<1) #define SC_ENABLE_MASK (0x1<<0) #define SC_ENABLE (0x1<<0) +#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) + #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) #define SCI_YMIN_MASK (0xffff<<16) #define SCI_XMIN_MASK (0xffff<<0) @@ -378,6 +489,10 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); #define DISPLAY_PLANE_A (0<<20) #define DISPLAY_PLANE_B (1<<20) +/* Define the region of interest for the binner: + */ +#define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4) + #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) #define BREADCRUMB_BITS 31 -- cgit v1.2.3 From 69b11f44f0a0cfe0806e18dae2f360bc1ed8e005 Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Thu, 30 Aug 2007 21:51:53 +0200 Subject: nouveau: give nv03 the last cut. --- shared-core/drm_pciids.txt | 7 ------- shared-core/nouveau_drm.h | 2 -- shared-core/nouveau_fifo.c | 3 --- shared-core/nouveau_mem.c | 12 ------------ shared-core/nouveau_state.c | 3 --- shared-core/nv04_instmem.c | 1 - 6 files changed, 28 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index 4bd690b2..8d90f3a7 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -482,9 +482,6 @@ 0x10DE 0x009E NV40 "NVidia 0x009E" [nouveau] -0x10de 0x0008 NV_03 "EDGE 3D" -0x10de 0x0009 NV_03 "EDGE 3D" -0x10de 0x0010 NV_03 "Mutara V08" 0x10de 0x0020 NV_04 "RIVA TNT" 0x10de 0x0028 NV_04 "RIVA TNT2/TNT2 Pro" 0x10de 0x0029 NV_04 "RIVA TNT2 Ultra" @@ -732,10 +729,6 @@ 0x10de 0x0421 NV_50 "GeForce 8500 GT" 0x10de 0x0422 NV_50 "GeForce 8400 GS" 0x10de 0x0423 NV_50 "GeForce 8300 GS" -0x12d2 0x0008 NV_03 "NV1" -0x12d2 0x0009 NV_03 "DAC64" -0x12d2 0x0018 NV_03 "Riva128" -0x12d2 0x0019 NV_03 "Riva128ZX" 0x12d2 0x0020 NV_04 "TNT" 0x12d2 0x0028 NV_04 "TNT2" 0x12d2 0x0029 NV_04 "UTNT2" diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h index bfc9bd4b..c4f1e9a4 100644 --- a/shared-core/nouveau_drm.h +++ b/shared-core/nouveau_drm.h @@ -119,8 +119,6 @@ struct drm_nouveau_setparam { enum nouveau_card_type { NV_UNKNOWN =0, - NV_01 =1, - NV_03 =3, NV_04 =4, NV_05 =5, NV_10 =10, diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 1aa724f1..437c84f2 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -34,8 +34,6 @@ int nouveau_fifo_number(struct drm_device *dev) struct drm_nouveau_private *dev_priv=dev->dev_private; switch(dev_priv->card_type) { - case NV_03: - return 8; case NV_04: case NV_05: return 16; @@ -109,7 +107,6 @@ static int nouveau_fifo_instmem_configure(struct drm_device *dev) case NV_11: case NV_10: case NV_04: - case NV_03: NV_WRITE(NV03_PFIFO_RAMFC, dev_priv->ramfc_offset>>8); break; } diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 2cc0ed77..dbfba351 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -257,18 +257,6 @@ uint64_t nouveau_mem_fb_amount(struct drm_device *dev) struct drm_nouveau_private *dev_priv=dev->dev_private; switch(dev_priv->card_type) { - case NV_03: - switch(NV_READ(NV03_BOOT_0)&NV03_BOOT_0_RAM_AMOUNT) - { - case NV03_BOOT_0_RAM_AMOUNT_8MB: - case NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM: - return 8*1024*1024; - case NV03_BOOT_0_RAM_AMOUNT_4MB: - return 4*1024*1024; - case NV03_BOOT_0_RAM_AMOUNT_2MB: - return 2*1024*1024; - } - break; case NV_04: case NV_05: if (NV_READ(NV03_BOOT_0) & 0x00000100) { diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index d885f7c6..e73b4878 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -538,9 +538,6 @@ void nouveau_wait_for_idle(struct drm_device *dev) { struct drm_nouveau_private *dev_priv=dev->dev_private; switch(dev_priv->card_type) { - case NV_03: - while (NV_READ(NV03_PGRAPH_STATUS)); - break; case NV_50: break; default: { diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index fed6ff7e..5a446450 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -70,7 +70,6 @@ nv04_instmem_configure_fixed_tables(struct drm_device *dev) case NV_11: case NV_10: case NV_04: - case NV_03: default: dev_priv->ramfc_offset = 0x11400; dev_priv->ramfc_size = nouveau_fifo_number(dev) * -- cgit v1.2.3 From bac3f49daa54bf34ea21854be23061d10a0d0d1b Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Fri, 31 Aug 2007 01:39:40 +0200 Subject: nouveau: nv04 context switching support. Works for starting X up at least. --- shared-core/nv04_graph.c | 638 ++++++++++++++++++++++++++--------------------- 1 file changed, 348 insertions(+), 290 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c index 050f6e81..213696ca 100644 --- a/shared-core/nv04_graph.c +++ b/shared-core/nv04_graph.c @@ -27,262 +27,321 @@ #include "nouveau_drm.h" #include "nouveau_drv.h" -struct reg_interval -{ - uint32_t reg; - int number; -} nv04_graph_ctx_regs [] = { - {NV04_PGRAPH_CTX_SWITCH1,1}, - {NV04_PGRAPH_CTX_SWITCH2,1}, - {NV04_PGRAPH_CTX_SWITCH3,1}, - {NV04_PGRAPH_CTX_SWITCH4,1}, - {NV04_PGRAPH_CTX_CACHE1,1}, - {NV04_PGRAPH_CTX_CACHE2,1}, - {NV04_PGRAPH_CTX_CACHE3,1}, - {NV04_PGRAPH_CTX_CACHE4,1}, - {0x00400184,1}, - {0x004001a4,1}, - {0x004001c4,1}, - {0x004001e4,1}, - {0x00400188,1}, - {0x004001a8,1}, - {0x004001c8,1}, - {0x004001e8,1}, - {0x0040018c,1}, - {0x004001ac,1}, - {0x004001cc,1}, - {0x004001ec,1}, - {0x00400190,1}, - {0x004001b0,1}, - {0x004001d0,1}, - {0x004001f0,1}, - {0x00400194,1}, - {0x004001b4,1}, - {0x004001d4,1}, - {0x004001f4,1}, - {0x00400198,1}, - {0x004001b8,1}, - {0x004001d8,1}, - {0x004001f8,1}, - {0x0040019c,1}, - {0x004001bc,1}, - {0x004001dc,1}, - {0x004001fc,1}, - {0x00400174,1}, - {NV04_PGRAPH_DMA_START_0,1}, - {NV04_PGRAPH_DMA_START_1,1}, - {NV04_PGRAPH_DMA_LENGTH,1}, - {NV04_PGRAPH_DMA_MISC,1}, - {NV04_PGRAPH_DMA_PITCH,1}, - {NV04_PGRAPH_BOFFSET0,1}, - {NV04_PGRAPH_BBASE0,1}, - {NV04_PGRAPH_BLIMIT0,1}, - {NV04_PGRAPH_BOFFSET1,1}, - {NV04_PGRAPH_BBASE1,1}, - {NV04_PGRAPH_BLIMIT1,1}, - {NV04_PGRAPH_BOFFSET2,1}, - {NV04_PGRAPH_BBASE2,1}, - {NV04_PGRAPH_BLIMIT2,1}, - {NV04_PGRAPH_BOFFSET3,1}, - {NV04_PGRAPH_BBASE3,1}, - {NV04_PGRAPH_BLIMIT3,1}, - {NV04_PGRAPH_BOFFSET4,1}, - {NV04_PGRAPH_BBASE4,1}, - {NV04_PGRAPH_BLIMIT4,1}, - {NV04_PGRAPH_BOFFSET5,1}, - {NV04_PGRAPH_BBASE5,1}, - {NV04_PGRAPH_BLIMIT5,1}, - {NV04_PGRAPH_BPITCH0,1}, - {NV04_PGRAPH_BPITCH1,1}, - {NV04_PGRAPH_BPITCH2,1}, - {NV04_PGRAPH_BPITCH3,1}, - {NV04_PGRAPH_BPITCH4,1}, - {NV04_PGRAPH_SURFACE,1}, - {NV04_PGRAPH_STATE,1}, - {NV04_PGRAPH_BSWIZZLE2,1}, - {NV04_PGRAPH_BSWIZZLE5,1}, - {NV04_PGRAPH_BPIXEL,1}, - {NV04_PGRAPH_NOTIFY,1}, - {NV04_PGRAPH_PATT_COLOR0,1}, - {NV04_PGRAPH_PATT_COLOR1,1}, - {NV04_PGRAPH_PATT_COLORRAM,64}, - {NV04_PGRAPH_PATTERN,1}, - {0x0040080c,1}, - {NV04_PGRAPH_PATTERN_SHAPE,1}, - {0x00400600,1}, - {NV04_PGRAPH_ROP3,1}, - {NV04_PGRAPH_CHROMA,1}, - {NV04_PGRAPH_BETA_AND,1}, - {NV04_PGRAPH_BETA_PREMULT,1}, - {NV04_PGRAPH_CONTROL0,1}, - {NV04_PGRAPH_CONTROL1,1}, - {NV04_PGRAPH_CONTROL2,1}, - {NV04_PGRAPH_BLEND,1}, - {NV04_PGRAPH_STORED_FMT,1}, - {NV04_PGRAPH_SOURCE_COLOR,1}, - {0x00400560,1}, - {0x00400568,1}, - {0x00400564,1}, - {0x0040056c,1}, - {0x00400400,1}, - {0x00400480,1}, - {0x00400404,1}, - {0x00400484,1}, - {0x00400408,1}, - {0x00400488,1}, - {0x0040040c,1}, - {0x0040048c,1}, - {0x00400410,1}, - {0x00400490,1}, - {0x00400414,1}, - {0x00400494,1}, - {0x00400418,1}, - {0x00400498,1}, - {0x0040041c,1}, - {0x0040049c,1}, - {0x00400420,1}, - {0x004004a0,1}, - {0x00400424,1}, - {0x004004a4,1}, - {0x00400428,1}, - {0x004004a8,1}, - {0x0040042c,1}, - {0x004004ac,1}, - {0x00400430,1}, - {0x004004b0,1}, - {0x00400434,1}, - {0x004004b4,1}, - {0x00400438,1}, - {0x004004b8,1}, - {0x0040043c,1}, - {0x004004bc,1}, - {0x00400440,1}, - {0x004004c0,1}, - {0x00400444,1}, - {0x004004c4,1}, - {0x00400448,1}, - {0x004004c8,1}, - {0x0040044c,1}, - {0x004004cc,1}, - {0x00400450,1}, - {0x004004d0,1}, - {0x00400454,1}, - {0x004004d4,1}, - {0x00400458,1}, - {0x004004d8,1}, - {0x0040045c,1}, - {0x004004dc,1}, - {0x00400460,1}, - {0x004004e0,1}, - {0x00400464,1}, - {0x004004e4,1}, - {0x00400468,1}, - {0x004004e8,1}, - {0x0040046c,1}, - {0x004004ec,1}, - {0x00400470,1}, - {0x004004f0,1}, - {0x00400474,1}, - {0x004004f4,1}, - {0x00400478,1}, - {0x004004f8,1}, - {0x0040047c,1}, - {0x004004fc,1}, - {0x0040053c,1}, - {0x00400544,1}, - {0x00400540,1}, - {0x00400548,1}, - {0x00400560,1}, - {0x00400568,1}, - {0x00400564,1}, - {0x0040056c,1}, - {0x00400534,1}, - {0x00400538,1}, - {0x00400514,1}, - {0x00400518,1}, - {0x0040051c,1}, - {0x00400520,1}, - {0x00400524,1}, - {0x00400528,1}, - {0x0040052c,1}, - {0x00400530,1}, - {0x00400d00,1}, - {0x00400d40,1}, - {0x00400d80,1}, - {0x00400d04,1}, - {0x00400d44,1}, - {0x00400d84,1}, - {0x00400d08,1}, - {0x00400d48,1}, - {0x00400d88,1}, - {0x00400d0c,1}, - {0x00400d4c,1}, - {0x00400d8c,1}, - {0x00400d10,1}, - {0x00400d50,1}, - {0x00400d90,1}, - {0x00400d14,1}, - {0x00400d54,1}, - {0x00400d94,1}, - {0x00400d18,1}, - {0x00400d58,1}, - {0x00400d98,1}, - {0x00400d1c,1}, - {0x00400d5c,1}, - {0x00400d9c,1}, - {0x00400d20,1}, - {0x00400d60,1}, - {0x00400da0,1}, - {0x00400d24,1}, - {0x00400d64,1}, - {0x00400da4,1}, - {0x00400d28,1}, - {0x00400d68,1}, - {0x00400da8,1}, - {0x00400d2c,1}, - {0x00400d6c,1}, - {0x00400dac,1}, - {0x00400d30,1}, - {0x00400d70,1}, - {0x00400db0,1}, - {0x00400d34,1}, - {0x00400d74,1}, - {0x00400db4,1}, - {0x00400d38,1}, - {0x00400d78,1}, - {0x00400db8,1}, - {0x00400d3c,1}, - {0x00400d7c,1}, - {0x00400dbc,1}, - {0x00400590,1}, - {0x00400594,1}, - {0x00400598,1}, - {0x0040059c,1}, - {0x004005a8,1}, - {0x004005ac,1}, - {0x004005b0,1}, - {0x004005b4,1}, - {0x004005c0,1}, - {0x004005c4,1}, - {0x004005c8,1}, - {0x004005cc,1}, - {0x004005d0,1}, - {0x004005d4,1}, - {0x004005d8,1}, - {0x004005dc,1}, - {0x004005e0,1}, - {NV04_PGRAPH_PASSTHRU_0,1}, - {NV04_PGRAPH_PASSTHRU_1,1}, - {NV04_PGRAPH_PASSTHRU_2,1}, - {NV04_PGRAPH_DVD_COLORFMT,1}, - {NV04_PGRAPH_SCALED_FORMAT,1}, - {NV04_PGRAPH_MISC24_0,1}, - {NV04_PGRAPH_MISC24_1,1}, - {NV04_PGRAPH_MISC24_2,1}, - {0x00400500,1}, - {0x00400504,1}, - {NV04_PGRAPH_VALID1,1}, - {NV04_PGRAPH_VALID2,1} +static uint32_t nv04_graph_ctx_regs [] = { + NV04_PGRAPH_CTX_SWITCH1, + NV04_PGRAPH_CTX_SWITCH2, + NV04_PGRAPH_CTX_SWITCH3, + NV04_PGRAPH_CTX_SWITCH4, + NV04_PGRAPH_CTX_CACHE1, + NV04_PGRAPH_CTX_CACHE2, + NV04_PGRAPH_CTX_CACHE3, + NV04_PGRAPH_CTX_CACHE4, + 0x00400184, + 0x004001a4, + 0x004001c4, + 0x004001e4, + 0x00400188, + 0x004001a8, + 0x004001c8, + 0x004001e8, + 0x0040018c, + 0x004001ac, + 0x004001cc, + 0x004001ec, + 0x00400190, + 0x004001b0, + 0x004001d0, + 0x004001f0, + 0x00400194, + 0x004001b4, + 0x004001d4, + 0x004001f4, + 0x00400198, + 0x004001b8, + 0x004001d8, + 0x004001f8, + 0x0040019c, + 0x004001bc, + 0x004001dc, + 0x004001fc, + 0x00400174, + NV04_PGRAPH_DMA_START_0, + NV04_PGRAPH_DMA_START_1, + NV04_PGRAPH_DMA_LENGTH, + NV04_PGRAPH_DMA_MISC, + NV04_PGRAPH_DMA_PITCH, + NV04_PGRAPH_BOFFSET0, + NV04_PGRAPH_BBASE0, + NV04_PGRAPH_BLIMIT0, + NV04_PGRAPH_BOFFSET1, + NV04_PGRAPH_BBASE1, + NV04_PGRAPH_BLIMIT1, + NV04_PGRAPH_BOFFSET2, + NV04_PGRAPH_BBASE2, + NV04_PGRAPH_BLIMIT2, + NV04_PGRAPH_BOFFSET3, + NV04_PGRAPH_BBASE3, + NV04_PGRAPH_BLIMIT3, + NV04_PGRAPH_BOFFSET4, + NV04_PGRAPH_BBASE4, + NV04_PGRAPH_BLIMIT4, + NV04_PGRAPH_BOFFSET5, + NV04_PGRAPH_BBASE5, + NV04_PGRAPH_BLIMIT5, + NV04_PGRAPH_BPITCH0, + NV04_PGRAPH_BPITCH1, + NV04_PGRAPH_BPITCH2, + NV04_PGRAPH_BPITCH3, + NV04_PGRAPH_BPITCH4, + NV04_PGRAPH_SURFACE, + NV04_PGRAPH_STATE, + NV04_PGRAPH_BSWIZZLE2, + NV04_PGRAPH_BSWIZZLE5, + NV04_PGRAPH_BPIXEL, + NV04_PGRAPH_NOTIFY, + NV04_PGRAPH_PATT_COLOR0, + NV04_PGRAPH_PATT_COLOR1, + NV04_PGRAPH_PATT_COLORRAM+0x00, + NV04_PGRAPH_PATT_COLORRAM+0x01, + NV04_PGRAPH_PATT_COLORRAM+0x02, + NV04_PGRAPH_PATT_COLORRAM+0x03, + NV04_PGRAPH_PATT_COLORRAM+0x04, + NV04_PGRAPH_PATT_COLORRAM+0x05, + NV04_PGRAPH_PATT_COLORRAM+0x06, + NV04_PGRAPH_PATT_COLORRAM+0x07, + NV04_PGRAPH_PATT_COLORRAM+0x08, + NV04_PGRAPH_PATT_COLORRAM+0x09, + NV04_PGRAPH_PATT_COLORRAM+0x0A, + NV04_PGRAPH_PATT_COLORRAM+0x0B, + NV04_PGRAPH_PATT_COLORRAM+0x0C, + NV04_PGRAPH_PATT_COLORRAM+0x0D, + NV04_PGRAPH_PATT_COLORRAM+0x0E, + NV04_PGRAPH_PATT_COLORRAM+0x0F, + NV04_PGRAPH_PATT_COLORRAM+0x10, + NV04_PGRAPH_PATT_COLORRAM+0x11, + NV04_PGRAPH_PATT_COLORRAM+0x12, + NV04_PGRAPH_PATT_COLORRAM+0x13, + NV04_PGRAPH_PATT_COLORRAM+0x14, + NV04_PGRAPH_PATT_COLORRAM+0x15, + NV04_PGRAPH_PATT_COLORRAM+0x16, + NV04_PGRAPH_PATT_COLORRAM+0x17, + NV04_PGRAPH_PATT_COLORRAM+0x18, + NV04_PGRAPH_PATT_COLORRAM+0x19, + NV04_PGRAPH_PATT_COLORRAM+0x1A, + NV04_PGRAPH_PATT_COLORRAM+0x1B, + NV04_PGRAPH_PATT_COLORRAM+0x1C, + NV04_PGRAPH_PATT_COLORRAM+0x1D, + NV04_PGRAPH_PATT_COLORRAM+0x1E, + NV04_PGRAPH_PATT_COLORRAM+0x1F, + NV04_PGRAPH_PATT_COLORRAM+0x20, + NV04_PGRAPH_PATT_COLORRAM+0x21, + NV04_PGRAPH_PATT_COLORRAM+0x22, + NV04_PGRAPH_PATT_COLORRAM+0x23, + NV04_PGRAPH_PATT_COLORRAM+0x24, + NV04_PGRAPH_PATT_COLORRAM+0x25, + NV04_PGRAPH_PATT_COLORRAM+0x26, + NV04_PGRAPH_PATT_COLORRAM+0x27, + NV04_PGRAPH_PATT_COLORRAM+0x28, + NV04_PGRAPH_PATT_COLORRAM+0x29, + NV04_PGRAPH_PATT_COLORRAM+0x2A, + NV04_PGRAPH_PATT_COLORRAM+0x2B, + NV04_PGRAPH_PATT_COLORRAM+0x2C, + NV04_PGRAPH_PATT_COLORRAM+0x2D, + NV04_PGRAPH_PATT_COLORRAM+0x2E, + NV04_PGRAPH_PATT_COLORRAM+0x2F, + NV04_PGRAPH_PATT_COLORRAM+0x30, + NV04_PGRAPH_PATT_COLORRAM+0x31, + NV04_PGRAPH_PATT_COLORRAM+0x32, + NV04_PGRAPH_PATT_COLORRAM+0x33, + NV04_PGRAPH_PATT_COLORRAM+0x34, + NV04_PGRAPH_PATT_COLORRAM+0x35, + NV04_PGRAPH_PATT_COLORRAM+0x36, + NV04_PGRAPH_PATT_COLORRAM+0x37, + NV04_PGRAPH_PATT_COLORRAM+0x38, + NV04_PGRAPH_PATT_COLORRAM+0x39, + NV04_PGRAPH_PATT_COLORRAM+0x3A, + NV04_PGRAPH_PATT_COLORRAM+0x3B, + NV04_PGRAPH_PATT_COLORRAM+0x3C, + NV04_PGRAPH_PATT_COLORRAM+0x3D, + NV04_PGRAPH_PATT_COLORRAM+0x3E, + NV04_PGRAPH_PATT_COLORRAM+0x3F, + NV04_PGRAPH_PATTERN, + 0x0040080c, + NV04_PGRAPH_PATTERN_SHAPE, + 0x00400600, + NV04_PGRAPH_ROP3, + NV04_PGRAPH_CHROMA, + NV04_PGRAPH_BETA_AND, + NV04_PGRAPH_BETA_PREMULT, + NV04_PGRAPH_CONTROL0, + NV04_PGRAPH_CONTROL1, + NV04_PGRAPH_CONTROL2, + NV04_PGRAPH_BLEND, + NV04_PGRAPH_STORED_FMT, + NV04_PGRAPH_SOURCE_COLOR, + 0x00400560, + 0x00400568, + 0x00400564, + 0x0040056c, + 0x00400400, + 0x00400480, + 0x00400404, + 0x00400484, + 0x00400408, + 0x00400488, + 0x0040040c, + 0x0040048c, + 0x00400410, + 0x00400490, + 0x00400414, + 0x00400494, + 0x00400418, + 0x00400498, + 0x0040041c, + 0x0040049c, + 0x00400420, + 0x004004a0, + 0x00400424, + 0x004004a4, + 0x00400428, + 0x004004a8, + 0x0040042c, + 0x004004ac, + 0x00400430, + 0x004004b0, + 0x00400434, + 0x004004b4, + 0x00400438, + 0x004004b8, + 0x0040043c, + 0x004004bc, + 0x00400440, + 0x004004c0, + 0x00400444, + 0x004004c4, + 0x00400448, + 0x004004c8, + 0x0040044c, + 0x004004cc, + 0x00400450, + 0x004004d0, + 0x00400454, + 0x004004d4, + 0x00400458, + 0x004004d8, + 0x0040045c, + 0x004004dc, + 0x00400460, + 0x004004e0, + 0x00400464, + 0x004004e4, + 0x00400468, + 0x004004e8, + 0x0040046c, + 0x004004ec, + 0x00400470, + 0x004004f0, + 0x00400474, + 0x004004f4, + 0x00400478, + 0x004004f8, + 0x0040047c, + 0x004004fc, + 0x0040053c, + 0x00400544, + 0x00400540, + 0x00400548, + 0x00400560, + 0x00400568, + 0x00400564, + 0x0040056c, + 0x00400534, + 0x00400538, + 0x00400514, + 0x00400518, + 0x0040051c, + 0x00400520, + 0x00400524, + 0x00400528, + 0x0040052c, + 0x00400530, + 0x00400d00, + 0x00400d40, + 0x00400d80, + 0x00400d04, + 0x00400d44, + 0x00400d84, + 0x00400d08, + 0x00400d48, + 0x00400d88, + 0x00400d0c, + 0x00400d4c, + 0x00400d8c, + 0x00400d10, + 0x00400d50, + 0x00400d90, + 0x00400d14, + 0x00400d54, + 0x00400d94, + 0x00400d18, + 0x00400d58, + 0x00400d98, + 0x00400d1c, + 0x00400d5c, + 0x00400d9c, + 0x00400d20, + 0x00400d60, + 0x00400da0, + 0x00400d24, + 0x00400d64, + 0x00400da4, + 0x00400d28, + 0x00400d68, + 0x00400da8, + 0x00400d2c, + 0x00400d6c, + 0x00400dac, + 0x00400d30, + 0x00400d70, + 0x00400db0, + 0x00400d34, + 0x00400d74, + 0x00400db4, + 0x00400d38, + 0x00400d78, + 0x00400db8, + 0x00400d3c, + 0x00400d7c, + 0x00400dbc, + 0x00400590, + 0x00400594, + 0x00400598, + 0x0040059c, + 0x004005a8, + 0x004005ac, + 0x004005b0, + 0x004005b4, + 0x004005c0, + 0x004005c4, + 0x004005c8, + 0x004005cc, + 0x004005d0, + 0x004005d4, + 0x004005d8, + 0x004005dc, + 0x004005e0, + NV04_PGRAPH_PASSTHRU_0, + NV04_PGRAPH_PASSTHRU_1, + NV04_PGRAPH_PASSTHRU_2, + NV04_PGRAPH_DVD_COLORFMT, + NV04_PGRAPH_SCALED_FORMAT, + NV04_PGRAPH_MISC24_0, + NV04_PGRAPH_MISC24_1, + NV04_PGRAPH_MISC24_2, + 0x00400500, + 0x00400504, + NV04_PGRAPH_VALID1, + NV04_PGRAPH_VALID2 }; @@ -290,43 +349,35 @@ struct reg_interval void nouveau_nv04_context_switch(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - int channel, channel_old, i, j, index; + struct nouveau_channel *next, *last; + int chid; + + chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); + next = dev_priv->fifos[chid]; - channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); - channel_old = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + chid = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + last = dev_priv->fifos[chid]; - DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel); + DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",last->id, next->id); NV_WRITE(NV03_PFIFO_CACHES, 0x0); NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0); NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0); NV_WRITE(NV04_PGRAPH_FIFO,0x0); - nouveau_wait_for_idle(dev); + nv04_graph_save_context(last); - // save PGRAPH context - index=0; - for (i = 0; ififos[channel_old]->pgraph_ctx[index] = NV_READ(nv04_graph_ctx_regs[i].reg+j*4); - index++; - } + nouveau_wait_for_idle(dev); NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10000000); NV_WRITE(NV04_PGRAPH_CTX_USER, (NV_READ(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x0f << 24)); - // restore PGRAPH context - index=0; - for (i = 0; ififos[channel]->pgraph_ctx[index]); - index++; - } + nouveau_wait_for_idle(dev); + + nv04_graph_load_context(last); NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100); - NV_WRITE(NV04_PGRAPH_CTX_USER, channel << 24); + NV_WRITE(NV04_PGRAPH_CTX_USER, next->id << 24); NV_WRITE(NV04_PGRAPH_FFINTFC_ST2, NV_READ(NV04_PGRAPH_FFINTFC_ST2)&0x000FFFFF); NV_WRITE(NV04_PGRAPH_FIFO,0x0); @@ -356,19 +407,30 @@ void nv04_graph_destroy_context(struct nouveau_channel *chan) int nv04_graph_load_context(struct nouveau_channel *chan) { - DRM_ERROR("stub!\n"); + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; + + for (i = 0; i < sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++) + NV_WRITE(nv04_graph_ctx_regs[i], chan->pgraph_ctx[i]); + return 0; } int nv04_graph_save_context(struct nouveau_channel *chan) { - DRM_ERROR("stub!\n"); + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; + + for (i = 0; i < sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++) + chan->pgraph_ctx[i] = NV_READ(nv04_graph_ctx_regs[i]); + return 0; } int nv04_graph_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - int i,sum=0; NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH); @@ -380,23 +442,19 @@ int nv04_graph_init(struct drm_device *dev) { NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); // check the context is big enough - for ( i = 0 ; isizeof(dev_priv->fifos[0]->pgraph_ctx) ) + if ( sizeof(nv04_graph_ctx_regs)>sizeof(dev_priv->fifos[0]->pgraph_ctx) ) DRM_ERROR("pgraph_ctx too small\n"); - NV_WRITE(NV03_PGRAPH_INTR_EN, 0x00000000); - NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x000001FF); - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x1230C000); - NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x72111101); - NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x11D5F071); + NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x1231c000); + NV_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100); + NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x11d5f870); NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x0004FF31); NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x4004FF31 | (0x00D00000) | (1<<29) | (1<<31)); + NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xfad4ff31); NV_WRITE(NV04_PGRAPH_STATE , 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_CTX_CONTROL , 0x10010100); -- cgit v1.2.3 From ef4944de85b974e6b91087fdcb8f241f2619d28d Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Tue, 4 Sep 2007 18:51:57 +0200 Subject: Add context init voodoo and context switch code for NV41. --- shared-core/nv40_graph.c | 147 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index 26237c7d..99c77cb9 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -34,6 +34,7 @@ * between the contexts */ #define NV40_GRCTX_SIZE (175*1024) +#define NV41_GRCTX_SIZE (92*1024) #define NV43_GRCTX_SIZE (70*1024) #define NV46_GRCTX_SIZE (70*1024) /* probably ~64KiB */ #define NV49_GRCTX_SIZE (164640) @@ -187,6 +188,116 @@ nv40_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) INSTANCE_WR(ctx, i/4, 0x3f800000); } +static void +nv41_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; + + INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start); + INSTANCE_WR(ctx, 0x00000024/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x00000028/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x00000030/4, 0x00000001); + INSTANCE_WR(ctx, 0x0000011c/4, 0x20010001); + INSTANCE_WR(ctx, 0x00000120/4, 0x0f73ef00); + INSTANCE_WR(ctx, 0x00000128/4, 0x02008821); + for (i = 0x00000178; i <= 0x00000180; i += 4) + INSTANCE_WR(ctx, i/4, 0x00000040); + INSTANCE_WR(ctx, 0x00000188/4, 0x00000040); + for (i = 0x00000194; i <= 0x000001b0; i += 4) + INSTANCE_WR(ctx, i/4, 0x80000000); + INSTANCE_WR(ctx, 0x000001d0/4, 0x0b0b0b0c); + INSTANCE_WR(ctx, 0x00000340/4, 0x00040000); + for (i = 0x00000350; i <= 0x0000035c; i += 4) + INSTANCE_WR(ctx, i/4, 0x55555555); + INSTANCE_WR(ctx, 0x00000388/4, 0x00000008); + INSTANCE_WR(ctx, 0x0000039c/4, 0x00001010); + INSTANCE_WR(ctx, 0x000003cc/4, 0x00000111); + INSTANCE_WR(ctx, 0x000003d0/4, 0x00080060); + INSTANCE_WR(ctx, 0x000003ec/4, 0x00000080); + INSTANCE_WR(ctx, 0x000003f0/4, 0xffff0000); + INSTANCE_WR(ctx, 0x000003f4/4, 0x00000001); + INSTANCE_WR(ctx, 0x00000408/4, 0x46400000); + INSTANCE_WR(ctx, 0x00000418/4, 0xffff0000); + INSTANCE_WR(ctx, 0x00000424/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x00000428/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x00000430/4, 0x00011100); + for (i = 0x0000044c; i <= 0x00000488; i += 4) + INSTANCE_WR(ctx, i/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x00000494/4, 0x4b7fffff); + INSTANCE_WR(ctx, 0x000004bc/4, 0x30201000); + INSTANCE_WR(ctx, 0x000004c0/4, 0x70605040); + INSTANCE_WR(ctx, 0x000004c4/4, 0xb8a89888); + INSTANCE_WR(ctx, 0x000004c8/4, 0xf8e8d8c8); + INSTANCE_WR(ctx, 0x000004dc/4, 0x40100000); + INSTANCE_WR(ctx, 0x000004f8/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x0000052c/4, 0x435185d6); + INSTANCE_WR(ctx, 0x00000530/4, 0x2155b699); + INSTANCE_WR(ctx, 0x00000534/4, 0xfedcba98); + INSTANCE_WR(ctx, 0x00000538/4, 0x00000098); + INSTANCE_WR(ctx, 0x00000548/4, 0xffffffff); + INSTANCE_WR(ctx, 0x0000054c/4, 0x00ff7000); + INSTANCE_WR(ctx, 0x00000550/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x00000560/4, 0x00ff0000); + INSTANCE_WR(ctx, 0x00000598/4, 0x00ffff00); + for (i = 0x000005dc; i <= 0x00000618; i += 4) + INSTANCE_WR(ctx, i/4, 0x00018488); + for (i = 0x0000061c; i <= 0x00000658; i += 4) + INSTANCE_WR(ctx, i/4, 0x00028202); + for (i = 0x0000069c; i <= 0x000006d8; i += 4) + INSTANCE_WR(ctx, i/4, 0x0000aae4); + for (i = 0x000006dc; i <= 0x00000718; i += 4) + INSTANCE_WR(ctx, i/4, 0x01012000); + for (i = 0x0000071c; i <= 0x00000758; i += 4) + INSTANCE_WR(ctx, i/4, 0x00080008); + for (i = 0x0000079c; i <= 0x000007d8; i += 4) + INSTANCE_WR(ctx, i/4, 0x00100008); + for (i = 0x0000082c; i <= 0x00000838; i += 4) + INSTANCE_WR(ctx, i/4, 0x0001bc80); + for (i = 0x0000083c; i <= 0x00000848; i += 4) + INSTANCE_WR(ctx, i/4, 0x00000202); + for (i = 0x0000085c; i <= 0x00000868; i += 4) + INSTANCE_WR(ctx, i/4, 0x00000008); + for (i = 0x0000087c; i <= 0x00000888; i += 4) + INSTANCE_WR(ctx, i/4, 0x00080008); + INSTANCE_WR(ctx, 0x0000089c/4, 0x00000002); + INSTANCE_WR(ctx, 0x000008d0/4, 0x00000021); + INSTANCE_WR(ctx, 0x000008d4/4, 0x030c30c3); + INSTANCE_WR(ctx, 0x000008e0/4, 0x3e020200); + INSTANCE_WR(ctx, 0x000008e4/4, 0x00ffffff); + INSTANCE_WR(ctx, 0x000008e8/4, 0x20103f00); + INSTANCE_WR(ctx, 0x000008f4/4, 0x00020000); + INSTANCE_WR(ctx, 0x0000092c/4, 0x00008100); + INSTANCE_WR(ctx, 0x000009b8/4, 0x00000001); + INSTANCE_WR(ctx, 0x000009fc/4, 0x00001001); + INSTANCE_WR(ctx, 0x00000a04/4, 0x00000003); + INSTANCE_WR(ctx, 0x00000a08/4, 0x00888001); + INSTANCE_WR(ctx, 0x00000aac/4, 0x00000005); + INSTANCE_WR(ctx, 0x00000ab8/4, 0x0000ffff); + for (i = 0x00000ad4; i <= 0x00000ae4; i += 4) + INSTANCE_WR(ctx, i/4, 0x00005555); + INSTANCE_WR(ctx, 0x00000ae8/4, 0x00000001); + INSTANCE_WR(ctx, 0x00000b20/4, 0x00000001); + for (i = 0x00002ee8; i <= 0x00002f60; i += 8) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i = 0x00005168; i <= 0x00007358; i += 24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for (i = 0x00007368; i <= 0x00007758; i += 16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i = 0x0000a068; i <= 0x0000c258; i += 24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for (i = 0x0000c268; i <= 0x0000c658; i += 16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i = 0x0000ef68; i <= 0x00011158; i += 24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for (i = 0x00011168; i <= 0x00011558; i += 16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i = 0x00013e68; i <= 0x00016058; i += 24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for (i = 0x00016068; i <= 0x00016458; i += 16) + INSTANCE_WR(ctx, i/4, 0x3f800000); +}; + static void nv43_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { @@ -1237,6 +1348,10 @@ nv40_graph_create_context(struct nouveau_channel *chan) ctx_size = NV40_GRCTX_SIZE; ctx_init = nv40_graph_context_init; break; + case 0x41: + ctx_size = NV41_GRCTX_SIZE; + ctx_init = nv41_graph_context_init; + break; case 0x43: ctx_size = NV43_GRCTX_SIZE; ctx_init = nv43_graph_context_init; @@ -1431,6 +1546,37 @@ static uint32_t nv40_ctx_voodoo[] = { ~0 }; +static uint32_t nv41_ctx_voodoo[] = { + 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, + 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00408f65, 0x00409306, + 0x0040a068, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042, + 0x00200001, 0x0060000a, 0x00700000, 0x001040c5, 0x00401826, 0x00401968, + 0x0060000d, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080, + 0x004020e6, 0x007000a0, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d, + 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4, + 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e, + 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143, + 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10, + 0x001046ec, 0x00500060, 0x00404087, 0x0060000d, 0x004079e6, 0x002000f1, + 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b, + 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6, + 0x00200020, 0x001006cc, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700, + 0x0010c3d7, 0x001043e1, 0x00500060, 0x00200233, 0x0060000a, 0x00104800, + 0x00108901, 0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00148a00, + 0x00108a14, 0x00200020, 0x00100b00, 0x00134b2c, 0x0010cd00, 0x0010cd04, + 0x00114d08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06, + 0x002002d2, 0x0060000a, 0x00300000, 0x00200680, 0x00407200, 0x00200684, + 0x00800001, 0x00200b1a, 0x0060000a, 0x00206380, 0x0040788a, 0x00201480, + 0x00800041, 0x00408900, 0x00600006, 0x004085e6, 0x00700080, 0x0020007a, + 0x0060000a, 0x00104280, 0x002002d2, 0x0060000a, 0x00200004, 0x00800001, + 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a068, 0x00700000, + 0x00200000, 0x0060000a, 0x00106002, 0x00700080, 0x00400a68, 0x00500060, + 0x00600007, 0x00409388, 0x0060000f, 0x00500060, 0x00200000, 0x0060000a, + 0x00700000, 0x00106001, 0x00910880, 0x00901ffe, 0x00940400, 0x00200020, + 0x0060000b, 0x00500069, 0x0060000c, 0x00402168, 0x0040a206, 0x0040a305, + 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0 +}; + static uint32_t nv43_ctx_voodoo[] = { 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409565, 0x00409a06, @@ -1683,6 +1829,7 @@ nv40_graph_init(struct drm_device *dev) switch (dev_priv->chipset) { case 0x40: ctx_voodoo = nv40_ctx_voodoo; break; + case 0x41: ctx_voodoo = nv41_ctx_voodoo; break; case 0x43: ctx_voodoo = nv43_ctx_voodoo; break; case 0x44: ctx_voodoo = nv44_ctx_voodoo; break; case 0x46: ctx_voodoo = nv46_ctx_voodoo; break; -- cgit v1.2.3 From ff9a019cf06b7ebaf2fa8dee8e37c866ca4623af Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Thu, 6 Sep 2007 02:12:05 +0200 Subject: nouveau: add pure nv30 support. --- shared-core/nv30_graph.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index ca43bb95..590a5c33 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -8,9 +8,8 @@ #include "nouveau_drm.h" /* - * There are 4 families : - * NV30 is 0x10de:0x030* (not working, no dump for that one) - * + * There are 3 families : + * NV30 is 0x10de:0x030* * NV31 is 0x10de:0x031* * * NV34 is 0x10de:0x032* @@ -25,11 +24,11 @@ */ -#define NV31_GRCTX_SIZE (22392) -#define NV34_GRCTX_SIZE (18140) -#define NV35_GRCTX_SIZE (22396) +#define NV30_31_GRCTX_SIZE (22392) +#define NV34_GRCTX_SIZE (18140) +#define NV35_36_GRCTX_SIZE (22396) -static void nv31_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) +static void nv30_31_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { struct drm_nouveau_private *dev_priv = dev->dev_private; int i; @@ -919,7 +918,8 @@ static void nv31_graph_context_init(struct drm_device *dev, struct nouveau_gpuob INSTANCE_WR(ctx, 0x3858/4, 0x40000000); INSTANCE_WR(ctx, 0x385c/4, 0x3f800000); INSTANCE_WR(ctx, 0x3864/4, 0xbf800000); - INSTANCE_WR(ctx, 0x386c/4, 0xbf800000);} + INSTANCE_WR(ctx, 0x386c/4, 0xbf800000); +} static void nv34_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { @@ -1814,7 +1814,7 @@ static void nv34_graph_context_init(struct drm_device *dev, struct nouveau_gpuob INSTANCE_WR(ctx, 0x2f00/4, 0xbf800000); } -static void nv35_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) +static void nv35_36_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { struct drm_nouveau_private *dev_priv = dev->dev_private; int i; @@ -2715,9 +2715,10 @@ int nv30_graph_create_context(struct nouveau_channel *chan) int ret; switch (dev_priv->chipset) { + case 0x30: case 0x31: - ctx_size = NV31_GRCTX_SIZE; - ctx_init = nv31_graph_context_init; + ctx_size = NV30_31_GRCTX_SIZE; + ctx_init = nv30_31_graph_context_init; break; case 0x34: ctx_size = NV34_GRCTX_SIZE; @@ -2725,12 +2726,12 @@ int nv30_graph_create_context(struct nouveau_channel *chan) break; case 0x35: case 0x36: - ctx_size = NV35_GRCTX_SIZE; - ctx_init = nv35_graph_context_init; + ctx_size = NV35_36_GRCTX_SIZE; + ctx_init = nv35_36_graph_context_init; break; default: ctx_size = 0; - ctx_init = nv35_graph_context_init; + ctx_init = nv35_36_graph_context_init; DRM_ERROR("Please contact the devs if you want your NV%x card to work\n",dev_priv->chipset); break; } -- cgit v1.2.3 From edf5a86a269690b0e42a5cee7d4ac3828b42ca3e Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Thu, 6 Sep 2007 02:46:45 +0200 Subject: nouveau: fix some nv04 graph switching. --- shared-core/nv04_graph.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c index 213696ca..f1117cd6 100644 --- a/shared-core/nv04_graph.c +++ b/shared-core/nv04_graph.c @@ -358,14 +358,15 @@ void nouveau_nv04_context_switch(struct drm_device *dev) chid = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); last = dev_priv->fifos[chid]; - DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",last->id, next->id); + DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",last->id, next->id); - NV_WRITE(NV03_PFIFO_CACHES, 0x0); +/* NV_WRITE(NV03_PFIFO_CACHES, 0x0); NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0); - NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0); + NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0);*/ NV_WRITE(NV04_PGRAPH_FIFO,0x0); - nv04_graph_save_context(last); + if (last) + nv04_graph_save_context(last); nouveau_wait_for_idle(dev); @@ -374,16 +375,16 @@ void nouveau_nv04_context_switch(struct drm_device *dev) nouveau_wait_for_idle(dev); - nv04_graph_load_context(last); + nv04_graph_load_context(next); NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100); NV_WRITE(NV04_PGRAPH_CTX_USER, next->id << 24); NV_WRITE(NV04_PGRAPH_FFINTFC_ST2, NV_READ(NV04_PGRAPH_FFINTFC_ST2)&0x000FFFFF); - NV_WRITE(NV04_PGRAPH_FIFO,0x0); +/* NV_WRITE(NV04_PGRAPH_FIFO,0x0); NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0); NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x1); - NV_WRITE(NV03_PFIFO_CACHES, 0x1); + NV_WRITE(NV03_PFIFO_CACHES, 0x1);*/ NV_WRITE(NV04_PGRAPH_FIFO,0x1); } -- cgit v1.2.3 From 06bb07259531d10df2c1979919af899e3812057b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 7 Sep 2007 20:07:13 +1000 Subject: nouveau: Use nv41 ctxprog/vals on nv42. --- shared-core/nv40_graph.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index 99c77cb9..3f3df515 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -1349,6 +1349,7 @@ nv40_graph_create_context(struct nouveau_channel *chan) ctx_init = nv40_graph_context_init; break; case 0x41: + case 0x42: ctx_size = NV41_GRCTX_SIZE; ctx_init = nv41_graph_context_init; break; @@ -1829,7 +1830,8 @@ nv40_graph_init(struct drm_device *dev) switch (dev_priv->chipset) { case 0x40: ctx_voodoo = nv40_ctx_voodoo; break; - case 0x41: ctx_voodoo = nv41_ctx_voodoo; break; + case 0x41: + case 0x42: ctx_voodoo = nv41_ctx_voodoo; break; case 0x43: ctx_voodoo = nv43_ctx_voodoo; break; case 0x44: ctx_voodoo = nv44_ctx_voodoo; break; case 0x46: ctx_voodoo = nv46_ctx_voodoo; break; -- cgit v1.2.3 From f19d80b0465d9ba93005d8499654e3256494c831 Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Sat, 8 Sep 2007 22:19:00 +0200 Subject: nouveau: Add Quadro NVS 140 pciid --- shared-core/drm_pciids.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'shared-core') diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index 39ddc1c5..74e7e75a 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -729,6 +729,7 @@ 0x10de 0x0421 NV_50 "GeForce 8500 GT" 0x10de 0x0422 NV_50 "GeForce 8400 GS" 0x10de 0x0423 NV_50 "GeForce 8300 GS" +0x10de 0x0429 NV_50 "Quadro NVS 140" 0x12d2 0x0020 NV_04 "TNT" 0x12d2 0x0028 NV_04 "TNT2" 0x12d2 0x0029 NV_04 "UTNT2" -- cgit v1.2.3 From b2ee72f4400999b2cf783256547fe8c7bfa698f5 Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Sun, 9 Sep 2007 12:13:00 +0200 Subject: nouveau : nv10 pipe ctx switch load/save. This fix some issues with more than one 3D fifo, but there still some "corruption" sometimes --- shared-core/nv10_graph.c | 333 ++++++++++++++++++++++++++++++----------------- 1 file changed, 215 insertions(+), 118 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index e470ff06..f90ba05b 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -27,13 +27,68 @@ #include "nouveau_drm.h" #include "nouveau_drv.h" +#define NV10_FIFO_NUMBER 32 + +struct pipe_state { + uint32_t pipe_0x0000[0x040/4]; + uint32_t pipe_0x0040[0x010/4]; + uint32_t pipe_0x0200[0x0c0/4]; + uint32_t pipe_0x4400[0x080/4]; + uint32_t pipe_0x6400[0x3b0/4]; + uint32_t pipe_0x6800[0x2f0/4]; + uint32_t pipe_0x6c00[0x030/4]; + uint32_t pipe_0x7000[0x130/4]; + uint32_t pipe_0x7400[0x0c0/4]; + uint32_t pipe_0x7800[0x0c0/4]; +}; + +/* TODO dynamic allocation ??? */ +static struct pipe_state pipe_state[NV10_FIFO_NUMBER]; + +static void nv10_graph_save_pipe(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct pipe_state *fifo_pipe_state = pipe_state + chan->id; + int i; +#define PIPE_SAVE(addr) \ + do { \ + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, addr); \ + for (i=0; i < sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]); i++) \ + fifo_pipe_state->pipe_##addr[i] = NV_READ(NV10_PGRAPH_PIPE_DATA); \ + } while (0) + + PIPE_SAVE(0x4400); + PIPE_SAVE(0x0200); + PIPE_SAVE(0x6400); + PIPE_SAVE(0x6800); + PIPE_SAVE(0x6c00); + PIPE_SAVE(0x7000); + PIPE_SAVE(0x7400); + PIPE_SAVE(0x7800); + PIPE_SAVE(0x0040); + PIPE_SAVE(0x0000); + +#undef PIPE_SAVE +} -static void nv10_praph_pipe(struct drm_device *dev) { +static void nv10_graph_load_pipe(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; + struct pipe_state *fifo_pipe_state = pipe_state + chan->id; int i; + uint32_t xfmode0, xfmode1; +#define PIPE_RESTORE(addr) \ + do { \ + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, addr); \ + for (i=0; i < sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]); i++) \ + NV_WRITE(NV10_PGRAPH_PIPE_DATA, fifo_pipe_state->pipe_##addr[i]); \ + } while (0) + nouveau_wait_for_idle(dev); /* XXX check haiku comments */ + xfmode0 = NV_READ(NV10_PGRAPH_XFMODE0); + xfmode1 = NV_READ(NV10_PGRAPH_XFMODE1); NV_WRITE(NV10_PGRAPH_XFMODE0, 0x10000000); NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); @@ -43,7 +98,6 @@ static void nv10_praph_pipe(struct drm_device *dev) { NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); - for (i = 0; i < 3; i++) NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); @@ -54,131 +108,176 @@ static void nv10_praph_pipe(struct drm_device *dev) { NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000008); - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000200); - for (i = 0; i < 48; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + PIPE_RESTORE(0x0200); nouveau_wait_for_idle(dev); - NV_WRITE(NV10_PGRAPH_XFMODE0, 0x00000000); - NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006400); - for (i = 0; i < 211; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + /* restore XFMODE */ + NV_WRITE(NV10_PGRAPH_XFMODE0, xfmode0); + NV_WRITE(NV10_PGRAPH_XFMODE1, xfmode1); + PIPE_RESTORE(0x6400); + PIPE_RESTORE(0x6800); + PIPE_RESTORE(0x6c00); + PIPE_RESTORE(0x7000); + PIPE_RESTORE(0x7400); + PIPE_RESTORE(0x7800); + PIPE_RESTORE(0x4400); + PIPE_RESTORE(0x0000); + PIPE_RESTORE(0x0040); + nouveau_wait_for_idle(dev); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); - - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006800); +#undef PIPE_RESTORE +} + +static void nv10_graph_create_pipe(struct nouveau_channel *chan) { + struct pipe_state *fifo_pipe_state = pipe_state + chan->id; + uint32_t *fifo_pipe_state_addr; + int i; +#define PIPE_INIT(addr) \ + do { \ + fifo_pipe_state_addr = fifo_pipe_state->pipe_##addr; \ + } while (0) +#define PIPE_INIT_END(addr) \ + do { \ + if (fifo_pipe_state_addr != \ + sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]) + fifo_pipe_state->pipe_##addr) \ + DRM_ERROR("incomplete pipe init for 0x%x : %p/%p\n", addr, fifo_pipe_state_addr, \ + sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]) + fifo_pipe_state->pipe_##addr); \ + } while (0) +#define NV_WRITE_PIPE_INIT(value) *(fifo_pipe_state_addr++) = value + + PIPE_INIT(0x0200); + for (i = 0; i < 48; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x0200); + + PIPE_INIT(0x6400); + for (i = 0; i < 211; i++) + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x40000000); + NV_WRITE_PIPE_INIT(0x40000000); + NV_WRITE_PIPE_INIT(0x40000000); + NV_WRITE_PIPE_INIT(0x40000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f000000); + NV_WRITE_PIPE_INIT(0x3f000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x3f800000); + PIPE_INIT_END(0x6400); + + PIPE_INIT(0x6800); for (i = 0; i < 162; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f800000); for (i = 0; i < 25; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006c00); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0xbf800000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x6800); + + PIPE_INIT(0x6c00); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0xbf800000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x6c00); + + PIPE_INIT(0x7000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); for (i = 0; i < 35; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x7000); - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007400); + PIPE_INIT(0x7400); for (i = 0; i < 48; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x7400); - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007800); + PIPE_INIT(0x7800); for (i = 0; i < 48; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x7800); - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00004400); + PIPE_INIT(0x4400); for (i = 0; i < 32; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x4400); - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000000); + PIPE_INIT(0x0000); for (i = 0; i < 16; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x0000); - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); + PIPE_INIT(0x0040); for (i = 0; i < 4; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x0040); - nouveau_wait_for_idle(dev); +#undef PIPE_INIT +#undef PIPE_INIT_END +#undef NV_WRITE_PIPE_INIT } static int nv10_graph_ctx_regs [] = { @@ -555,6 +654,8 @@ int nv10_graph_load_context(struct nouveau_channel *chan) } NV_WRITE(NV10_PGRAPH_CTX_USER, chan->id << 24); + nv10_graph_load_pipe(chan); + return 0; } @@ -571,6 +672,8 @@ int nv10_graph_save_context(struct nouveau_channel *chan) chan->pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); } + nv10_graph_save_pipe(chan); + return 0; } @@ -609,12 +712,13 @@ void nouveau_nv10_context_switch(struct drm_device *dev) DRM_DEBUG("WARNING: Invalid last channel, switch to %x\n", next->id); } else { - DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n", + DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n", last->id, next->id); } NV_WRITE(NV04_PGRAPH_FIFO,0x0); if (last) { + nouveau_wait_for_idle(dev); nv10_graph_save_context(last); } @@ -693,14 +797,7 @@ int nv10_graph_create_context(struct nouveau_channel *chan) { NV_WRITE_CTX(0x00400ed0, 0x00000080); } - /* for the first channel init the regs */ - if (dev_priv->fifo_alloc_count == 0) - nv10_graph_load_context(chan); - - - //XXX should be saved/restored for each fifo - //we supposed here we have X fifo and only one 3D fifo. - nv10_praph_pipe(dev); + nv10_graph_create_pipe(chan); return 0; } -- cgit v1.2.3 From 00bb534a546a4ca4bb6e167f5b387fa8156f4ca7 Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Sun, 9 Sep 2007 15:49:33 +0200 Subject: nouveau : nv10 fix NV10_PGRAPH_CTX_USER save/load --- shared-core/nv10_graph.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index f90ba05b..456bc5d3 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -652,7 +652,6 @@ int nv10_graph_load_context(struct nouveau_channel *chan) for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) NV_WRITE(nv17_graph_ctx_regs[j], chan->pgraph_ctx[i]); } - NV_WRITE(NV10_PGRAPH_CTX_USER, chan->id << 24); nv10_graph_load_pipe(chan); @@ -725,14 +724,12 @@ void nouveau_nv10_context_switch(struct drm_device *dev) nouveau_wait_for_idle(dev); NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000000); - NV_WRITE(NV10_PGRAPH_CTX_USER, (NV_READ(NV10_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24)); nouveau_wait_for_idle(dev); nv10_graph_load_context(next); NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100); - //NV_WRITE(NV10_PGRAPH_CTX_USER, next->id << 24); NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); NV_WRITE(NV04_PGRAPH_FIFO,0x1); } @@ -796,6 +793,7 @@ int nv10_graph_create_context(struct nouveau_channel *chan) { NV_WRITE_CTX(0x00400ec0, 0x00000080); NV_WRITE_CTX(0x00400ed0, 0x00000080); } + NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->id << 24); nv10_graph_create_pipe(chan); return 0; -- cgit v1.2.3 From 0bd8752a0cb8afb7f29a5f659c3459aab42d9955 Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Mon, 10 Sep 2007 18:52:17 +0200 Subject: nouveau: nv10: add combiner registers --- shared-core/nouveau_reg.h | 12 ++++++++++++ shared-core/nv10_graph.c | 24 ++++++++++++------------ 2 files changed, 24 insertions(+), 12 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index a1895c34..21133d98 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -319,6 +319,18 @@ #define NV47_PGRAPH_TSTATUS0(i) 0x00400D0C #define NV04_PGRAPH_V_RAM 0x00400D40 #define NV04_PGRAPH_W_RAM 0x00400D80 +#define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40 +#define NV10_PGRAPH_COMBINER1_IN_ALPHA 0x00400E44 +#define NV10_PGRAPH_COMBINER0_IN_RGB 0x00400E48 +#define NV10_PGRAPH_COMBINER1_IN_RGB 0x00400E4C +#define NV10_PGRAPH_COMBINER_COLOR0 0x00400E50 +#define NV10_PGRAPH_COMBINER_COLOR1 0x00400E54 +#define NV10_PGRAPH_COMBINER0_OUT_ALPHA 0x00400E58 +#define NV10_PGRAPH_COMBINER1_OUT_ALPHA 0x00400E5C +#define NV10_PGRAPH_COMBINER0_OUT_RGB 0x00400E60 +#define NV10_PGRAPH_COMBINER1_OUT_RGB 0x00400E64 +#define NV10_PGRAPH_COMBINER_FINAL0 0x00400E68 +#define NV10_PGRAPH_COMBINER_FINAL1 0x00400E6C #define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00 #define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20 #define NV10_PGRAPH_XFMODE0 0x00400F40 diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 456bc5d3..1fd185a0 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -558,18 +558,18 @@ NV03_PGRAPH_CLIPX_0, NV03_PGRAPH_CLIPX_1, NV03_PGRAPH_CLIPY_0, NV03_PGRAPH_CLIPY_1, -0x00400e40, -0x00400e44, -0x00400e48, -0x00400e4c, -0x00400e50, -0x00400e54, -0x00400e58, -0x00400e5c, -0x00400e60, -0x00400e64, -0x00400e68, -0x00400e6c, +NV10_PGRAPH_COMBINER0_IN_ALPHA, +NV10_PGRAPH_COMBINER1_IN_ALPHA, +NV10_PGRAPH_COMBINER0_IN_RGB, +NV10_PGRAPH_COMBINER1_IN_RGB, +NV10_PGRAPH_COMBINER_COLOR0, +NV10_PGRAPH_COMBINER_COLOR1, +NV10_PGRAPH_COMBINER0_OUT_ALPHA, +NV10_PGRAPH_COMBINER1_OUT_ALPHA, +NV10_PGRAPH_COMBINER0_OUT_RGB, +NV10_PGRAPH_COMBINER1_OUT_RGB, +NV10_PGRAPH_COMBINER_FINAL0, +NV10_PGRAPH_COMBINER_FINAL1, 0x00400e00, 0x00400e04, 0x00400e08, -- cgit v1.2.3 From 3cb8acd5abcb410ab2982f55aec94b5a793a47d6 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Tue, 11 Sep 2007 03:48:46 -0700 Subject: Disambiguate planes & pipes for swap operations This mod makes the SAREA track plane to pipe mappings and corrects the name of the plane info variables (they were mislabeled as pipe info since until now all code assumed a direct mapping between planes and pipes). It also updates the flip ioctl argument to take a set of planes rather than pipes, since planes are flipped while pipes generate vblank events. --- shared-core/i915_dma.c | 46 +++++++++++++++++------------------ shared-core/i915_drm.h | 21 +++++++++------- shared-core/i915_drv.h | 5 ++-- shared-core/i915_irq.c | 66 ++++++++++++++++++++++++++------------------------ 4 files changed, 73 insertions(+), 65 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 9f18feee..daa03df8 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -572,11 +572,11 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev, return 0; } -static void i915_do_dispatch_flip(struct drm_device * dev, int pipe, int sync) +static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync) { drm_i915_private_t *dev_priv = dev->dev_private; u32 num_pages, current_page, next_page, dspbase; - int shift = 2 * pipe, x, y; + int shift = 2 * plane, x, y; RING_LOCALS; /* Calculate display base offset */ @@ -597,25 +597,25 @@ static void i915_do_dispatch_flip(struct drm_device * dev, int pipe, int sync) break; } - if (pipe == 0) { - x = dev_priv->sarea_priv->pipeA_x; - y = dev_priv->sarea_priv->pipeA_y; + if (plane == 0) { + x = dev_priv->sarea_priv->planeA_x; + y = dev_priv->sarea_priv->planeA_y; } else { - x = dev_priv->sarea_priv->pipeB_x; - y = dev_priv->sarea_priv->pipeB_y; + x = dev_priv->sarea_priv->planeB_x; + y = dev_priv->sarea_priv->planeB_y; } dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp; - DRM_DEBUG("pipe=%d current_page=%d dspbase=0x%x\n", pipe, current_page, + DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page, dspbase); BEGIN_LP_RING(4); OUT_RING(sync ? 0 : - (MI_WAIT_FOR_EVENT | (pipe ? MI_WAIT_FOR_PLANE_B_FLIP : + (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP : MI_WAIT_FOR_PLANE_A_FLIP))); OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) | - (pipe ? DISPLAY_PLANE_B : DISPLAY_PLANE_A)); + (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A)); OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp); OUT_RING(dspbase); ADVANCE_LP_RING(); @@ -624,19 +624,19 @@ static void i915_do_dispatch_flip(struct drm_device * dev, int pipe, int sync) dev_priv->sarea_priv->pf_current_page |= next_page << shift; } -void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync) +void i915_dispatch_flip(struct drm_device * dev, int planes, int sync) { drm_i915_private_t *dev_priv = dev->dev_private; int i; - DRM_DEBUG("%s: pipes=0x%x pfCurrentPage=%d\n", + DRM_DEBUG("%s: planes=0x%x pfCurrentPage=%d\n", __FUNCTION__, - pipes, dev_priv->sarea_priv->pf_current_page); + planes, dev_priv->sarea_priv->pf_current_page); i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH); for (i = 0; i < 2; i++) - if (pipes & (1 << i)) + if (planes & (1 << i)) i915_do_dispatch_flip(dev, i, sync); i915_emit_breadcrumb(dev); @@ -728,21 +728,21 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data, static int i915_do_cleanup_pageflip(struct drm_device * dev) { drm_i915_private_t *dev_priv = dev->dev_private; - int i, pipes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2; + int i, planes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2; DRM_DEBUG("%s\n", __FUNCTION__); - for (i = 0, pipes = 0; i < 2; i++) + for (i = 0, planes = 0; i < 2; i++) if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) { dev_priv->sarea_priv->pf_current_page = (dev_priv->sarea_priv->pf_current_page & ~(0x3 << (2 * i))) | (num_pages - 1) << (2 * i); - pipes |= 1 << i; + planes |= 1 << i; } - if (pipes) - i915_dispatch_flip(dev, pipes, 0); + if (planes) + i915_dispatch_flip(dev, planes, 0); return 0; } @@ -755,13 +755,13 @@ static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *f LOCK_TEST_WITH_RETURN(dev, file_priv); - if (param->pipes & ~0x3) { - DRM_ERROR("Invalid pipes 0x%x, only <= 0x3 is valid\n", - param->pipes); + if (param->planes & ~0x3) { + DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n", + param->planes); return -EINVAL; } - i915_dispatch_flip(dev, param->pipes, 0); + i915_dispatch_flip(dev, param->planes, 0); return 0; } diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h index 3a90df6e..575b182a 100644 --- a/shared-core/i915_drm.h +++ b/shared-core/i915_drm.h @@ -105,14 +105,17 @@ typedef struct _drm_i915_sarea { unsigned int rotated_tiled; unsigned int rotated2_tiled; - int pipeA_x; - int pipeA_y; - int pipeA_w; - int pipeA_h; - int pipeB_x; - int pipeB_y; - int pipeB_w; - int pipeB_h; + int planeA_x; + int planeA_y; + int planeA_w; + int planeA_h; + int planeB_x; + int planeB_y; + int planeB_w; + int planeB_h; + + int planeA_pipe; + int planeB_pipe; /* Triple buffering */ drm_handle_t third_handle; @@ -182,7 +185,7 @@ typedef struct _drm_i915_sarea { /* Asynchronous page flipping: */ typedef struct drm_i915_flip { - int pipes; + int planes; } drm_i915_flip_t; /* Allow drivers to submit batchbuffers directly to hardware, relying diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index aff03bee..c5f51897 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -55,10 +55,11 @@ * - Support vertical blank on secondary display pipe * 1.8: New ioctl for ARB_Occlusion_Query * 1.9: Usable page flipping and triple buffering + * 1.10: Plane/pipe disentangling */ #define DRIVER_MAJOR 1 #if defined(I915_HAVE_FENCE) && defined(I915_HAVE_BUFFER) -#define DRIVER_MINOR 9 +#define DRIVER_MINOR 10 #else #define DRIVER_MINOR 6 #endif @@ -87,7 +88,7 @@ struct mem_block { typedef struct _drm_i915_vbl_swap { struct list_head head; drm_drawable_t drw_id; - unsigned int pipe; + unsigned int plane; unsigned int sequence; int flip; } drm_i915_vbl_swap_t; diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c index 1056b3e6..72c61876 100644 --- a/shared-core/i915_irq.c +++ b/shared-core/i915_irq.c @@ -44,28 +44,28 @@ */ static void i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw, - int pipe) + int plane) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; u16 x1, y1, x2, y2; - int pf_pipes = 1 << pipe; + int pf_planes = 1 << plane; DRM_SPINLOCK_ASSERT(&dev->drw_lock); - /* If the window is visible on the other pipe, we have to flip on that - * pipe as well. + /* If the window is visible on the other plane, we have to flip on that + * plane as well. */ - if (pipe == 1) { - x1 = sarea_priv->pipeA_x; - y1 = sarea_priv->pipeA_y; - x2 = x1 + sarea_priv->pipeA_w; - y2 = y1 + sarea_priv->pipeA_h; + if (plane == 1) { + x1 = sarea_priv->planeA_x; + y1 = sarea_priv->planeA_y; + x2 = x1 + sarea_priv->planeA_w; + y2 = y1 + sarea_priv->planeA_h; } else { - x1 = sarea_priv->pipeB_x; - y1 = sarea_priv->pipeB_y; - x2 = x1 + sarea_priv->pipeB_w; - y2 = y1 + sarea_priv->pipeB_h; + x1 = sarea_priv->planeB_x; + y1 = sarea_priv->planeB_y; + x2 = x1 + sarea_priv->planeB_w; + y2 = y1 + sarea_priv->planeB_h; } if (x2 > 0 && y2 > 0) { @@ -75,13 +75,13 @@ i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw, for (i = 0; i < num_rects; i++) if (!(rect[i].x1 >= x2 || rect[i].y1 >= y2 || rect[i].x2 <= x1 || rect[i].y2 <= y1)) { - pf_pipes = 0x3; + pf_planes = 0x3; break; } } - i915_dispatch_flip(dev, pf_pipes, 1); + i915_dispatch_flip(dev, pf_planes, 1); } /** @@ -124,8 +124,10 @@ static void i915_vblank_tasklet(struct drm_device *dev) list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) { drm_i915_vbl_swap_t *vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head); + int pipe = vbl_swap->plane ? sarea_priv->planeB_pipe : + sarea_priv->planeA_pipe; - if ((counter[vbl_swap->pipe] - vbl_swap->sequence) > (1<<23)) + if ((counter[pipe] - vbl_swap->sequence) > (1<<23)) continue; list_del(list); @@ -176,10 +178,10 @@ static void i915_vblank_tasklet(struct drm_device *dev) i915_kernel_lost_context(dev); upper[0] = upper[1] = 0; - slice[0] = max(sarea_priv->pipeA_h / nhits, 1); - slice[1] = max(sarea_priv->pipeB_h / nhits, 1); - lower[0] = sarea_priv->pipeA_y + slice[0]; - lower[1] = sarea_priv->pipeB_y + slice[0]; + slice[0] = max(sarea_priv->planeA_h / nhits, 1); + slice[1] = max(sarea_priv->planeB_h / nhits, 1); + lower[0] = sarea_priv->planeA_y + slice[0]; + lower[1] = sarea_priv->planeB_y + slice[0]; offsets[0] = sarea_priv->front_offset; offsets[1] = sarea_priv->back_offset; @@ -205,7 +207,7 @@ static void i915_vblank_tasklet(struct drm_device *dev) drm_i915_vbl_swap_t *swap_hit = list_entry(hit, drm_i915_vbl_swap_t, head); struct drm_clip_rect *rect; - int num_rects, pipe, front, back; + int num_rects, plane, front, back; unsigned short top, bottom; drw = drm_get_drawable_info(dev, swap_hit->drw_id); @@ -213,10 +215,10 @@ static void i915_vblank_tasklet(struct drm_device *dev) if (!drw) continue; - pipe = swap_hit->pipe; + plane = swap_hit->plane; if (swap_hit->flip) { - i915_dispatch_vsync_flip(dev, drw, pipe); + i915_dispatch_vsync_flip(dev, drw, plane); continue; } @@ -238,11 +240,11 @@ static void i915_vblank_tasklet(struct drm_device *dev) } rect = drw->rects; - top = upper[pipe]; - bottom = lower[pipe]; + top = upper[plane]; + bottom = lower[plane]; front = (dev_priv->sarea_priv->pf_current_page >> - (2 * pipe)) & 0x3; + (2 * plane)) & 0x3; back = (front + 1) % num_pages; for (num_rects = drw->num_rects; num_rects--; rect++) { @@ -560,9 +562,10 @@ int i915_vblank_swap(struct drm_device *dev, void *data, drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_vblank_swap_t *swap = data; drm_i915_vbl_swap_t *vbl_swap; - unsigned int pipe, seqtype, curseq; + unsigned int pipe, seqtype, curseq, plane; unsigned long irqflags; struct list_head *list; + drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __func__); @@ -581,7 +584,8 @@ int i915_vblank_swap(struct drm_device *dev, void *data, return -EINVAL; } - pipe = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0; + plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0; + pipe = plane ? sarea_priv->planeB_pipe : sarea_priv->planeA_pipe; seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE); @@ -624,7 +628,7 @@ int i915_vblank_swap(struct drm_device *dev, void *data, return -EINVAL; } - i915_dispatch_vsync_flip(dev, drw, pipe); + i915_dispatch_vsync_flip(dev, drw, plane); DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags); @@ -638,7 +642,7 @@ int i915_vblank_swap(struct drm_device *dev, void *data, vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head); if (vbl_swap->drw_id == swap->drawable && - vbl_swap->pipe == pipe && + vbl_swap->plane == plane && vbl_swap->sequence == swap->sequence) { vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP); DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags); @@ -664,7 +668,7 @@ int i915_vblank_swap(struct drm_device *dev, void *data, DRM_DEBUG("\n"); vbl_swap->drw_id = swap->drawable; - vbl_swap->pipe = pipe; + vbl_swap->plane = plane; vbl_swap->sequence = swap->sequence; vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP); -- cgit v1.2.3 From 852232fb803bef92b12136be2766ddee3e3613b2 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Wed, 12 Sep 2007 08:55:33 -0700 Subject: Remove plane->pipe mapping from SAREA private after all We can figure out which pipe a given plane is mapped to by looking at the display control registers instead of tracking it in a new SAREA private field. If this becomes a performance problem, we could move to an ioctl based solution by adding a new parameter for the DDX to set (defaulting to the old behavior if the param was never set of course). --- shared-core/i915_drm.h | 3 --- shared-core/i915_drv.h | 5 +++++ shared-core/i915_irq.c | 26 ++++++++++++++++++++++---- 3 files changed, 27 insertions(+), 7 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h index 575b182a..a57ffa73 100644 --- a/shared-core/i915_drm.h +++ b/shared-core/i915_drm.h @@ -114,9 +114,6 @@ typedef struct _drm_i915_sarea { int planeB_w; int planeB_h; - int planeA_pipe; - int planeB_pipe; - /* Triple buffering */ drm_handle_t third_handle; int third_offset; diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index c5f51897..899817ec 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -490,6 +490,11 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); #define DISPLAY_PLANE_A (0<<20) #define DISPLAY_PLANE_B (1<<20) +/* Display regs */ +#define DSPACNTR 0x70180 +#define DSPBCNTR 0x71180 +#define DISPPLANE_SEL_PIPE_MASK (1<<24) + /* Define the region of interest for the binner: */ #define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4) diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c index 72c61876..804e3fb1 100644 --- a/shared-core/i915_irq.c +++ b/shared-core/i915_irq.c @@ -37,6 +37,26 @@ #define MAX_NOPID ((u32)~0) +/** + * i915_get_pipe - return the the pipe associated with a given plane + * @dev: DRM device + * @plane: plane to look for + * + * We need to get the pipe associated with a given plane to correctly perform + * vblank driven swapping, and they may not always be equal. So look up the + * pipe associated with @plane here. + */ +static int +i915_get_pipe(struct drm_device *dev, int plane) +{ + drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; + u32 dspcntr; + + dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR); + + return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0; +} + /** * Emit a synchronous flip. * @@ -124,8 +144,7 @@ static void i915_vblank_tasklet(struct drm_device *dev) list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) { drm_i915_vbl_swap_t *vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head); - int pipe = vbl_swap->plane ? sarea_priv->planeB_pipe : - sarea_priv->planeA_pipe; + int pipe = i915_get_pipe(dev, vbl_swap->plane); if ((counter[pipe] - vbl_swap->sequence) > (1<<23)) continue; @@ -565,7 +584,6 @@ int i915_vblank_swap(struct drm_device *dev, void *data, unsigned int pipe, seqtype, curseq, plane; unsigned long irqflags; struct list_head *list; - drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; if (!dev_priv) { DRM_ERROR("%s called with no initialization\n", __func__); @@ -585,7 +603,7 @@ int i915_vblank_swap(struct drm_device *dev, void *data, } plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0; - pipe = plane ? sarea_priv->planeB_pipe : sarea_priv->planeA_pipe; + pipe = i915_get_pipe(dev, plane); seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE); -- cgit v1.2.3 From a3881ad2fef99aaf0a863609a847020ea822798c Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 18 Sep 2007 11:03:49 -0700 Subject: Add ioc32 compat layer for XGI DRM. --- shared-core/xgi_drm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/xgi_drm.h b/shared-core/xgi_drm.h index d8715df5..de0fb532 100644 --- a/shared-core/xgi_drm.h +++ b/shared-core/xgi_drm.h @@ -90,7 +90,7 @@ struct xgi_mem_alloc { * * See also DRM_XGI_FREE ioctl. */ - unsigned long index; + __u32 index; }; enum xgi_batch_type { -- cgit v1.2.3 From 78d111fa967d18e7f9f9b2acd26aff20b884eb6c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Tue, 18 Sep 2007 20:55:43 +0100 Subject: i915: Fix scheduled buffer swaps. One instance of unlocking a spinlock was converted incorrectly when this code was fixed to build on BSD. --- shared-core/i915_irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c index 804e3fb1..ea84c708 100644 --- a/shared-core/i915_irq.c +++ b/shared-core/i915_irq.c @@ -188,7 +188,7 @@ static void i915_vblank_tasklet(struct drm_device *dev) DRM_SPINLOCK(&dev_priv->swaps_lock); } - DRM_SPINUNLOCK(&dev->drw_lock); + DRM_SPINUNLOCK(&dev_priv->swaps_lock); if (nhits == 0) { return; -- cgit v1.2.3 From e349b58b4a6ebfe299720cb921039a600c145e65 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Tue, 18 Sep 2007 21:03:22 +0100 Subject: i915: Reinstate check that drawable has valid information in i915_vblank_swap. --- shared-core/i915_irq.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'shared-core') diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c index ea84c708..7baa23c0 100644 --- a/shared-core/i915_irq.c +++ b/shared-core/i915_irq.c @@ -612,6 +612,21 @@ int i915_vblank_swap(struct drm_device *dev, void *data, return -EINVAL; } + DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags); + + /* It makes no sense to schedule a swap for a drawable that doesn't have + * valid information at this point. E.g. this could mean that the X + * server is too old to push drawable information to the DRM, in which + * case all such swaps would become ineffective. + */ + if (!drm_get_drawable_info(dev, swap->drawable)) { + DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags); + DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable); + return -EINVAL; + } + + DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags); + curseq = atomic_read(pipe ? &dev->vbl_received2 : &dev->vbl_received); if (seqtype == _DRM_VBLANK_RELATIVE) -- cgit v1.2.3 From 74c6f2f47a9977fef8fcc7c698862d5bd2f54336 Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Fri, 21 Sep 2007 22:04:45 +0200 Subject: nouveau: add some checks to the nv04 graph switching code. --- shared-core/nv04_graph.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c index f1117cd6..2cf052cf 100644 --- a/shared-core/nv04_graph.c +++ b/shared-core/nv04_graph.c @@ -352,13 +352,38 @@ void nouveau_nv04_context_switch(struct drm_device *dev) struct nouveau_channel *next, *last; int chid; + if (!dev) { + DRM_DEBUG("Invalid drm_device\n"); + return; + } + dev_priv = dev->dev_private; + if (!dev_priv) { + DRM_DEBUG("Invalid drm_nouveau_private\n"); + return; + } + if (!dev_priv->fifos) { + DRM_DEBUG("Invalid drm_nouveau_private->fifos\n"); + return; + } + chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); next = dev_priv->fifos[chid]; + if (!next) { + DRM_DEBUG("Invalid next channel\n"); + return; + } + chid = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); last = dev_priv->fifos[chid]; - DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",last->id, next->id); + if (!last) { + DRM_DEBUG("WARNING: Invalid last channel, switch to %x\n", + next->id); + } else { + DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n", + last->id, next->id); + } /* NV_WRITE(NV03_PFIFO_CACHES, 0x0); NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0); -- cgit v1.2.3 From dc60c452e6ac72ebc4e5c73153d4d9d8c9edfae5 Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Fri, 21 Sep 2007 22:27:53 +0200 Subject: nouveau: fix notifiers on PPC. --- shared-core/nouveau_notifier.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index 71b8cbe1..fbd4b56f 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -37,9 +37,12 @@ nouveau_notifier_init_channel(struct nouveau_channel *chan) int flags, ret; /*TODO: PCI notifier blocks */ +#if defined(__powerpc__) if (dev_priv->agp_heap) flags = NOUVEAU_MEM_AGP; - else if (dev_priv->pci_heap) + else +#endif + if (dev_priv->pci_heap) flags = NOUVEAU_MEM_PCI; else flags = NOUVEAU_MEM_FB; -- cgit v1.2.3 From 7587e9682c1b70930c015915d588b42ccd00c7c4 Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Fri, 21 Sep 2007 22:42:39 +0200 Subject: nouveau: fix ppc and get it right this time. --- shared-core/nouveau_notifier.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index fbd4b56f..d3b79683 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -37,7 +37,7 @@ nouveau_notifier_init_channel(struct nouveau_channel *chan) int flags, ret; /*TODO: PCI notifier blocks */ -#if defined(__powerpc__) +#ifndef __powerpc__ if (dev_priv->agp_heap) flags = NOUVEAU_MEM_AGP; else -- cgit v1.2.3 From e7bfeb3031374653f7e55d67cc1b5c823849359f Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 21 Sep 2007 16:14:22 -0700 Subject: Add some more verbosity to drm_bo_set_pin_req comments. --- shared-core/drm.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index 28275169..30c7a1a3 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -792,7 +792,9 @@ struct drm_bo_set_pin_req { unsigned int handle; /** * - 0: Unpin the given buffer object. - * - 1: Pin the given buffer object. + * - 1: Pin the given buffer object, requiring that its offset and + * memory area stay constant until unpin. The intended use is for + * scanout buffers. */ unsigned int pin; }; -- cgit v1.2.3 From da63f4ba0f15c3ae614eba92c8219670c674727e Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Sat, 22 Sep 2007 13:34:33 +0200 Subject: Add fence error member. Modify the TTM backend bind arguments. Export a number of functions needed for driver-specific super-ioctls. Add a function to map buffer objects from the kernel, regardless of where they're currently placed. A number of error fixes. --- shared-core/drm.h | 3 ++- shared-core/i915_drv.h | 3 ++- shared-core/via_drv.h | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index 30c7a1a3..21386a57 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -639,6 +639,7 @@ struct drm_set_version { #define DRM_FENCE_FLAG_SHAREABLE 0x00000002 #define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004 #define DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS 0x00000008 +#define DRM_FENCE_FLAG_NO_USER 0x00000010 /* Reserved for driver use */ #define DRM_FENCE_MASK_DRIVER 0xFF000000 @@ -651,7 +652,7 @@ struct drm_fence_arg { unsigned int type; unsigned int flags; unsigned int signaled; - unsigned int pad64; + unsigned int error; uint64_t expand_pad[3]; /*Future expansion */ }; diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 899817ec..3b26040f 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -214,7 +214,8 @@ extern int i915_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t f #ifdef I915_HAVE_BUFFER /* i915_buffer.c */ extern struct drm_ttm_backend *i915_create_ttm_backend_entry(struct drm_device *dev); -extern int i915_fence_types(struct drm_buffer_object *bo, uint32_t *type); +extern int i915_fence_types(struct drm_buffer_object *bo, uint32_t *fclass, + uint32_t *type); extern int i915_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags); extern int i915_init_mem_type(struct drm_device *dev, uint32_t type, struct drm_mem_type_manager *man); diff --git a/shared-core/via_drv.h b/shared-core/via_drv.h index 15e65950..0b474844 100644 --- a/shared-core/via_drv.h +++ b/shared-core/via_drv.h @@ -206,7 +206,8 @@ extern int via_fence_has_irq(struct drm_device * dev, uint32_t class, #ifdef VIA_HAVE_BUFFER extern struct drm_ttm_backend *via_create_ttm_backend_entry(struct drm_device *dev); -extern int via_fence_types(struct drm_buffer_object *bo, uint32_t *type); +extern int via_fence_types(struct drm_buffer_object *bo, uint32_t *fclass, + uint32_t *type); extern int via_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags); extern int via_init_mem_type(struct drm_device *dev, uint32_t type, struct drm_mem_type_manager *man); -- cgit v1.2.3 From 03c47f1420bf17a1e0f2b86be500656ae5a4c95b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 25 Sep 2007 16:16:14 +1000 Subject: drm: use fence_class as name instead of class --- shared-core/drm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index 30c7a1a3..b4754ead 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -647,11 +647,11 @@ struct drm_set_version { struct drm_fence_arg { unsigned int handle; - unsigned int class; + unsigned int fence_class; unsigned int type; unsigned int flags; unsigned int signaled; - unsigned int pad64; + unsigned int sequence; uint64_t expand_pad[3]; /*Future expansion */ }; -- cgit v1.2.3 From 0bb2395a8be0c33cc687dfd6aae7df81a82ed8e5 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Fri, 28 Sep 2007 10:10:08 -0700 Subject: Revert drm_i915_flip_t braindamage I should not have renamed this field. I should not have renamed this field. I should not have renamed this field. On the plus side, it was at least binary compatible. --- shared-core/i915_dma.c | 7 ++++--- shared-core/i915_drm.h | 8 +++++++- 2 files changed, 11 insertions(+), 4 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index daa03df8..3a9ecab2 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -755,13 +755,14 @@ static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *f LOCK_TEST_WITH_RETURN(dev, file_priv); - if (param->planes & ~0x3) { + /* This is really planes */ + if (param->pipes & ~0x3) { DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n", - param->planes); + param->pipes); return -EINVAL; } - i915_dispatch_flip(dev, param->planes, 0); + i915_dispatch_flip(dev, param->pipes, 0); return 0; } diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h index a57ffa73..9976804e 100644 --- a/shared-core/i915_drm.h +++ b/shared-core/i915_drm.h @@ -182,7 +182,13 @@ typedef struct _drm_i915_sarea { /* Asynchronous page flipping: */ typedef struct drm_i915_flip { - int planes; + /* + * This is really talking about planes, and we could rename it + * except for the fact that some of the duplicated i915_drm.h files + * out there check for HAVE_I915_FLIP and so might pick up this + * version. + */ + int pipes; } drm_i915_flip_t; /* Allow drivers to submit batchbuffers directly to hardware, relying -- cgit v1.2.3 From 72134e939eda578bc53746bf43f7096cbeaf9b7b Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Fri, 28 Sep 2007 21:28:47 +0200 Subject: nouveau : clean chan->pgraph_ctx stuff. We now do a static init of the array. This avoid hardcoding pgraph_ctx size and potential buffer overflow. --- shared-core/nv10_graph.c | 543 ++++++++++++++++++++++++----------------------- 1 file changed, 282 insertions(+), 261 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 1fd185a0..311e0e91 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -42,244 +42,6 @@ struct pipe_state { uint32_t pipe_0x7800[0x0c0/4]; }; -/* TODO dynamic allocation ??? */ -static struct pipe_state pipe_state[NV10_FIFO_NUMBER]; - -static void nv10_graph_save_pipe(struct nouveau_channel *chan) { - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct pipe_state *fifo_pipe_state = pipe_state + chan->id; - int i; -#define PIPE_SAVE(addr) \ - do { \ - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, addr); \ - for (i=0; i < sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]); i++) \ - fifo_pipe_state->pipe_##addr[i] = NV_READ(NV10_PGRAPH_PIPE_DATA); \ - } while (0) - - PIPE_SAVE(0x4400); - PIPE_SAVE(0x0200); - PIPE_SAVE(0x6400); - PIPE_SAVE(0x6800); - PIPE_SAVE(0x6c00); - PIPE_SAVE(0x7000); - PIPE_SAVE(0x7400); - PIPE_SAVE(0x7800); - PIPE_SAVE(0x0040); - PIPE_SAVE(0x0000); - -#undef PIPE_SAVE -} - -static void nv10_graph_load_pipe(struct nouveau_channel *chan) { - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct pipe_state *fifo_pipe_state = pipe_state + chan->id; - int i; - uint32_t xfmode0, xfmode1; -#define PIPE_RESTORE(addr) \ - do { \ - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, addr); \ - for (i=0; i < sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]); i++) \ - NV_WRITE(NV10_PGRAPH_PIPE_DATA, fifo_pipe_state->pipe_##addr[i]); \ - } while (0) - - - nouveau_wait_for_idle(dev); - /* XXX check haiku comments */ - xfmode0 = NV_READ(NV10_PGRAPH_XFMODE0); - xfmode1 = NV_READ(NV10_PGRAPH_XFMODE1); - NV_WRITE(NV10_PGRAPH_XFMODE0, 0x10000000); - NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000); - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); - for (i = 0; i < 4; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); - for (i = 0; i < 4; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); - for (i = 0; i < 3; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); - - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); - for (i = 0; i < 3; i++) - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - - NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); - NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000008); - - - PIPE_RESTORE(0x0200); - nouveau_wait_for_idle(dev); - - /* restore XFMODE */ - NV_WRITE(NV10_PGRAPH_XFMODE0, xfmode0); - NV_WRITE(NV10_PGRAPH_XFMODE1, xfmode1); - PIPE_RESTORE(0x6400); - PIPE_RESTORE(0x6800); - PIPE_RESTORE(0x6c00); - PIPE_RESTORE(0x7000); - PIPE_RESTORE(0x7400); - PIPE_RESTORE(0x7800); - PIPE_RESTORE(0x4400); - PIPE_RESTORE(0x0000); - PIPE_RESTORE(0x0040); - nouveau_wait_for_idle(dev); - -#undef PIPE_RESTORE -} - -static void nv10_graph_create_pipe(struct nouveau_channel *chan) { - struct pipe_state *fifo_pipe_state = pipe_state + chan->id; - uint32_t *fifo_pipe_state_addr; - int i; -#define PIPE_INIT(addr) \ - do { \ - fifo_pipe_state_addr = fifo_pipe_state->pipe_##addr; \ - } while (0) -#define PIPE_INIT_END(addr) \ - do { \ - if (fifo_pipe_state_addr != \ - sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]) + fifo_pipe_state->pipe_##addr) \ - DRM_ERROR("incomplete pipe init for 0x%x : %p/%p\n", addr, fifo_pipe_state_addr, \ - sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]) + fifo_pipe_state->pipe_##addr); \ - } while (0) -#define NV_WRITE_PIPE_INIT(value) *(fifo_pipe_state_addr++) = value - - PIPE_INIT(0x0200); - for (i = 0; i < 48; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x0200); - - PIPE_INIT(0x6400); - for (i = 0; i < 211; i++) - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x40000000); - NV_WRITE_PIPE_INIT(0x40000000); - NV_WRITE_PIPE_INIT(0x40000000); - NV_WRITE_PIPE_INIT(0x40000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f000000); - NV_WRITE_PIPE_INIT(0x3f000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x3f800000); - NV_WRITE_PIPE_INIT(0x3f800000); - PIPE_INIT_END(0x6400); - - PIPE_INIT(0x6800); - for (i = 0; i < 162; i++) - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x3f800000); - for (i = 0; i < 25; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x6800); - - PIPE_INIT(0x6c00); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0xbf800000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x6c00); - - PIPE_INIT(0x7000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x00000000); - NV_WRITE_PIPE_INIT(0x7149f2ca); - for (i = 0; i < 35; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x7000); - - PIPE_INIT(0x7400); - for (i = 0; i < 48; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x7400); - - PIPE_INIT(0x7800); - for (i = 0; i < 48; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x7800); - - PIPE_INIT(0x4400); - for (i = 0; i < 32; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x4400); - - PIPE_INIT(0x0000); - for (i = 0; i < 16; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x0000); - - PIPE_INIT(0x0040); - for (i = 0; i < 4; i++) - NV_WRITE_PIPE_INIT(0x00000000); - PIPE_INIT_END(0x0040); - -#undef PIPE_INIT -#undef PIPE_INIT_END -#undef NV_WRITE_PIPE_INIT -} - static int nv10_graph_ctx_regs [] = { NV10_PGRAPH_CTX_SWITCH1, NV10_PGRAPH_CTX_SWITCH2, @@ -623,20 +385,270 @@ NV10_PGRAPH_DEBUG_4, 0x00400a04, }; +struct graph_state { + int nv10[sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0])]; + int nv17[sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0])]; +}; + +/* TODO dynamic allocation ??? */ +static struct pipe_state pipe_state[NV10_FIFO_NUMBER]; +static struct graph_state graph_state[NV10_FIFO_NUMBER]; + + +static void nv10_graph_save_pipe(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct pipe_state *fifo_pipe_state = pipe_state + chan->id; + int i; +#define PIPE_SAVE(addr) \ + do { \ + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, addr); \ + for (i=0; i < sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]); i++) \ + fifo_pipe_state->pipe_##addr[i] = NV_READ(NV10_PGRAPH_PIPE_DATA); \ + } while (0) + + PIPE_SAVE(0x4400); + PIPE_SAVE(0x0200); + PIPE_SAVE(0x6400); + PIPE_SAVE(0x6800); + PIPE_SAVE(0x6c00); + PIPE_SAVE(0x7000); + PIPE_SAVE(0x7400); + PIPE_SAVE(0x7800); + PIPE_SAVE(0x0040); + PIPE_SAVE(0x0000); + +#undef PIPE_SAVE +} + +static void nv10_graph_load_pipe(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct pipe_state *fifo_pipe_state = pipe_state + chan->id; + int i; + uint32_t xfmode0, xfmode1; +#define PIPE_RESTORE(addr) \ + do { \ + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, addr); \ + for (i=0; i < sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]); i++) \ + NV_WRITE(NV10_PGRAPH_PIPE_DATA, fifo_pipe_state->pipe_##addr[i]); \ + } while (0) + + + nouveau_wait_for_idle(dev); + /* XXX check haiku comments */ + xfmode0 = NV_READ(NV10_PGRAPH_XFMODE0); + xfmode1 = NV_READ(NV10_PGRAPH_XFMODE1); + NV_WRITE(NV10_PGRAPH_XFMODE0, 0x10000000); + NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); + for (i = 0; i < 4; i++) + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + for (i = 0; i < 4; i++) + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); + for (i = 0; i < 3; i++) + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); + for (i = 0; i < 3; i++) + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000008); + + + PIPE_RESTORE(0x0200); + nouveau_wait_for_idle(dev); + + /* restore XFMODE */ + NV_WRITE(NV10_PGRAPH_XFMODE0, xfmode0); + NV_WRITE(NV10_PGRAPH_XFMODE1, xfmode1); + PIPE_RESTORE(0x6400); + PIPE_RESTORE(0x6800); + PIPE_RESTORE(0x6c00); + PIPE_RESTORE(0x7000); + PIPE_RESTORE(0x7400); + PIPE_RESTORE(0x7800); + PIPE_RESTORE(0x4400); + PIPE_RESTORE(0x0000); + PIPE_RESTORE(0x0040); + nouveau_wait_for_idle(dev); + +#undef PIPE_RESTORE +} + +static void nv10_graph_create_pipe(struct nouveau_channel *chan) { + struct pipe_state *fifo_pipe_state = pipe_state + chan->id; + uint32_t *fifo_pipe_state_addr; + int i; +#define PIPE_INIT(addr) \ + do { \ + fifo_pipe_state_addr = fifo_pipe_state->pipe_##addr; \ + } while (0) +#define PIPE_INIT_END(addr) \ + do { \ + if (fifo_pipe_state_addr != \ + sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]) + fifo_pipe_state->pipe_##addr) \ + DRM_ERROR("incomplete pipe init for 0x%x : %p/%p\n", addr, fifo_pipe_state_addr, \ + sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]) + fifo_pipe_state->pipe_##addr); \ + } while (0) +#define NV_WRITE_PIPE_INIT(value) *(fifo_pipe_state_addr++) = value + + PIPE_INIT(0x0200); + for (i = 0; i < 48; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x0200); + + PIPE_INIT(0x6400); + for (i = 0; i < 211; i++) + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x40000000); + NV_WRITE_PIPE_INIT(0x40000000); + NV_WRITE_PIPE_INIT(0x40000000); + NV_WRITE_PIPE_INIT(0x40000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f000000); + NV_WRITE_PIPE_INIT(0x3f000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x3f800000); + NV_WRITE_PIPE_INIT(0x3f800000); + PIPE_INIT_END(0x6400); + + PIPE_INIT(0x6800); + for (i = 0; i < 162; i++) + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x3f800000); + for (i = 0; i < 25; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x6800); + + PIPE_INIT(0x6c00); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0xbf800000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x6c00); + + PIPE_INIT(0x7000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x00000000); + NV_WRITE_PIPE_INIT(0x7149f2ca); + for (i = 0; i < 35; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x7000); + + PIPE_INIT(0x7400); + for (i = 0; i < 48; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x7400); + + PIPE_INIT(0x7800); + for (i = 0; i < 48; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x7800); + + PIPE_INIT(0x4400); + for (i = 0; i < 32; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x4400); + + PIPE_INIT(0x0000); + for (i = 0; i < 16; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x0000); + + PIPE_INIT(0x0040); + for (i = 0; i < 4; i++) + NV_WRITE_PIPE_INIT(0x00000000); + PIPE_INIT_END(0x0040); + +#undef PIPE_INIT +#undef PIPE_INIT_END +#undef NV_WRITE_PIPE_INIT +} + static int nv10_graph_ctx_regs_find_offset(struct drm_device *dev, int reg) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i, j; + int i; for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) { if (nv10_graph_ctx_regs[i] == reg) return i; } - if (dev_priv->chipset>=0x17) { - for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) { - if (nv17_graph_ctx_regs[j] == reg) - return i; - } + DRM_ERROR("unknow offset nv10_ctx_regs %d\n", reg); + return -1; +} + +static int nv17_graph_ctx_regs_find_offset(struct drm_device *dev, int reg) +{ + int i; + for (i = 0; i < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++) { + if (nv17_graph_ctx_regs[i] == reg) + return i; } + DRM_ERROR("unknow offset nv17_ctx_regs %d\n", reg); return -1; } @@ -644,13 +656,14 @@ int nv10_graph_load_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - int i, j; + struct graph_state* pgraph_ctx = graph_state + chan->id; + int i; for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) - NV_WRITE(nv10_graph_ctx_regs[i], chan->pgraph_ctx[i]); + NV_WRITE(nv10_graph_ctx_regs[i], pgraph_ctx->nv10[i]); if (dev_priv->chipset>=0x17) { - for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) - NV_WRITE(nv17_graph_ctx_regs[j], chan->pgraph_ctx[i]); + for (i = 0; i < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++) + NV_WRITE(nv17_graph_ctx_regs[i], pgraph_ctx->nv17[i]); } nv10_graph_load_pipe(chan); @@ -662,13 +675,14 @@ int nv10_graph_save_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - int i, j; + struct graph_state* pgraph_ctx = graph_state + chan->id; + int i; for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) - chan->pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); + pgraph_ctx->nv10[i] = NV_READ(nv10_graph_ctx_regs[i]); if (dev_priv->chipset>=0x17) { - for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) - chan->pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); + for (i = 0; i < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++) + pgraph_ctx->nv17[i] = NV_READ(nv17_graph_ctx_regs[i]); } nv10_graph_save_pipe(chan); @@ -737,16 +751,23 @@ void nouveau_nv10_context_switch(struct drm_device *dev) #define NV_WRITE_CTX(reg, val) do { \ int offset = nv10_graph_ctx_regs_find_offset(dev, reg); \ if (offset > 0) \ - chan->pgraph_ctx[offset] = val; \ + pgraph_ctx->nv10[offset] = val; \ + } while (0) + +#define NV17_WRITE_CTX(reg, val) do { \ + int offset = nv17_graph_ctx_regs_find_offset(dev, reg); \ + if (offset > 0) \ + pgraph_ctx->nv17[offset] = val; \ } while (0) int nv10_graph_create_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; + struct graph_state* pgraph_ctx = graph_state + chan->id; DRM_DEBUG("nv10_graph_context_create %d\n", chan->id); - memset(chan->pgraph_ctx, 0, sizeof(chan->pgraph_ctx)); + memset(pgraph_ctx, 0, sizeof(*pgraph_ctx)); /* mmio trace suggest that should be done in ddx with methods/objects */ #if 0 @@ -786,12 +807,12 @@ int nv10_graph_create_context(struct nouveau_channel *chan) { NV_WRITE_CTX(0x00400e34, 0x00080008); if (dev_priv->chipset>=0x17) { /* is it really needed ??? */ - NV_WRITE_CTX(NV10_PGRAPH_DEBUG_4, NV_READ(NV10_PGRAPH_DEBUG_4)); - NV_WRITE_CTX(0x004006b0, NV_READ(0x004006b0)); - NV_WRITE_CTX(0x00400eac, 0x0fff0000); - NV_WRITE_CTX(0x00400eb0, 0x0fff0000); - NV_WRITE_CTX(0x00400ec0, 0x00000080); - NV_WRITE_CTX(0x00400ed0, 0x00000080); + NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4, NV_READ(NV10_PGRAPH_DEBUG_4)); + NV17_WRITE_CTX(0x004006b0, NV_READ(0x004006b0)); + NV17_WRITE_CTX(0x00400eac, 0x0fff0000); + NV17_WRITE_CTX(0x00400eb0, 0x0fff0000); + NV17_WRITE_CTX(0x00400ec0, 0x00000080); + NV17_WRITE_CTX(0x00400ed0, 0x00000080); } NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->id << 24); -- cgit v1.2.3 From f863d23e01bf0b851c2c7addedfaec77ef951a0c Mon Sep 17 00:00:00 2001 From: chaohong guo Date: Sat, 29 Sep 2007 18:06:47 +0200 Subject: radeon: Commit the ring after each partial texture upload blit. This makes sure each blit starts as early as possible, which may improve texture upload performance in some cases. --- shared-core/radeon_state.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c index ac7f6011..e3aadfb9 100644 --- a/shared-core/radeon_state.c +++ b/shared-core/radeon_state.c @@ -1861,6 +1861,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev, OUT_RING((image->width << 16) | height); RADEON_WAIT_UNTIL_2D_IDLE(); ADVANCE_RING(); + COMMIT_RING(); radeon_cp_discard_buffer(dev, buf); @@ -1878,6 +1879,8 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev, RADEON_FLUSH_CACHE(); RADEON_WAIT_UNTIL_2D_IDLE(); ADVANCE_RING(); + COMMIT_RING(); + return 0; } @@ -2401,7 +2404,6 @@ static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image); - COMMIT_RING(); return ret; } -- cgit v1.2.3 From 097db7a9b0cd0e53fb82dffa57c662f327c19670 Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Sat, 29 Sep 2007 23:05:44 +0200 Subject: nouveau : nv1x fix strange corruption that appears when running glxgears and nouveau demo --- shared-core/nv10_graph.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 311e0e91..c115ba7f 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -714,7 +714,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev) next = dev_priv->fifos[chid]; if (!next) { - DRM_DEBUG("Invalid next channel\n"); + DRM_ERROR("Invalid next channel\n"); return; } @@ -722,7 +722,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev) last = dev_priv->fifos[chid]; if (!last) { - DRM_DEBUG("WARNING: Invalid last channel, switch to %x\n", + DRM_INFO("WARNING: Invalid last channel, switch to %x\n", next->id); } else { DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n", @@ -827,6 +827,9 @@ void nv10_graph_destroy_context(struct nouveau_channel *chan) int chid; chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + /* This code seems to corrupt the 3D pipe, but blob seems to do similar things ???? + */ +#if 0 /* does this avoid a potential context switch while we are written graph * reg, or we should mask graph interrupt ??? */ @@ -838,7 +841,12 @@ void nv10_graph_destroy_context(struct nouveau_channel *chan) nv10_graph_create_context(chan); nv10_graph_load_context(chan); } - NV_WRITE(NV04_PGRAPH_FIFO,0x1); + NV_WRITE(NV04_PGRAPH_FIFO, 0x1); +#else + if (chid == chan->id) { + DRM_INFO("cleanning a channel with graph in current context\n"); + } +#endif } int nv10_graph_init(struct drm_device *dev) { -- cgit v1.2.3 From f8f31f04574cd6986d7d9ef2215bbb23e0f44b73 Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Sat, 29 Sep 2007 23:06:29 +0200 Subject: nouveau : stop the fifo of the channel we are deleting --- shared-core/nouveau_fifo.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 437c84f2..f82d130b 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -403,7 +403,19 @@ void nouveau_fifo_free(struct nouveau_channel *chan) /* disable the fifo caches */ NV_WRITE(NV03_PFIFO_CACHES, 0x00000000); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1)); + NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000); + NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000); + /* stop the fifo, otherwise it could be running and + * it will crash when removing gpu objects */ + if (dev_priv->card_type < NV_50) { + NV_WRITE(NV03_FIFO_REGS_DMAPUT(chan->id), chan->pushbuf_base); + NV_WRITE(NV03_FIFO_REGS_DMAGET(chan->id), chan->pushbuf_base); + } else { + NV_WRITE(NV50_FIFO_REGS_DMAPUT(chan->id), chan->pushbuf_base); + NV_WRITE(NV50_FIFO_REGS_DMAGET(chan->id), chan->pushbuf_base); + } // FIXME XXX needs more code engine->fifo.destroy_context(chan); @@ -412,6 +424,10 @@ void nouveau_fifo_free(struct nouveau_channel *chan) engine->graph.destroy_context(chan); /* reenable the fifo caches */ + NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, + NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) | 1); + NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001); + NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001); NV_WRITE(NV03_PFIFO_CACHES, 0x00000001); /* Deallocate push buffer */ -- cgit v1.2.3 From c76e04828bd5849f526fae5af7deaf1cbc9f4c55 Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Sun, 30 Sep 2007 14:21:47 +0200 Subject: nouveau : nv04 don't use chan->pgraph_ctx array This commit is a first step to dynamic alloc pgraph context on nv04, nv10. --- shared-core/nv04_graph.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c index 2cf052cf..b07bcfb9 100644 --- a/shared-core/nv04_graph.c +++ b/shared-core/nv04_graph.c @@ -346,6 +346,13 @@ static uint32_t nv04_graph_ctx_regs [] = { }; +struct graph_state { + int nv04[sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0])]; +}; + +/* TODO dynamic allocation ??? */ +static struct graph_state graph_state[16]; + void nouveau_nv04_context_switch(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -414,12 +421,13 @@ void nouveau_nv04_context_switch(struct drm_device *dev) } int nv04_graph_create_context(struct nouveau_channel *chan) { + struct graph_state* pgraph_ctx = graph_state + chan->id; DRM_DEBUG("nv04_graph_context_create %d\n", chan->id); - memset(chan->pgraph_ctx, 0, sizeof(chan->pgraph_ctx)); + memset(pgraph_ctx, 0, sizeof(*pgraph_ctx)); //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; - chan->pgraph_ctx[0] = 0x0001ffff; + pgraph_ctx->nv04[0] = 0x0001ffff; /* is it really needed ??? */ //dev_priv->fifos[channel].pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4); //dev_priv->fifos[channel].pgraph_ctx[2] = NV_READ(0x004006b0); @@ -435,10 +443,11 @@ int nv04_graph_load_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; + struct graph_state* pgraph_ctx = graph_state + chan->id; int i; for (i = 0; i < sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++) - NV_WRITE(nv04_graph_ctx_regs[i], chan->pgraph_ctx[i]); + NV_WRITE(nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]); return 0; } @@ -447,10 +456,11 @@ int nv04_graph_save_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; + struct graph_state* pgraph_ctx = graph_state + chan->id; int i; for (i = 0; i < sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++) - chan->pgraph_ctx[i] = NV_READ(nv04_graph_ctx_regs[i]); + pgraph_ctx->nv04[i] = NV_READ(nv04_graph_ctx_regs[i]); return 0; } @@ -467,10 +477,6 @@ int nv04_graph_init(struct drm_device *dev) { NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF); NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - // check the context is big enough - if ( sizeof(nv04_graph_ctx_regs)>sizeof(dev_priv->fifos[0]->pgraph_ctx) ) - DRM_ERROR("pgraph_ctx too small\n"); - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x000001FF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x1231c000); NV_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100); -- cgit v1.2.3 From fb3ed99fb110a540d16923417c33ff581721ba3a Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Sun, 30 Sep 2007 14:50:22 +0200 Subject: nouveau : pgraph_ctx dynamic alloc for nv04, nv10 --- shared-core/nouveau_drv.h | 3 ++- shared-core/nv04_graph.c | 19 ++++++++++++------- shared-core/nv10_graph.c | 35 ++++++++++++++++++++++------------- 3 files changed, 36 insertions(+), 21 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index e96c8fad..02a4ee75 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -120,8 +120,9 @@ struct nouveau_channel struct nouveau_gpuobj_ref *ramfc; /* PGRAPH context */ + /* XXX may be merge 2 pointers as private data ??? */ struct nouveau_gpuobj_ref *ramin_grctx; - uint32_t pgraph_ctx [340]; /* XXX dynamic alloc ? */ + void *pgraph_ctx; /* NV50 VM */ struct nouveau_gpuobj *vm_pd; diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c index b07bcfb9..33dd0a86 100644 --- a/shared-core/nv04_graph.c +++ b/shared-core/nv04_graph.c @@ -350,9 +350,6 @@ struct graph_state { int nv04[sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0])]; }; -/* TODO dynamic allocation ??? */ -static struct graph_state graph_state[16]; - void nouveau_nv04_context_switch(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -421,10 +418,14 @@ void nouveau_nv04_context_switch(struct drm_device *dev) } int nv04_graph_create_context(struct nouveau_channel *chan) { - struct graph_state* pgraph_ctx = graph_state + chan->id; + struct graph_state* pgraph_ctx; DRM_DEBUG("nv04_graph_context_create %d\n", chan->id); - memset(pgraph_ctx, 0, sizeof(*pgraph_ctx)); + chan->pgraph_ctx = pgraph_ctx = drm_calloc(1, sizeof(*pgraph_ctx), + DRM_MEM_DRIVER); + + if (pgraph_ctx == NULL) + return -ENOMEM; //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; pgraph_ctx->nv04[0] = 0x0001ffff; @@ -437,13 +438,17 @@ int nv04_graph_create_context(struct nouveau_channel *chan) { void nv04_graph_destroy_context(struct nouveau_channel *chan) { + struct graph_state* pgraph_ctx = chan->pgraph_ctx; + + drm_free(pgraph_ctx, sizeof(*pgraph_ctx), DRM_MEM_DRIVER); + chan->pgraph_ctx = NULL; } int nv04_graph_load_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct graph_state* pgraph_ctx = graph_state + chan->id; + struct graph_state* pgraph_ctx = chan->pgraph_ctx; int i; for (i = 0; i < sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++) @@ -456,7 +461,7 @@ int nv04_graph_save_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct graph_state* pgraph_ctx = graph_state + chan->id; + struct graph_state* pgraph_ctx = chan->pgraph_ctx; int i; for (i = 0; i < sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++) diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index c115ba7f..c6319b8f 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -388,17 +388,14 @@ NV10_PGRAPH_DEBUG_4, struct graph_state { int nv10[sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0])]; int nv17[sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0])]; + struct pipe_state pipe_state; }; -/* TODO dynamic allocation ??? */ -static struct pipe_state pipe_state[NV10_FIFO_NUMBER]; -static struct graph_state graph_state[NV10_FIFO_NUMBER]; - - static void nv10_graph_save_pipe(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct pipe_state *fifo_pipe_state = pipe_state + chan->id; + struct graph_state* pgraph_ctx = chan->pgraph_ctx; + struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state; int i; #define PIPE_SAVE(addr) \ do { \ @@ -424,7 +421,8 @@ static void nv10_graph_save_pipe(struct nouveau_channel *chan) { static void nv10_graph_load_pipe(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct pipe_state *fifo_pipe_state = pipe_state + chan->id; + struct graph_state* pgraph_ctx = chan->pgraph_ctx; + struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state; int i; uint32_t xfmode0, xfmode1; #define PIPE_RESTORE(addr) \ @@ -480,7 +478,8 @@ static void nv10_graph_load_pipe(struct nouveau_channel *chan) { } static void nv10_graph_create_pipe(struct nouveau_channel *chan) { - struct pipe_state *fifo_pipe_state = pipe_state + chan->id; + struct graph_state* pgraph_ctx = chan->pgraph_ctx; + struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state; uint32_t *fifo_pipe_state_addr; int i; #define PIPE_INIT(addr) \ @@ -656,7 +655,7 @@ int nv10_graph_load_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct graph_state* pgraph_ctx = graph_state + chan->id; + struct graph_state* pgraph_ctx = chan->pgraph_ctx; int i; for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) @@ -675,7 +674,7 @@ int nv10_graph_save_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct graph_state* pgraph_ctx = graph_state + chan->id; + struct graph_state* pgraph_ctx = chan->pgraph_ctx; int i; for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) @@ -763,11 +762,15 @@ void nouveau_nv10_context_switch(struct drm_device *dev) int nv10_graph_create_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct graph_state* pgraph_ctx = graph_state + chan->id; + struct graph_state* pgraph_ctx; DRM_DEBUG("nv10_graph_context_create %d\n", chan->id); - memset(pgraph_ctx, 0, sizeof(*pgraph_ctx)); + chan->pgraph_ctx = pgraph_ctx = drm_calloc(1, sizeof(*pgraph_ctx), + DRM_MEM_DRIVER); + + if (pgraph_ctx == NULL) + return -ENOMEM; /* mmio trace suggest that should be done in ddx with methods/objects */ #if 0 @@ -824,7 +827,12 @@ void nv10_graph_destroy_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; + struct graph_state* pgraph_ctx = chan->pgraph_ctx; int chid; + + drm_free(pgraph_ctx, sizeof(*pgraph_ctx), DRM_MEM_DRIVER); + chan->pgraph_ctx = NULL; + chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); /* This code seems to corrupt the 3D pipe, but blob seems to do similar things ???? @@ -838,7 +846,8 @@ void nv10_graph_destroy_context(struct nouveau_channel *chan) DRM_INFO("cleanning a channel with graph in current context\n"); nouveau_wait_for_idle(dev); DRM_INFO("reseting current graph context\n"); - nv10_graph_create_context(chan); + /* can't be call here because of dynamic mem alloc */ + //nv10_graph_create_context(chan); nv10_graph_load_context(chan); } NV_WRITE(NV04_PGRAPH_FIFO, 0x1); -- cgit v1.2.3 From a45fce77125aafc42c2cae6b5a896526ec4ab630 Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Sat, 29 Sep 2007 21:07:46 +0300 Subject: nouveau: NV30 should never call nouveau_nv20_context_switch(). --- shared-core/nouveau_irq.c | 1 - 1 file changed, 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index e64677ed..c0199c60 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -364,7 +364,6 @@ static void nouveau_pgraph_irq_handler(struct drm_device *dev) nouveau_nv10_context_switch(dev); break; case NV_20: - case NV_30: nouveau_nv20_context_switch(dev); break; default: -- cgit v1.2.3 From 88bdb38cea60cea918b6e6a1ca97a7ec3de5b832 Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Sat, 29 Sep 2007 21:09:09 +0300 Subject: nouveau: Change couple constants to symbols. --- shared-core/nv30_graph.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index 590a5c33..2210abdb 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -2769,11 +2769,11 @@ nouveau_graph_wait_idle(struct drm_device *dev) int tv = 1000; while (tv--) { - if (NV_READ(0x400700) == 0) + if (NV_READ(NV04_PGRAPH_STATUS) == 0) break; } - if (NV_READ(0x400700)) { + if (NV_READ(NV04_PGRAPH_STATUS)) { DRM_ERROR("timeout!\n"); return -EBUSY; } @@ -2859,7 +2859,7 @@ int nv30_graph_init(struct drm_device *dev) NV_WRITE(0x400B84, 0x0c000000); NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x62ff0f7f); NV_WRITE(0x4000c0, 0x00000016); - NV_WRITE(0x400780, 0x000014e4); + NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, 0x000014e4); /* copy tile info from PFB */ for (i=0; i Date: Sat, 29 Sep 2007 23:06:29 +0300 Subject: nouveau: Make nv20 use the nv30 PGRAPH ctx functions. --- shared-core/nouveau_state.c | 8 ++++---- shared-core/nv20_graph.c | 2 ++ shared-core/nv30_graph.c | 25 +++++++++++++++++++++++-- 3 files changed, 29 insertions(+), 6 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index e73b4878..f8dd3ad5 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -166,10 +166,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) engine->fb.takedown = nv10_fb_takedown; engine->graph.init = nv20_graph_init; engine->graph.takedown = nv20_graph_takedown; - engine->graph.create_context = nv20_graph_create_context; - engine->graph.destroy_context = nv20_graph_destroy_context; - engine->graph.load_context = nv20_graph_load_context; - engine->graph.save_context = nv20_graph_save_context; + engine->graph.create_context = nv30_graph_create_context; + engine->graph.destroy_context = nv30_graph_destroy_context; + engine->graph.load_context = nv30_graph_load_context; + engine->graph.save_context = nv30_graph_save_context; engine->fifo.init = nouveau_fifo_init; engine->fifo.takedown = nouveau_stub_takedown; engine->fifo.create_context = nv10_fifo_create_context; diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index c163daf9..252d90b5 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -29,6 +29,7 @@ #define NV20_GRCTX_SIZE (3529*4) +#if 0 int nv20_graph_create_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -56,6 +57,7 @@ void nv20_graph_destroy_context(struct nouveau_channel *chan) { INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0); } +#endif /* 0 */ static void nv20_graph_rdi(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index 2210abdb..108412ed 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -23,11 +23,23 @@ * */ +/*#define NV20_GRCTX_SIZE (3529*4)*/ + +#define NV28_GRCTX_SIZE (3529*4) #define NV30_31_GRCTX_SIZE (22392) #define NV34_GRCTX_SIZE (18140) #define NV35_36_GRCTX_SIZE (22396) + +static void nv28_graph_context_init(struct drm_device *dev, + struct nouveau_gpuobj *ctx) +{ + int i; + (void)dev; + +} + static void nv30_31_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -2715,6 +2727,10 @@ int nv30_graph_create_context(struct nouveau_channel *chan) int ret; switch (dev_priv->chipset) { + case 0x28: + ctx_size = NV28_GRCTX_SIZE; + ctx_init = nv28_graph_context_init; + break; case 0x30: case 0x31: ctx_size = NV30_31_GRCTX_SIZE; @@ -2732,7 +2748,9 @@ int nv30_graph_create_context(struct nouveau_channel *chan) default: ctx_size = 0; ctx_init = nv35_36_graph_context_init; - DRM_ERROR("Please contact the devs if you want your NV%x card to work\n",dev_priv->chipset); + DRM_ERROR("Please contact the devs if you want your NV%x" + " card to work\n", dev_priv->chipset); + return -ENOSYS; break; } @@ -2744,7 +2762,10 @@ int nv30_graph_create_context(struct nouveau_channel *chan) /* Initialise default context values */ ctx_init(dev, chan->ramin_grctx->gpuobj); - INSTANCE_WR(chan->ramin_grctx->gpuobj, 0x28/4, (chan->id<<24)|0x1); /* CTX_USER */ + /* nv20: INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); */ + INSTANCE_WR(chan->ramin_grctx->gpuobj, 0x28/4, (chan->id<<24)|0x1); + /* CTX_USER */ + INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, chan->ramin_grctx->instance >> 4); -- cgit v1.2.3 From 8ad605a2644251a400700e6f0e25ef76a1c80628 Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Sat, 29 Sep 2007 23:17:19 +0300 Subject: nouveau: let nv20 hardware do ctx switching automatically. --- shared-core/nouveau_irq.c | 3 --- shared-core/nv20_graph.c | 26 +++++++++++++------------- 2 files changed, 13 insertions(+), 16 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index c0199c60..45ae6edf 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -363,9 +363,6 @@ static void nouveau_pgraph_irq_handler(struct drm_device *dev) case NV_17: nouveau_nv10_context_switch(dev); break; - case NV_20: - nouveau_nv20_context_switch(dev); - break; default: DRM_ERROR("Context switch not implemented\n"); break; diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 252d90b5..de97a591 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -57,18 +57,6 @@ void nv20_graph_destroy_context(struct nouveau_channel *chan) { INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0); } -#endif /* 0 */ - -static void nv20_graph_rdi(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000); - for (i = 0; i < 32; i++) - NV_WRITE(NV10_PGRAPH_RDI_DATA, 0); - - nouveau_wait_for_idle(dev); -} /* Save current context (from PGRAPH) into the channel's context */ @@ -145,6 +133,18 @@ void nouveau_nv20_context_switch(struct drm_device *dev) NV_WRITE(NV04_PGRAPH_FIFO,0x1); } +#endif /* 0 */ + +static void nv20_graph_rdi(struct drm_device *dev) { + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; + + NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000); + for (i = 0; i < 32; i++) + NV_WRITE(NV10_PGRAPH_RDI_DATA, 0); + + nouveau_wait_for_idle(dev); +} int nv20_graph_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = @@ -177,7 +177,7 @@ int nv20_graph_init(struct drm_device *dev) { NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700); - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xF20E0431); + NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xF20E0435); /* 0x4 = auto ctx switch */ NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000); NV_WRITE(0x40009C , 0x00000040); -- cgit v1.2.3 From aa2c3379914fc6fea63bfcfd8579ab6cd8d70a68 Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Sun, 30 Sep 2007 12:03:22 +0300 Subject: nouveau: nv28 graph context init --- shared-core/nv30_graph.c | 160 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 156 insertions(+), 4 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index 108412ed..951947df 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -35,12 +35,162 @@ static void nv28_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { + struct drm_nouveau_private *dev_priv = dev->dev_private; int i; - (void)dev; +/* +write32 #1 block at +0x00740a7c NV_PRAMIN.GRCTX0+0x35c of 173 (0xad) elements: ++0x00740a7c: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740a9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740abc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740adc: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000 ++0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740b3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + ++0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740bbc: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000 ++0x00740bdc: 00000000 00000000 00000000 00000080 ffff0000 00000001 00000000 00000000 ++0x00740bfc: 00000000 00000000 44400000 00000000 00000000 00000000 00000000 00000000 ++0x00740c1c: 4b800000 00000000 00000000 00000000 00000000 00030303 00030303 00030303 ++0x00740c3c: 00030303 00000000 00000000 00000000 00000000 00080000 00080000 00080000 ++0x00740c5c: 00080000 00000000 00000000 01012000 01012000 01012000 01012000 000105b8 + ++0x00740c7c: 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008 00000000 ++0x00740c9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 07ff0000 ++0x00740cbc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 ++0x00740cdc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 00000000 ++0x00740cfc: 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740d1c: 00000000 00000000 00000000 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x35c/4)+0, 0xffff0000); + INSTANCE_WR(ctx, (0x35c/4)+25, 0x0fff0000); + INSTANCE_WR(ctx, (0x35c/4)+26, 0x0fff0000); + INSTANCE_WR(ctx, (0x35c/4)+80, 0x00000101); + INSTANCE_WR(ctx, (0x35c/4)+85, 0x00000111); + INSTANCE_WR(ctx, (0x35c/4)+91, 0x00000080); + INSTANCE_WR(ctx, (0x35c/4)+92, 0xffff0000); + INSTANCE_WR(ctx, (0x35c/4)+93, 0x00000001); + INSTANCE_WR(ctx, (0x35c/4)+98, 0x44400000); + INSTANCE_WR(ctx, (0x35c/4)+104, 0x4b800000); + INSTANCE_WR(ctx, (0x35c/4)+109, 0x00030303); + INSTANCE_WR(ctx, (0x35c/4)+110, 0x00030303); + INSTANCE_WR(ctx, (0x35c/4)+111, 0x00030303); + INSTANCE_WR(ctx, (0x35c/4)+112, 0x00030303); + INSTANCE_WR(ctx, (0x35c/4)+117, 0x00080000); + INSTANCE_WR(ctx, (0x35c/4)+118, 0x00080000); + INSTANCE_WR(ctx, (0x35c/4)+119, 0x00080000); + INSTANCE_WR(ctx, (0x35c/4)+120, 0x00080000); + INSTANCE_WR(ctx, (0x35c/4)+123, 0x01012000); + INSTANCE_WR(ctx, (0x35c/4)+124, 0x01012000); + INSTANCE_WR(ctx, (0x35c/4)+125, 0x01012000); + INSTANCE_WR(ctx, (0x35c/4)+126, 0x01012000); + INSTANCE_WR(ctx, (0x35c/4)+127, 0x000105b8); + INSTANCE_WR(ctx, (0x35c/4)+128, 0x000105b8); + INSTANCE_WR(ctx, (0x35c/4)+129, 0x000105b8); + INSTANCE_WR(ctx, (0x35c/4)+130, 0x000105b8); + INSTANCE_WR(ctx, (0x35c/4)+131, 0x00080008); + INSTANCE_WR(ctx, (0x35c/4)+132, 0x00080008); + INSTANCE_WR(ctx, (0x35c/4)+133, 0x00080008); + INSTANCE_WR(ctx, (0x35c/4)+134, 0x00080008); + for (i=0; i<16; ++i) + INSTANCE_WR(ctx, (0x35c/4)+143+i, 0x07ff0000); + INSTANCE_WR(ctx, (0x35c/4)+161, 0x4b7ffff); + +/* +write32 #1 block at +0x00740d34 NV_PRAMIN.GRCTX0+0x614 of 3136 (0xc40) elements: ++0x00740d34: 00000000 00000000 00000000 00000080 30201000 70605040 b0a09080 f0e0d0c0 ++0x00740d54: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740d74: 00000000 00000000 00000000 00000000 00000001 00000000 00004000 00000000 ++0x00740d94: 00000000 00000001 00000000 00040000 00010000 00000000 00000000 00000000 ++0x00740db4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +... ++0x00742214: 00000000 00000000 00000000 00000000 10700ff9 0436086c 000c001b 00000000 ++0x00742234: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 ++0x00742254: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 ++0x00742274: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 +... ++0x00742a34: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 ++0x00742a54: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 ++0x00742a74: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 ++0x00742a94: 10700ff9 0436086c 000c001b 00000000 00000000 00000000 00000000 00000000 ++0x00742ab4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00742ad4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x614/4)+3, 0x00000080); + INSTANCE_WR(ctx, (0x614/4)+4, 0x30201000); + INSTANCE_WR(ctx, (0x614/4)+5, 0x70605040); + INSTANCE_WR(ctx, (0x614/4)+6, 0xb0a09080); + INSTANCE_WR(ctx, (0x614/4)+7, 0xf0e0d0c0); + INSTANCE_WR(ctx, (0x614/4)+20, 0x00000001); + INSTANCE_WR(ctx, (0x614/4)+22, 0x00004000); + INSTANCE_WR(ctx, (0x614/4)+25, 0x00000001); + INSTANCE_WR(ctx, (0x614/4)+27, 0x00040000); + INSTANCE_WR(ctx, (0x614/4)+28, 0x00010000); + for (i=0; i<0x880; i+=4) { + INSTANCE_WR(ctx, (0x1b04/4)+i+0, 0x10700ff9); + INSTANCE_WR(ctx, (0x1b04/4)+i+1, 0x0436086c); + INSTANCE_WR(ctx, (0x1b04/4)+i+2, 0x000c001b); + INSTANCE_WR(ctx, (0x1b04/4)+i+3, 0x00000000); + } + +/* +write32 #1 block at +0x00742e24 NV_PRAMIN.GRCTX0+0x2704 of 4 (0x4) elements: ++0x00742e24: 3f800000 00000000 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x2704/4), 0x3f800000); + +/* +write32 #1 block at +0x00742e64 NV_PRAMIN.GRCTX0+0x2744 of 12 (0xc) elements: ++0x00742e64: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000 ++0x00742e84: 00000000 bf800000 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x2744/4)+0, 0x40000000); + INSTANCE_WR(ctx, (0x2744/4)+1, 0x3f800000); + INSTANCE_WR(ctx, (0x2744/4)+2, 0x3f000000); + INSTANCE_WR(ctx, (0x2744/4)+4, 0x40000000); + INSTANCE_WR(ctx, (0x2744/4)+5, 0x3f800000); + INSTANCE_WR(ctx, (0x2744/4)+7, 0xbf800000); + INSTANCE_WR(ctx, (0x2744/4)+9, 0xbf800000); + +/* +write32 #1 block at +0x00742e34 NV_PRAMIN.GRCTX0+0x2714 of 4 (0x4) elements: ++0x00742e34: 00000000 3f800000 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x2714/4)+1, 0x3f800000); + +/* +write32 #1 block at +0x00742e94 NV_PRAMIN.GRCTX0+0x2774 of 4 (0x4) elements: ++0x00742e94: 00000000 00000000 00000000 00000000 +write32 #1 block at +0x00743804 NV_PRAMIN.GRCTX0+0x30e4 of 4 (0x4) elements: ++0x00743804: 00000000 00000000 00000000 00000000 +write32 #1 block at +0x007437a4 NV_PRAMIN.GRCTX0+0x3084 of 8 (0x8) elements: ++0x007437a4: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x3084/4)+2, 0x000fe000); +/* +write32 #1 block at +0x007437d4 NV_PRAMIN.GRCTX0+0x30b4 of 4 (0x4) elements: ++0x007437d4: 00000000 00000000 00000000 00000000 +write32 #1 block at +0x00743824 NV_PRAMIN.GRCTX0+0x3104 of 4 (0x4) elements: ++0x00743824: 00000000 000003f8 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x3104/4)+1, 0x000003f8); + +/* write32 #1 NV_PRAMIN.GRCTX0+0x3468 <- 0x002fe000 */ + INSTANCE_WR(ctx, 0x3468/4, 0x002fe000); + +/* +write32 #1 block at +0x00743ba4 NV_PRAMIN.GRCTX0+0x3484 of 8 (0x8) elements: ++0x00743ba4: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c +*/ + for (i=0; i<8; ++i) + INSTANCE_WR(ctx, (0x3484/4)+i, 0x001c527c); } -static void nv30_31_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) +static void nv30_31_graph_context_init(struct drm_device *dev, + struct nouveau_gpuobj *ctx) { struct drm_nouveau_private *dev_priv = dev->dev_private; int i; @@ -933,7 +1083,8 @@ static void nv30_31_graph_context_init(struct drm_device *dev, struct nouveau_gp INSTANCE_WR(ctx, 0x386c/4, 0xbf800000); } -static void nv34_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) +static void nv34_graph_context_init(struct drm_device *dev, + struct nouveau_gpuobj *ctx) { struct drm_nouveau_private *dev_priv = dev->dev_private; int i; @@ -1826,7 +1977,8 @@ static void nv34_graph_context_init(struct drm_device *dev, struct nouveau_gpuob INSTANCE_WR(ctx, 0x2f00/4, 0xbf800000); } -static void nv35_36_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) +static void nv35_36_graph_context_init(struct drm_device *dev, + struct nouveau_gpuobj *ctx) { struct drm_nouveau_private *dev_priv = dev->dev_private; int i; -- cgit v1.2.3 From a67060c810613059b71c14e9fa91ea114fcf0106 Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Sun, 30 Sep 2007 18:14:24 +0300 Subject: nouveau: graph ctx init nv25 According to mmio_trace_900XGL.tar.bz2 by Evan Fraser the nv25 init is exactly the same as nv28 init. --- shared-core/nv30_graph.c | 1 + 1 file changed, 1 insertion(+) (limited to 'shared-core') diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index 951947df..0ec4f096 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -2879,6 +2879,7 @@ int nv30_graph_create_context(struct nouveau_channel *chan) int ret; switch (dev_priv->chipset) { + case 0x25: case 0x28: ctx_size = NV28_GRCTX_SIZE; ctx_init = nv28_graph_context_init; -- cgit v1.2.3 From 205403aea8213ffc0e36f4103d78d62bf1584a69 Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Sun, 30 Sep 2007 21:10:06 +0300 Subject: nouveau: nv30 graph function renames, removed nv20_graph.c All nv30 functions in nv30_graph.c that can be used on nv20 are renamed as accordingly. nv20 specific parts from nv20_graph.c are moved into nv30_graph.c. --- shared-core/nouveau_drv.h | 14 +-- shared-core/nouveau_state.c | 18 ++-- shared-core/nv20_graph.c | 251 -------------------------------------------- shared-core/nv30_graph.c | 144 +++++++++++++++++++++---- 4 files changed, 136 insertions(+), 291 deletions(-) delete mode 100644 shared-core/nv20_graph.c (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 02a4ee75..85a2dd57 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -490,22 +490,14 @@ extern void nv10_graph_destroy_context(struct nouveau_channel *); extern int nv10_graph_load_context(struct nouveau_channel *); extern int nv10_graph_save_context(struct nouveau_channel *); -/* nv20_graph.c */ -extern void nouveau_nv20_context_switch(struct drm_device *); -extern int nv20_graph_init(struct drm_device *); -extern void nv20_graph_takedown(struct drm_device *); +/* nv30_graph.c */ extern int nv20_graph_create_context(struct nouveau_channel *); extern void nv20_graph_destroy_context(struct nouveau_channel *); extern int nv20_graph_load_context(struct nouveau_channel *); extern int nv20_graph_save_context(struct nouveau_channel *); - -/* nv30_graph.c */ +extern int nv20_graph_init(struct drm_device *); +extern void nv20_graph_takedown(struct drm_device *); extern int nv30_graph_init(struct drm_device *); -extern void nv30_graph_takedown(struct drm_device *); -extern int nv30_graph_create_context(struct nouveau_channel *); -extern void nv30_graph_destroy_context(struct nouveau_channel *); -extern int nv30_graph_load_context(struct nouveau_channel *); -extern int nv30_graph_save_context(struct nouveau_channel *); /* nv40_graph.c */ extern int nv40_graph_init(struct drm_device *); diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index f8dd3ad5..cba12b57 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -166,10 +166,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) engine->fb.takedown = nv10_fb_takedown; engine->graph.init = nv20_graph_init; engine->graph.takedown = nv20_graph_takedown; - engine->graph.create_context = nv30_graph_create_context; - engine->graph.destroy_context = nv30_graph_destroy_context; - engine->graph.load_context = nv30_graph_load_context; - engine->graph.save_context = nv30_graph_save_context; + engine->graph.create_context = nv20_graph_create_context; + engine->graph.destroy_context = nv20_graph_destroy_context; + engine->graph.load_context = nv20_graph_load_context; + engine->graph.save_context = nv20_graph_save_context; engine->fifo.init = nouveau_fifo_init; engine->fifo.takedown = nouveau_stub_takedown; engine->fifo.create_context = nv10_fifo_create_context; @@ -192,11 +192,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) engine->fb.init = nv10_fb_init; engine->fb.takedown = nv10_fb_takedown; engine->graph.init = nv30_graph_init; - engine->graph.takedown = nv30_graph_takedown; - engine->graph.create_context = nv30_graph_create_context; - engine->graph.destroy_context = nv30_graph_destroy_context; - engine->graph.load_context = nv30_graph_load_context; - engine->graph.save_context = nv30_graph_save_context; + engine->graph.takedown = nv20_graph_takedown; + engine->graph.create_context = nv20_graph_create_context; + engine->graph.destroy_context = nv20_graph_destroy_context; + engine->graph.load_context = nv20_graph_load_context; + engine->graph.save_context = nv20_graph_save_context; engine->fifo.init = nouveau_fifo_init; engine->fifo.takedown = nouveau_stub_takedown; engine->fifo.create_context = nv10_fifo_create_context; diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c deleted file mode 100644 index de97a591..00000000 --- a/shared-core/nv20_graph.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright 2007 Matthieu CASTET - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "drmP.h" -#include "drm.h" -#include "nouveau_drv.h" -#include "nouveau_drm.h" - -#define NV20_GRCTX_SIZE (3529*4) - -#if 0 -int nv20_graph_create_context(struct nouveau_channel *chan) { - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - unsigned int ctx_size = NV20_GRCTX_SIZE; - int ret; - - if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16, - NVOBJ_FLAG_ZERO_ALLOC, - &chan->ramin_grctx))) - return ret; - - /* Initialise default context values */ - INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); /* CTX_USER */ - - INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, - chan->ramin_grctx->instance >> 4); - return 0; -} - -void nv20_graph_destroy_context(struct nouveau_channel *chan) { - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - - nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); - - INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0); -} - -/* Save current context (from PGRAPH) into the channel's context - */ -int nv20_graph_save_context(struct nouveau_channel *chan) { - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t instance; - - instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, chan->id); - if (!instance) { - return -EINVAL; - } - if (instance != (chan->ramin_grctx->instance >> 4)) - DRM_ERROR("nv20_graph_save_context : bad instance\n"); - - NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance); - NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 2 /* save ctx */); - return 0; -} - - -/* Restore the context for a specific channel into PGRAPH - */ -int nv20_graph_load_context(struct nouveau_channel *chan) { - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t instance; - - instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, chan->id); - if (!instance) { - return -EINVAL; - } - if (instance != (chan->ramin_grctx->instance >> 4)) - DRM_ERROR("nv20_graph_load_context_current : bad instance\n"); - - NV_WRITE(NV10_PGRAPH_CTX_USER, chan->id << 24); - NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance); - NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 1 /* restore ctx */); - return 0; -} - -void nouveau_nv20_context_switch(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_channel *next, *last; - int chid; - - chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); - next = dev_priv->fifos[chid]; - - chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); - last = dev_priv->fifos[chid]; - - DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n", - last->id, next->id); - - NV_WRITE(NV04_PGRAPH_FIFO,0x0); - - nv20_graph_save_context(last); - - nouveau_wait_for_idle(dev); - - NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000000); - - nv20_graph_load_context(next); - - nouveau_wait_for_idle(dev); - - if ((NV_READ(NV10_PGRAPH_CTX_USER) >> 24) != next->id) - DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", next->id, NV_READ(NV10_PGRAPH_CTX_USER) >> 24); - - NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100); - NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); - - NV_WRITE(NV04_PGRAPH_FIFO,0x1); -} -#endif /* 0 */ - -static void nv20_graph_rdi(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000); - for (i = 0; i < 32; i++) - NV_WRITE(NV10_PGRAPH_RDI_DATA, 0); - - nouveau_wait_for_idle(dev); -} - -int nv20_graph_init(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = - (struct drm_nouveau_private *)dev->dev_private; - uint32_t tmp, vramsz; - int ret, i; - - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & - ~NV_PMC_ENABLE_PGRAPH); - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | - NV_PMC_ENABLE_PGRAPH); - - /* Create Context Pointer Table */ - dev_priv->ctx_table_size = 32 * 4; - if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, - dev_priv->ctx_table_size, 16, - NVOBJ_FLAG_ZERO_ALLOC, - &dev_priv->ctx_table))) - return ret; - - NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, - dev_priv->ctx_table->instance >> 4); - - //XXX need to be done and save/restore for each fifo ??? - nv20_graph_rdi(dev); - - NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); - NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); - NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700); - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xF20E0435); /* 0x4 = auto ctx switch */ - NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000); - NV_WRITE(0x40009C , 0x00000040); - - if (dev_priv->chipset >= 0x25) { - NV_WRITE(0x400890, 0x00080000); - NV_WRITE(0x400610, 0x304B1FB6); - NV_WRITE(0x400B80, 0x18B82880); - NV_WRITE(0x400B84, 0x44000000); - NV_WRITE(0x400098, 0x40000080); - NV_WRITE(0x400B88, 0x000000ff); - } else { - NV_WRITE(0x400880, 0x00080000); - NV_WRITE(0x400094, 0x00000005); - NV_WRITE(0x400B80, 0x45CAA208); - NV_WRITE(0x400B84, 0x24000000); - NV_WRITE(0x400098, 0x00000040); - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00038); - NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030); - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E10038); - NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030); - } - - /* copy tile info from PFB */ - for (i=0; idev_private; - - nouveau_gpuobj_ref_del(dev, &dev_priv->ctx_table); -} - diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index 0ec4f096..8ca1f84c 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -1,7 +1,3 @@ -/* - * Based on nv40_graph.c - * Someday this will all go away... - */ #include "drmP.h" #include "drm.h" #include "nouveau_drv.h" @@ -25,14 +21,14 @@ /*#define NV20_GRCTX_SIZE (3529*4)*/ -#define NV28_GRCTX_SIZE (3529*4) +#define NV25_GRCTX_SIZE (3529*4) #define NV30_31_GRCTX_SIZE (22392) #define NV34_GRCTX_SIZE (18140) #define NV35_36_GRCTX_SIZE (22396) -static void nv28_graph_context_init(struct drm_device *dev, +static void nv25_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -2868,9 +2864,10 @@ static void nv35_36_graph_context_init(struct drm_device *dev, INSTANCE_WR(ctx, 0x385c/4, 0x40000000); INSTANCE_WR(ctx, 0x3860/4, 0x3f800000); INSTANCE_WR(ctx, 0x3868/4, 0xbf800000); - INSTANCE_WR(ctx, 0x3870/4, 0xbf800000);} + INSTANCE_WR(ctx, 0x3870/4, 0xbf800000); +} -int nv30_graph_create_context(struct nouveau_channel *chan) +int nv20_graph_create_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -2881,8 +2878,8 @@ int nv30_graph_create_context(struct nouveau_channel *chan) switch (dev_priv->chipset) { case 0x25: case 0x28: - ctx_size = NV28_GRCTX_SIZE; - ctx_init = nv28_graph_context_init; + ctx_size = NV25_GRCTX_SIZE; + ctx_init = nv25_graph_context_init; break; case 0x30: case 0x31: @@ -2925,7 +2922,7 @@ int nv30_graph_create_context(struct nouveau_channel *chan) return 0; } -void nv30_graph_destroy_context(struct nouveau_channel *chan) +void nv20_graph_destroy_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -2954,7 +2951,7 @@ nouveau_graph_wait_idle(struct drm_device *dev) return 0; } -int nv30_graph_load_context(struct nouveau_channel *chan) +int nv20_graph_load_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -2971,7 +2968,7 @@ int nv30_graph_load_context(struct nouveau_channel *chan) return nouveau_graph_wait_idle(dev); } -int nv30_graph_save_context(struct nouveau_channel *chan) +int nv20_graph_save_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -2988,6 +2985,120 @@ int nv30_graph_save_context(struct nouveau_channel *chan) return nouveau_graph_wait_idle(dev); } +static void nv20_graph_rdi(struct drm_device *dev) { + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; + + NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000); + for (i = 0; i < 32; i++) + NV_WRITE(NV10_PGRAPH_RDI_DATA, 0); + + nouveau_wait_for_idle(dev); +} + +int nv20_graph_init(struct drm_device *dev) { + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; + uint32_t tmp, vramsz; + int ret, i; + + NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & + ~NV_PMC_ENABLE_PGRAPH); + NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | + NV_PMC_ENABLE_PGRAPH); + + /* Create Context Pointer Table */ + dev_priv->ctx_table_size = 32 * 4; + if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, + dev_priv->ctx_table_size, 16, + NVOBJ_FLAG_ZERO_ALLOC, + &dev_priv->ctx_table))) + return ret; + + NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, + dev_priv->ctx_table->instance >> 4); + + //XXX need to be done and save/restore for each fifo ??? + nv20_graph_rdi(dev); + + NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); + NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); + + NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); + NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); + NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700); + NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xF20E0435); /* 0x4 = auto ctx switch */ + NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000); + NV_WRITE(0x40009C , 0x00000040); + + if (dev_priv->chipset >= 0x25) { + NV_WRITE(0x400890, 0x00080000); + NV_WRITE(0x400610, 0x304B1FB6); + NV_WRITE(0x400B80, 0x18B82880); + NV_WRITE(0x400B84, 0x44000000); + NV_WRITE(0x400098, 0x40000080); + NV_WRITE(0x400B88, 0x000000ff); + } else { + NV_WRITE(0x400880, 0x00080000); + NV_WRITE(0x400094, 0x00000005); + NV_WRITE(0x400B80, 0x45CAA208); + NV_WRITE(0x400B84, 0x24000000); + NV_WRITE(0x400098, 0x00000040); + NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00038); + NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030); + NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E10038); + NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030); + } + + /* copy tile info from PFB */ + for (i=0; idev_private; + + nouveau_gpuobj_ref_del(dev, &dev_priv->ctx_table); +} + int nv30_graph_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -3077,10 +3188,3 @@ int nv30_graph_init(struct drm_device *dev) return 0; } -void nv30_graph_takedown(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - nouveau_gpuobj_ref_del(dev, &dev_priv->ctx_table); -} - -- cgit v1.2.3 From aa135ba8e86d43a738973a25d638b7dc4cdddc55 Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Sun, 30 Sep 2007 22:04:53 +0300 Subject: nouveau: rename nv30_graph.c to nv20_graph.c --- shared-core/nouveau_drv.h | 2 +- shared-core/nv20_graph.c | 3190 +++++++++++++++++++++++++++++++++++++++++++++ shared-core/nv30_graph.c | 3190 --------------------------------------------- 3 files changed, 3191 insertions(+), 3191 deletions(-) create mode 100644 shared-core/nv20_graph.c delete mode 100644 shared-core/nv30_graph.c (limited to 'shared-core') diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 85a2dd57..e5cef075 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -490,7 +490,7 @@ extern void nv10_graph_destroy_context(struct nouveau_channel *); extern int nv10_graph_load_context(struct nouveau_channel *); extern int nv10_graph_save_context(struct nouveau_channel *); -/* nv30_graph.c */ +/* nv20_graph.c */ extern int nv20_graph_create_context(struct nouveau_channel *); extern void nv20_graph_destroy_context(struct nouveau_channel *); extern int nv20_graph_load_context(struct nouveau_channel *); diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c new file mode 100644 index 00000000..8ca1f84c --- /dev/null +++ b/shared-core/nv20_graph.c @@ -0,0 +1,3190 @@ +#include "drmP.h" +#include "drm.h" +#include "nouveau_drv.h" +#include "nouveau_drm.h" + +/* + * There are 3 families : + * NV30 is 0x10de:0x030* + * NV31 is 0x10de:0x031* + * + * NV34 is 0x10de:0x032* + * + * NV35 is 0x10de:0x033* (NV35 and NV36 are the same) + * NV36 is 0x10de:0x034* + * + * Not seen in the wild, no dumps (probably NV35) : + * NV37 is 0x10de:0x00fc, 0x10de:0x00fd + * NV38 is 0x10de:0x0333, 0x10de:0x00fe + * + */ + +/*#define NV20_GRCTX_SIZE (3529*4)*/ + +#define NV25_GRCTX_SIZE (3529*4) + +#define NV30_31_GRCTX_SIZE (22392) +#define NV34_GRCTX_SIZE (18140) +#define NV35_36_GRCTX_SIZE (22396) + + +static void nv25_graph_context_init(struct drm_device *dev, + struct nouveau_gpuobj *ctx) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; +/* +write32 #1 block at +0x00740a7c NV_PRAMIN.GRCTX0+0x35c of 173 (0xad) elements: ++0x00740a7c: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740a9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740abc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740adc: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000 ++0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740b3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + ++0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740bbc: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000 ++0x00740bdc: 00000000 00000000 00000000 00000080 ffff0000 00000001 00000000 00000000 ++0x00740bfc: 00000000 00000000 44400000 00000000 00000000 00000000 00000000 00000000 ++0x00740c1c: 4b800000 00000000 00000000 00000000 00000000 00030303 00030303 00030303 ++0x00740c3c: 00030303 00000000 00000000 00000000 00000000 00080000 00080000 00080000 ++0x00740c5c: 00080000 00000000 00000000 01012000 01012000 01012000 01012000 000105b8 + ++0x00740c7c: 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008 00000000 ++0x00740c9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 07ff0000 ++0x00740cbc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 ++0x00740cdc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 00000000 ++0x00740cfc: 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740d1c: 00000000 00000000 00000000 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x35c/4)+0, 0xffff0000); + INSTANCE_WR(ctx, (0x35c/4)+25, 0x0fff0000); + INSTANCE_WR(ctx, (0x35c/4)+26, 0x0fff0000); + INSTANCE_WR(ctx, (0x35c/4)+80, 0x00000101); + INSTANCE_WR(ctx, (0x35c/4)+85, 0x00000111); + INSTANCE_WR(ctx, (0x35c/4)+91, 0x00000080); + INSTANCE_WR(ctx, (0x35c/4)+92, 0xffff0000); + INSTANCE_WR(ctx, (0x35c/4)+93, 0x00000001); + INSTANCE_WR(ctx, (0x35c/4)+98, 0x44400000); + INSTANCE_WR(ctx, (0x35c/4)+104, 0x4b800000); + INSTANCE_WR(ctx, (0x35c/4)+109, 0x00030303); + INSTANCE_WR(ctx, (0x35c/4)+110, 0x00030303); + INSTANCE_WR(ctx, (0x35c/4)+111, 0x00030303); + INSTANCE_WR(ctx, (0x35c/4)+112, 0x00030303); + INSTANCE_WR(ctx, (0x35c/4)+117, 0x00080000); + INSTANCE_WR(ctx, (0x35c/4)+118, 0x00080000); + INSTANCE_WR(ctx, (0x35c/4)+119, 0x00080000); + INSTANCE_WR(ctx, (0x35c/4)+120, 0x00080000); + INSTANCE_WR(ctx, (0x35c/4)+123, 0x01012000); + INSTANCE_WR(ctx, (0x35c/4)+124, 0x01012000); + INSTANCE_WR(ctx, (0x35c/4)+125, 0x01012000); + INSTANCE_WR(ctx, (0x35c/4)+126, 0x01012000); + INSTANCE_WR(ctx, (0x35c/4)+127, 0x000105b8); + INSTANCE_WR(ctx, (0x35c/4)+128, 0x000105b8); + INSTANCE_WR(ctx, (0x35c/4)+129, 0x000105b8); + INSTANCE_WR(ctx, (0x35c/4)+130, 0x000105b8); + INSTANCE_WR(ctx, (0x35c/4)+131, 0x00080008); + INSTANCE_WR(ctx, (0x35c/4)+132, 0x00080008); + INSTANCE_WR(ctx, (0x35c/4)+133, 0x00080008); + INSTANCE_WR(ctx, (0x35c/4)+134, 0x00080008); + for (i=0; i<16; ++i) + INSTANCE_WR(ctx, (0x35c/4)+143+i, 0x07ff0000); + INSTANCE_WR(ctx, (0x35c/4)+161, 0x4b7ffff); + +/* +write32 #1 block at +0x00740d34 NV_PRAMIN.GRCTX0+0x614 of 3136 (0xc40) elements: ++0x00740d34: 00000000 00000000 00000000 00000080 30201000 70605040 b0a09080 f0e0d0c0 ++0x00740d54: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740d74: 00000000 00000000 00000000 00000000 00000001 00000000 00004000 00000000 ++0x00740d94: 00000000 00000001 00000000 00040000 00010000 00000000 00000000 00000000 ++0x00740db4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +... ++0x00742214: 00000000 00000000 00000000 00000000 10700ff9 0436086c 000c001b 00000000 ++0x00742234: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 ++0x00742254: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 ++0x00742274: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 +... ++0x00742a34: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 ++0x00742a54: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 ++0x00742a74: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 ++0x00742a94: 10700ff9 0436086c 000c001b 00000000 00000000 00000000 00000000 00000000 ++0x00742ab4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00742ad4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x614/4)+3, 0x00000080); + INSTANCE_WR(ctx, (0x614/4)+4, 0x30201000); + INSTANCE_WR(ctx, (0x614/4)+5, 0x70605040); + INSTANCE_WR(ctx, (0x614/4)+6, 0xb0a09080); + INSTANCE_WR(ctx, (0x614/4)+7, 0xf0e0d0c0); + INSTANCE_WR(ctx, (0x614/4)+20, 0x00000001); + INSTANCE_WR(ctx, (0x614/4)+22, 0x00004000); + INSTANCE_WR(ctx, (0x614/4)+25, 0x00000001); + INSTANCE_WR(ctx, (0x614/4)+27, 0x00040000); + INSTANCE_WR(ctx, (0x614/4)+28, 0x00010000); + for (i=0; i<0x880; i+=4) { + INSTANCE_WR(ctx, (0x1b04/4)+i+0, 0x10700ff9); + INSTANCE_WR(ctx, (0x1b04/4)+i+1, 0x0436086c); + INSTANCE_WR(ctx, (0x1b04/4)+i+2, 0x000c001b); + INSTANCE_WR(ctx, (0x1b04/4)+i+3, 0x00000000); + } + +/* +write32 #1 block at +0x00742e24 NV_PRAMIN.GRCTX0+0x2704 of 4 (0x4) elements: ++0x00742e24: 3f800000 00000000 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x2704/4), 0x3f800000); + +/* +write32 #1 block at +0x00742e64 NV_PRAMIN.GRCTX0+0x2744 of 12 (0xc) elements: ++0x00742e64: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000 ++0x00742e84: 00000000 bf800000 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x2744/4)+0, 0x40000000); + INSTANCE_WR(ctx, (0x2744/4)+1, 0x3f800000); + INSTANCE_WR(ctx, (0x2744/4)+2, 0x3f000000); + INSTANCE_WR(ctx, (0x2744/4)+4, 0x40000000); + INSTANCE_WR(ctx, (0x2744/4)+5, 0x3f800000); + INSTANCE_WR(ctx, (0x2744/4)+7, 0xbf800000); + INSTANCE_WR(ctx, (0x2744/4)+9, 0xbf800000); + +/* +write32 #1 block at +0x00742e34 NV_PRAMIN.GRCTX0+0x2714 of 4 (0x4) elements: ++0x00742e34: 00000000 3f800000 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x2714/4)+1, 0x3f800000); + +/* +write32 #1 block at +0x00742e94 NV_PRAMIN.GRCTX0+0x2774 of 4 (0x4) elements: ++0x00742e94: 00000000 00000000 00000000 00000000 +write32 #1 block at +0x00743804 NV_PRAMIN.GRCTX0+0x30e4 of 4 (0x4) elements: ++0x00743804: 00000000 00000000 00000000 00000000 +write32 #1 block at +0x007437a4 NV_PRAMIN.GRCTX0+0x3084 of 8 (0x8) elements: ++0x007437a4: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x3084/4)+2, 0x000fe000); + +/* +write32 #1 block at +0x007437d4 NV_PRAMIN.GRCTX0+0x30b4 of 4 (0x4) elements: ++0x007437d4: 00000000 00000000 00000000 00000000 +write32 #1 block at +0x00743824 NV_PRAMIN.GRCTX0+0x3104 of 4 (0x4) elements: ++0x00743824: 00000000 000003f8 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x3104/4)+1, 0x000003f8); + +/* write32 #1 NV_PRAMIN.GRCTX0+0x3468 <- 0x002fe000 */ + INSTANCE_WR(ctx, 0x3468/4, 0x002fe000); + +/* +write32 #1 block at +0x00743ba4 NV_PRAMIN.GRCTX0+0x3484 of 8 (0x8) elements: ++0x00743ba4: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c +*/ + for (i=0; i<8; ++i) + INSTANCE_WR(ctx, (0x3484/4)+i, 0x001c527c); +} + +static void nv30_31_graph_context_init(struct drm_device *dev, + struct nouveau_gpuobj *ctx) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; + + INSTANCE_WR(ctx, 0x410/4, 0x00000101); + INSTANCE_WR(ctx, 0x424/4, 0x00000111); + INSTANCE_WR(ctx, 0x428/4, 0x00000060); + INSTANCE_WR(ctx, 0x444/4, 0x00000080); + INSTANCE_WR(ctx, 0x448/4, 0xffff0000); + INSTANCE_WR(ctx, 0x44c/4, 0x00000001); + INSTANCE_WR(ctx, 0x460/4, 0x44400000); + INSTANCE_WR(ctx, 0x48c/4, 0xffff0000); + for(i = 0x4e0; i< 0x4e8; i += 4) + INSTANCE_WR(ctx, i/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x4ec/4, 0x00011100); + for(i = 0x508; i< 0x548; i += 4) + INSTANCE_WR(ctx, i/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x550/4, 0x4b7fffff); + INSTANCE_WR(ctx, 0x58c/4, 0x00000080); + INSTANCE_WR(ctx, 0x590/4, 0x30201000); + INSTANCE_WR(ctx, 0x594/4, 0x70605040); + INSTANCE_WR(ctx, 0x598/4, 0xb8a89888); + INSTANCE_WR(ctx, 0x59c/4, 0xf8e8d8c8); + INSTANCE_WR(ctx, 0x5b0/4, 0xb0000000); + for(i = 0x600; i< 0x640; i += 4) + INSTANCE_WR(ctx, i/4, 0x00010588); + for(i = 0x640; i< 0x680; i += 4) + INSTANCE_WR(ctx, i/4, 0x00030303); + for(i = 0x6c0; i< 0x700; i += 4) + INSTANCE_WR(ctx, i/4, 0x0008aae4); + for(i = 0x700; i< 0x740; i += 4) + INSTANCE_WR(ctx, i/4, 0x01012000); + for(i = 0x740; i< 0x780; i += 4) + INSTANCE_WR(ctx, i/4, 0x00080008); + INSTANCE_WR(ctx, 0x85c/4, 0x00040000); + INSTANCE_WR(ctx, 0x860/4, 0x00010000); + for(i = 0x864; i< 0x874; i += 4) + INSTANCE_WR(ctx, i/4, 0x00040004); + INSTANCE_WR(ctx, 0x1f18/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f1c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f20/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f28/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f2c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f30/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f38/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f3c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f40/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f48/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f4c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f50/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f58/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f5c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f60/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f68/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f6c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f70/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f78/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f7c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f80/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f88/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f8c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f90/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f98/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f9c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fa0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fa8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fb0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fb8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fbc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fc0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fc8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fcc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fd0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fd8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fdc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fe0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fe8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ff0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1ff8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ffc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2000/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2008/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x200c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2010/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2018/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x201c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2020/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2028/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x202c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2030/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2038/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x203c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2040/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2048/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x204c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2050/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2058/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x205c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2060/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2068/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x206c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2070/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2078/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x207c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2080/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2088/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x208c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2090/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2098/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x209c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2100/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2108/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x210c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2110/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2118/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x211c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2120/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2128/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x212c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2130/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2138/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x213c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2140/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2148/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x214c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2150/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2158/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x215c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2160/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2168/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x216c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2170/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2178/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x217c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2180/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2188/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x218c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2190/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2198/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x219c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2200/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2208/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x220c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2210/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2218/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x221c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2220/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2228/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x222c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2230/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2238/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x223c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2240/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2248/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x224c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2250/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2258/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x225c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2260/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2268/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x226c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2270/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2278/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x227c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2280/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2288/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x228c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2290/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2298/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x229c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2300/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2308/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x230c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2310/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2318/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x231c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2320/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2328/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x232c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2330/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2338/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x233c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2340/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2348/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x234c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2350/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2358/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x235c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2360/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2368/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x236c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2370/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2378/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x237c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2380/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2388/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x238c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2390/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2398/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x239c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2400/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2408/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x240c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2410/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2418/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x241c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2420/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2428/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x242c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2430/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2438/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x243c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2440/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2448/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x244c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2450/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2458/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x245c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2460/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2468/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x246c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2470/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2478/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x247c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2480/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2488/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x248c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2490/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2498/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x249c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2500/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2508/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x250c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2510/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2518/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x251c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2520/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2528/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x252c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2530/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2538/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x253c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2540/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2548/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x254c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2550/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2558/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x255c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2560/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2568/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x256c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2570/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2578/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x257c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2580/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2588/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x258c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2590/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2598/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x259c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2600/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2608/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x260c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2610/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2618/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x261c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2620/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2628/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x262c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2630/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2638/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x263c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2640/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2648/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x264c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2650/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2658/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x265c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2660/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2668/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x266c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2670/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2678/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x267c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2680/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2688/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x268c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2690/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2698/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x269c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2700/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2708/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x270c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2710/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2718/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x271c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2720/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2728/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x272c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2730/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2738/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x273c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2740/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2748/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x274c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2750/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2758/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x275c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2760/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2768/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x276c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2770/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2778/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x277c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2780/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2788/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x278c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2790/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2798/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x279c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2800/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2808/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x280c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2810/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2818/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x281c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2820/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2828/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x282c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2830/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2838/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x283c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2840/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2848/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x284c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2850/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2858/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x285c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2860/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2868/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x286c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2870/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2878/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x287c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2880/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2888/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x288c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2890/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2898/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x289c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2900/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2908/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x290c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2910/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2918/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x291c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2920/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2928/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x292c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2930/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2938/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x293c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2940/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2948/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x294c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2950/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2958/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x295c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2960/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2968/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x296c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2970/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2978/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x297c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2980/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2988/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x298c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2990/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2998/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x299c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29a0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29a8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29ac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29b0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29b8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29bc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29c0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29c8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29cc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29d0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29d8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29dc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29e0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29e8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29ec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29f0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29f8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29fc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a00/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a08/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a0c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a10/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a18/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a1c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a20/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a28/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a2c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a30/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a38/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a3c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a40/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a48/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a4c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a50/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a58/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a5c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a60/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a68/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a6c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a70/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a78/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a7c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a80/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a88/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a8c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a90/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a98/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a9c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2aa0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2aa8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2aac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ab0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ab8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2abc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ac0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ac8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2acc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ad0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ad8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2adc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ae0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ae8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2aec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2af0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2af8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2afc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b00/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b08/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b0c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b10/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b18/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b1c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b20/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b28/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b2c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b30/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b38/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b3c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b40/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b48/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b4c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b50/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b58/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b5c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b60/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b68/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b6c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b70/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b78/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b7c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b80/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b88/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b8c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b90/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b98/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b9c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ba0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ba8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2bb0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bb8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bbc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2bc0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bc8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bcc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2bd0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bd8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bdc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2be0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2be8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2bf0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bf8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bfc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c00/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c08/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c0c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c10/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c18/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c1c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c20/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c28/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c2c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c30/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c38/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c3c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c40/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c48/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c4c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c50/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c58/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c5c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c60/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c68/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c6c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c70/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c78/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c7c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c80/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c88/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c8c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c90/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c98/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c9c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ca0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ca8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2cb0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cb8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cbc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2cc0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cc8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ccc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2cd0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cd8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cdc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ce0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ce8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2cf0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cf8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cfc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d00/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d08/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d0c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d10/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d18/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d1c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d20/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d28/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d2c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d30/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d38/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d3c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d40/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d48/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d4c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d50/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d58/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d5c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d60/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d68/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d6c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d70/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d78/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d7c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d80/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d88/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d8c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d90/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d98/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d9c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2da0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2da8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2dac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2db0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2db8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2dbc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2dc0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2dc8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2dcc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2dd0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2dd8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ddc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2de0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2de8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2dec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2df0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2df8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2dfc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e00/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e08/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e0c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e10/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e18/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e1c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e20/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e28/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e2c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e30/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e38/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e3c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e40/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e48/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e4c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e50/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e58/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e5c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e60/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e68/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e6c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e70/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e78/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e7c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e80/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e88/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e8c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e90/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e98/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e9c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ea0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ea8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2eac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2eb0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2eb8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ebc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ec0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ec8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ecc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ed0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ed8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2edc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ee0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ee8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2eec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ef0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ef8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2efc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f00/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f08/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f0c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f10/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f18/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f1c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f20/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f28/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f2c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f30/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f38/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f3c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f40/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f48/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f4c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f50/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f58/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f5c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f60/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f68/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f6c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f70/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f78/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f7c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f80/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f88/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f8c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f90/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f98/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f9c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fa0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fa8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fac/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fb0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fb8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fbc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fc0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fc8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fcc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fd0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fd8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fdc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fe0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fe8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fec/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ff0/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ff8/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ffc/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3000/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3008/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x300c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3010/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3018/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x301c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3020/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3028/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x302c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3030/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3038/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x303c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3040/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3048/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x304c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3050/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3058/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x305c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3060/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3068/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x306c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3070/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3078/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x307c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3080/4, 0x000c001b); + INSTANCE_WR(ctx, 0x3088/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x308c/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3090/4, 0x000c001b); + for(i = 0x30b8; i< 0x30c8; i += 4) + INSTANCE_WR(ctx, i/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x344c/4, 0x3f800000); + INSTANCE_WR(ctx, 0x3808/4, 0x3f800000); + INSTANCE_WR(ctx, 0x381c/4, 0x3f800000); + INSTANCE_WR(ctx, 0x3848/4, 0x40000000); + INSTANCE_WR(ctx, 0x384c/4, 0x3f800000); + INSTANCE_WR(ctx, 0x3850/4, 0x3f000000); + INSTANCE_WR(ctx, 0x3858/4, 0x40000000); + INSTANCE_WR(ctx, 0x385c/4, 0x3f800000); + INSTANCE_WR(ctx, 0x3864/4, 0xbf800000); + INSTANCE_WR(ctx, 0x386c/4, 0xbf800000); +} + +static void nv34_graph_context_init(struct drm_device *dev, + struct nouveau_gpuobj *ctx) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; + + INSTANCE_WR(ctx, 0x40c/4, 0x01000101); + INSTANCE_WR(ctx, 0x420/4, 0x00000111); + INSTANCE_WR(ctx, 0x424/4, 0x00000060); + INSTANCE_WR(ctx, 0x440/4, 0x00000080); + INSTANCE_WR(ctx, 0x444/4, 0xffff0000); + INSTANCE_WR(ctx, 0x448/4, 0x00000001); + INSTANCE_WR(ctx, 0x45c/4, 0x44400000); + INSTANCE_WR(ctx, 0x480/4, 0xffff0000); + for(i = 0x4d4; i< 0x4dc; i += 4) + INSTANCE_WR(ctx, i/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x4e0/4, 0x00011100); + for(i = 0x4fc; i< 0x53c; i += 4) + INSTANCE_WR(ctx, i/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x544/4, 0x4b7fffff); + INSTANCE_WR(ctx, 0x57c/4, 0x00000080); + INSTANCE_WR(ctx, 0x580/4, 0x30201000); + INSTANCE_WR(ctx, 0x584/4, 0x70605040); + INSTANCE_WR(ctx, 0x588/4, 0xb8a89888); + INSTANCE_WR(ctx, 0x58c/4, 0xf8e8d8c8); + INSTANCE_WR(ctx, 0x5a0/4, 0xb0000000); + for(i = 0x5f0; i< 0x630; i += 4) + INSTANCE_WR(ctx, i/4, 0x00010588); + for(i = 0x630; i< 0x670; i += 4) + INSTANCE_WR(ctx, i/4, 0x00030303); + for(i = 0x6b0; i< 0x6f0; i += 4) + INSTANCE_WR(ctx, i/4, 0x0008aae4); + for(i = 0x6f0; i< 0x730; i += 4) + INSTANCE_WR(ctx, i/4, 0x01012000); + for(i = 0x730; i< 0x770; i += 4) + INSTANCE_WR(ctx, i/4, 0x00080008); + INSTANCE_WR(ctx, 0x850/4, 0x00040000); + INSTANCE_WR(ctx, 0x854/4, 0x00010000); + for(i = 0x858; i< 0x868; i += 4) + INSTANCE_WR(ctx, i/4, 0x00040004); + INSTANCE_WR(ctx, 0x15ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x15b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x15b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x15bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x15c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x15c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x15cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x15d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x15d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x15dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x15e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x15e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x15ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x15f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x15f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x15fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1600/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1604/4, 0x000c001b); + INSTANCE_WR(ctx, 0x160c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1610/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1614/4, 0x000c001b); + INSTANCE_WR(ctx, 0x161c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1620/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1624/4, 0x000c001b); + INSTANCE_WR(ctx, 0x162c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1630/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1634/4, 0x000c001b); + INSTANCE_WR(ctx, 0x163c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1640/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1644/4, 0x000c001b); + INSTANCE_WR(ctx, 0x164c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1650/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1654/4, 0x000c001b); + INSTANCE_WR(ctx, 0x165c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1660/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1664/4, 0x000c001b); + INSTANCE_WR(ctx, 0x166c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1670/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1674/4, 0x000c001b); + INSTANCE_WR(ctx, 0x167c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1680/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1684/4, 0x000c001b); + INSTANCE_WR(ctx, 0x168c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1690/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1694/4, 0x000c001b); + INSTANCE_WR(ctx, 0x169c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x16a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x16a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x16ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x16b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x16b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x16bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x16c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x16c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x16cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x16d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x16d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x16dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x16e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x16e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x16ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x16f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x16f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x16fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1700/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1704/4, 0x000c001b); + INSTANCE_WR(ctx, 0x170c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1710/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1714/4, 0x000c001b); + INSTANCE_WR(ctx, 0x171c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1720/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1724/4, 0x000c001b); + INSTANCE_WR(ctx, 0x172c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1730/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1734/4, 0x000c001b); + INSTANCE_WR(ctx, 0x173c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1740/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1744/4, 0x000c001b); + INSTANCE_WR(ctx, 0x174c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1750/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1754/4, 0x000c001b); + INSTANCE_WR(ctx, 0x175c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1760/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1764/4, 0x000c001b); + INSTANCE_WR(ctx, 0x176c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1770/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1774/4, 0x000c001b); + INSTANCE_WR(ctx, 0x177c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1780/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1784/4, 0x000c001b); + INSTANCE_WR(ctx, 0x178c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1790/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1794/4, 0x000c001b); + INSTANCE_WR(ctx, 0x179c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x17a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x17a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x17ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x17b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x17b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x17bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x17c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x17c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x17cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x17d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x17d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x17dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x17e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x17e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x17ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x17f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x17f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x17fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1800/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1804/4, 0x000c001b); + INSTANCE_WR(ctx, 0x180c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1810/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1814/4, 0x000c001b); + INSTANCE_WR(ctx, 0x181c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1820/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1824/4, 0x000c001b); + INSTANCE_WR(ctx, 0x182c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1830/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1834/4, 0x000c001b); + INSTANCE_WR(ctx, 0x183c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1840/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1844/4, 0x000c001b); + INSTANCE_WR(ctx, 0x184c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1850/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1854/4, 0x000c001b); + INSTANCE_WR(ctx, 0x185c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1860/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1864/4, 0x000c001b); + INSTANCE_WR(ctx, 0x186c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1870/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1874/4, 0x000c001b); + INSTANCE_WR(ctx, 0x187c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1880/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1884/4, 0x000c001b); + INSTANCE_WR(ctx, 0x188c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1890/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1894/4, 0x000c001b); + INSTANCE_WR(ctx, 0x189c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x18a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x18a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x18ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x18b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x18b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x18bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x18c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x18c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x18cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x18d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x18d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x18dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x18e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x18e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x18ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x18f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x18f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x18fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1900/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1904/4, 0x000c001b); + INSTANCE_WR(ctx, 0x190c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1910/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1914/4, 0x000c001b); + INSTANCE_WR(ctx, 0x191c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1920/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1924/4, 0x000c001b); + INSTANCE_WR(ctx, 0x192c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1930/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1934/4, 0x000c001b); + INSTANCE_WR(ctx, 0x193c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1940/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1944/4, 0x000c001b); + INSTANCE_WR(ctx, 0x194c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1950/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1954/4, 0x000c001b); + INSTANCE_WR(ctx, 0x195c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1960/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1964/4, 0x000c001b); + INSTANCE_WR(ctx, 0x196c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1970/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1974/4, 0x000c001b); + INSTANCE_WR(ctx, 0x197c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1980/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1984/4, 0x000c001b); + INSTANCE_WR(ctx, 0x198c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1990/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1994/4, 0x000c001b); + INSTANCE_WR(ctx, 0x199c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x19a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x19a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x19ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x19b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x19b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x19bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x19c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x19c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x19cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x19d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x19d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x19dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x19e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x19e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x19ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x19f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x19f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x19fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1a90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1a94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1a9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1aa0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1aa4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1aac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ab0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ab4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1abc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ac0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ac4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1acc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ad0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ad4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1adc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ae0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ae4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1aec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1af0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1af4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1afc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1b90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1b94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1b9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ba0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ba4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1bac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1bb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1bb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1bbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1bc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1bc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1bcc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1bd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1bd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1bdc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1be0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1be4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1bec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1bf0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1bf4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1bfc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1c90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1c94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1c9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ca0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ca4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1cac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1cb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1cb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1cbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1cc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1cc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1ccc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1cd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1cd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1cdc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ce0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ce4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1cec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1cf0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1cf4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1cfc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1d90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1d94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1d9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1da0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1da4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1dac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1db0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1db4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1dbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1dc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1dc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1dcc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1dd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1dd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1ddc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1de0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1de4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1dec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1df0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1df4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1dfc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1e90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1e94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1e9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ea0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ea4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1eac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1eb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1eb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1ebc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ec0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ec4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1ecc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ed0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ed4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1edc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ee0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ee4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1eec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ef0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ef4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1efc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fa0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fa4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fcc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fdc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fe0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fe4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ff0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ff4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1ffc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2000/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2004/4, 0x000c001b); + INSTANCE_WR(ctx, 0x200c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2010/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2014/4, 0x000c001b); + INSTANCE_WR(ctx, 0x201c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2020/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2024/4, 0x000c001b); + INSTANCE_WR(ctx, 0x202c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2030/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2034/4, 0x000c001b); + INSTANCE_WR(ctx, 0x203c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2040/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2044/4, 0x000c001b); + INSTANCE_WR(ctx, 0x204c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2050/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2054/4, 0x000c001b); + INSTANCE_WR(ctx, 0x205c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2060/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2064/4, 0x000c001b); + INSTANCE_WR(ctx, 0x206c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2070/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2074/4, 0x000c001b); + INSTANCE_WR(ctx, 0x207c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2080/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2084/4, 0x000c001b); + INSTANCE_WR(ctx, 0x208c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2090/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2094/4, 0x000c001b); + INSTANCE_WR(ctx, 0x209c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2100/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2104/4, 0x000c001b); + INSTANCE_WR(ctx, 0x210c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2110/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2114/4, 0x000c001b); + INSTANCE_WR(ctx, 0x211c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2120/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2124/4, 0x000c001b); + INSTANCE_WR(ctx, 0x212c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2130/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2134/4, 0x000c001b); + INSTANCE_WR(ctx, 0x213c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2140/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2144/4, 0x000c001b); + INSTANCE_WR(ctx, 0x214c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2150/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2154/4, 0x000c001b); + INSTANCE_WR(ctx, 0x215c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2160/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2164/4, 0x000c001b); + INSTANCE_WR(ctx, 0x216c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2170/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2174/4, 0x000c001b); + INSTANCE_WR(ctx, 0x217c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2180/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2184/4, 0x000c001b); + INSTANCE_WR(ctx, 0x218c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2190/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2194/4, 0x000c001b); + INSTANCE_WR(ctx, 0x219c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2200/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2204/4, 0x000c001b); + INSTANCE_WR(ctx, 0x220c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2210/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2214/4, 0x000c001b); + INSTANCE_WR(ctx, 0x221c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2220/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2224/4, 0x000c001b); + INSTANCE_WR(ctx, 0x222c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2230/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2234/4, 0x000c001b); + INSTANCE_WR(ctx, 0x223c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2240/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2244/4, 0x000c001b); + INSTANCE_WR(ctx, 0x224c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2250/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2254/4, 0x000c001b); + INSTANCE_WR(ctx, 0x225c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2260/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2264/4, 0x000c001b); + INSTANCE_WR(ctx, 0x226c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2270/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2274/4, 0x000c001b); + INSTANCE_WR(ctx, 0x227c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2280/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2284/4, 0x000c001b); + INSTANCE_WR(ctx, 0x228c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2290/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2294/4, 0x000c001b); + INSTANCE_WR(ctx, 0x229c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2300/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2304/4, 0x000c001b); + INSTANCE_WR(ctx, 0x230c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2310/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2314/4, 0x000c001b); + INSTANCE_WR(ctx, 0x231c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2320/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2324/4, 0x000c001b); + INSTANCE_WR(ctx, 0x232c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2330/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2334/4, 0x000c001b); + INSTANCE_WR(ctx, 0x233c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2340/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2344/4, 0x000c001b); + INSTANCE_WR(ctx, 0x234c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2350/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2354/4, 0x000c001b); + INSTANCE_WR(ctx, 0x235c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2360/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2364/4, 0x000c001b); + INSTANCE_WR(ctx, 0x236c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2370/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2374/4, 0x000c001b); + INSTANCE_WR(ctx, 0x237c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2380/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2384/4, 0x000c001b); + INSTANCE_WR(ctx, 0x238c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2390/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2394/4, 0x000c001b); + INSTANCE_WR(ctx, 0x239c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2400/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2404/4, 0x000c001b); + INSTANCE_WR(ctx, 0x240c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2410/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2414/4, 0x000c001b); + INSTANCE_WR(ctx, 0x241c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2420/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2424/4, 0x000c001b); + INSTANCE_WR(ctx, 0x242c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2430/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2434/4, 0x000c001b); + INSTANCE_WR(ctx, 0x243c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2440/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2444/4, 0x000c001b); + INSTANCE_WR(ctx, 0x244c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2450/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2454/4, 0x000c001b); + INSTANCE_WR(ctx, 0x245c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2460/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2464/4, 0x000c001b); + INSTANCE_WR(ctx, 0x246c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2470/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2474/4, 0x000c001b); + INSTANCE_WR(ctx, 0x247c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2480/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2484/4, 0x000c001b); + INSTANCE_WR(ctx, 0x248c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2490/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2494/4, 0x000c001b); + INSTANCE_WR(ctx, 0x249c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2500/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2504/4, 0x000c001b); + INSTANCE_WR(ctx, 0x250c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2510/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2514/4, 0x000c001b); + INSTANCE_WR(ctx, 0x251c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2520/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2524/4, 0x000c001b); + INSTANCE_WR(ctx, 0x252c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2530/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2534/4, 0x000c001b); + INSTANCE_WR(ctx, 0x253c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2540/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2544/4, 0x000c001b); + INSTANCE_WR(ctx, 0x254c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2550/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2554/4, 0x000c001b); + INSTANCE_WR(ctx, 0x255c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2560/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2564/4, 0x000c001b); + INSTANCE_WR(ctx, 0x256c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2570/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2574/4, 0x000c001b); + INSTANCE_WR(ctx, 0x257c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2580/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2584/4, 0x000c001b); + INSTANCE_WR(ctx, 0x258c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2590/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2594/4, 0x000c001b); + INSTANCE_WR(ctx, 0x259c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2600/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2604/4, 0x000c001b); + INSTANCE_WR(ctx, 0x260c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2610/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2614/4, 0x000c001b); + INSTANCE_WR(ctx, 0x261c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2620/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2624/4, 0x000c001b); + INSTANCE_WR(ctx, 0x262c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2630/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2634/4, 0x000c001b); + INSTANCE_WR(ctx, 0x263c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2640/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2644/4, 0x000c001b); + INSTANCE_WR(ctx, 0x264c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2650/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2654/4, 0x000c001b); + INSTANCE_WR(ctx, 0x265c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2660/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2664/4, 0x000c001b); + INSTANCE_WR(ctx, 0x266c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2670/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2674/4, 0x000c001b); + INSTANCE_WR(ctx, 0x267c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2680/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2684/4, 0x000c001b); + INSTANCE_WR(ctx, 0x268c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2690/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2694/4, 0x000c001b); + INSTANCE_WR(ctx, 0x269c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2700/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2704/4, 0x000c001b); + INSTANCE_WR(ctx, 0x270c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2710/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2714/4, 0x000c001b); + INSTANCE_WR(ctx, 0x271c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2720/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2724/4, 0x000c001b); + for(i = 0x274c; i< 0x275c; i += 4) + INSTANCE_WR(ctx, i/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x2ae0/4, 0x3f800000); + INSTANCE_WR(ctx, 0x2e9c/4, 0x3f800000); + INSTANCE_WR(ctx, 0x2eb0/4, 0x3f800000); + INSTANCE_WR(ctx, 0x2edc/4, 0x40000000); + INSTANCE_WR(ctx, 0x2ee0/4, 0x3f800000); + INSTANCE_WR(ctx, 0x2ee4/4, 0x3f000000); + INSTANCE_WR(ctx, 0x2eec/4, 0x40000000); + INSTANCE_WR(ctx, 0x2ef0/4, 0x3f800000); + INSTANCE_WR(ctx, 0x2ef8/4, 0xbf800000); + INSTANCE_WR(ctx, 0x2f00/4, 0xbf800000); +} + +static void nv35_36_graph_context_init(struct drm_device *dev, + struct nouveau_gpuobj *ctx) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; + + INSTANCE_WR(ctx, 0x40c/4, 0x00000101); + INSTANCE_WR(ctx, 0x420/4, 0x00000111); + INSTANCE_WR(ctx, 0x424/4, 0x00000060); + INSTANCE_WR(ctx, 0x440/4, 0x00000080); + INSTANCE_WR(ctx, 0x444/4, 0xffff0000); + INSTANCE_WR(ctx, 0x448/4, 0x00000001); + INSTANCE_WR(ctx, 0x45c/4, 0x44400000); + INSTANCE_WR(ctx, 0x488/4, 0xffff0000); + for(i = 0x4dc; i< 0x4e4; i += 4) + INSTANCE_WR(ctx, i/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x4e8/4, 0x00011100); + for(i = 0x504; i< 0x544; i += 4) + INSTANCE_WR(ctx, i/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x54c/4, 0x4b7fffff); + INSTANCE_WR(ctx, 0x588/4, 0x00000080); + INSTANCE_WR(ctx, 0x58c/4, 0x30201000); + INSTANCE_WR(ctx, 0x590/4, 0x70605040); + INSTANCE_WR(ctx, 0x594/4, 0xb8a89888); + INSTANCE_WR(ctx, 0x598/4, 0xf8e8d8c8); + INSTANCE_WR(ctx, 0x5ac/4, 0xb0000000); + for(i = 0x604; i< 0x644; i += 4) + INSTANCE_WR(ctx, i/4, 0x00010588); + for(i = 0x644; i< 0x684; i += 4) + INSTANCE_WR(ctx, i/4, 0x00030303); + for(i = 0x6c4; i< 0x704; i += 4) + INSTANCE_WR(ctx, i/4, 0x0008aae4); + for(i = 0x704; i< 0x744; i += 4) + INSTANCE_WR(ctx, i/4, 0x01012000); + for(i = 0x744; i< 0x784; i += 4) + INSTANCE_WR(ctx, i/4, 0x00080008); + INSTANCE_WR(ctx, 0x860/4, 0x00040000); + INSTANCE_WR(ctx, 0x864/4, 0x00010000); + for(i = 0x868; i< 0x878; i += 4) + INSTANCE_WR(ctx, i/4, 0x00040004); + INSTANCE_WR(ctx, 0x1f1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1f90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1f94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1f9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fa0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fa4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fcc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fdc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1fe0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1fe4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1fec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x1ff0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x1ff4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x1ffc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2000/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2004/4, 0x000c001b); + INSTANCE_WR(ctx, 0x200c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2010/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2014/4, 0x000c001b); + INSTANCE_WR(ctx, 0x201c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2020/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2024/4, 0x000c001b); + INSTANCE_WR(ctx, 0x202c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2030/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2034/4, 0x000c001b); + INSTANCE_WR(ctx, 0x203c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2040/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2044/4, 0x000c001b); + INSTANCE_WR(ctx, 0x204c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2050/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2054/4, 0x000c001b); + INSTANCE_WR(ctx, 0x205c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2060/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2064/4, 0x000c001b); + INSTANCE_WR(ctx, 0x206c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2070/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2074/4, 0x000c001b); + INSTANCE_WR(ctx, 0x207c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2080/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2084/4, 0x000c001b); + INSTANCE_WR(ctx, 0x208c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2090/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2094/4, 0x000c001b); + INSTANCE_WR(ctx, 0x209c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x20f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x20f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x20fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2100/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2104/4, 0x000c001b); + INSTANCE_WR(ctx, 0x210c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2110/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2114/4, 0x000c001b); + INSTANCE_WR(ctx, 0x211c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2120/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2124/4, 0x000c001b); + INSTANCE_WR(ctx, 0x212c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2130/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2134/4, 0x000c001b); + INSTANCE_WR(ctx, 0x213c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2140/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2144/4, 0x000c001b); + INSTANCE_WR(ctx, 0x214c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2150/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2154/4, 0x000c001b); + INSTANCE_WR(ctx, 0x215c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2160/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2164/4, 0x000c001b); + INSTANCE_WR(ctx, 0x216c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2170/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2174/4, 0x000c001b); + INSTANCE_WR(ctx, 0x217c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2180/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2184/4, 0x000c001b); + INSTANCE_WR(ctx, 0x218c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2190/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2194/4, 0x000c001b); + INSTANCE_WR(ctx, 0x219c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x21f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x21f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x21fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2200/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2204/4, 0x000c001b); + INSTANCE_WR(ctx, 0x220c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2210/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2214/4, 0x000c001b); + INSTANCE_WR(ctx, 0x221c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2220/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2224/4, 0x000c001b); + INSTANCE_WR(ctx, 0x222c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2230/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2234/4, 0x000c001b); + INSTANCE_WR(ctx, 0x223c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2240/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2244/4, 0x000c001b); + INSTANCE_WR(ctx, 0x224c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2250/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2254/4, 0x000c001b); + INSTANCE_WR(ctx, 0x225c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2260/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2264/4, 0x000c001b); + INSTANCE_WR(ctx, 0x226c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2270/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2274/4, 0x000c001b); + INSTANCE_WR(ctx, 0x227c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2280/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2284/4, 0x000c001b); + INSTANCE_WR(ctx, 0x228c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2290/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2294/4, 0x000c001b); + INSTANCE_WR(ctx, 0x229c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x22f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x22f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x22fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2300/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2304/4, 0x000c001b); + INSTANCE_WR(ctx, 0x230c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2310/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2314/4, 0x000c001b); + INSTANCE_WR(ctx, 0x231c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2320/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2324/4, 0x000c001b); + INSTANCE_WR(ctx, 0x232c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2330/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2334/4, 0x000c001b); + INSTANCE_WR(ctx, 0x233c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2340/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2344/4, 0x000c001b); + INSTANCE_WR(ctx, 0x234c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2350/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2354/4, 0x000c001b); + INSTANCE_WR(ctx, 0x235c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2360/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2364/4, 0x000c001b); + INSTANCE_WR(ctx, 0x236c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2370/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2374/4, 0x000c001b); + INSTANCE_WR(ctx, 0x237c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2380/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2384/4, 0x000c001b); + INSTANCE_WR(ctx, 0x238c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2390/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2394/4, 0x000c001b); + INSTANCE_WR(ctx, 0x239c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x23f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x23f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x23fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2400/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2404/4, 0x000c001b); + INSTANCE_WR(ctx, 0x240c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2410/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2414/4, 0x000c001b); + INSTANCE_WR(ctx, 0x241c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2420/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2424/4, 0x000c001b); + INSTANCE_WR(ctx, 0x242c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2430/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2434/4, 0x000c001b); + INSTANCE_WR(ctx, 0x243c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2440/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2444/4, 0x000c001b); + INSTANCE_WR(ctx, 0x244c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2450/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2454/4, 0x000c001b); + INSTANCE_WR(ctx, 0x245c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2460/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2464/4, 0x000c001b); + INSTANCE_WR(ctx, 0x246c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2470/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2474/4, 0x000c001b); + INSTANCE_WR(ctx, 0x247c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2480/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2484/4, 0x000c001b); + INSTANCE_WR(ctx, 0x248c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2490/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2494/4, 0x000c001b); + INSTANCE_WR(ctx, 0x249c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x24f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x24f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x24fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2500/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2504/4, 0x000c001b); + INSTANCE_WR(ctx, 0x250c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2510/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2514/4, 0x000c001b); + INSTANCE_WR(ctx, 0x251c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2520/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2524/4, 0x000c001b); + INSTANCE_WR(ctx, 0x252c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2530/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2534/4, 0x000c001b); + INSTANCE_WR(ctx, 0x253c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2540/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2544/4, 0x000c001b); + INSTANCE_WR(ctx, 0x254c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2550/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2554/4, 0x000c001b); + INSTANCE_WR(ctx, 0x255c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2560/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2564/4, 0x000c001b); + INSTANCE_WR(ctx, 0x256c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2570/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2574/4, 0x000c001b); + INSTANCE_WR(ctx, 0x257c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2580/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2584/4, 0x000c001b); + INSTANCE_WR(ctx, 0x258c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2590/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2594/4, 0x000c001b); + INSTANCE_WR(ctx, 0x259c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x25f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x25f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x25fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2600/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2604/4, 0x000c001b); + INSTANCE_WR(ctx, 0x260c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2610/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2614/4, 0x000c001b); + INSTANCE_WR(ctx, 0x261c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2620/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2624/4, 0x000c001b); + INSTANCE_WR(ctx, 0x262c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2630/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2634/4, 0x000c001b); + INSTANCE_WR(ctx, 0x263c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2640/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2644/4, 0x000c001b); + INSTANCE_WR(ctx, 0x264c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2650/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2654/4, 0x000c001b); + INSTANCE_WR(ctx, 0x265c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2660/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2664/4, 0x000c001b); + INSTANCE_WR(ctx, 0x266c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2670/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2674/4, 0x000c001b); + INSTANCE_WR(ctx, 0x267c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2680/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2684/4, 0x000c001b); + INSTANCE_WR(ctx, 0x268c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2690/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2694/4, 0x000c001b); + INSTANCE_WR(ctx, 0x269c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x26f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x26f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x26fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2700/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2704/4, 0x000c001b); + INSTANCE_WR(ctx, 0x270c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2710/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2714/4, 0x000c001b); + INSTANCE_WR(ctx, 0x271c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2720/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2724/4, 0x000c001b); + INSTANCE_WR(ctx, 0x272c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2730/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2734/4, 0x000c001b); + INSTANCE_WR(ctx, 0x273c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2740/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2744/4, 0x000c001b); + INSTANCE_WR(ctx, 0x274c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2750/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2754/4, 0x000c001b); + INSTANCE_WR(ctx, 0x275c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2760/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2764/4, 0x000c001b); + INSTANCE_WR(ctx, 0x276c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2770/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2774/4, 0x000c001b); + INSTANCE_WR(ctx, 0x277c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2780/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2784/4, 0x000c001b); + INSTANCE_WR(ctx, 0x278c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2790/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2794/4, 0x000c001b); + INSTANCE_WR(ctx, 0x279c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x27f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x27f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x27fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2800/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2804/4, 0x000c001b); + INSTANCE_WR(ctx, 0x280c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2810/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2814/4, 0x000c001b); + INSTANCE_WR(ctx, 0x281c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2820/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2824/4, 0x000c001b); + INSTANCE_WR(ctx, 0x282c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2830/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2834/4, 0x000c001b); + INSTANCE_WR(ctx, 0x283c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2840/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2844/4, 0x000c001b); + INSTANCE_WR(ctx, 0x284c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2850/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2854/4, 0x000c001b); + INSTANCE_WR(ctx, 0x285c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2860/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2864/4, 0x000c001b); + INSTANCE_WR(ctx, 0x286c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2870/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2874/4, 0x000c001b); + INSTANCE_WR(ctx, 0x287c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2880/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2884/4, 0x000c001b); + INSTANCE_WR(ctx, 0x288c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2890/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2894/4, 0x000c001b); + INSTANCE_WR(ctx, 0x289c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x28f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x28f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x28fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2900/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2904/4, 0x000c001b); + INSTANCE_WR(ctx, 0x290c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2910/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2914/4, 0x000c001b); + INSTANCE_WR(ctx, 0x291c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2920/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2924/4, 0x000c001b); + INSTANCE_WR(ctx, 0x292c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2930/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2934/4, 0x000c001b); + INSTANCE_WR(ctx, 0x293c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2940/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2944/4, 0x000c001b); + INSTANCE_WR(ctx, 0x294c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2950/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2954/4, 0x000c001b); + INSTANCE_WR(ctx, 0x295c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2960/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2964/4, 0x000c001b); + INSTANCE_WR(ctx, 0x296c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2970/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2974/4, 0x000c001b); + INSTANCE_WR(ctx, 0x297c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2980/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2984/4, 0x000c001b); + INSTANCE_WR(ctx, 0x298c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2990/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2994/4, 0x000c001b); + INSTANCE_WR(ctx, 0x299c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29a0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29a4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29ac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29b0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29b4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29bc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29c0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29c4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29cc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29d0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29d4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29dc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29e0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29e4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29ec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x29f0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x29f4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x29fc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2a90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2a94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2a9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2aa0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2aa4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2aac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ab0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ab4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2abc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ac0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ac4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2acc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ad0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ad4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2adc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ae0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ae4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2aec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2af0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2af4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2afc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2b90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2b94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2b9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ba0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ba4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2bb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2bc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bcc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2bd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bdc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2be0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2be4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2bf0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2bf4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2bfc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2c90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2c94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2c9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ca0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ca4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2cb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2cc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ccc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2cd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cdc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ce0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ce4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2cf0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2cf4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2cfc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2d90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2d94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2d9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2da0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2da4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2dac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2db0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2db4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2dbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2dc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2dc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2dcc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2dd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2dd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ddc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2de0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2de4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2dec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2df0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2df4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2dfc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2e90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2e94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2e9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ea0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ea4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2eac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2eb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2eb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ebc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ec0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ec4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ecc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ed0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ed4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2edc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ee0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ee4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2eec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ef0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ef4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2efc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f00/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f04/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f0c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f10/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f14/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f1c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f20/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f24/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f2c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f30/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f34/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f3c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f40/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f44/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f4c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f50/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f54/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f5c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f60/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f64/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f6c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f70/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f74/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f7c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f80/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f84/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f8c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2f90/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2f94/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2f9c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fa0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fa4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fac/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fb0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fb4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fbc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fc0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fc4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fcc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fd0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fd4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fdc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2fe0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2fe4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2fec/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x2ff0/4, 0x0436086c); + INSTANCE_WR(ctx, 0x2ff4/4, 0x000c001b); + INSTANCE_WR(ctx, 0x2ffc/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3000/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3004/4, 0x000c001b); + INSTANCE_WR(ctx, 0x300c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3010/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3014/4, 0x000c001b); + INSTANCE_WR(ctx, 0x301c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3020/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3024/4, 0x000c001b); + INSTANCE_WR(ctx, 0x302c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3030/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3034/4, 0x000c001b); + INSTANCE_WR(ctx, 0x303c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3040/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3044/4, 0x000c001b); + INSTANCE_WR(ctx, 0x304c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3050/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3054/4, 0x000c001b); + INSTANCE_WR(ctx, 0x305c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3060/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3064/4, 0x000c001b); + INSTANCE_WR(ctx, 0x306c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3070/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3074/4, 0x000c001b); + INSTANCE_WR(ctx, 0x307c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3080/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3084/4, 0x000c001b); + INSTANCE_WR(ctx, 0x308c/4, 0x10700ff9); + INSTANCE_WR(ctx, 0x3090/4, 0x0436086c); + INSTANCE_WR(ctx, 0x3094/4, 0x000c001b); + for(i = 0x30bc; i< 0x30cc; i += 4) + INSTANCE_WR(ctx, i/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x3450/4, 0x3f800000); + INSTANCE_WR(ctx, 0x380c/4, 0x3f800000); + INSTANCE_WR(ctx, 0x3820/4, 0x3f800000); + INSTANCE_WR(ctx, 0x384c/4, 0x40000000); + INSTANCE_WR(ctx, 0x3850/4, 0x3f800000); + INSTANCE_WR(ctx, 0x3854/4, 0x3f000000); + INSTANCE_WR(ctx, 0x385c/4, 0x40000000); + INSTANCE_WR(ctx, 0x3860/4, 0x3f800000); + INSTANCE_WR(ctx, 0x3868/4, 0xbf800000); + INSTANCE_WR(ctx, 0x3870/4, 0xbf800000); +} + +int nv20_graph_create_context(struct nouveau_channel *chan) +{ + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *); + unsigned int ctx_size; + int ret; + + switch (dev_priv->chipset) { + case 0x25: + case 0x28: + ctx_size = NV25_GRCTX_SIZE; + ctx_init = nv25_graph_context_init; + break; + case 0x30: + case 0x31: + ctx_size = NV30_31_GRCTX_SIZE; + ctx_init = nv30_31_graph_context_init; + break; + case 0x34: + ctx_size = NV34_GRCTX_SIZE; + ctx_init = nv34_graph_context_init; + break; + case 0x35: + case 0x36: + ctx_size = NV35_36_GRCTX_SIZE; + ctx_init = nv35_36_graph_context_init; + break; + default: + ctx_size = 0; + ctx_init = nv35_36_graph_context_init; + DRM_ERROR("Please contact the devs if you want your NV%x" + " card to work\n", dev_priv->chipset); + return -ENOSYS; + break; + } + + if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16, + NVOBJ_FLAG_ZERO_ALLOC, + &chan->ramin_grctx))) + return ret; + + /* Initialise default context values */ + ctx_init(dev, chan->ramin_grctx->gpuobj); + + /* nv20: INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); */ + INSTANCE_WR(chan->ramin_grctx->gpuobj, 0x28/4, (chan->id<<24)|0x1); + /* CTX_USER */ + + INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, + chan->ramin_grctx->instance >> 4); + + return 0; +} + +void nv20_graph_destroy_context(struct nouveau_channel *chan) +{ + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + + if (chan->ramin_grctx) + nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); + + INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0); +} + +static int +nouveau_graph_wait_idle(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int tv = 1000; + + while (tv--) { + if (NV_READ(NV04_PGRAPH_STATUS) == 0) + break; + } + + if (NV_READ(NV04_PGRAPH_STATUS)) { + DRM_ERROR("timeout!\n"); + return -EBUSY; + } + return 0; +} + +int nv20_graph_load_context(struct nouveau_channel *chan) +{ + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + uint32_t inst; + + if (!chan->ramin_grctx) + return -EINVAL; + inst = chan->ramin_grctx->instance >> 4; + + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER, + NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD); + + return nouveau_graph_wait_idle(dev); +} + +int nv20_graph_save_context(struct nouveau_channel *chan) +{ + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + uint32_t inst; + + if (!chan->ramin_grctx) + return -EINVAL; + inst = chan->ramin_grctx->instance >> 4; + + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER, + NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE); + + return nouveau_graph_wait_idle(dev); +} + +static void nv20_graph_rdi(struct drm_device *dev) { + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; + + NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000); + for (i = 0; i < 32; i++) + NV_WRITE(NV10_PGRAPH_RDI_DATA, 0); + + nouveau_wait_for_idle(dev); +} + +int nv20_graph_init(struct drm_device *dev) { + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; + uint32_t tmp, vramsz; + int ret, i; + + NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & + ~NV_PMC_ENABLE_PGRAPH); + NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | + NV_PMC_ENABLE_PGRAPH); + + /* Create Context Pointer Table */ + dev_priv->ctx_table_size = 32 * 4; + if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, + dev_priv->ctx_table_size, 16, + NVOBJ_FLAG_ZERO_ALLOC, + &dev_priv->ctx_table))) + return ret; + + NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, + dev_priv->ctx_table->instance >> 4); + + //XXX need to be done and save/restore for each fifo ??? + nv20_graph_rdi(dev); + + NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); + NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); + + NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); + NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); + NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700); + NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xF20E0435); /* 0x4 = auto ctx switch */ + NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000); + NV_WRITE(0x40009C , 0x00000040); + + if (dev_priv->chipset >= 0x25) { + NV_WRITE(0x400890, 0x00080000); + NV_WRITE(0x400610, 0x304B1FB6); + NV_WRITE(0x400B80, 0x18B82880); + NV_WRITE(0x400B84, 0x44000000); + NV_WRITE(0x400098, 0x40000080); + NV_WRITE(0x400B88, 0x000000ff); + } else { + NV_WRITE(0x400880, 0x00080000); + NV_WRITE(0x400094, 0x00000005); + NV_WRITE(0x400B80, 0x45CAA208); + NV_WRITE(0x400B84, 0x24000000); + NV_WRITE(0x400098, 0x00000040); + NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00038); + NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030); + NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E10038); + NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030); + } + + /* copy tile info from PFB */ + for (i=0; idev_private; + + nouveau_gpuobj_ref_del(dev, &dev_priv->ctx_table); +} + +int nv30_graph_init(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + uint32_t vramsz, tmp; + int ret, i; + + NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & + ~NV_PMC_ENABLE_PGRAPH); + NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | + NV_PMC_ENABLE_PGRAPH); + + /* Create Context Pointer Table */ + dev_priv->ctx_table_size = 32 * 4; + if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, + dev_priv->ctx_table_size, 16, + NVOBJ_FLAG_ZERO_ALLOC, + &dev_priv->ctx_table))) + return ret; + + NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, + dev_priv->ctx_table->instance >> 4); + + NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); + NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); + + NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); + NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); + NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x401287c0); + NV_WRITE(0x400890, 0x01b463ff); + NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xf3de0471); + NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000); + NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); + NV_WRITE(0x400B80, 0x1003d888); + NV_WRITE(0x400098, 0x00000000); + NV_WRITE(0x40009C, 0x0005ad00); + NV_WRITE(0x400B88, 0x62ff00ff); // suspiciously like PGRAPH_DEBUG_2 + NV_WRITE(0x4000a0, 0x00000000); + NV_WRITE(0x4000a4, 0x00000008); + NV_WRITE(0x4008a8, 0xb784a400); + NV_WRITE(0x400ba0, 0x002f8685); + NV_WRITE(0x400ba4, 0x00231f3f); + NV_WRITE(0x4008a4, 0x40000020); + NV_WRITE(0x400B84, 0x0c000000); + NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x62ff0f7f); + NV_WRITE(0x4000c0, 0x00000016); + NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, 0x000014e4); + + /* copy tile info from PFB */ + for (i=0; idev_private; - int i; -/* -write32 #1 block at +0x00740a7c NV_PRAMIN.GRCTX0+0x35c of 173 (0xad) elements: -+0x00740a7c: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740a9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740abc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740adc: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000 -+0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740b3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 - -+0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740bbc: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000 -+0x00740bdc: 00000000 00000000 00000000 00000080 ffff0000 00000001 00000000 00000000 -+0x00740bfc: 00000000 00000000 44400000 00000000 00000000 00000000 00000000 00000000 -+0x00740c1c: 4b800000 00000000 00000000 00000000 00000000 00030303 00030303 00030303 -+0x00740c3c: 00030303 00000000 00000000 00000000 00000000 00080000 00080000 00080000 -+0x00740c5c: 00080000 00000000 00000000 01012000 01012000 01012000 01012000 000105b8 - -+0x00740c7c: 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008 00000000 -+0x00740c9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 07ff0000 -+0x00740cbc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 -+0x00740cdc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 00000000 -+0x00740cfc: 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740d1c: 00000000 00000000 00000000 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x35c/4)+0, 0xffff0000); - INSTANCE_WR(ctx, (0x35c/4)+25, 0x0fff0000); - INSTANCE_WR(ctx, (0x35c/4)+26, 0x0fff0000); - INSTANCE_WR(ctx, (0x35c/4)+80, 0x00000101); - INSTANCE_WR(ctx, (0x35c/4)+85, 0x00000111); - INSTANCE_WR(ctx, (0x35c/4)+91, 0x00000080); - INSTANCE_WR(ctx, (0x35c/4)+92, 0xffff0000); - INSTANCE_WR(ctx, (0x35c/4)+93, 0x00000001); - INSTANCE_WR(ctx, (0x35c/4)+98, 0x44400000); - INSTANCE_WR(ctx, (0x35c/4)+104, 0x4b800000); - INSTANCE_WR(ctx, (0x35c/4)+109, 0x00030303); - INSTANCE_WR(ctx, (0x35c/4)+110, 0x00030303); - INSTANCE_WR(ctx, (0x35c/4)+111, 0x00030303); - INSTANCE_WR(ctx, (0x35c/4)+112, 0x00030303); - INSTANCE_WR(ctx, (0x35c/4)+117, 0x00080000); - INSTANCE_WR(ctx, (0x35c/4)+118, 0x00080000); - INSTANCE_WR(ctx, (0x35c/4)+119, 0x00080000); - INSTANCE_WR(ctx, (0x35c/4)+120, 0x00080000); - INSTANCE_WR(ctx, (0x35c/4)+123, 0x01012000); - INSTANCE_WR(ctx, (0x35c/4)+124, 0x01012000); - INSTANCE_WR(ctx, (0x35c/4)+125, 0x01012000); - INSTANCE_WR(ctx, (0x35c/4)+126, 0x01012000); - INSTANCE_WR(ctx, (0x35c/4)+127, 0x000105b8); - INSTANCE_WR(ctx, (0x35c/4)+128, 0x000105b8); - INSTANCE_WR(ctx, (0x35c/4)+129, 0x000105b8); - INSTANCE_WR(ctx, (0x35c/4)+130, 0x000105b8); - INSTANCE_WR(ctx, (0x35c/4)+131, 0x00080008); - INSTANCE_WR(ctx, (0x35c/4)+132, 0x00080008); - INSTANCE_WR(ctx, (0x35c/4)+133, 0x00080008); - INSTANCE_WR(ctx, (0x35c/4)+134, 0x00080008); - for (i=0; i<16; ++i) - INSTANCE_WR(ctx, (0x35c/4)+143+i, 0x07ff0000); - INSTANCE_WR(ctx, (0x35c/4)+161, 0x4b7ffff); - -/* -write32 #1 block at +0x00740d34 NV_PRAMIN.GRCTX0+0x614 of 3136 (0xc40) elements: -+0x00740d34: 00000000 00000000 00000000 00000080 30201000 70605040 b0a09080 f0e0d0c0 -+0x00740d54: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00740d74: 00000000 00000000 00000000 00000000 00000001 00000000 00004000 00000000 -+0x00740d94: 00000000 00000001 00000000 00040000 00010000 00000000 00000000 00000000 -+0x00740db4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -... -+0x00742214: 00000000 00000000 00000000 00000000 10700ff9 0436086c 000c001b 00000000 -+0x00742234: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -+0x00742254: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -+0x00742274: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -... -+0x00742a34: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -+0x00742a54: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -+0x00742a74: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 -+0x00742a94: 10700ff9 0436086c 000c001b 00000000 00000000 00000000 00000000 00000000 -+0x00742ab4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -+0x00742ad4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x614/4)+3, 0x00000080); - INSTANCE_WR(ctx, (0x614/4)+4, 0x30201000); - INSTANCE_WR(ctx, (0x614/4)+5, 0x70605040); - INSTANCE_WR(ctx, (0x614/4)+6, 0xb0a09080); - INSTANCE_WR(ctx, (0x614/4)+7, 0xf0e0d0c0); - INSTANCE_WR(ctx, (0x614/4)+20, 0x00000001); - INSTANCE_WR(ctx, (0x614/4)+22, 0x00004000); - INSTANCE_WR(ctx, (0x614/4)+25, 0x00000001); - INSTANCE_WR(ctx, (0x614/4)+27, 0x00040000); - INSTANCE_WR(ctx, (0x614/4)+28, 0x00010000); - for (i=0; i<0x880; i+=4) { - INSTANCE_WR(ctx, (0x1b04/4)+i+0, 0x10700ff9); - INSTANCE_WR(ctx, (0x1b04/4)+i+1, 0x0436086c); - INSTANCE_WR(ctx, (0x1b04/4)+i+2, 0x000c001b); - INSTANCE_WR(ctx, (0x1b04/4)+i+3, 0x00000000); - } - -/* -write32 #1 block at +0x00742e24 NV_PRAMIN.GRCTX0+0x2704 of 4 (0x4) elements: -+0x00742e24: 3f800000 00000000 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x2704/4), 0x3f800000); - -/* -write32 #1 block at +0x00742e64 NV_PRAMIN.GRCTX0+0x2744 of 12 (0xc) elements: -+0x00742e64: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000 -+0x00742e84: 00000000 bf800000 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x2744/4)+0, 0x40000000); - INSTANCE_WR(ctx, (0x2744/4)+1, 0x3f800000); - INSTANCE_WR(ctx, (0x2744/4)+2, 0x3f000000); - INSTANCE_WR(ctx, (0x2744/4)+4, 0x40000000); - INSTANCE_WR(ctx, (0x2744/4)+5, 0x3f800000); - INSTANCE_WR(ctx, (0x2744/4)+7, 0xbf800000); - INSTANCE_WR(ctx, (0x2744/4)+9, 0xbf800000); - -/* -write32 #1 block at +0x00742e34 NV_PRAMIN.GRCTX0+0x2714 of 4 (0x4) elements: -+0x00742e34: 00000000 3f800000 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x2714/4)+1, 0x3f800000); - -/* -write32 #1 block at +0x00742e94 NV_PRAMIN.GRCTX0+0x2774 of 4 (0x4) elements: -+0x00742e94: 00000000 00000000 00000000 00000000 -write32 #1 block at +0x00743804 NV_PRAMIN.GRCTX0+0x30e4 of 4 (0x4) elements: -+0x00743804: 00000000 00000000 00000000 00000000 -write32 #1 block at +0x007437a4 NV_PRAMIN.GRCTX0+0x3084 of 8 (0x8) elements: -+0x007437a4: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x3084/4)+2, 0x000fe000); - -/* -write32 #1 block at +0x007437d4 NV_PRAMIN.GRCTX0+0x30b4 of 4 (0x4) elements: -+0x007437d4: 00000000 00000000 00000000 00000000 -write32 #1 block at +0x00743824 NV_PRAMIN.GRCTX0+0x3104 of 4 (0x4) elements: -+0x00743824: 00000000 000003f8 00000000 00000000 -*/ - INSTANCE_WR(ctx, (0x3104/4)+1, 0x000003f8); - -/* write32 #1 NV_PRAMIN.GRCTX0+0x3468 <- 0x002fe000 */ - INSTANCE_WR(ctx, 0x3468/4, 0x002fe000); - -/* -write32 #1 block at +0x00743ba4 NV_PRAMIN.GRCTX0+0x3484 of 8 (0x8) elements: -+0x00743ba4: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c -*/ - for (i=0; i<8; ++i) - INSTANCE_WR(ctx, (0x3484/4)+i, 0x001c527c); -} - -static void nv30_31_graph_context_init(struct drm_device *dev, - struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - INSTANCE_WR(ctx, 0x410/4, 0x00000101); - INSTANCE_WR(ctx, 0x424/4, 0x00000111); - INSTANCE_WR(ctx, 0x428/4, 0x00000060); - INSTANCE_WR(ctx, 0x444/4, 0x00000080); - INSTANCE_WR(ctx, 0x448/4, 0xffff0000); - INSTANCE_WR(ctx, 0x44c/4, 0x00000001); - INSTANCE_WR(ctx, 0x460/4, 0x44400000); - INSTANCE_WR(ctx, 0x48c/4, 0xffff0000); - for(i = 0x4e0; i< 0x4e8; i += 4) - INSTANCE_WR(ctx, i/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x4ec/4, 0x00011100); - for(i = 0x508; i< 0x548; i += 4) - INSTANCE_WR(ctx, i/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x550/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x58c/4, 0x00000080); - INSTANCE_WR(ctx, 0x590/4, 0x30201000); - INSTANCE_WR(ctx, 0x594/4, 0x70605040); - INSTANCE_WR(ctx, 0x598/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x59c/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x5b0/4, 0xb0000000); - for(i = 0x600; i< 0x640; i += 4) - INSTANCE_WR(ctx, i/4, 0x00010588); - for(i = 0x640; i< 0x680; i += 4) - INSTANCE_WR(ctx, i/4, 0x00030303); - for(i = 0x6c0; i< 0x700; i += 4) - INSTANCE_WR(ctx, i/4, 0x0008aae4); - for(i = 0x700; i< 0x740; i += 4) - INSTANCE_WR(ctx, i/4, 0x01012000); - for(i = 0x740; i< 0x780; i += 4) - INSTANCE_WR(ctx, i/4, 0x00080008); - INSTANCE_WR(ctx, 0x85c/4, 0x00040000); - INSTANCE_WR(ctx, 0x860/4, 0x00010000); - for(i = 0x864; i< 0x874; i += 4) - INSTANCE_WR(ctx, i/4, 0x00040004); - INSTANCE_WR(ctx, 0x1f18/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f1c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f20/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f28/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f2c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f30/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f38/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f3c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f40/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f48/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f4c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f50/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f58/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f5c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f60/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f68/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f6c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f70/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f78/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f7c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f80/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f88/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f8c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f90/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f98/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f9c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fa0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fa8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fb0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fb8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fbc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fc0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fc8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fcc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fd0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fd8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fdc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fe0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fe8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ff0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1ff8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ffc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2000/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2008/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x200c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2010/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2018/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x201c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2020/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2028/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x202c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2030/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2038/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x203c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2040/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2048/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x204c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2050/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2058/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x205c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2060/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2068/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x206c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2070/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2078/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x207c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2080/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2088/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x208c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2090/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2098/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x209c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2100/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2108/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x210c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2110/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2118/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x211c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2120/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2128/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x212c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2130/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2138/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x213c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2140/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2148/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x214c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2150/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2158/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x215c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2160/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2168/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x216c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2170/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2178/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x217c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2180/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2188/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x218c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2190/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2198/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x219c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2200/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2208/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x220c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2210/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2218/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x221c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2220/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2228/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x222c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2230/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2238/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x223c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2240/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2248/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x224c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2250/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2258/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x225c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2260/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2268/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x226c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2270/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2278/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x227c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2280/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2288/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x228c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2290/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2298/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x229c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2300/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2308/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x230c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2310/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2318/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x231c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2320/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2328/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x232c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2330/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2338/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x233c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2340/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2348/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x234c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2350/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2358/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x235c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2360/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2368/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x236c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2370/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2378/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x237c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2380/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2388/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x238c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2390/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2398/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x239c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2400/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2408/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x240c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2410/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2418/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x241c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2420/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2428/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x242c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2430/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2438/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x243c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2440/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2448/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x244c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2450/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2458/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x245c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2460/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2468/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x246c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2470/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2478/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x247c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2480/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2488/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x248c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2490/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2498/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x249c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2500/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2508/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x250c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2510/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2518/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x251c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2520/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2528/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x252c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2530/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2538/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x253c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2540/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2548/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x254c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2550/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2558/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x255c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2560/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2568/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x256c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2570/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2578/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x257c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2580/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2588/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x258c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2590/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2598/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x259c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2600/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2608/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x260c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2610/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2618/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x261c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2620/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2628/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x262c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2630/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2638/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x263c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2640/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2648/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x264c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2650/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2658/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x265c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2660/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2668/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x266c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2670/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2678/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x267c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2680/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2688/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x268c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2690/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2698/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x269c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2700/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2708/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x270c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2710/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2718/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x271c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2720/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2728/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x272c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2730/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2738/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x273c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2740/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2748/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x274c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2750/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2758/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x275c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2760/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2768/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x276c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2770/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2778/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x277c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2780/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2788/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x278c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2790/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2798/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x279c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2800/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2808/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x280c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2810/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2818/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x281c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2820/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2828/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x282c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2830/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2838/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x283c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2840/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2848/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x284c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2850/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2858/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x285c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2860/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2868/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x286c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2870/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2878/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x287c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2880/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2888/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x288c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2890/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2898/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x289c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2900/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2908/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x290c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2910/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2918/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x291c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2920/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2928/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x292c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2930/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2938/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x293c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2940/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2948/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x294c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2950/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2958/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x295c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2960/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2968/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x296c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2970/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2978/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x297c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2980/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2988/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x298c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2990/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2998/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x299c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a00/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a08/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a0c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a10/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a18/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a1c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a20/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a28/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a2c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a30/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a38/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a3c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a40/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a48/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a4c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a50/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a58/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a5c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a60/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a68/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a6c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a70/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a78/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a7c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a80/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a88/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a8c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a90/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a98/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a9c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2aa0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2aa8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2aac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ab0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ab8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2abc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ac0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ac8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2acc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ad0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ad8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2adc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ae0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ae8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2aec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2af0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2af8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2afc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b00/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b08/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b0c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b10/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b18/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b1c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b20/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b28/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b2c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b30/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b38/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b3c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b40/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b48/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b4c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b50/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b58/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b5c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b60/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b68/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b6c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b70/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b78/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b7c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b80/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b88/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b8c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b90/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b98/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b9c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ba0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ba8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2bb0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bb8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bbc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2bc0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bc8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bcc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2bd0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bd8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bdc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2be0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2be8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2bf0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bf8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bfc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c00/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c08/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c0c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c10/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c18/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c1c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c20/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c28/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c2c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c30/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c38/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c3c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c40/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c48/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c4c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c50/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c58/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c5c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c60/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c68/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c6c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c70/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c78/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c7c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c80/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c88/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c8c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c90/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c98/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c9c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ca0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ca8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2cb0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cb8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cbc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2cc0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cc8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ccc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2cd0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cd8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cdc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ce0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ce8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2cf0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cf8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cfc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d00/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d08/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d0c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d10/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d18/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d1c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d20/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d28/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d2c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d30/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d38/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d3c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d40/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d48/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d4c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d50/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d58/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d5c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d60/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d68/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d6c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d70/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d78/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d7c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d80/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d88/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d8c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d90/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d98/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d9c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2da0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2da8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2dac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2db0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2db8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2dbc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2dc0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2dc8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2dcc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2dd0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2dd8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ddc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2de0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2de8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2dec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2df0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2df8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2dfc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e00/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e08/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e0c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e10/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e18/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e1c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e20/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e28/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e2c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e30/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e38/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e3c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e40/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e48/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e4c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e50/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e58/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e5c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e60/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e68/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e6c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e70/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e78/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e7c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e80/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e88/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e8c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e90/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e98/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e9c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ea0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ea8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2eac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2eb0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2eb8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ebc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ec0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ec8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ecc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ed0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ed8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2edc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ee0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ee8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2eec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ef0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ef8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2efc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f00/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f08/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f0c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f10/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f18/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f1c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f20/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f28/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f2c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f30/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f38/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f3c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f40/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f48/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f4c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f50/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f58/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f5c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f60/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f68/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f6c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f70/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f78/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f7c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f80/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f88/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f8c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f90/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f98/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f9c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fa0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fa8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fb0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fb8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fbc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fc0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fc8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fcc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fd0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fd8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fdc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fe0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fe8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ff0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ff8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ffc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3000/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3008/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x300c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3010/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3018/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x301c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3020/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3028/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x302c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3030/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3038/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x303c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3040/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3048/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x304c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3050/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3058/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x305c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3060/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3068/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x306c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3070/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3078/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x307c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3080/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3088/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x308c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3090/4, 0x000c001b); - for(i = 0x30b8; i< 0x30c8; i += 4) - INSTANCE_WR(ctx, i/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x344c/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3808/4, 0x3f800000); - INSTANCE_WR(ctx, 0x381c/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3848/4, 0x40000000); - INSTANCE_WR(ctx, 0x384c/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3850/4, 0x3f000000); - INSTANCE_WR(ctx, 0x3858/4, 0x40000000); - INSTANCE_WR(ctx, 0x385c/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3864/4, 0xbf800000); - INSTANCE_WR(ctx, 0x386c/4, 0xbf800000); -} - -static void nv34_graph_context_init(struct drm_device *dev, - struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - INSTANCE_WR(ctx, 0x40c/4, 0x01000101); - INSTANCE_WR(ctx, 0x420/4, 0x00000111); - INSTANCE_WR(ctx, 0x424/4, 0x00000060); - INSTANCE_WR(ctx, 0x440/4, 0x00000080); - INSTANCE_WR(ctx, 0x444/4, 0xffff0000); - INSTANCE_WR(ctx, 0x448/4, 0x00000001); - INSTANCE_WR(ctx, 0x45c/4, 0x44400000); - INSTANCE_WR(ctx, 0x480/4, 0xffff0000); - for(i = 0x4d4; i< 0x4dc; i += 4) - INSTANCE_WR(ctx, i/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x4e0/4, 0x00011100); - for(i = 0x4fc; i< 0x53c; i += 4) - INSTANCE_WR(ctx, i/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x544/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x57c/4, 0x00000080); - INSTANCE_WR(ctx, 0x580/4, 0x30201000); - INSTANCE_WR(ctx, 0x584/4, 0x70605040); - INSTANCE_WR(ctx, 0x588/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x58c/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x5a0/4, 0xb0000000); - for(i = 0x5f0; i< 0x630; i += 4) - INSTANCE_WR(ctx, i/4, 0x00010588); - for(i = 0x630; i< 0x670; i += 4) - INSTANCE_WR(ctx, i/4, 0x00030303); - for(i = 0x6b0; i< 0x6f0; i += 4) - INSTANCE_WR(ctx, i/4, 0x0008aae4); - for(i = 0x6f0; i< 0x730; i += 4) - INSTANCE_WR(ctx, i/4, 0x01012000); - for(i = 0x730; i< 0x770; i += 4) - INSTANCE_WR(ctx, i/4, 0x00080008); - INSTANCE_WR(ctx, 0x850/4, 0x00040000); - INSTANCE_WR(ctx, 0x854/4, 0x00010000); - for(i = 0x858; i< 0x868; i += 4) - INSTANCE_WR(ctx, i/4, 0x00040004); - INSTANCE_WR(ctx, 0x15ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x15b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x15b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x15bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x15c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x15c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x15cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x15d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x15d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x15dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x15e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x15e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x15ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x15f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x15f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x15fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1600/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1604/4, 0x000c001b); - INSTANCE_WR(ctx, 0x160c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1610/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1614/4, 0x000c001b); - INSTANCE_WR(ctx, 0x161c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1620/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1624/4, 0x000c001b); - INSTANCE_WR(ctx, 0x162c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1630/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1634/4, 0x000c001b); - INSTANCE_WR(ctx, 0x163c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1640/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1644/4, 0x000c001b); - INSTANCE_WR(ctx, 0x164c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1650/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1654/4, 0x000c001b); - INSTANCE_WR(ctx, 0x165c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1660/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1664/4, 0x000c001b); - INSTANCE_WR(ctx, 0x166c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1670/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1674/4, 0x000c001b); - INSTANCE_WR(ctx, 0x167c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1680/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1684/4, 0x000c001b); - INSTANCE_WR(ctx, 0x168c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1690/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1694/4, 0x000c001b); - INSTANCE_WR(ctx, 0x169c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x16a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x16a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x16ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x16b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x16b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x16bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x16c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x16c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x16cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x16d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x16d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x16dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x16e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x16e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x16ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x16f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x16f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x16fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1700/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1704/4, 0x000c001b); - INSTANCE_WR(ctx, 0x170c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1710/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1714/4, 0x000c001b); - INSTANCE_WR(ctx, 0x171c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1720/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1724/4, 0x000c001b); - INSTANCE_WR(ctx, 0x172c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1730/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1734/4, 0x000c001b); - INSTANCE_WR(ctx, 0x173c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1740/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1744/4, 0x000c001b); - INSTANCE_WR(ctx, 0x174c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1750/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1754/4, 0x000c001b); - INSTANCE_WR(ctx, 0x175c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1760/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1764/4, 0x000c001b); - INSTANCE_WR(ctx, 0x176c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1770/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1774/4, 0x000c001b); - INSTANCE_WR(ctx, 0x177c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1780/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1784/4, 0x000c001b); - INSTANCE_WR(ctx, 0x178c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1790/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1794/4, 0x000c001b); - INSTANCE_WR(ctx, 0x179c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x17a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x17a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x17ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x17b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x17b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x17bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x17c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x17c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x17cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x17d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x17d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x17dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x17e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x17e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x17ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x17f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x17f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x17fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1800/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1804/4, 0x000c001b); - INSTANCE_WR(ctx, 0x180c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1810/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1814/4, 0x000c001b); - INSTANCE_WR(ctx, 0x181c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1820/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1824/4, 0x000c001b); - INSTANCE_WR(ctx, 0x182c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1830/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1834/4, 0x000c001b); - INSTANCE_WR(ctx, 0x183c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1840/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1844/4, 0x000c001b); - INSTANCE_WR(ctx, 0x184c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1850/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1854/4, 0x000c001b); - INSTANCE_WR(ctx, 0x185c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1860/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1864/4, 0x000c001b); - INSTANCE_WR(ctx, 0x186c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1870/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1874/4, 0x000c001b); - INSTANCE_WR(ctx, 0x187c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1880/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1884/4, 0x000c001b); - INSTANCE_WR(ctx, 0x188c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1890/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1894/4, 0x000c001b); - INSTANCE_WR(ctx, 0x189c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x18a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x18a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x18ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x18b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x18b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x18bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x18c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x18c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x18cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x18d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x18d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x18dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x18e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x18e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x18ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x18f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x18f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x18fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1900/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1904/4, 0x000c001b); - INSTANCE_WR(ctx, 0x190c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1910/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1914/4, 0x000c001b); - INSTANCE_WR(ctx, 0x191c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1920/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1924/4, 0x000c001b); - INSTANCE_WR(ctx, 0x192c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1930/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1934/4, 0x000c001b); - INSTANCE_WR(ctx, 0x193c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1940/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1944/4, 0x000c001b); - INSTANCE_WR(ctx, 0x194c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1950/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1954/4, 0x000c001b); - INSTANCE_WR(ctx, 0x195c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1960/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1964/4, 0x000c001b); - INSTANCE_WR(ctx, 0x196c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1970/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1974/4, 0x000c001b); - INSTANCE_WR(ctx, 0x197c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1980/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1984/4, 0x000c001b); - INSTANCE_WR(ctx, 0x198c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1990/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1994/4, 0x000c001b); - INSTANCE_WR(ctx, 0x199c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x19a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x19a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x19ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x19b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x19b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x19bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x19c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x19c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x19cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x19d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x19d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x19dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x19e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x19e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x19ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x19f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x19f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x19fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1aa0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1aa4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1aac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ab0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ab4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1abc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ac0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ac4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1acc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ad0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ad4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1adc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ae0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ae4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1aec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1af0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1af4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1afc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ba0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ba4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1bac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1bb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1bb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1bbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1bc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1bc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1bcc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1bd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1bd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1bdc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1be0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1be4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1bec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1bf0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1bf4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1bfc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ca0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ca4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1cac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1cb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1cb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1cbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1cc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1cc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1ccc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1cd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1cd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1cdc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ce0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ce4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1cec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1cf0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1cf4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1cfc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1da0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1da4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1dac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1db0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1db4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1dbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1dc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1dc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1dcc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1dd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1dd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1ddc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1de0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1de4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1dec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1df0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1df4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1dfc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ea0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ea4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1eac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1eb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1eb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1ebc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ec0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ec4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1ecc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ed0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ed4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1edc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ee0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ee4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1eec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ef0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ef4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1efc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fa0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fa4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fcc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fdc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fe0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fe4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ff0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ff4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1ffc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2000/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2004/4, 0x000c001b); - INSTANCE_WR(ctx, 0x200c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2010/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2014/4, 0x000c001b); - INSTANCE_WR(ctx, 0x201c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2020/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2024/4, 0x000c001b); - INSTANCE_WR(ctx, 0x202c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2030/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2034/4, 0x000c001b); - INSTANCE_WR(ctx, 0x203c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2040/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2044/4, 0x000c001b); - INSTANCE_WR(ctx, 0x204c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2050/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2054/4, 0x000c001b); - INSTANCE_WR(ctx, 0x205c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2060/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2064/4, 0x000c001b); - INSTANCE_WR(ctx, 0x206c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2070/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2074/4, 0x000c001b); - INSTANCE_WR(ctx, 0x207c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2080/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2084/4, 0x000c001b); - INSTANCE_WR(ctx, 0x208c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2090/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2094/4, 0x000c001b); - INSTANCE_WR(ctx, 0x209c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2100/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2104/4, 0x000c001b); - INSTANCE_WR(ctx, 0x210c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2110/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2114/4, 0x000c001b); - INSTANCE_WR(ctx, 0x211c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2120/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2124/4, 0x000c001b); - INSTANCE_WR(ctx, 0x212c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2130/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2134/4, 0x000c001b); - INSTANCE_WR(ctx, 0x213c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2140/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2144/4, 0x000c001b); - INSTANCE_WR(ctx, 0x214c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2150/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2154/4, 0x000c001b); - INSTANCE_WR(ctx, 0x215c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2160/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2164/4, 0x000c001b); - INSTANCE_WR(ctx, 0x216c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2170/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2174/4, 0x000c001b); - INSTANCE_WR(ctx, 0x217c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2180/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2184/4, 0x000c001b); - INSTANCE_WR(ctx, 0x218c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2190/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2194/4, 0x000c001b); - INSTANCE_WR(ctx, 0x219c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2200/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2204/4, 0x000c001b); - INSTANCE_WR(ctx, 0x220c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2210/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2214/4, 0x000c001b); - INSTANCE_WR(ctx, 0x221c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2220/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2224/4, 0x000c001b); - INSTANCE_WR(ctx, 0x222c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2230/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2234/4, 0x000c001b); - INSTANCE_WR(ctx, 0x223c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2240/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2244/4, 0x000c001b); - INSTANCE_WR(ctx, 0x224c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2250/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2254/4, 0x000c001b); - INSTANCE_WR(ctx, 0x225c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2260/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2264/4, 0x000c001b); - INSTANCE_WR(ctx, 0x226c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2270/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2274/4, 0x000c001b); - INSTANCE_WR(ctx, 0x227c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2280/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2284/4, 0x000c001b); - INSTANCE_WR(ctx, 0x228c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2290/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2294/4, 0x000c001b); - INSTANCE_WR(ctx, 0x229c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2300/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2304/4, 0x000c001b); - INSTANCE_WR(ctx, 0x230c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2310/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2314/4, 0x000c001b); - INSTANCE_WR(ctx, 0x231c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2320/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2324/4, 0x000c001b); - INSTANCE_WR(ctx, 0x232c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2330/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2334/4, 0x000c001b); - INSTANCE_WR(ctx, 0x233c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2340/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2344/4, 0x000c001b); - INSTANCE_WR(ctx, 0x234c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2350/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2354/4, 0x000c001b); - INSTANCE_WR(ctx, 0x235c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2360/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2364/4, 0x000c001b); - INSTANCE_WR(ctx, 0x236c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2370/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2374/4, 0x000c001b); - INSTANCE_WR(ctx, 0x237c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2380/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2384/4, 0x000c001b); - INSTANCE_WR(ctx, 0x238c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2390/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2394/4, 0x000c001b); - INSTANCE_WR(ctx, 0x239c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2400/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2404/4, 0x000c001b); - INSTANCE_WR(ctx, 0x240c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2410/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2414/4, 0x000c001b); - INSTANCE_WR(ctx, 0x241c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2420/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2424/4, 0x000c001b); - INSTANCE_WR(ctx, 0x242c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2430/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2434/4, 0x000c001b); - INSTANCE_WR(ctx, 0x243c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2440/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2444/4, 0x000c001b); - INSTANCE_WR(ctx, 0x244c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2450/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2454/4, 0x000c001b); - INSTANCE_WR(ctx, 0x245c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2460/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2464/4, 0x000c001b); - INSTANCE_WR(ctx, 0x246c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2470/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2474/4, 0x000c001b); - INSTANCE_WR(ctx, 0x247c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2480/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2484/4, 0x000c001b); - INSTANCE_WR(ctx, 0x248c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2490/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2494/4, 0x000c001b); - INSTANCE_WR(ctx, 0x249c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2500/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2504/4, 0x000c001b); - INSTANCE_WR(ctx, 0x250c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2510/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2514/4, 0x000c001b); - INSTANCE_WR(ctx, 0x251c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2520/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2524/4, 0x000c001b); - INSTANCE_WR(ctx, 0x252c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2530/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2534/4, 0x000c001b); - INSTANCE_WR(ctx, 0x253c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2540/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2544/4, 0x000c001b); - INSTANCE_WR(ctx, 0x254c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2550/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2554/4, 0x000c001b); - INSTANCE_WR(ctx, 0x255c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2560/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2564/4, 0x000c001b); - INSTANCE_WR(ctx, 0x256c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2570/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2574/4, 0x000c001b); - INSTANCE_WR(ctx, 0x257c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2580/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2584/4, 0x000c001b); - INSTANCE_WR(ctx, 0x258c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2590/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2594/4, 0x000c001b); - INSTANCE_WR(ctx, 0x259c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2600/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2604/4, 0x000c001b); - INSTANCE_WR(ctx, 0x260c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2610/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2614/4, 0x000c001b); - INSTANCE_WR(ctx, 0x261c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2620/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2624/4, 0x000c001b); - INSTANCE_WR(ctx, 0x262c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2630/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2634/4, 0x000c001b); - INSTANCE_WR(ctx, 0x263c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2640/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2644/4, 0x000c001b); - INSTANCE_WR(ctx, 0x264c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2650/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2654/4, 0x000c001b); - INSTANCE_WR(ctx, 0x265c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2660/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2664/4, 0x000c001b); - INSTANCE_WR(ctx, 0x266c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2670/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2674/4, 0x000c001b); - INSTANCE_WR(ctx, 0x267c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2680/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2684/4, 0x000c001b); - INSTANCE_WR(ctx, 0x268c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2690/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2694/4, 0x000c001b); - INSTANCE_WR(ctx, 0x269c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2700/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2704/4, 0x000c001b); - INSTANCE_WR(ctx, 0x270c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2710/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2714/4, 0x000c001b); - INSTANCE_WR(ctx, 0x271c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2720/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2724/4, 0x000c001b); - for(i = 0x274c; i< 0x275c; i += 4) - INSTANCE_WR(ctx, i/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x2ae0/4, 0x3f800000); - INSTANCE_WR(ctx, 0x2e9c/4, 0x3f800000); - INSTANCE_WR(ctx, 0x2eb0/4, 0x3f800000); - INSTANCE_WR(ctx, 0x2edc/4, 0x40000000); - INSTANCE_WR(ctx, 0x2ee0/4, 0x3f800000); - INSTANCE_WR(ctx, 0x2ee4/4, 0x3f000000); - INSTANCE_WR(ctx, 0x2eec/4, 0x40000000); - INSTANCE_WR(ctx, 0x2ef0/4, 0x3f800000); - INSTANCE_WR(ctx, 0x2ef8/4, 0xbf800000); - INSTANCE_WR(ctx, 0x2f00/4, 0xbf800000); -} - -static void nv35_36_graph_context_init(struct drm_device *dev, - struct nouveau_gpuobj *ctx) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - INSTANCE_WR(ctx, 0x40c/4, 0x00000101); - INSTANCE_WR(ctx, 0x420/4, 0x00000111); - INSTANCE_WR(ctx, 0x424/4, 0x00000060); - INSTANCE_WR(ctx, 0x440/4, 0x00000080); - INSTANCE_WR(ctx, 0x444/4, 0xffff0000); - INSTANCE_WR(ctx, 0x448/4, 0x00000001); - INSTANCE_WR(ctx, 0x45c/4, 0x44400000); - INSTANCE_WR(ctx, 0x488/4, 0xffff0000); - for(i = 0x4dc; i< 0x4e4; i += 4) - INSTANCE_WR(ctx, i/4, 0x0fff0000); - INSTANCE_WR(ctx, 0x4e8/4, 0x00011100); - for(i = 0x504; i< 0x544; i += 4) - INSTANCE_WR(ctx, i/4, 0x07ff0000); - INSTANCE_WR(ctx, 0x54c/4, 0x4b7fffff); - INSTANCE_WR(ctx, 0x588/4, 0x00000080); - INSTANCE_WR(ctx, 0x58c/4, 0x30201000); - INSTANCE_WR(ctx, 0x590/4, 0x70605040); - INSTANCE_WR(ctx, 0x594/4, 0xb8a89888); - INSTANCE_WR(ctx, 0x598/4, 0xf8e8d8c8); - INSTANCE_WR(ctx, 0x5ac/4, 0xb0000000); - for(i = 0x604; i< 0x644; i += 4) - INSTANCE_WR(ctx, i/4, 0x00010588); - for(i = 0x644; i< 0x684; i += 4) - INSTANCE_WR(ctx, i/4, 0x00030303); - for(i = 0x6c4; i< 0x704; i += 4) - INSTANCE_WR(ctx, i/4, 0x0008aae4); - for(i = 0x704; i< 0x744; i += 4) - INSTANCE_WR(ctx, i/4, 0x01012000); - for(i = 0x744; i< 0x784; i += 4) - INSTANCE_WR(ctx, i/4, 0x00080008); - INSTANCE_WR(ctx, 0x860/4, 0x00040000); - INSTANCE_WR(ctx, 0x864/4, 0x00010000); - for(i = 0x868; i< 0x878; i += 4) - INSTANCE_WR(ctx, i/4, 0x00040004); - INSTANCE_WR(ctx, 0x1f1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fa0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fa4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fcc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fdc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fe0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fe4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ff0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ff4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1ffc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2000/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2004/4, 0x000c001b); - INSTANCE_WR(ctx, 0x200c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2010/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2014/4, 0x000c001b); - INSTANCE_WR(ctx, 0x201c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2020/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2024/4, 0x000c001b); - INSTANCE_WR(ctx, 0x202c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2030/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2034/4, 0x000c001b); - INSTANCE_WR(ctx, 0x203c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2040/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2044/4, 0x000c001b); - INSTANCE_WR(ctx, 0x204c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2050/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2054/4, 0x000c001b); - INSTANCE_WR(ctx, 0x205c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2060/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2064/4, 0x000c001b); - INSTANCE_WR(ctx, 0x206c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2070/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2074/4, 0x000c001b); - INSTANCE_WR(ctx, 0x207c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2080/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2084/4, 0x000c001b); - INSTANCE_WR(ctx, 0x208c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2090/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2094/4, 0x000c001b); - INSTANCE_WR(ctx, 0x209c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2100/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2104/4, 0x000c001b); - INSTANCE_WR(ctx, 0x210c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2110/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2114/4, 0x000c001b); - INSTANCE_WR(ctx, 0x211c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2120/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2124/4, 0x000c001b); - INSTANCE_WR(ctx, 0x212c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2130/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2134/4, 0x000c001b); - INSTANCE_WR(ctx, 0x213c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2140/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2144/4, 0x000c001b); - INSTANCE_WR(ctx, 0x214c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2150/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2154/4, 0x000c001b); - INSTANCE_WR(ctx, 0x215c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2160/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2164/4, 0x000c001b); - INSTANCE_WR(ctx, 0x216c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2170/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2174/4, 0x000c001b); - INSTANCE_WR(ctx, 0x217c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2180/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2184/4, 0x000c001b); - INSTANCE_WR(ctx, 0x218c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2190/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2194/4, 0x000c001b); - INSTANCE_WR(ctx, 0x219c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2200/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2204/4, 0x000c001b); - INSTANCE_WR(ctx, 0x220c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2210/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2214/4, 0x000c001b); - INSTANCE_WR(ctx, 0x221c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2220/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2224/4, 0x000c001b); - INSTANCE_WR(ctx, 0x222c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2230/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2234/4, 0x000c001b); - INSTANCE_WR(ctx, 0x223c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2240/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2244/4, 0x000c001b); - INSTANCE_WR(ctx, 0x224c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2250/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2254/4, 0x000c001b); - INSTANCE_WR(ctx, 0x225c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2260/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2264/4, 0x000c001b); - INSTANCE_WR(ctx, 0x226c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2270/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2274/4, 0x000c001b); - INSTANCE_WR(ctx, 0x227c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2280/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2284/4, 0x000c001b); - INSTANCE_WR(ctx, 0x228c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2290/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2294/4, 0x000c001b); - INSTANCE_WR(ctx, 0x229c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2300/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2304/4, 0x000c001b); - INSTANCE_WR(ctx, 0x230c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2310/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2314/4, 0x000c001b); - INSTANCE_WR(ctx, 0x231c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2320/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2324/4, 0x000c001b); - INSTANCE_WR(ctx, 0x232c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2330/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2334/4, 0x000c001b); - INSTANCE_WR(ctx, 0x233c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2340/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2344/4, 0x000c001b); - INSTANCE_WR(ctx, 0x234c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2350/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2354/4, 0x000c001b); - INSTANCE_WR(ctx, 0x235c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2360/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2364/4, 0x000c001b); - INSTANCE_WR(ctx, 0x236c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2370/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2374/4, 0x000c001b); - INSTANCE_WR(ctx, 0x237c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2380/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2384/4, 0x000c001b); - INSTANCE_WR(ctx, 0x238c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2390/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2394/4, 0x000c001b); - INSTANCE_WR(ctx, 0x239c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2400/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2404/4, 0x000c001b); - INSTANCE_WR(ctx, 0x240c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2410/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2414/4, 0x000c001b); - INSTANCE_WR(ctx, 0x241c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2420/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2424/4, 0x000c001b); - INSTANCE_WR(ctx, 0x242c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2430/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2434/4, 0x000c001b); - INSTANCE_WR(ctx, 0x243c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2440/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2444/4, 0x000c001b); - INSTANCE_WR(ctx, 0x244c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2450/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2454/4, 0x000c001b); - INSTANCE_WR(ctx, 0x245c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2460/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2464/4, 0x000c001b); - INSTANCE_WR(ctx, 0x246c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2470/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2474/4, 0x000c001b); - INSTANCE_WR(ctx, 0x247c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2480/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2484/4, 0x000c001b); - INSTANCE_WR(ctx, 0x248c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2490/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2494/4, 0x000c001b); - INSTANCE_WR(ctx, 0x249c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2500/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2504/4, 0x000c001b); - INSTANCE_WR(ctx, 0x250c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2510/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2514/4, 0x000c001b); - INSTANCE_WR(ctx, 0x251c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2520/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2524/4, 0x000c001b); - INSTANCE_WR(ctx, 0x252c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2530/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2534/4, 0x000c001b); - INSTANCE_WR(ctx, 0x253c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2540/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2544/4, 0x000c001b); - INSTANCE_WR(ctx, 0x254c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2550/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2554/4, 0x000c001b); - INSTANCE_WR(ctx, 0x255c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2560/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2564/4, 0x000c001b); - INSTANCE_WR(ctx, 0x256c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2570/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2574/4, 0x000c001b); - INSTANCE_WR(ctx, 0x257c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2580/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2584/4, 0x000c001b); - INSTANCE_WR(ctx, 0x258c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2590/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2594/4, 0x000c001b); - INSTANCE_WR(ctx, 0x259c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2600/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2604/4, 0x000c001b); - INSTANCE_WR(ctx, 0x260c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2610/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2614/4, 0x000c001b); - INSTANCE_WR(ctx, 0x261c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2620/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2624/4, 0x000c001b); - INSTANCE_WR(ctx, 0x262c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2630/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2634/4, 0x000c001b); - INSTANCE_WR(ctx, 0x263c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2640/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2644/4, 0x000c001b); - INSTANCE_WR(ctx, 0x264c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2650/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2654/4, 0x000c001b); - INSTANCE_WR(ctx, 0x265c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2660/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2664/4, 0x000c001b); - INSTANCE_WR(ctx, 0x266c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2670/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2674/4, 0x000c001b); - INSTANCE_WR(ctx, 0x267c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2680/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2684/4, 0x000c001b); - INSTANCE_WR(ctx, 0x268c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2690/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2694/4, 0x000c001b); - INSTANCE_WR(ctx, 0x269c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2700/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2704/4, 0x000c001b); - INSTANCE_WR(ctx, 0x270c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2710/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2714/4, 0x000c001b); - INSTANCE_WR(ctx, 0x271c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2720/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2724/4, 0x000c001b); - INSTANCE_WR(ctx, 0x272c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2730/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2734/4, 0x000c001b); - INSTANCE_WR(ctx, 0x273c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2740/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2744/4, 0x000c001b); - INSTANCE_WR(ctx, 0x274c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2750/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2754/4, 0x000c001b); - INSTANCE_WR(ctx, 0x275c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2760/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2764/4, 0x000c001b); - INSTANCE_WR(ctx, 0x276c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2770/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2774/4, 0x000c001b); - INSTANCE_WR(ctx, 0x277c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2780/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2784/4, 0x000c001b); - INSTANCE_WR(ctx, 0x278c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2790/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2794/4, 0x000c001b); - INSTANCE_WR(ctx, 0x279c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2800/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2804/4, 0x000c001b); - INSTANCE_WR(ctx, 0x280c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2810/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2814/4, 0x000c001b); - INSTANCE_WR(ctx, 0x281c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2820/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2824/4, 0x000c001b); - INSTANCE_WR(ctx, 0x282c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2830/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2834/4, 0x000c001b); - INSTANCE_WR(ctx, 0x283c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2840/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2844/4, 0x000c001b); - INSTANCE_WR(ctx, 0x284c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2850/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2854/4, 0x000c001b); - INSTANCE_WR(ctx, 0x285c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2860/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2864/4, 0x000c001b); - INSTANCE_WR(ctx, 0x286c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2870/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2874/4, 0x000c001b); - INSTANCE_WR(ctx, 0x287c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2880/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2884/4, 0x000c001b); - INSTANCE_WR(ctx, 0x288c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2890/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2894/4, 0x000c001b); - INSTANCE_WR(ctx, 0x289c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2900/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2904/4, 0x000c001b); - INSTANCE_WR(ctx, 0x290c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2910/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2914/4, 0x000c001b); - INSTANCE_WR(ctx, 0x291c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2920/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2924/4, 0x000c001b); - INSTANCE_WR(ctx, 0x292c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2930/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2934/4, 0x000c001b); - INSTANCE_WR(ctx, 0x293c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2940/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2944/4, 0x000c001b); - INSTANCE_WR(ctx, 0x294c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2950/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2954/4, 0x000c001b); - INSTANCE_WR(ctx, 0x295c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2960/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2964/4, 0x000c001b); - INSTANCE_WR(ctx, 0x296c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2970/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2974/4, 0x000c001b); - INSTANCE_WR(ctx, 0x297c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2980/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2984/4, 0x000c001b); - INSTANCE_WR(ctx, 0x298c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2990/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2994/4, 0x000c001b); - INSTANCE_WR(ctx, 0x299c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2aa0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2aa4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2aac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ab0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ab4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2abc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ac0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ac4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2acc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ad0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ad4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2adc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ae0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ae4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2aec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2af0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2af4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2afc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ba0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ba4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2bb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2bc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bcc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2bd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bdc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2be0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2be4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bf0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2bf4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bfc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ca0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ca4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2cb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2cc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ccc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2cd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cdc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ce0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ce4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cf0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2cf4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cfc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2da0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2da4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2dac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2db0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2db4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2dbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2dc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2dc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2dcc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2dd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2dd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ddc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2de0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2de4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2dec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2df0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2df4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2dfc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ea0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ea4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2eac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2eb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2eb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ebc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ec0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ec4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ecc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ed0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ed4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2edc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ee0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ee4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2eec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ef0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ef4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2efc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fa0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fa4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fcc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fdc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fe0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fe4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ff0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ff4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ffc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3000/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3004/4, 0x000c001b); - INSTANCE_WR(ctx, 0x300c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3010/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3014/4, 0x000c001b); - INSTANCE_WR(ctx, 0x301c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3020/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3024/4, 0x000c001b); - INSTANCE_WR(ctx, 0x302c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3030/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3034/4, 0x000c001b); - INSTANCE_WR(ctx, 0x303c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3040/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3044/4, 0x000c001b); - INSTANCE_WR(ctx, 0x304c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3050/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3054/4, 0x000c001b); - INSTANCE_WR(ctx, 0x305c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3060/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3064/4, 0x000c001b); - INSTANCE_WR(ctx, 0x306c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3070/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3074/4, 0x000c001b); - INSTANCE_WR(ctx, 0x307c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3080/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3084/4, 0x000c001b); - INSTANCE_WR(ctx, 0x308c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3090/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3094/4, 0x000c001b); - for(i = 0x30bc; i< 0x30cc; i += 4) - INSTANCE_WR(ctx, i/4, 0x0000ffff); - INSTANCE_WR(ctx, 0x3450/4, 0x3f800000); - INSTANCE_WR(ctx, 0x380c/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3820/4, 0x3f800000); - INSTANCE_WR(ctx, 0x384c/4, 0x40000000); - INSTANCE_WR(ctx, 0x3850/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3854/4, 0x3f000000); - INSTANCE_WR(ctx, 0x385c/4, 0x40000000); - INSTANCE_WR(ctx, 0x3860/4, 0x3f800000); - INSTANCE_WR(ctx, 0x3868/4, 0xbf800000); - INSTANCE_WR(ctx, 0x3870/4, 0xbf800000); -} - -int nv20_graph_create_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *); - unsigned int ctx_size; - int ret; - - switch (dev_priv->chipset) { - case 0x25: - case 0x28: - ctx_size = NV25_GRCTX_SIZE; - ctx_init = nv25_graph_context_init; - break; - case 0x30: - case 0x31: - ctx_size = NV30_31_GRCTX_SIZE; - ctx_init = nv30_31_graph_context_init; - break; - case 0x34: - ctx_size = NV34_GRCTX_SIZE; - ctx_init = nv34_graph_context_init; - break; - case 0x35: - case 0x36: - ctx_size = NV35_36_GRCTX_SIZE; - ctx_init = nv35_36_graph_context_init; - break; - default: - ctx_size = 0; - ctx_init = nv35_36_graph_context_init; - DRM_ERROR("Please contact the devs if you want your NV%x" - " card to work\n", dev_priv->chipset); - return -ENOSYS; - break; - } - - if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16, - NVOBJ_FLAG_ZERO_ALLOC, - &chan->ramin_grctx))) - return ret; - - /* Initialise default context values */ - ctx_init(dev, chan->ramin_grctx->gpuobj); - - /* nv20: INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); */ - INSTANCE_WR(chan->ramin_grctx->gpuobj, 0x28/4, (chan->id<<24)|0x1); - /* CTX_USER */ - - INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, - chan->ramin_grctx->instance >> 4); - - return 0; -} - -void nv20_graph_destroy_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - - if (chan->ramin_grctx) - nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); - - INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0); -} - -static int -nouveau_graph_wait_idle(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int tv = 1000; - - while (tv--) { - if (NV_READ(NV04_PGRAPH_STATUS) == 0) - break; - } - - if (NV_READ(NV04_PGRAPH_STATUS)) { - DRM_ERROR("timeout!\n"); - return -EBUSY; - } - return 0; -} - -int nv20_graph_load_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t inst; - - if (!chan->ramin_grctx) - return -EINVAL; - inst = chan->ramin_grctx->instance >> 4; - - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER, - NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD); - - return nouveau_graph_wait_idle(dev); -} - -int nv20_graph_save_context(struct nouveau_channel *chan) -{ - struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t inst; - - if (!chan->ramin_grctx) - return -EINVAL; - inst = chan->ramin_grctx->instance >> 4; - - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER, - NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE); - - return nouveau_graph_wait_idle(dev); -} - -static void nv20_graph_rdi(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - int i; - - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000); - for (i = 0; i < 32; i++) - NV_WRITE(NV10_PGRAPH_RDI_DATA, 0); - - nouveau_wait_for_idle(dev); -} - -int nv20_graph_init(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = - (struct drm_nouveau_private *)dev->dev_private; - uint32_t tmp, vramsz; - int ret, i; - - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & - ~NV_PMC_ENABLE_PGRAPH); - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | - NV_PMC_ENABLE_PGRAPH); - - /* Create Context Pointer Table */ - dev_priv->ctx_table_size = 32 * 4; - if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, - dev_priv->ctx_table_size, 16, - NVOBJ_FLAG_ZERO_ALLOC, - &dev_priv->ctx_table))) - return ret; - - NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, - dev_priv->ctx_table->instance >> 4); - - //XXX need to be done and save/restore for each fifo ??? - nv20_graph_rdi(dev); - - NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); - NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); - NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700); - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xF20E0435); /* 0x4 = auto ctx switch */ - NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000); - NV_WRITE(0x40009C , 0x00000040); - - if (dev_priv->chipset >= 0x25) { - NV_WRITE(0x400890, 0x00080000); - NV_WRITE(0x400610, 0x304B1FB6); - NV_WRITE(0x400B80, 0x18B82880); - NV_WRITE(0x400B84, 0x44000000); - NV_WRITE(0x400098, 0x40000080); - NV_WRITE(0x400B88, 0x000000ff); - } else { - NV_WRITE(0x400880, 0x00080000); - NV_WRITE(0x400094, 0x00000005); - NV_WRITE(0x400B80, 0x45CAA208); - NV_WRITE(0x400B84, 0x24000000); - NV_WRITE(0x400098, 0x00000040); - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00038); - NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030); - NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E10038); - NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030); - } - - /* copy tile info from PFB */ - for (i=0; idev_private; - - nouveau_gpuobj_ref_del(dev, &dev_priv->ctx_table); -} - -int nv30_graph_init(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t vramsz, tmp; - int ret, i; - - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & - ~NV_PMC_ENABLE_PGRAPH); - NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | - NV_PMC_ENABLE_PGRAPH); - - /* Create Context Pointer Table */ - dev_priv->ctx_table_size = 32 * 4; - if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, - dev_priv->ctx_table_size, 16, - NVOBJ_FLAG_ZERO_ALLOC, - &dev_priv->ctx_table))) - return ret; - - NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, - dev_priv->ctx_table->instance >> 4); - - NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); - NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); - NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x401287c0); - NV_WRITE(0x400890, 0x01b463ff); - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xf3de0471); - NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000); - NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); - NV_WRITE(0x400B80, 0x1003d888); - NV_WRITE(0x400098, 0x00000000); - NV_WRITE(0x40009C, 0x0005ad00); - NV_WRITE(0x400B88, 0x62ff00ff); // suspiciously like PGRAPH_DEBUG_2 - NV_WRITE(0x4000a0, 0x00000000); - NV_WRITE(0x4000a4, 0x00000008); - NV_WRITE(0x4008a8, 0xb784a400); - NV_WRITE(0x400ba0, 0x002f8685); - NV_WRITE(0x400ba4, 0x00231f3f); - NV_WRITE(0x4008a4, 0x40000020); - NV_WRITE(0x400B84, 0x0c000000); - NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x62ff0f7f); - NV_WRITE(0x4000c0, 0x00000016); - NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, 0x000014e4); - - /* copy tile info from PFB */ - for (i=0; i Date: Sun, 30 Sep 2007 23:09:30 +0200 Subject: nouveau : nv20_graph replace nouveau_graph_wait_idle by nouveau_wait_for_idle Also clean PGRAPH_CHANNEL macros --- shared-core/nouveau_reg.h | 4 +--- shared-core/nv20_graph.c | 30 +++++++----------------------- 2 files changed, 8 insertions(+), 26 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 21133d98..59b69547 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -286,10 +286,8 @@ #define NV10_PGRAPH_DMA_PITCH 0x00400770 #define NV10_PGRAPH_DVD_COLORFMT 0x00400774 #define NV10_PGRAPH_SCALED_FORMAT 0x00400778 -#define NV10_PGRAPH_CHANNEL_CTX_TABLE 0x00400780 -#define NV10_PGRAPH_CHANNEL_CTX_SIZE 0x00400784 +#define NV20_PGRAPH_CHANNEL_CTX_TABLE 0x00400780 #define NV20_PGRAPH_CHANNEL_CTX_POINTER 0x00400784 -#define NV10_PGRAPH_CHANNEL_CTX_POINTER 0x00400788 #define NV20_PGRAPH_CHANNEL_CTX_XFER 0x00400788 #define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD 0x00000001 #define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE 0x00000002 diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 8ca1f84c..f87d3138 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -2933,24 +2933,6 @@ void nv20_graph_destroy_context(struct nouveau_channel *chan) INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0); } -static int -nouveau_graph_wait_idle(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - int tv = 1000; - - while (tv--) { - if (NV_READ(NV04_PGRAPH_STATUS) == 0) - break; - } - - if (NV_READ(NV04_PGRAPH_STATUS)) { - DRM_ERROR("timeout!\n"); - return -EBUSY; - } - return 0; -} - int nv20_graph_load_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; @@ -2965,7 +2947,8 @@ int nv20_graph_load_context(struct nouveau_channel *chan) NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER, NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD); - return nouveau_graph_wait_idle(dev); + nouveau_wait_for_idle(dev); + return 0; } int nv20_graph_save_context(struct nouveau_channel *chan) @@ -2982,7 +2965,8 @@ int nv20_graph_save_context(struct nouveau_channel *chan) NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER, NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE); - return nouveau_graph_wait_idle(dev); + nouveau_wait_for_idle(dev); + return 0; } static void nv20_graph_rdi(struct drm_device *dev) { @@ -3015,7 +2999,7 @@ int nv20_graph_init(struct drm_device *dev) { &dev_priv->ctx_table))) return ret; - NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_TABLE, dev_priv->ctx_table->instance >> 4); //XXX need to be done and save/restore for each fifo ??? @@ -3118,7 +3102,7 @@ int nv30_graph_init(struct drm_device *dev) &dev_priv->ctx_table))) return ret; - NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_TABLE, dev_priv->ctx_table->instance >> 4); NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); @@ -3144,7 +3128,7 @@ int nv30_graph_init(struct drm_device *dev) NV_WRITE(0x400B84, 0x0c000000); NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x62ff0f7f); NV_WRITE(0x4000c0, 0x00000016); - NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, 0x000014e4); + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_TABLE, 0x000014e4); /* copy tile info from PFB */ for (i=0; i Date: Sun, 30 Sep 2007 23:19:39 +0200 Subject: nouveau : nv30 remove harcoded NV20_PGRAPH_CHANNEL_CTX_TABLE --- shared-core/nv20_graph.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index f87d3138..233afd37 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -3002,7 +3002,6 @@ int nv20_graph_init(struct drm_device *dev) { NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_TABLE, dev_priv->ctx_table->instance >> 4); - //XXX need to be done and save/restore for each fifo ??? nv20_graph_rdi(dev); NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); @@ -3094,16 +3093,16 @@ int nv30_graph_init(struct drm_device *dev) NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH); - /* Create Context Pointer Table */ - dev_priv->ctx_table_size = 32 * 4; + /* Create Context Pointer Table */ + dev_priv->ctx_table_size = 32 * 4; if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, dev_priv->ctx_table_size, 16, NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ctx_table))) return ret; - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_TABLE, - dev_priv->ctx_table->instance >> 4); + NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_TABLE, + dev_priv->ctx_table->instance >> 4); NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); @@ -3128,7 +3127,6 @@ int nv30_graph_init(struct drm_device *dev) NV_WRITE(0x400B84, 0x0c000000); NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x62ff0f7f); NV_WRITE(0x4000c0, 0x00000016); - NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_TABLE, 0x000014e4); /* copy tile info from PFB */ for (i=0; i Date: Mon, 1 Oct 2007 03:28:10 +0200 Subject: nouveau: flip the ctx switch bit on. it seems to be ignored on nv34 but causes nv30 issues. --- shared-core/nv20_graph.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 233afd37..8291f214 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -3111,7 +3111,7 @@ int nv30_graph_init(struct drm_device *dev) NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x401287c0); NV_WRITE(0x400890, 0x01b463ff); - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xf3de0471); + NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xf3de0475); NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000); NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); NV_WRITE(0x400B80, 0x1003d888); -- cgit v1.2.3 From 69fcfb413e72ad2204d306f20af6547819e040da Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Mon, 1 Oct 2007 22:21:23 +0200 Subject: nouveau: Fix dereferencing a NULL pointer when erroring out during initialization. --- shared-core/nouveau_state.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index cba12b57..cb19c880 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -423,12 +423,15 @@ void nouveau_lastclose(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - nouveau_card_takedown(dev); - - if(dev_priv->fb_mtrr>0) - { - drm_mtrr_del(dev_priv->fb_mtrr, drm_get_resource_start(dev, 1),nouveau_mem_fb_amount(dev), DRM_MTRR_WC); - dev_priv->fb_mtrr=0; + /* In the case of an error dev_priv may not be be allocated yet */ + if (dev_priv && dev_priv->card_type) { + nouveau_card_takedown(dev); + + if(dev_priv->fb_mtrr>0) + { + drm_mtrr_del(dev_priv->fb_mtrr, drm_get_resource_start(dev, 1),nouveau_mem_fb_amount(dev), DRM_MTRR_WC); + dev_priv->fb_mtrr=0; + } } } -- cgit v1.2.3 From ffa3173ec4bb5a310b3f8539bb6c2f8589ce2ed5 Mon Sep 17 00:00:00 2001 From: Stuart Bennett Date: Tue, 2 Oct 2007 15:45:30 +0100 Subject: nouveau: nv20 graph context init --- shared-core/nv20_graph.c | 140 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 138 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 8291f214..213d60cc 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -19,14 +19,146 @@ * */ -/*#define NV20_GRCTX_SIZE (3529*4)*/ - +#define NV20_GRCTX_SIZE (3580*4) #define NV25_GRCTX_SIZE (3529*4) #define NV30_31_GRCTX_SIZE (22392) #define NV34_GRCTX_SIZE (18140) #define NV35_36_GRCTX_SIZE (22396) +static void nv20_graph_context_init(struct drm_device *dev, + struct nouveau_gpuobj *ctx) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; +/* +write32 #1 block at +0x00740adc NV_PRAMIN+0x40adc of 3369 (0xd29) elements: ++0x00740adc: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740b3c: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000 ++0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740bbc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740bdc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740bfc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + ++0x00740c1c: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000 ++0x00740c3c: 00000000 00000000 00000000 44400000 00000000 00000000 00000000 00000000 ++0x00740c5c: 00000000 00000000 00000000 00000000 00000000 00000000 00030303 00030303 ++0x00740c7c: 00030303 00030303 00000000 00000000 00000000 00000000 00080000 00080000 ++0x00740c9c: 00080000 00080000 00000000 00000000 01012000 01012000 01012000 01012000 ++0x00740cbc: 000105b8 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008 ++0x00740cdc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740cfc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 ++0x00740d1c: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 ++0x00740d3c: 00000000 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000 + ++0x00740d5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740d7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740d9c: 00000001 00000000 00004000 00000000 00000000 00000001 00000000 00040000 ++0x00740dbc: 00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x00740ddc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +... +*/ + INSTANCE_WR(ctx, (0x33c/4)+0, 0xffff0000); + INSTANCE_WR(ctx, (0x33c/4)+25, 0x0fff0000); + INSTANCE_WR(ctx, (0x33c/4)+26, 0x0fff0000); + INSTANCE_WR(ctx, (0x33c/4)+80, 0x00000101); + INSTANCE_WR(ctx, (0x33c/4)+85, 0x00000111); + INSTANCE_WR(ctx, (0x33c/4)+91, 0x44400000); + for (i = 0; i < 4; ++i) + INSTANCE_WR(ctx, (0x33c/4)+102+i, 0x00030303); + for (i = 0; i < 4; ++i) + INSTANCE_WR(ctx, (0x33c/4)+110+i, 0x00080000); + for (i = 0; i < 4; ++i) + INSTANCE_WR(ctx, (0x33c/4)+116+i, 0x01012000); + for (i = 0; i < 4; ++i) + INSTANCE_WR(ctx, (0x33c/4)+120+i, 0x000105b8); + for (i = 0; i < 4; ++i) + INSTANCE_WR(ctx, (0x33c/4)+124+i, 0x00080008); + for (i = 0; i < 16; ++i) + INSTANCE_WR(ctx, (0x33c/4)+136+i, 0x07ff0000); + INSTANCE_WR(ctx, (0x33c/4)+154, 0x4b7ffff); + INSTANCE_WR(ctx, (0x33c/4)+176, 0x00000001); + INSTANCE_WR(ctx, (0x33c/4)+178, 0x00004000); + INSTANCE_WR(ctx, (0x33c/4)+181, 0x00000001); + INSTANCE_WR(ctx, (0x33c/4)+183, 0x00004000); + INSTANCE_WR(ctx, (0x33c/4)+184, 0x00010000); + +/* +... ++0x0074239c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ++0x007423bc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 ++0x007423dc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 ++0x007423fc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 +... ++0x00742bdc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 ++0x00742bfc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 ++0x00742c1c: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000 ++0x00742c3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +... +*/ + for (i = 0; i < 0x880; i += 0x10) { + INSTANCE_WR(ctx, ((0x1c1c + i)/4)+0, 0x10700ff9); + INSTANCE_WR(ctx, ((0x1c1c + i)/4)+1, 0x0436086c); + INSTANCE_WR(ctx, ((0x1c1c + i)/4)+2, 0x000c001b); + } + +/* +write32 #1 block at +0x00742fbc NV_PRAMIN+0x42fbc of 4 (0x4) elements: ++0x00742fbc: 3f800000 00000000 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x281c/4), 0x3f800000); + +/* +write32 #1 block at +0x00742ffc NV_PRAMIN+0x42ffc of 12 (0xc) elements: ++0x00742ffc: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000 ++0x0074301c: 00000000 bf800000 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x285c/4)+0, 0x40000000); + INSTANCE_WR(ctx, (0x285c/4)+1, 0x3f800000); + INSTANCE_WR(ctx, (0x285c/4)+2, 0x3f000000); + INSTANCE_WR(ctx, (0x285c/4)+4, 0x40000000); + INSTANCE_WR(ctx, (0x285c/4)+5, 0x3f800000); + INSTANCE_WR(ctx, (0x285c/4)+7, 0xbf800000); + INSTANCE_WR(ctx, (0x285c/4)+9, 0xbf800000); + +/* +write32 #1 block at +0x00742fcc NV_PRAMIN+0x42fcc of 4 (0x4) elements: ++0x00742fcc: 00000000 3f800000 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x282c/4)+1, 0x3f800000); + +/* +write32 #1 block at +0x0074302c NV_PRAMIN+0x4302c of 4 (0x4) elements: ++0x0074302c: 00000000 00000000 00000000 00000000 +write32 #1 block at +0x00743c9c NV_PRAMIN+0x43c9c of 4 (0x4) elements: ++0x00743c9c: 00000000 00000000 00000000 00000000 +write32 #1 block at +0x00743c3c NV_PRAMIN+0x43c3c of 8 (0x8) elements: ++0x00743c3c: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x349c/4)+2, 0x000fe000); + +/* +write32 #1 block at +0x00743c6c NV_PRAMIN+0x43c6c of 4 (0x4) elements: ++0x00743c6c: 00000000 00000000 00000000 00000000 +write32 #1 block at +0x00743ccc NV_PRAMIN+0x43ccc of 4 (0x4) elements: ++0x00743ccc: 00000000 000003f8 00000000 00000000 +*/ + INSTANCE_WR(ctx, (0x352c/4)+1, 0x000003f8); + +/* write32 #1 NV_PRAMIN+0x43ce0 <- 0x002fe000 */ + INSTANCE_WR(ctx, 0x3540/4, 0x002fe000); + +/* +write32 #1 block at +0x00743cfc NV_PRAMIN+0x43cfc of 8 (0x8) elements: ++0x00743cfc: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c +*/ + for (i = 0; i < 8; ++i) + INSTANCE_WR(ctx, (0x355c/4)+i, 0x001c527c); +} static void nv25_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) @@ -2876,6 +3008,10 @@ int nv20_graph_create_context(struct nouveau_channel *chan) int ret; switch (dev_priv->chipset) { + case 0x20: + ctx_size = NV20_GRCTX_SIZE; + ctx_init = nv20_graph_context_init; + break; case 0x25: case 0x28: ctx_size = NV25_GRCTX_SIZE; -- cgit v1.2.3 From afc57ef1dfb5bdf17411505d4dfbb03863a870bf Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Tue, 2 Oct 2007 21:51:14 +0300 Subject: nouveau: fix nv25_graph_context_init It was writing 4x the data in a loop. --- shared-core/nv20_graph.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 213d60cc..6b4c25e0 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -256,11 +256,10 @@ write32 #1 block at +0x00740d34 NV_PRAMIN.GRCTX0+0x614 of 3136 (0xc40) elements: INSTANCE_WR(ctx, (0x614/4)+25, 0x00000001); INSTANCE_WR(ctx, (0x614/4)+27, 0x00040000); INSTANCE_WR(ctx, (0x614/4)+28, 0x00010000); - for (i=0; i<0x880; i+=4) { + for (i=0; i < 0x880/4; i+=4) { INSTANCE_WR(ctx, (0x1b04/4)+i+0, 0x10700ff9); INSTANCE_WR(ctx, (0x1b04/4)+i+1, 0x0436086c); INSTANCE_WR(ctx, (0x1b04/4)+i+2, 0x000c001b); - INSTANCE_WR(ctx, (0x1b04/4)+i+3, 0x00000000); } /* -- cgit v1.2.3 From a72eb27fbc7a66e35018ffbcb5137cfaaf4049aa Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Tue, 2 Oct 2007 21:56:01 +0300 Subject: nouveau: nv20 graph_create_context difference nv20 writes the chan->id to a different place than nv28. This still does not make nv20 run nv10_demo. --- shared-core/nv20_graph.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 6b4c25e0..aba5a7e4 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -3004,12 +3004,14 @@ int nv20_graph_create_context(struct nouveau_channel *chan) struct drm_nouveau_private *dev_priv = dev->dev_private; void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *); unsigned int ctx_size; + unsigned int idoffs = 0x28/4; int ret; switch (dev_priv->chipset) { case 0x20: ctx_size = NV20_GRCTX_SIZE; ctx_init = nv20_graph_context_init; + idoffs = 0; break; case 0x25: case 0x28: @@ -3048,7 +3050,7 @@ int nv20_graph_create_context(struct nouveau_channel *chan) ctx_init(dev, chan->ramin_grctx->gpuobj); /* nv20: INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); */ - INSTANCE_WR(chan->ramin_grctx->gpuobj, 0x28/4, (chan->id<<24)|0x1); + INSTANCE_WR(chan->ramin_grctx->gpuobj, idoffs, (chan->id<<24)|0x1); /* CTX_USER */ INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, -- cgit v1.2.3 From 7fbd10d93310345164d1e65da281848b05493797 Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Thu, 4 Oct 2007 03:43:59 +0200 Subject: nouveau: nv2a drm context switch support. --- shared-core/nv20_graph.c | 74 ++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 69 insertions(+), 5 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index aba5a7e4..9edab594 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -4,14 +4,19 @@ #include "nouveau_drm.h" /* + * NV20 + * ----- * There are 3 families : - * NV30 is 0x10de:0x030* - * NV31 is 0x10de:0x031* + * NV20 is 0x10de:0x020* + * NV25/28 is 0x10de:0x025* / 0x10de:0x028* + * NV2A is 0x10de:0x02A0 * + * NV30 + * ----- + * There are 3 families : + * NV30/31 is 0x10de:0x030* / 0x10de:0x031* * NV34 is 0x10de:0x032* - * - * NV35 is 0x10de:0x033* (NV35 and NV36 are the same) - * NV36 is 0x10de:0x034* + * NV35/36 is 0x10de:0x033* / 0x10de:0x034* * * Not seen in the wild, no dumps (probably NV35) : * NV37 is 0x10de:0x00fc, 0x10de:0x00fd @@ -21,6 +26,7 @@ #define NV20_GRCTX_SIZE (3580*4) #define NV25_GRCTX_SIZE (3529*4) +#define NV2A_GRCTX_SIZE (3500*4) #define NV30_31_GRCTX_SIZE (22392) #define NV34_GRCTX_SIZE (18140) @@ -160,6 +166,59 @@ write32 #1 block at +0x00743cfc NV_PRAMIN+0x43cfc of 8 (0x8) elements: INSTANCE_WR(ctx, (0x355c/4)+i, 0x001c527c); } +static void nv2a_graph_context_init(struct drm_device *dev, + struct nouveau_gpuobj *ctx) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; + + INSTANCE_WR(ctx, 0x33c/4, 0xffff0000); + for(i = 0x3a0; i< 0x3a8; i += 4) + INSTANCE_WR(ctx, i/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x47c/4, 0x00000101); + INSTANCE_WR(ctx, 0x490/4, 0x00000111); + INSTANCE_WR(ctx, 0x4a8/4, 0x44400000); + for(i = 0x4d4; i< 0x4e4; i += 4) + INSTANCE_WR(ctx, i/4, 0x00030303); + for(i = 0x4f4; i< 0x504; i += 4) + INSTANCE_WR(ctx, i/4, 0x00080000); + for(i = 0x50c; i< 0x51c; i += 4) + INSTANCE_WR(ctx, i/4, 0x01012000); + for(i = 0x51c; i< 0x52c; i += 4) + INSTANCE_WR(ctx, i/4, 0x000105b8); + for(i = 0x52c; i< 0x53c; i += 4) + INSTANCE_WR(ctx, i/4, 0x00080008); + for(i = 0x55c; i< 0x59c; i += 4) + INSTANCE_WR(ctx, i/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x5a4/4, 0x4b7fffff); + INSTANCE_WR(ctx, 0x5fc/4, 0x00000001); + INSTANCE_WR(ctx, 0x604/4, 0x00004000); + INSTANCE_WR(ctx, 0x610/4, 0x00000001); + INSTANCE_WR(ctx, 0x618/4, 0x00040000); + INSTANCE_WR(ctx, 0x61c/4, 0x00010000); + + for (i=0x1a9c; i <= 0x22fc/4; i += 32) { + INSTANCE_WR(ctx, i/4 , 0x10700ff9); + INSTANCE_WR(ctx, i/4 + 1, 0x0436086c); + INSTANCE_WR(ctx, i/4 + 2, 0x000c001b); + } + + INSTANCE_WR(ctx, 0x269c/4, 0x3f800000); + INSTANCE_WR(ctx, 0x26b0/4, 0x3f800000); + INSTANCE_WR(ctx, 0x26dc/4, 0x40000000); + INSTANCE_WR(ctx, 0x26e0/4, 0x3f800000); + INSTANCE_WR(ctx, 0x26e4/4, 0x3f000000); + INSTANCE_WR(ctx, 0x26ec/4, 0x40000000); + INSTANCE_WR(ctx, 0x26f0/4, 0x3f800000); + INSTANCE_WR(ctx, 0x26f8/4, 0xbf800000); + INSTANCE_WR(ctx, 0x2700/4, 0xbf800000); + INSTANCE_WR(ctx, 0x3024/4, 0x000fe000); + INSTANCE_WR(ctx, 0x30a0/4, 0x000003f8); + INSTANCE_WR(ctx, 0x33fc/4, 0x002fe000); + for(i = 0x341c; i< 0x343c; i += 4) + INSTANCE_WR(ctx, i/4, 0x001c527c); +} + static void nv25_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { @@ -3018,6 +3077,11 @@ int nv20_graph_create_context(struct nouveau_channel *chan) ctx_size = NV25_GRCTX_SIZE; ctx_init = nv25_graph_context_init; break; + case 0x2a: + ctx_size = NV2A_GRCTX_SIZE; + ctx_init = nv2a_graph_context_init; + idoffs = 0; + break; case 0x30: case 0x31: ctx_size = NV30_31_GRCTX_SIZE; -- cgit v1.2.3 From b510517d59efcb45cc7079743be967bee122b251 Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Thu, 4 Oct 2007 09:31:46 +0200 Subject: nouveau: Switch over to using PMC_BOOT_0 for card detection. --- shared-core/drm_pciids.txt | 255 -------------------------------------------- shared-core/nouveau_state.c | 74 +++++++++++-- 2 files changed, 68 insertions(+), 261 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index 74e7e75a..05d32f2e 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -481,261 +481,6 @@ 0x10DE 0x009D NV40 "NVidia Quadro FX 4500" 0x10DE 0x009E NV40 "NVidia 0x009E" -[nouveau] -0x10de 0x0020 NV_04 "RIVA TNT" -0x10de 0x0028 NV_04 "RIVA TNT2/TNT2 Pro" -0x10de 0x0029 NV_04 "RIVA TNT2 Ultra" -0x10de 0x002a NV_04 "Riva TnT2" -0x10de 0x002b NV_04 "Riva TnT2" -0x10de 0x002c NV_04 "Vanta/Vanta LT" -0x10de 0x002d NV_04 "RIVA TNT2 Model 64/Model 64 Pro" -0x10de 0x002e NV_04 "Vanta" -0x10de 0x002f NV_04 "Vanta" -0x10de 0x0040 NV_40 "GeForce 6800 Ultra" -0x10de 0x0041 NV_40 "GeForce 6800" -0x10de 0x0042 NV_40 "GeForce 6800 LE" -0x10de 0x0043 NV_40 "NV40.3" -0x10de 0x0044 NV_40 "GeForce 6800 XT" -0x10de 0x0045 NV_40 "GeForce 6800 GT" -0x10de 0x0046 NV_40 "GeForce 6800 GT" -0x10de 0x0047 NV_40 "GeForce 6800 GS" -0x10de 0x0048 NV_40 "GeForce 6800 XT" -0x10de 0x0049 NV_40 "NV40GL" -0x10de 0x004d NV_40 "Quadro FX 4000" -0x10de 0x004e NV_40 "Quadro FX 4000" -0x10de 0x0090 NV_40 "GeForce 7800 GTX" -0x10de 0x0091 NV_40 "GeForce 7800 GTX" -0x10de 0x0092 NV_40 "GeForce 7800 GT" -0x10de 0x0093 NV_40 "GeForce 7800 GS" -0x10de 0x0095 NV_40 "GeForce 7800 SLI" -0x10de 0x0098 NV_40 "GeForce Go 7800" -0x10de 0x0099 NV_40 "GeForce Go 7800 GTX" -0x10de 0x009d NV_40 "Quadro FX4500" -0x10de 0x00a0 NV_04 "Aladdin TNT2" -0x10de 0x00c0 NV_40 "GeForce 6800 GS" -0x10de 0x00c1 NV_40 "GeForce 6800" -0x10de 0x00c2 NV_40 "GeForce 6800 LE" -0x10de 0x00c3 NV_40 "Geforce 6800 XT" -0x10de 0x00c8 NV_40 "GeForce Go 6800" -0x10de 0x00c9 NV_40 "GeForce Go 6800 Ultra" -0x10de 0x00cc NV_40 "Quadro FX Go1400" -0x10de 0x00cd NV_40 "Quadro FX 3450/4000 SDI" -0x10de 0x00ce NV_40 "Quadro FX 1400" -0x10de 0x00f0 NV_40 "GeForce 6800/GeForce 6800 Ultra" -0x10de 0x00f1 NV_40 "GeForce 6600/GeForce 6600 GT" -0x10de 0x00f2 NV_40 "GeForce 6600/GeForce 6600 GT" -0x10de 0x00f3 NV_40 "GeForce 6200" -0x10de 0x00f4 NV_40 "GeForce 6600 LE" -0x10de 0x00f5 NV_40 "GeForce 7800 GS" -0x10de 0x00f6 NV_40 "GeForce 6600 GS" -0x10de 0x00f8 NV_40 "Quadro FX 3400/4400" -0x10de 0x00f9 NV_40 "GeForce 6800 Ultra/GeForce 6800 GT" -0x10de 0x00fa NV_30 "GeForce PCX 5750" -0x10de 0x00fb NV_30 "GeForce PCX 5900" -0x10de 0x00fc NV_30 "Quadro FX 330/GeForce PCX 5300" -0x10de 0x00fd NV_30 "Quadro FX 330/Quadro NVS280" -0x10de 0x00fe NV_30 "Quadro FX 1300" -0x10de 0x00ff NV_17 "GeForce PCX 4300" -0x10de 0x0100 NV_10 "GeForce 256 SDR" -0x10de 0x0101 NV_10 "GeForce 256 DDR" -0x10de 0x0103 NV_10 "Quadro" -0x10de 0x0110 NV_11 "GeForce2 MX/MX 400" -0x10de 0x0111 NV_11 "GeForce2 MX 100 DDR/200 DDR" -0x10de 0x0112 NV_11 "GeForce2 Go" -0x10de 0x0113 NV_11 "Quadro2 MXR/EX/Go" -0x10de 0x0140 NV_40 "GeForce 6600 GT" -0x10de 0x0141 NV_40 "GeForce 6600" -0x10de 0x0142 NV_40 "GeForce 6600 LE" -0x10de 0x0143 NV_40 "GeForce 6600 VE" -0x10de 0x0144 NV_40 "GeForce Go 6600" -0x10de 0x0145 NV_40 "GeForce 6610 XL" -0x10de 0x0146 NV_40 "Geforce Go 6600TE/6200TE" -0x10de 0x0147 NV_40 "GeForce 6700 XL" -0x10de 0x0148 NV_40 "GeForce Go 6600" -0x10de 0x0149 NV_40 "GeForce Go 6600 GT" -0x10de 0x014a NV_40 "Quadro NVS 440" -0x10de 0x014c NV_40 "Quadro FX 550" -0x10de 0x014d NV_17 "Quadro FX 550" -0x10de 0x014e NV_40 "Quadro FX 540" -0x10de 0x014f NV_40 "GeForce 6200" -0x10de 0x0150 NV_15 "GeForce2 GTS/Pro" -0x10de 0x0151 NV_15 "GeForce2 Ti" -0x10de 0x0152 NV_15 "GeForce2 Ultra, Bladerunner" -0x10de 0x0153 NV_15 "Quadro2 Pro" -0x10de 0x0160 NV_44 "GeForce 6500" -0x10de 0x0161 NV_44 "GeForce 6200 TurboCache(TM)" -0x10de 0x0162 NV_44 "GeForce 6200 SE TurboCache (TM)" -0x10de 0x0163 NV_44 "GeForce 6200 LE" -0x10de 0x0164 NV_44 "GeForce Go 6200" -0x10de 0x0165 NV_44 "Quadro NVS 285" -0x10de 0x0166 NV_44 "GeForce Go 6400" -0x10de 0x0167 NV_44 "GeForce Go 6200 TurboCache" -0x10de 0x0168 NV_44 "GeForce Go 6200 TurboCache" -0x10de 0x0169 NV_44 "GeForce 6250" -0x10de 0x0170 NV_17 "GeForce4 MX 460" -0x10de 0x0171 NV_17 "GeForce4 MX 440" -0x10de 0x0172 NV_17 "GeForce4 MX 420" -0x10de 0x0173 NV_17 "GeForce4 MX 440-SE" -0x10de 0x0174 NV_17 "GeForce4 440 Go" -0x10de 0x0175 NV_17 "GeForce4 420 Go" -0x10de 0x0176 NV_17 "GeForce4 420 Go 32M" -0x10de 0x0177 NV_17 "GeForce4 460 Go" -0x10de 0x0178 NV_17 "Quadro4 550 XGL" -0x10de 0x0179 NV_17 "GeForce4 420 Go 32M" -0x10de 0x017a NV_17 "Quadro4 200/400 NVS" -0x10de 0x017b NV_17 "Quadro4 550 XGL" -0x10de 0x017c NV_17 "Quadro4 500 GoGL" -0x10de 0x017d NV_17 "GeForce4 410 Go 16M" -0x10de 0x0181 NV_17 "GeForce4 MX 440 AGP 8x" -0x10de 0x0182 NV_17 "GeForce4 MX 440SE AGP 8x" -0x10de 0x0183 NV_17 "GeForce4 MX 420 AGP 8x" -0x10de 0x0185 NV_17 "GeForce4 MX 4000 AGP 8x" -0x10de 0x0186 NV_17 "GeForce4 448 Go" -0x10de 0x0187 NV_17 "GeForce4 488 Go" -0x10de 0x0188 NV_17 "Quadro4 580 XGL" -0x10de 0x018a NV_17 "Quadro4 NVS AGP 8x" -0x10de 0x018b NV_17 "Quadro4 380 XGL" -0x10de 0x018c NV_17 "Quadro NVS 50 PCI" -0x10de 0x018d NV_17 "GeForce4 448 Go" -0x10de 0x0191 NV_50 "GeForce 8800 GTX" -0x10de 0x0193 NV_50 "GeForce 8800 GTS" -0x10de 0x0194 NV_50 "GeForce 8800 Ultra" -0x10de 0x019d NV_50 "Quadro FX 5600" -0x10de 0x019e NV_50 "Quadro FX 4600" -0x10de 0x01a0 NV_11|NV_NFORCE "GeForce2 MX Integrated Graphics" -0x10de 0x01d1 NV_44 "GeForce 7300 LE" -0x10de 0x01d3 NV_44 "Geforce 7300 SE" -0x10de 0x01d6 NV_44 "GeForce Go 7200" -0x10de 0x01d7 NV_44 "Quadro NVS 110M / GeForce Go 7300" -0x10de 0x01d8 NV_44 "GeForce Go 7400" -0x10de 0x01d9 NV_44 "GeForce Go 7400 GS" -0x10de 0x01da NV_44 "Quadro NVS 110M" -0x10de 0x01db NV_44 "Quadro NVS 120M" -0x10de 0x01dc NV_44 "Quadro FX 350M" -0x10de 0x01dd NV_44 "GeForce 7500 LE" -0x10de 0x01de NV_44 "Quadro FX 350" -0x10de 0x01df NV_44 "GeForce 7300 GS" -0x10de 0x01f0 NV_17|NV_NFORCE2 "GeForce4 MX - nForce GPU" -0x10de 0x0200 NV_20 "GeForce3" -0x10de 0x0201 NV_20 "GeForce3 Ti 200" -0x10de 0x0202 NV_20 "GeForce3 Ti 500" -0x10de 0x0203 NV_20 "Quadro DCC" -0x10de 0x0211 NV_40 "GeForce 6800" -0x10de 0x0212 NV_40 "GeForce 6800 LE" -0x10de 0x0215 NV_40 "GeForce 6800 GT" -0x10de 0x0218 NV_40 "GeForce 6800 XT" -0x10de 0x0221 NV_44 "GeForce 6200" -0x10de 0x0222 NV_44 "GeForce 6200 A-LE" -0x10de 0x0240 NV_44 "GeForce 6150" -0x10de 0x0241 NV_44 "GeForce 6150 LE" -0x10de 0x0242 NV_44 "GeForce 6100" -0x10de 0x0244 NV_44 "GeForce Go 6150" -0x10de 0x0247 NV_44 "GeForce Go 6100" -0x10de 0x0250 NV_25 "GeForce4 Ti 4600" -0x10de 0x0251 NV_25 "GeForce4 Ti 4400" -0x10de 0x0252 NV_25 "GeForce4 Ti" -0x10de 0x0253 NV_25 "GeForce4 Ti 4200" -0x10de 0x0258 NV_25 "Quadro4 900 XGL" -0x10de 0x0259 NV_25 "Quadro4 750 XGL" -0x10de 0x025b NV_25 "Quadro4 700 XGL" -0x10de 0x0280 NV_25 "GeForce4 Ti 4800" -0x10de 0x0281 NV_25 "GeForce4 Ti 4200 AGP 8x" -0x10de 0x0282 NV_25 "GeForce4 Ti 4800 SE" -0x10de 0x0286 NV_25 "GeForce4 Ti 4200 Go AGP 8x" -0x10de 0x0288 NV_25 "Quadro4 980 XGL" -0x10de 0x0289 NV_25 "Quadro4 780 XGL" -0x10de 0x028c NV_25 "Quadro4 700 GoGL" -0x10de 0x0290 NV_40 "GeForce 7900 GTX" -0x10de 0x0291 NV_40 "GeForce 7900 GT" -0x10de 0x0292 NV_40 "GeForce 7900 GS" -0x10de 0x0298 NV_40 "GeForce Go 7900 GS" -0x10de 0x0299 NV_40 "GeForce Go 7900 GTX" -0x10de 0x029a NV_40 "Quadro FX 2500M" -0x10de 0x029b NV_40 "Quadro FX 1500M" -0x10de 0x029c NV_40 "Quadro FX 5500" -0x10de 0x029d NV_40 "Quadro FX 3500" -0x10de 0x029e NV_40 "Quadro FX 1500" -0x10de 0x029f NV_40 "Quadro FX 4500 X2" -0x10de 0x02a0 NV_20 "XGPU" -0x10de 0x02e1 NV_40 "GeForce 7600 GS" -0x10de 0x0300 NV_30 "GeForce FX" -0x10de 0x0301 NV_30 "GeForce FX 5800 Ultra" -0x10de 0x0302 NV_30 "GeForce FX 5800" -0x10de 0x0308 NV_30 "Quadro FX 2000" -0x10de 0x0309 NV_30 "Quadro FX 1000" -0x10de 0x0311 NV_30 "GeForce FX 5600 Ultra" -0x10de 0x0312 NV_30 "GeForce FX 5600" -0x10de 0x0313 NV_30 "NV31" -0x10de 0x0314 NV_30 "GeForce FX 5600XT" -0x10de 0x0316 NV_30 "NV31M" -0x10de 0x0317 NV_30 "NV31M Pro" -0x10de 0x031a NV_30 "GeForce FX Go5600" -0x10de 0x031b NV_30 "GeForce FX Go5650" -0x10de 0x031d NV_30 "NV31GLM" -0x10de 0x031e NV_30 "NV31GLM Pro" -0x10de 0x031f NV_30 "NV31GLM Pro" -0x10de 0x0320 NV_34 "GeForce FX 5200" -0x10de 0x0321 NV_34 "GeForce FX 5200 Ultra" -0x10de 0x0322 NV_34 "GeForce FX 5200" -0x10de 0x0323 NV_34 "GeForce FX 5200LE" -0x10de 0x0324 NV_34 "GeForce FX Go5200" -0x10de 0x0325 NV_34 "GeForce FX Go5250" -0x10de 0x0326 NV_34 "GeForce FX 5500" -0x10de 0x0327 NV_34 "GeForce FX 5100" -0x10de 0x0328 NV_34 "GeForce FX Go5200 32M/64M" -0x10de 0x0329 NV_34 "GeForce FX Go5200" -0x10de 0x032a NV_34 "Quadro NVS 280 PCI" -0x10de 0x032b NV_34 "Quadro FX 500/600 PCI" -0x10de 0x032c NV_34 "GeForce FX Go 5300" -0x10de 0x032d NV_34 "GeForce FX Go5100" -0x10de 0x032f NV_34 "NV34GL" -0x10de 0x0330 NV_30 "GeForce FX 5900 Ultra" -0x10de 0x0331 NV_30 "GeForce FX 5900" -0x10de 0x0332 NV_30 "GeForce FX 5900XT" -0x10de 0x0333 NV_30 "GeForce FX 5950 Ultra" -0x10de 0x0334 NV_30 "GeForce FX 5900ZT" -0x10de 0x0338 NV_30 "Quadro FX 3000" -0x10de 0x033f NV_30 "Quadro FX 700" -0x10de 0x0341 NV_30 "GeForce FX 5700 Ultra" -0x10de 0x0342 NV_30 "GeForce FX 5700" -0x10de 0x0343 NV_30 "GeForce FX 5700LE" -0x10de 0x0344 NV_30 "GeForce FX 5700VE" -0x10de 0x0345 NV_30 "NV36.5" -0x10de 0x0347 NV_30 "GeForce FX Go5700" -0x10de 0x0348 NV_30 "GeForce FX Go5700" -0x10de 0x0349 NV_30 "NV36M Pro" -0x10de 0x034b NV_30 "NV36MAP" -0x10de 0x034c NV_30 "Quadro FX Go1000" -0x10de 0x034e NV_30 "Quadro FX 1100" -0x10de 0x034f NV_30 "NV36GL" -0x10de 0x0391 NV_40 "GeForce 7600 GT" -0x10de 0x0392 NV_40 "GeForce 7600 GS" -0x10de 0x0393 NV_40 "GeForce 7300 GT" -0x10de 0x0394 NV_40 "GeForce 7600 LE" -0x10de 0x0395 NV_40 "GeForce 7300 GT" -0x10de 0x0397 NV_40 "GeForce Go 7700" -0x10de 0x0398 NV_40 "GeForce Go 7600" -0x10de 0x0399 NV_40 "GeForce Go 7600 GT" -0x10de 0x039a NV_40 "Quadro NVS 300M" -0x10de 0x039b NV_40 "GeForce Go 7900 SE" -0x10de 0x039c NV_40 "Quadro FX 550M" -0x10de 0x039e NV_40 "Quadro FX 560" -0x10de 0x03d0 NV_44 "GeForce 6100 nForce 430" -0x10de 0x03d1 NV_44 "GeForce 6100 nForce 405" -0x10de 0x03d2 NV_44 "GeForce 6100 nForce 400" -0x10de 0x03d5 NV_44 "GeForce 6100 nForce 420" -0x10de 0x0400 NV_50 "GeForce 8600 GTS" -0x10de 0x0402 NV_50 "GeForce 8600 GT" -0x10de 0x0421 NV_50 "GeForce 8500 GT" -0x10de 0x0422 NV_50 "GeForce 8400 GS" -0x10de 0x0423 NV_50 "GeForce 8300 GS" -0x10de 0x0429 NV_50 "Quadro NVS 140" -0x12d2 0x0020 NV_04 "TNT" -0x12d2 0x0028 NV_04 "TNT2" -0x12d2 0x0029 NV_04 "UTNT2" -0x12d2 0x002c NV_04 "VTNT2" -0x12d2 0x00a0 NV_04 "ITNT2" - [xgi] 0x18ca 0x2200 0 "XP5" 0x18ca 0x0047 0 "XP10 / XG47" diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index cb19c880..a163ae63 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -403,19 +403,81 @@ int nouveau_firstopen(struct drm_device *dev) int nouveau_load(struct drm_device *dev, unsigned long flags) { struct drm_nouveau_private *dev_priv; - - if (flags==NV_UNKNOWN) - return -EINVAL; + void __iomem *regs; + uint32_t reg0; + char architecture = 0; dev_priv = drm_calloc(1, sizeof(*dev_priv), DRM_MEM_DRIVER); - if (!dev_priv) + if (!dev_priv) return -ENOMEM; - dev_priv->card_type=flags&NOUVEAU_FAMILY; - dev_priv->flags=flags&NOUVEAU_FLAGS; + dev_priv->flags = flags & NOUVEAU_FLAGS; dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN; + DRM_DEBUG("vendor: 0x%X device: 0x%X class: 0x%X\n", dev->pci_vendor, dev->pci_device, dev->pdev->class); + + /* Time to determine the card architecture */ + regs = ioremap_nocache(pci_resource_start(dev->pdev, 0), 0x4); + if (!regs) { + DRM_ERROR("Could not ioremap to determine register\n"); + return -ENOMEM; + } + reg0 = readl(regs); + + /* We're dealing with >=NV10 */ + if ((reg0 & 0x0f000000) > 0 ) { + /* Bit 27-20 contain the architecture in hex */ + architecture = (reg0 & 0xff00000) >> 20; + /* NV04 or NV05 */ + } else if ((reg0 & 0xff00fff0) == 0x20004000) { + architecture = 0x04; + } + + iounmap(regs); + + if (architecture >= 0x50) { + dev_priv->card_type = NV_50; + } else if (architecture >= 0x44) { + dev_priv->card_type = NV_44; + } else if (architecture >= 0x40) { + dev_priv->card_type = NV_40; + } else if (architecture >= 0x34) { + dev_priv->card_type = NV_34; + } else if (architecture >= 0x30) { + dev_priv->card_type = NV_30; + } else if (architecture >= 0x25) { + dev_priv->card_type = NV_25; + } else if (architecture >= 0x20) { + dev_priv->card_type = NV_20; + } else if (architecture >= 0x17) { + dev_priv->card_type = NV_17; + } else if (architecture >= 0x15) { + dev_priv->card_type = NV_15; + } else if (architecture >= 0x11) { + dev_priv->card_type = NV_11; + } else if (architecture >= 0x10) { + dev_priv->card_type = NV_10; + } else if (architecture >= 0x04) { + dev_priv->card_type = NV_04; + } else { + dev_priv->card_type = NV_UNKNOWN; + } + + DRM_INFO("Detected an NV%d generation card\n", dev_priv->card_type); + + if (dev_priv->card_type == NV_UNKNOWN) { + return -EINVAL; + } + + /* Special flags */ + if (dev->pci_device == 0x01a0) { + dev_priv->flags |= NV_NFORCE; + } else if (dev->pci_device == 0x01f0) { + dev_priv->flags |= NV_NFORCE2; + } + dev->dev_private = (void *)dev_priv; + return 0; } -- cgit v1.2.3 From 319436c5cc51a1beb641e899987969fcf912deda Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Thu, 4 Oct 2007 09:39:31 +0200 Subject: nouveau: NV47 context switching voodoo + warning --- shared-core/nv40_graph.c | 169 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index 3f3df515..7ce4273d 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -37,6 +37,7 @@ #define NV41_GRCTX_SIZE (92*1024) #define NV43_GRCTX_SIZE (70*1024) #define NV46_GRCTX_SIZE (70*1024) /* probably ~64KiB */ +#define NV47_GRCTX_SIZE (125*1024) #define NV49_GRCTX_SIZE (164640) #define NV4A_GRCTX_SIZE (64*1024) #define NV4B_GRCTX_SIZE (164640) @@ -565,6 +566,136 @@ nv46_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) INSTANCE_WR(ctx, i/4, 0x3f800000); } +/* This may only work on 7800 AGP cards, will include a warning */ +static void +nv47_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; + + INSTANCE_WR(ctx, 0x00000000/4, ctx->im_pramin->start); + INSTANCE_WR(ctx, 0x00000024/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x00000028/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x00000030/4, 0x00000001); + INSTANCE_WR(ctx, 0x0000011c/4, 0x20010001); + INSTANCE_WR(ctx, 0x00000120/4, 0x0f73ef00); + INSTANCE_WR(ctx, 0x00000128/4, 0x02008821); + INSTANCE_WR(ctx, 0x00000178/4, 0x00000040); + INSTANCE_WR(ctx, 0x0000017c/4, 0x00000040); + INSTANCE_WR(ctx, 0x00000180/4, 0x00000040); + INSTANCE_WR(ctx, 0x00000188/4, 0x00000040); + for (i=0x00000194; i<=0x000001b0; i+=4) + INSTANCE_WR(ctx, i/4, 0x80000000); + INSTANCE_WR(ctx, 0x000001d0/4, 0x0b0b0b0c); + INSTANCE_WR(ctx, 0x00000340/4, 0x00040000); + INSTANCE_WR(ctx, 0x00000350/4, 0x55555555); + INSTANCE_WR(ctx, 0x00000354/4, 0x55555555); + INSTANCE_WR(ctx, 0x00000358/4, 0x55555555); + INSTANCE_WR(ctx, 0x0000035c/4, 0x55555555); + INSTANCE_WR(ctx, 0x00000388/4, 0x00000008); + INSTANCE_WR(ctx, 0x0000039c/4, 0x00001010); + for (i=0x000003c0; i<=0x000003fc; i+=4) + INSTANCE_WR(ctx, i/4, 0x00000111); + INSTANCE_WR(ctx, 0x00000454/4, 0x00000111); + INSTANCE_WR(ctx, 0x00000458/4, 0x00080060); + INSTANCE_WR(ctx, 0x00000474/4, 0x00000080); + INSTANCE_WR(ctx, 0x00000478/4, 0xffff0000); + INSTANCE_WR(ctx, 0x0000047c/4, 0x00000001); + INSTANCE_WR(ctx, 0x00000490/4, 0x46400000); + INSTANCE_WR(ctx, 0x000004a0/4, 0xffff0000); + for (i=0x000004a4; i<=0x000004e0; i+=4) + INSTANCE_WR(ctx, i/4, 0x88888888); + INSTANCE_WR(ctx, 0x000004f4/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x000004f8/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x00000500/4, 0x00011100); + for (i=0x0000051c; i<=0x00000558; i+=4) + INSTANCE_WR(ctx, i/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x00000564/4, 0x4b7fffff); + INSTANCE_WR(ctx, 0x0000058c/4, 0x30201000); + INSTANCE_WR(ctx, 0x00000590/4, 0x70605040); + INSTANCE_WR(ctx, 0x00000594/4, 0xb8a89888); + INSTANCE_WR(ctx, 0x00000598/4, 0xf8e8d8c8); + INSTANCE_WR(ctx, 0x000005ac/4, 0x40100000); + INSTANCE_WR(ctx, 0x000005c8/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x000005fc/4, 0x435185d6); + INSTANCE_WR(ctx, 0x00000600/4, 0x2155b699); + INSTANCE_WR(ctx, 0x00000604/4, 0xfedcba98); + INSTANCE_WR(ctx, 0x00000608/4, 0x00000098); + INSTANCE_WR(ctx, 0x00000618/4, 0xffffffff); + INSTANCE_WR(ctx, 0x0000061c/4, 0x00ff7000); + INSTANCE_WR(ctx, 0x00000620/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x00000630/4, 0x00ff0000); + INSTANCE_WR(ctx, 0x0000066c/4, 0x00ffff00); + for (i=0x000006b0; i<=0x000006ec; i+=4) + INSTANCE_WR(ctx, i/4, 0x00018488); + for (i=0x000006f0; i<=0x0000072c; i+=4) + INSTANCE_WR(ctx, i/4, 0x00028202); + for (i=0x00000770; i<=0x000007ac; i+=4) + INSTANCE_WR(ctx, i/4, 0x0000aae4); + for (i=0x000007b0; i<=0x000007ec; i+=4) + INSTANCE_WR(ctx, i/4, 0x01012000); + for (i=0x000007f0; i<=0x0000082c; i+=4) + INSTANCE_WR(ctx, i/4, 0x00080008); + for (i=0x00000870; i<=0x000008ac; i+=4) + INSTANCE_WR(ctx, i/4, 0x00100008); + INSTANCE_WR(ctx, 0x00000900/4, 0x0001bc80); + INSTANCE_WR(ctx, 0x00000904/4, 0x0001bc80); + INSTANCE_WR(ctx, 0x00000908/4, 0x0001bc80); + INSTANCE_WR(ctx, 0x0000090c/4, 0x0001bc80); + INSTANCE_WR(ctx, 0x00000910/4, 0x00000202); + INSTANCE_WR(ctx, 0x00000914/4, 0x00000202); + INSTANCE_WR(ctx, 0x00000918/4, 0x00000202); + INSTANCE_WR(ctx, 0x0000091c/4, 0x00000202); + for (i=0x00000930; i<=0x0000095c; i+=4) + INSTANCE_WR(ctx, i/4, 0x00000008); + INSTANCE_WR(ctx, 0x00000970/4, 0x00000002); + INSTANCE_WR(ctx, 0x000009a4/4, 0x00000021); + INSTANCE_WR(ctx, 0x000009a8/4, 0x030c30c3); + INSTANCE_WR(ctx, 0x000009b4/4, 0x3e020200); + INSTANCE_WR(ctx, 0x000009b8/4, 0x00ffffff); + INSTANCE_WR(ctx, 0x000009bc/4, 0x40103f00); + INSTANCE_WR(ctx, 0x000009c8/4, 0x00040000); + INSTANCE_WR(ctx, 0x00000a00/4, 0x00008100); + INSTANCE_WR(ctx, 0x00000a8c/4, 0x00000001); + INSTANCE_WR(ctx, 0x00000ad0/4, 0x00001001); + INSTANCE_WR(ctx, 0x00000adc/4, 0x00000003); + INSTANCE_WR(ctx, 0x00000ae0/4, 0x00888001); + for (i=0x00000b10; i<=0x00000b8c; i+=4) + INSTANCE_WR(ctx, i/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00000bb4/4, 0x00000005); + INSTANCE_WR(ctx, 0x00000bc0/4, 0x0000ffff); + for (i=0x00000bdc; i<=0x00000bf8; i+=4) + INSTANCE_WR(ctx, i/4, 0x00005555); + INSTANCE_WR(ctx, 0x00000bfc/4, 0x00000001); + INSTANCE_WR(ctx, 0x00000c34/4, 0x00000001); + INSTANCE_WR(ctx, 0x00000c38/4, 0x08e00001); + INSTANCE_WR(ctx, 0x00000c3c/4, 0x000e3000); + for (i=0x00003000; i<=0x00003078; i+=8) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i=0x00004dc0; i<=0x00006fb0; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for (i=0x00006fc0; i<=0x000073b0; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i=0x00009800; i<=0x0000b9f0; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for (i=0x0000ba00; i<=0x00010430; i+=24) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i=0x00010440; i<=0x00010830; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i=0x00012c80; i<=0x00014e70; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for (i=0x00014e80; i<=0x00015270; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i=0x000176c0; i<=0x000198b0; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for (i=0x000198c0; i<=0x00019cb0; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i=0x0001c100; i<=0x0001e2f0; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for (i=0x0001e300; i<=0x0001e6f0; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); +} + static void nv49_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) { @@ -1361,6 +1492,11 @@ nv40_graph_create_context(struct nouveau_channel *chan) ctx_size = NV46_GRCTX_SIZE; ctx_init = nv46_graph_context_init; break; + case 0x47: + DRM_INFO("NV47 warning: If your card behaves strangely, please come to the irc channel\n"); + ctx_size = NV47_GRCTX_SIZE; + ctx_init = nv47_graph_context_init; + break; case 0x49: ctx_size = NV49_GRCTX_SIZE; ctx_init = nv49_graph_context_init; @@ -1675,6 +1811,38 @@ static uint32_t nv46_ctx_voodoo[] = { 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0 }; +static uint32_t nv47_ctx_voodoo[] = { + 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, + 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409265, 0x00409606, + 0x0040a368, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042, + 0x00200001, 0x0060000a, 0x00700000, 0x001040c5, 0x00401826, 0x00401968, + 0x0060000d, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080, + 0x004020e6, 0x007000a0, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d, + 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4, + 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e, + 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143, + 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d12, + 0x00500060, 0x00403f87, 0x0060000d, 0x00407ce6, 0x002000f0, 0x0060000a, + 0x00200020, 0x00100620, 0x00154650, 0x00104668, 0x0017466d, 0x0011068b, + 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6, + 0x00200022, 0x001006cc, 0x001246f0, 0x002000c0, 0x00100700, 0x0010c3d7, + 0x001043e1, 0x00500060, 0x00200268, 0x0060000a, 0x00104800, 0x00108901, + 0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00144a00, 0x00104a19, + 0x0010ca1c, 0x00110b00, 0x00200028, 0x00100b08, 0x00134c2e, 0x0010cd00, + 0x0010cd04, 0x00120d08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00, + 0x00104f06, 0x00105406, 0x00105709, 0x00200318, 0x0060000a, 0x00300000, + 0x00200680, 0x00407500, 0x00200684, 0x00800001, 0x00200b60, 0x0060000a, + 0x00209540, 0x00407b8a, 0x00201350, 0x00800041, 0x00408c00, 0x00600006, + 0x004088e6, 0x00700080, 0x0020007a, 0x0060000a, 0x00104280, 0x00200318, + 0x0060000a, 0x00200004, 0x00800001, 0x00700000, 0x00200000, 0x0060000a, + 0x00106002, 0x0040a368, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, + 0x00700080, 0x00400a68, 0x00500060, 0x00600007, 0x00409688, 0x0060000f, + 0x00500060, 0x00200000, 0x0060000a, 0x00700000, 0x00106001, 0x0091a880, + 0x00901ffe, 0x10940000, 0x00200020, 0x0060000b, 0x00500069, 0x0060000c, + 0x00402168, 0x0040a506, 0x0040a605, 0x00600009, 0x00700005, 0x00700006, + 0x0060000e, ~0 +}; + //this is used for nv49 and nv4b static uint32_t nv49_4b_ctx_voodoo[] ={ 0x00400564, 0x00400505, 0x00408165, 0x00408206, 0x00409e68, 0x00200020, @@ -1835,6 +2003,7 @@ nv40_graph_init(struct drm_device *dev) case 0x43: ctx_voodoo = nv43_ctx_voodoo; break; case 0x44: ctx_voodoo = nv44_ctx_voodoo; break; case 0x46: ctx_voodoo = nv46_ctx_voodoo; break; + case 0x47: ctx_voodoo = nv47_ctx_voodoo; break; case 0x49: ctx_voodoo = nv49_4b_ctx_voodoo; break; case 0x4a: ctx_voodoo = nv4a_ctx_voodoo; break; case 0x4b: ctx_voodoo = nv49_4b_ctx_voodoo; break; -- cgit v1.2.3 From d351601899e5814d809b8e86ab6f0d6e7676f585 Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Thu, 4 Oct 2007 09:46:16 +0200 Subject: nouveau: Remove excess device classes. --- shared-core/nouveau_drm.h | 3 --- shared-core/nouveau_state.c | 6 ------ 2 files changed, 9 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h index c4f1e9a4..988d467a 100644 --- a/shared-core/nouveau_drm.h +++ b/shared-core/nouveau_drm.h @@ -123,12 +123,9 @@ enum nouveau_card_type { NV_05 =5, NV_10 =10, NV_11 =11, - NV_15 =11, NV_17 =17, NV_20 =20, - NV_25 =20, NV_30 =30, - NV_34 =30, NV_40 =40, NV_44 =44, NV_50 =50, diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index a163ae63..dc075d0c 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -441,18 +441,12 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) dev_priv->card_type = NV_44; } else if (architecture >= 0x40) { dev_priv->card_type = NV_40; - } else if (architecture >= 0x34) { - dev_priv->card_type = NV_34; } else if (architecture >= 0x30) { dev_priv->card_type = NV_30; - } else if (architecture >= 0x25) { - dev_priv->card_type = NV_25; } else if (architecture >= 0x20) { dev_priv->card_type = NV_20; } else if (architecture >= 0x17) { dev_priv->card_type = NV_17; - } else if (architecture >= 0x15) { - dev_priv->card_type = NV_15; } else if (architecture >= 0x11) { dev_priv->card_type = NV_11; } else if (architecture >= 0x10) { -- cgit v1.2.3 From 18952a167014f21545e3fda28ed2c09b09789323 Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Sat, 6 Oct 2007 12:00:08 +0200 Subject: nouveau : print correct value in nouveau_graph_dump_trap_info for nv04 --- shared-core/nouveau_irq.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 45ae6edf..506e8052 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -303,7 +303,11 @@ nouveau_graph_dump_trap_info(struct drm_device *dev) } nsource = NV_READ(NV03_PGRAPH_NSOURCE); nstatus = NV_READ(NV03_PGRAPH_NSTATUS); - if (dev_priv->card_type < NV_50) { + if (dev_priv->card_type < NV_10) { + class = NV_READ(0x400180 + subc*4) & 0xFF; + } else if (dev_priv->card_type < NV_40) { + class = NV_READ(0x400160 + subc*4) & 0xFFF; + } else if (dev_priv->card_type < NV_50) { class = NV_READ(0x400160 + subc*4) & 0xFFFF; } else { class = NV_READ(0x400814); -- cgit v1.2.3 From 20928a2f2b3f1fa15c46edcf7e20f97566664ce8 Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Sun, 7 Oct 2007 19:01:56 +0200 Subject: nouveau: A char is signed, so it may overflow for >NV50. --- shared-core/nouveau_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index dc075d0c..fd80e1e7 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -405,7 +405,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) struct drm_nouveau_private *dev_priv; void __iomem *regs; uint32_t reg0; - char architecture = 0; + uint8_t architecture = 0; dev_priv = drm_calloc(1, sizeof(*dev_priv), DRM_MEM_DRIVER); if (!dev_priv) -- cgit v1.2.3 From 9b294bbe0ec79177298ea32746fbed03fcf62055 Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Wed, 10 Oct 2007 01:12:20 +0200 Subject: nouveau: try to fix big endian. --- shared-core/nouveau_reg.h | 1 + shared-core/nouveau_state.c | 14 +++++++++++--- 2 files changed, 12 insertions(+), 3 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 59b69547..76f5950d 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -57,6 +57,7 @@ # define NV50_FIFO_REGS_DMAGET(i) (NV50_FIFO_REGS(i)+0x44) #define NV03_PMC_BOOT_0 0x00000000 +#define NV03_PMC_BOOT_1 0x00000004 #define NV03_PMC_INTR_0 0x00000100 # define NV_PMC_INTR_0_PFIFO_PENDING (1<< 8) # define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12) diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index fd80e1e7..eec88fe4 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -283,6 +283,10 @@ nouveau_card_init(struct drm_device *dev) ret = nouveau_init_card_mappings(dev); if (ret) return ret; + /* Put the card in BE mode if it's not */ + if (NV_READ(NV03_PMC_BOOT_1)) + NV_WRITE(NV03_PMC_BOOT_1,0x01000001); + /* Determine exact chipset we're running on */ if (dev_priv->card_type < NV_10) dev_priv->chipset = dev_priv->card_type; @@ -404,7 +408,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) { struct drm_nouveau_private *dev_priv; void __iomem *regs; - uint32_t reg0; + uint32_t reg0,reg1; uint8_t architecture = 0; dev_priv = drm_calloc(1, sizeof(*dev_priv), DRM_MEM_DRIVER); @@ -422,7 +426,11 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) DRM_ERROR("Could not ioremap to determine register\n"); return -ENOMEM; } - reg0 = readl(regs); + + reg0 = readl(regs+NV03_PMC_BOOT_0); + reg1 = readl(regs+NV03_PMC_BOOT_1); + if (reg1) + reg0=___swab32(reg0); /* We're dealing with >=NV10 */ if ((reg0 & 0x0f000000) > 0 ) { @@ -457,7 +465,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) dev_priv->card_type = NV_UNKNOWN; } - DRM_INFO("Detected an NV%d generation card\n", dev_priv->card_type); + DRM_INFO("Detected an NV%d generation card (0x%08x)\n", dev_priv->card_type,reg0); if (dev_priv->card_type == NV_UNKNOWN) { return -EINVAL; -- cgit v1.2.3 From d912709a63c59d0b3e48458bac41fb76ea279214 Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Wed, 10 Oct 2007 16:41:21 +0200 Subject: nouveau: PMC_BOOT_1 was not mapped. --- shared-core/nouveau_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index eec88fe4..3ce9247f 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -421,7 +421,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) DRM_DEBUG("vendor: 0x%X device: 0x%X class: 0x%X\n", dev->pci_vendor, dev->pci_device, dev->pdev->class); /* Time to determine the card architecture */ - regs = ioremap_nocache(pci_resource_start(dev->pdev, 0), 0x4); + regs = ioremap_nocache(pci_resource_start(dev->pdev, 0), 0x8); if (!regs) { DRM_ERROR("Could not ioremap to determine register\n"); return -ENOMEM; -- cgit v1.2.3 From bf126f4925bf1601935e085be2feeb004b474a05 Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Wed, 10 Oct 2007 21:11:43 +0200 Subject: nouveau : nv10 and nv04 PGRAPH_NSTATUS are different --- shared-core/nouveau_irq.c | 22 +++++++++++++++++----- shared-core/nouveau_reg.h | 12 ++++++++---- 2 files changed, 25 insertions(+), 9 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 506e8052..dfef718b 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -175,10 +175,18 @@ struct nouveau_bitfield_names static struct nouveau_bitfield_names nouveau_nstatus_names[] = { - { NV03_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" }, - { NV03_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" }, - { NV03_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" }, - { NV03_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" } + { NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" }, + { NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" }, + { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" }, + { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" } +}; + +static struct nouveau_bitfield_names nouveau_nstatus_names_nv10[] = +{ + { NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" }, + { NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" }, + { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" }, + { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" } }; static struct nouveau_bitfield_names nouveau_nsource_names[] = @@ -317,8 +325,12 @@ nouveau_graph_dump_trap_info(struct drm_device *dev) nouveau_print_bitfield_names(nsource, nouveau_nsource_names, ARRAY_SIZE(nouveau_nsource_names)); printk(", nStatus:"); - nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names, + if (dev_priv->card_type < NV_10) + nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names, ARRAY_SIZE(nouveau_nstatus_names)); + else + nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names_nv10, + ARRAY_SIZE(nouveau_nstatus_names_nv10)); printk("\n"); DRM_ERROR("Channel %d/%d (class 0x%04x) - Method 0x%04x, Data 0x%08x:0x%08x\n", diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 76f5950d..4dc3b7fa 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -119,10 +119,14 @@ #define NV10_PGRAPH_DEBUG_4 0x00400090 #define NV03_PGRAPH_INTR 0x00400100 #define NV03_PGRAPH_NSTATUS 0x00400104 -# define NV03_PGRAPH_NSTATUS_STATE_IN_USE (1<<23) -# define NV03_PGRAPH_NSTATUS_INVALID_STATE (1<<24) -# define NV03_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<25) -# define NV03_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<26) +# define NV04_PGRAPH_NSTATUS_STATE_IN_USE (1<<11) +# define NV04_PGRAPH_NSTATUS_INVALID_STATE (1<<12) +# define NV04_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<13) +# define NV04_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<14) +# define NV10_PGRAPH_NSTATUS_STATE_IN_USE (1<<23) +# define NV10_PGRAPH_NSTATUS_INVALID_STATE (1<<24) +# define NV10_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<25) +# define NV10_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<26) #define NV03_PGRAPH_NSOURCE 0x00400108 # define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<< 0) # define NV03_PGRAPH_NSOURCE_DATA_ERROR (1<< 1) -- cgit v1.2.3 From 74001c34e5ad768feec8b2fbe9a617bc598a0a4b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 12 Oct 2007 10:54:38 +1000 Subject: i915: add superioctl support to i915 This adds the initial i915 superioctl interface. The interface should be sufficent even if the implementation may needs fixes/optimisations internally in the drm wrt caching etc. --- shared-core/i915_dma.c | 344 +++++++++++++++++++++++++++++++++++++++++++++++++ shared-core/i915_drm.h | 39 +++++- shared-core/i915_drv.h | 10 +- 3 files changed, 391 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 3a9ecab2..7209a8de 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -147,6 +147,10 @@ static int i915_initialize(struct drm_device * dev, return -EINVAL; } +#ifdef I915_HAVE_BUFFER + dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS; +#endif + dev_priv->sarea_priv = (drm_i915_sarea_t *) ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset); @@ -725,6 +729,343 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data, return 0; } +#ifdef I915_HAVE_BUFFER +struct i915_relocatee_info { + struct drm_buffer_object *buf; + unsigned long offset; + u32 *data_page; + unsigned page_offset; + struct drm_bo_kmap_obj kmap; + int is_iomem; +}; + +static void i915_dereference_buffers_locked(struct drm_buffer_object **buffers, + unsigned num_buffers) +{ + while (num_buffers--) + drm_bo_usage_deref_locked(&buffers[num_buffers]); +} + +int i915_apply_reloc(struct drm_file *file_priv, int num_buffers, + struct drm_buffer_object **buffers, + struct i915_relocatee_info *relocatee, + uint32_t *reloc) +{ + unsigned index; + unsigned long new_cmd_offset; + u32 val; + int ret; + + if (reloc[2] >= num_buffers) { + DRM_ERROR("Illegal relocation buffer %08X\n", reloc[2]); + return -EINVAL; + } + + new_cmd_offset = reloc[0]; + if (!relocatee->data_page || + !drm_bo_same_page(relocatee->offset, new_cmd_offset)) { + drm_bo_kunmap(&relocatee->kmap); + relocatee->offset = new_cmd_offset; + ret = drm_bo_kmap(relocatee->buf, new_cmd_offset >> PAGE_SHIFT, + 1, &relocatee->kmap); + if (ret) { + DRM_ERROR("Could not map command buffer to apply relocs\n %08lx", new_cmd_offset); + return ret; + } + + relocatee->data_page = drm_bmo_virtual(&relocatee->kmap, + &relocatee->is_iomem); + relocatee->page_offset = (relocatee->offset & PAGE_MASK); + } + + val = buffers[reloc[2]]->offset; + index = (reloc[0] - relocatee->page_offset) >> 2; + + /* add in validate */ + val = val + reloc[1]; + + relocatee->data_page[index] = val; + return 0; +} + +int i915_process_relocs(struct drm_file *file_priv, + uint32_t buf_handle, + uint32_t *reloc_buf_handle, + struct i915_relocatee_info *relocatee, + struct drm_buffer_object **buffers, + uint32_t num_buffers) +{ + struct drm_device *dev = file_priv->head->dev; + struct drm_buffer_object *reloc_list_object; + uint32_t cur_handle = *reloc_buf_handle; + uint32_t *reloc_page; + int ret, reloc_is_iomem, reloc_stride; + uint32_t num_relocs, reloc_offset, reloc_end, reloc_page_offset, next_offset, cur_offset; + struct drm_bo_kmap_obj reloc_kmap; + + memset(&reloc_kmap, 0, sizeof(reloc_kmap)); + + reloc_list_object = drm_lookup_buffer_object(file_priv, cur_handle, 1); + if (!reloc_list_object) + return -EINVAL; + + ret = drm_bo_kmap(reloc_list_object, 0, 1, &reloc_kmap); + if (ret) { + DRM_ERROR("Could not map relocation buffer.\n"); + goto out; + } + + reloc_page = drm_bmo_virtual(&reloc_kmap, &reloc_is_iomem); + num_relocs = reloc_page[0] & 0xffff; + + if ((reloc_page[0] >> 16) & 0xffff) { + DRM_ERROR("Unsupported relocation type requested\n"); + goto out; + } + + /* get next relocate buffer handle */ + *reloc_buf_handle = reloc_page[1]; + reloc_stride = I915_RELOC0_STRIDE * sizeof(uint32_t); /* may be different for other types of relocs */ + + DRM_DEBUG("num relocs is %d, next is %08X\n", num_relocs, reloc_page[1]); + + reloc_page_offset = 0; + reloc_offset = I915_RELOC_HEADER * sizeof(uint32_t); + reloc_end = reloc_offset + (num_relocs * reloc_stride); + + do { + next_offset = drm_bo_offset_end(reloc_offset, reloc_end); + + do { + cur_offset = ((reloc_offset + reloc_page_offset) & ~PAGE_MASK) / sizeof(uint32_t); + ret = i915_apply_reloc(file_priv, num_buffers, + buffers, relocatee, &reloc_page[cur_offset]); + if (ret) + goto out; + + reloc_offset += reloc_stride; + } while (reloc_offset < next_offset); + + drm_bo_kunmap(&reloc_kmap); + + reloc_offset = next_offset; + if (reloc_offset != reloc_end) { + ret = drm_bo_kmap(reloc_list_object, reloc_offset >> PAGE_SHIFT, 1, &reloc_kmap); + if (ret) { + DRM_ERROR("Could not map relocation buffer.\n"); + goto out; + } + + reloc_page = drm_bmo_virtual(&reloc_kmap, &reloc_is_iomem); + reloc_page_offset = reloc_offset & ~PAGE_MASK; + } + + } while (reloc_offset != reloc_end); +out: + drm_bo_kunmap(&reloc_kmap); + + mutex_lock(&dev->struct_mutex); + drm_bo_usage_deref_locked(&reloc_list_object); + mutex_unlock(&dev->struct_mutex); + + return ret; +} + +/* + * Validate, add fence and relocate a block of bos from a userspace list + */ +int i915_validate_buffer_list(struct drm_file *file_priv, + unsigned int fence_class, uint64_t data, + struct drm_buffer_object **buffers, + uint32_t *num_buffers) +{ + struct drm_i915_op_arg arg; + struct drm_bo_op_req *req = &arg.d.req; + struct drm_bo_arg_rep rep; + unsigned long next = 0; + int ret = 0; + unsigned buf_count = 0; + struct drm_device *dev = file_priv->head->dev; + uint32_t buf_reloc_handle, buf_handle; + struct i915_relocatee_info relocatee; + + do { + if (buf_count >= *num_buffers) { + DRM_ERROR("Buffer count exceeded %d\n.", *num_buffers); + ret = -EINVAL; + goto out_err; + } + + buffers[buf_count] = NULL; + + if (copy_from_user(&arg, (void __user *)(unsigned)data, sizeof(arg))) { + ret = -EFAULT; + goto out_err; + } + + if (arg.handled) { + data = arg.next; + buffers[buf_count] = drm_lookup_buffer_object(file_priv, req->arg_handle, 1); + buf_count++; + continue; + } + + rep.ret = 0; + if (req->op != drm_bo_validate) { + DRM_ERROR + ("Buffer object operation wasn't \"validate\".\n"); + rep.ret = -EINVAL; + goto out_err; + } + + buf_handle = req->bo_req.handle; + buf_reloc_handle = arg.reloc_handle; + + rep.ret = drm_bo_handle_validate(file_priv, req->bo_req.handle, + req->bo_req.fence_class, + req->bo_req.flags, + req->bo_req.mask, + req->bo_req.hint, + &rep.bo_info, + &buffers[buf_count]); + + if (rep.ret) { + DRM_ERROR("error on handle validate %d\n", rep.ret); + goto out_err; + } + + + next = arg.next; + arg.handled = 1; + arg.d.rep = rep; + + if (copy_to_user((void __user *)(unsigned)data, &arg, sizeof(arg))) + return -EFAULT; + + data = next; + buf_count++; + + if (buf_reloc_handle) { + memset(&relocatee, 0, sizeof(relocatee)); + + relocatee.buf = drm_lookup_buffer_object(file_priv, buf_handle, 1); + if (!relocatee.buf) { + DRM_DEBUG("relocatee buffer invalid %08x\n", buf_handle); + ret = -EINVAL; + goto out_err; + } + + while (buf_reloc_handle) { + ret = i915_process_relocs(file_priv, buf_handle, &buf_reloc_handle, &relocatee, buffers, buf_count); + if (ret) { + DRM_ERROR("process relocs failed\n"); + break; + } + } + + drm_bo_kunmap(&relocatee.kmap); + mutex_lock(&dev->struct_mutex); + drm_bo_usage_deref_locked(&relocatee.buf); + mutex_unlock(&dev->struct_mutex); + + if (ret) + goto out_err; + + } + } while (next != 0); + *num_buffers = buf_count; + return 0; +out_err: + mutex_lock(&dev->struct_mutex); + i915_dereference_buffers_locked(buffers, buf_count); + mutex_unlock(&dev->struct_mutex); + *num_buffers = 0; + return (ret) ? ret : rep.ret; +} + +static int i915_execbuffer(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; + drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) + dev_priv->sarea_priv; + struct drm_i915_execbuffer *exec_buf = data; + struct _drm_i915_batchbuffer *batch = &exec_buf->batch; + struct drm_fence_arg *fence_arg = &exec_buf->fence_arg; + int num_buffers; + int ret; + struct drm_buffer_object **buffers; + struct drm_fence_object *fence; + + if (!dev_priv->allow_batchbuffer) { + DRM_ERROR("Batchbuffer ioctl disabled\n"); + return -EINVAL; + } + + + LOCK_TEST_WITH_RETURN(dev, file_priv); + + if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects, + batch->num_cliprects * + sizeof(struct drm_clip_rect))) + return -EFAULT; + + if (exec_buf->num_buffers > dev_priv->max_validate_buffers) + return -EINVAL; + + num_buffers = exec_buf->num_buffers; + + buffers = drm_calloc(num_buffers, sizeof(struct drm_buffer_object *), DRM_MEM_DRIVER); + if (!buffers) + return -ENOMEM; + + /* validate buffer list + fixup relocations */ + ret = i915_validate_buffer_list(file_priv, 0, exec_buf->ops_list, + buffers, &num_buffers); + if (ret) + goto out_free; + + /* submit buffer */ + batch->start = buffers[num_buffers-1]->offset; + + DRM_DEBUG("i915 exec batchbuffer, start %x used %d cliprects %d\n", + batch->start, batch->used, batch->num_cliprects); + + ret = i915_dispatch_batchbuffer(dev, batch); + if (ret) + goto out_err0; + + sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); + + /* fence */ + ret = drm_fence_buffer_objects(dev, NULL, 0, NULL, &fence); + if (ret) + goto out_err0; + + if (!(fence_arg->flags & DRM_FENCE_FLAG_NO_USER)) { + ret = drm_fence_add_user_object(file_priv, fence, fence_arg->flags & DRM_FENCE_FLAG_SHAREABLE); + if (!ret) { + fence_arg->handle = fence->base.hash.key; + fence_arg->fence_class = fence->fence_class; + fence_arg->type = fence->type; + fence_arg->signaled = fence->signaled; + } + } + drm_fence_usage_deref_unlocked(&fence); +out_err0: + + /* handle errors */ + mutex_lock(&dev->struct_mutex); + i915_dereference_buffers_locked(buffers, num_buffers); + mutex_unlock(&dev->struct_mutex); + +out_free: + drm_free(buffers, (exec_buf->num_buffers * sizeof(struct drm_buffer_object *)), DRM_MEM_DRIVER); + + return ret; +} +#endif + static int i915_do_cleanup_pageflip(struct drm_device * dev) { drm_i915_private_t *dev_priv = dev->dev_private; @@ -977,6 +1318,9 @@ struct drm_ioctl_desc i915_ioctls[] = { DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH), DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH), +#ifdef I915_HAVE_BUFFER + DRM_IOCTL_DEF(DRM_I915_EXECBUFFER, i915_execbuffer, DRM_AUTH), +#endif }; int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h index 9976804e..a6c3cf30 100644 --- a/shared-core/i915_drm.h +++ b/shared-core/i915_drm.h @@ -160,6 +160,7 @@ typedef struct _drm_i915_sarea { #define DRM_I915_VBLANK_SWAP 0x0f #define DRM_I915_MMIO 0x10 #define DRM_I915_HWS_ADDR 0x11 +#define DRM_I915_EXECBUFFER 0x12 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) @@ -177,7 +178,7 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) - +#define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer) /* Asynchronous page flipping: */ @@ -325,4 +326,40 @@ typedef struct drm_i915_hws_addr { uint64_t addr; } drm_i915_hws_addr_t; +/* + * Relocation header is 4 uint32_ts + * 0 - (16-bit relocation type << 16)| 16 bit reloc count + * 1 - buffer handle for another list of relocs + * 2-3 - spare. + */ +#define I915_RELOC_HEADER 4 + +/* + * type 0 relocation has 4-uint32_t stride + * 0 - offset into buffer + * 1 - delta to add in + * 2 - index into buffer list + * 3 - reserved (for optimisations later). + */ +#define I915_RELOC_TYPE_0 0 +#define I915_RELOC0_STRIDE 4 + +struct drm_i915_op_arg { + uint64_t next; + uint32_t reloc_handle; + int handled; + union { + struct drm_bo_op_req req; + struct drm_bo_arg_rep rep; + } d; + +}; + +struct drm_i915_execbuffer { + uint64_t ops_list; + uint32_t num_buffers; + struct _drm_i915_batchbuffer batch; + struct drm_fence_arg fence_arg; +}; + #endif /* _I915_DRM_H_ */ diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 3b26040f..e8f18798 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -56,15 +56,20 @@ * 1.8: New ioctl for ARB_Occlusion_Query * 1.9: Usable page flipping and triple buffering * 1.10: Plane/pipe disentangling + * 1.11: TTM superioctl */ #define DRIVER_MAJOR 1 #if defined(I915_HAVE_FENCE) && defined(I915_HAVE_BUFFER) -#define DRIVER_MINOR 10 +#define DRIVER_MINOR 11 #else #define DRIVER_MINOR 6 #endif #define DRIVER_PATCHLEVEL 0 +#ifdef I915_HAVE_BUFFER +#define I915_MAX_VALIDATE_BUFFERS 4096 +#endif + typedef struct _drm_i915_ring_buffer { int tail_mask; unsigned long Start; @@ -133,10 +138,13 @@ typedef struct drm_i915_private { #endif #ifdef I915_HAVE_BUFFER void *agp_iomap; + unsigned int max_validate_buffers; #endif + DRM_SPINTYPE swaps_lock; drm_i915_vbl_swap_t vbl_swaps; unsigned int swaps_pending; + } drm_i915_private_t; enum intel_chip_family { -- cgit v1.2.3 From 74ea019863c1d08d31eac81d3bfc73e97479b2c5 Mon Sep 17 00:00:00 2001 From: Arthur Huillet Date: Fri, 12 Oct 2007 22:35:39 +0200 Subject: nouveau: added support for software methods, and implemented those necessary for NV04 (TNT1) to start X --- shared-core/nouveau_swmthd.c | 193 +++++++++++++++++++++++++++++++++++++++++++ shared-core/nouveau_swmthd.h | 34 ++++++++ 2 files changed, 227 insertions(+) create mode 100644 shared-core/nouveau_swmthd.c create mode 100644 shared-core/nouveau_swmthd.h (limited to 'shared-core') diff --git a/shared-core/nouveau_swmthd.c b/shared-core/nouveau_swmthd.c new file mode 100644 index 00000000..66ef6233 --- /dev/null +++ b/shared-core/nouveau_swmthd.c @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2007 Arthur Huillet. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/* + * Authors: + * Arthur Huillet + */ + +#include "drmP.h" +#include "drm.h" +#include "nouveau_drm.h" +#include "nouveau_drv.h" +#include "nouveau_reg.h" + +/*TODO: add a "card_type" attribute*/ +typedef struct{ + uint32_t oclass; /* object class for this software method */ + uint32_t mthd; /* method number */ + void (*method_code)(struct drm_device *dev, uint32_t oclass, uint32_t mthd); /* pointer to the function that does the work */ + } nouveau_software_method_t; + + + /* This function handles the NV04 setcontext software methods. +One function for all because they are very similar.*/ +static void nouveau_NV04_setcontext_sw_method(struct drm_device *dev, uint32_t oclass, uint32_t mthd) { + struct drm_nouveau_private *dev_priv = dev->dev_private; + uint32_t inst_loc = NV_READ(NV04_PGRAPH_CTX_SWITCH4) & 0xFFFF; + uint32_t value_to_set = 0, bit_to_set = 0; + + switch ( oclass ) { + case 0x4a: + switch ( mthd ) { + case 0x188 : + case 0x18c : + bit_to_set = 0; + break; + case 0x198 : + bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/ + break; + case 0x2fc : + bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/ + break; + default : ; + }; + break; + case 0x5c: + switch ( mthd ) { + case 0x184: + bit_to_set = 1 << 13; /*USER_CLIP_ENABLE*/ + break; + case 0x188: + case 0x18c: + bit_to_set = 0; + break; + case 0x198: + bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/ + break; + case 0x2fc : + bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/ + break; + }; + break; + case 0x5f: + switch ( mthd ) { + case 0x184 : + bit_to_set = 1 << 12; /*CHROMA_KEY_ENABLE*/ + break; + case 0x188 : + bit_to_set = 1 << 13; /*USER_CLIP_ENABLE*/ + break; + case 0x18c : + case 0x190 : + bit_to_set = 0; + break; + case 0x19c : + bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/ + break; + case 0x2fc : + bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/ + break; + }; + break; + case 0x61: + switch ( mthd ) { + case 0x188 : + bit_to_set = 1 << 13; /*USER_CLIP_ENABLE*/ + break; + case 0x18c : + case 0x190 : + bit_to_set = 0; + break; + case 0x19c : + bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/ + break; + case 0x2fc : + bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/ + break; + }; + break; + case 0x77: + switch ( mthd ) { + case 0x198 : + bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/ + break; + case 0x304 : + bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; //PATCH_CONFIG + break; + }; + break; + default :; + }; + + value_to_set = (NV_READ(0x00700000 | inst_loc << 4))| bit_to_set; + + /*RAMIN*/ + nouveau_wait_for_idle(dev); + NV_WRITE(0x00700000 | inst_loc << 4, value_to_set); + + /*DRM_DEBUG("CTX_SWITCH1 value is %#x\n", NV_READ(NV04_PGRAPH_CTX_SWITCH1));*/ + NV_WRITE(NV04_PGRAPH_CTX_SWITCH1, value_to_set); + + /*DRM_DEBUG("CTX_CACHE1 + xxx value is %#x\n", NV_READ(NV04_PGRAPH_CTX_CACHE1 + (((NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7) << 2)));*/ + NV_WRITE(NV04_PGRAPH_CTX_CACHE1 + (((NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7) << 2), value_to_set); +} + + nouveau_software_method_t nouveau_sw_methods[] = { + /*NV04 context software methods*/ + { 0x4a, 0x188, nouveau_NV04_setcontext_sw_method }, + { 0x4a, 0x18c, nouveau_NV04_setcontext_sw_method }, + { 0x4a, 0x198, nouveau_NV04_setcontext_sw_method }, + { 0x4a, 0x2fc, nouveau_NV04_setcontext_sw_method }, + { 0x5c, 0x184, nouveau_NV04_setcontext_sw_method }, + { 0x5c, 0x188, nouveau_NV04_setcontext_sw_method }, + { 0x5c, 0x18c, nouveau_NV04_setcontext_sw_method }, + { 0x5c, 0x198, nouveau_NV04_setcontext_sw_method }, + { 0x5c, 0x2fc, nouveau_NV04_setcontext_sw_method }, + { 0x5f, 0x184, nouveau_NV04_setcontext_sw_method }, + { 0x5f, 0x188, nouveau_NV04_setcontext_sw_method }, + { 0x5f, 0x18c, nouveau_NV04_setcontext_sw_method }, + { 0x5f, 0x190, nouveau_NV04_setcontext_sw_method }, + { 0x5f, 0x19c, nouveau_NV04_setcontext_sw_method }, + { 0x5f, 0x2fc, nouveau_NV04_setcontext_sw_method }, + { 0x61, 0x188, nouveau_NV04_setcontext_sw_method }, + { 0x61, 0x18c, nouveau_NV04_setcontext_sw_method }, + { 0x61, 0x190, nouveau_NV04_setcontext_sw_method }, + { 0x61, 0x19c, nouveau_NV04_setcontext_sw_method }, + { 0x61, 0x2fc, nouveau_NV04_setcontext_sw_method }, + { 0x77, 0x198, nouveau_NV04_setcontext_sw_method }, + { 0x77, 0x304, nouveau_NV04_setcontext_sw_method }, + /*terminator*/ + { 0x0, 0x0, NULL, }, + }; + + int nouveau_sw_method_execute(struct drm_device *dev, uint32_t oclass, uint32_t method) { + int i = 0; + while ( nouveau_sw_methods[ i ] . method_code != NULL ) + { + if ( nouveau_sw_methods[ i ] . oclass == oclass && nouveau_sw_methods[ i ] . mthd == method ) + { + nouveau_sw_methods[ i ] . method_code(dev, oclass, method); + return 0; + } + i ++; + } + + return 1; + } + + diff --git a/shared-core/nouveau_swmthd.h b/shared-core/nouveau_swmthd.h new file mode 100644 index 00000000..df8c7400 --- /dev/null +++ b/shared-core/nouveau_swmthd.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2007 Arthur Huillet. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/* + * Authors: + * Arthur Huillet + */ + +int nouveau_sw_method_execute(struct drm_device *dev, uint32_t oclass, uint32_t method); /* execute the given software method, returns 0 on success */ + -- cgit v1.2.3 From 9d779e2c88a02f5f9d57618145654610f0f10e28 Mon Sep 17 00:00:00 2001 From: Arthur Huillet Date: Fri, 12 Oct 2007 22:39:58 +0200 Subject: nouveau: mandatory "oops I forgot half of the files" commit --- shared-core/nouveau_irq.c | 21 +++++++++++++++------ shared-core/nv04_graph.c | 25 +++++++++++++++---------- 2 files changed, 30 insertions(+), 16 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index dfef718b..7ba45700 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -35,6 +35,7 @@ #include "nouveau_drm.h" #include "nouveau_drv.h" #include "nouveau_reg.h" +#include "nouveau_swmthd.h" void nouveau_irq_preinstall(struct drm_device *dev) { @@ -340,20 +341,27 @@ nouveau_graph_dump_trap_info(struct drm_device *dev) static void nouveau_pgraph_irq_handler(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t status, nsource; + uint32_t status, nsource, method; + uint32_t obj_class; - status = NV_READ(NV03_PGRAPH_INTR); - if (!status) - return; + while ( (status = NV_READ(NV03_PGRAPH_INTR)) ) { nsource = NV_READ(NV03_PGRAPH_NSOURCE); if (status & NV_PGRAPH_INTR_NOTIFY) { DRM_DEBUG("PGRAPH notify interrupt\n"); - nouveau_graph_dump_trap_info(dev); + if ( dev_priv->card_type == NV_04 && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD ) ) { + /* NV4 (nvidia TNT 1) reports software methods with PGRAPH NOTIFY ILLEGAL_MTHD*/ + method = NV_READ(NV04_PGRAPH_TRAPPED_ADDR) & 0x1FFC; + obj_class = NV_READ(NV04_PGRAPH_CTX_SWITCH1) & 0xFFF; + DRM_DEBUG("Got NV04 software method method %x for class %#x\n", method, obj_class); + if ( nouveau_sw_method_execute(dev, obj_class, method) ) + DRM_ERROR("Unable to execute NV04 software method %x for object class %x. Please report.\n", method, obj_class); + } status &= ~NV_PGRAPH_INTR_NOTIFY; NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY); + NV_WRITE(NV04_PGRAPH_FIFO, 1); } if (status & NV_PGRAPH_INTR_ERROR) { @@ -392,8 +400,9 @@ static void nouveau_pgraph_irq_handler(struct drm_device *dev) DRM_ERROR("Unhandled PGRAPH interrupt: STAT=0x%08x\n", status); NV_WRITE(NV03_PGRAPH_INTR, status); } +NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING); + } - NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING); } static void nouveau_crtc_irq_handler(struct drm_device *dev, int crtc) diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c index 33dd0a86..cffa3e4a 100644 --- a/shared-core/nv04_graph.c +++ b/shared-core/nv04_graph.c @@ -482,16 +482,22 @@ int nv04_graph_init(struct drm_device *dev) { NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF); NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x000001FF); + NV_WRITE(NV04_PGRAPH_VALID1, 0); + NV_WRITE(NV04_PGRAPH_VALID2, 0); + /*NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x000001FF); + NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/ NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x1231c000); - NV_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100); - NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x11d5f870); - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x0004FF31); - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x4004FF31 | - (0x00D00000) | - (1<<29) | - (1<<31)); - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xfad4ff31); + /*1231C000 blob, 001 haiku*/ + //*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/ + NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x72111100); + /*0x72111100 blob , 01 haiku*/ + /*NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/ + NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x11d5f071); + /*haiku same*/ + + /*NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/ + NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x10d4ff31); + /*haiku and blob 10d4*/ NV_WRITE(NV04_PGRAPH_STATE , 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_CTX_CONTROL , 0x10010100); @@ -507,4 +513,3 @@ int nv04_graph_init(struct drm_device *dev) { void nv04_graph_takedown(struct drm_device *dev) { } - -- cgit v1.2.3 From 0d2554f83e72cae1bc44e476fbed4fc78873264f Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Fri, 12 Oct 2007 23:43:31 +0300 Subject: nouveau: Make notifiers go into PCI memory On some hardware notifers in AGP memory just don't work. --- shared-core/nouveau_notifier.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index d3b79683..c361bc69 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -36,17 +36,8 @@ nouveau_notifier_init_channel(struct nouveau_channel *chan) struct drm_nouveau_private *dev_priv = dev->dev_private; int flags, ret; - /*TODO: PCI notifier blocks */ -#ifndef __powerpc__ - if (dev_priv->agp_heap) - flags = NOUVEAU_MEM_AGP; - else -#endif - if (dev_priv->pci_heap) - flags = NOUVEAU_MEM_PCI; - else - flags = NOUVEAU_MEM_FB; - flags |= (NOUVEAU_MEM_MAPPED | NOUVEAU_MEM_FB_ACCEPTABLE); + flags = (NOUVEAU_MEM_PCI | NOUVEAU_MEM_MAPPED | + NOUVEAU_MEM_FB_ACCEPTABLE); chan->notifier_block = nouveau_mem_alloc(dev, 0, PAGE_SIZE, flags, (struct drm_file *)-2); -- cgit v1.2.3 From 50deb31e9ff556f941449bc788821eaa2e5f9e34 Mon Sep 17 00:00:00 2001 From: Stuart Bennett Date: Tue, 9 Oct 2007 20:39:10 +0100 Subject: nouveau: Fix typos in nv20_graph_context_init --- shared-core/nv20_graph.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 9edab594..6b2aa5ad 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -86,11 +86,11 @@ write32 #1 block at +0x00740adc NV_PRAMIN+0x40adc of 3369 (0xd29) elements: INSTANCE_WR(ctx, (0x33c/4)+124+i, 0x00080008); for (i = 0; i < 16; ++i) INSTANCE_WR(ctx, (0x33c/4)+136+i, 0x07ff0000); - INSTANCE_WR(ctx, (0x33c/4)+154, 0x4b7ffff); + INSTANCE_WR(ctx, (0x33c/4)+154, 0x4b7fffff); INSTANCE_WR(ctx, (0x33c/4)+176, 0x00000001); INSTANCE_WR(ctx, (0x33c/4)+178, 0x00004000); INSTANCE_WR(ctx, (0x33c/4)+181, 0x00000001); - INSTANCE_WR(ctx, (0x33c/4)+183, 0x00004000); + INSTANCE_WR(ctx, (0x33c/4)+183, 0x00040000); INSTANCE_WR(ctx, (0x33c/4)+184, 0x00010000); /* -- cgit v1.2.3 From 3ab7627651f4c48a114d91158d41e4c4f528c4cc Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Fri, 12 Oct 2007 23:55:59 +0300 Subject: nouveau: Fix a typo in nv25_graph_context_init --- shared-core/nv20_graph.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 6b2aa5ad..ae0e0858 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -283,7 +283,7 @@ write32 #1 block at +0x00740a7c NV_PRAMIN.GRCTX0+0x35c of 173 (0xad) elements: INSTANCE_WR(ctx, (0x35c/4)+134, 0x00080008); for (i=0; i<16; ++i) INSTANCE_WR(ctx, (0x35c/4)+143+i, 0x07ff0000); - INSTANCE_WR(ctx, (0x35c/4)+161, 0x4b7ffff); + INSTANCE_WR(ctx, (0x35c/4)+161, 0x4b7fffff); /* write32 #1 block at +0x00740d34 NV_PRAMIN.GRCTX0+0x614 of 3136 (0xc40) elements: -- cgit v1.2.3 From 8d3cb7e472ceb31a28de3acc19176e3a2d2995b1 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 14 Oct 2007 21:19:13 +1000 Subject: i915: fix vbl_swap allocation --- shared-core/i915_irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c index 7baa23c0..db18a895 100644 --- a/shared-core/i915_irq.c +++ b/shared-core/i915_irq.c @@ -691,7 +691,7 @@ int i915_vblank_swap(struct drm_device *dev, void *data, return -EBUSY; } - vbl_swap = drm_calloc(1, sizeof(vbl_swap), DRM_MEM_DRIVER); + vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER); if (!vbl_swap) { DRM_ERROR("Failed to allocate memory to queue swap\n"); -- cgit v1.2.3 From 811e43f9e27abdf4c8a4b36c7c287e53134fc950 Mon Sep 17 00:00:00 2001 From: Jeremy Kolb Date: Sun, 14 Oct 2007 10:56:17 -0400 Subject: nouveau: fix warning. --- shared-core/nouveau_mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index dbfba351..e2f0b38d 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -430,7 +430,7 @@ int nouveau_mem_init(struct drm_device *dev) sgreq.size = 16 << 20; //16MB of PCI scatter-gather zone if (drm_sg_alloc(dev, &sgreq)) { - DRM_ERROR("Unable to allocate %dMB of scatter-gather" + DRM_ERROR("Unable to allocate %ldMB of scatter-gather" " pages for PCI DMA!",sgreq.size>>20); } else { if (nouveau_mem_init_heap(&dev_priv->pci_heap, 0, -- cgit v1.2.3 From 837e364353b3137ce87b5cce9c06f05a3d603201 Mon Sep 17 00:00:00 2001 From: Jeremy Kolb Date: Sun, 14 Oct 2007 10:56:31 -0400 Subject: nouveau: fix warning. --- shared-core/nouveau_notifier.c | 1 - 1 file changed, 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_notifier.c b/shared-core/nouveau_notifier.c index c361bc69..31e2b244 100644 --- a/shared-core/nouveau_notifier.c +++ b/shared-core/nouveau_notifier.c @@ -33,7 +33,6 @@ int nouveau_notifier_init_channel(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; int flags, ret; flags = (NOUVEAU_MEM_PCI | NOUVEAU_MEM_MAPPED | -- cgit v1.2.3 From 30353c8efcc026ee8940f3eadab084c42a3acd4e Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Sun, 14 Oct 2007 23:07:30 +0200 Subject: nouveau: PPC fixes. These regs are very touchy. --- shared-core/nouveau_state.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 3ce9247f..add2d598 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -285,7 +285,9 @@ nouveau_card_init(struct drm_device *dev) /* Put the card in BE mode if it's not */ if (NV_READ(NV03_PMC_BOOT_1)) - NV_WRITE(NV03_PMC_BOOT_1,0x01000001); + NV_WRITE(NV03_PMC_BOOT_1,0x00000001); + + DRM_MEMORYBARRIER(); /* Determine exact chipset we're running on */ if (dev_priv->card_type < NV_10) -- cgit v1.2.3 From 6398325ba11da8a01c72f6203af0a2e4b43125c2 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 16 Oct 2007 13:27:27 +1100 Subject: nouveau: Handle multiple PFIFO exceptions per irq, cleanup output. --- shared-core/nouveau_irq.c | 80 +++++++++++++++++++++++------------------------ shared-core/nouveau_mem.c | 3 +- 2 files changed, 40 insertions(+), 43 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 7ba45700..5a696d5e 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -63,58 +63,56 @@ void nouveau_irq_uninstall(struct drm_device *dev) static void nouveau_fifo_irq_handler(struct drm_device *dev) { - uint32_t status, chmode, chstat, channel; struct drm_nouveau_private *dev_priv = dev->dev_private; + uint32_t status; - status = NV_READ(NV03_PFIFO_INTR_0); - if (!status) - return; - chmode = NV_READ(NV04_PFIFO_MODE); - chstat = NV_READ(NV04_PFIFO_DMA); - channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); - - if (status & NV_PFIFO_INTR_CACHE_ERROR) { - uint32_t c1get, c1method, c1data; + while ((status = NV_READ(NV03_PFIFO_INTR_0))) { + uint32_t chid, get; + + NV_WRITE(NV03_PFIFO_CACHES, 0); + + chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & + (nouveau_fifo_number(dev) - 1); + get = NV_READ(NV03_PFIFO_CACHE1_GET); + + if (status & NV_PFIFO_INTR_CACHE_ERROR) { + uint32_t mthd, data; + int ptr; + + ptr = get >> 2; + if (dev_priv->card_type < NV_40) { + mthd = NV_READ(NV04_PFIFO_CACHE1_METHOD(ptr)); + data = NV_READ(NV04_PFIFO_CACHE1_DATA(ptr)); + } else { + mthd = NV_READ(NV40_PFIFO_CACHE1_METHOD(ptr)); + data = NV_READ(NV40_PFIFO_CACHE1_DATA(ptr)); + } - DRM_ERROR("PFIFO error interrupt\n"); + DRM_INFO("PFIFO_CACHE_ERROR - " + "Ch %d/%d Mthd 0x%04x Data 0x%08x\n", + chid, (mthd >> 13) & 7, mthd & 0x1ffc, data); - c1get = NV_READ(NV03_PFIFO_CACHE1_GET) >> 2; - if (dev_priv->card_type < NV_40) { - /* Untested, so it may not work.. */ - c1method = NV_READ(NV04_PFIFO_CACHE1_METHOD(c1get)); - c1data = NV_READ(NV04_PFIFO_CACHE1_DATA(c1get)); - } else { - c1method = NV_READ(NV40_PFIFO_CACHE1_METHOD(c1get)); - c1data = NV_READ(NV40_PFIFO_CACHE1_DATA(c1get)); + status &= ~NV_PFIFO_INTR_CACHE_ERROR; + NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); } - DRM_ERROR("Channel %d/%d - Method 0x%04x, Data 0x%08x\n", - channel, (c1method >> 13) & 7, c1method & 0x1ffc, - c1data); - - status &= ~NV_PFIFO_INTR_CACHE_ERROR; - NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); - } - - if (status & NV_PFIFO_INTR_DMA_PUSHER) { - DRM_ERROR("PFIFO DMA pusher interrupt: ch%d, 0x%08x\n", - channel, NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); + if (status & NV_PFIFO_INTR_DMA_PUSHER) { + DRM_INFO("PFIFO_DMA_PUSHER - Ch %d\n", chid); - status &= ~NV_PFIFO_INTR_DMA_PUSHER; - NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_DMA_PUSHER); + status &= ~NV_PFIFO_INTR_DMA_PUSHER; + NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_DMA_PUSHER); - NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000); - if (NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)!=NV_READ(NV04_PFIFO_CACHE1_DMA_GET)) - { - uint32_t getval=NV_READ(NV04_PFIFO_CACHE1_DMA_GET)+4; - NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET,getval); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000); + if (NV_READ(NV04_PFIFO_CACHE1_DMA_PUT) != get) + NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, get + 4); } - } - if (status) { - DRM_ERROR("Unhandled PFIFO interrupt: status=0x%08x\n", status); + if (status) { + DRM_INFO("Unhandled PFIFO_INTR - 0x%8x\n", status); + NV_WRITE(NV03_PFIFO_INTR_0, status); + } - NV_WRITE(NV03_PFIFO_INTR_0, status); + NV_WRITE(NV03_PFIFO_CACHES, 1); } NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING); diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index e2f0b38d..97691780 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -399,8 +399,7 @@ int nouveau_mem_init(struct drm_device *dev) } /*Note: this is *not* just NV50 code, but only used on NV50 for now */ - if (dev_priv->gart_info.type == NOUVEAU_GART_NONE && - dev_priv->card_type >= NV_50) { + if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) { ret = nouveau_sgdma_init(dev); if (!ret) { ret = nouveau_sgdma_nottm_hack_init(dev); -- cgit v1.2.3 From 3af053779cb0fe9b75a657df76c3dd0cc08966b6 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 16 Oct 2007 13:32:03 +1100 Subject: nouveau: Survive PFIFO_CACHE_ERROR. --- shared-core/nouveau_irq.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 5a696d5e..ea93c3fd 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -92,6 +92,9 @@ static void nouveau_fifo_irq_handler(struct drm_device *dev) "Ch %d/%d Mthd 0x%04x Data 0x%08x\n", chid, (mthd >> 13) & 7, mthd & 0x1ffc, data); + NV_WRITE(NV03_PFIFO_CACHE1_GET, get + 4); + NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 1); + status &= ~NV_PFIFO_INTR_CACHE_ERROR; NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); } -- cgit v1.2.3 From 677753047f2b8a8b0b12bae348a2f4f9718682f1 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 16 Oct 2007 14:42:26 +1100 Subject: nouveau: Cleanup PGRAPH handler, attempt to survive PGRAPH exceptions. --- shared-core/nouveau_irq.c | 214 +++++++++++++++++++++++----------------------- 1 file changed, 105 insertions(+), 109 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index ea93c3fd..ac507299 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -37,7 +37,8 @@ #include "nouveau_reg.h" #include "nouveau_swmthd.h" -void nouveau_irq_preinstall(struct drm_device *dev) +void +nouveau_irq_preinstall(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -45,7 +46,8 @@ void nouveau_irq_preinstall(struct drm_device *dev) NV_WRITE(NV03_PMC_INTR_EN_0, 0); } -void nouveau_irq_postinstall(struct drm_device *dev) +void +nouveau_irq_postinstall(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -53,7 +55,8 @@ void nouveau_irq_postinstall(struct drm_device *dev) NV_WRITE(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE); } -void nouveau_irq_uninstall(struct drm_device *dev) +void +nouveau_irq_uninstall(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -61,7 +64,8 @@ void nouveau_irq_uninstall(struct drm_device *dev) NV_WRITE(NV03_PMC_INTR_EN_0, 0); } -static void nouveau_fifo_irq_handler(struct drm_device *dev) +static void +nouveau_fifo_irq_handler(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t status; @@ -121,56 +125,7 @@ static void nouveau_fifo_irq_handler(struct drm_device *dev) NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING); } -#if 0 -static void nouveau_nv04_context_switch(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t channel,i; - uint32_t max=0; - NV_WRITE(NV04_PGRAPH_FIFO,0x0); - channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); - //DRM_INFO("raw PFIFO_CACH1_PHS1 reg is %x\n",NV_READ(NV03_PFIFO_CACHE1_PUSH1)); - //DRM_INFO("currently on channel %d\n",channel); - for (i=0;ififos[i].used)&&(i!=channel)) { - uint32_t put,get,pending; - //put=NV_READ(dev_priv->ramfc_offset+i*32); - //get=NV_READ(dev_priv->ramfc_offset+4+i*32); - put=NV_READ(NV03_FIFO_REGS_DMAPUT(i)); - get=NV_READ(NV03_FIFO_REGS_DMAGET(i)); - pending=NV_READ(NV04_PFIFO_DMA); - //DRM_INFO("Channel %d (put/get %x/%x)\n",i,put,get); - /* mark all pending channels as such */ - if ((put!=get)&!(pending&(1<cur_fifo=channel; - NV_WRITE(NV04_PFIFO_NEXT_CHANNEL,channel|0x100); -#endif - //NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,max|0x100); - //NV_WRITE(0x2050,max|0x100); - - NV_WRITE(NV04_PGRAPH_FIFO,0x1); - -} -#endif - - -struct nouveau_bitfield_names -{ +struct nouveau_bitfield_names { uint32_t mask; const char * name; }; @@ -290,7 +245,7 @@ nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret) } static void -nouveau_graph_dump_trap_info(struct drm_device *dev) +nouveau_graph_dump_trap_info(struct drm_device *dev, const char *id) { struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t address; @@ -323,7 +278,7 @@ nouveau_graph_dump_trap_info(struct drm_device *dev) class = NV_READ(0x400814); } - DRM_ERROR("nSource:"); + DRM_INFO("%s - nSource:", id); nouveau_print_bitfield_names(nsource, nouveau_nsource_names, ARRAY_SIZE(nouveau_nsource_names)); printk(", nStatus:"); @@ -335,78 +290,118 @@ nouveau_graph_dump_trap_info(struct drm_device *dev) ARRAY_SIZE(nouveau_nstatus_names_nv10)); printk("\n"); - DRM_ERROR("Channel %d/%d (class 0x%04x) - Method 0x%04x, Data 0x%08x:0x%08x\n", - channel, subc, class, method, data2, data); + DRM_INFO("%s - Ch %d/%d Class 0x%04x Mthd 0x%04x Data 0x%08x:0x%08x\n", + id, channel, subc, class, method, data2, data); } -static void nouveau_pgraph_irq_handler(struct drm_device *dev) +static inline void +nouveau_pgraph_intr_notify(struct drm_device *dev, uint32_t nsource) { struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t status, nsource, method; - uint32_t obj_class; + int handled = 0; - while ( (status = NV_READ(NV03_PGRAPH_INTR)) ) { - nsource = NV_READ(NV03_PGRAPH_NSOURCE); + DRM_DEBUG("PGRAPH notify interrupt\n"); + if (dev_priv->card_type == NV_04 && + (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) { + uint32_t class, mthd; - if (status & NV_PGRAPH_INTR_NOTIFY) { - DRM_DEBUG("PGRAPH notify interrupt\n"); + /* NV4 (nvidia TNT 1) reports software methods with + * PGRAPH NOTIFY ILLEGAL_MTHD + */ + mthd = NV_READ(NV04_PGRAPH_TRAPPED_ADDR) & 0x1FFC; + class = NV_READ(NV04_PGRAPH_CTX_SWITCH1) & 0xFFF; + DRM_DEBUG("Got NV04 software method method %x for class %#x\n", + mthd, class); + + if (nouveau_sw_method_execute(dev, class, mthd)) { + DRM_ERROR("Unable to execute NV04 software method %x " + "for object class %x. Please report.\n", + mthd, class); + } else { + handled = 1; + } + } - if ( dev_priv->card_type == NV_04 && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD ) ) { - /* NV4 (nvidia TNT 1) reports software methods with PGRAPH NOTIFY ILLEGAL_MTHD*/ - method = NV_READ(NV04_PGRAPH_TRAPPED_ADDR) & 0x1FFC; - obj_class = NV_READ(NV04_PGRAPH_CTX_SWITCH1) & 0xFFF; - DRM_DEBUG("Got NV04 software method method %x for class %#x\n", method, obj_class); + if (!handled) + nouveau_graph_dump_trap_info(dev, "PGRAPH_NOTIFY"); +} - if ( nouveau_sw_method_execute(dev, obj_class, method) ) - DRM_ERROR("Unable to execute NV04 software method %x for object class %x. Please report.\n", method, obj_class); - } - status &= ~NV_PGRAPH_INTR_NOTIFY; - NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY); - NV_WRITE(NV04_PGRAPH_FIFO, 1); +static inline void +nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource) +{ + nouveau_graph_dump_trap_info(dev, "PGRAPH_ERROR"); +} + +static inline void +nouveau_pgraph_intr_context_switch(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + uint32_t chid; + + chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1); + DRM_DEBUG("PGRAPH context switch interrupt channel %x\n", chid); + + switch(dev_priv->card_type) { + case NV_04: + case NV_05: + nouveau_nv04_context_switch(dev); + break; + case NV_10: + case NV_11: + case NV_17: + nouveau_nv10_context_switch(dev); + break; + default: + DRM_ERROR("Context switch not implemented\n"); + break; } +} - if (status & NV_PGRAPH_INTR_ERROR) { - DRM_ERROR("PGRAPH error interrupt\n"); +static void +nouveau_pgraph_irq_handler(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + uint32_t status; - nouveau_graph_dump_trap_info(dev); + while ((status = NV_READ(NV03_PGRAPH_INTR))) { + uint32_t nsource = NV_READ(NV03_PGRAPH_NSOURCE); - status &= ~NV_PGRAPH_INTR_ERROR; - NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR); - } + if (status & NV_PGRAPH_INTR_NOTIFY) { + nouveau_pgraph_intr_notify(dev, nsource); - if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) { - uint32_t channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); - DRM_DEBUG("PGRAPH context switch interrupt channel %x\n",channel); - switch(dev_priv->card_type) - { - case NV_04: - case NV_05: - nouveau_nv04_context_switch(dev); - break; - case NV_10: - case NV_11: - case NV_17: - nouveau_nv10_context_switch(dev); - break; - default: - DRM_ERROR("Context switch not implemented\n"); - break; + status &= ~NV_PGRAPH_INTR_NOTIFY; + NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY); } - status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; - NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); - } + if (status & NV_PGRAPH_INTR_ERROR) { + nouveau_pgraph_intr_error(dev, nsource); - if (status) { - DRM_ERROR("Unhandled PGRAPH interrupt: STAT=0x%08x\n", status); - NV_WRITE(NV03_PGRAPH_INTR, status); - } -NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING); + status &= ~NV_PGRAPH_INTR_ERROR; + NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR); + } + + if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) { + nouveau_pgraph_intr_context_switch(dev); + + status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; + NV_WRITE(NV03_PGRAPH_INTR, + NV_PGRAPH_INTR_CONTEXT_SWITCH); + } + + if (status) { + DRM_INFO("Unhandled PGRAPH_INTR - 0x%8x\n", status); + NV_WRITE(NV03_PGRAPH_INTR, status); + } + + if ((NV_READ(NV04_PGRAPH_FIFO) & (1 << 0)) == 0) + NV_WRITE(NV04_PGRAPH_FIFO, 1); } + NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING); } -static void nouveau_crtc_irq_handler(struct drm_device *dev, int crtc) +static void +nouveau_crtc_irq_handler(struct drm_device *dev, int crtc) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -419,7 +414,8 @@ static void nouveau_crtc_irq_handler(struct drm_device *dev, int crtc) } } -irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS) +irqreturn_t +nouveau_irq_handler(DRM_IRQ_ARGS) { struct drm_device *dev = (struct drm_device*)arg; struct drm_nouveau_private *dev_priv = dev->dev_private; -- cgit v1.2.3 From 9fdab5b5c512f586012654917438327b3c67eaa4 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 16 Oct 2007 14:43:57 +1100 Subject: nouveau: revert unintended change. --- shared-core/nouveau_mem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 97691780..e2f0b38d 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -399,7 +399,8 @@ int nouveau_mem_init(struct drm_device *dev) } /*Note: this is *not* just NV50 code, but only used on NV50 for now */ - if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) { + if (dev_priv->gart_info.type == NOUVEAU_GART_NONE && + dev_priv->card_type >= NV_50) { ret = nouveau_sgdma_init(dev); if (!ret) { ret = nouveau_sgdma_nottm_hack_init(dev); -- cgit v1.2.3 From 440fc5113ef1ffb1a22bff92cf34eaf23896db8d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=5Butf-8=5D=20Kristian=20H=C3=B8gsberg?= Date: Tue, 9 Oct 2007 21:09:29 -0400 Subject: Eliminate support for fake buffers. --- shared-core/drm.h | 1 - 1 file changed, 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index 19292344..279f858f 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -757,7 +757,6 @@ struct drm_fence_arg { enum drm_bo_type { drm_bo_type_dc, drm_bo_type_user, - drm_bo_type_fake, drm_bo_type_kernel, /* for initial kernel allocations */ }; -- cgit v1.2.3 From dccefba71a65566e7e1628b3be67621866000411 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kristian=20H=C3=B8gsberg?= Date: Tue, 9 Oct 2007 21:09:30 -0400 Subject: Take bo type argument out of the ioctl interface. The buffer object type is still tracked internally, but it is no longer part of the user space visible ioctl interface. If the bo create ioctl specifies a non-NULL buffer address we assume drm_bo_type_user, otherwise drm_bo_type_dc. Kernel side allocations call drm_buffer_object_create() directly and can still specify drm_bo_type_kernel. Not 100% this makes sense either, but with this patch, the buffer type is no longer exported and we can clean up the internals later on. --- shared-core/drm.h | 8 -------- 1 file changed, 8 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index 279f858f..568b1003 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -754,12 +754,6 @@ struct drm_fence_arg { #define DRM_BO_INIT_MINOR 1 -enum drm_bo_type { - drm_bo_type_dc, - drm_bo_type_user, - drm_bo_type_kernel, /* for initial kernel allocations */ -}; - struct drm_bo_info_req { uint64_t mask; uint64_t flags; @@ -775,8 +769,6 @@ struct drm_bo_create_req { uint64_t buffer_start; unsigned int hint; unsigned int page_alignment; - enum drm_bo_type type; - unsigned int pad64; }; struct drm_bo_op_req { -- cgit v1.2.3 From a69c85fec8ed323bffb1324ea08157b3897e97db Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kristian=20H=C3=B8gsberg?= Date: Tue, 9 Oct 2007 21:09:31 -0400 Subject: Drop destroy ioctls for fences and buffer objects. We now always create a drm_ref_object for user objects and this is then the only things that holds a reference to the user object. This way unreference on will destroy the user object when the last drm_ref_object goes way. --- shared-core/drm.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index 568b1003..30650bd9 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -962,7 +962,6 @@ struct drm_mm_init_arg { #define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg) #define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg) -#define DRM_IOCTL_FENCE_DESTROY DRM_IOWR(0xc5, struct drm_fence_arg) #define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg) #define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg) #define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg) @@ -972,7 +971,6 @@ struct drm_mm_init_arg { #define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg) #define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg) -#define DRM_IOCTL_BO_DESTROY DRM_IOWR(0xce, struct drm_bo_handle_arg) #define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg) #define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg) #define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg) -- cgit v1.2.3 From ec1162b212248042bf1317abcb3c47bb10db8aa3 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 17 Oct 2007 15:36:14 +1000 Subject: i915: lock struct mutex about buffer object lookups --- shared-core/i915_dma.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 7209a8de..5a51f6ef 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -805,7 +805,9 @@ int i915_process_relocs(struct drm_file *file_priv, memset(&reloc_kmap, 0, sizeof(reloc_kmap)); + mutex_lock(&dev->struct_mutex); reloc_list_object = drm_lookup_buffer_object(file_priv, cur_handle, 1); + mutex_unlock(&dev->struct_mutex); if (!reloc_list_object) return -EINVAL; @@ -905,7 +907,9 @@ int i915_validate_buffer_list(struct drm_file *file_priv, if (arg.handled) { data = arg.next; + mutex_lock(&dev->struct_mutex); buffers[buf_count] = drm_lookup_buffer_object(file_priv, req->arg_handle, 1); + mutex_unlock(&dev->struct_mutex); buf_count++; continue; } @@ -948,7 +952,9 @@ int i915_validate_buffer_list(struct drm_file *file_priv, if (buf_reloc_handle) { memset(&relocatee, 0, sizeof(relocatee)); + mutex_lock(&dev->struct_mutex); relocatee.buf = drm_lookup_buffer_object(file_priv, buf_handle, 1); + mutex_unlock(&dev->struct_mutex); if (!relocatee.buf) { DRM_DEBUG("relocatee buffer invalid %08x\n", buf_handle); ret = -EINVAL; -- cgit v1.2.3 From 646560d1d112b58899f9e4cab0c966cec7e0b8c3 Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Thu, 4 Oct 2007 09:50:29 +0200 Subject: Revert "Add some more verbosity to drm_bo_set_pin_req comments." This reverts e7bfeb3031374653f7e55d67cc1b5c823849359f commit. --- shared-core/drm.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index 30650bd9..56edaeef 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -786,9 +786,7 @@ struct drm_bo_set_pin_req { unsigned int handle; /** * - 0: Unpin the given buffer object. - * - 1: Pin the given buffer object, requiring that its offset and - * memory area stay constant until unpin. The intended use is for - * scanout buffers. + * - 1: Pin the given buffer object. */ unsigned int pin; }; -- cgit v1.2.3 From 0d1926d36e59ddfc34d8c9c0cdef10b71a49ecf1 Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Thu, 4 Oct 2007 10:14:41 +0200 Subject: Revert "Replace NO_MOVE/NO_EVICT flags to buffer objects with an ioctl to set pinning." This reverts cf2d569daca6954d11a796f4d110148ae2e0c827 commit. --- shared-core/drm.h | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index 56edaeef..021a52e6 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -673,6 +673,14 @@ struct drm_fence_arg { * Can also be set in the buffer mask before validation. */ +/* + * Mask: Never evict this buffer. Not even with force. This type of buffer is only + * available to root and must be manually removed before buffer manager shutdown + * or lock. + * Flags: Acknowledge + */ +#define DRM_BO_FLAG_NO_EVICT (1ULL << 4) + /* * Mask: Require that the buffer is placed in mappable memory when validated. * If not set the buffer may or may not be in mappable memory when validated. @@ -781,16 +789,6 @@ struct drm_bo_op_req { struct drm_bo_info_req bo_req; }; -struct drm_bo_set_pin_req { - /** Buffer object ID */ - unsigned int handle; - /** - * - 0: Unpin the given buffer object. - * - 1: Pin the given buffer object. - */ - unsigned int pin; -}; - /* * Reply flags */ @@ -856,13 +854,6 @@ struct drm_bo_op_arg { unsigned int pad64; }; -struct drm_bo_set_pin_arg { - union { - struct drm_bo_set_pin_req req; - struct drm_bo_info_rep rep; - } d; -}; - #define DRM_BO_MEM_LOCAL 0 #define DRM_BO_MEM_TT 1 #define DRM_BO_MEM_VRAM 2 @@ -976,7 +967,7 @@ struct drm_mm_init_arg { #define DRM_IOCTL_BO_OP DRM_IOWR(0xd3, struct drm_bo_op_arg) #define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg) #define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg) -#define DRM_IOCTL_BO_SET_PIN DRM_IOWR(0xd6, struct drm_bo_set_pin_arg) + /*@}*/ -- cgit v1.2.3 From 086c058a417317491320129d2cbeb68d1cfcfefe Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Wed, 17 Oct 2007 10:55:21 +0200 Subject: Remove the op ioctl, and replace it with a setuser ioctl. Remove need for lock for now. May create races when we clean memory areas or on takedown. Needs to be fixed. Really do a validate on buffer creation in order to avoid problems with fixed memory buffers. --- shared-core/drm.h | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index 021a52e6..0ffd0ad5 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -723,6 +723,7 @@ struct drm_fence_arg { * Flags: Acknowledge. */ #define DRM_BO_FLAG_FORCE_MAPPABLE (1ULL << 14) +#define DRM_BO_FLAG_TILE (1ULL << 15) /* * Memory type flags that can be or'ed together in the mask, but only @@ -755,7 +756,6 @@ struct drm_fence_arg { /* Don't place this buffer on the unfenced list.*/ #define DRM_BO_HINT_DONT_FENCE 0x00000004 #define DRM_BO_HINT_WAIT_LAZY 0x00000008 -#define DRM_BO_HINT_ALLOW_UNFENCED_MAP 0x00000010 #define DRM_BO_INIT_MAGIC 0xfe769812 #define DRM_BO_INIT_MAJOR 0 @@ -768,6 +768,8 @@ struct drm_bo_info_req { unsigned int handle; unsigned int hint; unsigned int fence_class; + unsigned int desired_tile_stride; + unsigned int tile_info; unsigned int pad64; }; @@ -779,15 +781,6 @@ struct drm_bo_create_req { unsigned int page_alignment; }; -struct drm_bo_op_req { - enum { - drm_bo_validate, - drm_bo_fence, - drm_bo_ref_fence, - } op; - unsigned int arg_handle; - struct drm_bo_info_req bo_req; -}; /* * Reply flags @@ -844,6 +837,17 @@ struct drm_bo_map_wait_idle_arg { } d; }; +struct drm_bo_op_req { + enum { + drm_bo_validate, + drm_bo_fence, + drm_bo_ref_fence, + } op; + unsigned int arg_handle; + struct drm_bo_info_req bo_req; +}; + + struct drm_bo_op_arg { uint64_t next; union { @@ -854,6 +858,7 @@ struct drm_bo_op_arg { unsigned int pad64; }; + #define DRM_BO_MEM_LOCAL 0 #define DRM_BO_MEM_TT 1 #define DRM_BO_MEM_VRAM 2 @@ -964,7 +969,7 @@ struct drm_mm_init_arg { #define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg) #define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg) #define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg) -#define DRM_IOCTL_BO_OP DRM_IOWR(0xd3, struct drm_bo_op_arg) +#define DRM_IOCTL_BO_SETSTATUS DRM_IOWR(0xd3, struct drm_bo_map_wait_idle_arg) #define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg) #define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg) -- cgit v1.2.3 From 48b5eaf303b60077faed09db77785d7a544ac335 Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Sat, 20 Oct 2007 16:49:43 +0200 Subject: Simple replacement for hardware lock in some cases. Fix i915 since last commit. --- shared-core/drm.h | 1 + shared-core/i915_dma.c | 1 + 2 files changed, 2 insertions(+) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index 0ffd0ad5..f88192ff 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -872,6 +872,7 @@ struct drm_bo_op_arg { struct drm_mm_type_arg { unsigned int mem_type; + int lock_unlock_bm; }; struct drm_mm_init_arg { diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 5a51f6ef..99d98cd3 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -930,6 +930,7 @@ int i915_validate_buffer_list(struct drm_file *file_priv, req->bo_req.flags, req->bo_req.mask, req->bo_req.hint, + 0, &rep.bo_info, &buffers[buf_count]); -- cgit v1.2.3 From 3b19b50cb5cd31e60eb03e99dd1109b6d0f5b8a3 Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Sun, 21 Oct 2007 12:20:56 +0200 Subject: Remove the need for the hardware lock in the buffer manager. Add interface entry cleaning a memory type without touching NO_EVICT buffers. --- shared-core/drm.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index f88192ff..80c1a3e2 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -870,9 +870,12 @@ struct drm_bo_op_arg { #define DRM_BO_MEM_TYPES 8 /* For now. */ +#define DRM_BO_LOCK_UNLOCK_BM (1 << 0) +#define DRM_BO_LOCK_IGNORE_NO_EVICT (1 << 1) + struct drm_mm_type_arg { unsigned int mem_type; - int lock_unlock_bm; + unsigned int lock_flags; }; struct drm_mm_init_arg { -- cgit v1.2.3 From 9ddff6d15fdff571193aac10ef81e67798fd712d Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Sun, 21 Oct 2007 12:26:26 +0200 Subject: Adapt i915 super-ioctl for lock-free operation. --- shared-core/i915_dma.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 99d98cd3..14a91f36 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -1010,8 +1010,6 @@ static int i915_execbuffer(struct drm_device *dev, void *data, } - LOCK_TEST_WITH_RETURN(dev, file_priv); - if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects, batch->num_cliprects * sizeof(struct drm_clip_rect))) @@ -1020,11 +1018,18 @@ static int i915_execbuffer(struct drm_device *dev, void *data, if (exec_buf->num_buffers > dev_priv->max_validate_buffers) return -EINVAL; + + ret = drm_bo_read_lock(&dev->bm.bm_lock); + if (ret) + return ret; + num_buffers = exec_buf->num_buffers; buffers = drm_calloc(num_buffers, sizeof(struct drm_buffer_object *), DRM_MEM_DRIVER); - if (!buffers) + if (!buffers) { + drm_bo_read_unlock(&dev->bm.bm_lock); return -ENOMEM; + } /* validate buffer list + fixup relocations */ ret = i915_validate_buffer_list(file_priv, 0, exec_buf->ops_list, @@ -1068,7 +1073,7 @@ out_err0: out_free: drm_free(buffers, (exec_buf->num_buffers * sizeof(struct drm_buffer_object *)), DRM_MEM_DRIVER); - + drm_bo_read_unlock(&dev->bm.bm_lock); return ret; } #endif -- cgit v1.2.3 From 22883ff26b8a45ab2bec60accc4b822cf6b4f214 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 22 Oct 2007 11:54:41 +1100 Subject: i915: split reloc execution into separate function --- shared-core/i915_dma.c | 65 ++++++++++++++++++++++++++++++-------------------- 1 file changed, 39 insertions(+), 26 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 5a51f6ef..d0d65f8c 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -873,6 +873,43 @@ out: return ret; } +static int i915_exec_reloc(struct drm_file *file_priv, drm_handle_t buf_handle, + drm_handle_t buf_reloc_handle, + struct drm_buffer_object **buffers, + uint32_t buf_count) +{ + struct drm_device *dev = file_priv->head->dev; + struct i915_relocatee_info relocatee; + int ret = 0; + + memset(&relocatee, 0, sizeof(relocatee)); + + mutex_lock(&dev->struct_mutex); + relocatee.buf = drm_lookup_buffer_object(file_priv, buf_handle, 1); + mutex_unlock(&dev->struct_mutex); + if (!relocatee.buf) { + DRM_DEBUG("relocatee buffer invalid %08x\n", buf_handle); + ret = -EINVAL; + goto out_err; + } + + while (buf_reloc_handle) { + ret = i915_process_relocs(file_priv, buf_handle, &buf_reloc_handle, &relocatee, buffers, buf_count); + if (ret) { + DRM_ERROR("process relocs failed\n"); + break; + } + } + + drm_bo_kunmap(&relocatee.kmap); + mutex_lock(&dev->struct_mutex); + drm_bo_usage_deref_locked(&relocatee.buf); + mutex_unlock(&dev->struct_mutex); + +out_err: + return ret; +} + /* * Validate, add fence and relocate a block of bos from a userspace list */ @@ -889,7 +926,7 @@ int i915_validate_buffer_list(struct drm_file *file_priv, unsigned buf_count = 0; struct drm_device *dev = file_priv->head->dev; uint32_t buf_reloc_handle, buf_handle; - struct i915_relocatee_info relocatee; + do { if (buf_count >= *num_buffers) { @@ -950,33 +987,9 @@ int i915_validate_buffer_list(struct drm_file *file_priv, buf_count++; if (buf_reloc_handle) { - memset(&relocatee, 0, sizeof(relocatee)); - - mutex_lock(&dev->struct_mutex); - relocatee.buf = drm_lookup_buffer_object(file_priv, buf_handle, 1); - mutex_unlock(&dev->struct_mutex); - if (!relocatee.buf) { - DRM_DEBUG("relocatee buffer invalid %08x\n", buf_handle); - ret = -EINVAL; - goto out_err; - } - - while (buf_reloc_handle) { - ret = i915_process_relocs(file_priv, buf_handle, &buf_reloc_handle, &relocatee, buffers, buf_count); - if (ret) { - DRM_ERROR("process relocs failed\n"); - break; - } - } - - drm_bo_kunmap(&relocatee.kmap); - mutex_lock(&dev->struct_mutex); - drm_bo_usage_deref_locked(&relocatee.buf); - mutex_unlock(&dev->struct_mutex); - + ret = i915_exec_reloc(file_priv, buf_handle, buf_reloc_handle, buffers, buf_count); if (ret) goto out_err; - } } while (next != 0); *num_buffers = buf_count; -- cgit v1.2.3 From 919c886b2b7728768720aac93e0f6fd1acb8b2df Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Mon, 22 Oct 2007 18:59:37 +0200 Subject: A cmdbuf mutex to implement validate-submit-fence atomicity in the absence of a hardware lock. --- shared-core/i915_dma.c | 15 +++++++++++++++ shared-core/i915_drv.h | 1 + 2 files changed, 16 insertions(+) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 14a91f36..d07be6e0 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -213,6 +213,7 @@ static int i915_initialize(struct drm_device * dev, } DRM_DEBUG("Enabled hardware status page\n"); dev->dev_private = (void *)dev_priv; + mutex_init(&dev_priv->cmdbuf_mutex); return 0; } @@ -1023,11 +1024,23 @@ static int i915_execbuffer(struct drm_device *dev, void *data, if (ret) return ret; + /* + * The cmdbuf_mutex makes sure the validate-submit-fence + * operation is atomic. + */ + + ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex); + if (ret) { + drm_bo_read_unlock(&dev->bm.bm_lock); + return -EAGAIN; + } + num_buffers = exec_buf->num_buffers; buffers = drm_calloc(num_buffers, sizeof(struct drm_buffer_object *), DRM_MEM_DRIVER); if (!buffers) { drm_bo_read_unlock(&dev->bm.bm_lock); + mutex_unlock(&dev_priv->cmdbuf_mutex); return -ENOMEM; } @@ -1073,6 +1086,8 @@ out_err0: out_free: drm_free(buffers, (exec_buf->num_buffers * sizeof(struct drm_buffer_object *)), DRM_MEM_DRIVER); + + mutex_unlock(&dev_priv->cmdbuf_mutex); drm_bo_read_unlock(&dev->bm.bm_lock); return ret; } diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index e8f18798..817288b6 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -139,6 +139,7 @@ typedef struct drm_i915_private { #ifdef I915_HAVE_BUFFER void *agp_iomap; unsigned int max_validate_buffers; + struct mutex cmdbuf_mutex; #endif DRM_SPINTYPE swaps_lock; -- cgit v1.2.3 From 9a115080e870f8196adef4a19598343e63e61e45 Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Tue, 23 Oct 2007 02:18:56 +0200 Subject: nouveau: fix IGP --- shared-core/nouveau_mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index e2f0b38d..448b69d3 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -223,7 +223,7 @@ void nouveau_mem_close(struct drm_device *dev) static uint32_t nouveau_mem_fb_amount_igp(struct drm_device *dev) { -#if defined(LINUX) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)) +#if defined(__linux__) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)) struct drm_nouveau_private *dev_priv = dev->dev_private; struct pci_dev *bridge; uint32_t mem; -- cgit v1.2.3 From a294aa724a1e932fb6017383e08532bfcc914df0 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 23 Oct 2007 17:54:07 +1000 Subject: i915: require mfence before submitting batchbuffer --- shared-core/i915_dma.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index d0d65f8c..f0fd6037 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -1044,6 +1044,9 @@ static int i915_execbuffer(struct drm_device *dev, void *data, if (ret) goto out_free; + /* make sure all previous memory operations have passed */ + asm volatile("mfence":::"memory"); + /* submit buffer */ batch->start = buffers[num_buffers-1]->offset; -- cgit v1.2.3 From fd7c24753c4020a0022aaa183cfe8fc04a307abd Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 24 Oct 2007 11:13:15 +1100 Subject: i915: use a drm memory barrier define --- shared-core/i915_dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index f0fd6037..9bc7431d 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -1045,7 +1045,7 @@ static int i915_execbuffer(struct drm_device *dev, void *data, goto out_free; /* make sure all previous memory operations have passed */ - asm volatile("mfence":::"memory"); + DRM_MEMORYBARRIER(); /* submit buffer */ batch->start = buffers[num_buffers-1]->offset; -- cgit v1.2.3 From 83199c257ea68a7cc0c6928109ff77bf25131819 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 24 Oct 2007 16:27:46 -0700 Subject: Fix missing \n on some DRM_ERROR in i915_dma.c --- shared-core/i915_dma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 9bc7431d..eb8c9153 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -494,7 +494,7 @@ static int i915_dispatch_cmdbuffer(struct drm_device * dev, int i = 0, count, ret; if (cmd->sz & 0x3) { - DRM_ERROR("alignment"); + DRM_ERROR("alignment\n"); return -EINVAL; } @@ -532,7 +532,7 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev, RING_LOCALS; if ((batch->start | batch->used) & 0x7) { - DRM_ERROR("alignment"); + DRM_ERROR("alignment\n"); return -EINVAL; } -- cgit v1.2.3 From c5f158abbe97492f56eb60ac54679945e9d6ddae Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 25 Oct 2007 16:52:33 +1000 Subject: i915: remove relocatee kernel mapping sooner stops mutex taking during sleep --- shared-core/i915_dma.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index eb8c9153..acbb41dc 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -864,6 +864,9 @@ int i915_process_relocs(struct drm_file *file_priv, } while (reloc_offset != reloc_end); out: + drm_bo_kunmap(&relocatee->kmap); + relocatee->data_page = NULL; + drm_bo_kunmap(&reloc_kmap); mutex_lock(&dev->struct_mutex); @@ -901,7 +904,6 @@ static int i915_exec_reloc(struct drm_file *file_priv, drm_handle_t buf_handle, } } - drm_bo_kunmap(&relocatee.kmap); mutex_lock(&dev->struct_mutex); drm_bo_usage_deref_locked(&relocatee.buf); mutex_unlock(&dev->struct_mutex); -- cgit v1.2.3 From a70fe82baf0ca2be98e02680cff489f90b0ea3de Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 25 Oct 2007 16:53:18 +1000 Subject: i915: relocate buffers before validation add memory barrier between two --- shared-core/i915_dma.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index acbb41dc..1e15e7ce 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -964,6 +964,13 @@ int i915_validate_buffer_list(struct drm_file *file_priv, buf_handle = req->bo_req.handle; buf_reloc_handle = arg.reloc_handle; + if (buf_reloc_handle) { + ret = i915_exec_reloc(file_priv, buf_handle, buf_reloc_handle, buffers, buf_count); + if (ret) + goto out_err; + DRM_MEMORYBARRIER(); + } + rep.ret = drm_bo_handle_validate(file_priv, req->bo_req.handle, req->bo_req.fence_class, req->bo_req.flags, @@ -988,11 +995,6 @@ int i915_validate_buffer_list(struct drm_file *file_priv, data = next; buf_count++; - if (buf_reloc_handle) { - ret = i915_exec_reloc(file_priv, buf_handle, buf_reloc_handle, buffers, buf_count); - if (ret) - goto out_err; - } } while (next != 0); *num_buffers = buf_count; return 0; -- cgit v1.2.3 From 11f3e5e53f8fc4de90d1c289e0ba218ddfca23dc Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Thu, 25 Oct 2007 10:12:21 +0200 Subject: Buffer manager: Implement a version check IOCTL for drivers that don't use drmMMInit from user-space. Remove the minor check from the kernel code. That's really up to the driver. Bump major. --- shared-core/drm.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index 80c1a3e2..a48f347e 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -758,8 +758,9 @@ struct drm_fence_arg { #define DRM_BO_HINT_WAIT_LAZY 0x00000008 #define DRM_BO_INIT_MAGIC 0xfe769812 -#define DRM_BO_INIT_MAJOR 0 +#define DRM_BO_INIT_MAJOR 1 #define DRM_BO_INIT_MINOR 1 +#define DRM_BO_INIT_PATCH 0 struct drm_bo_info_req { @@ -873,6 +874,12 @@ struct drm_bo_op_arg { #define DRM_BO_LOCK_UNLOCK_BM (1 << 0) #define DRM_BO_LOCK_IGNORE_NO_EVICT (1 << 1) +struct drm_bo_version_arg { + uint32_t major; + uint32_t minor; + uint32_t patchlevel; +}; + struct drm_mm_type_arg { unsigned int mem_type; unsigned int lock_flags; @@ -976,6 +983,7 @@ struct drm_mm_init_arg { #define DRM_IOCTL_BO_SETSTATUS DRM_IOWR(0xd3, struct drm_bo_map_wait_idle_arg) #define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg) #define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg) +#define DRM_IOCTL_BO_VERSION DRM_IOR(0xd6, struct drm_bo_version_arg) /*@}*/ -- cgit v1.2.3 From b9d9c30474238ac8ba4899a19fe4a97e9376f6c4 Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Thu, 25 Oct 2007 10:29:15 +0200 Subject: Tighten permissions on some buffer manager ioctls. Set bo init minor to 0. Add the version function to header. --- shared-core/drm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index a48f347e..ae88ce61 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -759,7 +759,7 @@ struct drm_fence_arg { #define DRM_BO_INIT_MAGIC 0xfe769812 #define DRM_BO_INIT_MAJOR 1 -#define DRM_BO_INIT_MINOR 1 +#define DRM_BO_INIT_MINOR 0 #define DRM_BO_INIT_PATCH 0 -- cgit v1.2.3 From b9d8ddd3ca587e87474d37637096b9ebd0a927e9 Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Fri, 26 Oct 2007 15:11:38 +0200 Subject: nouveau: flip the CHECK_STATE bit off on nv30. This lets you do 8-bit surface destination. --- shared-core/nv20_graph.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index ae0e0858..94ce32c1 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -28,7 +28,7 @@ #define NV25_GRCTX_SIZE (3529*4) #define NV2A_GRCTX_SIZE (3500*4) -#define NV30_31_GRCTX_SIZE (22392) +#define NV30_31_GRCTX_SIZE (24392) #define NV34_GRCTX_SIZE (18140) #define NV35_36_GRCTX_SIZE (22396) @@ -3312,7 +3312,7 @@ int nv30_graph_init(struct drm_device *dev) NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x401287c0); NV_WRITE(0x400890, 0x01b463ff); - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xf3de0475); + NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xf2de0475); NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000); NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); NV_WRITE(0x400B80, 0x1003d888); -- cgit v1.2.3 From 1e2a2bababf3fbaa0a665983856761c2284dba30 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Fri, 26 Oct 2007 16:10:02 -0700 Subject: i915: suspend/resume support Add suspend/resume support to the i915 driver. Moves some of the initialization into the driver load routine, and fixes up places where we assumed no dev_private existed in some of the cleanup paths. This allows us to suspend/resume properly even if X isn't running. --- shared-core/i915_dma.c | 112 +++++---- shared-core/i915_drv.h | 663 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 721 insertions(+), 54 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index b1168635..24a4ec4a 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -31,17 +31,6 @@ #include "i915_drm.h" #include "i915_drv.h" -#define IS_I965G(dev) (dev->pci_device == 0x2972 || \ - dev->pci_device == 0x2982 || \ - dev->pci_device == 0x2992 || \ - dev->pci_device == 0x29A2 || \ - dev->pci_device == 0x2A02 || \ - dev->pci_device == 0x2A12) - -#define IS_G33(dev) (dev->pci_device == 0x29C2 || \ - dev->pci_device == 0x29B2 || \ - dev->pci_device == 0x29D2) - /* Really want an OS-independent resettable timer. Would like to have * this loop run for (eg) 3 sec, but have the timer reset every time * the head pointer changes, so that EBUSY only happens if the ring @@ -91,6 +80,7 @@ void i915_kernel_lost_context(struct drm_device * dev) static int i915_dma_cleanup(struct drm_device * dev) { + drm_i915_private_t *dev_priv = dev->dev_private; /* Make sure interrupts are disabled here because the uninstall ioctl * may not have been called from userspace and after dev_private * is freed, it's too late. @@ -98,50 +88,42 @@ static int i915_dma_cleanup(struct drm_device * dev) if (dev->irq) drm_irq_uninstall(dev); - if (dev->dev_private) { - drm_i915_private_t *dev_priv = - (drm_i915_private_t *) dev->dev_private; - - if (dev_priv->ring.virtual_start) { - drm_core_ioremapfree(&dev_priv->ring.map, dev); - } + if (dev_priv->ring.virtual_start) { + drm_core_ioremapfree(&dev_priv->ring.map, dev); + dev_priv->ring.virtual_start = 0; + dev_priv->ring.map.handle = 0; + dev_priv->ring.map.size = 0; + } - if (dev_priv->status_page_dmah) { - drm_pci_free(dev, dev_priv->status_page_dmah); - /* Need to rewrite hardware status page */ - I915_WRITE(0x02080, 0x1ffff000); - } - if (dev_priv->status_gfx_addr) { - dev_priv->status_gfx_addr = 0; - drm_core_ioremapfree(&dev_priv->hws_map, dev); - I915_WRITE(0x02080, 0x1ffff000); - } - drm_free(dev->dev_private, sizeof(drm_i915_private_t), - DRM_MEM_DRIVER); + if (dev_priv->status_page_dmah) { + drm_pci_free(dev, dev_priv->status_page_dmah); + dev_priv->status_page_dmah = NULL; + /* Need to rewrite hardware status page */ + I915_WRITE(0x02080, 0x1ffff000); + } - dev->dev_private = NULL; + if (dev_priv->status_gfx_addr) { + dev_priv->status_gfx_addr = 0; + drm_core_ioremapfree(&dev_priv->hws_map, dev); + I915_WRITE(0x02080, 0x1ffff000); } return 0; } -static int i915_initialize(struct drm_device * dev, - drm_i915_private_t * dev_priv, - drm_i915_init_t * init) +static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) { - memset(dev_priv, 0, sizeof(drm_i915_private_t)); + drm_i915_private_t *dev_priv = dev->dev_private; dev_priv->sarea = drm_getsarea(dev); if (!dev_priv->sarea) { DRM_ERROR("can not find sarea!\n"); - dev->dev_private = (void *)dev_priv; i915_dma_cleanup(dev); return -EINVAL; } dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); if (!dev_priv->mmio_map) { - dev->dev_private = (void *)dev_priv; i915_dma_cleanup(dev); DRM_ERROR("can not find mmio map!\n"); return -EINVAL; @@ -168,7 +150,6 @@ static int i915_initialize(struct drm_device * dev, drm_core_ioremap(&dev_priv->ring.map, dev); if (dev_priv->ring.map.handle == NULL) { - dev->dev_private = (void *)dev_priv; i915_dma_cleanup(dev); DRM_ERROR("can not ioremap virtual address for" " ring buffer\n"); @@ -199,7 +180,6 @@ static int i915_initialize(struct drm_device * dev, drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); if (!dev_priv->status_page_dmah) { - dev->dev_private = (void *)dev_priv; i915_dma_cleanup(dev); DRM_ERROR("Can not allocate hardware status page\n"); return -ENOMEM; @@ -212,7 +192,6 @@ static int i915_initialize(struct drm_device * dev, I915_WRITE(0x02080, dev_priv->dma_status_page); } DRM_DEBUG("Enabled hardware status page\n"); - dev->dev_private = (void *)dev_priv; mutex_init(&dev_priv->cmdbuf_mutex); return 0; } @@ -258,17 +237,12 @@ static int i915_dma_resume(struct drm_device * dev) static int i915_dma_init(struct drm_device *dev, void *data, struct drm_file *file_priv) { - drm_i915_private_t *dev_priv; drm_i915_init_t *init = data; int retcode = 0; switch (init->func) { case I915_INIT_DMA: - dev_priv = drm_alloc(sizeof(drm_i915_private_t), - DRM_MEM_DRIVER); - if (dev_priv == NULL) - return -ENOMEM; - retcode = i915_initialize(dev, dev_priv, init); + retcode = i915_initialize(dev, init); break; case I915_CLEANUP_DMA: retcode = i915_dma_cleanup(dev); @@ -1299,7 +1273,6 @@ static int i915_set_status_page(struct drm_device *dev, void *data, drm_core_ioremap(&dev_priv->hws_map, dev); if (dev_priv->hws_map.handle == NULL) { - dev->dev_private = (void *)dev_priv; i915_dma_cleanup(dev); dev_priv->status_gfx_addr = 0; DRM_ERROR("can not ioremap virtual address for" @@ -1318,6 +1291,10 @@ static int i915_set_status_page(struct drm_device *dev, void *data, int i915_driver_load(struct drm_device *dev, unsigned long flags) { + struct drm_i915_private *dev_priv = dev->dev_private; + unsigned long base, size; + int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1; + /* i915 has 4 more counters */ dev->counters += 4; dev->types[6] = _DRM_STAT_IRQ; @@ -1325,25 +1302,52 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) dev->types[8] = _DRM_STAT_SECONDARY; dev->types[9] = _DRM_STAT_DMA; + dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER); + if (dev_priv == NULL) + return -ENOMEM; + + memset(dev_priv, 0, sizeof(drm_i915_private_t)); + + dev->dev_private = (void *)dev_priv; + + /* Add register map (needed for suspend/resume) */ + base = drm_get_resource_start(dev, mmio_bar); + size = drm_get_resource_len(dev, mmio_bar); + + ret = drm_addmap(dev, base, size, _DRM_REGISTERS, _DRM_KERNEL, + &dev_priv->mmio_map); + + return ret; +} + +int i915_driver_unload(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (dev_priv->mmio_map) + drm_rmmap(dev, dev_priv->mmio_map); + + drm_free(dev->dev_private, sizeof(drm_i915_private_t), + DRM_MEM_DRIVER); return 0; } void i915_driver_lastclose(struct drm_device * dev) { - if (dev->dev_private) { - drm_i915_private_t *dev_priv = dev->dev_private; + drm_i915_private_t *dev_priv = dev->dev_private; + + if (drm_getsarea(dev) && dev_priv->sarea_priv) i915_do_cleanup_pageflip(dev); + if (dev_priv->agp_heap) i915_mem_takedown(&(dev_priv->agp_heap)); - } + i915_dma_cleanup(dev); } void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) { - if (dev->dev_private) { - drm_i915_private_t *dev_priv = dev->dev_private; - i915_mem_release(dev, file_priv, dev_priv->agp_heap); - } + drm_i915_private_t *dev_priv = dev->dev_private; + i915_mem_release(dev, file_priv, dev_priv->agp_heap); } struct drm_ioctl_desc i915_ioctls[] = { diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 817288b6..07a173ac 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -146,6 +146,88 @@ typedef struct drm_i915_private { drm_i915_vbl_swap_t vbl_swaps; unsigned int swaps_pending; + /* Register state */ + u8 saveLBB; + u32 saveDSPACNTR; + u32 saveDSPBCNTR; + u32 savePIPEACONF; + u32 savePIPEBCONF; + u32 savePIPEASRC; + u32 savePIPEBSRC; + u32 saveFPA0; + u32 saveFPA1; + u32 saveDPLL_A; + u32 saveDPLL_A_MD; + u32 saveHTOTAL_A; + u32 saveHBLANK_A; + u32 saveHSYNC_A; + u32 saveVTOTAL_A; + u32 saveVBLANK_A; + u32 saveVSYNC_A; + u32 saveBCLRPAT_A; + u32 saveDSPASTRIDE; + u32 saveDSPASIZE; + u32 saveDSPAPOS; + u32 saveDSPABASE; + u32 saveDSPASURF; + u32 saveDSPATILEOFF; + u32 savePFIT_PGM_RATIOS; + u32 saveBLC_PWM_CTL; + u32 saveBLC_PWM_CTL2; + u32 saveFPB0; + u32 saveFPB1; + u32 saveDPLL_B; + u32 saveDPLL_B_MD; + u32 saveHTOTAL_B; + u32 saveHBLANK_B; + u32 saveHSYNC_B; + u32 saveVTOTAL_B; + u32 saveVBLANK_B; + u32 saveVSYNC_B; + u32 saveBCLRPAT_B; + u32 saveDSPBSTRIDE; + u32 saveDSPBSIZE; + u32 saveDSPBPOS; + u32 saveDSPBBASE; + u32 saveDSPBSURF; + u32 saveDSPBTILEOFF; + u32 saveVCLK_DIVISOR_VGA0; + u32 saveVCLK_DIVISOR_VGA1; + u32 saveVCLK_POST_DIV; + u32 saveVGACNTRL; + u32 saveADPA; + u32 saveLVDS; + u32 saveLVDSPP_ON; + u32 saveLVDSPP_OFF; + u32 saveDVOA; + u32 saveDVOB; + u32 saveDVOC; + u32 savePP_ON; + u32 savePP_OFF; + u32 savePP_CONTROL; + u32 savePP_CYCLE; + u32 savePFIT_CONTROL; + u32 save_palette_a[256]; + u32 save_palette_b[256]; + u32 saveFBC_CFB_BASE; + u32 saveFBC_LL_BASE; + u32 saveFBC_CONTROL; + u32 saveFBC_CONTROL2; + u32 saveSWF0[16]; + u32 saveSWF1[16]; + u32 saveSWF2[3]; + u8 saveMSR; + u8 saveSR[8]; + u8 saveGR[24]; + u8 saveAR_INDEX; + u8 saveAR[20]; + u8 saveDACMASK; + u8 saveDACDATA[256*3]; /* 256 3-byte colors */ + u8 saveCR[36]; + u8 savePLANE0[64*1024]; + u8 savePLANE1[64*1024]; + u8 savePLANE2[64*1024]; + u8 savePLANE3[64*1024]; } drm_i915_private_t; enum intel_chip_family { @@ -161,6 +243,7 @@ extern int i915_max_ioctl; /* i915_dma.c */ extern void i915_kernel_lost_context(struct drm_device * dev); extern int i915_driver_load(struct drm_device *, unsigned long flags); +extern int i915_driver_unload(struct drm_device *); extern void i915_driver_lastclose(struct drm_device * dev); extern void i915_driver_preclose(struct drm_device *dev, struct drm_file *file_priv); @@ -273,6 +356,50 @@ extern int i915_move(struct drm_buffer_object *bo, int evict, extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); +/* Extended config space */ +#define LBB 0xf4 + +/* VGA stuff */ + +#define VGA_ST01_MDA 0x3ba +#define VGA_ST01_CGA 0x3da + +#define VGA_MSR_WRITE 0x3c2 +#define VGA_MSR_READ 0x3cc +#define VGA_MSR_MEM_EN (1<<1) +#define VGA_MSR_CGA_MODE (1<<0) + +#define VGA_SR_INDEX 0x3c4 +#define VGA_SR_DATA 0x3c5 + +#define VGA_AR_INDEX 0x3c0 +#define VGA_AR_VID_EN (1<<5) +#define VGA_AR_DATA_WRITE 0x3c0 +#define VGA_AR_DATA_READ 0x3c1 + +#define VGA_GR_INDEX 0x3ce +#define VGA_GR_DATA 0x3cf +/* GR05 */ +#define VGA_GR_MEM_READ_MODE_SHIFT 3 +#define VGA_GR_MEM_READ_MODE_PLANE 1 +/* GR06 */ +#define VGA_GR_MEM_MODE_MASK 0xc +#define VGA_GR_MEM_MODE_SHIFT 2 +#define VGA_GR_MEM_A0000_AFFFF 0 +#define VGA_GR_MEM_A0000_BFFFF 1 +#define VGA_GR_MEM_B0000_B7FFF 2 +#define VGA_GR_MEM_B0000_BFFFF 3 + +#define VGA_DACMASK 0x3c6 +#define VGA_DACRX 0x3c7 +#define VGA_DACWX 0x3c8 +#define VGA_DACDATA 0x3c9 + +#define VGA_CR_INDEX_MDA 0x3b4 +#define VGA_CR_DATA_MDA 0x3b5 +#define VGA_CR_INDEX_CGA 0x3d4 +#define VGA_CR_DATA_CGA 0x3d5 + #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) #define CMD_REPORT_HEAD (7<<23) @@ -295,6 +422,37 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); #define BB1_UNPROTECTED (0<<0) #define BB2_END_ADDR_MASK (~0x7) +/* Framebuffer compression */ +#define FBC_CFB_BASE 0x03200 /* 4k page aligned */ +#define FBC_LL_BASE 0x03204 /* 4k page aligned */ +#define FBC_CONTROL 0x03208 +#define FBC_CTL_EN (1<<31) +#define FBC_CTL_PERIODIC (1<<30) +#define FBC_CTL_INTERVAL_SHIFT (16) +#define FBC_CTL_UNCOMPRESSIBLE (1<<14) +#define FBC_CTL_STRIDE_SHIFT (5) +#define FBC_CTL_FENCENO (1<<0) +#define FBC_COMMAND 0x0320c +#define FBC_CMD_COMPRESS (1<<0) +#define FBC_STATUS 0x03210 +#define FBC_STAT_COMPRESSING (1<<31) +#define FBC_STAT_COMPRESSED (1<<30) +#define FBC_STAT_MODIFIED (1<<29) +#define FBC_STAT_CURRENT_LINE (1<<0) +#define FBC_CONTROL2 0x03214 +#define FBC_CTL_FENCE_DBL (0<<4) +#define FBC_CTL_IDLE_IMM (0<<2) +#define FBC_CTL_IDLE_FULL (1<<2) +#define FBC_CTL_IDLE_LINE (2<<2) +#define FBC_CTL_IDLE_DEBUG (3<<2) +#define FBC_CTL_CPU_FENCE (1<<1) +#define FBC_CTL_PLANEA (0<<0) +#define FBC_CTL_PLANEB (1<<0) +#define FBC_FENCE_OFF 0x0321b + +#define FBC_LL_SIZE (1536) +#define FBC_LL_PAD (32) + /* Interrupt bits: */ #define USER_INT_FLAG (1<<1) @@ -516,4 +674,509 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5]) #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) + +#define BLC_PWM_CTL 0x61254 +#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) + +#define BLC_PWM_CTL2 0x61250 +/** + * This is the most significant 15 bits of the number of backlight cycles in a + * complete cycle of the modulated backlight control. + * + * The actual value is this field multiplied by two. + */ +#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) +#define BLM_LEGACY_MODE (1 << 16) +/** + * This is the number of cycles out of the backlight modulation cycle for which + * the backlight is on. + * + * This field must be no greater than the number of cycles in the complete + * backlight modulation cycle. + */ +#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) +#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) + +#define I915_GCFGC 0xf0 +#define I915_LOW_FREQUENCY_ENABLE (1 << 7) +#define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4) +#define I915_DISPLAY_CLOCK_333_MHZ (4 << 4) +#define I915_DISPLAY_CLOCK_MASK (7 << 4) + +#define I855_HPLLCC 0xc0 +#define I855_CLOCK_CONTROL_MASK (3 << 0) +#define I855_CLOCK_133_200 (0 << 0) +#define I855_CLOCK_100_200 (1 << 0) +#define I855_CLOCK_100_133 (2 << 0) +#define I855_CLOCK_166_250 (3 << 0) + +/* p317, 319 + */ +#define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */ +#define VCLK2_VCO_N 0x600a +#define VCLK2_VCO_DIV_SEL 0x6012 + +#define VCLK_DIVISOR_VGA0 0x6000 +#define VCLK_DIVISOR_VGA1 0x6004 +#define VCLK_POST_DIV 0x6010 +/** Selects a post divisor of 4 instead of 2. */ +# define VGA1_PD_P2_DIV_4 (1 << 15) +/** Overrides the p2 post divisor field */ +# define VGA1_PD_P1_DIV_2 (1 << 13) +# define VGA1_PD_P1_SHIFT 8 +/** P1 value is 2 greater than this field */ +# define VGA1_PD_P1_MASK (0x1f << 8) +/** Selects a post divisor of 4 instead of 2. */ +# define VGA0_PD_P2_DIV_4 (1 << 7) +/** Overrides the p2 post divisor field */ +# define VGA0_PD_P1_DIV_2 (1 << 5) +# define VGA0_PD_P1_SHIFT 0 +/** P1 value is 2 greater than this field */ +# define VGA0_PD_P1_MASK (0x1f << 0) + +/* I830 CRTC registers */ +#define HTOTAL_A 0x60000 +#define HBLANK_A 0x60004 +#define HSYNC_A 0x60008 +#define VTOTAL_A 0x6000c +#define VBLANK_A 0x60010 +#define VSYNC_A 0x60014 +#define PIPEASRC 0x6001c +#define BCLRPAT_A 0x60020 +#define VSYNCSHIFT_A 0x60028 + +#define HTOTAL_B 0x61000 +#define HBLANK_B 0x61004 +#define HSYNC_B 0x61008 +#define VTOTAL_B 0x6100c +#define VBLANK_B 0x61010 +#define VSYNC_B 0x61014 +#define PIPEBSRC 0x6101c +#define BCLRPAT_B 0x61020 +#define VSYNCSHIFT_B 0x61028 + +#define PP_STATUS 0x61200 +# define PP_ON (1 << 31) +/** + * Indicates that all dependencies of the panel are on: + * + * - PLL enabled + * - pipe enabled + * - LVDS/DVOB/DVOC on + */ +# define PP_READY (1 << 30) +# define PP_SEQUENCE_NONE (0 << 28) +# define PP_SEQUENCE_ON (1 << 28) +# define PP_SEQUENCE_OFF (2 << 28) +# define PP_SEQUENCE_MASK 0x30000000 +#define PP_CONTROL 0x61204 +# define POWER_TARGET_ON (1 << 0) + +#define LVDSPP_ON 0x61208 +#define LVDSPP_OFF 0x6120c +#define PP_CYCLE 0x61210 + +#define PFIT_CONTROL 0x61230 +# define PFIT_ENABLE (1 << 31) +# define PFIT_PIPE_MASK (3 << 29) +# define PFIT_PIPE_SHIFT 29 +# define VERT_INTERP_DISABLE (0 << 10) +# define VERT_INTERP_BILINEAR (1 << 10) +# define VERT_INTERP_MASK (3 << 10) +# define VERT_AUTO_SCALE (1 << 9) +# define HORIZ_INTERP_DISABLE (0 << 6) +# define HORIZ_INTERP_BILINEAR (1 << 6) +# define HORIZ_INTERP_MASK (3 << 6) +# define HORIZ_AUTO_SCALE (1 << 5) +# define PANEL_8TO6_DITHER_ENABLE (1 << 3) + +#define PFIT_PGM_RATIOS 0x61234 +# define PFIT_VERT_SCALE_MASK 0xfff00000 +# define PFIT_HORIZ_SCALE_MASK 0x0000fff0 + +#define PFIT_AUTO_RATIOS 0x61238 + + +#define DPLL_A 0x06014 +#define DPLL_B 0x06018 +# define DPLL_VCO_ENABLE (1 << 31) +# define DPLL_DVO_HIGH_SPEED (1 << 30) +# define DPLL_SYNCLOCK_ENABLE (1 << 29) +# define DPLL_VGA_MODE_DIS (1 << 28) +# define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ +# define DPLLB_MODE_LVDS (2 << 26) /* i915 */ +# define DPLL_MODE_MASK (3 << 26) +# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ +# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ +# define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ +# define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ +# define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ +# define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ +/** + * The i830 generation, in DAC/serial mode, defines p1 as two plus this + * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. + */ +# define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 +/** + * The i830 generation, in LVDS mode, defines P1 as the bit number set within + * this field (only one bit may be set). + */ +# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 +# define DPLL_FPA01_P1_POST_DIV_SHIFT 16 +# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */ +# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ +# define PLL_REF_INPUT_DREFCLK (0 << 13) +# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ +# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ +# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) +# define PLL_REF_INPUT_MASK (3 << 13) +# define PLL_LOAD_PULSE_PHASE_SHIFT 9 +/* + * Parallel to Serial Load Pulse phase selection. + * Selects the phase for the 10X DPLL clock for the PCIe + * digital display port. The range is 4 to 13; 10 or more + * is just a flip delay. The default is 6 + */ +# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) +# define DISPLAY_RATE_SELECT_FPA1 (1 << 8) + +/** + * SDVO multiplier for 945G/GM. Not used on 965. + * + * \sa DPLL_MD_UDI_MULTIPLIER_MASK + */ +# define SDVO_MULTIPLIER_MASK 0x000000ff +# define SDVO_MULTIPLIER_SHIFT_HIRES 4 +# define SDVO_MULTIPLIER_SHIFT_VGA 0 + +/** @defgroup DPLL_MD + * @{ + */ +/** Pipe A SDVO/UDI clock multiplier/divider register for G965. */ +#define DPLL_A_MD 0x0601c +/** Pipe B SDVO/UDI clock multiplier/divider register for G965. */ +#define DPLL_B_MD 0x06020 +/** + * UDI pixel divider, controlling how many pixels are stuffed into a packet. + * + * Value is pixels minus 1. Must be set to 1 pixel for SDVO. + */ +# define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 +# define DPLL_MD_UDI_DIVIDER_SHIFT 24 +/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ +# define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 +# define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 +/** + * SDVO/UDI pixel multiplier. + * + * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus + * clock rate is 10 times the DPLL clock. At low resolution/refresh rate + * modes, the bus rate would be below the limits, so SDVO allows for stuffing + * dummy bytes in the datastream at an increased clock rate, with both sides of + * the link knowing how many bytes are fill. + * + * So, for a mode with a dotclock of 65Mhz, we would want to double the clock + * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be + * set to 130Mhz, and the SDVO multiplier set to 2x in this register and + * through an SDVO command. + * + * This register field has values of multiplication factor minus 1, with + * a maximum multiplier of 5 for SDVO. + */ +# define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 +# define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 +/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. + * This best be set to the default value (3) or the CRT won't work. No, + * I don't entirely understand what this does... + */ +# define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f +# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 +/** @} */ + +#define DPLL_TEST 0x606c +# define DPLLB_TEST_SDVO_DIV_1 (0 << 22) +# define DPLLB_TEST_SDVO_DIV_2 (1 << 22) +# define DPLLB_TEST_SDVO_DIV_4 (2 << 22) +# define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) +# define DPLLB_TEST_N_BYPASS (1 << 19) +# define DPLLB_TEST_M_BYPASS (1 << 18) +# define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) +# define DPLLA_TEST_N_BYPASS (1 << 3) +# define DPLLA_TEST_M_BYPASS (1 << 2) +# define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) + +#define ADPA 0x61100 +#define ADPA_DAC_ENABLE (1<<31) +#define ADPA_DAC_DISABLE 0 +#define ADPA_PIPE_SELECT_MASK (1<<30) +#define ADPA_PIPE_A_SELECT 0 +#define ADPA_PIPE_B_SELECT (1<<30) +#define ADPA_USE_VGA_HVPOLARITY (1<<15) +#define ADPA_SETS_HVPOLARITY 0 +#define ADPA_VSYNC_CNTL_DISABLE (1<<11) +#define ADPA_VSYNC_CNTL_ENABLE 0 +#define ADPA_HSYNC_CNTL_DISABLE (1<<10) +#define ADPA_HSYNC_CNTL_ENABLE 0 +#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) +#define ADPA_VSYNC_ACTIVE_LOW 0 +#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) +#define ADPA_HSYNC_ACTIVE_LOW 0 + +#define FPA0 0x06040 +#define FPA1 0x06044 +#define FPB0 0x06048 +#define FPB1 0x0604c +# define FP_N_DIV_MASK 0x003f0000 +# define FP_N_DIV_SHIFT 16 +# define FP_M1_DIV_MASK 0x00003f00 +# define FP_M1_DIV_SHIFT 8 +# define FP_M2_DIV_MASK 0x0000003f +# define FP_M2_DIV_SHIFT 0 + + +#define PORT_HOTPLUG_EN 0x61110 +# define SDVOB_HOTPLUG_INT_EN (1 << 26) +# define SDVOC_HOTPLUG_INT_EN (1 << 25) +# define TV_HOTPLUG_INT_EN (1 << 18) +# define CRT_HOTPLUG_INT_EN (1 << 9) +# define CRT_HOTPLUG_FORCE_DETECT (1 << 3) + +#define PORT_HOTPLUG_STAT 0x61114 +# define CRT_HOTPLUG_INT_STATUS (1 << 11) +# define TV_HOTPLUG_INT_STATUS (1 << 10) +# define CRT_HOTPLUG_MONITOR_MASK (3 << 8) +# define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) +# define CRT_HOTPLUG_MONITOR_MONO (2 << 8) +# define CRT_HOTPLUG_MONITOR_NONE (0 << 8) +# define SDVOC_HOTPLUG_INT_STATUS (1 << 7) +# define SDVOB_HOTPLUG_INT_STATUS (1 << 6) + +#define SDVOB 0x61140 +#define SDVOC 0x61160 +#define SDVO_ENABLE (1 << 31) +#define SDVO_PIPE_B_SELECT (1 << 30) +#define SDVO_STALL_SELECT (1 << 29) +#define SDVO_INTERRUPT_ENABLE (1 << 26) +/** + * 915G/GM SDVO pixel multiplier. + * + * Programmed value is multiplier - 1, up to 5x. + * + * \sa DPLL_MD_UDI_MULTIPLIER_MASK + */ +#define SDVO_PORT_MULTIPLY_MASK (7 << 23) +#define SDVO_PORT_MULTIPLY_SHIFT 23 +#define SDVO_PHASE_SELECT_MASK (15 << 19) +#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) +#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) +#define SDVOC_GANG_MODE (1 << 16) +#define SDVO_BORDER_ENABLE (1 << 7) +#define SDVOB_PCIE_CONCURRENCY (1 << 3) +#define SDVO_DETECTED (1 << 2) +/* Bits to be preserved when writing */ +#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14)) +#define SDVOC_PRESERVE_MASK (1 << 17) + +/** @defgroup LVDS + * @{ + */ +/** + * This register controls the LVDS output enable, pipe selection, and data + * format selection. + * + * All of the clock/data pairs are force powered down by power sequencing. + */ +#define LVDS 0x61180 +/** + * Enables the LVDS port. This bit must be set before DPLLs are enabled, as + * the DPLL semantics change when the LVDS is assigned to that pipe. + */ +# define LVDS_PORT_EN (1 << 31) +/** Selects pipe B for LVDS data. Must be set on pre-965. */ +# define LVDS_PIPEB_SELECT (1 << 30) + +/** + * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per + * pixel. + */ +# define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) +# define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) +# define LVDS_A0A2_CLKA_POWER_UP (3 << 8) +/** + * Controls the A3 data pair, which contains the additional LSBs for 24 bit + * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be + * on. + */ +# define LVDS_A3_POWER_MASK (3 << 6) +# define LVDS_A3_POWER_DOWN (0 << 6) +# define LVDS_A3_POWER_UP (3 << 6) +/** + * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP + * is set. + */ +# define LVDS_CLKB_POWER_MASK (3 << 4) +# define LVDS_CLKB_POWER_DOWN (0 << 4) +# define LVDS_CLKB_POWER_UP (3 << 4) + +/** + * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 + * setting for whether we are in dual-channel mode. The B3 pair will + * additionally only be powered up when LVDS_A3_POWER_UP is set. + */ +# define LVDS_B0B3_POWER_MASK (3 << 2) +# define LVDS_B0B3_POWER_DOWN (0 << 2) +# define LVDS_B0B3_POWER_UP (3 << 2) + +#define PIPEACONF 0x70008 +#define PIPEACONF_ENABLE (1<<31) +#define PIPEACONF_DISABLE 0 +#define PIPEACONF_DOUBLE_WIDE (1<<30) +#define I965_PIPECONF_ACTIVE (1<<30) +#define PIPEACONF_SINGLE_WIDE 0 +#define PIPEACONF_PIPE_UNLOCKED 0 +#define PIPEACONF_PIPE_LOCKED (1<<25) +#define PIPEACONF_PALETTE 0 +#define PIPEACONF_GAMMA (1<<24) +#define PIPECONF_FORCE_BORDER (1<<25) +#define PIPECONF_PROGRESSIVE (0 << 21) +#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) +#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) + +#define PIPEBCONF 0x71008 +#define PIPEBCONF_ENABLE (1<<31) +#define PIPEBCONF_DISABLE 0 +#define PIPEBCONF_DOUBLE_WIDE (1<<30) +#define PIPEBCONF_DISABLE 0 +#define PIPEBCONF_GAMMA (1<<24) +#define PIPEBCONF_PALETTE 0 + +#define PIPEBGCMAXRED 0x71010 +#define PIPEBGCMAXGREEN 0x71014 +#define PIPEBGCMAXBLUE 0x71018 +#define PIPEBSTAT 0x71024 +#define PIPEBFRAMEHIGH 0x71040 +#define PIPEBFRAMEPIXEL 0x71044 + +#define DSPACNTR 0x70180 +#define DSPBCNTR 0x71180 +#define DISPLAY_PLANE_ENABLE (1<<31) +#define DISPLAY_PLANE_DISABLE 0 +#define DISPPLANE_GAMMA_ENABLE (1<<30) +#define DISPPLANE_GAMMA_DISABLE 0 +#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) +#define DISPPLANE_8BPP (0x2<<26) +#define DISPPLANE_15_16BPP (0x4<<26) +#define DISPPLANE_16BPP (0x5<<26) +#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) +#define DISPPLANE_32BPP (0x7<<26) +#define DISPPLANE_STEREO_ENABLE (1<<25) +#define DISPPLANE_STEREO_DISABLE 0 +#define DISPPLANE_SEL_PIPE_MASK (1<<24) +#define DISPPLANE_SEL_PIPE_A 0 +#define DISPPLANE_SEL_PIPE_B (1<<24) +#define DISPPLANE_SRC_KEY_ENABLE (1<<22) +#define DISPPLANE_SRC_KEY_DISABLE 0 +#define DISPPLANE_LINE_DOUBLE (1<<20) +#define DISPPLANE_NO_LINE_DOUBLE 0 +#define DISPPLANE_STEREO_POLARITY_FIRST 0 +#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) +/* plane B only */ +#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) +#define DISPPLANE_ALPHA_TRANS_DISABLE 0 +#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 +#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) + +#define DSPABASE 0x70184 +#define DSPASTRIDE 0x70188 + +#define DSPBBASE 0x71184 +#define DSPBADDR DSPBBASE +#define DSPBSTRIDE 0x71188 + +#define DSPAKEYVAL 0x70194 +#define DSPAKEYMASK 0x70198 + +#define DSPAPOS 0x7018C /* reserved */ +#define DSPASIZE 0x70190 +#define DSPBPOS 0x7118C +#define DSPBSIZE 0x71190 + +#define DSPASURF 0x7019C +#define DSPATILEOFF 0x701A4 + +#define DSPBSURF 0x7119C +#define DSPBTILEOFF 0x711A4 + +#define VGACNTRL 0x71400 +# define VGA_DISP_DISABLE (1 << 31) +# define VGA_2X_MODE (1 << 30) +# define VGA_PIPE_B_SELECT (1 << 29) + +/* + * Some BIOS scratch area registers. The 845 (and 830?) store the amount + * of video memory available to the BIOS in SWF1. + */ + +#define SWF0 0x71410 + +/* + * 855 scratch registers. + */ +#define SWF10 0x70410 + +#define SWF30 0x72414 + +/* + * Overlay registers. These are overlay registers accessed via MMIO. + * Those loaded via the overlay register page are defined in i830_video.c. + */ +#define OVADD 0x30000 + +#define DOVSTA 0x30008 +#define OC_BUF (0x3<<20) + +#define OGAMC5 0x30010 +#define OGAMC4 0x30014 +#define OGAMC3 0x30018 +#define OGAMC2 0x3001c +#define OGAMC1 0x30020 +#define OGAMC0 0x30024 +/* + * Palette registers + */ +#define PALETTE_A 0x0a000 +#define PALETTE_B 0x0a800 + +#define IS_I830(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82830_CGC) +#define IS_845G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82845G_IG) +#define IS_I85X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG) +#define IS_I855(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG) +#define IS_I865G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82865_IG) + +#define IS_I915G(dev) (dev->pci_device == PCI_DEVICE_ID_INTEL_82915G_IG)/* || dev->pci_device == PCI_DEVICE_ID_INTELPCI_CHIP_E7221_G)*/ +#define IS_I915GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82915GM_IG) +#define IS_I945G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945G_IG) +#define IS_I945GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945GM_IG) + +#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ + (dev)->pci_device == 0x2982 || \ + (dev)->pci_device == 0x2992 || \ + (dev)->pci_device == 0x29A2 || \ + (dev)->pci_device == 0x2A02 || \ + (dev)->pci_device == 0x2A12) + +#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) + +#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ + (dev)->pci_device == 0x29B2 || \ + (dev)->pci_device == 0x29D2) + +#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ + IS_I945GM(dev) || IS_I965G(dev)) + +#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ + IS_I945GM(dev) || IS_I965GM(dev)) + +#define PRIMARY_RINGBUFFER_SIZE (128*1024) + #endif -- cgit v1.2.3 From cc745fcc3a16cb1ffc2ab578155dc880b862f95a Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Sun, 28 Oct 2007 01:59:11 +0200 Subject: nouveau: don't touch PMC_BOOT_1 on x86, it seems to be undefined on some early cards. --- shared-core/nouveau_state.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index add2d598..c617bfd3 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -283,11 +283,13 @@ nouveau_card_init(struct drm_device *dev) ret = nouveau_init_card_mappings(dev); if (ret) return ret; +#if defined(__powerpc__) /* Put the card in BE mode if it's not */ if (NV_READ(NV03_PMC_BOOT_1)) NV_WRITE(NV03_PMC_BOOT_1,0x00000001); DRM_MEMORYBARRIER(); +#endif /* Determine exact chipset we're running on */ if (dev_priv->card_type < NV_10) @@ -431,8 +433,10 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) reg0 = readl(regs+NV03_PMC_BOOT_0); reg1 = readl(regs+NV03_PMC_BOOT_1); +#if defined(__powerpc__) if (reg1) reg0=___swab32(reg0); +#endif /* We're dealing with >=NV10 */ if ((reg0 & 0x0f000000) > 0 ) { -- cgit v1.2.3 From 6342e0507be177be309774aff0c31746beab73f6 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Mon, 29 Oct 2007 10:51:11 -0700 Subject: Remove unused memory save areas These need to be kmalloc'd separately anyway or we may hit kmalloc size limits. --- shared-core/i915_drv.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'shared-core') diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 07a173ac..6716f28f 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -224,10 +224,6 @@ typedef struct drm_i915_private { u8 saveDACMASK; u8 saveDACDATA[256*3]; /* 256 3-byte colors */ u8 saveCR[36]; - u8 savePLANE0[64*1024]; - u8 savePLANE1[64*1024]; - u8 savePLANE2[64*1024]; - u8 savePLANE3[64*1024]; } drm_i915_private_t; enum intel_chip_family { -- cgit v1.2.3 From ff5889f8316e0c16112f114c1c8f57645b8dc54f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kristian=20H=C3=B8gsberg?= Date: Mon, 29 Oct 2007 19:32:32 -0400 Subject: Move struct drm_drawable_info out of public header file. --- shared-core/drm.h | 9 --------- 1 file changed, 9 deletions(-) (limited to 'shared-core') diff --git a/shared-core/drm.h b/shared-core/drm.h index ae88ce61..3a102735 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -134,14 +134,6 @@ struct drm_clip_rect { unsigned short y2; }; -/** - * Drawable information. - */ -struct drm_drawable_info { - unsigned int num_rects; - struct drm_clip_rect *rects; -}; - /** * Texture region, */ @@ -1002,7 +994,6 @@ struct drm_mm_init_arg { /* typedef area */ #if !defined(__KERNEL__) || defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) typedef struct drm_clip_rect drm_clip_rect_t; -typedef struct drm_drawable_info drm_drawable_info_t; typedef struct drm_tex_region drm_tex_region_t; typedef struct drm_hw_lock drm_hw_lock_t; typedef struct drm_version drm_version_t; -- cgit v1.2.3 From 50dec29c800a6e980a01be38190e44a0ba7916b5 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 30 Oct 2007 17:51:59 +1000 Subject: drm/i915: add driver cache flush entry point Use clflush on Intel hardware to flush cached objects. --- shared-core/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core') diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 6716f28f..9f69d841 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -310,7 +310,7 @@ extern int i915_init_mem_type(struct drm_device *dev, uint32_t type, extern uint32_t i915_evict_mask(struct drm_buffer_object *bo); extern int i915_move(struct drm_buffer_object *bo, int evict, int no_wait, struct drm_bo_mem_reg *new_mem); - +void i915_flush_ttm(struct drm_ttm *ttm); #endif #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) -- cgit v1.2.3 From 0cebcd43dd7b950c07625601b87c72329857d831 Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Tue, 30 Oct 2007 16:54:57 +0100 Subject: Nouveau: fold some loops. --- shared-core/nv20_graph.c | 2535 +--------------------------------------------- 1 file changed, 15 insertions(+), 2520 deletions(-) (limited to 'shared-core') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 94ce32c1..e6ccf672 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -415,846 +415,11 @@ static void nv30_31_graph_context_init(struct drm_device *dev, INSTANCE_WR(ctx, 0x860/4, 0x00010000); for(i = 0x864; i< 0x874; i += 4) INSTANCE_WR(ctx, i/4, 0x00040004); - INSTANCE_WR(ctx, 0x1f18/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f1c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f20/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f28/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f2c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f30/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f38/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f3c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f40/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f48/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f4c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f50/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f58/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f5c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f60/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f68/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f6c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f70/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f78/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f7c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f80/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f88/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f8c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f90/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f98/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f9c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fa0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fa8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fb0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fb8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fbc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fc0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fc8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fcc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fd0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fd8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fdc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fe0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fe8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ff0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1ff8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ffc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2000/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2008/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x200c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2010/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2018/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x201c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2020/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2028/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x202c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2030/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2038/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x203c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2040/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2048/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x204c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2050/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2058/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x205c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2060/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2068/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x206c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2070/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2078/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x207c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2080/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2088/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x208c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2090/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2098/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x209c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2100/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2108/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x210c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2110/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2118/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x211c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2120/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2128/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x212c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2130/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2138/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x213c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2140/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2148/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x214c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2150/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2158/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x215c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2160/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2168/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x216c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2170/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2178/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x217c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2180/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2188/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x218c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2190/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2198/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x219c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2200/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2208/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x220c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2210/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2218/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x221c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2220/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2228/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x222c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2230/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2238/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x223c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2240/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2248/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x224c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2250/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2258/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x225c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2260/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2268/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x226c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2270/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2278/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x227c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2280/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2288/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x228c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2290/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2298/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x229c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2300/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2308/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x230c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2310/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2318/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x231c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2320/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2328/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x232c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2330/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2338/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x233c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2340/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2348/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x234c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2350/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2358/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x235c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2360/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2368/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x236c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2370/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2378/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x237c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2380/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2388/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x238c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2390/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2398/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x239c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2400/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2408/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x240c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2410/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2418/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x241c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2420/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2428/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x242c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2430/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2438/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x243c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2440/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2448/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x244c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2450/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2458/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x245c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2460/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2468/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x246c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2470/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2478/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x247c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2480/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2488/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x248c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2490/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2498/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x249c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2500/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2508/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x250c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2510/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2518/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x251c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2520/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2528/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x252c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2530/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2538/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x253c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2540/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2548/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x254c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2550/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2558/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x255c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2560/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2568/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x256c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2570/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2578/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x257c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2580/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2588/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x258c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2590/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2598/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x259c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2600/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2608/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x260c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2610/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2618/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x261c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2620/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2628/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x262c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2630/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2638/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x263c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2640/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2648/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x264c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2650/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2658/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x265c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2660/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2668/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x266c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2670/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2678/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x267c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2680/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2688/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x268c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2690/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2698/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x269c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2700/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2708/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x270c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2710/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2718/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x271c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2720/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2728/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x272c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2730/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2738/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x273c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2740/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2748/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x274c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2750/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2758/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x275c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2760/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2768/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x276c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2770/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2778/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x277c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2780/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2788/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x278c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2790/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2798/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x279c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2800/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2808/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x280c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2810/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2818/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x281c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2820/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2828/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x282c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2830/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2838/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x283c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2840/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2848/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x284c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2850/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2858/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x285c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2860/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2868/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x286c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2870/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2878/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x287c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2880/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2888/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x288c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2890/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2898/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x289c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2900/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2908/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x290c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2910/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2918/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x291c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2920/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2928/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x292c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2930/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2938/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x293c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2940/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2948/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x294c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2950/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2958/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x295c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2960/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2968/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x296c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2970/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2978/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x297c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2980/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2988/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x298c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2990/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2998/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x299c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29a0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29a8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29ac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29b0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29b8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29bc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29c0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29c8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29cc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29d0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29d8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29dc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29e0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29e8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29ec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29f0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29f8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29fc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a00/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a08/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a0c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a10/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a18/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a1c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a20/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a28/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a2c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a30/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a38/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a3c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a40/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a48/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a4c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a50/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a58/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a5c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a60/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a68/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a6c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a70/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a78/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a7c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a80/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a88/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a8c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a90/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a98/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a9c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2aa0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2aa8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2aac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ab0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ab8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2abc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ac0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ac8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2acc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ad0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ad8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2adc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ae0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ae8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2aec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2af0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2af8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2afc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b00/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b08/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b0c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b10/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b18/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b1c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b20/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b28/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b2c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b30/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b38/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b3c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b40/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b48/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b4c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b50/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b58/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b5c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b60/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b68/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b6c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b70/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b78/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b7c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b80/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b88/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b8c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b90/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b98/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b9c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ba0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ba8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2bb0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bb8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bbc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2bc0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bc8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bcc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2bd0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bd8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bdc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2be0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2be8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2bf0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bf8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bfc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c00/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c08/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c0c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c10/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c18/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c1c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c20/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c28/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c2c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c30/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c38/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c3c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c40/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c48/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c4c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c50/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c58/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c5c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c60/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c68/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c6c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c70/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c78/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c7c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c80/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c88/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c8c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c90/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c98/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c9c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ca0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ca8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2cb0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cb8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cbc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2cc0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cc8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ccc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2cd0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cd8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cdc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ce0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ce8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2cf0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cf8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cfc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d00/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d08/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d0c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d10/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d18/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d1c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d20/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d28/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d2c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d30/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d38/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d3c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d40/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d48/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d4c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d50/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d58/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d5c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d60/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d68/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d6c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d70/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d78/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d7c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d80/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d88/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d8c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d90/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d98/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d9c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2da0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2da8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2dac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2db0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2db8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2dbc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2dc0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2dc8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2dcc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2dd0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2dd8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ddc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2de0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2de8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2dec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2df0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2df8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2dfc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e00/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e08/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e0c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e10/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e18/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e1c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e20/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e28/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e2c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e30/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e38/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e3c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e40/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e48/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e4c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e50/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e58/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e5c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e60/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e68/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e6c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e70/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e78/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e7c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e80/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e88/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e8c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e90/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e98/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e9c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ea0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ea8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2eac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2eb0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2eb8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ebc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ec0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ec8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ecc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ed0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ed8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2edc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ee0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ee8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2eec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ef0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ef8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2efc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f00/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f08/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f0c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f10/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f18/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f1c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f20/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f28/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f2c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f30/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f38/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f3c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f40/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f48/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f4c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f50/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f58/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f5c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f60/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f68/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f6c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f70/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f78/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f7c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f80/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f88/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f8c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f90/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f98/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f9c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fa0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fa8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fac/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fb0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fb8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fbc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fc0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fc8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fcc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fd0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fd8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fdc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fe0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fe8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fec/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ff0/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ff8/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ffc/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3000/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3008/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x300c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3010/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3018/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x301c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3020/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3028/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x302c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3030/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3038/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x303c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3040/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3048/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x304c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3050/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3058/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x305c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3060/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3068/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x306c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3070/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3078/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x307c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3080/4, 0x000c001b); - INSTANCE_WR(ctx, 0x3088/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x308c/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3090/4, 0x000c001b); + for(i = 0x1f18; i<= 0x3088 ; i+= 16) { + INSTANCE_WR(ctx, i/4 + 0, 0x10700ff9); + INSTANCE_WR(ctx, i/4 + 1, 0x0436086c); + INSTANCE_WR(ctx, i/4 + 2, 0x000c001b); + } for(i = 0x30b8; i< 0x30c8; i += 4) INSTANCE_WR(ctx, i/4, 0x0000ffff); INSTANCE_WR(ctx, 0x344c/4, 0x3f800000); @@ -1309,846 +474,11 @@ static void nv34_graph_context_init(struct drm_device *dev, INSTANCE_WR(ctx, 0x854/4, 0x00010000); for(i = 0x858; i< 0x868; i += 4) INSTANCE_WR(ctx, i/4, 0x00040004); - INSTANCE_WR(ctx, 0x15ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x15b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x15b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x15bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x15c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x15c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x15cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x15d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x15d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x15dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x15e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x15e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x15ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x15f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x15f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x15fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1600/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1604/4, 0x000c001b); - INSTANCE_WR(ctx, 0x160c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1610/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1614/4, 0x000c001b); - INSTANCE_WR(ctx, 0x161c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1620/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1624/4, 0x000c001b); - INSTANCE_WR(ctx, 0x162c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1630/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1634/4, 0x000c001b); - INSTANCE_WR(ctx, 0x163c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1640/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1644/4, 0x000c001b); - INSTANCE_WR(ctx, 0x164c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1650/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1654/4, 0x000c001b); - INSTANCE_WR(ctx, 0x165c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1660/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1664/4, 0x000c001b); - INSTANCE_WR(ctx, 0x166c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1670/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1674/4, 0x000c001b); - INSTANCE_WR(ctx, 0x167c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1680/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1684/4, 0x000c001b); - INSTANCE_WR(ctx, 0x168c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1690/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1694/4, 0x000c001b); - INSTANCE_WR(ctx, 0x169c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x16a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x16a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x16ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x16b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x16b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x16bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x16c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x16c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x16cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x16d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x16d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x16dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x16e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x16e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x16ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x16f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x16f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x16fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1700/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1704/4, 0x000c001b); - INSTANCE_WR(ctx, 0x170c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1710/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1714/4, 0x000c001b); - INSTANCE_WR(ctx, 0x171c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1720/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1724/4, 0x000c001b); - INSTANCE_WR(ctx, 0x172c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1730/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1734/4, 0x000c001b); - INSTANCE_WR(ctx, 0x173c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1740/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1744/4, 0x000c001b); - INSTANCE_WR(ctx, 0x174c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1750/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1754/4, 0x000c001b); - INSTANCE_WR(ctx, 0x175c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1760/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1764/4, 0x000c001b); - INSTANCE_WR(ctx, 0x176c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1770/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1774/4, 0x000c001b); - INSTANCE_WR(ctx, 0x177c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1780/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1784/4, 0x000c001b); - INSTANCE_WR(ctx, 0x178c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1790/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1794/4, 0x000c001b); - INSTANCE_WR(ctx, 0x179c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x17a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x17a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x17ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x17b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x17b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x17bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x17c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x17c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x17cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x17d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x17d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x17dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x17e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x17e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x17ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x17f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x17f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x17fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1800/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1804/4, 0x000c001b); - INSTANCE_WR(ctx, 0x180c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1810/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1814/4, 0x000c001b); - INSTANCE_WR(ctx, 0x181c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1820/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1824/4, 0x000c001b); - INSTANCE_WR(ctx, 0x182c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1830/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1834/4, 0x000c001b); - INSTANCE_WR(ctx, 0x183c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1840/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1844/4, 0x000c001b); - INSTANCE_WR(ctx, 0x184c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1850/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1854/4, 0x000c001b); - INSTANCE_WR(ctx, 0x185c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1860/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1864/4, 0x000c001b); - INSTANCE_WR(ctx, 0x186c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1870/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1874/4, 0x000c001b); - INSTANCE_WR(ctx, 0x187c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1880/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1884/4, 0x000c001b); - INSTANCE_WR(ctx, 0x188c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1890/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1894/4, 0x000c001b); - INSTANCE_WR(ctx, 0x189c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x18a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x18a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x18ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x18b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x18b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x18bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x18c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x18c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x18cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x18d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x18d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x18dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x18e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x18e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x18ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x18f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x18f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x18fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1900/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1904/4, 0x000c001b); - INSTANCE_WR(ctx, 0x190c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1910/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1914/4, 0x000c001b); - INSTANCE_WR(ctx, 0x191c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1920/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1924/4, 0x000c001b); - INSTANCE_WR(ctx, 0x192c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1930/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1934/4, 0x000c001b); - INSTANCE_WR(ctx, 0x193c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1940/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1944/4, 0x000c001b); - INSTANCE_WR(ctx, 0x194c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1950/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1954/4, 0x000c001b); - INSTANCE_WR(ctx, 0x195c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1960/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1964/4, 0x000c001b); - INSTANCE_WR(ctx, 0x196c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1970/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1974/4, 0x000c001b); - INSTANCE_WR(ctx, 0x197c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1980/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1984/4, 0x000c001b); - INSTANCE_WR(ctx, 0x198c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1990/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1994/4, 0x000c001b); - INSTANCE_WR(ctx, 0x199c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x19a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x19a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x19ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x19b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x19b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x19bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x19c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x19c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x19cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x19d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x19d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x19dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x19e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x19e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x19ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x19f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x19f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x19fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1a90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1a94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1a9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1aa0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1aa4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1aac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ab0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ab4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1abc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ac0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ac4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1acc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ad0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ad4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1adc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ae0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ae4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1aec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1af0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1af4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1afc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1b90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1b94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1b9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ba0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ba4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1bac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1bb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1bb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1bbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1bc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1bc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1bcc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1bd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1bd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1bdc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1be0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1be4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1bec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1bf0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1bf4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1bfc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1c90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1c94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1c9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ca0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ca4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1cac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1cb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1cb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1cbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1cc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1cc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1ccc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1cd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1cd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1cdc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ce0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ce4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1cec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1cf0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1cf4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1cfc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1d90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1d94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1d9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1da0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1da4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1dac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1db0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1db4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1dbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1dc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1dc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1dcc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1dd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1dd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1ddc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1de0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1de4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1dec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1df0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1df4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1dfc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1e90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1e94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1e9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ea0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ea4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1eac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1eb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1eb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1ebc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ec0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ec4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1ecc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ed0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ed4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1edc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ee0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ee4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1eec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ef0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ef4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1efc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fa0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fa4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fcc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fdc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fe0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fe4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ff0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ff4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1ffc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2000/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2004/4, 0x000c001b); - INSTANCE_WR(ctx, 0x200c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2010/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2014/4, 0x000c001b); - INSTANCE_WR(ctx, 0x201c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2020/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2024/4, 0x000c001b); - INSTANCE_WR(ctx, 0x202c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2030/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2034/4, 0x000c001b); - INSTANCE_WR(ctx, 0x203c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2040/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2044/4, 0x000c001b); - INSTANCE_WR(ctx, 0x204c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2050/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2054/4, 0x000c001b); - INSTANCE_WR(ctx, 0x205c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2060/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2064/4, 0x000c001b); - INSTANCE_WR(ctx, 0x206c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2070/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2074/4, 0x000c001b); - INSTANCE_WR(ctx, 0x207c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2080/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2084/4, 0x000c001b); - INSTANCE_WR(ctx, 0x208c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2090/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2094/4, 0x000c001b); - INSTANCE_WR(ctx, 0x209c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2100/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2104/4, 0x000c001b); - INSTANCE_WR(ctx, 0x210c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2110/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2114/4, 0x000c001b); - INSTANCE_WR(ctx, 0x211c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2120/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2124/4, 0x000c001b); - INSTANCE_WR(ctx, 0x212c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2130/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2134/4, 0x000c001b); - INSTANCE_WR(ctx, 0x213c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2140/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2144/4, 0x000c001b); - INSTANCE_WR(ctx, 0x214c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2150/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2154/4, 0x000c001b); - INSTANCE_WR(ctx, 0x215c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2160/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2164/4, 0x000c001b); - INSTANCE_WR(ctx, 0x216c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2170/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2174/4, 0x000c001b); - INSTANCE_WR(ctx, 0x217c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2180/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2184/4, 0x000c001b); - INSTANCE_WR(ctx, 0x218c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2190/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2194/4, 0x000c001b); - INSTANCE_WR(ctx, 0x219c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2200/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2204/4, 0x000c001b); - INSTANCE_WR(ctx, 0x220c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2210/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2214/4, 0x000c001b); - INSTANCE_WR(ctx, 0x221c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2220/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2224/4, 0x000c001b); - INSTANCE_WR(ctx, 0x222c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2230/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2234/4, 0x000c001b); - INSTANCE_WR(ctx, 0x223c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2240/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2244/4, 0x000c001b); - INSTANCE_WR(ctx, 0x224c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2250/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2254/4, 0x000c001b); - INSTANCE_WR(ctx, 0x225c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2260/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2264/4, 0x000c001b); - INSTANCE_WR(ctx, 0x226c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2270/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2274/4, 0x000c001b); - INSTANCE_WR(ctx, 0x227c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2280/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2284/4, 0x000c001b); - INSTANCE_WR(ctx, 0x228c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2290/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2294/4, 0x000c001b); - INSTANCE_WR(ctx, 0x229c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2300/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2304/4, 0x000c001b); - INSTANCE_WR(ctx, 0x230c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2310/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2314/4, 0x000c001b); - INSTANCE_WR(ctx, 0x231c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2320/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2324/4, 0x000c001b); - INSTANCE_WR(ctx, 0x232c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2330/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2334/4, 0x000c001b); - INSTANCE_WR(ctx, 0x233c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2340/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2344/4, 0x000c001b); - INSTANCE_WR(ctx, 0x234c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2350/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2354/4, 0x000c001b); - INSTANCE_WR(ctx, 0x235c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2360/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2364/4, 0x000c001b); - INSTANCE_WR(ctx, 0x236c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2370/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2374/4, 0x000c001b); - INSTANCE_WR(ctx, 0x237c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2380/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2384/4, 0x000c001b); - INSTANCE_WR(ctx, 0x238c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2390/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2394/4, 0x000c001b); - INSTANCE_WR(ctx, 0x239c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2400/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2404/4, 0x000c001b); - INSTANCE_WR(ctx, 0x240c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2410/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2414/4, 0x000c001b); - INSTANCE_WR(ctx, 0x241c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2420/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2424/4, 0x000c001b); - INSTANCE_WR(ctx, 0x242c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2430/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2434/4, 0x000c001b); - INSTANCE_WR(ctx, 0x243c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2440/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2444/4, 0x000c001b); - INSTANCE_WR(ctx, 0x244c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2450/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2454/4, 0x000c001b); - INSTANCE_WR(ctx, 0x245c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2460/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2464/4, 0x000c001b); - INSTANCE_WR(ctx, 0x246c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2470/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2474/4, 0x000c001b); - INSTANCE_WR(ctx, 0x247c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2480/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2484/4, 0x000c001b); - INSTANCE_WR(ctx, 0x248c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2490/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2494/4, 0x000c001b); - INSTANCE_WR(ctx, 0x249c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2500/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2504/4, 0x000c001b); - INSTANCE_WR(ctx, 0x250c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2510/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2514/4, 0x000c001b); - INSTANCE_WR(ctx, 0x251c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2520/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2524/4, 0x000c001b); - INSTANCE_WR(ctx, 0x252c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2530/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2534/4, 0x000c001b); - INSTANCE_WR(ctx, 0x253c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2540/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2544/4, 0x000c001b); - INSTANCE_WR(ctx, 0x254c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2550/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2554/4, 0x000c001b); - INSTANCE_WR(ctx, 0x255c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2560/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2564/4, 0x000c001b); - INSTANCE_WR(ctx, 0x256c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2570/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2574/4, 0x000c001b); - INSTANCE_WR(ctx, 0x257c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2580/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2584/4, 0x000c001b); - INSTANCE_WR(ctx, 0x258c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2590/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2594/4, 0x000c001b); - INSTANCE_WR(ctx, 0x259c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2600/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2604/4, 0x000c001b); - INSTANCE_WR(ctx, 0x260c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2610/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2614/4, 0x000c001b); - INSTANCE_WR(ctx, 0x261c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2620/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2624/4, 0x000c001b); - INSTANCE_WR(ctx, 0x262c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2630/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2634/4, 0x000c001b); - INSTANCE_WR(ctx, 0x263c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2640/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2644/4, 0x000c001b); - INSTANCE_WR(ctx, 0x264c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2650/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2654/4, 0x000c001b); - INSTANCE_WR(ctx, 0x265c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2660/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2664/4, 0x000c001b); - INSTANCE_WR(ctx, 0x266c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2670/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2674/4, 0x000c001b); - INSTANCE_WR(ctx, 0x267c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2680/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2684/4, 0x000c001b); - INSTANCE_WR(ctx, 0x268c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2690/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2694/4, 0x000c001b); - INSTANCE_WR(ctx, 0x269c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2700/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2704/4, 0x000c001b); - INSTANCE_WR(ctx, 0x270c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2710/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2714/4, 0x000c001b); - INSTANCE_WR(ctx, 0x271c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2720/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2724/4, 0x000c001b); + for(i = 0x15ac; i<= 0x271c ; i+= 16) { + INSTANCE_WR(ctx, i/4 + 0, 0x10700ff9); + INSTANCE_WR(ctx, i/4 + 1, 0x0436086c); + INSTANCE_WR(ctx, i/4 + 2, 0x000c001b); + } for(i = 0x274c; i< 0x275c; i += 4) INSTANCE_WR(ctx, i/4, 0x0000ffff); INSTANCE_WR(ctx, 0x2ae0/4, 0x3f800000); @@ -2203,846 +533,11 @@ static void nv35_36_graph_context_init(struct drm_device *dev, INSTANCE_WR(ctx, 0x864/4, 0x00010000); for(i = 0x868; i< 0x878; i += 4) INSTANCE_WR(ctx, i/4, 0x00040004); - INSTANCE_WR(ctx, 0x1f1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1f90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1f94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1f9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fa0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fa4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fcc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fdc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1fe0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1fe4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1fec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x1ff0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x1ff4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x1ffc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2000/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2004/4, 0x000c001b); - INSTANCE_WR(ctx, 0x200c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2010/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2014/4, 0x000c001b); - INSTANCE_WR(ctx, 0x201c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2020/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2024/4, 0x000c001b); - INSTANCE_WR(ctx, 0x202c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2030/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2034/4, 0x000c001b); - INSTANCE_WR(ctx, 0x203c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2040/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2044/4, 0x000c001b); - INSTANCE_WR(ctx, 0x204c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2050/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2054/4, 0x000c001b); - INSTANCE_WR(ctx, 0x205c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2060/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2064/4, 0x000c001b); - INSTANCE_WR(ctx, 0x206c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2070/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2074/4, 0x000c001b); - INSTANCE_WR(ctx, 0x207c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2080/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2084/4, 0x000c001b); - INSTANCE_WR(ctx, 0x208c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2090/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2094/4, 0x000c001b); - INSTANCE_WR(ctx, 0x209c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x20f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x20f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x20fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2100/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2104/4, 0x000c001b); - INSTANCE_WR(ctx, 0x210c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2110/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2114/4, 0x000c001b); - INSTANCE_WR(ctx, 0x211c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2120/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2124/4, 0x000c001b); - INSTANCE_WR(ctx, 0x212c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2130/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2134/4, 0x000c001b); - INSTANCE_WR(ctx, 0x213c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2140/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2144/4, 0x000c001b); - INSTANCE_WR(ctx, 0x214c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2150/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2154/4, 0x000c001b); - INSTANCE_WR(ctx, 0x215c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2160/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2164/4, 0x000c001b); - INSTANCE_WR(ctx, 0x216c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2170/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2174/4, 0x000c001b); - INSTANCE_WR(ctx, 0x217c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2180/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2184/4, 0x000c001b); - INSTANCE_WR(ctx, 0x218c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2190/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2194/4, 0x000c001b); - INSTANCE_WR(ctx, 0x219c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x21f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x21f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x21fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2200/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2204/4, 0x000c001b); - INSTANCE_WR(ctx, 0x220c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2210/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2214/4, 0x000c001b); - INSTANCE_WR(ctx, 0x221c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2220/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2224/4, 0x000c001b); - INSTANCE_WR(ctx, 0x222c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2230/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2234/4, 0x000c001b); - INSTANCE_WR(ctx, 0x223c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2240/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2244/4, 0x000c001b); - INSTANCE_WR(ctx, 0x224c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2250/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2254/4, 0x000c001b); - INSTANCE_WR(ctx, 0x225c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2260/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2264/4, 0x000c001b); - INSTANCE_WR(ctx, 0x226c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2270/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2274/4, 0x000c001b); - INSTANCE_WR(ctx, 0x227c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2280/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2284/4, 0x000c001b); - INSTANCE_WR(ctx, 0x228c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2290/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2294/4, 0x000c001b); - INSTANCE_WR(ctx, 0x229c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x22f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x22f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x22fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2300/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2304/4, 0x000c001b); - INSTANCE_WR(ctx, 0x230c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2310/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2314/4, 0x000c001b); - INSTANCE_WR(ctx, 0x231c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2320/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2324/4, 0x000c001b); - INSTANCE_WR(ctx, 0x232c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2330/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2334/4, 0x000c001b); - INSTANCE_WR(ctx, 0x233c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2340/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2344/4, 0x000c001b); - INSTANCE_WR(ctx, 0x234c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2350/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2354/4, 0x000c001b); - INSTANCE_WR(ctx, 0x235c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2360/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2364/4, 0x000c001b); - INSTANCE_WR(ctx, 0x236c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2370/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2374/4, 0x000c001b); - INSTANCE_WR(ctx, 0x237c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2380/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2384/4, 0x000c001b); - INSTANCE_WR(ctx, 0x238c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2390/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2394/4, 0x000c001b); - INSTANCE_WR(ctx, 0x239c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x23f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x23f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x23fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2400/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2404/4, 0x000c001b); - INSTANCE_WR(ctx, 0x240c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2410/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2414/4, 0x000c001b); - INSTANCE_WR(ctx, 0x241c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2420/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2424/4, 0x000c001b); - INSTANCE_WR(ctx, 0x242c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2430/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2434/4, 0x000c001b); - INSTANCE_WR(ctx, 0x243c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2440/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2444/4, 0x000c001b); - INSTANCE_WR(ctx, 0x244c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2450/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2454/4, 0x000c001b); - INSTANCE_WR(ctx, 0x245c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2460/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2464/4, 0x000c001b); - INSTANCE_WR(ctx, 0x246c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2470/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2474/4, 0x000c001b); - INSTANCE_WR(ctx, 0x247c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2480/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2484/4, 0x000c001b); - INSTANCE_WR(ctx, 0x248c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2490/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2494/4, 0x000c001b); - INSTANCE_WR(ctx, 0x249c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x24f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x24f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x24fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2500/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2504/4, 0x000c001b); - INSTANCE_WR(ctx, 0x250c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2510/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2514/4, 0x000c001b); - INSTANCE_WR(ctx, 0x251c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2520/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2524/4, 0x000c001b); - INSTANCE_WR(ctx, 0x252c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2530/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2534/4, 0x000c001b); - INSTANCE_WR(ctx, 0x253c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2540/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2544/4, 0x000c001b); - INSTANCE_WR(ctx, 0x254c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2550/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2554/4, 0x000c001b); - INSTANCE_WR(ctx, 0x255c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2560/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2564/4, 0x000c001b); - INSTANCE_WR(ctx, 0x256c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2570/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2574/4, 0x000c001b); - INSTANCE_WR(ctx, 0x257c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2580/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2584/4, 0x000c001b); - INSTANCE_WR(ctx, 0x258c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2590/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2594/4, 0x000c001b); - INSTANCE_WR(ctx, 0x259c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x25f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x25f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x25fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2600/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2604/4, 0x000c001b); - INSTANCE_WR(ctx, 0x260c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2610/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2614/4, 0x000c001b); - INSTANCE_WR(ctx, 0x261c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2620/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2624/4, 0x000c001b); - INSTANCE_WR(ctx, 0x262c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2630/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2634/4, 0x000c001b); - INSTANCE_WR(ctx, 0x263c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2640/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2644/4, 0x000c001b); - INSTANCE_WR(ctx, 0x264c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2650/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2654/4, 0x000c001b); - INSTANCE_WR(ctx, 0x265c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2660/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2664/4, 0x000c001b); - INSTANCE_WR(ctx, 0x266c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2670/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2674/4, 0x000c001b); - INSTANCE_WR(ctx, 0x267c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2680/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2684/4, 0x000c001b); - INSTANCE_WR(ctx, 0x268c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2690/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2694/4, 0x000c001b); - INSTANCE_WR(ctx, 0x269c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x26f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x26f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x26fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2700/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2704/4, 0x000c001b); - INSTANCE_WR(ctx, 0x270c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2710/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2714/4, 0x000c001b); - INSTANCE_WR(ctx, 0x271c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2720/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2724/4, 0x000c001b); - INSTANCE_WR(ctx, 0x272c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2730/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2734/4, 0x000c001b); - INSTANCE_WR(ctx, 0x273c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2740/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2744/4, 0x000c001b); - INSTANCE_WR(ctx, 0x274c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2750/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2754/4, 0x000c001b); - INSTANCE_WR(ctx, 0x275c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2760/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2764/4, 0x000c001b); - INSTANCE_WR(ctx, 0x276c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2770/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2774/4, 0x000c001b); - INSTANCE_WR(ctx, 0x277c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2780/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2784/4, 0x000c001b); - INSTANCE_WR(ctx, 0x278c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2790/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2794/4, 0x000c001b); - INSTANCE_WR(ctx, 0x279c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x27f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x27f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x27fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2800/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2804/4, 0x000c001b); - INSTANCE_WR(ctx, 0x280c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2810/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2814/4, 0x000c001b); - INSTANCE_WR(ctx, 0x281c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2820/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2824/4, 0x000c001b); - INSTANCE_WR(ctx, 0x282c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2830/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2834/4, 0x000c001b); - INSTANCE_WR(ctx, 0x283c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2840/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2844/4, 0x000c001b); - INSTANCE_WR(ctx, 0x284c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2850/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2854/4, 0x000c001b); - INSTANCE_WR(ctx, 0x285c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2860/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2864/4, 0x000c001b); - INSTANCE_WR(ctx, 0x286c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2870/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2874/4, 0x000c001b); - INSTANCE_WR(ctx, 0x287c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2880/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2884/4, 0x000c001b); - INSTANCE_WR(ctx, 0x288c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2890/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2894/4, 0x000c001b); - INSTANCE_WR(ctx, 0x289c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x28f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x28f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x28fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2900/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2904/4, 0x000c001b); - INSTANCE_WR(ctx, 0x290c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2910/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2914/4, 0x000c001b); - INSTANCE_WR(ctx, 0x291c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2920/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2924/4, 0x000c001b); - INSTANCE_WR(ctx, 0x292c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2930/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2934/4, 0x000c001b); - INSTANCE_WR(ctx, 0x293c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2940/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2944/4, 0x000c001b); - INSTANCE_WR(ctx, 0x294c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2950/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2954/4, 0x000c001b); - INSTANCE_WR(ctx, 0x295c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2960/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2964/4, 0x000c001b); - INSTANCE_WR(ctx, 0x296c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2970/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2974/4, 0x000c001b); - INSTANCE_WR(ctx, 0x297c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2980/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2984/4, 0x000c001b); - INSTANCE_WR(ctx, 0x298c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2990/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2994/4, 0x000c001b); - INSTANCE_WR(ctx, 0x299c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29a0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29a4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29ac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29b0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29b4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29bc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29c0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29c4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29cc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29d0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29d4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29dc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29e0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29e4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29ec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x29f0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x29f4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x29fc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2a90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2a94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2a9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2aa0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2aa4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2aac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ab0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ab4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2abc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ac0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ac4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2acc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ad0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ad4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2adc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ae0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ae4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2aec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2af0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2af4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2afc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2b90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2b94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2b9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ba0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ba4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2bb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2bc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bcc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2bd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bdc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2be0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2be4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2bf0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2bf4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2bfc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2c90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2c94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2c9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ca0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ca4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2cb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2cc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ccc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2cd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cdc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ce0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ce4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2cf0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2cf4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2cfc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2d90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2d94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2d9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2da0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2da4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2dac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2db0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2db4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2dbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2dc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2dc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2dcc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2dd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2dd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ddc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2de0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2de4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2dec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2df0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2df4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2dfc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2e90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2e94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2e9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ea0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ea4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2eac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2eb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2eb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ebc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ec0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ec4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ecc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ed0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ed4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2edc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ee0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ee4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2eec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ef0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ef4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2efc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f00/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f04/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f0c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f10/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f14/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f1c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f20/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f24/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f2c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f30/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f34/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f3c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f40/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f44/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f4c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f50/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f54/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f5c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f60/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f64/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f6c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f70/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f74/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f7c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f80/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f84/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f8c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2f90/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2f94/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2f9c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fa0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fa4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fac/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fb0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fb4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fbc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fc0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fc4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fcc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fd0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fd4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fdc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2fe0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2fe4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2fec/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x2ff0/4, 0x0436086c); - INSTANCE_WR(ctx, 0x2ff4/4, 0x000c001b); - INSTANCE_WR(ctx, 0x2ffc/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3000/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3004/4, 0x000c001b); - INSTANCE_WR(ctx, 0x300c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3010/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3014/4, 0x000c001b); - INSTANCE_WR(ctx, 0x301c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3020/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3024/4, 0x000c001b); - INSTANCE_WR(ctx, 0x302c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3030/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3034/4, 0x000c001b); - INSTANCE_WR(ctx, 0x303c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3040/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3044/4, 0x000c001b); - INSTANCE_WR(ctx, 0x304c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3050/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3054/4, 0x000c001b); - INSTANCE_WR(ctx, 0x305c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3060/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3064/4, 0x000c001b); - INSTANCE_WR(ctx, 0x306c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3070/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3074/4, 0x000c001b); - INSTANCE_WR(ctx, 0x307c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3080/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3084/4, 0x000c001b); - INSTANCE_WR(ctx, 0x308c/4, 0x10700ff9); - INSTANCE_WR(ctx, 0x3090/4, 0x0436086c); - INSTANCE_WR(ctx, 0x3094/4, 0x000c001b); + for(i = 0x1f1c; i<= 0x308c ; i+= 16) { + INSTANCE_WR(ctx, i/4 + 0, 0x10700ff9); + INSTANCE_WR(ctx, i/4 + 1, 0x0436086c); + INSTANCE_WR(ctx, i/4 + 2, 0x000c001b); + } for(i = 0x30bc; i< 0x30cc; i += 4) INSTANCE_WR(ctx, i/4, 0x0000ffff); INSTANCE_WR(ctx, 0x3450/4, 0x3f800000); -- cgit v1.2.3 From 79744d730c90019edd367eee4a8ec1fa22d53402 Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Tue, 30 Oct 2007 16:55:17 +0100 Subject: Nouveau: add a comment about SKIPS for next API breakage. --- shared-core/nouveau_dma.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'shared-core') diff --git a/shared-core/nouveau_dma.c b/shared-core/nouveau_dma.c index ab502e6a..b33df588 100644 --- a/shared-core/nouveau_dma.c +++ b/shared-core/nouveau_dma.c @@ -29,6 +29,9 @@ #include "nouveau_drv.h" #include "nouveau_dma.h" +/* FIXME : should go into a nouveau_drm.h define ? + * (it's shared between DRI & DDX & DRM) + */ #define SKIPS 8 int -- cgit v1.2.3