From 73bf29a6c14d12f86fbce48f6f6bace0de6732a6 Mon Sep 17 00:00:00 2001 From: Michel Daenzer Date: Tue, 4 Feb 2003 19:20:18 +0000 Subject: fix PCI and AGP posting problems (based on testing by Chris Ison and suggestions by Benjamin Herrenschmidt and Arjan van de Ven) remove radeon_flush_write_combine() which has been unused for a while --- shared-core/radeon_drv.h | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) (limited to 'shared-core') diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 22c5d04f..fb8fbafe 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -824,13 +824,6 @@ do { \ * Ring control */ -#if defined(__powerpc__) -#define radeon_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring ) -#else -#define radeon_flush_write_combine() DRM_WRITEMEMORYBARRIER() -#endif - - #define RADEON_VERBOSE 0 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; @@ -864,8 +857,13 @@ do { \ dev_priv->ring.tail = write; \ } while (0) -#define COMMIT_RING() do { \ - RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ +#define COMMIT_RING() do { \ + /* Flush writes to ring */ \ + DRM_READMEMORYBARRIER(); \ + GET_RING_HEAD( &dev_priv->ring ); \ + RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ + /* read from PCI bus to ensure correct posting */ \ + RADEON_READ( RADEON_CP_RB_RPTR ); \ } while (0) #define OUT_RING( x ) do { \ -- cgit v1.2.3