From 25cedcf76fae45f8a1a63ccb6b4bc5746b7d1587 Mon Sep 17 00:00:00 2001
From: Matthieu Castet <castet.matthieu@free.fr>
Date: Sun, 1 Apr 2007 14:21:29 +0200
Subject: nouveau : nv10 ctx switch fix restoring NV10_PGRAPH_CTX_SWITCH1 now
 works

---
 shared-core/nv10_graph.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'shared-core')

diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c
index bf36136d..db2757d7 100644
--- a/shared-core/nv10_graph.c
+++ b/shared-core/nv10_graph.c
@@ -186,7 +186,7 @@ static void nv10_praph_pipe(drm_device_t *dev) {
 static int nv10_graph_ctx_regs [] = {
 NV03_PGRAPH_XY_LOGIC_MISC0,
 
-//NV10_PGRAPH_CTX_SWITCH1, make ctx switch crash
+NV10_PGRAPH_CTX_SWITCH1,
 NV10_PGRAPH_CTX_SWITCH2,
 NV10_PGRAPH_CTX_SWITCH3,
 NV10_PGRAPH_CTX_SWITCH4,
-- 
cgit v1.2.3


From cbbdbd5e653860bcae165c8abd16006d4425e3de Mon Sep 17 00:00:00 2001
From: Matthieu Castet <castet.matthieu@free.fr>
Date: Sun, 1 Apr 2007 14:31:41 +0200
Subject: nouveau: fix usage of PGRAPH_CTX_CONTROL on nv20+

http://gitweb.freedesktop.org/?p=mesa/drm.git;a=commitdiff;h=17985f07d68322519919a7f629a6d2d9bf3916ed could have broken some nvxx_graph code : it rename NV03_PGRAPH_CTX_CONTROL to NV10_PGRAPH_CTX_CONTROL, but forgot to update it in nvxx_graph file.

Also when migrating init stuff in http://gitweb.freedesktop.org/?p=mesa/drm.git;a=commitdiff;h=674cefd4fe4b537a20a10edcb4ec5df55facca8e, NV04_PGRAPH_CTX_CONTROL is used everywhere but the old ddx code use NV_PGRAPH_CTX_CONTROL_NV04 or NV_PGRAPH_CTX_CONTROL.
---
 shared-core/nv20_graph.c | 6 +++---
 shared-core/nv30_graph.c | 2 +-
 shared-core/nv40_graph.c | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c
index 45d88d6b..7190fc84 100644
--- a/shared-core/nv20_graph.c
+++ b/shared-core/nv20_graph.c
@@ -117,7 +117,7 @@ void nouveau_nv20_context_switch(drm_device_t *dev)
 	
 	nouveau_wait_for_idle(dev);
 
-	NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10000000);
+	NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000000);
 
 	nv20_graph_context_restore(dev, channel);
 
@@ -126,7 +126,7 @@ void nouveau_nv20_context_switch(drm_device_t *dev)
 	if ((NV_READ(NV10_PGRAPH_CTX_USER) >> 24) != channel)
 		DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", channel, NV_READ(NV10_PGRAPH_CTX_USER) >> 24);
 
-	NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10010100);
+	NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
 	NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
 
 	NV_WRITE(NV04_PGRAPH_FIFO,0x1);
@@ -194,7 +194,7 @@ int nv20_graph_init(drm_device_t *dev) {
 		NV_WRITE(NV10_PGRAPH_TSTATUS(i), NV_READ(NV10_PFB_TSTATUS(i)));
 	}
 
-	NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100);
+	NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
 	NV_WRITE(NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 	NV_WRITE(NV04_PGRAPH_FIFO       , 0x00000001);
 
diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c
index 391a1063..f4faadd8 100644
--- a/shared-core/nv30_graph.c
+++ b/shared-core/nv30_graph.c
@@ -182,7 +182,7 @@ int nv30_graph_init(drm_device_t *dev)
 		NV_WRITE(NV10_PGRAPH_TSTATUS(i), NV_READ(NV10_PFB_TSTATUS(i)));
 	}
 
-	NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100);
+	NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
 	NV_WRITE(NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 	NV_WRITE(NV04_PGRAPH_FIFO       , 0x00000001);
 
diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c
index 510ffa76..5d5d0dc7 100644
--- a/shared-core/nv40_graph.c
+++ b/shared-core/nv40_graph.c
@@ -947,7 +947,7 @@ nv40_graph_init(drm_device_t *dev)
 	NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000);
 	NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
 
-	NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100);
+	NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
 	NV_WRITE(NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 	NV_WRITE(NV04_PGRAPH_FIFO       , 0x00000001);
 
-- 
cgit v1.2.3


From 5395a92d40337aa3de424f87fb38cb5a0ca45bcf Mon Sep 17 00:00:00 2001
From: Oliver McFadden <z3ro.geek@gmail.com>
Date: Mon, 2 Apr 2007 19:45:10 +0000
Subject: r300: Synchronize the register header file again.

It's a good idea to keep these synchronized; even though the DRM doesn't use all
the defines, maintaining two different copies is prone to errors when the diff
gets bigger.
---
 shared-core/r300_reg.h | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/r300_reg.h b/shared-core/r300_reg.h
index a85a7d48..1f65f9a7 100644
--- a/shared-core/r300_reg.h
+++ b/shared-core/r300_reg.h
@@ -325,7 +325,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  * Most likely this is used to ignore rest of the program in cases
  * where group of verts arent visible. For some reason this "section"
  * is sometimes accepted other instruction that have no relationship with
- *position calculations. 
+ *position calculations.
  */
 #define R300_VAP_PVS_CNTL_1                 0x22D0
 #       define R300_PVS_CNTL_1_PROGRAM_START_SHIFT   0
@@ -497,6 +497,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 /* Zero to flush caches. */
 #define R300_TX_CNTL                        0x4100
+#define R300_TX_FLUSH                       0x0
 
 /* The upper enable bits are guessed, based on fglrx reported limits. */
 #define R300_TX_ENABLE                      0x4104
@@ -565,12 +566,13 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define R300_RE_FOG_SCALE                     0x4294
 #define R300_RE_FOG_START                     0x4298
 
-/* Not sure why there are duplicate of factor and constant values. 
- * My best guess so far is that there are seperate zbiases for test and write. 
+/* Not sure why there are duplicate of factor and constant values.
+ * My best guess so far is that there are seperate zbiases for test and write.
  * Ordering might be wrong.
  * Some of the tests indicate that fgl has a fallback implementation of zbias
  * via pixel shaders.
  */
+#define R300_RE_ZBIAS_CNTL                    0x42A0 /* GUESS */
 #define R300_RE_ZBIAS_T_FACTOR                0x42A4
 #define R300_RE_ZBIAS_T_CONSTANT              0x42A8
 #define R300_RE_ZBIAS_W_FACTOR                0x42AC
@@ -907,7 +909,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 /* 32 bit chroma key */
 #define R300_TX_CHROMA_KEY_0                      0x4580
 /* ff00ff00 == { 0, 1.0, 0, 1.0 } */
-#define R300_TX_BORDER_COLOR_0              0x45C0 
+#define R300_TX_BORDER_COLOR_0              0x45C0
 
 /* END: Texture specification */
 
@@ -997,6 +999,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #		define R300_FPITX_OP_KIL	2
 #		define R300_FPITX_OP_TXP	3
 #		define R300_FPITX_OP_TXB	4
+#	define R300_FPITX_OPCODE_MASK           (7 << 15)
 
 /* ALU
  * The ALU instructions register blocks are enumerated according to the order
@@ -1045,7 +1048,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  * WRT swizzling. If, for example, you want to load an R component into an
  * Alpha operand, this R component is taken from a *color* source, not from
  * an alpha source. The corresponding register doesn't even have to appear in
- * the alpha sources list. (I hope this alll makes sense to you)
+ * the alpha sources list. (I hope this all makes sense to you)
  *
  * Destination selection
  * The destination register index is in FPI1 (color) and FPI3 (alpha)
@@ -1072,6 +1075,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #       define R300_FPI1_SRC2C_SHIFT             12
 #       define R300_FPI1_SRC2C_MASK              (31 << 12)
 #       define R300_FPI1_SRC2C_CONST             (1 << 17)
+#       define R300_FPI1_SRC_MASK                0x0003ffff
 #       define R300_FPI1_DSTC_SHIFT              18
 #       define R300_FPI1_DSTC_MASK               (31 << 18)
 #		define R300_FPI1_DSTC_REG_MASK_SHIFT     23
@@ -1093,6 +1097,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #       define R300_FPI3_SRC2A_SHIFT             12
 #       define R300_FPI3_SRC2A_MASK              (31 << 12)
 #       define R300_FPI3_SRC2A_CONST             (1 << 17)
+#       define R300_FPI3_SRC_MASK                0x0003ffff
 #       define R300_FPI3_DSTA_SHIFT              18
 #       define R300_FPI3_DSTA_MASK               (31 << 18)
 #       define R300_FPI3_DSTA_REG                (1 << 23)
-- 
cgit v1.2.3


From 139e4bbc73c65d6e1d7fc831ae15c8b28f92e821 Mon Sep 17 00:00:00 2001
From: Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
Date: Tue, 3 Apr 2007 10:21:41 +0200
Subject: Make sure we ack irqs before we read a breadcrumb so that

breadcrumb updates that occur _AFTER_ we've read the breadcrumb really
generates a new IRQ.
---
 shared-core/i915_irq.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'shared-core')

diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c
index 5da54107..4047e77e 100644
--- a/shared-core/i915_irq.c
+++ b/shared-core/i915_irq.c
@@ -294,6 +294,8 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 		return IRQ_NONE;
 
 	I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
+	(void) I915_READ16(I915REG_INT_IDENTITY_R);
+	DRM_READMEMORYBARRIER();
 
 	dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 
-- 
cgit v1.2.3


From 38f52402a8b7126f0c1ceccf7c1843b1a5247ef6 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <skeggsb@gmail.com>
Date: Fri, 6 Apr 2007 03:03:59 +1000
Subject: nouveau: Power up all card units by default on startup.

---
 shared-core/nv04_mc.c | 5 +++++
 shared-core/nv40_mc.c | 5 +++++
 2 files changed, 10 insertions(+)

(limited to 'shared-core')

diff --git a/shared-core/nv04_mc.c b/shared-core/nv04_mc.c
index 2619eb71..0e23efb2 100644
--- a/shared-core/nv04_mc.c
+++ b/shared-core/nv04_mc.c
@@ -8,6 +8,11 @@ nv04_mc_init(drm_device_t *dev)
 {
 	drm_nouveau_private_t *dev_priv = dev->dev_private;
 
+	/* Power up everything, resetting each individual unit will
+	 * be done later if needed.
+	 */
+	NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF);
+
 	NV_WRITE(NV03_PMC_INTR_EN_0, 0);
 
 	return 0;
diff --git a/shared-core/nv40_mc.c b/shared-core/nv40_mc.c
index 554a2241..8dbd96fd 100644
--- a/shared-core/nv40_mc.c
+++ b/shared-core/nv40_mc.c
@@ -9,6 +9,11 @@ nv40_mc_init(drm_device_t *dev)
 	drm_nouveau_private_t *dev_priv = dev->dev_private;
 	uint32_t tmp;
 
+	/* Power up everything, resetting each individual unit will
+	 * be done later if needed.
+	 */
+	NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF);
+
 	NV_WRITE(NV03_PMC_INTR_EN_0, 0);
 
 	switch (dev_priv->chipset) {
-- 
cgit v1.2.3


From 78034c06dfc0cd79cc47c2daa119ca3ee2a4fed4 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <skeggsb@gmail.com>
Date: Fri, 6 Apr 2007 03:24:39 +1000
Subject: nouveau: make a note about a bit that breaks some cards

---
 shared-core/nouveau_reg.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'shared-core')

diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h
index 3360fec2..ea4a2f6b 100644
--- a/shared-core/nouveau_reg.h
+++ b/shared-core/nouveau_reg.h
@@ -65,6 +65,10 @@
 #define NV03_PMC_ENABLE                                    0x00000200
 #    define NV_PMC_ENABLE_PFIFO                               (1<< 8)
 #    define NV_PMC_ENABLE_PGRAPH                              (1<<12)
+/* Disabling the below bit breaks newer (G7X only?) mobile chipsets,
+ * the card will hang early on in the X init process.
+ */
+#    define NV_PMC_ENABLE_UNK13                               (1<<13)
 #define NV40_PMC_1700                                      0x00001700
 #define NV40_PMC_1704                                      0x00001704
 #define NV40_PMC_1708                                      0x00001708
-- 
cgit v1.2.3


From 46257c51c1e402cf04007f01a90cb423b141f89e Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Sun, 1 Apr 2007 16:30:52 +1000
Subject: i915: use breadcrumb macro everywhere

---
 shared-core/i915_dma.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index aed3eea1..f66c08e6 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -643,7 +643,6 @@ static int i915_batchbuffer(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-	u32 *hw_status = dev_priv->hw_status_page;
 	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 	    dev_priv->sarea_priv;
 	drm_i915_batchbuffer_t batch;
@@ -669,7 +668,7 @@ static int i915_batchbuffer(DRM_IOCTL_ARGS)
 
 	ret = i915_dispatch_batchbuffer(dev, &batch);
 
-	sarea_priv->last_dispatch = (int)hw_status[5];
+	sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 	return ret;
 }
 
@@ -677,7 +676,6 @@ static int i915_cmdbuffer(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-	u32 *hw_status = dev_priv->hw_status_page;
 	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 	    dev_priv->sarea_priv;
 	drm_i915_cmdbuffer_t cmdbuf;
@@ -705,7 +703,7 @@ static int i915_cmdbuffer(DRM_IOCTL_ARGS)
 		return ret;
 	}
 
-	sarea_priv->last_dispatch = (int)hw_status[5];
+	sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 	return 0;
 }
 
-- 
cgit v1.2.3


From a70f8e0ab265cc4a26ed2f9e92ab0618bd920a93 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Mon, 9 Apr 2007 21:52:59 +1000
Subject: radeon: add support for reverse engineered xpress200m

The IGPGART setup code was traced using mmio-trace on fglrx by myself
and Phillip Ezolt <phillipezolt@gmail.com> on dri-devel.

This code doesn't let the 3D driver work properly as the card has no
vertex shader support.

Thanks to Matthew Garrett + Ubuntu for providing me some hardware to do this
work on.
---
 shared-core/drm_pciids.txt |  1 +
 shared-core/r128_cce.c     |  2 +-
 shared-core/radeon_cp.c    | 66 +++++++++++++++++++++++++++++++++++++++++++---
 shared-core/radeon_drv.h   | 19 +++++++++++++
 4 files changed, 83 insertions(+), 5 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt
index 5cea11a7..72c28627 100644
--- a/shared-core/drm_pciids.txt
+++ b/shared-core/drm_pciids.txt
@@ -98,6 +98,7 @@
 0x1002 0x5653 CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon Mobility X700 M26"
 0x1002 0x5834 CHIP_RS300|RADEON_IS_IGP "ATI Radeon RS300 9100 IGP"
 0x1002 0x5835 CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY "ATI Radeon RS300 Mobility IGP"
+0x1002 0x5955 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon XPRESS 200M 5955"
 0x1002 0x5960 CHIP_RV280 "ATI Radeon RV280 9250"
 0x1002 0x5961 CHIP_RV280 "ATI Radeon RV280 9200"
 0x1002 0x5962 CHIP_RV280 "ATI Radeon RV280 9200"
diff --git a/shared-core/r128_cce.c b/shared-core/r128_cce.c
index 62859d5a..fc7bb8fc 100644
--- a/shared-core/r128_cce.c
+++ b/shared-core/r128_cce.c
@@ -563,7 +563,7 @@ static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init)
 		dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;
 		dev_priv->gart_info.addr = NULL;
 		dev_priv->gart_info.bus_addr = 0;
-		dev_priv->gart_info.is_pcie = 0;
+		dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
 		if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
 			DRM_ERROR("failed to init PCI GART!\n");
 			dev->dev_private = (void *)dev_priv;
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index e02796e7..a741eb7f 100644
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -824,12 +824,21 @@ static int RADEON_READ_PLL(drm_device_t * dev, int addr)
 	return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 }
 
-static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
+static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 {
 	RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 	return RADEON_READ(RADEON_PCIE_DATA);
 }
 
+static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
+{
+	u32 ret;
+	RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
+	ret = RADEON_READ(RADEON_IGPGART_DATA);
+	RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
+	return ret;
+}
+
 #if RADEON_FIFO_DEBUG
 static void radeon_status(drm_radeon_private_t * dev_priv)
 {
@@ -1266,7 +1275,45 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 	}
 }
 
-/* Enable or disable PCI-E GART on the chip */
+/* Enable or disable IGP GART on the chip */
+static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+{
+	u32 temp, tmp;
+
+	tmp = RADEON_READ(RADEON_AIC_CNTL);
+	DRM_DEBUG("setting igpgart AIC CNTL is %08X\n", tmp);
+	if (on) {
+		DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
+			 dev_priv->gart_vm_start,
+			 (long)dev_priv->gart_info.bus_addr,
+			 dev_priv->gart_size);
+
+		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
+		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_38, 0x1);
+		RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
+		RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
+				     dev_priv->gart_info.bus_addr);
+
+		temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
+		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
+
+		RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
+		dev_priv->gart_size = 32*1024*1024;
+		RADEON_WRITE(RADEON_MC_AGP_LOCATION,
+			     (((dev_priv->gart_vm_start - 1 +
+			       dev_priv->gart_size) & 0xffff0000) |
+			     (dev_priv->gart_vm_start >> 16)));
+
+		temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_38);
+		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_38, temp);
+
+		RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_2E);
+		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_2E, 0x1);
+		RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_2E);
+		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_2E, 0x0);
+       }
+}
+
 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 {
 	u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
@@ -1301,6 +1348,11 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 {
 	u32 tmp;
 
+	if (dev_priv->flags & RADEON_IS_IGPGART) {
+		radeon_set_igpgart(dev_priv, on);
+		return;
+	}
+
 	if (dev_priv->flags & RADEON_IS_PCIE) {
 		radeon_set_pciegart(dev_priv, on);
 		return;
@@ -1635,8 +1687,10 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
 			dev_priv->gart_info.addr =
 			    dev_priv->gart_info.mapping.handle;
 
-			dev_priv->gart_info.is_pcie =
-			    !!(dev_priv->flags & RADEON_IS_PCIE);
+			if (dev_priv->flags & RADEON_IS_PCIE)
+				dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
+			else
+				dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
 			dev_priv->gart_info.gart_table_location =
 			    DRM_ATI_GART_FB;
 
@@ -1644,6 +1698,10 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
 				  dev_priv->gart_info.addr,
 				  dev_priv->pcigart_offset);
 		} else {
+			if (dev_priv->flags & RADEON_IS_IGPGART)
+				dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
+			else
+				dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
 			dev_priv->gart_info.gart_table_location =
 			    DRM_ATI_GART_MAIN;
 			dev_priv->gart_info.addr = NULL;
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 3e56af30..646b2c56 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -145,6 +145,7 @@ enum radeon_chip_flags {
 	RADEON_IS_PCIE = 0x00200000UL,
 	RADEON_NEW_MEMMAP = 0x00400000UL,
 	RADEON_IS_PCI = 0x00800000UL,
+	RADEON_IS_IGPGART = 0x01000000UL,
 };
 
 #define GET_RING_HEAD(dev_priv)	(dev_priv->writeback_works ? \
@@ -432,6 +433,16 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp,
 #define RADEON_PCIE_TX_GART_END_LO	0x16
 #define RADEON_PCIE_TX_GART_END_HI	0x17
 
+#define RADEON_IGPGART_INDEX            0x168
+#define RADEON_IGPGART_DATA             0x16c
+#define RADEON_IGPGART_UNK_18           0x18
+#define RADEON_IGPGART_CTRL             0x2b
+#define RADEON_IGPGART_BASE_ADDR        0x2c
+#define RADEON_IGPGART_UNK_2E           0x2e
+#define RADEON_IGPGART_UNK_38           0x38
+#define RADEON_IGPGART_UNK_39           0x39
+
+
 #define RADEON_MPP_TB_CONFIG		0x01c0
 #define RADEON_MEM_CNTL			0x0140
 #define RADEON_MEM_SDRAM_MODE_REG	0x0158
@@ -994,6 +1005,14 @@ do {									\
 	RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) );			\
 } while (0)
 
+#define RADEON_WRITE_IGPGART( addr, val )				\
+do {									\
+	RADEON_WRITE( RADEON_IGPGART_INDEX,				\
+			((addr) & 0x7f) | (1 << 8));			\
+	RADEON_WRITE( RADEON_IGPGART_DATA, (val) );			\
+	RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f );			\
+} while (0)
+
 #define RADEON_WRITE_PCIE( addr, val )					\
 do {									\
 	RADEON_WRITE8( RADEON_PCIE_INDEX,				\
-- 
cgit v1.2.3


From 29f8fe80469a161c89c1a690ae2b62b3c21e4794 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Mon, 9 Apr 2007 22:00:34 +1000
Subject: radeon: bump version for IGPGART support

---
 shared-core/radeon_drv.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'shared-core')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 646b2c56..950f6828 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -96,10 +96,11 @@
  * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
  *       new packet type)
  * 1.26- Add support for variable size PCI(E) gart aperture
+ * 1.27- Add support for IGP GART
  */
 
 #define DRIVER_MAJOR		1
-#define DRIVER_MINOR		26
+#define DRIVER_MINOR		27
 #define DRIVER_PATCHLEVEL	0
 
 /*
-- 
cgit v1.2.3


From 2d7f9f59c3ae9dbaa516ee45ae26b32825e7bf3e Mon Sep 17 00:00:00 2001
From: Ben Skeggs <skeggsb@gmail.com>
Date: Mon, 9 Apr 2007 23:20:26 +1000
Subject: nouveau: NV46 support

---
 shared-core/nv40_graph.c | 189 ++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 188 insertions(+), 1 deletion(-)

(limited to 'shared-core')

diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c
index 5d5d0dc7..792734ed 100644
--- a/shared-core/nv40_graph.c
+++ b/shared-core/nv40_graph.c
@@ -10,6 +10,7 @@
  */
 #define NV40_GRCTX_SIZE (175*1024)
 #define NV43_GRCTX_SIZE (70*1024)
+#define NV46_GRCTX_SIZE (70*1024) /* probably ~64KiB */
 #define NV4A_GRCTX_SIZE (64*1024)
 #define NV4C_GRCTX_SIZE (25*1024)
 #define NV4E_GRCTX_SIZE (25*1024)
@@ -274,6 +275,156 @@ nv43_graph_context_init(drm_device_t *dev, struct mem_block *ctx)
 		INSTANCE_WR(ctx, i/4, 0x3f800000);
 };
 
+static void nv46_graph_context_init(drm_device_t *dev, struct mem_block *ctx)
+{
+	drm_nouveau_private_t *dev_priv = dev->dev_private;
+	int i;
+
+	INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx));
+	INSTANCE_WR(ctx, 0x00040/4, 0x0000ffff);
+	INSTANCE_WR(ctx, 0x00044/4, 0x0000ffff);
+	INSTANCE_WR(ctx, 0x0004c/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00138/4, 0x20010001);
+	INSTANCE_WR(ctx, 0x0013c/4, 0x0f73ef00);
+	INSTANCE_WR(ctx, 0x00144/4, 0x02008821);
+	INSTANCE_WR(ctx, 0x00174/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00178/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x0017c/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00180/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00184/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00188/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x0018c/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00190/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00194/4, 0x00000040);
+	INSTANCE_WR(ctx, 0x00198/4, 0x00000040);
+	INSTANCE_WR(ctx, 0x0019c/4, 0x00000040);
+	INSTANCE_WR(ctx, 0x001a4/4, 0x00000040);
+	INSTANCE_WR(ctx, 0x001ec/4, 0x0b0b0b0c);
+	INSTANCE_WR(ctx, 0x0035c/4, 0x00040000);
+	INSTANCE_WR(ctx, 0x0036c/4, 0x55555555);
+	INSTANCE_WR(ctx, 0x00370/4, 0x55555555);
+	INSTANCE_WR(ctx, 0x00374/4, 0x55555555);
+	INSTANCE_WR(ctx, 0x00378/4, 0x55555555);
+	INSTANCE_WR(ctx, 0x003a4/4, 0x00000008);
+	INSTANCE_WR(ctx, 0x003b8/4, 0x00003010);
+	INSTANCE_WR(ctx, 0x003dc/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x003e0/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x003e4/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x003e8/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x003ec/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x003f0/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x003f4/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x003f8/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x003fc/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x00400/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x00404/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x00408/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x0040c/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x00410/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x00414/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x00418/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x004b0/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x004b4/4, 0x00080060);
+	INSTANCE_WR(ctx, 0x004d0/4, 0x00000080);
+	INSTANCE_WR(ctx, 0x004d4/4, 0xffff0000);
+	INSTANCE_WR(ctx, 0x004d8/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x004ec/4, 0x46400000);
+	INSTANCE_WR(ctx, 0x004fc/4, 0xffff0000);
+	INSTANCE_WR(ctx, 0x00500/4, 0x88888888);
+	INSTANCE_WR(ctx, 0x00504/4, 0x88888888);
+	INSTANCE_WR(ctx, 0x00508/4, 0x88888888);
+	INSTANCE_WR(ctx, 0x0050c/4, 0x88888888);
+	INSTANCE_WR(ctx, 0x00510/4, 0x88888888);
+	INSTANCE_WR(ctx, 0x00514/4, 0x88888888);
+	INSTANCE_WR(ctx, 0x00518/4, 0x88888888);
+	INSTANCE_WR(ctx, 0x0051c/4, 0x88888888);
+	INSTANCE_WR(ctx, 0x00520/4, 0x88888888);
+	INSTANCE_WR(ctx, 0x00524/4, 0x88888888);
+	INSTANCE_WR(ctx, 0x00528/4, 0x88888888);
+	INSTANCE_WR(ctx, 0x0052c/4, 0x88888888);
+	INSTANCE_WR(ctx, 0x00530/4, 0x88888888);
+	INSTANCE_WR(ctx, 0x00534/4, 0x88888888);
+	INSTANCE_WR(ctx, 0x00538/4, 0x88888888);
+	INSTANCE_WR(ctx, 0x0053c/4, 0x88888888);
+	INSTANCE_WR(ctx, 0x00550/4, 0x0fff0000);
+	INSTANCE_WR(ctx, 0x00554/4, 0x0fff0000);
+	INSTANCE_WR(ctx, 0x0055c/4, 0x00011100);
+	for (i=0x00578; i<0x005b4; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x07ff0000);
+	INSTANCE_WR(ctx, 0x005c0/4, 0x4b7fffff);
+	INSTANCE_WR(ctx, 0x005e8/4, 0x30201000);
+	INSTANCE_WR(ctx, 0x005ec/4, 0x70605040);
+	INSTANCE_WR(ctx, 0x005f0/4, 0xb8a89888);
+	INSTANCE_WR(ctx, 0x005f4/4, 0xf8e8d8c8);
+	INSTANCE_WR(ctx, 0x00608/4, 0x40100000);
+	INSTANCE_WR(ctx, 0x00624/4, 0x0000ffff);
+	INSTANCE_WR(ctx, 0x00658/4, 0x435185d6);
+	INSTANCE_WR(ctx, 0x0065c/4, 0x2155b699);
+	INSTANCE_WR(ctx, 0x00660/4, 0xfedcba98);
+	INSTANCE_WR(ctx, 0x00664/4, 0x00000098);
+	INSTANCE_WR(ctx, 0x00674/4, 0xffffffff);
+	INSTANCE_WR(ctx, 0x00678/4, 0x00ff7000);
+	INSTANCE_WR(ctx, 0x0067c/4, 0x0000ffff);
+	INSTANCE_WR(ctx, 0x0068c/4, 0x00ff0000);
+	INSTANCE_WR(ctx, 0x006c8/4, 0x00ffff00);
+	for (i=0x0070c; i<=0x00748; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x00018488);
+	for (i=0x0074c; i<=0x00788; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x00028202);
+	for (i=0x007cc; i<=0x00808; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x0000aae4);
+	for (i=0x0080c; i<=0x00848; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x01012000);
+	for (i=0x0084c; i<=0x00888; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x00080008);
+	for (i=0x008cc; i<=0x00908; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x00100008);
+	for (i=0x0095c; i<=0x00968; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x0001bc80);
+	for (i=0x0096c; i<=0x00978; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x00000202);
+	for (i=0x0098c; i<=0x00998; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x00000008);
+	for (i=0x009ac; i<=0x009b8; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x00080008);
+	INSTANCE_WR(ctx, 0x009cc/4, 0x00000002);
+	INSTANCE_WR(ctx, 0x00a00/4, 0x00000421);
+	INSTANCE_WR(ctx, 0x00a04/4, 0x030c30c3);
+	INSTANCE_WR(ctx, 0x00a08/4, 0x00011001);
+	INSTANCE_WR(ctx, 0x00a14/4, 0x3e020200);
+	INSTANCE_WR(ctx, 0x00a18/4, 0x00ffffff);
+	INSTANCE_WR(ctx, 0x00a1c/4, 0x0c103f00);
+	INSTANCE_WR(ctx, 0x00a28/4, 0x00040000);
+	INSTANCE_WR(ctx, 0x00a60/4, 0x00008100);
+	INSTANCE_WR(ctx, 0x00aec/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00b30/4, 0x00001001);
+	INSTANCE_WR(ctx, 0x00b38/4, 0x00000003);
+	INSTANCE_WR(ctx, 0x00b3c/4, 0x00888001);
+	INSTANCE_WR(ctx, 0x00bc0/4, 0x00000005);
+	INSTANCE_WR(ctx, 0x00bcc/4, 0x0000ffff);
+	INSTANCE_WR(ctx, 0x00be8/4, 0x00005555);
+	INSTANCE_WR(ctx, 0x00bec/4, 0x00005555);
+	INSTANCE_WR(ctx, 0x00bf0/4, 0x00005555);
+	INSTANCE_WR(ctx, 0x00bf4/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00c2c/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00c30/4, 0x08e00001);
+	INSTANCE_WR(ctx, 0x00c34/4, 0x000e3000);
+	for (i=0x017f8; i<=0x01870; i+=8)
+		INSTANCE_WR(ctx, i/4, 0x3f800000);
+	for (i=0x035b8; i<=0x057a8; i+=24)
+		INSTANCE_WR(ctx, i/4, 0x00000001);
+	for (i=0x057b8; i<=0x05ba8; i+=16)
+		INSTANCE_WR(ctx, i/4, 0x3f800000);
+	for (i=0x07f38; i<=0x0a128; i+=24)
+		INSTANCE_WR(ctx, i/4, 0x00000001);
+	for (i=0x0a138; i<=0x0a528; i+=16)
+		INSTANCE_WR(ctx, i/4, 0x3f800000);
+	for (i=0x0c8b8; i<=0x0eaa8; i+=24)
+		INSTANCE_WR(ctx, i/4, 0x00000001);
+	for (i=0x0eab8; i<=0x0eea8; i+=16)
+		INSTANCE_WR(ctx, i/4, 0x3f800000);
+}
+
 static void nv4a_graph_context_init(drm_device_t *dev, struct mem_block *ctx)
 {
 	drm_nouveau_private_t *dev_priv = dev->dev_private;
@@ -622,6 +773,10 @@ nv40_graph_context_create(drm_device_t *dev, int channel)
 		ctx_size = NV43_GRCTX_SIZE;
 		ctx_init = nv43_graph_context_init;
 		break;
+	case 0x46:
+		ctx_size = NV46_GRCTX_SIZE;
+		ctx_init = nv46_graph_context_init;
+		break;
 	case 0x4a:
 		ctx_size = NV4A_GRCTX_SIZE;
 		ctx_init = nv4a_graph_context_init;
@@ -821,6 +976,37 @@ static uint32_t nv43_ctx_voodoo[] = {
 	~0
 };
 
+static uint32_t nv46_ctx_voodoo[] = {
+	0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
+	0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00408f65, 0x00409306,
+	0x0040a068, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042,
+	0x00200001, 0x0060000a, 0x00700000, 0x001040c5, 0x00401826, 0x00401968,
+	0x0060000d, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,
+	0x004020e6, 0x007000a0, 0x00500060, 0x00200008, 0x0060000a, 0x0011814d,
+	0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,
+	0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e,
+	0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143,
+	0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10,
+	0x00500060, 0x00403f87, 0x0060000d, 0x004079e6, 0x002000f7, 0x0060000a,
+	0x00200045, 0x00100620, 0x00104668, 0x0017466d, 0x0011068b, 0x00168691,
+	0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6, 0x00200022,
+	0x001006cc, 0x001246f0, 0x002000c0, 0x00100700, 0x0010c3d7, 0x001043e1,
+	0x00500060, 0x0020027f, 0x0060000a, 0x00104800, 0x00108901, 0x00104910,
+	0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00148a00, 0x00108a14,
+	0x00160b00, 0x00134b2c, 0x0010cd00, 0x0010cd04, 0x0010cd08, 0x00104d80,
+	0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06, 0x00105406, 0x00105709,
+	0x00200316, 0x0060000a, 0x00300000, 0x00200080, 0x00407200, 0x00200084,
+	0x00800001, 0x0020055e, 0x0060000a, 0x002037e0, 0x0040788a, 0x00201320,
+	0x00800029, 0x00408900, 0x00600006, 0x004085e6, 0x00700080, 0x00200081,
+	0x0060000a, 0x00104280, 0x00200316, 0x0060000a, 0x00200004, 0x00800001,
+	0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a068, 0x00700000,
+	0x00200000, 0x0060000a, 0x00106002, 0x00700080, 0x00400a68, 0x00500060,
+	0x00600007, 0x00409388, 0x0060000f, 0x00500060, 0x00200000, 0x0060000a,
+	0x00700000, 0x00106001, 0x00910880, 0x00901ffe, 0x01940000, 0x00200020,
+	0x0060000b, 0x00500069, 0x0060000c, 0x00402168, 0x0040a206, 0x0040a305,
+	0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0
+};
+
 static uint32_t nv4a_ctx_voodoo[] = {
 	0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, 
 	0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409965, 0x00409e06, 
@@ -891,7 +1077,7 @@ static uint32_t nv4e_ctx_voodoo[] = {
  * G70		0x47
  * G71		0x49
  * NV45		0x48
- * G72		0x46
+ * G72[M]	0x46
  * G73		0x4b
  * C51_G7X	0x4c
  * C51		0x4e
@@ -913,6 +1099,7 @@ nv40_graph_init(drm_device_t *dev)
 	switch (dev_priv->chipset) {
 	case 0x40: ctx_voodoo = nv40_ctx_voodoo; break;
 	case 0x43: ctx_voodoo = nv43_ctx_voodoo; break;
+	case 0x46: ctx_voodoo = nv46_ctx_voodoo; break;
 	case 0x4a: ctx_voodoo = nv4a_ctx_voodoo; break;
 	case 0x4e: ctx_voodoo = nv4e_ctx_voodoo; break;
 	default:
-- 
cgit v1.2.3


From 059b5d90770e32ba3d6d9a62acf74b352de7f421 Mon Sep 17 00:00:00 2001
From: Oliver McFadden <z3ro.geek@gmail.com>
Date: Mon, 9 Apr 2007 23:23:40 +0000
Subject: rs480: Renamed some unknown registers. See dri-devel list.

---
 shared-core/radeon_cp.c  | 14 +++++++-------
 shared-core/radeon_drv.h |  4 ++--
 2 files changed, 9 insertions(+), 9 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index a741eb7f..bfc2d088 100644
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -1289,7 +1289,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 			 dev_priv->gart_size);
 
 		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_38, 0x1);
+		RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
 		RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
 		RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
 				     dev_priv->gart_info.bus_addr);
@@ -1304,13 +1304,13 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 			       dev_priv->gart_size) & 0xffff0000) |
 			     (dev_priv->gart_vm_start >> 16)));
 
-		temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_38);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_38, temp);
+		temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
+		RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
 
-		RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_2E);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_2E, 0x1);
-		RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_2E);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_2E, 0x0);
+		RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
+		RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
+		RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
+		RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
        }
 }
 
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 950f6828..00646c8f 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -439,8 +439,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp,
 #define RADEON_IGPGART_UNK_18           0x18
 #define RADEON_IGPGART_CTRL             0x2b
 #define RADEON_IGPGART_BASE_ADDR        0x2c
-#define RADEON_IGPGART_UNK_2E           0x2e
-#define RADEON_IGPGART_UNK_38           0x38
+#define RADEON_IGPGART_FLUSH            0x2e
+#define RADEON_IGPGART_ENABLE           0x38
 #define RADEON_IGPGART_UNK_39           0x39
 
 
-- 
cgit v1.2.3


From 9b7211dd6793dc62d11ad1ae980b22fa2d61f9dd Mon Sep 17 00:00:00 2001
From: Matthieu Castet <castet.matthieu@free.fr>
Date: Tue, 10 Apr 2007 23:19:29 +0200
Subject: nouveau: nv10 per channel init from ddx

---
 shared-core/nv10_graph.c | 99 +++++++++++++++++++++++++++++++++---------------
 1 file changed, 69 insertions(+), 30 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c
index db2757d7..4cc44e21 100644
--- a/shared-core/nv10_graph.c
+++ b/shared-core/nv10_graph.c
@@ -527,6 +527,37 @@ NV10_PGRAPH_DEBUG_4,
 0x00400a04,
 };
 
+static int nv10_graph_ctx_regs_find_offset(drm_device_t *dev, int reg)
+{
+	drm_nouveau_private_t *dev_priv = dev->dev_private;
+	int i, j;
+	for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) {
+		if (nv10_graph_ctx_regs[i] == reg)
+			return i;
+	}
+	if (dev_priv->chipset>=0x17) {
+		for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) {
+			if (nv17_graph_ctx_regs[j] == reg)
+				return i;
+		}
+	}
+	return -1;
+}
+
+static void restore_ctx_regs(drm_device_t *dev, int channel)
+{
+	drm_nouveau_private_t *dev_priv = dev->dev_private;
+	struct nouveau_fifo *fifo = &dev_priv->fifos[channel];
+	int i, j;
+	for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++)
+		NV_WRITE(nv10_graph_ctx_regs[i], fifo->pgraph_ctx[i]);
+	if (dev_priv->chipset>=0x17) {
+		for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++)
+			NV_WRITE(nv17_graph_ctx_regs[j], fifo->pgraph_ctx[i]);
+	}
+	nouveau_wait_for_idle(dev);
+}
+
 void nouveau_nv10_context_switch(drm_device_t *dev)
 {
 	drm_nouveau_private_t *dev_priv = dev->dev_private;
@@ -559,15 +590,8 @@ void nouveau_nv10_context_switch(drm_device_t *dev)
 
 	nouveau_wait_for_idle(dev);
 	// restore PGRAPH context
-	//XXX not working yet
 #if 1
-	for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++)
-		NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].pgraph_ctx[i]);
-	if (dev_priv->chipset>=0x17) {
-		for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++)
-			NV_WRITE(nv17_graph_ctx_regs[j], dev_priv->fifos[channel].pgraph_ctx[i]);
-	}
-	nouveau_wait_for_idle(dev);
+	restore_ctx_regs(dev, channel);
 #endif
 	
 	NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
@@ -582,20 +606,52 @@ void nouveau_nv10_context_switch(drm_device_t *dev)
 	NV_WRITE(NV04_PGRAPH_FIFO,0x1);
 }
 
+#define NV_WRITE_CTX(reg, val) do { \
+	int offset = nv10_graph_ctx_regs_find_offset(dev, reg); \
+	if (offset > 0) \
+		fifo->pgraph_ctx[offset] = val; \
+	} while (0)
 int nv10_graph_context_create(drm_device_t *dev, int channel) {
 	drm_nouveau_private_t *dev_priv = dev->dev_private;
+	struct nouveau_fifo *fifo = &dev_priv->fifos[channel];
+	uint32_t tmp, vramsz;
+
 	DRM_DEBUG("nv10_graph_context_create %d\n", channel);
 
-	memset(dev_priv->fifos[channel].pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].pgraph_ctx));
+	memset(fifo->pgraph_ctx, 0, sizeof(fifo->pgraph_ctx));
+
+	/* per channel init from ddx */
+	tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
+	/*XXX the original ddx code, does this in 2 steps :
+	 * tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
+	 * NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
+	 * tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;
+	 * NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
+	 */
+	tmp |= 0x00020100;
+	NV_WRITE_CTX(NV10_PGRAPH_SURFACE, tmp);
+
+	vramsz = drm_get_resource_len(dev, 0) - 1;
+	NV_WRITE_CTX(NV04_PGRAPH_BOFFSET0, 0);
+	NV_WRITE_CTX(NV04_PGRAPH_BOFFSET1, 0);
+	NV_WRITE_CTX(NV04_PGRAPH_BLIMIT0 , vramsz);
+	NV_WRITE_CTX(NV04_PGRAPH_BLIMIT1 , vramsz);
+
+	NV_WRITE_CTX(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
+	NV_WRITE_CTX(NV04_PGRAPH_BETA_AND     , 0xFFFFFFFF);
 
-	//dev_priv->fifos[channel].pgraph_ctx_user = channel << 24;
-	dev_priv->fifos[channel].pgraph_ctx[0] = 0x0001ffff;
+
+	NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff);
 	/* is it really needed ??? */
 	if (dev_priv->chipset>=0x17) {
-		dev_priv->fifos[channel].pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 0] = NV_READ(NV10_PGRAPH_DEBUG_4);
-		dev_priv->fifos[channel].pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 1] = NV_READ(0x004006b0);
+		NV_WRITE_CTX(NV10_PGRAPH_DEBUG_4, NV_READ(NV10_PGRAPH_DEBUG_4));
+		NV_WRITE_CTX(0x004006b0, NV_READ(0x004006b0));
 	}
 
+	/* for the first channel init the regs */
+	if (dev_priv->fifo_alloc_count == 0)
+		restore_ctx_regs(dev, channel);
+
 
 	//XXX should be saved/restored for each fifo
 	//we supposed here we have X fifo and only one 3D fifo.
@@ -606,7 +662,6 @@ int nv10_graph_context_create(drm_device_t *dev, int channel) {
 
 int nv10_graph_init(drm_device_t *dev) {
 	drm_nouveau_private_t *dev_priv = dev->dev_private;
-	uint32_t tmp, vramsz;
 	int i;
 
 	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
@@ -637,23 +692,7 @@ int nv10_graph_init(drm_device_t *dev) {
 	NV_WRITE(NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 	NV_WRITE(NV04_PGRAPH_FIFO       , 0x00000001);
 
-	/* the below don't belong here, per-channel context state */
-	tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
-	NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
-	tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;
-	NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
-
-	vramsz = drm_get_resource_len(dev, 0) - 1;
-	NV_WRITE(NV04_PGRAPH_BOFFSET0, 0);
-	NV_WRITE(NV04_PGRAPH_BOFFSET1, 0);
-	NV_WRITE(NV04_PGRAPH_BLIMIT0 , vramsz);
-	NV_WRITE(NV04_PGRAPH_BLIMIT1 , vramsz);
-
-	NV_WRITE(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
-	NV_WRITE(NV04_PGRAPH_BETA_AND     , 0xFFFFFFFF);
-
 	return 0;
-
 }
 
 void nv10_graph_takedown(drm_device_t *dev)
-- 
cgit v1.2.3


From e805ca959dbef85ac7b508639a64832a7995703a Mon Sep 17 00:00:00 2001
From: Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
Date: Tue, 17 Apr 2007 08:58:23 +0200
Subject: via: Make sure we flush write-combining using a follow-up read.

---
 shared-core/via_dma.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/via_dma.c b/shared-core/via_dma.c
index 8c5a5c64..c73634e4 100644
--- a/shared-core/via_dma.c
+++ b/shared-core/via_dma.c
@@ -430,8 +430,10 @@ static int via_hook_segment(drm_via_private_t *dev_priv,
 
 	paused = 0;
 	via_flush_write_combine();
-	*dev_priv->last_pause_ptr = pause_addr_lo;
+	(void) *(volatile uint32_t *)(via_get_dma(dev_priv) -1);
+	*paused_at = pause_addr_lo;
 	via_flush_write_combine();
+	(void) *paused_at;
 	reader = *(dev_priv->hw_addr_ptr);
 	ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +
 		dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
@@ -536,7 +538,7 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv)
 			      &pause_addr_hi, & pause_addr_lo, 1) - 1;
 
 	via_flush_write_combine();
-	while(! *dev_priv->last_pause_ptr);
+	(void) *(volatile uint32_t *)dev_priv->last_pause_ptr;
 
 	VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
 	VIA_WRITE(VIA_REG_TRANSPACE, command);
-- 
cgit v1.2.3


From 61477d60c466b4aac395057a285c1d238a83ce1c Mon Sep 17 00:00:00 2001
From: Stephane Marchesin <marchesin@icps.u-strasbg.fr>
Date: Mon, 23 Apr 2007 22:37:01 +0200
Subject: nouveau: fix wacky pci id

---
 shared-core/drm_pciids.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'shared-core')

diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt
index 72c28627..f090489f 100644
--- a/shared-core/drm_pciids.txt
+++ b/shared-core/drm_pciids.txt
@@ -358,7 +358,7 @@
 0x10DE 0x0309 NV30 "NVidia Quadro FX 1000"
 0x10DE 0x0311 NV30 "NVidia GeForce FX 5600 Ultra"
 0x10DE 0x0312 NV30 "NVidia GeForce FX 5600"
-0x10DE 0x0313 NV30 "NVidia 0x0313"},
+0x10DE 0x0313 NV30 "NVidia 0x0313"
 0x10DE 0x0314 NV30 "NVidia GeForce FX 5600SE"
 0x10DE 0x0316 NV30 "NVidia 0x0316"
 0x10DE 0x0317 NV30 "NVidia 0x0317"
-- 
cgit v1.2.3


From 3c384a9ad5f964709a237cfe035ea5d6df2da5fa Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@hobbes.virtuousgeek.org>
Date: Wed, 11 Apr 2007 12:51:52 -0700
Subject: Add new buffer object type for kernel allocations that don't
 initially have a user mapping. (cherry picked from commit
 2e21779992bd5026d8ec4dea52466377dbe5a0ed)

---
 shared-core/drm.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core')

diff --git a/shared-core/drm.h b/shared-core/drm.h
index 3c59cd40..9ddb480b 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -795,6 +795,7 @@ typedef struct drm_fence_arg {
 
 typedef enum {
 	drm_bo_type_dc,
+	drm_bo_type_kernel, /* for initial kernel allocations */
 	drm_bo_type_user,
 	drm_bo_type_fake
 }drm_bo_type_t;
-- 
cgit v1.2.3


From 942d9be296df38aa69987845a08d3d607b85f83e Mon Sep 17 00:00:00 2001
From: George Sapountzis <gsap7@yahoo.gr>
Date: Thu, 26 Apr 2007 14:16:13 +0300
Subject: freebsd: remove stray apperance of IN_MODULE.

The xserver no longer uses the libc-wrapper.
---
 shared-core/drm.h | 7 -------
 1 file changed, 7 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/drm.h b/shared-core/drm.h
index 9ddb480b..b7b2ac04 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -80,14 +80,7 @@
 #define DRM_IOC_READWRITE	_IOC_READ|_IOC_WRITE
 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__)
-#if (defined(__FreeBSD__) || defined(__FreeBSD_kernel__)) && defined(IN_MODULE)
-/* Prevent name collision when including sys/ioccom.h */
-#undef ioctl
 #include <sys/ioccom.h>
-#define ioctl(a,b,c)		xf86ioctl(a,b,c)
-#else
-#include <sys/ioccom.h>
-#endif				/* __FreeBSD__ && xf86ioctl */
 #define DRM_IOCTL_NR(n)		((n) & 0xff)
 #define DRM_IOC_VOID		IOC_VOID
 #define DRM_IOC_READ		IOC_OUT
-- 
cgit v1.2.3


From e88934274ab80119d6dd139e3d780c3cdea7e9e5 Mon Sep 17 00:00:00 2001
From: George Sapountzis <gsap7@yahoo.gr>
Date: Thu, 26 Apr 2007 14:16:51 +0300
Subject: Revert "bug 7092 : add pci ids for mach64 in Dell poweredge 4200"

This reverts commit 255f3e6f76dfd267a14765dd1293229184298d89.

Rage IIc does not have a vertex setup engine.
---
 shared-core/drm_pciids.txt | 1 -
 1 file changed, 1 deletion(-)

(limited to 'shared-core')

diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt
index f090489f..ad67dda2 100644
--- a/shared-core/drm_pciids.txt
+++ b/shared-core/drm_pciids.txt
@@ -187,7 +187,6 @@
 0x1002 0x4c51 0 "3D Rage LT Pro"
 0x1002 0x4c42 0 "3D Rage LT Pro AGP-133"
 0x1002 0x4c44 0 "3D Rage LT Pro AGP-66"
-0x1002 0x4759 0 "Rage 3D IICATI 3D RAGE IIC AGP(A12/A13)"
 0x1002 0x474c 0 "Rage XC"
 0x1002 0x474f 0 "Rage XL"
 0x1002 0x4752 0 "Rage XL"
-- 
cgit v1.2.3


From 9f9c19065cecde16aa2994b6f777336a6e5f3409 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Sat, 28 Apr 2007 14:49:27 +1000
Subject: remove DRM_GETSAREA and replace with drm_getsarea function

---
 shared-core/i915_dma.c   | 2 +-
 shared-core/mach64_dma.c | 3 +--
 shared-core/mga_dma.c    | 3 +--
 shared-core/r128_cce.c   | 3 +--
 shared-core/radeon_cp.c  | 2 +-
 shared-core/savage_bci.c | 2 +-
 shared-core/via_map.c    | 2 +-
 7 files changed, 7 insertions(+), 10 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index f66c08e6..cb5dcea8 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -123,7 +123,7 @@ static int i915_initialize(drm_device_t * dev,
 {
 	memset(dev_priv, 0, sizeof(drm_i915_private_t));
 
-	DRM_GETSAREA();
+	dev_priv->sarea = drm_getsarea(dev);
 	if (!dev_priv->sarea) {
 		DRM_ERROR("can not find sarea!\n");
 		dev->dev_private = (void *)dev_priv;
diff --git a/shared-core/mach64_dma.c b/shared-core/mach64_dma.c
index 3a5fdee8..60f55900 100644
--- a/shared-core/mach64_dma.c
+++ b/shared-core/mach64_dma.c
@@ -792,8 +792,7 @@ static int mach64_do_dma_init(drm_device_t * dev, drm_mach64_init_t * init)
 	INIT_LIST_HEAD(&dev_priv->placeholders);
 	INIT_LIST_HEAD(&dev_priv->pending);
 
-	DRM_GETSAREA();
-
+	dev_priv->sarea = drm_getsarea(dev);
 	if (!dev_priv->sarea) {
 		DRM_ERROR("can not find sarea!\n");
 		dev->dev_private = (void *)dev_priv;
diff --git a/shared-core/mga_dma.c b/shared-core/mga_dma.c
index e6468d67..78448282 100644
--- a/shared-core/mga_dma.c
+++ b/shared-core/mga_dma.c
@@ -830,8 +830,7 @@ static int mga_do_init_dma(drm_device_t * dev, drm_mga_init_t * init)
 	dev_priv->texture_offset = init->texture_offset[0];
 	dev_priv->texture_size = init->texture_size[0];
 
-	DRM_GETSAREA();
-
+	dev_priv->sarea = drm_getsarea(dev);
 	if (!dev_priv->sarea) {
 		DRM_ERROR("failed to find sarea!\n");
 		return DRM_ERR(EINVAL);
diff --git a/shared-core/r128_cce.c b/shared-core/r128_cce.c
index fc7bb8fc..a2ee18b7 100644
--- a/shared-core/r128_cce.c
+++ b/shared-core/r128_cce.c
@@ -456,8 +456,7 @@ static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init)
 	dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
 					 (dev_priv->span_offset >> 5));
 
-	DRM_GETSAREA();
-
+	dev_priv->sarea = drm_getsarea(dev);
 	if (!dev_priv->sarea) {
 		DRM_ERROR("could not find sarea!\n");
 		dev->dev_private = (void *)dev_priv;
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index bfc2d088..bde98b30 100644
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -1505,13 +1505,13 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
 					 RADEON_ROUND_MODE_TRUNC |
 					 RADEON_ROUND_PREC_8TH_PIX);
 
-	DRM_GETSAREA();
 
 	dev_priv->ring_offset = init->ring_offset;
 	dev_priv->ring_rptr_offset = init->ring_rptr_offset;
 	dev_priv->buffers_offset = init->buffers_offset;
 	dev_priv->gart_textures_offset = init->gart_textures_offset;
 
+	dev_priv->sarea = drm_getsarea(dev);
 	if (!dev_priv->sarea) {
 		DRM_ERROR("could not find sarea!\n");
 		radeon_do_cleanup_cp(dev);
diff --git a/shared-core/savage_bci.c b/shared-core/savage_bci.c
index 5632b5c8..9a3ae1f1 100644
--- a/shared-core/savage_bci.c
+++ b/shared-core/savage_bci.c
@@ -710,7 +710,7 @@ static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init)
 	dev_priv->texture_offset = init->texture_offset;
 	dev_priv->texture_size = init->texture_size;
 
-	DRM_GETSAREA();
+	dev_priv->sarea = drm_getsarea(dev);
 	if (!dev_priv->sarea) {
 		DRM_ERROR("could not find sarea!\n");
 		savage_do_cleanup_bci(dev);
diff --git a/shared-core/via_map.c b/shared-core/via_map.c
index 83324cfa..037a1c2c 100644
--- a/shared-core/via_map.c
+++ b/shared-core/via_map.c
@@ -32,7 +32,7 @@ static int via_do_init_map(drm_device_t * dev, drm_via_init_t * init)
 
 	DRM_DEBUG("%s\n", __FUNCTION__);
 
-	DRM_GETSAREA();
+	dev_priv->sarea = drm_getsarea(dev);
 	if (!dev_priv->sarea) {
 		DRM_ERROR("could not find sarea!\n");
 		dev->dev_private = (void *)dev_priv;
-- 
cgit v1.2.3


From feb68037784ac09e333a321d294fdb2d8c57a4c8 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Sat, 28 Apr 2007 15:07:22 +1000
Subject: move i915 to new drm_wait_on function

---
 shared-core/i915_irq.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c
index 4047e77e..8748b647 100644
--- a/shared-core/i915_irq.c
+++ b/shared-core/i915_irq.c
@@ -381,6 +381,13 @@ void i915_user_irq_off(drm_i915_private_t *dev_priv)
 	spin_unlock(&dev_priv->user_irq_lock);
 }
 		
+static int wait_compare(struct drm_device *dev, void *priv)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	int irq_nr = (u64)priv;
+
+	return (READ_BREADCRUMB(dev_priv) >= irq_nr);
+}
 
 static int i915_wait_irq(drm_device_t * dev, int irq_nr)
 {
@@ -396,8 +403,8 @@ static int i915_wait_irq(drm_device_t * dev, int irq_nr)
 	dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 	
 	i915_user_irq_on(dev_priv);
-	DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
-		    READ_BREADCRUMB(dev_priv) >= irq_nr);
+	ret = drm_wait_on(dev, &dev_priv->irq_queue, 3 * DRM_HZ, wait_compare,
+			  (void *)(u64)irq_nr);
 	i915_user_irq_off(dev_priv);
 
 	if (ret == DRM_ERR(EBUSY)) {
-- 
cgit v1.2.3


From ca1cd3257c7c41821788ca45d45e51065f436803 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel@tungstengraphics.com>
Date: Sun, 29 Apr 2007 12:17:57 +0200
Subject: radeon: Don't mess up page flipping when a file descriptor is closed.

There can still be other contexts that may use page flipping later on, so don't
just unilaterally 'clean it up', which could lead to the wrong page being
displayed, e.g. when running 3D apps with a GLX compositing manager such as
compiz using page flipping.
---
 shared-core/radeon_drv.h   |  1 -
 shared-core/radeon_state.c | 46 +++++++++++++++++++---------------------------
 2 files changed, 19 insertions(+), 28 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 00646c8f..4a36ea70 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -245,7 +245,6 @@ typedef struct drm_radeon_private {
 
 	int do_boxes;
 	int page_flipping;
-	int current_page;
 
 	u32 color_fmt;
 	unsigned int front_offset;
diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c
index b95549d8..bad054d7 100644
--- a/shared-core/radeon_state.c
+++ b/shared-core/radeon_state.c
@@ -773,7 +773,7 @@ static void radeon_clear_box(drm_radeon_private_t * dev_priv,
 		 RADEON_GMC_SRC_DATATYPE_COLOR |
 		 RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);
 
-	if (dev_priv->page_flipping && dev_priv->current_page == 1) {
+	if (dev_priv->sarea_priv->pfCurrentPage == 1) {
 		OUT_RING(dev_priv->front_pitch_offset);
 	} else {
 		OUT_RING(dev_priv->back_pitch_offset);
@@ -861,7 +861,7 @@ static void radeon_cp_dispatch_clear(drm_device_t * dev,
 
 	dev_priv->stats.clears++;
 
-	if (dev_priv->page_flipping && dev_priv->current_page == 1) {
+	if (dev_priv->sarea_priv->pfCurrentPage == 1) {
 		unsigned int tmp = flags;
 
 		flags &= ~(RADEON_FRONT | RADEON_BACK);
@@ -1382,7 +1382,7 @@ static void radeon_cp_dispatch_swap(drm_device_t * dev)
 		/* Make this work even if front & back are flipped:
 		 */
 		OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1));
-		if (dev_priv->current_page == 0) {
+		if (dev_priv->sarea_priv->pfCurrentPage == 0) {
 			OUT_RING(dev_priv->back_pitch_offset);
 			OUT_RING(dev_priv->front_pitch_offset);
 		} else {
@@ -1416,12 +1416,12 @@ static void radeon_cp_dispatch_flip(drm_device_t * dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_sarea_t *sarea = (drm_sarea_t *) dev_priv->sarea->handle;
-	int offset = (dev_priv->current_page == 1)
+	int offset = (dev_priv->sarea_priv->pfCurrentPage == 1)
 	    ? dev_priv->front_offset : dev_priv->back_offset;
 	RING_LOCALS;
-	DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
+	DRM_DEBUG("%s: pfCurrentPage=%d\n",
 		  __FUNCTION__,
-		  dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
+		  dev_priv->sarea_priv->pfCurrentPage);
 
 	/* Do some trivial performance monitoring...
 	 */
@@ -1449,8 +1449,8 @@ static void radeon_cp_dispatch_flip(drm_device_t * dev)
 	 * performing the swapbuffer ioctl.
 	 */
 	dev_priv->sarea_priv->last_frame++;
-	dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
-	    1 - dev_priv->current_page;
+	dev_priv->sarea_priv->pfCurrentPage =
+		1 - dev_priv->sarea_priv->pfCurrentPage;
 
 	BEGIN_RING(2);
 
@@ -2162,24 +2162,10 @@ static int radeon_do_init_pageflip(drm_device_t * dev)
 	ADVANCE_RING();
 
 	dev_priv->page_flipping = 1;
-	dev_priv->current_page = 0;
-	dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
 
-	return 0;
-}
-
-/* Called whenever a client dies, from drm_release.
- * NOTE:  Lock isn't necessarily held when this is called!
- */
-static int radeon_do_cleanup_pageflip(drm_device_t * dev)
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG("\n");
+	if (dev_priv->sarea_priv->pfCurrentPage != 1)
+		dev_priv->sarea_priv->pfCurrentPage = 0;
 
-	if (dev_priv->current_page != 0)
-		radeon_cp_dispatch_flip(dev);
-
-	dev_priv->page_flipping = 0;
 	return 0;
 }
 
@@ -3225,9 +3211,7 @@ void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp)
 {
 	if (dev->dev_private) {
 		drm_radeon_private_t *dev_priv = dev->dev_private;
-		if (dev_priv->page_flipping) {
-			radeon_do_cleanup_pageflip(dev);
-		}
+		dev_priv->page_flipping = 0;
 		radeon_mem_release(filp, dev_priv->gart_heap);
 		radeon_mem_release(filp, dev_priv->fb_heap);
 		radeon_surfaces_release(filp, dev_priv);
@@ -3236,6 +3220,14 @@ void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp)
 
 void radeon_driver_lastclose(drm_device_t * dev)
 {
+	if (dev->dev_private) {
+		drm_radeon_private_t *dev_priv = dev->dev_private;
+
+		if (dev_priv->sarea_priv &&
+		    dev_priv->sarea_priv->pfCurrentPage != 0)
+			radeon_cp_dispatch_flip(dev);
+	}
+
 	radeon_do_release(dev);
 }
 
-- 
cgit v1.2.3


From f06ad82ecdc2c84f913bb4d6d48132f27f02c3a9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel@tungstengraphics.com>
Date: Tue, 1 May 2007 17:03:55 +0200
Subject: Fix userspace ABI breakage from
 3c384a9ad5f964709a237cfe035ea5d6df2da5fa.

---
 shared-core/drm.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/drm.h b/shared-core/drm.h
index b7b2ac04..b4195419 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -788,9 +788,9 @@ typedef struct drm_fence_arg {
 
 typedef enum {
 	drm_bo_type_dc,
-	drm_bo_type_kernel, /* for initial kernel allocations */
 	drm_bo_type_user,
-	drm_bo_type_fake
+	drm_bo_type_fake,
+	drm_bo_type_kernel, /* for initial kernel allocations */
 }drm_bo_type_t;
 
 
-- 
cgit v1.2.3


From 87ec1fea6c1ac93b4ff02f8c06ed476c0081e2e5 Mon Sep 17 00:00:00 2001
From: Oliver McFadden <z3ro.geek@gmail.com>
Date: Sun, 6 May 2007 12:35:16 +0000
Subject: r300: Use the defined names for known registers.

---
 shared-core/r300_cmdbuf.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/r300_cmdbuf.c b/shared-core/r300_cmdbuf.c
index 667a829b..d3c52d43 100644
--- a/shared-core/r300_cmdbuf.c
+++ b/shared-core/r300_cmdbuf.c
@@ -148,15 +148,15 @@ void r300_init_reg_flags(void)
 
 	/* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */
 	ADD_RANGE(R300_SE_VPORT_XSCALE, 6);
-	ADD_RANGE(0x2080, 1);
+	ADD_RANGE(R300_VAP_CNTL, 1);
 	ADD_RANGE(R300_SE_VTE_CNTL, 2);
 	ADD_RANGE(0x2134, 2);
-	ADD_RANGE(0x2140, 1);
+	ADD_RANGE(R300_VAP_CNTL_STATUS, 1);
 	ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2);
 	ADD_RANGE(0x21DC, 1);
-	ADD_RANGE(0x221C, 1);
+	ADD_RANGE(R300_VAP_UNKNOWN_221C, 1);
 	ADD_RANGE(0x2220, 4);
-	ADD_RANGE(0x2288, 1);
+	ADD_RANGE(R300_VAP_UNKNOWN_2288, 1);
 	ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2);
 	ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
 	ADD_RANGE(R300_GB_ENABLE, 1);
@@ -168,13 +168,13 @@ void r300_init_reg_flags(void)
 	ADD_RANGE(R300_RE_POINTSIZE, 1);
 	ADD_RANGE(0x4230, 3);
 	ADD_RANGE(R300_RE_LINE_CNT, 1);
-	ADD_RANGE(0x4238, 1);
+	ADD_RANGE(R300_RE_UNK4238, 1);
 	ADD_RANGE(0x4260, 3);
-	ADD_RANGE(0x4274, 4);
-	ADD_RANGE(0x4288, 5);
-	ADD_RANGE(0x42A0, 1);
+	ADD_RANGE(R300_RE_SHADE, 4);
+	ADD_RANGE(R300_RE_POLYGON_MODE, 5);
+	ADD_RANGE(R300_RE_ZBIAS_CNTL, 1);
 	ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4);
-	ADD_RANGE(0x42B4, 1);
+	ADD_RANGE(R300_RE_OCCLUSION_CNTL, 1);
 	ADD_RANGE(R300_RE_CULL_CNTL, 1);
 	ADD_RANGE(0x42C0, 2);
 	ADD_RANGE(R300_RS_CNTL_0, 2);
@@ -190,22 +190,22 @@ void r300_init_reg_flags(void)
 	ADD_RANGE(R300_PFS_INSTR1_0, 64);
 	ADD_RANGE(R300_PFS_INSTR2_0, 64);
 	ADD_RANGE(R300_PFS_INSTR3_0, 64);
-	ADD_RANGE(0x4BC0, 1);
-	ADD_RANGE(0x4BC8, 3);
+	ADD_RANGE(R300_RE_FOG_STATE, 1);
+	ADD_RANGE(R300_FOG_COLOR_R, 3);
 	ADD_RANGE(R300_PP_ALPHA_TEST, 2);
 	ADD_RANGE(0x4BD8, 1);
 	ADD_RANGE(R300_PFS_PARAM_0_X, 64);
 	ADD_RANGE(0x4E00, 1);
 	ADD_RANGE(R300_RB3D_CBLEND, 2);
 	ADD_RANGE(R300_RB3D_COLORMASK, 1);
-	ADD_RANGE(0x4E10, 3);
+	ADD_RANGE(R300_RB3D_BLEND_COLOR, 3);
 	ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET);	/* check offset */
 	ADD_RANGE(R300_RB3D_COLORPITCH0, 1);
 	ADD_RANGE(0x4E50, 9);
 	ADD_RANGE(0x4E88, 1);
 	ADD_RANGE(0x4EA0, 2);
 	ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
-	ADD_RANGE(0x4F10, 4);
+	ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4);
 	ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET);	/* check offset */
 	ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
 	ADD_RANGE(0x4F28, 1);
-- 
cgit v1.2.3


From 4e858f8811d057a86740b27e0c9af933d382ed0d Mon Sep 17 00:00:00 2001
From: Oliver McFadden <z3ro.geek@gmail.com>
Date: Sun, 6 May 2007 12:47:03 +0000
Subject: r300: Synchronize the register file from Mesa.

---
 shared-core/r300_reg.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'shared-core')

diff --git a/shared-core/r300_reg.h b/shared-core/r300_reg.h
index 1f65f9a7..3754a5be 100644
--- a/shared-core/r300_reg.h
+++ b/shared-core/r300_reg.h
@@ -145,6 +145,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #	define R300_VC_NO_SWAP                  (0 << 0)
 #	define R300_VC_16BIT_SWAP               (1 << 0)
 #	define R300_VC_32BIT_SWAP               (2 << 0)
+#	define R300_VAP_TCL_BYPASS		(1 << 8)
 
 /* gap */
 
@@ -487,6 +488,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #	define R300_GB_W_SELECT_1		(1<<4)
 
 #define R300_GB_AA_CONFIG		0x4020
+#	define R300_AA_DISABLE			0x00
 #	define R300_AA_ENABLE			0x01
 #	define R300_AA_SUBSAMPLES_2		0
 #	define R300_AA_SUBSAMPLES_3		(1<<1)
-- 
cgit v1.2.3


From 59784116bf7d18cfbbb7236fbdd601476207b9dc Mon Sep 17 00:00:00 2001
From: Matthieu Castet <castet.matthieu@free.fr>
Date: Tue, 8 May 2007 21:18:02 +0200
Subject: nouveau : fix fifo context size for nv10

---
 shared-core/nouveau_drm.h  |  2 +-
 shared-core/nouveau_fifo.c | 14 ++++++++++----
 shared-core/nouveau_irq.c  |  1 +
 shared-core/nouveau_mem.c  |  2 ++
 4 files changed, 14 insertions(+), 5 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h
index 3ba7e961..1e7322e0 100644
--- a/shared-core/nouveau_drm.h
+++ b/shared-core/nouveau_drm.h
@@ -114,7 +114,7 @@ enum nouveau_card_type {
 	NV_10      =10,
 	NV_11      =10,
 	NV_15      =10,
-	NV_17      =10,
+	NV_17      =17,
 	NV_20      =20,
 	NV_25      =20,
 	NV_30      =30,
diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c
index 92166eeb..8e66ca2e 100644
--- a/shared-core/nouveau_fifo.c
+++ b/shared-core/nouveau_fifo.c
@@ -51,7 +51,7 @@ int nouveau_fifo_ctx_size(drm_device_t* dev)
 
 	if (dev_priv->card_type >= NV_40)
 		return 128;
-	else if (dev_priv->card_type >= NV_10)
+	else if (dev_priv->card_type >= NV_17)
 		return 64;
 	else
 		return 32;
@@ -90,10 +90,12 @@ static int nouveau_fifo_instmem_configure(drm_device_t *dev)
 			break;
 		case NV_30:
 		case NV_20:
-		case NV_10:
+		case NV_17:
 			NV_WRITE(NV03_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) |
 					(1 << 16) /* 64 Bytes entry*/);
+			/* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */
 			break;
+		case NV_10:
 		case NV_04:
 		case NV_03:
 			NV_WRITE(NV03_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
@@ -269,11 +271,12 @@ static void nouveau_nv10_context_init(drm_device_t *dev, int channel)
         drm_nouveau_private_t *dev_priv = dev->dev_private;
         struct nouveau_object *cb_obj;
         uint32_t fifoctx;
+        int ctx_size = nouveau_fifo_ctx_size(dev);
         int i;
         cb_obj  = dev_priv->fifos[channel].cmdbuf_obj;
-        fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64;
+        fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*ctx_size;
 
-        for (i=0;i<64;i+=4)
+        for (i=0;i<ctx_size;i+=4)
                 NV_WRITE(fifoctx + i, 0);
 
         /* Fill entries that are seen filled in dumps of nvidia driver just
@@ -327,6 +330,7 @@ static void nouveau_nv30_context_init(drm_device_t *dev, int channel)
         RAMFC_WR(SEMAPHORE,             NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
 }
 
+#if 0
 static void nouveau_nv10_context_save(drm_device_t *dev)
 {
 	drm_nouveau_private_t *dev_priv = dev->dev_private;
@@ -350,6 +354,7 @@ static void nouveau_nv10_context_save(drm_device_t *dev)
 	RAMFC_WR(SEMAPHORE        , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
 	RAMFC_WR(DMA_SUBROUTINE   , NV_READ(NV10_PFIFO_CACHE1_DMA_SUBROUTINE));
 }
+#endif
 #undef RAMFC_WR
 
 #define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV40_RAMFC_##offset, (val))
@@ -507,6 +512,7 @@ static int nouveau_fifo_alloc(drm_device_t* dev, int *chan_ret, DRMFILE filp)
 			nouveau_nv04_context_init(dev, channel);
 			break;
 		case NV_10:
+		case NV_17:
 			nv10_graph_context_create(dev, channel);
 			nouveau_nv10_context_init(dev, channel);
 			break;
diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c
index b7c1d532..8de6e705 100644
--- a/shared-core/nouveau_irq.c
+++ b/shared-core/nouveau_irq.c
@@ -372,6 +372,7 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev)
 				nouveau_nv04_context_switch(dev);
 				break;
 			case NV_10:
+			case NV_17:
 				nouveau_nv10_context_switch(dev);
 				break;
 			case NV_20:
diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c
index 541f1545..a5343b99 100644
--- a/shared-core/nouveau_mem.c
+++ b/shared-core/nouveau_mem.c
@@ -248,6 +248,7 @@ uint64_t nouveau_mem_fb_amount(struct drm_device *dev)
 			}
 			break;
 		case NV_10:
+		case NV_17:
 		case NV_20:
 		case NV_30:
 		case NV_40:
@@ -521,6 +522,7 @@ nouveau_instmem_configure_fixed_tables(struct drm_device *dev)
 			break;
 		case NV_30:
 		case NV_20:
+		case NV_17:
 		case NV_10:
 		case NV_04:
 		case NV_03:
-- 
cgit v1.2.3


From a02b04514250bff19aaf90d1f9699b4ec4749343 Mon Sep 17 00:00:00 2001
From: Oliver McFadden <z3ro.geek@gmail.com>
Date: Wed, 9 May 2007 15:22:09 +0000
Subject: r300: Synchronized R300 register defines file.

---
 shared-core/r300_reg.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core')

diff --git a/shared-core/r300_reg.h b/shared-core/r300_reg.h
index 3754a5be..8131478e 100644
--- a/shared-core/r300_reg.h
+++ b/shared-core/r300_reg.h
@@ -1555,6 +1555,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define R300_PRIM_COLOR_ORDER_BGRA              (0 << 6)
 #define R300_PRIM_COLOR_ORDER_RGBA              (1 << 6)
 #define R300_PRIM_NUM_VERTICES_SHIFT            16
+#define R300_PRIM_NUM_VERTICES_MASK             0xffff
 
 /* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
  * Two parameter dwords:
-- 
cgit v1.2.3


From e0056c7eb4640fc4863a352997ba00e3142b3355 Mon Sep 17 00:00:00 2001
From: Oliver McFadden <z3ro.geek@gmail.com>
Date: Wed, 9 May 2007 18:31:31 +0000
Subject: r300: Synchronized R300 register defines file.

---
 shared-core/r300_reg.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'shared-core')

diff --git a/shared-core/r300_reg.h b/shared-core/r300_reg.h
index 8131478e..e309a48c 100644
--- a/shared-core/r300_reg.h
+++ b/shared-core/r300_reg.h
@@ -26,6 +26,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #ifndef _R300_REG_H
 #define _R300_REG_H
 
+/* *INDENT-OFF* */
+
 #define R300_MC_INIT_MISC_LAT_TIMER	0x180
 #	define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT	0
 #	define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT	4
@@ -1604,5 +1606,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 #define R300_CP_CMD_BITBLT_MULTI	0xC0009B00
 
+/* *INDENT-ON* */
 
 #endif /* _R300_REG_H */
-- 
cgit v1.2.3


From e4d163d81ad7ce46af43cf84485dc96c4cb22b1f Mon Sep 17 00:00:00 2001
From: Keith Packard <keithp@neko.keithp.com>
Date: Mon, 7 May 2007 09:07:48 -0400
Subject: Allow vblank interrupts to remain disabled across VT switch.

i915_driver_irq_postinstall was forcing vblank interrupts to pipe A when
called with vblank interrupts disabled. This caused vblank interrupts to be
accidentally re-enabled when VT switching the X server. Instead, start the
driver with vblank interrupts enabled on pipe A to support older X servers,
but then leave control over the state to the X server if it is able to do so.
---
 shared-core/i915_dma.c | 4 ++++
 shared-core/i915_irq.c | 5 -----
 2 files changed, 4 insertions(+), 5 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index cb5dcea8..8991a3ce 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -177,6 +177,10 @@ static int i915_initialize(drm_device_t * dev,
 	 */
 	dev_priv->allow_batchbuffer = 1;
 
+	/* Enable vblank on pipe A for older X servers
+	 */
+    	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
+
 	/* Program Hardware Status Page */
 	dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 
 	    0xffffffff);
diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c
index 8748b647..e3335458 100644
--- a/shared-core/i915_irq.c
+++ b/shared-core/i915_irq.c
@@ -726,9 +726,6 @@ void i915_driver_irq_postinstall(drm_device_t * dev)
 	INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
 	dev_priv->swaps_pending = 0;
 
-	if (!dev_priv->vblank_pipe)
-		dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
-
 	dev_priv->swaps_lock = SPIN_LOCK_UNLOCKED;
 	INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
 	dev_priv->swaps_pending = 0;
@@ -736,8 +733,6 @@ void i915_driver_irq_postinstall(drm_device_t * dev)
 	dev_priv->user_irq_lock = SPIN_LOCK_UNLOCKED;
 	dev_priv->user_irq_refcount = 0;
 
-	if (!dev_priv->vblank_pipe)
-		dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
 	i915_enable_interrupt(dev);
 	DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
 
-- 
cgit v1.2.3


From 5d623935c0e4f5f283c961de186b78b30db12463 Mon Sep 17 00:00:00 2001
From: Matthieu Castet <castet.matthieu@free.fr>
Date: Sat, 12 May 2007 15:16:37 +0200
Subject: nouveau : nv10 graph clipping values were forgoten in ddx to drm
 commit

---
 shared-core/nv10_graph.c | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'shared-core')

diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c
index 4cc44e21..80d07bd9 100644
--- a/shared-core/nv10_graph.c
+++ b/shared-core/nv10_graph.c
@@ -692,6 +692,11 @@ int nv10_graph_init(drm_device_t *dev) {
 	NV_WRITE(NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 	NV_WRITE(NV04_PGRAPH_FIFO       , 0x00000001);
 
+	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
+	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
+	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
+	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
+
 	return 0;
 }
 
-- 
cgit v1.2.3


From e9b604ed3fd6b4e056920bd327646b3e0e9b3be8 Mon Sep 17 00:00:00 2001
From: Matthieu Castet <castet.matthieu@free.fr>
Date: Sat, 12 May 2007 15:35:39 +0200
Subject: nouveau : nv10 graph move clipping value to per channel init

---
 shared-core/nv10_graph.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c
index 80d07bd9..fb189709 100644
--- a/shared-core/nv10_graph.c
+++ b/shared-core/nv10_graph.c
@@ -640,6 +640,10 @@ int nv10_graph_context_create(drm_device_t *dev, int channel) {
 	NV_WRITE_CTX(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
 	NV_WRITE_CTX(NV04_PGRAPH_BETA_AND     , 0xFFFFFFFF);
 
+	NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
+	NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
+	NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
+	NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
 
 	NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff);
 	/* is it really needed ??? */
@@ -692,11 +696,6 @@ int nv10_graph_init(drm_device_t *dev) {
 	NV_WRITE(NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 	NV_WRITE(NV04_PGRAPH_FIFO       , 0x00000001);
 
-	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
-	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
-	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
-	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
-
 	return 0;
 }
 
-- 
cgit v1.2.3


From c6ff0caaa3e8f61f7c19950913b1ce731f979ce3 Mon Sep 17 00:00:00 2001
From: Oliver McFadden <z3ro.geek@gmail.com>
Date: Sun, 13 May 2007 07:53:40 +0000
Subject: r300: Synchronized R300 register defines file.

Just moved the indent control comments so that indent doesn't try to change
anything.
---
 shared-core/r300_reg.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/r300_reg.h b/shared-core/r300_reg.h
index e309a48c..8ff362b9 100644
--- a/shared-core/r300_reg.h
+++ b/shared-core/r300_reg.h
@@ -23,11 +23,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 **************************************************************************/
 
+/* *INDENT-OFF* */
+
 #ifndef _R300_REG_H
 #define _R300_REG_H
 
-/* *INDENT-OFF* */
-
 #define R300_MC_INIT_MISC_LAT_TIMER	0x180
 #	define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT	0
 #	define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT	4
@@ -1606,6 +1606,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 #define R300_CP_CMD_BITBLT_MULTI	0xC0009B00
 
-/* *INDENT-ON* */
-
 #endif /* _R300_REG_H */
+
+/* *INDENT-ON* */
-- 
cgit v1.2.3


From ca725bba8472d5d94bcb7414b510d7d3027cbb1c Mon Sep 17 00:00:00 2001
From: Oliver McFadden <z3ro.geek@gmail.com>
Date: Sun, 13 May 2007 16:18:54 +0000
Subject: r300: Added my comments into r300_reg.h.

---
 shared-core/r300_reg.h | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'shared-core')

diff --git a/shared-core/r300_reg.h b/shared-core/r300_reg.h
index 8ff362b9..0a31f0b9 100644
--- a/shared-core/r300_reg.h
+++ b/shared-core/r300_reg.h
@@ -673,6 +673,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 /* Special handling for color: When the fragment program uses color,
  * the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the
  * color register index.
+ *
+ * Apperently you may set the R300_RS_ROUTE_0_COLOR bit, but not provide any
+ * R300_RS_ROUTE_0_COLOR_DEST value; this setup is used for clearing the state.
+ * See r300_ioctl.c:r300EmitClearState. I'm not sure if this setup is strictly
+ * correct or not. - Oliver.
  */
 #       define R300_RS_ROUTE_0_COLOR             (1 << 14)
 #       define R300_RS_ROUTE_0_COLOR_DEST_SHIFT  17
-- 
cgit v1.2.3


From 7b48f0022a24bc5f565ae64b450dda77dee616c1 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Sat, 26 May 2007 04:26:24 +1000
Subject: drm: cleanup use of Linux list handling macros

This makes the drms use of the list handling macros a lot cleaner
and more along the lines of how they should be used.
---
 shared-core/mga_dma.c      | 2 +-
 shared-core/via_verifier.c | 4 +---
 2 files changed, 2 insertions(+), 4 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/mga_dma.c b/shared-core/mga_dma.c
index 78448282..d48313c7 100644
--- a/shared-core/mga_dma.c
+++ b/shared-core/mga_dma.c
@@ -551,7 +551,7 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
 		drm_map_list_t *_entry;
 		unsigned long agp_token = 0;
 
-		list_for_each_entry(_entry, &dev->maplist->head, head) {
+		list_for_each_entry(_entry, &dev->maplist, head) {
 			if (_entry->map == dev->agp_buffer_map)
 				agp_token = _entry->user_token;
 		}
diff --git a/shared-core/via_verifier.c b/shared-core/via_verifier.c
index b5a1d33a..4b844af0 100644
--- a/shared-core/via_verifier.c
+++ b/shared-core/via_verifier.c
@@ -255,7 +255,6 @@ static __inline__ drm_local_map_t *via_drm_lookup_agp_map(drm_via_state_t * seq,
 							  drm_device_t * dev)
 {
 #ifdef __linux__
-	struct list_head *list;
 	drm_map_list_t *r_list;
 #endif
 	drm_local_map_t *map = seq->map_cache;
@@ -265,8 +264,7 @@ static __inline__ drm_local_map_t *via_drm_lookup_agp_map(drm_via_state_t * seq,
 		return map;
 	}
 #ifdef __linux__
-	list_for_each(list, &dev->maplist->head) {
-		r_list = (drm_map_list_t *) list;
+	list_for_each_entry(r_list, &dev->maplist, head) {
 		map = r_list->map;
 		if (!map)
 			continue;
-- 
cgit v1.2.3


From 3fdef0dc2000308b16907b95f637c60acde80a74 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Sun, 6 May 2007 11:17:30 +1000
Subject: drm/ttm: cleanup mm_ioctl ioctls to be separate ioctls.

This is the first bunch of ioctls
---
 shared-core/drm.h | 54 +++++++++++++++++++++++++++++++++++-------------------
 1 file changed, 35 insertions(+), 19 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/drm.h b/shared-core/drm.h
index b4195419..d561a082 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -862,24 +862,14 @@ typedef struct drm_bo_arg{
 
 #define DRM_BO_MEM_TYPES 8 /* For now. */
 
-typedef union drm_mm_init_arg{
-	struct {
-		enum {
-			mm_init,
-			mm_takedown,
-			mm_query,
-			mm_lock,
-			mm_unlock
-		} op;
-		drm_u64_t p_offset;
-		drm_u64_t p_size;
-		unsigned mem_type;
-		unsigned expand_pad[8]; /*Future expansion */
-	} req;
-	struct {
-		drm_handle_t mm_sarea;
-		unsigned expand_pad[8]; /*Future expansion */
-	} rep;
+typedef struct drm_mm_type_arg {
+	unsigned int mem_type;
+} drm_mm_type_arg_t; 
+
+typedef struct drm_mm_init_arg {
+	drm_u64_t p_offset;
+	drm_u64_t p_size;
+	unsigned int mem_type;
 } drm_mm_init_arg_t;
 
 /**
@@ -949,10 +939,36 @@ typedef union drm_mm_init_arg{
 
 #define DRM_IOCTL_FENCE                 DRM_IOWR(0x3b, drm_fence_arg_t)
 #define DRM_IOCTL_BUFOBJ                DRM_IOWR(0x3d, drm_bo_arg_t)
-#define DRM_IOCTL_MM_INIT               DRM_IOWR(0x3e, drm_mm_init_arg_t)
 
 #define DRM_IOCTL_UPDATE_DRAW           DRM_IOW(0x3f, drm_update_draw_t)
 
+#define DRM_IOCTL_MM_INIT               DRM_IOWR(0xc0, drm_mm_init_arg_t)
+#define DRM_IOCTL_MM_TAKEDOWN           DRM_IOWR(0xc1, drm_mm_type_arg_t)
+#define DRM_IOCTL_MM_LOCK               DRM_IOWR(0xc2, drm_mm_type_arg_t)
+#define DRM_IOCTL_MM_UNLOCK             DRM_IOWR(0xc3, drm_mm_type_arg_t)
+
+#define DRM_IOCTL_FENCE_CREATE          DRM_IOWR(0xc4, drm_fence_arg_t)
+#define DRM_IOCTL_FENCE_DESTROY         DRM_IOWR(0xc5, drm_fence_arg_t)
+#define DRM_IOCTL_FENCE_REFERENCE       DRM_IOWR(0xc6, drm_fence_arg_t)
+#define DRM_IOCTL_FENCE_UNREFERENCE     DRM_IOWR(0xc7, drm_fence_arg_t)
+#define DRM_IOCTL_FENCE_SIGNALED        DRM_IOWR(0xc8, drm_fence_arg_t)
+#define DRM_IOCTL_FENCE_FLUSH           DRM_IOWR(0xc9, drm_fence_arg_t)
+#define DRM_IOCTL_FENCE_WAIT            DRM_IOWR(0xca, drm_fence_arg_t)
+#define DRM_IOCTL_FENCE_BUFFERS         DRM_IOWR(0xcb, drm_fence_arg_t)
+
+#define DRM_IOCTL_BO_CREATE             DRM_IOWR(0xcc, drm_bo_arg_t)
+#define DRM_IOCTL_BO_DESTROY            DRM_IOWR(0xcd, drm_bo_arg_t)
+#define DRM_IOCTL_BO_MAP                DRM_IOWR(0xce, drm_bo_arg_t)
+#define DRM_IOCTL_BO_UNMAP              DRM_IOWR(0xcf, drm_bo_arg_t)
+#define DRM_IOCTL_BO_REFERENCE          DRM_IOWR(0xd0, drm_bo_arg_t)
+#define DRM_IOCTL_BO_UNREFERENCE        DRM_IOWR(0xd1, drm_bo_arg_t)
+#define DRM_IOCTL_BO_VALIDATE           DRM_IOWR(0xd2, drm_bo_arg_t)
+#define DRM_IOCTL_BO_FENCE              DRM_IOWR(0xd3, drm_bo_arg_t)
+#define DRM_IOCTL_BO_INFO               DRM_IOWR(0xd4, drm_bo_arg_t)
+#define DRM_IOCTL_BO_WAIT_IDLE          DRM_IOWR(0xd5, drm_bo_arg_t)
+#define DRM_IOCTL_BO_REF_FENCE          DRM_IOWR(0xd6, drm_bo_arg_t)
+
+
 /*@}*/
 
 /**
-- 
cgit v1.2.3


From 3dfc1400e9fc58c69292d7cf7c2e1653fa5e6991 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Sun, 6 May 2007 11:35:11 +1000
Subject: drm/ttm: cleanup most of fence ioctl split out

---
 shared-core/drm.h | 38 ++++++++++++++------------------------
 1 file changed, 14 insertions(+), 24 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/drm.h b/shared-core/drm.h
index d561a082..9810321e 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -677,17 +677,6 @@ typedef struct drm_fence_arg {
 	unsigned flags;
 	unsigned signaled;
 	unsigned expand_pad[4]; /*Future expansion */
-	enum {
-		drm_fence_create,
-		drm_fence_destroy,
-		drm_fence_reference,
-		drm_fence_unreference,
-		drm_fence_signaled,
-		drm_fence_flush,
-		drm_fence_wait,
-		drm_fence_emit,
-		drm_fence_buffers
-	} op;
 } drm_fence_arg_t;
 
 /* Buffer permissions, referring to how the GPU uses the buffers.
@@ -954,19 +943,20 @@ typedef struct drm_mm_init_arg {
 #define DRM_IOCTL_FENCE_SIGNALED        DRM_IOWR(0xc8, drm_fence_arg_t)
 #define DRM_IOCTL_FENCE_FLUSH           DRM_IOWR(0xc9, drm_fence_arg_t)
 #define DRM_IOCTL_FENCE_WAIT            DRM_IOWR(0xca, drm_fence_arg_t)
-#define DRM_IOCTL_FENCE_BUFFERS         DRM_IOWR(0xcb, drm_fence_arg_t)
-
-#define DRM_IOCTL_BO_CREATE             DRM_IOWR(0xcc, drm_bo_arg_t)
-#define DRM_IOCTL_BO_DESTROY            DRM_IOWR(0xcd, drm_bo_arg_t)
-#define DRM_IOCTL_BO_MAP                DRM_IOWR(0xce, drm_bo_arg_t)
-#define DRM_IOCTL_BO_UNMAP              DRM_IOWR(0xcf, drm_bo_arg_t)
-#define DRM_IOCTL_BO_REFERENCE          DRM_IOWR(0xd0, drm_bo_arg_t)
-#define DRM_IOCTL_BO_UNREFERENCE        DRM_IOWR(0xd1, drm_bo_arg_t)
-#define DRM_IOCTL_BO_VALIDATE           DRM_IOWR(0xd2, drm_bo_arg_t)
-#define DRM_IOCTL_BO_FENCE              DRM_IOWR(0xd3, drm_bo_arg_t)
-#define DRM_IOCTL_BO_INFO               DRM_IOWR(0xd4, drm_bo_arg_t)
-#define DRM_IOCTL_BO_WAIT_IDLE          DRM_IOWR(0xd5, drm_bo_arg_t)
-#define DRM_IOCTL_BO_REF_FENCE          DRM_IOWR(0xd6, drm_bo_arg_t)
+#define DRM_IOCTL_FENCE_EMIT            DRM_IOWR(0xcb, drm_fence_arg_t)
+#define DRM_IOCTL_FENCE_BUFFERS         DRM_IOWR(0xcc, drm_fence_arg_t)
+
+#define DRM_IOCTL_BO_CREATE             DRM_IOWR(0xcd, drm_bo_arg_t)
+#define DRM_IOCTL_BO_DESTROY            DRM_IOWR(0xce, drm_bo_arg_t)
+#define DRM_IOCTL_BO_MAP                DRM_IOWR(0xcf, drm_bo_arg_t)
+#define DRM_IOCTL_BO_UNMAP              DRM_IOWR(0xd0, drm_bo_arg_t)
+#define DRM_IOCTL_BO_REFERENCE          DRM_IOWR(0xd1, drm_bo_arg_t)
+#define DRM_IOCTL_BO_UNREFERENCE        DRM_IOWR(0xd2, drm_bo_arg_t)
+#define DRM_IOCTL_BO_VALIDATE           DRM_IOWR(0xd3, drm_bo_arg_t)
+#define DRM_IOCTL_BO_FENCE              DRM_IOWR(0xd4, drm_bo_arg_t)
+#define DRM_IOCTL_BO_INFO               DRM_IOWR(0xd5, drm_bo_arg_t)
+#define DRM_IOCTL_BO_WAIT_IDLE          DRM_IOWR(0xd6, drm_bo_arg_t)
+#define DRM_IOCTL_BO_REF_FENCE          DRM_IOWR(0xd7, drm_bo_arg_t)
 
 
 /*@}*/
-- 
cgit v1.2.3


From ce58e53a01e61818210ebf65623e35a3af20167b Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Tue, 8 May 2007 15:43:29 +1000
Subject: whitespace fixups from kernel

---
 shared-core/radeon_cp.c |  3 +--
 shared-core/via_dma.c   | 49 +++++++++++++++++++++----------------------------
 2 files changed, 22 insertions(+), 30 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index bde98b30..023ae933 100644
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -1391,8 +1391,7 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
 	DRM_DEBUG("\n");
 
 	/* if we require new memory map but we don't have it fail */
-	if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap)
-	{
+	if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
 		DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
 		radeon_do_cleanup_cp(dev);
 		return DRM_ERR(EINVAL);
diff --git a/shared-core/via_dma.c b/shared-core/via_dma.c
index c73634e4..333c4bcf 100644
--- a/shared-core/via_dma.c
+++ b/shared-core/via_dma.c
@@ -84,9 +84,9 @@ static uint32_t via_cmdbuf_lag(drm_via_private_t *dev_priv)
 {
 	uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 	uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
-	
-	return ((hw_addr <= dev_priv->dma_low) ? 
-		(dev_priv->dma_low - hw_addr) : 
+
+	return ((hw_addr <= dev_priv->dma_low) ?
+		(dev_priv->dma_low - hw_addr) :
 		(dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));
 }
 
@@ -103,7 +103,7 @@ via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
 	uint32_t count;
 	hw_addr_ptr = dev_priv->hw_addr_ptr;
 	cur_addr = dev_priv->dma_low;
-	next_addr = cur_addr + size + 512*1024;
+	next_addr = cur_addr + size + 512 * 1024;
 	count = 1000000;
 	do {
 		hw_addr = *hw_addr_ptr - agp_base;
@@ -207,8 +207,8 @@ static int via_initialize(drm_device_t * dev,
 	dev_priv->dma_offset = init->offset;
 	dev_priv->last_pause_ptr = NULL;
 	dev_priv->hw_addr_ptr =
-	    (volatile uint32_t *)((char *)dev_priv->mmio->handle +
-	    init->reg_pause_addr);
+		(volatile uint32_t *)((char *)dev_priv->mmio->handle +
+		init->reg_pause_addr);
 
 	via_cmdbuf_start(dev_priv);
 
@@ -239,8 +239,8 @@ static int via_dma_init(DRM_IOCTL_ARGS)
 			retcode = via_dma_cleanup(dev);
 		break;
 	case VIA_DMA_INITIALIZED:
-		retcode = (dev_priv->ring.virtual_start != NULL) ? 
-			0: DRM_ERR( EFAULT );
+		retcode = (dev_priv->ring.virtual_start != NULL) ?
+			0 : DRM_ERR(EFAULT);
 		break;
 	default:
 		retcode = DRM_ERR(EINVAL);
@@ -268,8 +268,7 @@ static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd)
 
 	if (cmd->size > VIA_PCI_BUF_SIZE) {
 		return DRM_ERR(ENOMEM);
-	} 
-
+	}
 
 	if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
 		return DRM_ERR(EFAULT);
@@ -292,7 +291,7 @@ static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd)
 	}
 
 	memcpy(vb, dev_priv->pci_buf, cmd->size);
-	
+
 	dev_priv->dma_low += cmd->size;
 
 	/*
@@ -301,7 +300,7 @@ static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd)
 	 */
 
 	if (cmd->size < 0x100)
-	  via_pad_cache(dev_priv,(0x100 - cmd->size) >> 3);
+		via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3);
 	via_cmdbuf_pause(dev_priv);
 
 	return 0;
@@ -321,7 +320,7 @@ static int via_flush_ioctl(DRM_IOCTL_ARGS)
 {
 	DRM_DEVICE;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
 	return via_driver_dma_quiescent(dev);
 }
@@ -332,7 +331,7 @@ static int via_cmdbuffer(DRM_IOCTL_ARGS)
 	drm_via_cmdbuffer_t cmdbuf;
 	int ret;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
 	DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
 				 sizeof(cmdbuf));
@@ -355,16 +354,16 @@ static int via_dispatch_pci_cmdbuffer(drm_device_t * dev,
 
 	if (cmd->size > VIA_PCI_BUF_SIZE) {
 		return DRM_ERR(ENOMEM);
-	} 
+	}
 	if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
 		return DRM_ERR(EFAULT);
-	
-	if ((ret = 
-	     via_verify_command_stream((uint32_t *)dev_priv->pci_buf,
+
+	if ((ret =
+	     via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
 				       cmd->size, dev, 0))) {
 		return ret;
 	}
-	
+
 	ret =
 	    via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf,
 				     cmd->size);
@@ -377,7 +376,7 @@ static int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
 	drm_via_cmdbuffer_t cmdbuf;
 	int ret;
 
-	LOCK_TEST_WITH_RETURN( dev, filp );
+	LOCK_TEST_WITH_RETURN(dev, filp);
 
 	DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
 				 sizeof(cmdbuf));
@@ -393,7 +392,6 @@ static int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
 	return 0;
 }
 
-
 static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
 					 uint32_t * vb, int qw_count)
 {
@@ -403,7 +401,6 @@ static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
 	return vb;
 }
 
-
 /*
  * This function is used internally by ring buffer mangement code.
  *
@@ -419,8 +416,7 @@ static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)
  * modifying the pause address stored in the buffer itself. If
  * the regulator has already paused, restart it.
  */
-
-static int via_hook_segment(drm_via_private_t *dev_priv,
+static int via_hook_segment(drm_via_private_t * dev_priv,
 			    uint32_t pause_addr_hi, uint32_t pause_addr_lo,
 			    int no_pci_fire)
 {
@@ -479,7 +475,7 @@ static int via_wait_idle(drm_via_private_t * dev_priv)
 }
 
 static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type,
-			       uint32_t addr, uint32_t *cmd_addr_hi, 
+			       uint32_t addr, uint32_t *cmd_addr_hi,
 			       uint32_t *cmd_addr_lo, int skip_wait)
 {
 	uint32_t agp_base;
@@ -508,9 +504,6 @@ static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type,
 	return vb;
 }
 
-
-
-
 static void via_cmdbuf_start(drm_via_private_t * dev_priv)
 {
 	uint32_t pause_addr_lo, pause_addr_hi;
-- 
cgit v1.2.3


From 375f3f2884cd1437e9ec2608647face0c3cbef3a Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Sat, 26 May 2007 03:47:48 +1000
Subject: Revert "drm/ttm: cleanup most of fence ioctl split out"

This reverts commit 3dfc1400e9fc58c69292d7cf7c2e1653fa5e6991.

this shouldn't have gone on master yet
---
 shared-core/drm.h | 38 ++++++++++++++++++++++++--------------
 1 file changed, 24 insertions(+), 14 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/drm.h b/shared-core/drm.h
index 9810321e..d561a082 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -677,6 +677,17 @@ typedef struct drm_fence_arg {
 	unsigned flags;
 	unsigned signaled;
 	unsigned expand_pad[4]; /*Future expansion */
+	enum {
+		drm_fence_create,
+		drm_fence_destroy,
+		drm_fence_reference,
+		drm_fence_unreference,
+		drm_fence_signaled,
+		drm_fence_flush,
+		drm_fence_wait,
+		drm_fence_emit,
+		drm_fence_buffers
+	} op;
 } drm_fence_arg_t;
 
 /* Buffer permissions, referring to how the GPU uses the buffers.
@@ -943,20 +954,19 @@ typedef struct drm_mm_init_arg {
 #define DRM_IOCTL_FENCE_SIGNALED        DRM_IOWR(0xc8, drm_fence_arg_t)
 #define DRM_IOCTL_FENCE_FLUSH           DRM_IOWR(0xc9, drm_fence_arg_t)
 #define DRM_IOCTL_FENCE_WAIT            DRM_IOWR(0xca, drm_fence_arg_t)
-#define DRM_IOCTL_FENCE_EMIT            DRM_IOWR(0xcb, drm_fence_arg_t)
-#define DRM_IOCTL_FENCE_BUFFERS         DRM_IOWR(0xcc, drm_fence_arg_t)
-
-#define DRM_IOCTL_BO_CREATE             DRM_IOWR(0xcd, drm_bo_arg_t)
-#define DRM_IOCTL_BO_DESTROY            DRM_IOWR(0xce, drm_bo_arg_t)
-#define DRM_IOCTL_BO_MAP                DRM_IOWR(0xcf, drm_bo_arg_t)
-#define DRM_IOCTL_BO_UNMAP              DRM_IOWR(0xd0, drm_bo_arg_t)
-#define DRM_IOCTL_BO_REFERENCE          DRM_IOWR(0xd1, drm_bo_arg_t)
-#define DRM_IOCTL_BO_UNREFERENCE        DRM_IOWR(0xd2, drm_bo_arg_t)
-#define DRM_IOCTL_BO_VALIDATE           DRM_IOWR(0xd3, drm_bo_arg_t)
-#define DRM_IOCTL_BO_FENCE              DRM_IOWR(0xd4, drm_bo_arg_t)
-#define DRM_IOCTL_BO_INFO               DRM_IOWR(0xd5, drm_bo_arg_t)
-#define DRM_IOCTL_BO_WAIT_IDLE          DRM_IOWR(0xd6, drm_bo_arg_t)
-#define DRM_IOCTL_BO_REF_FENCE          DRM_IOWR(0xd7, drm_bo_arg_t)
+#define DRM_IOCTL_FENCE_BUFFERS         DRM_IOWR(0xcb, drm_fence_arg_t)
+
+#define DRM_IOCTL_BO_CREATE             DRM_IOWR(0xcc, drm_bo_arg_t)
+#define DRM_IOCTL_BO_DESTROY            DRM_IOWR(0xcd, drm_bo_arg_t)
+#define DRM_IOCTL_BO_MAP                DRM_IOWR(0xce, drm_bo_arg_t)
+#define DRM_IOCTL_BO_UNMAP              DRM_IOWR(0xcf, drm_bo_arg_t)
+#define DRM_IOCTL_BO_REFERENCE          DRM_IOWR(0xd0, drm_bo_arg_t)
+#define DRM_IOCTL_BO_UNREFERENCE        DRM_IOWR(0xd1, drm_bo_arg_t)
+#define DRM_IOCTL_BO_VALIDATE           DRM_IOWR(0xd2, drm_bo_arg_t)
+#define DRM_IOCTL_BO_FENCE              DRM_IOWR(0xd3, drm_bo_arg_t)
+#define DRM_IOCTL_BO_INFO               DRM_IOWR(0xd4, drm_bo_arg_t)
+#define DRM_IOCTL_BO_WAIT_IDLE          DRM_IOWR(0xd5, drm_bo_arg_t)
+#define DRM_IOCTL_BO_REF_FENCE          DRM_IOWR(0xd6, drm_bo_arg_t)
 
 
 /*@}*/
-- 
cgit v1.2.3


From 58b2ed78329305d5760c6df55175f958477f89ae Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Sat, 26 May 2007 03:48:08 +1000
Subject: Revert "drm/ttm: cleanup mm_ioctl ioctls to be separate ioctls."

This reverts commit 3fdef0dc2000308b16907b95f637c60acde80a74.

ditto not on master yet
---
 shared-core/drm.h | 54 +++++++++++++++++++-----------------------------------
 1 file changed, 19 insertions(+), 35 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/drm.h b/shared-core/drm.h
index d561a082..b4195419 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -862,14 +862,24 @@ typedef struct drm_bo_arg{
 
 #define DRM_BO_MEM_TYPES 8 /* For now. */
 
-typedef struct drm_mm_type_arg {
-	unsigned int mem_type;
-} drm_mm_type_arg_t; 
-
-typedef struct drm_mm_init_arg {
-	drm_u64_t p_offset;
-	drm_u64_t p_size;
-	unsigned int mem_type;
+typedef union drm_mm_init_arg{
+	struct {
+		enum {
+			mm_init,
+			mm_takedown,
+			mm_query,
+			mm_lock,
+			mm_unlock
+		} op;
+		drm_u64_t p_offset;
+		drm_u64_t p_size;
+		unsigned mem_type;
+		unsigned expand_pad[8]; /*Future expansion */
+	} req;
+	struct {
+		drm_handle_t mm_sarea;
+		unsigned expand_pad[8]; /*Future expansion */
+	} rep;
 } drm_mm_init_arg_t;
 
 /**
@@ -939,36 +949,10 @@ typedef struct drm_mm_init_arg {
 
 #define DRM_IOCTL_FENCE                 DRM_IOWR(0x3b, drm_fence_arg_t)
 #define DRM_IOCTL_BUFOBJ                DRM_IOWR(0x3d, drm_bo_arg_t)
+#define DRM_IOCTL_MM_INIT               DRM_IOWR(0x3e, drm_mm_init_arg_t)
 
 #define DRM_IOCTL_UPDATE_DRAW           DRM_IOW(0x3f, drm_update_draw_t)
 
-#define DRM_IOCTL_MM_INIT               DRM_IOWR(0xc0, drm_mm_init_arg_t)
-#define DRM_IOCTL_MM_TAKEDOWN           DRM_IOWR(0xc1, drm_mm_type_arg_t)
-#define DRM_IOCTL_MM_LOCK               DRM_IOWR(0xc2, drm_mm_type_arg_t)
-#define DRM_IOCTL_MM_UNLOCK             DRM_IOWR(0xc3, drm_mm_type_arg_t)
-
-#define DRM_IOCTL_FENCE_CREATE          DRM_IOWR(0xc4, drm_fence_arg_t)
-#define DRM_IOCTL_FENCE_DESTROY         DRM_IOWR(0xc5, drm_fence_arg_t)
-#define DRM_IOCTL_FENCE_REFERENCE       DRM_IOWR(0xc6, drm_fence_arg_t)
-#define DRM_IOCTL_FENCE_UNREFERENCE     DRM_IOWR(0xc7, drm_fence_arg_t)
-#define DRM_IOCTL_FENCE_SIGNALED        DRM_IOWR(0xc8, drm_fence_arg_t)
-#define DRM_IOCTL_FENCE_FLUSH           DRM_IOWR(0xc9, drm_fence_arg_t)
-#define DRM_IOCTL_FENCE_WAIT            DRM_IOWR(0xca, drm_fence_arg_t)
-#define DRM_IOCTL_FENCE_BUFFERS         DRM_IOWR(0xcb, drm_fence_arg_t)
-
-#define DRM_IOCTL_BO_CREATE             DRM_IOWR(0xcc, drm_bo_arg_t)
-#define DRM_IOCTL_BO_DESTROY            DRM_IOWR(0xcd, drm_bo_arg_t)
-#define DRM_IOCTL_BO_MAP                DRM_IOWR(0xce, drm_bo_arg_t)
-#define DRM_IOCTL_BO_UNMAP              DRM_IOWR(0xcf, drm_bo_arg_t)
-#define DRM_IOCTL_BO_REFERENCE          DRM_IOWR(0xd0, drm_bo_arg_t)
-#define DRM_IOCTL_BO_UNREFERENCE        DRM_IOWR(0xd1, drm_bo_arg_t)
-#define DRM_IOCTL_BO_VALIDATE           DRM_IOWR(0xd2, drm_bo_arg_t)
-#define DRM_IOCTL_BO_FENCE              DRM_IOWR(0xd3, drm_bo_arg_t)
-#define DRM_IOCTL_BO_INFO               DRM_IOWR(0xd4, drm_bo_arg_t)
-#define DRM_IOCTL_BO_WAIT_IDLE          DRM_IOWR(0xd5, drm_bo_arg_t)
-#define DRM_IOCTL_BO_REF_FENCE          DRM_IOWR(0xd6, drm_bo_arg_t)
-
-
 /*@}*/
 
 /**
-- 
cgit v1.2.3


From ad02c536dfaeaeb7ad025dfcfcb1a2a99aa5ad7e Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Sat, 26 May 2007 04:02:55 +1000
Subject: radeon: add other IGP chipsets

---
 shared-core/drm_pciids.txt | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'shared-core')

diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt
index ad67dda2..6ae3596f 100644
--- a/shared-core/drm_pciids.txt
+++ b/shared-core/drm_pciids.txt
@@ -98,13 +98,20 @@
 0x1002 0x5653 CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon Mobility X700 M26"
 0x1002 0x5834 CHIP_RS300|RADEON_IS_IGP "ATI Radeon RS300 9100 IGP"
 0x1002 0x5835 CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY "ATI Radeon RS300 Mobility IGP"
+0x1002 0x5954 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI RS480 XPRESS 200G"
 0x1002 0x5955 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon XPRESS 200M 5955"
+0x1002 0x5974 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RS482 XPRESS 200"
+0x1002 0x5975 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RS485 XPRESS 1100 IGP"
 0x1002 0x5960 CHIP_RV280 "ATI Radeon RV280 9250"
 0x1002 0x5961 CHIP_RV280 "ATI Radeon RV280 9200"
 0x1002 0x5962 CHIP_RV280 "ATI Radeon RV280 9200"
 0x1002 0x5964 CHIP_RV280 "ATI Radeon RV280 9200 SE"
 0x1002 0x5965 CHIP_RV280 "ATI FireMV 2200 PCI"
 0x1002 0x5969 CHIP_RV100 "ATI ES1000 RN50"
+0x1002 0x5a41 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RS400 XPRESS 200"
+0x1002 0x5a42 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RS400 XPRESS 200M"
+0x1002 0x5a61 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RC410 XPRESS 200"
+0x1002 0x5a62 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RC410 XPRESS 200M"
 0x1002 0x5b60 CHIP_RV380|RADEON_NEW_MEMMAP "ATI Radeon RV370 X300 SE"
 0x1002 0x5b62 CHIP_RV380|RADEON_NEW_MEMMAP "ATI Radeon RV370 X600 Pro"
 0x1002 0x5b63 CHIP_RV380|RADEON_NEW_MEMMAP "ATI Radeon RV370 X550"
-- 
cgit v1.2.3


From 2bb7703698bef1f599295126ca3834d37a8596c0 Mon Sep 17 00:00:00 2001
From: Thomas Gleixner <tglx@linutronix.de>
Date: Sat, 26 May 2007 05:20:59 +1000
Subject: drm: spinlock initializer cleanup

---
 shared-core/i915_irq.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c
index e3335458..7955a2e8 100644
--- a/shared-core/i915_irq.c
+++ b/shared-core/i915_irq.c
@@ -722,11 +722,7 @@ void i915_driver_irq_postinstall(drm_device_t * dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
-	dev_priv->swaps_lock = SPIN_LOCK_UNLOCKED;
-	INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
-	dev_priv->swaps_pending = 0;
-
-	dev_priv->swaps_lock = SPIN_LOCK_UNLOCKED;
+	spin_lock_init(&dev_priv->swaps_lock);
 	INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
 	dev_priv->swaps_pending = 0;
 
-- 
cgit v1.2.3


From b0c8d885ce645aee5027a75e4149ba4be265b55d Mon Sep 17 00:00:00 2001
From: Jung-uk Kim <jkim@FreeBSD.org>
Date: Tue, 15 May 2007 13:35:33 -0700
Subject: Update a bunch of FreeBSD port code.

Tested on r200/r300.  i915 updates still remain to be done.
---
 shared-core/i915_dma.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index 8991a3ce..5ea0bdab 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -471,7 +471,9 @@ int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush)
 static int i915_dispatch_cmdbuffer(drm_device_t * dev,
 				   drm_i915_cmdbuffer_t * cmd)
 {
+#ifdef I915_HAVE_FENCE
 	drm_i915_private_t *dev_priv = dev->dev_private;
+#endif
 	int nbox = cmd->num_cliprects;
 	int i = 0, count, ret;
 
@@ -856,7 +858,7 @@ static int i915_mmio(DRM_IOCTL_ARGS)
 		return DRM_ERR(EINVAL);
 
 	e = &mmio_table[mmio.reg];
-	base = dev_priv->mmio_map->handle + e->offset;
+	base = (u8 *) dev_priv->mmio_map->handle + e->offset;
 
         switch (mmio.read_write) {
 		case I915_MMIO_READ:
-- 
cgit v1.2.3


From 3917f85c73c32105b59f5185a89fe136ed6962a1 Mon Sep 17 00:00:00 2001
From: Wang Zhenyu <zhenyu.z.wang@intel.com>
Date: Wed, 30 May 2007 16:24:42 +0800
Subject: i915: Add support for 965GME/GLE chip.

---
 shared-core/drm_pciids.txt | 1 +
 shared-core/i915_dma.c     | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

(limited to 'shared-core')

diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt
index 6ae3596f..5fbc7a68 100644
--- a/shared-core/drm_pciids.txt
+++ b/shared-core/drm_pciids.txt
@@ -287,6 +287,7 @@
 0x8086 0x2992 CHIP_I9XX|CHIP_I965 "Intel i965Q"
 0x8086 0x29A2 CHIP_I9XX|CHIP_I965 "Intel i965G"
 0x8086 0x2A02 CHIP_I9XX|CHIP_I965 "Intel i965GM"
+0x8086 0x2A12 CHIP_I9XX|CHIP_I965 "Intel i965GME/GLE"
 
 [imagine]
 0x105d 0x2309 IMAGINE_128 "Imagine 128"
diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index 5ea0bdab..c6a80f1c 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -35,7 +35,8 @@
 			dev->pci_device == 0x2982 || \
 			dev->pci_device == 0x2992 || \
 			dev->pci_device == 0x29A2 || \
-			dev->pci_device == 0x2A02)
+			dev->pci_device == 0x2A02 || \
+			dev->pci_device == 0x2A12)
 
 
 /* Really want an OS-independent resettable timer.  Would like to have
-- 
cgit v1.2.3


From 5c394b309de4325daae67fc766a0640b39658a64 Mon Sep 17 00:00:00 2001
From: Wang Zhenyu <zhenyu.z.wang@intel.com>
Date: Wed, 30 May 2007 16:25:49 +0800
Subject: i915: Add support for 945GME chip

---
 shared-core/drm_pciids.txt | 1 +
 1 file changed, 1 insertion(+)

(limited to 'shared-core')

diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt
index 5fbc7a68..4b07e4f6 100644
--- a/shared-core/drm_pciids.txt
+++ b/shared-core/drm_pciids.txt
@@ -282,6 +282,7 @@
 0x8086 0x2592 CHIP_I9XX|CHIP_I915 "Intel i915GM"
 0x8086 0x2772 CHIP_I9XX|CHIP_I915 "Intel i945G"
 0x8086 0x27A2 CHIP_I9XX|CHIP_I915 "Intel i945GM"
+0x8086 0x27AE CHIP_I9XX|CHIP_I915 "Intel i945GME"
 0x8086 0x2972 CHIP_I9XX|CHIP_I965 "Intel i946GZ"
 0x8086 0x2982 CHIP_I9XX|CHIP_I965 "Intel i965G"
 0x8086 0x2992 CHIP_I9XX|CHIP_I965 "Intel i965Q"
-- 
cgit v1.2.3


From 4e9d215bdfe72588cbacdb17ab9b60a42a43aefb Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Sun, 3 Jun 2007 16:28:21 +1000
Subject: radeon: add support for vblank on crtc2

This add support for CRTC2 vblank on radeon similiar to the i915 support
---
 shared-core/radeon_cp.c    |  4 +++
 shared-core/radeon_drm.h   |  5 ++-
 shared-core/radeon_drv.h   | 13 ++++++-
 shared-core/radeon_irq.c   | 87 +++++++++++++++++++++++++++++++++++++++++-----
 shared-core/radeon_state.c |  6 ++++
 5 files changed, 104 insertions(+), 11 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index 023ae933..e9c635d7 100644
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -1423,6 +1423,10 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
 		return DRM_ERR(EINVAL);
 	}
 
+	/* Enable vblank on CRTC1 for older X servers
+	 */
+	dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
+
 	switch(init->func) {
 	case RADEON_INIT_R200_CP:
 		dev_priv->microcode_version = UCODE_R200;
diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h
index e96e7851..6a57b804 100644
--- a/shared-core/radeon_drm.h
+++ b/shared-core/radeon_drm.h
@@ -655,6 +655,7 @@ typedef struct drm_radeon_indirect {
 #define RADEON_PARAM_GART_TEX_HANDLE       10
 #define RADEON_PARAM_SCRATCH_OFFSET        11
 #define RADEON_PARAM_CARD_TYPE             12
+#define RADEON_PARAM_VBLANK_CRTC           13   /* VBLANK CRTC */
 
 typedef struct drm_radeon_getparam {
 	int param;
@@ -709,7 +710,7 @@ typedef struct drm_radeon_setparam {
 
 #define RADEON_SETPARAM_NEW_MEMMAP 4		/* Use new memory map */
 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5    /* PCI GART Table Size */
-
+#define RADEON_SETPARAM_VBLANK_CRTC 6           /* VBLANK CRTC */
 /* 1.14: Clients can allocate/free a surface
  */
 typedef struct drm_radeon_surface_alloc {
@@ -722,5 +723,7 @@ typedef struct drm_radeon_surface_free {
 	unsigned int address;
 } drm_radeon_surface_free_t;
 
+#define	DRM_RADEON_VBLANK_CRTC1 	1
+#define	DRM_RADEON_VBLANK_CRTC2 	2
 
 #endif
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 4a36ea70..f1d9ca9e 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -97,10 +97,11 @@
  *       new packet type)
  * 1.26- Add support for variable size PCI(E) gart aperture
  * 1.27- Add support for IGP GART
+ * 1.28- Add support for VBL on CRTC2
  */
 
 #define DRIVER_MAJOR		1
-#define DRIVER_MINOR		27
+#define DRIVER_MINOR		28
 #define DRIVER_PATCHLEVEL	0
 
 /*
@@ -279,6 +280,9 @@ typedef struct drm_radeon_private {
 	/* SW interrupt */
 	wait_queue_head_t swi_queue;
 	atomic_t swi_emitted;
+	int vblank_crtc;
+	uint32_t irq_enable_reg;
+	int irq_enabled;
 
 	struct radeon_surface surfaces[RADEON_MAX_SURFACES];
 	struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
@@ -355,10 +359,14 @@ extern int radeon_irq_wait(DRM_IOCTL_ARGS);
 extern void radeon_do_release(drm_device_t * dev);
 extern int radeon_driver_vblank_wait(drm_device_t * dev,
 				     unsigned int *sequence);
+extern int radeon_driver_vblank_wait2(drm_device_t * dev,
+				      unsigned int *sequence);
 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
 extern void radeon_driver_irq_preinstall(drm_device_t * dev);
 extern void radeon_driver_irq_postinstall(drm_device_t * dev);
 extern void radeon_driver_irq_uninstall(drm_device_t * dev);
+extern int radeon_vblank_crtc_get(drm_device_t *dev);
+extern int radeon_vblank_crtc_set(drm_device_t *dev, int64_t value);
 
 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
 extern int radeon_driver_unload(struct drm_device *dev);
@@ -495,12 +503,15 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp,
 
 #define RADEON_GEN_INT_CNTL		0x0040
 #	define RADEON_CRTC_VBLANK_MASK		(1 << 0)
+#	define RADEON_CRTC2_VBLANK_MASK		(1 << 9)
 #	define RADEON_GUI_IDLE_INT_ENABLE	(1 << 19)
 #	define RADEON_SW_INT_ENABLE		(1 << 25)
 
 #define RADEON_GEN_INT_STATUS		0x0044
 #	define RADEON_CRTC_VBLANK_STAT		(1 << 0)
 #	define RADEON_CRTC_VBLANK_STAT_ACK   	(1 << 0)
+#	define RADEON_CRTC2_VBLANK_STAT		(1 << 9)
+#	define RADEON_CRTC2_VBLANK_STAT_ACK   	(1 << 9)
 #	define RADEON_GUI_IDLE_INT_TEST_ACK     (1 << 19)
 #	define RADEON_SW_INT_TEST		(1 << 25)
 #	define RADEON_SW_INT_TEST_ACK   	(1 << 25)
diff --git a/shared-core/radeon_irq.c b/shared-core/radeon_irq.c
index 3ff0baa2..41e3bde3 100644
--- a/shared-core/radeon_irq.c
+++ b/shared-core/radeon_irq.c
@@ -72,8 +72,7 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
 	/* Only consider the bits we're interested in - others could be used
 	 * outside the DRM
 	 */
-	stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
-						  RADEON_CRTC_VBLANK_STAT));
+	stat = radeon_acknowledge_irqs(dev_priv, dev_priv->irq_enable_reg);
 	if (!stat)
 		return IRQ_NONE;
 
@@ -83,8 +82,22 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
 	}
 
 	/* VBLANK interrupt */
-	if (stat & RADEON_CRTC_VBLANK_STAT) {
-		atomic_inc(&dev->vbl_received);
+	if (stat & (RADEON_CRTC_VBLANK_STAT|RADEON_CRTC2_VBLANK_STAT)) {
+		int vblank_crtc = dev_priv->vblank_crtc;
+
+		if ((vblank_crtc &
+		     (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) ==
+		    (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
+			if (stat & RADEON_CRTC_VBLANK_STAT)
+				atomic_inc(&dev->vbl_received);
+			if (stat & RADEON_CRTC2_VBLANK_STAT)
+				atomic_inc(&dev->vbl_received2);
+		} else if (((stat & RADEON_CRTC_VBLANK_STAT) &&
+			   (vblank_crtc & DRM_RADEON_VBLANK_CRTC1)) ||
+			   ((stat & RADEON_CRTC2_VBLANK_STAT) &&
+			    (vblank_crtc & DRM_RADEON_VBLANK_CRTC2)))
+			atomic_inc(&dev->vbl_received);
+
 		DRM_WAKEUP(&dev->vbl_queue);
 		drm_vbl_send_signals(dev);
 	}
@@ -127,7 +140,8 @@ static int radeon_wait_irq(drm_device_t * dev, int swi_nr)
 	return ret;
 }
 
-int radeon_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
+int radeon_driver_vblank_do_wait(drm_device_t * dev, unsigned int *sequence,
+				 atomic_t *counter)
 {
 	drm_radeon_private_t *dev_priv =
 	    (drm_radeon_private_t *) dev->dev_private;
@@ -148,7 +162,7 @@ int radeon_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
 	 * using vertical blanks...
 	 */
 	DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
-		    (((cur_vblank = atomic_read(&dev->vbl_received))
+		    (((cur_vblank = atomic_read(counter))
 		      - *sequence) <= (1 << 23)));
 
 	*sequence = cur_vblank;
@@ -156,6 +170,16 @@ int radeon_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
 	return ret;
 }
 
+int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
+{
+	return radeon_driver_vblank_do_wait(dev, sequence, &dev->vbl_received);
+}
+
+int radeon_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence)
+{
+	return radeon_driver_vblank_do_wait(dev, sequence, &dev->vbl_received2);
+}
+
 /* Needs the lock as it touches the ring.
  */
 int radeon_irq_emit(DRM_IOCTL_ARGS)
@@ -204,6 +228,21 @@ int radeon_irq_wait(DRM_IOCTL_ARGS)
 	return radeon_wait_irq(dev, irqwait.irq_seq);
 }
 
+static void radeon_enable_interrupt(drm_device_t *dev)
+{
+	drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
+
+	dev_priv->irq_enable_reg = RADEON_SW_INT_ENABLE;
+	if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC1)
+		dev_priv->irq_enable_reg |= RADEON_CRTC_VBLANK_MASK;
+
+	if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC2)
+		dev_priv->irq_enable_reg |= RADEON_CRTC2_VBLANK_MASK;
+
+	RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
+	dev_priv->irq_enabled = 1;
+}
+
 /* drm_dma.h hooks
 */
 void radeon_driver_irq_preinstall(drm_device_t * dev)
@@ -227,9 +266,7 @@ void radeon_driver_irq_postinstall(drm_device_t * dev)
 	atomic_set(&dev_priv->swi_emitted, 0);
 	DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
 
-	/* Turn on SW and VBL ints */
-	RADEON_WRITE(RADEON_GEN_INT_CNTL,
-		     RADEON_CRTC_VBLANK_MASK | RADEON_SW_INT_ENABLE);
+	radeon_enable_interrupt(dev);
 }
 
 void radeon_driver_irq_uninstall(drm_device_t * dev)
@@ -239,6 +276,38 @@ void radeon_driver_irq_uninstall(drm_device_t * dev)
 	if (!dev_priv)
 		return;
 
+	dev_priv->irq_enabled = 0;
+
 	/* Disable *all* interrupts */
 	RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 }
+
+
+int radeon_vblank_crtc_get(drm_device_t *dev)
+{
+	drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
+	u32 flag;
+	u32 value;
+
+	flag = RADEON_READ(RADEON_GEN_INT_CNTL);
+	value = 0;
+
+	if (flag & RADEON_CRTC_VBLANK_MASK)
+		value |= DRM_RADEON_VBLANK_CRTC1;
+
+	if (flag & RADEON_CRTC2_VBLANK_MASK)
+		value |= DRM_RADEON_VBLANK_CRTC2;
+	return value;
+}
+
+int radeon_vblank_crtc_set(drm_device_t *dev, int64_t value)
+{
+	drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
+	if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
+		DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
+		return DRM_ERR(EINVAL);
+	}
+	dev_priv->vblank_crtc = (unsigned int)value;
+	radeon_enable_interrupt(dev);
+	return 0;
+}
diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c
index bad054d7..8ccd0981 100644
--- a/shared-core/radeon_state.c
+++ b/shared-core/radeon_state.c
@@ -3131,6 +3131,9 @@ static int radeon_cp_getparam(DRM_IOCTL_ARGS)
 		else
 			value = RADEON_CARD_PCI;
 		break;
+	case RADEON_PARAM_VBLANK_CRTC:
+		value = radeon_vblank_crtc_get(dev);
+		break;
 	default:
 		DRM_DEBUG( "Invalid parameter %d\n", param.param );
 		return DRM_ERR(EINVAL);
@@ -3192,6 +3195,9 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS)
 		if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE)
 			dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
 		break;
+	case RADEON_SETPARAM_VBLANK_CRTC:
+		return radeon_vblank_crtc_set(dev, sp.value);
+		break;
 	default:
 		DRM_DEBUG("Invalid parameter %d\n", sp.param);
 		return DRM_ERR(EINVAL);
-- 
cgit v1.2.3


From 8d95f4bd91fcc46b3e59767cb86b6c99bc8679c3 Mon Sep 17 00:00:00 2001
From: root <airlied@linux.ie>
Date: Sun, 3 Jun 2007 18:11:44 +1000
Subject: Revert "move i915 to new drm_wait_on function"

This reverts commit feb68037784ac09e333a321d294fdb2d8c57a4c8.

This was a bad idea, the macro is actually a bit harder to convert
to a static for the other use cases
---
 shared-core/i915_irq.c | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c
index 7955a2e8..dc00f983 100644
--- a/shared-core/i915_irq.c
+++ b/shared-core/i915_irq.c
@@ -381,13 +381,6 @@ void i915_user_irq_off(drm_i915_private_t *dev_priv)
 	spin_unlock(&dev_priv->user_irq_lock);
 }
 		
-static int wait_compare(struct drm_device *dev, void *priv)
-{
-	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-	int irq_nr = (u64)priv;
-
-	return (READ_BREADCRUMB(dev_priv) >= irq_nr);
-}
 
 static int i915_wait_irq(drm_device_t * dev, int irq_nr)
 {
@@ -403,8 +396,8 @@ static int i915_wait_irq(drm_device_t * dev, int irq_nr)
 	dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 	
 	i915_user_irq_on(dev_priv);
-	ret = drm_wait_on(dev, &dev_priv->irq_queue, 3 * DRM_HZ, wait_compare,
-			  (void *)(u64)irq_nr);
+	DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
+		    READ_BREADCRUMB(dev_priv) >= irq_nr);
 	i915_user_irq_off(dev_priv);
 
 	if (ret == DRM_ERR(EBUSY)) {
-- 
cgit v1.2.3


From a05d4fecd3307aa2f2f27531e7ff0b1985ef5c56 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Sun, 3 Jun 2007 18:30:52 +1000
Subject: radeon: refine irq acking for vbl on crtc 2

---
 shared-core/radeon_irq.c | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

(limited to 'shared-core')

diff --git a/shared-core/radeon_irq.c b/shared-core/radeon_irq.c
index 41e3bde3..5151b4d6 100644
--- a/shared-core/radeon_irq.c
+++ b/shared-core/radeon_irq.c
@@ -141,19 +141,29 @@ static int radeon_wait_irq(drm_device_t * dev, int swi_nr)
 }
 
 int radeon_driver_vblank_do_wait(drm_device_t * dev, unsigned int *sequence,
-				 atomic_t *counter)
+				 int crtc)
 {
 	drm_radeon_private_t *dev_priv =
 	    (drm_radeon_private_t *) dev->dev_private;
 	unsigned int cur_vblank;
 	int ret = 0;
-
+	int ack = 0;
+	atomic_t *counter;
 	if (!dev_priv) {
 		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 		return DRM_ERR(EINVAL);
 	}
 
-	radeon_acknowledge_irqs(dev_priv, RADEON_CRTC_VBLANK_STAT);
+	if (crtc == DRM_RADEON_VBLANK_CRTC1) {
+		counter = &dev->vbl_received;
+		ack |= RADEON_CRTC_VBLANK_STAT;
+	} else if (crtc == DRM_RADEON_VBLANK_CRTC2) {
+		counter = &dev->vbl_received2;
+		ack |= RADEON_CRTC2_VBLANK_STAT;
+	} else
+		return DRM_ERR(EINVAL);
+
+	radeon_acknowledge_irqs(dev_priv, ack);
 
 	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 
@@ -172,12 +182,12 @@ int radeon_driver_vblank_do_wait(drm_device_t * dev, unsigned int *sequence,
 
 int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
 {
-	return radeon_driver_vblank_do_wait(dev, sequence, &dev->vbl_received);
+	return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC1);
 }
 
 int radeon_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence)
 {
-	return radeon_driver_vblank_do_wait(dev, sequence, &dev->vbl_received2);
+	return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC2);
 }
 
 /* Needs the lock as it touches the ring.
-- 
cgit v1.2.3


From 4327d7f3142cdbf3f3f94426ae33e2d30b5a40c8 Mon Sep 17 00:00:00 2001
From: Maurice van der Pot <griffon26@kfk4ever.com>
Date: Mon, 4 Jun 2007 10:49:30 +1000
Subject: nouveau: fix RAMHT wrapping

---
 shared-core/nouveau_object.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'shared-core')

diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c
index ace7c2aa..e36568c6 100644
--- a/shared-core/nouveau_object.c
+++ b/shared-core/nouveau_object.c
@@ -167,7 +167,7 @@ nouveau_ht_object_insert(drm_device_t* dev, int channel, uint32_t handle,
 
 	while (NV_READ(ht_base + ofs) || NV_READ(ht_base + ofs + 4)) {
 		ofs += 8;
-		if (ofs == ht_end) ofs = ht_base;
+		if (ofs == dev_priv->ramht_size) ofs = 0;
 		if (ofs == o_ofs) {
 			DRM_ERROR("no free hash table entries\n");
 			return 1;
-- 
cgit v1.2.3