From 0d6b7fcb79e9bf6f823b5802f8317056015faeec Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 1 Feb 2005 11:08:31 +0000 Subject: cleanup patch from Adrian Bunk --- shared-core/radeon_state.c | 95 +++++++++++++++++++++++----------------------- 1 file changed, 47 insertions(+), 48 deletions(-) (limited to 'shared-core/radeon_state.c') diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c index 11d4000a..2ce44933 100644 --- a/shared-core/radeon_state.c +++ b/shared-core/radeon_state.c @@ -33,39 +33,6 @@ #include "radeon_drm.h" #include "radeon_drv.h" -drm_ioctl_desc_t radeon_ioctls[] = { - [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = {radeon_cp_init, 1, 1}, - [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = {radeon_cp_start, 1, 1}, - [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = {radeon_cp_stop, 1, 1}, - [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = {radeon_cp_reset, 1, 1}, - [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = {radeon_cp_idle, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = {radeon_cp_resume, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_RESET)] = {radeon_engine_reset, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = {radeon_fullscreen, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = {radeon_cp_swap, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = {radeon_cp_clear, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = {radeon_cp_vertex, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = {radeon_cp_indices, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = {radeon_cp_texture, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = {radeon_cp_stipple, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = {radeon_cp_indirect, 1, 1}, - [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = {radeon_cp_vertex2, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = {radeon_cp_cmdbuf, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = {radeon_cp_getparam, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = {radeon_cp_flip, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = {radeon_mem_alloc, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_FREE)] = {radeon_mem_free, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = {radeon_mem_init_heap, 1, 1}, - [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = {radeon_irq_emit, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = {radeon_irq_wait, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = {radeon_cp_setparam, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = {radeon_surface_alloc, 1, 0}, - [DRM_IOCTL_NR(DRM_RADEON_SURF_FREE)] = {radeon_surface_free, 1, 0} -}; - -int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); - - /* ================================================================ * Helper functions for client state checking and fixup */ @@ -1870,7 +1837,7 @@ static void radeon_surfaces_release(DRMFILE filp, drm_radeon_private_t *dev_priv * IOCTL functions */ -int radeon_surface_alloc(DRM_IOCTL_ARGS) +static int radeon_surface_alloc(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1890,7 +1857,7 @@ int radeon_surface_alloc(DRM_IOCTL_ARGS) return 0; } -int radeon_surface_free(DRM_IOCTL_ARGS) +static int radeon_surface_free(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1910,7 +1877,7 @@ int radeon_surface_free(DRM_IOCTL_ARGS) return 0; } -int radeon_cp_clear(DRM_IOCTL_ARGS) +static int radeon_cp_clear(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1968,7 +1935,7 @@ static int radeon_do_init_pageflip(drm_device_t * dev) /* Called whenever a client dies, from drm_release. * NOTE: Lock isn't necessarily held when this is called! */ -int radeon_do_cleanup_pageflip(drm_device_t * dev) +static int radeon_do_cleanup_pageflip(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; DRM_DEBUG("\n"); @@ -1983,7 +1950,7 @@ int radeon_do_cleanup_pageflip(drm_device_t * dev) /* Swapping and flipping are different operations, need different ioctls. * They can & should be intermixed to support multiple 3d windows. */ -int radeon_cp_flip(DRM_IOCTL_ARGS) +static int radeon_cp_flip(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2002,7 +1969,7 @@ int radeon_cp_flip(DRM_IOCTL_ARGS) return 0; } -int radeon_cp_swap(DRM_IOCTL_ARGS) +static int radeon_cp_swap(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2023,7 +1990,7 @@ int radeon_cp_swap(DRM_IOCTL_ARGS) return 0; } -int radeon_cp_vertex(DRM_IOCTL_ARGS) +static int radeon_cp_vertex(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2111,7 +2078,7 @@ int radeon_cp_vertex(DRM_IOCTL_ARGS) return 0; } -int radeon_cp_indices(DRM_IOCTL_ARGS) +static int radeon_cp_indices(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2210,7 +2177,7 @@ int radeon_cp_indices(DRM_IOCTL_ARGS) return 0; } -int radeon_cp_texture(DRM_IOCTL_ARGS) +static int radeon_cp_texture(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2242,7 +2209,7 @@ int radeon_cp_texture(DRM_IOCTL_ARGS) return ret; } -int radeon_cp_stipple(DRM_IOCTL_ARGS) +static int radeon_cp_stipple(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2265,7 +2232,7 @@ int radeon_cp_stipple(DRM_IOCTL_ARGS) return 0; } -int radeon_cp_indirect(DRM_IOCTL_ARGS) +static int radeon_cp_indirect(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2339,7 +2306,7 @@ int radeon_cp_indirect(DRM_IOCTL_ARGS) return 0; } -int radeon_cp_vertex2(DRM_IOCTL_ARGS) +static int radeon_cp_vertex2(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2665,7 +2632,7 @@ static int radeon_emit_wait(drm_device_t * dev, int flags) return 0; } -int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) +static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2803,7 +2770,7 @@ int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) return 0; } -int radeon_cp_getparam(DRM_IOCTL_ARGS) +static int radeon_cp_getparam(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2877,7 +2844,7 @@ int radeon_cp_getparam(DRM_IOCTL_ARGS) return 0; } -int radeon_cp_setparam(DRM_IOCTL_ARGS) +static int radeon_cp_setparam(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2976,3 +2943,35 @@ void radeon_driver_free_filp_priv(drm_device_t * dev, drm_file_t * filp_priv) drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); } + +drm_ioctl_desc_t radeon_ioctls[] = { + [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = {radeon_cp_init, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = {radeon_cp_start, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = {radeon_cp_stop, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = {radeon_cp_reset, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = {radeon_cp_idle, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = {radeon_cp_resume, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_RESET)] = {radeon_engine_reset, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = {radeon_fullscreen, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = {radeon_cp_swap, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = {radeon_cp_clear, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = {radeon_cp_vertex, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = {radeon_cp_indices, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = {radeon_cp_texture, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = {radeon_cp_stipple, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = {radeon_cp_indirect, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = {radeon_cp_vertex2, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = {radeon_cp_cmdbuf, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = {radeon_cp_getparam, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = {radeon_cp_flip, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = {radeon_mem_alloc, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_FREE)] = {radeon_mem_free, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = {radeon_mem_init_heap, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = {radeon_irq_emit, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = {radeon_irq_wait, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = {radeon_cp_setparam, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = {radeon_surface_alloc, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_SURF_FREE)] = {radeon_surface_free, 1, 0} +}; + +int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); -- cgit v1.2.3