From 34797ff67c16beb9c331920f663bdf8387c14c78 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sun, 2 Dec 2007 23:48:45 +0100 Subject: radeon_ms: radeon modesetting first commit. This should work on all radeon but there is still many things todo: - add crtc2 - tmds - lvds - add bios data table so we don't need to hardcode dac/crtc infos - separate clock control to make power saving easier & cleaner - tiling (warning tiling shouldn't be enable in double scan or interlace) - surface reg manager (this goes along with tiling) - suspend/resume hook - avivo & r500 family support - atom bios support (for posting card mostly) - finish superioctl skeleton - what else ? :) --- shared-core/radeon_ms_drm.h | 60 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 shared-core/radeon_ms_drm.h (limited to 'shared-core/radeon_ms_drm.h') diff --git a/shared-core/radeon_ms_drm.h b/shared-core/radeon_ms_drm.h new file mode 100644 index 00000000..842d5331 --- /dev/null +++ b/shared-core/radeon_ms_drm.h @@ -0,0 +1,60 @@ +/* + * Copyright 2007 Jérôme Glisse + * Copyright 2007 Dave Airlie + * Copyright 2007 Alex Deucher + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Authors: + * Jérôme Glisse + */ +#ifndef __RADEON_MS_DRM_H__ +#define __RADEON_MS_DRM_H__ + +/* fence definitions */ +/* The only fence class we support */ +#define DRM_RADEON_FENCE_CLASS_ACCEL 0 +/* Fence type that guarantees read-write flush */ +#define DRM_RADEON_FENCE_TYPE_RW 2 +/* cache flushes programmed just before the fence */ +#define DRM_RADEON_FENCE_FLAG_FLUSHED 0x01000000 + +/* radeon ms ioctl */ +#define DRM_RADEON_EXECBUFFER 0x00 + +struct drm_radeon_execbuffer_arg { + uint64_t next; + uint32_t reloc_offset; + union { + struct drm_bo_op_req req; + struct drm_bo_arg_rep rep; + } d; +}; + +struct drm_radeon_execbuffer { + uint32_t args_count; + uint64_t args; + uint32_t cmd_size; + struct drm_fence_arg fence_arg; +}; + +#endif -- cgit v1.2.3 From d8c94a84b7f8da5fdf32a0799eaac72a1fc3007d Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 19 Dec 2007 18:27:38 +0100 Subject: radeon_ms: add sarea & install header --- shared-core/radeon_ms_drm.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'shared-core/radeon_ms_drm.h') diff --git a/shared-core/radeon_ms_drm.h b/shared-core/radeon_ms_drm.h index 842d5331..7186030c 100644 --- a/shared-core/radeon_ms_drm.h +++ b/shared-core/radeon_ms_drm.h @@ -57,4 +57,12 @@ struct drm_radeon_execbuffer { struct drm_fence_arg fence_arg; }; +#define RADEON_MS_MAX_SAREA_CLIPRECTS 16 + +struct drm_radeon_ms_sarea { + /* the cliprects */ + struct drm_clip_rect boxes[RADEON_MS_MAX_SAREA_CLIPRECTS]; + unsigned int nbox; +}; + #endif -- cgit v1.2.3 From 10937cf20b6814e4cf68114fab4619fad94eafcb Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 4 Jan 2008 16:12:24 +1100 Subject: drm: move drm_head to drm_minor and fix up users --- shared-core/radeon_ms_drm.h | 8 -------- 1 file changed, 8 deletions(-) (limited to 'shared-core/radeon_ms_drm.h') diff --git a/shared-core/radeon_ms_drm.h b/shared-core/radeon_ms_drm.h index 7186030c..842d5331 100644 --- a/shared-core/radeon_ms_drm.h +++ b/shared-core/radeon_ms_drm.h @@ -57,12 +57,4 @@ struct drm_radeon_execbuffer { struct drm_fence_arg fence_arg; }; -#define RADEON_MS_MAX_SAREA_CLIPRECTS 16 - -struct drm_radeon_ms_sarea { - /* the cliprects */ - struct drm_clip_rect boxes[RADEON_MS_MAX_SAREA_CLIPRECTS]; - unsigned int nbox; -}; - #endif -- cgit v1.2.3 From a7dc4d08b9b4f8fe6fcaa4c778f6dd3718d1e36a Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Mon, 10 Mar 2008 23:35:07 +0100 Subject: rradeon_ms: rework fence code and bring radeon ms up to date --- shared-core/radeon_ms_drm.h | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) (limited to 'shared-core/radeon_ms_drm.h') diff --git a/shared-core/radeon_ms_drm.h b/shared-core/radeon_ms_drm.h index 842d5331..39c050ad 100644 --- a/shared-core/radeon_ms_drm.h +++ b/shared-core/radeon_ms_drm.h @@ -30,16 +30,23 @@ #ifndef __RADEON_MS_DRM_H__ #define __RADEON_MS_DRM_H__ -/* fence definitions */ -/* The only fence class we support */ -#define DRM_RADEON_FENCE_CLASS_ACCEL 0 -/* Fence type that guarantees read-write flush */ -#define DRM_RADEON_FENCE_TYPE_RW 2 -/* cache flushes programmed just before the fence */ -#define DRM_RADEON_FENCE_FLAG_FLUSHED 0x01000000 +/* Fence + * We have only one fence class as we submit command through th + * same fifo so there is no need to synchronize buffer btw different + * cmd stream. + * + * Set DRM_RADEON_FENCE_FLAG_FLUSHED if you want a flush with + * emission of the fence + * + * For fence type we have the native DRM EXE type and the radeon RW + * type. + */ +#define DRM_RADEON_FENCE_CLASS_ACCEL 0 +#define DRM_RADEON_FENCE_TYPE_RW 2 +#define DRM_RADEON_FENCE_FLAG_FLUSHED 0x01000000 /* radeon ms ioctl */ -#define DRM_RADEON_EXECBUFFER 0x00 +#define DRM_RADEON_EXECBUFFER 0x00 struct drm_radeon_execbuffer_arg { uint64_t next; -- cgit v1.2.3 From 2d9eccfd056425e4ebdf1a7b879979fd0a9d1340 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sun, 30 Mar 2008 12:45:57 +0200 Subject: radeon_ms: add hang debuging helper functions --- shared-core/radeon_ms_drm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'shared-core/radeon_ms_drm.h') diff --git a/shared-core/radeon_ms_drm.h b/shared-core/radeon_ms_drm.h index 39c050ad..e1b4c18c 100644 --- a/shared-core/radeon_ms_drm.h +++ b/shared-core/radeon_ms_drm.h @@ -47,6 +47,7 @@ /* radeon ms ioctl */ #define DRM_RADEON_EXECBUFFER 0x00 +#define DRM_RADEON_RESETCP 0x01 struct drm_radeon_execbuffer_arg { uint64_t next; -- cgit v1.2.3 From 5891b0bd2ae441d738e78737a4c4826bd2e60b43 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sat, 12 Apr 2008 00:15:12 +0200 Subject: radeon_ms: rework command submission ioctl & cleanup --- shared-core/radeon_ms_drm.h | 64 +++++++++++++++++++++++++++------------------ 1 file changed, 38 insertions(+), 26 deletions(-) (limited to 'shared-core/radeon_ms_drm.h') diff --git a/shared-core/radeon_ms_drm.h b/shared-core/radeon_ms_drm.h index e1b4c18c..d7fe6fab 100644 --- a/shared-core/radeon_ms_drm.h +++ b/shared-core/radeon_ms_drm.h @@ -27,42 +27,54 @@ * Authors: * Jérôme Glisse */ -#ifndef __RADEON_MS_DRM_H__ -#define __RADEON_MS_DRM_H__ +#ifndef __AMD_DRM_H__ +#define __AMD_DRM_H__ /* Fence - * We have only one fence class as we submit command through th - * same fifo so there is no need to synchronize buffer btw different - * cmd stream. * - * Set DRM_RADEON_FENCE_FLAG_FLUSHED if you want a flush with + * Set DRM_AND_FENCE_FLAG_FLUSH if you want a flush with * emission of the fence * - * For fence type we have the native DRM EXE type and the radeon RW - * type. + * For fence type we have the native DRM EXE type and the amd R & W type. */ -#define DRM_RADEON_FENCE_CLASS_ACCEL 0 -#define DRM_RADEON_FENCE_TYPE_RW 2 -#define DRM_RADEON_FENCE_FLAG_FLUSHED 0x01000000 +#define DRM_AMD_FENCE_CLASS_2D 0 +#define DRM_AMD_FENCE_TYPE_R (1 << 1) +#define DRM_AMD_FENCE_TYPE_W (1 << 2) +#define DRM_AMD_FENCE_FLAG_FLUSH 0x01000000 -/* radeon ms ioctl */ -#define DRM_RADEON_EXECBUFFER 0x00 -#define DRM_RADEON_RESETCP 0x01 +/* ioctl */ +#define DRM_AMD_CMD 0x00 +#define DRM_AMD_RESETCP 0x01 -struct drm_radeon_execbuffer_arg { - uint64_t next; - uint32_t reloc_offset; - union { - struct drm_bo_op_req req; - struct drm_bo_arg_rep rep; - } d; +/* cmd ioctl */ + +#define DRM_AMD_CMD_BO_TYPE_INVALID 0 +#define DRM_AMD_CMD_BO_TYPE_CMD_RING (1 << 0) +#define DRM_AMD_CMD_BO_TYPE_CMD_INDIRECT (1 << 1) +#define DRM_AMD_CMD_BO_TYPE_DATA (1 << 2) + +struct drm_amd_cmd_bo_offset +{ + uint64_t next; + uint64_t offset; + uint32_t cs_id; +}; + +struct drm_amd_cmd_bo +{ + uint32_t type; + uint64_t next; + uint64_t offset; + struct drm_bo_op_req op_req; + struct drm_bo_arg_rep op_rep; }; -struct drm_radeon_execbuffer { - uint32_t args_count; - uint64_t args; - uint32_t cmd_size; - struct drm_fence_arg fence_arg; +struct drm_amd_cmd +{ + uint32_t cdw_count; + uint32_t bo_count; + uint64_t bo; + struct drm_fence_arg fence_arg; }; #endif -- cgit v1.2.3