From 9fad101da95bfd37987b797020f71fe306c6f876 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 18 Feb 2006 03:04:30 +0000 Subject: add benh's memory management patch --- shared-core/radeon_drv.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'shared-core/radeon_drv.h') diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 786af0df..b751534f 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -90,10 +90,11 @@ * 1.20- Add support for r300 texrect * 1.21- Add support for card type getparam * 1.22- Add support for texture cache flushes (R300_TX_CNTL) + * 1.23- Add new radeon memory map work from benh */ #define DRIVER_MAJOR 1 -#define DRIVER_MINOR 22 +#define DRIVER_MINOR 23 #define DRIVER_PATCHLEVEL 0 enum radeon_family { @@ -135,7 +136,8 @@ enum radeon_chip_flags { CHIP_IS_PCIE = 0x00200000UL, }; -#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 ) +#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ + DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR)) #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) typedef struct drm_radeon_freelist { @@ -197,6 +199,8 @@ typedef struct drm_radeon_private { drm_radeon_sarea_t *sarea_priv; u32 fb_location; + u32 fb_size; + int new_memmap; int gart_size; u32 gart_vm_start; -- cgit v1.2.3